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Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_31 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_41 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_31( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_41 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSource_Phit_3 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, async : { mem : { phit : UInt<32>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} wire sink_ready : UInt<1> connect sink_ready, UInt<1>(0h1) reg mem : { phit : UInt<32>}[8], clock node _widx_T = asAsyncReset(reset) node _widx_T_1 = and(io.enq.ready, io.enq.valid) node _widx_T_2 = eq(sink_ready, UInt<1>(0h0)) wire widx_incremented : UInt<4> regreset widx_widx_bin : UInt, clock, _widx_T, UInt<1>(0h0) connect widx_widx_bin, widx_incremented node _widx_incremented_T = add(widx_widx_bin, _widx_T_1) node _widx_incremented_T_1 = tail(_widx_incremented_T, 1) node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>(0h0), _widx_incremented_T_1) connect widx_incremented, _widx_incremented_T_2 node _widx_T_3 = shr(widx_incremented, 1) node widx = xor(widx_incremented, _widx_T_3) inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_6 connect ridx_ridx_gray.clock, clock connect ridx_ridx_gray.reset, reset connect ridx_ridx_gray.io.d, io.async.ridx wire ridx : UInt<4> connect ridx, ridx_ridx_gray.io.q node _ready_T = xor(ridx, UInt<4>(0hc)) node _ready_T_1 = neq(widx, _ready_T) node ready = and(sink_ready, _ready_T_1) node _index_T = bits(io.async.widx, 2, 0) node _index_T_1 = bits(io.async.widx, 3, 3) node _index_T_2 = shl(_index_T_1, 2) node index = xor(_index_T, _index_T_2) node _T = and(io.enq.ready, io.enq.valid) when _T : connect mem[index], io.enq.bits node _ready_reg_T = asAsyncReset(reset) regreset ready_reg : UInt<1>, clock, _ready_reg_T, UInt<1>(0h0) connect ready_reg, ready node _io_enq_ready_T = and(ready_reg, sink_ready) connect io.enq.ready, _io_enq_ready_T node _widx_reg_T = asAsyncReset(reset) regreset widx_gray : UInt, clock, _widx_reg_T, UInt<1>(0h0) connect widx_gray, widx connect io.async.widx, widx_gray connect io.async.mem, mem inst source_valid_0 of AsyncValidSync_48 inst source_valid_1 of AsyncValidSync_49 inst sink_extend of AsyncValidSync_50 inst sink_valid of AsyncValidSync_51 node _source_valid_0_reset_T = asUInt(reset) node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1) node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2) connect source_valid_0.reset, _source_valid_0_reset_T_3 node _source_valid_1_reset_T = asUInt(reset) node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1) node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2) connect source_valid_1.reset, _source_valid_1_reset_T_3 node _sink_extend_reset_T = asUInt(reset) node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1) node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2) connect sink_extend.reset, _sink_extend_reset_T_3 node _sink_valid_reset_T = asAsyncReset(reset) connect sink_valid.reset, _sink_valid_reset_T connect source_valid_0.clock, clock connect source_valid_1.clock, clock connect sink_extend.clock, clock connect sink_valid.clock, clock connect source_valid_0.io.in, UInt<1>(0h1) connect source_valid_1.io.in, source_valid_0.io.out connect io.async.safe.widx_valid, source_valid_1.io.out connect sink_extend.io.in, io.async.safe.ridx_valid connect sink_valid.io.in, sink_extend.io.out connect sink_ready, sink_valid.io.out node _io_async_safe_source_reset_n_T = asUInt(reset) node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>(0h0)) connect io.async.safe.source_reset_n, _io_async_safe_source_reset_n_T_1	module AsyncQueueSource_Phit_3( // @[AsyncQueue.scala:70:7] input clock, // @[AsyncQueue.scala:70:7] input reset, // @[AsyncQueue.scala:70:7] output io_enq_ready, // @[AsyncQueue.scala:73:14] input io_enq_valid, // @[AsyncQueue.scala:73:14] input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:73:14] input [3:0] io_async_ridx, // @[AsyncQueue.scala:73:14] output [3:0] io_async_widx, // @[AsyncQueue.scala:73:14] input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14] input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14] ); wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30] wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32] wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7] wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7] wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7] wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7] wire _widx_T = reset; // @[AsyncQueue.scala:83:30] wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35] wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34] wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36] wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36] wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36] wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35] wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34] wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29] wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27] wire io_enq_ready_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_0_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_1_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_2_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_3_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_4_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_5_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_6_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_7_phit_0; // @[AsyncQueue.scala:70:7] wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7] wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_widx_0; // @[AsyncQueue.scala:70:7] wire sink_ready; // @[AsyncQueue.scala:81:28] reg [31:0] mem_0_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_phit_0 = mem_0_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_1_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_phit_0 = mem_1_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_2_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_phit_0 = mem_2_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_3_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_phit_0 = mem_3_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_4_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_phit_0 = mem_4_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_5_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_phit_0 = mem_5_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_6_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_phit_0 = mem_6_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_7_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_phit_0 = mem_7_phit; // @[AsyncQueue.scala:70:7, :82:16] wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77] wire [3:0] _widx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] widx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] widx_widx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77] assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _widx_T_3 = widx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] ridx; // @[ShiftReg.scala:48:24] wire [3:0] _ready_T = ridx ^ 4'hC; // @[ShiftReg.scala:48:24] wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}] wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}] wire [2:0] _index_T = io_async_widx_0[2:0]; // @[AsyncQueue.scala:70:7, :87:52] wire _index_T_1 = io_async_widx_0[3]; // @[AsyncQueue.scala:70:7, :87:80] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:87:{80,93}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:87:{52,64,93}] reg ready_reg; // @[AsyncQueue.scala:90:56] assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29] assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29] reg [3:0] widx_gray; // @[AsyncQueue.scala:93:55] assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55] wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46] wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T \| _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}] wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}] wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46] wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T \| _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}] wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}] wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46] wire _sink_extend_reset_T_2 = _sink_extend_reset_T \| _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}] wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}] assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}] assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27] always @(posedge clock) begin // @[AsyncQueue.scala:70:7] if (_widx_T_1 & index == 3'h0) // @[Decoupled.scala:51:35] mem_0_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h1) // @[Decoupled.scala:51:35] mem_1_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h2) // @[Decoupled.scala:51:35] mem_2_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h3) // @[Decoupled.scala:51:35] mem_3_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h4) // @[Decoupled.scala:51:35] mem_4_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h5) // @[Decoupled.scala:51:35] mem_5_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h6) // @[Decoupled.scala:51:35] mem_6_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & (&index)) // @[Decoupled.scala:51:35] mem_7_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] always @(posedge) always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30] if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30] widx_widx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:70:7] widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35] if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35] ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56] else // @[AsyncQueue.scala:70:7] ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56] always @(posedge, posedge) always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34] if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34] widx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :93:55] else // @[AsyncQueue.scala:70:7] widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_80 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[20] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[9]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[10]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[11]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[12]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[13]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[14]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[15]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[16]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[17]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[18]) node source_ok = or(_source_ok_T_57, _source_ok_WIRE[19]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = and(_T_11, _T_24) node _T_185 = and(_T_184, _T_37) node _T_186 = and(_T_185, _T_50) node _T_187 = and(_T_186, _T_63) node _T_188 = and(_T_187, _T_71) node _T_189 = and(_T_188, _T_79) node _T_190 = and(_T_189, _T_87) node _T_191 = and(_T_190, _T_95) node _T_192 = and(_T_191, _T_103) node _T_193 = and(_T_192, _T_111) node _T_194 = and(_T_193, _T_119) node _T_195 = and(_T_194, _T_127) node _T_196 = and(_T_195, _T_135) node _T_197 = and(_T_196, _T_143) node _T_198 = and(_T_197, _T_151) node _T_199 = and(_T_198, _T_159) node _T_200 = and(_T_199, _T_167) node _T_201 = and(_T_200, _T_175) node _T_202 = and(_T_201, _T_183) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_202, UInt<1>(0h1), "") : assert_1 node _T_206 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_206 : node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_211 = shr(io.in.a.bits.source, 2) node _T_212 = eq(_T_211, UInt<1>(0h0)) node _T_213 = leq(UInt<1>(0h0), uncommonBits_4) node _T_214 = and(_T_212, _T_213) node _T_215 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_217 = shr(io.in.a.bits.source, 2) node _T_218 = eq(_T_217, UInt<1>(0h1)) node _T_219 = leq(UInt<1>(0h0), uncommonBits_5) node _T_220 = and(_T_218, _T_219) node _T_221 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_222 = and(_T_220, _T_221) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_223 = shr(io.in.a.bits.source, 2) node _T_224 = eq(_T_223, UInt<2>(0h2)) node _T_225 = leq(UInt<1>(0h0), uncommonBits_6) node _T_226 = and(_T_224, _T_225) node _T_227 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_228 = and(_T_226, _T_227) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_229 = shr(io.in.a.bits.source, 2) node _T_230 = eq(_T_229, UInt<2>(0h3)) node _T_231 = leq(UInt<1>(0h0), uncommonBits_7) node _T_232 = and(_T_230, _T_231) node _T_233 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_236 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_237 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_238 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_241 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_249 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_250 = or(_T_210, _T_216) node _T_251 = or(_T_250, _T_222) node _T_252 = or(_T_251, _T_228) node _T_253 = or(_T_252, _T_234) node _T_254 = or(_T_253, _T_235) node _T_255 = or(_T_254, _T_236) node _T_256 = or(_T_255, _T_237) node _T_257 = or(_T_256, _T_238) node _T_258 = or(_T_257, _T_239) node _T_259 = or(_T_258, _T_240) node _T_260 = or(_T_259, _T_241) node _T_261 = or(_T_260, _T_242) node _T_262 = or(_T_261, _T_243) node _T_263 = or(_T_262, _T_244) node _T_264 = or(_T_263, _T_245) node _T_265 = or(_T_264, _T_246) node _T_266 = or(_T_265, _T_247) node _T_267 = or(_T_266, _T_248) node _T_268 = or(_T_267, _T_249) node _T_269 = and(_T_209, _T_268) node _T_270 = or(UInt<1>(0h0), _T_269) node _T_271 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_272 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_273 = cvt(_T_272) node _T_274 = and(_T_273, asSInt(UInt<13>(0h1000))) node _T_275 = asSInt(_T_274) node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = and(_T_271, _T_276) node _T_278 = or(UInt<1>(0h0), _T_277) node _T_279 = and(_T_270, _T_278) node _T_280 = asUInt(reset) node _T_281 = eq(_T_280, UInt<1>(0h0)) when _T_281 : node _T_282 = eq(_T_279, UInt<1>(0h0)) when _T_282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_279, UInt<1>(0h1), "") : assert_2 node _T_283 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<1>(0h0)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_8) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<1>(0h1)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_9) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_296 = shr(io.in.a.bits.source, 2) node _T_297 = eq(_T_296, UInt<2>(0h2)) node _T_298 = leq(UInt<1>(0h0), uncommonBits_10) node _T_299 = and(_T_297, _T_298) node _T_300 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_301 = and(_T_299, _T_300) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_302 = shr(io.in.a.bits.source, 2) node _T_303 = eq(_T_302, UInt<2>(0h3)) node _T_304 = leq(UInt<1>(0h0), uncommonBits_11) node _T_305 = and(_T_303, _T_304) node _T_306 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_309 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_310 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_311 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_314 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_315 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_316 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_317 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_318 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_321 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_322 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[20] connect _WIRE[0], _T_283 connect _WIRE[1], _T_289 connect _WIRE[2], _T_295 connect _WIRE[3], _T_301 connect _WIRE[4], _T_307 connect _WIRE[5], _T_308 connect _WIRE[6], _T_309 connect _WIRE[7], _T_310 connect _WIRE[8], _T_311 connect _WIRE[9], _T_312 connect _WIRE[10], _T_313 connect _WIRE[11], _T_314 connect _WIRE[12], _T_315 connect _WIRE[13], _T_316 connect _WIRE[14], _T_317 connect _WIRE[15], _T_318 connect _WIRE[16], _T_319 connect _WIRE[17], _T_320 connect _WIRE[18], _T_321 connect _WIRE[19], _T_322 node _T_323 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_324 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_325 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_326 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_327 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_328 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_329 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_331 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_332 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE[5], _T_323, UInt<1>(0h0)) node _T_335 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE[8], _T_324, UInt<1>(0h0)) node _T_338 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE[10], _T_325, UInt<1>(0h0)) node _T_340 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = mux(_WIRE[12], _T_326, UInt<1>(0h0)) node _T_342 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_343 = mux(_WIRE[14], _T_327, UInt<1>(0h0)) node _T_344 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_345 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_346 = mux(_WIRE[17], _T_328, UInt<1>(0h0)) node _T_347 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_348 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_349 = or(_T_329, _T_330) node _T_350 = or(_T_349, _T_331) node _T_351 = or(_T_350, _T_332) node _T_352 = or(_T_351, _T_333) node _T_353 = or(_T_352, _T_334) node _T_354 = or(_T_353, _T_335) node _T_355 = or(_T_354, _T_336) node _T_356 = or(_T_355, _T_337) node _T_357 = or(_T_356, _T_338) node _T_358 = or(_T_357, _T_339) node _T_359 = or(_T_358, _T_340) node _T_360 = or(_T_359, _T_341) node _T_361 = or(_T_360, _T_342) node _T_362 = or(_T_361, _T_343) node _T_363 = or(_T_362, _T_344) node _T_364 = or(_T_363, _T_345) node _T_365 = or(_T_364, _T_346) node _T_366 = or(_T_365, _T_347) node _T_367 = or(_T_366, _T_348) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_367 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = and(_T_371, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = and(_WIRE_1, _T_378) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_379, UInt<1>(0h1), "") : assert_3 node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(source_ok, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_386, UInt<1>(0h1), "") : assert_5 node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(is_aligned, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_393, UInt<1>(0h1), "") : assert_7 node _T_397 = not(io.in.a.bits.mask) node _T_398 = eq(_T_397, UInt<1>(0h0)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_398, UInt<1>(0h1), "") : assert_8 node _T_402 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_402, UInt<1>(0h1), "") : assert_9 node _T_406 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_406 : node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_408 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_411 = shr(io.in.a.bits.source, 2) node _T_412 = eq(_T_411, UInt<1>(0h0)) node _T_413 = leq(UInt<1>(0h0), uncommonBits_12) node _T_414 = and(_T_412, _T_413) node _T_415 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_416 = and(_T_414, _T_415) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_417 = shr(io.in.a.bits.source, 2) node _T_418 = eq(_T_417, UInt<1>(0h1)) node _T_419 = leq(UInt<1>(0h0), uncommonBits_13) node _T_420 = and(_T_418, _T_419) node _T_421 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_422 = and(_T_420, _T_421) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_423 = shr(io.in.a.bits.source, 2) node _T_424 = eq(_T_423, UInt<2>(0h2)) node _T_425 = leq(UInt<1>(0h0), uncommonBits_14) node _T_426 = and(_T_424, _T_425) node _T_427 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_428 = and(_T_426, _T_427) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_429 = shr(io.in.a.bits.source, 2) node _T_430 = eq(_T_429, UInt<2>(0h3)) node _T_431 = leq(UInt<1>(0h0), uncommonBits_15) node _T_432 = and(_T_430, _T_431) node _T_433 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_443 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_444 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_449 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_450 = or(_T_410, _T_416) node _T_451 = or(_T_450, _T_422) node _T_452 = or(_T_451, _T_428) node _T_453 = or(_T_452, _T_434) node _T_454 = or(_T_453, _T_435) node _T_455 = or(_T_454, _T_436) node _T_456 = or(_T_455, _T_437) node _T_457 = or(_T_456, _T_438) node _T_458 = or(_T_457, _T_439) node _T_459 = or(_T_458, _T_440) node _T_460 = or(_T_459, _T_441) node _T_461 = or(_T_460, _T_442) node _T_462 = or(_T_461, _T_443) node _T_463 = or(_T_462, _T_444) node _T_464 = or(_T_463, _T_445) node _T_465 = or(_T_464, _T_446) node _T_466 = or(_T_465, _T_447) node _T_467 = or(_T_466, _T_448) node _T_468 = or(_T_467, _T_449) node _T_469 = and(_T_409, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_472 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<13>(0h1000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = and(_T_471, _T_476) node _T_478 = or(UInt<1>(0h0), _T_477) node _T_479 = and(_T_470, _T_478) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_479, UInt<1>(0h1), "") : assert_10 node _T_483 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<1>(0h0)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_16) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<1>(0h1)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_17) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_496 = shr(io.in.a.bits.source, 2) node _T_497 = eq(_T_496, UInt<2>(0h2)) node _T_498 = leq(UInt<1>(0h0), uncommonBits_18) node _T_499 = and(_T_497, _T_498) node _T_500 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_501 = and(_T_499, _T_500) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_502 = shr(io.in.a.bits.source, 2) node _T_503 = eq(_T_502, UInt<2>(0h3)) node _T_504 = leq(UInt<1>(0h0), uncommonBits_19) node _T_505 = and(_T_503, _T_504) node _T_506 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_510 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_511 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_512 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_513 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_514 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_515 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_516 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_517 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_518 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_519 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_520 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_521 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_522 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[20] connect _WIRE_2[0], _T_483 connect _WIRE_2[1], _T_489 connect _WIRE_2[2], _T_495 connect _WIRE_2[3], _T_501 connect _WIRE_2[4], _T_507 connect _WIRE_2[5], _T_508 connect _WIRE_2[6], _T_509 connect _WIRE_2[7], _T_510 connect _WIRE_2[8], _T_511 connect _WIRE_2[9], _T_512 connect _WIRE_2[10], _T_513 connect _WIRE_2[11], _T_514 connect _WIRE_2[12], _T_515 connect _WIRE_2[13], _T_516 connect _WIRE_2[14], _T_517 connect _WIRE_2[15], _T_518 connect _WIRE_2[16], _T_519 connect _WIRE_2[17], _T_520 connect _WIRE_2[18], _T_521 connect _WIRE_2[19], _T_522 node _T_523 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_524 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_525 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_526 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_527 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_528 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_529 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_530 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_531 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_532 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_533 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_534 = mux(_WIRE_2[5], _T_523, UInt<1>(0h0)) node _T_535 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_536 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_537 = mux(_WIRE_2[8], _T_524, UInt<1>(0h0)) node _T_538 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_539 = mux(_WIRE_2[10], _T_525, UInt<1>(0h0)) node _T_540 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_541 = mux(_WIRE_2[12], _T_526, UInt<1>(0h0)) node _T_542 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_543 = mux(_WIRE_2[14], _T_527, UInt<1>(0h0)) node _T_544 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_545 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_546 = mux(_WIRE_2[17], _T_528, UInt<1>(0h0)) node _T_547 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_548 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_549 = or(_T_529, _T_530) node _T_550 = or(_T_549, _T_531) node _T_551 = or(_T_550, _T_532) node _T_552 = or(_T_551, _T_533) node _T_553 = or(_T_552, _T_534) node _T_554 = or(_T_553, _T_535) node _T_555 = or(_T_554, _T_536) node _T_556 = or(_T_555, _T_537) node _T_557 = or(_T_556, _T_538) node _T_558 = or(_T_557, _T_539) node _T_559 = or(_T_558, _T_540) node _T_560 = or(_T_559, _T_541) node _T_561 = or(_T_560, _T_542) node _T_562 = or(_T_561, _T_543) node _T_563 = or(_T_562, _T_544) node _T_564 = or(_T_563, _T_545) node _T_565 = or(_T_564, _T_546) node _T_566 = or(_T_565, _T_547) node _T_567 = or(_T_566, _T_548) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_567 node _T_568 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_569 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_570 = and(_T_568, _T_569) node _T_571 = or(UInt<1>(0h0), _T_570) node _T_572 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_573 = cvt(_T_572) node _T_574 = and(_T_573, asSInt(UInt<13>(0h1000))) node _T_575 = asSInt(_T_574) node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0))) node _T_577 = and(_T_571, _T_576) node _T_578 = or(UInt<1>(0h0), _T_577) node _T_579 = and(_WIRE_3, _T_578) node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(_T_579, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_579, UInt<1>(0h1), "") : assert_11 node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(source_ok, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_586 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_586, UInt<1>(0h1), "") : assert_13 node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(is_aligned, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_593 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(_T_593, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_593, UInt<1>(0h1), "") : assert_15 node _T_597 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_597, UInt<1>(0h1), "") : assert_16 node _T_601 = not(io.in.a.bits.mask) node _T_602 = eq(_T_601, UInt<1>(0h0)) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_602, UInt<1>(0h1), "") : assert_17 node _T_606 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_607 = asUInt(reset) node _T_608 = eq(_T_607, UInt<1>(0h0)) when _T_608 : node _T_609 = eq(_T_606, UInt<1>(0h0)) when _T_609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_606, UInt<1>(0h1), "") : assert_18 node _T_610 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_610 : node _T_611 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_612 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_613 = and(_T_611, _T_612) node _T_614 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_615 = shr(io.in.a.bits.source, 2) node _T_616 = eq(_T_615, UInt<1>(0h0)) node _T_617 = leq(UInt<1>(0h0), uncommonBits_20) node _T_618 = and(_T_616, _T_617) node _T_619 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_620 = and(_T_618, _T_619) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_621 = shr(io.in.a.bits.source, 2) node _T_622 = eq(_T_621, UInt<1>(0h1)) node _T_623 = leq(UInt<1>(0h0), uncommonBits_21) node _T_624 = and(_T_622, _T_623) node _T_625 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_626 = and(_T_624, _T_625) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_627 = shr(io.in.a.bits.source, 2) node _T_628 = eq(_T_627, UInt<2>(0h2)) node _T_629 = leq(UInt<1>(0h0), uncommonBits_22) node _T_630 = and(_T_628, _T_629) node _T_631 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_632 = and(_T_630, _T_631) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_633 = shr(io.in.a.bits.source, 2) node _T_634 = eq(_T_633, UInt<2>(0h3)) node _T_635 = leq(UInt<1>(0h0), uncommonBits_23) node _T_636 = and(_T_634, _T_635) node _T_637 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_638 = and(_T_636, _T_637) node _T_639 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_640 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_641 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_642 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_643 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_647 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_648 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_649 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_651 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_652 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_653 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_654 = or(_T_614, _T_620) node _T_655 = or(_T_654, _T_626) node _T_656 = or(_T_655, _T_632) node _T_657 = or(_T_656, _T_638) node _T_658 = or(_T_657, _T_639) node _T_659 = or(_T_658, _T_640) node _T_660 = or(_T_659, _T_641) node _T_661 = or(_T_660, _T_642) node _T_662 = or(_T_661, _T_643) node _T_663 = or(_T_662, _T_644) node _T_664 = or(_T_663, _T_645) node _T_665 = or(_T_664, _T_646) node _T_666 = or(_T_665, _T_647) node _T_667 = or(_T_666, _T_648) node _T_668 = or(_T_667, _T_649) node _T_669 = or(_T_668, _T_650) node _T_670 = or(_T_669, _T_651) node _T_671 = or(_T_670, _T_652) node _T_672 = or(_T_671, _T_653) node _T_673 = and(_T_613, _T_672) node _T_674 = or(UInt<1>(0h0), _T_673) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_674, UInt<1>(0h1), "") : assert_19 node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_679 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_680 = and(_T_678, _T_679) node _T_681 = or(UInt<1>(0h0), _T_680) node _T_682 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_683 = cvt(_T_682) node _T_684 = and(_T_683, asSInt(UInt<13>(0h1000))) node _T_685 = asSInt(_T_684) node _T_686 = eq(_T_685, asSInt(UInt<1>(0h0))) node _T_687 = and(_T_681, _T_686) node _T_688 = or(UInt<1>(0h0), _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_688, UInt<1>(0h1), "") : assert_20 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(source_ok, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(is_aligned, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_698, UInt<1>(0h1), "") : assert_23 node _T_702 = eq(io.in.a.bits.mask, mask) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_702, UInt<1>(0h1), "") : assert_24 node _T_706 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(_T_706, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_706, UInt<1>(0h1), "") : assert_25 node _T_710 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_710 : node _T_711 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_712 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_713 = and(_T_711, _T_712) node _T_714 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_715 = shr(io.in.a.bits.source, 2) node _T_716 = eq(_T_715, UInt<1>(0h0)) node _T_717 = leq(UInt<1>(0h0), uncommonBits_24) node _T_718 = and(_T_716, _T_717) node _T_719 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_720 = and(_T_718, _T_719) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_721 = shr(io.in.a.bits.source, 2) node _T_722 = eq(_T_721, UInt<1>(0h1)) node _T_723 = leq(UInt<1>(0h0), uncommonBits_25) node _T_724 = and(_T_722, _T_723) node _T_725 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_726 = and(_T_724, _T_725) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_727 = shr(io.in.a.bits.source, 2) node _T_728 = eq(_T_727, UInt<2>(0h2)) node _T_729 = leq(UInt<1>(0h0), uncommonBits_26) node _T_730 = and(_T_728, _T_729) node _T_731 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_732 = and(_T_730, _T_731) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_733 = shr(io.in.a.bits.source, 2) node _T_734 = eq(_T_733, UInt<2>(0h3)) node _T_735 = leq(UInt<1>(0h0), uncommonBits_27) node _T_736 = and(_T_734, _T_735) node _T_737 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_738 = and(_T_736, _T_737) node _T_739 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_740 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_741 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_742 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_743 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_744 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_745 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_746 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_747 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_748 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_749 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_750 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_751 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_752 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_754 = or(_T_714, _T_720) node _T_755 = or(_T_754, _T_726) node _T_756 = or(_T_755, _T_732) node _T_757 = or(_T_756, _T_738) node _T_758 = or(_T_757, _T_739) node _T_759 = or(_T_758, _T_740) node _T_760 = or(_T_759, _T_741) node _T_761 = or(_T_760, _T_742) node _T_762 = or(_T_761, _T_743) node _T_763 = or(_T_762, _T_744) node _T_764 = or(_T_763, _T_745) node _T_765 = or(_T_764, _T_746) node _T_766 = or(_T_765, _T_747) node _T_767 = or(_T_766, _T_748) node _T_768 = or(_T_767, _T_749) node _T_769 = or(_T_768, _T_750) node _T_770 = or(_T_769, _T_751) node _T_771 = or(_T_770, _T_752) node _T_772 = or(_T_771, _T_753) node _T_773 = and(_T_713, _T_772) node _T_774 = or(UInt<1>(0h0), _T_773) node _T_775 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_776 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_777 = and(_T_775, _T_776) node _T_778 = or(UInt<1>(0h0), _T_777) node _T_779 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_780 = cvt(_T_779) node _T_781 = and(_T_780, asSInt(UInt<13>(0h1000))) node _T_782 = asSInt(_T_781) node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0))) node _T_784 = and(_T_778, _T_783) node _T_785 = or(UInt<1>(0h0), _T_784) node _T_786 = and(_T_774, _T_785) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_786, UInt<1>(0h1), "") : assert_26 node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(source_ok, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(is_aligned, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_796 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_796, UInt<1>(0h1), "") : assert_29 node _T_800 = eq(io.in.a.bits.mask, mask) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_800, UInt<1>(0h1), "") : assert_30 node _T_804 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<1>(0h0)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_28) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_815 = shr(io.in.a.bits.source, 2) node _T_816 = eq(_T_815, UInt<1>(0h1)) node _T_817 = leq(UInt<1>(0h0), uncommonBits_29) node _T_818 = and(_T_816, _T_817) node _T_819 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_820 = and(_T_818, _T_819) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_821 = shr(io.in.a.bits.source, 2) node _T_822 = eq(_T_821, UInt<2>(0h2)) node _T_823 = leq(UInt<1>(0h0), uncommonBits_30) node _T_824 = and(_T_822, _T_823) node _T_825 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_826 = and(_T_824, _T_825) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_827 = shr(io.in.a.bits.source, 2) node _T_828 = eq(_T_827, UInt<2>(0h3)) node _T_829 = leq(UInt<1>(0h0), uncommonBits_31) node _T_830 = and(_T_828, _T_829) node _T_831 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_832 = and(_T_830, _T_831) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_847 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_848 = or(_T_808, _T_814) node _T_849 = or(_T_848, _T_820) node _T_850 = or(_T_849, _T_826) node _T_851 = or(_T_850, _T_832) node _T_852 = or(_T_851, _T_833) node _T_853 = or(_T_852, _T_834) node _T_854 = or(_T_853, _T_835) node _T_855 = or(_T_854, _T_836) node _T_856 = or(_T_855, _T_837) node _T_857 = or(_T_856, _T_838) node _T_858 = or(_T_857, _T_839) node _T_859 = or(_T_858, _T_840) node _T_860 = or(_T_859, _T_841) node _T_861 = or(_T_860, _T_842) node _T_862 = or(_T_861, _T_843) node _T_863 = or(_T_862, _T_844) node _T_864 = or(_T_863, _T_845) node _T_865 = or(_T_864, _T_846) node _T_866 = or(_T_865, _T_847) node _T_867 = and(_T_807, _T_866) node _T_868 = or(UInt<1>(0h0), _T_867) node _T_869 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_870 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_871 = and(_T_869, _T_870) node _T_872 = or(UInt<1>(0h0), _T_871) node _T_873 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<13>(0h1000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = and(_T_872, _T_877) node _T_879 = or(UInt<1>(0h0), _T_878) node _T_880 = and(_T_868, _T_879) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_880, UInt<1>(0h1), "") : assert_31 node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(source_ok, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(is_aligned, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_890 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_890, UInt<1>(0h1), "") : assert_34 node _T_894 = not(mask) node _T_895 = and(io.in.a.bits.mask, _T_894) node _T_896 = eq(_T_895, UInt<1>(0h0)) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_896, UInt<1>(0h1), "") : assert_35 node _T_900 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_905 = shr(io.in.a.bits.source, 2) node _T_906 = eq(_T_905, UInt<1>(0h0)) node _T_907 = leq(UInt<1>(0h0), uncommonBits_32) node _T_908 = and(_T_906, _T_907) node _T_909 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_910 = and(_T_908, _T_909) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_911 = shr(io.in.a.bits.source, 2) node _T_912 = eq(_T_911, UInt<1>(0h1)) node _T_913 = leq(UInt<1>(0h0), uncommonBits_33) node _T_914 = and(_T_912, _T_913) node _T_915 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_916 = and(_T_914, _T_915) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_917 = shr(io.in.a.bits.source, 2) node _T_918 = eq(_T_917, UInt<2>(0h2)) node _T_919 = leq(UInt<1>(0h0), uncommonBits_34) node _T_920 = and(_T_918, _T_919) node _T_921 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_922 = and(_T_920, _T_921) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_923 = shr(io.in.a.bits.source, 2) node _T_924 = eq(_T_923, UInt<2>(0h3)) node _T_925 = leq(UInt<1>(0h0), uncommonBits_35) node _T_926 = and(_T_924, _T_925) node _T_927 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_928 = and(_T_926, _T_927) node _T_929 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_930 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_931 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_932 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_933 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_934 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_935 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_936 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_937 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_938 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_939 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_940 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_941 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_942 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_943 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_944 = or(_T_904, _T_910) node _T_945 = or(_T_944, _T_916) node _T_946 = or(_T_945, _T_922) node _T_947 = or(_T_946, _T_928) node _T_948 = or(_T_947, _T_929) node _T_949 = or(_T_948, _T_930) node _T_950 = or(_T_949, _T_931) node _T_951 = or(_T_950, _T_932) node _T_952 = or(_T_951, _T_933) node _T_953 = or(_T_952, _T_934) node _T_954 = or(_T_953, _T_935) node _T_955 = or(_T_954, _T_936) node _T_956 = or(_T_955, _T_937) node _T_957 = or(_T_956, _T_938) node _T_958 = or(_T_957, _T_939) node _T_959 = or(_T_958, _T_940) node _T_960 = or(_T_959, _T_941) node _T_961 = or(_T_960, _T_942) node _T_962 = or(_T_961, _T_943) node _T_963 = and(_T_903, _T_962) node _T_964 = or(UInt<1>(0h0), _T_963) node _T_965 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_966 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_967 = cvt(_T_966) node _T_968 = and(_T_967, asSInt(UInt<13>(0h1000))) node _T_969 = asSInt(_T_968) node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0))) node _T_971 = and(_T_965, _T_970) node _T_972 = or(UInt<1>(0h0), _T_971) node _T_973 = and(_T_964, _T_972) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_973, UInt<1>(0h1), "") : assert_36 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(source_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(is_aligned, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_983 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_983, UInt<1>(0h1), "") : assert_39 node _T_987 = eq(io.in.a.bits.mask, mask) node _T_988 = asUInt(reset) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(_T_987, UInt<1>(0h0)) when _T_990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_987, UInt<1>(0h1), "") : assert_40 node _T_991 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_991 : node _T_992 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_993 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_994 = and(_T_992, _T_993) node _T_995 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_996 = shr(io.in.a.bits.source, 2) node _T_997 = eq(_T_996, UInt<1>(0h0)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_36) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1001 = and(_T_999, _T_1000) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1002 = shr(io.in.a.bits.source, 2) node _T_1003 = eq(_T_1002, UInt<1>(0h1)) node _T_1004 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1007 = and(_T_1005, _T_1006) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1008 = shr(io.in.a.bits.source, 2) node _T_1009 = eq(_T_1008, UInt<2>(0h2)) node _T_1010 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1013 = and(_T_1011, _T_1012) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1014 = shr(io.in.a.bits.source, 2) node _T_1015 = eq(_T_1014, UInt<2>(0h3)) node _T_1016 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1017 = and(_T_1015, _T_1016) node _T_1018 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1019 = and(_T_1017, _T_1018) node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1022 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1023 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_1025 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1026 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1027 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1028 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_1029 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1030 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1031 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1032 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1033 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1034 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1035 = or(_T_995, _T_1001) node _T_1036 = or(_T_1035, _T_1007) node _T_1037 = or(_T_1036, _T_1013) node _T_1038 = or(_T_1037, _T_1019) node _T_1039 = or(_T_1038, _T_1020) node _T_1040 = or(_T_1039, _T_1021) node _T_1041 = or(_T_1040, _T_1022) node _T_1042 = or(_T_1041, _T_1023) node _T_1043 = or(_T_1042, _T_1024) node _T_1044 = or(_T_1043, _T_1025) node _T_1045 = or(_T_1044, _T_1026) node _T_1046 = or(_T_1045, _T_1027) node _T_1047 = or(_T_1046, _T_1028) node _T_1048 = or(_T_1047, _T_1029) node _T_1049 = or(_T_1048, _T_1030) node _T_1050 = or(_T_1049, _T_1031) node _T_1051 = or(_T_1050, _T_1032) node _T_1052 = or(_T_1051, _T_1033) node _T_1053 = or(_T_1052, _T_1034) node _T_1054 = and(_T_994, _T_1053) node _T_1055 = or(UInt<1>(0h0), _T_1054) node _T_1056 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1057 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1058 = cvt(_T_1057) node _T_1059 = and(_T_1058, asSInt(UInt<13>(0h1000))) node _T_1060 = asSInt(_T_1059) node _T_1061 = eq(_T_1060, asSInt(UInt<1>(0h0))) node _T_1062 = and(_T_1056, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = and(_T_1055, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_41 node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(source_ok, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(is_aligned, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1074 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_44 node _T_1078 = eq(io.in.a.bits.mask, mask) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_45 node _T_1082 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1082 : node _T_1083 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1084 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1085 = and(_T_1083, _T_1084) node _T_1086 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1087 = shr(io.in.a.bits.source, 2) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) node _T_1089 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1092 = and(_T_1090, _T_1091) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1093 = shr(io.in.a.bits.source, 2) node _T_1094 = eq(_T_1093, UInt<1>(0h1)) node _T_1095 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1098 = and(_T_1096, _T_1097) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1099 = shr(io.in.a.bits.source, 2) node _T_1100 = eq(_T_1099, UInt<2>(0h2)) node _T_1101 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1104 = and(_T_1102, _T_1103) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1105 = shr(io.in.a.bits.source, 2) node _T_1106 = eq(_T_1105, UInt<2>(0h3)) node _T_1107 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_1120 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1121 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1122 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1123 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1124 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1125 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1126 = or(_T_1086, _T_1092) node _T_1127 = or(_T_1126, _T_1098) node _T_1128 = or(_T_1127, _T_1104) node _T_1129 = or(_T_1128, _T_1110) node _T_1130 = or(_T_1129, _T_1111) node _T_1131 = or(_T_1130, _T_1112) node _T_1132 = or(_T_1131, _T_1113) node _T_1133 = or(_T_1132, _T_1114) node _T_1134 = or(_T_1133, _T_1115) node _T_1135 = or(_T_1134, _T_1116) node _T_1136 = or(_T_1135, _T_1117) node _T_1137 = or(_T_1136, _T_1118) node _T_1138 = or(_T_1137, _T_1119) node _T_1139 = or(_T_1138, _T_1120) node _T_1140 = or(_T_1139, _T_1121) node _T_1141 = or(_T_1140, _T_1122) node _T_1142 = or(_T_1141, _T_1123) node _T_1143 = or(_T_1142, _T_1124) node _T_1144 = or(_T_1143, _T_1125) node _T_1145 = and(_T_1085, _T_1144) node _T_1146 = or(UInt<1>(0h0), _T_1145) node _T_1147 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1148 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1149 = cvt(_T_1148) node _T_1150 = and(_T_1149, asSInt(UInt<13>(0h1000))) node _T_1151 = asSInt(_T_1150) node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0))) node _T_1153 = and(_T_1147, _T_1152) node _T_1154 = or(UInt<1>(0h0), _T_1153) node _T_1155 = and(_T_1146, _T_1154) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_46 node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(source_ok, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(is_aligned, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1165 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_49 node _T_1169 = eq(io.in.a.bits.mask, mask) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_50 node _T_1173 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1177 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_52 node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_59 = shr(io.in.d.bits.source, 2) node _source_ok_T_60 = eq(_source_ok_T_59, UInt<1>(0h0)) node _source_ok_T_61 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_T_63 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_65 = shr(io.in.d.bits.source, 2) node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h1)) node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_T_69 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_71 = shr(io.in.d.bits.source, 2) node _source_ok_T_72 = eq(_source_ok_T_71, UInt<2>(0h2)) node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 2) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h3)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h2f)) node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<6>(0h2b)) node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_95 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_96 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_97 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[20] connect _source_ok_WIRE_1[0], _source_ok_T_58 connect _source_ok_WIRE_1[1], _source_ok_T_64 connect _source_ok_WIRE_1[2], _source_ok_T_70 connect _source_ok_WIRE_1[3], _source_ok_T_76 connect _source_ok_WIRE_1[4], _source_ok_T_82 connect _source_ok_WIRE_1[5], _source_ok_T_83 connect _source_ok_WIRE_1[6], _source_ok_T_84 connect _source_ok_WIRE_1[7], _source_ok_T_85 connect _source_ok_WIRE_1[8], _source_ok_T_86 connect _source_ok_WIRE_1[9], _source_ok_T_87 connect _source_ok_WIRE_1[10], _source_ok_T_88 connect _source_ok_WIRE_1[11], _source_ok_T_89 connect _source_ok_WIRE_1[12], _source_ok_T_90 connect _source_ok_WIRE_1[13], _source_ok_T_91 connect _source_ok_WIRE_1[14], _source_ok_T_92 connect _source_ok_WIRE_1[15], _source_ok_T_93 connect _source_ok_WIRE_1[16], _source_ok_T_94 connect _source_ok_WIRE_1[17], _source_ok_T_95 connect _source_ok_WIRE_1[18], _source_ok_T_96 connect _source_ok_WIRE_1[19], _source_ok_T_97 node _source_ok_T_98 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[2]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[3]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[4]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[5]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[6]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[7]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[8]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[9]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[10]) node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[11]) node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[12]) node _source_ok_T_110 = or(_source_ok_T_109, _source_ok_WIRE_1[13]) node _source_ok_T_111 = or(_source_ok_T_110, _source_ok_WIRE_1[14]) node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_1[15]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[16]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[17]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[18]) node source_ok_1 = or(_source_ok_T_115, _source_ok_WIRE_1[19]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1181 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1181 : node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(source_ok_1, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1185 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_54 node _T_1189 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_55 node _T_1193 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_56 node _T_1197 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(_T_1197, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1197, UInt<1>(0h1), "") : assert_57 node _T_1201 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1201 : node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(source_ok_1, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(sink_ok, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1208 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_60 node _T_1212 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_61 node _T_1216 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_62 node _T_1220 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_63 node _T_1224 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1225 = or(UInt<1>(0h0), _T_1224) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_64 node _T_1229 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1229 : node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(source_ok_1, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(sink_ok, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1236 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_67 node _T_1240 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_68 node _T_1244 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_69 node _T_1248 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1249 = or(_T_1248, io.in.d.bits.corrupt) node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(_T_1249, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1249, UInt<1>(0h1), "") : assert_70 node _T_1253 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1254 = or(UInt<1>(0h0), _T_1253) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_71 node _T_1258 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1258 : node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(source_ok_1, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1262 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_73 node _T_1266 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(_T_1266, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1266, UInt<1>(0h1), "") : assert_74 node _T_1270 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1271 = or(UInt<1>(0h0), _T_1270) node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(_T_1271, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1271, UInt<1>(0h1), "") : assert_75 node _T_1275 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1275 : node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(source_ok_1, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1279 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_77 node _T_1283 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1284 = or(_T_1283, io.in.d.bits.corrupt) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_78 node _T_1288 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1289 = or(UInt<1>(0h0), _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_79 node _T_1293 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1293 : node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(source_ok_1, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1297 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_81 node _T_1301 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(_T_1301, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1301, UInt<1>(0h1), "") : assert_82 node _T_1305 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1306 = or(UInt<1>(0h0), _T_1305) node _T_1307 = asUInt(reset) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) when _T_1308 : node _T_1309 = eq(_T_1306, UInt<1>(0h0)) when _T_1309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1306, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1310 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1314 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1318 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1322 = eq(a_first, UInt<1>(0h0)) node _T_1323 = and(io.in.a.valid, _T_1322) when _T_1323 : node _T_1324 = eq(io.in.a.bits.opcode, opcode) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_87 node _T_1328 = eq(io.in.a.bits.param, param) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_88 node _T_1332 = eq(io.in.a.bits.size, size) node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(_T_1332, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1332, UInt<1>(0h1), "") : assert_89 node _T_1336 = eq(io.in.a.bits.source, source) node _T_1337 = asUInt(reset) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) when _T_1338 : node _T_1339 = eq(_T_1336, UInt<1>(0h0)) when _T_1339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1336, UInt<1>(0h1), "") : assert_90 node _T_1340 = eq(io.in.a.bits.address, address) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_91 node _T_1344 = and(io.in.a.ready, io.in.a.valid) node _T_1345 = and(_T_1344, a_first) when _T_1345 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1346 = eq(d_first, UInt<1>(0h0)) node _T_1347 = and(io.in.d.valid, _T_1346) when _T_1347 : node _T_1348 = eq(io.in.d.bits.opcode, opcode_1) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_92 node _T_1352 = eq(io.in.d.bits.param, param_1) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_93 node _T_1356 = eq(io.in.d.bits.size, size_1) node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(_T_1356, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1356, UInt<1>(0h1), "") : assert_94 node _T_1360 = eq(io.in.d.bits.source, source_1) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_95 node _T_1364 = eq(io.in.d.bits.sink, sink) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_96 node _T_1368 = eq(io.in.d.bits.denied, denied) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_97 node _T_1372 = and(io.in.d.ready, io.in.d.valid) node _T_1373 = and(_T_1372, d_first) when _T_1373 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1374 = and(io.in.a.valid, a_first_1) node _T_1375 = and(_T_1374, UInt<1>(0h1)) when _T_1375 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1376 = and(io.in.a.ready, io.in.a.valid) node _T_1377 = and(_T_1376, a_first_1) node _T_1378 = and(_T_1377, UInt<1>(0h1)) when _T_1378 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1379 = dshr(inflight, io.in.a.bits.source) node _T_1380 = bits(_T_1379, 0, 0) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(_T_1381, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1381, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1385 = and(io.in.d.valid, d_first_1) node _T_1386 = and(_T_1385, UInt<1>(0h1)) node _T_1387 = eq(d_release_ack, UInt<1>(0h0)) node _T_1388 = and(_T_1386, _T_1387) when _T_1388 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1389 = and(io.in.d.ready, io.in.d.valid) node _T_1390 = and(_T_1389, d_first_1) node _T_1391 = and(_T_1390, UInt<1>(0h1)) node _T_1392 = eq(d_release_ack, UInt<1>(0h0)) node _T_1393 = and(_T_1391, _T_1392) when _T_1393 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1394 = and(io.in.d.valid, d_first_1) node _T_1395 = and(_T_1394, UInt<1>(0h1)) node _T_1396 = eq(d_release_ack, UInt<1>(0h0)) node _T_1397 = and(_T_1395, _T_1396) when _T_1397 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1398 = dshr(inflight, io.in.d.bits.source) node _T_1399 = bits(_T_1398, 0, 0) node _T_1400 = or(_T_1399, same_cycle_resp) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1404 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1405 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1406 = or(_T_1404, _T_1405) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_100 node _T_1410 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_101 else : node _T_1414 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1415 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1416 = or(_T_1414, _T_1415) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_102 node _T_1420 = eq(io.in.d.bits.size, a_size_lookup) node _T_1421 = asUInt(reset) node _T_1422 = eq(_T_1421, UInt<1>(0h0)) when _T_1422 : node _T_1423 = eq(_T_1420, UInt<1>(0h0)) when _T_1423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1420, UInt<1>(0h1), "") : assert_103 node _T_1424 = and(io.in.d.valid, d_first_1) node _T_1425 = and(_T_1424, a_first_1) node _T_1426 = and(_T_1425, io.in.a.valid) node _T_1427 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1428 = and(_T_1426, _T_1427) node _T_1429 = eq(d_release_ack, UInt<1>(0h0)) node _T_1430 = and(_T_1428, _T_1429) when _T_1430 : node _T_1431 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1432 = or(_T_1431, io.in.a.ready) node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(_T_1432, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1432, UInt<1>(0h1), "") : assert_104 node _T_1436 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1437 = orr(a_set_wo_ready) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) node _T_1439 = or(_T_1436, _T_1438) node _T_1440 = asUInt(reset) node _T_1441 = eq(_T_1440, UInt<1>(0h0)) when _T_1441 : node _T_1442 = eq(_T_1439, UInt<1>(0h0)) when _T_1442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1439, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_163 node _T_1443 = orr(inflight) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) node _T_1445 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1446 = or(_T_1444, _T_1445) node _T_1447 = lt(watchdog, plusarg_reader.out) node _T_1448 = or(_T_1446, _T_1447) node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(_T_1448, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1448, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1452 = and(io.in.a.ready, io.in.a.valid) node _T_1453 = and(io.in.d.ready, io.in.d.valid) node _T_1454 = or(_T_1452, _T_1453) when _T_1454 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1455 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1456 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1457 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1458 = and(_T_1456, _T_1457) node _T_1459 = and(_T_1455, _T_1458) when _T_1459 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1460 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1461 = and(_T_1460, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1462 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1463 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1464 = and(_T_1462, _T_1463) node _T_1465 = and(_T_1461, _T_1464) when _T_1465 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1466 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1467 = bits(_T_1466, 0, 0) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1472 = and(io.in.d.valid, d_first_2) node _T_1473 = and(_T_1472, UInt<1>(0h1)) node _T_1474 = and(_T_1473, d_release_ack_1) when _T_1474 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1475 = and(io.in.d.ready, io.in.d.valid) node _T_1476 = and(_T_1475, d_first_2) node _T_1477 = and(_T_1476, UInt<1>(0h1)) node _T_1478 = and(_T_1477, d_release_ack_1) when _T_1478 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1479 = and(io.in.d.valid, d_first_2) node _T_1480 = and(_T_1479, UInt<1>(0h1)) node _T_1481 = and(_T_1480, d_release_ack_1) when _T_1481 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1482 = dshr(inflight_1, io.in.d.bits.source) node _T_1483 = bits(_T_1482, 0, 0) node _T_1484 = or(_T_1483, same_cycle_resp_1) node _T_1485 = asUInt(reset) node _T_1486 = eq(_T_1485, UInt<1>(0h0)) when _T_1486 : node _T_1487 = eq(_T_1484, UInt<1>(0h0)) when _T_1487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1484, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1488 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1489 = asUInt(reset) node _T_1490 = eq(_T_1489, UInt<1>(0h0)) when _T_1490 : node _T_1491 = eq(_T_1488, UInt<1>(0h0)) when _T_1491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1488, UInt<1>(0h1), "") : assert_109 else : node _T_1492 = eq(io.in.d.bits.size, c_size_lookup) node _T_1493 = asUInt(reset) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) when _T_1494 : node _T_1495 = eq(_T_1492, UInt<1>(0h0)) when _T_1495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1492, UInt<1>(0h1), "") : assert_110 node _T_1496 = and(io.in.d.valid, d_first_2) node _T_1497 = and(_T_1496, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1498 = and(_T_1497, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1499 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1500 = and(_T_1498, _T_1499) node _T_1501 = and(_T_1500, d_release_ack_1) node _T_1502 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1503 = and(_T_1501, _T_1502) when _T_1503 : node _T_1504 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1505 = or(_T_1504, _WIRE_27.ready) node _T_1506 = asUInt(reset) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) when _T_1507 : node _T_1508 = eq(_T_1505, UInt<1>(0h0)) when _T_1508 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1505, UInt<1>(0h1), "") : assert_111 node _T_1509 = orr(c_set_wo_ready) when _T_1509 : node _T_1510 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_164 node _T_1514 = orr(inflight_1) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) node _T_1516 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1517 = or(_T_1515, _T_1516) node _T_1518 = lt(watchdog_1, plusarg_reader_1.out) node _T_1519 = or(_T_1517, _T_1518) node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(_T_1519, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rerocc/src/main/scala/Integration.scala:57:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1519, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1523 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1524 = and(io.in.d.ready, io.in.d.valid) node _T_1525 = or(_T_1523, _T_1524) when _T_1525 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_80( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 \| _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 \| _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 \| _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 \| _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_57 \| _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_60 = _source_ok_T_59 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_66 = _source_ok_T_65 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_83; // @[Parameters.scala:1138:31] wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire _source_ok_T_85 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire _source_ok_T_86 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31] wire _source_ok_T_87 = io_in_d_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire _source_ok_T_88 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire _source_ok_T_95 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_95; // @[Parameters.scala:1138:31] wire _source_ok_T_96 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire _source_ok_T_97 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_108 = _source_ok_T_107 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_109 = _source_ok_T_108 \| _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_110 = _source_ok_T_109 \| _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_111 = _source_ok_T_110 \| _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_112 = _source_ok_T_111 \| _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 \| _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 \| _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 \| _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_115 \| _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _T_1452 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1452; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1452; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1525 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1525; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1525; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1525; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1378 = _T_1452 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1378 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1378 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1378 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1378 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1378 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1424 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1424 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1393 = _T_1525 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1393 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1393 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1393 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1496 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1496 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1478 = _T_1525 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1478 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1478 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1478 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_50 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_50( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_62 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_3 : input clock : Clock input reset : Reset output io : { flip inR : { bits : UInt<32>}, flip inD : { bits : UInt<32>}, outL : { bits : UInt<32>}, outU : { bits : UInt<32>}, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : { bits : UInt<32>}, clock when io.en : connect reg.bits, _reg_T_1.bits connect io.outU, reg connect io.outL, reg	module PE_3( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [31:0] io_inR_bits, // @[Transposer.scala:101:16] input [31:0] io_inD_bits, // @[Transposer.scala:101:16] output [31:0] io_outL_bits, // @[Transposer.scala:101:16] output [31:0] io_outU_bits, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [31:0] io_inR_bits_0 = io_inR_bits; // @[Transposer.scala:100:9] wire [31:0] io_inD_bits_0 = io_inD_bits; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [31:0] io_outL_bits_0; // @[Transposer.scala:100:9] wire [31:0] io_outU_bits_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [31:0] _reg_T_1_bits = _reg_T ? io_inR_bits_0 : io_inD_bits_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [31:0] reg_bits; // @[Transposer.scala:110:24] assign io_outL_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] assign io_outU_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_bits <= _reg_T_1_bits; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL_bits = io_outL_bits_0; // @[Transposer.scala:100:9] assign io_outU_bits = io_outU_bits_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_3 : input clock : Clock input reset : Reset output auto : { } skip	module TLFragmenter_3( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset // @[Fragmenter.scala:92:9] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_205 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_205( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_15 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_15( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_324 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_324( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_59 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_59 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_59( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_59 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLFIFOFixer_3 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_32 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in node _a_notFIFO_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) node _a_notFIFO_T_1 = cvt(_a_notFIFO_T) node _a_notFIFO_T_2 = and(_a_notFIFO_T_1, asSInt(UInt<1>(0h0))) node _a_notFIFO_T_3 = asSInt(_a_notFIFO_T_2) node _a_notFIFO_T_4 = eq(_a_notFIFO_T_3, asSInt(UInt<1>(0h0))) node _a_id_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) node _a_id_T_1 = cvt(_a_id_T) node _a_id_T_2 = and(_a_id_T_1, asSInt(UInt<18>(0h10000))) node _a_id_T_3 = asSInt(_a_id_T_2) node _a_id_T_4 = eq(_a_id_T_3, asSInt(UInt<1>(0h0))) node _a_id_T_5 = xor(anonIn.a.bits.address, UInt<17>(0h10000)) node _a_id_T_6 = cvt(_a_id_T_5) node _a_id_T_7 = and(_a_id_T_6, asSInt(UInt<18>(0h10000))) node _a_id_T_8 = asSInt(_a_id_T_7) node _a_id_T_9 = eq(_a_id_T_8, asSInt(UInt<1>(0h0))) node _a_id_T_10 = mux(_a_id_T_4, UInt<1>(0h1), UInt<1>(0h0)) node _a_id_T_11 = mux(_a_id_T_9, UInt<2>(0h2), UInt<1>(0h0)) node _a_id_T_12 = or(_a_id_T_10, _a_id_T_11) wire a_id : UInt<2> connect a_id, _a_id_T_12 node a_noDomain = eq(a_id, UInt<1>(0h0)) node _a_first_T = and(anonIn.a.ready, anonIn.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), anonIn.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(anonIn.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T node _d_first_T = and(anonOut.d.ready, anonOut.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), anonOut.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(anonOut.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T node _d_first_T_1 = neq(anonOut.d.bits.opcode, UInt<3>(0h6)) node d_first = and(d_first_first, _d_first_T_1) wire _flight_WIRE : UInt<1>[65] connect _flight_WIRE[0], UInt<1>(0h0) connect _flight_WIRE[1], UInt<1>(0h0) connect _flight_WIRE[2], UInt<1>(0h0) connect _flight_WIRE[3], UInt<1>(0h0) connect _flight_WIRE[4], UInt<1>(0h0) connect _flight_WIRE[5], UInt<1>(0h0) connect _flight_WIRE[6], UInt<1>(0h0) connect _flight_WIRE[7], UInt<1>(0h0) connect _flight_WIRE[8], UInt<1>(0h0) connect _flight_WIRE[9], UInt<1>(0h0) connect _flight_WIRE[10], UInt<1>(0h0) connect _flight_WIRE[11], UInt<1>(0h0) connect _flight_WIRE[12], UInt<1>(0h0) connect _flight_WIRE[13], UInt<1>(0h0) connect _flight_WIRE[14], UInt<1>(0h0) connect _flight_WIRE[15], UInt<1>(0h0) connect _flight_WIRE[16], UInt<1>(0h0) connect _flight_WIRE[17], UInt<1>(0h0) connect _flight_WIRE[18], UInt<1>(0h0) connect _flight_WIRE[19], UInt<1>(0h0) connect _flight_WIRE[20], UInt<1>(0h0) connect _flight_WIRE[21], UInt<1>(0h0) connect _flight_WIRE[22], UInt<1>(0h0) connect _flight_WIRE[23], UInt<1>(0h0) connect _flight_WIRE[24], UInt<1>(0h0) connect _flight_WIRE[25], UInt<1>(0h0) connect _flight_WIRE[26], UInt<1>(0h0) connect _flight_WIRE[27], UInt<1>(0h0) connect _flight_WIRE[28], UInt<1>(0h0) connect _flight_WIRE[29], UInt<1>(0h0) connect _flight_WIRE[30], UInt<1>(0h0) connect _flight_WIRE[31], UInt<1>(0h0) connect _flight_WIRE[32], UInt<1>(0h0) connect _flight_WIRE[33], UInt<1>(0h0) connect _flight_WIRE[34], UInt<1>(0h0) connect _flight_WIRE[35], UInt<1>(0h0) connect _flight_WIRE[36], UInt<1>(0h0) connect _flight_WIRE[37], UInt<1>(0h0) connect _flight_WIRE[38], UInt<1>(0h0) connect _flight_WIRE[39], UInt<1>(0h0) connect _flight_WIRE[40], UInt<1>(0h0) connect _flight_WIRE[41], UInt<1>(0h0) connect _flight_WIRE[42], UInt<1>(0h0) connect _flight_WIRE[43], UInt<1>(0h0) connect _flight_WIRE[44], UInt<1>(0h0) connect _flight_WIRE[45], UInt<1>(0h0) connect _flight_WIRE[46], UInt<1>(0h0) connect _flight_WIRE[47], UInt<1>(0h0) connect _flight_WIRE[48], UInt<1>(0h0) connect _flight_WIRE[49], UInt<1>(0h0) connect _flight_WIRE[50], UInt<1>(0h0) connect _flight_WIRE[51], UInt<1>(0h0) connect _flight_WIRE[52], UInt<1>(0h0) connect _flight_WIRE[53], UInt<1>(0h0) connect _flight_WIRE[54], UInt<1>(0h0) connect _flight_WIRE[55], UInt<1>(0h0) connect _flight_WIRE[56], UInt<1>(0h0) connect _flight_WIRE[57], UInt<1>(0h0) connect _flight_WIRE[58], UInt<1>(0h0) connect _flight_WIRE[59], UInt<1>(0h0) connect _flight_WIRE[60], UInt<1>(0h0) connect _flight_WIRE[61], UInt<1>(0h0) connect _flight_WIRE[62], UInt<1>(0h0) connect _flight_WIRE[63], UInt<1>(0h0) connect _flight_WIRE[64], UInt<1>(0h0) regreset flight : UInt<1>[65], clock, reset, _flight_WIRE node _T = and(anonIn.a.ready, anonIn.a.valid) node _T_1 = and(a_first, _T) when _T_1 : node _flight_T = eq(UInt<1>(0h0), UInt<1>(0h0)) connect flight[anonIn.a.bits.source], _flight_T node _T_2 = and(anonIn.d.ready, anonIn.d.valid) node _T_3 = and(d_first, _T_2) when _T_3 : connect flight[anonIn.d.bits.source], UInt<1>(0h0) node _stalls_a_sel_uncommonBits_T = or(anonIn.a.bits.source, UInt<3>(0h0)) node stalls_a_sel_uncommonBits = bits(_stalls_a_sel_uncommonBits_T, 2, 0) node _stalls_a_sel_T = shr(anonIn.a.bits.source, 3) node _stalls_a_sel_T_1 = eq(_stalls_a_sel_T, UInt<1>(0h1)) node _stalls_a_sel_T_2 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits) node _stalls_a_sel_T_3 = and(_stalls_a_sel_T_1, _stalls_a_sel_T_2) node _stalls_a_sel_T_4 = leq(stalls_a_sel_uncommonBits, UInt<3>(0h7)) node stalls_a_sel = and(_stalls_a_sel_T_3, _stalls_a_sel_T_4) node _stalls_id_T = and(anonIn.a.ready, anonIn.a.valid) node _stalls_id_T_1 = and(_stalls_id_T, stalls_a_sel) node _stalls_id_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _stalls_id_T_3 = and(_stalls_id_T_1, _stalls_id_T_2) reg stalls_id : UInt<2>, clock when _stalls_id_T_3 : connect stalls_id, a_id node _stalls_T = and(stalls_a_sel, a_first) node _stalls_T_1 = or(flight[8], flight[9]) node _stalls_T_2 = or(_stalls_T_1, flight[10]) node _stalls_T_3 = or(_stalls_T_2, flight[11]) node _stalls_T_4 = or(_stalls_T_3, flight[12]) node _stalls_T_5 = or(_stalls_T_4, flight[13]) node _stalls_T_6 = or(_stalls_T_5, flight[14]) node _stalls_T_7 = or(_stalls_T_6, flight[15]) node _stalls_T_8 = and(_stalls_T, _stalls_T_7) node _stalls_T_9 = neq(stalls_id, a_id) node _stalls_T_10 = or(a_noDomain, _stalls_T_9) node stalls_0 = and(_stalls_T_8, _stalls_T_10) node stall = or(UInt<1>(0h0), stalls_0) connect anonOut.a, anonIn.a connect anonIn.d, anonOut.d node _anonOut_a_valid_T = eq(stall, UInt<1>(0h0)) node _anonOut_a_valid_T_1 = or(UInt<1>(0h0), _anonOut_a_valid_T) node _anonOut_a_valid_T_2 = and(anonIn.a.valid, _anonOut_a_valid_T_1) connect anonOut.a.valid, _anonOut_a_valid_T_2 node _anonIn_a_ready_T = eq(stall, UInt<1>(0h0)) node _anonIn_a_ready_T_1 = or(UInt<1>(0h0), _anonIn_a_ready_T) node _anonIn_a_ready_T_2 = and(anonOut.a.ready, _anonIn_a_ready_T_1) connect anonIn.a.ready, _anonIn_a_ready_T_2 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) node _T_4 = and(anonIn.a.valid, stall) regreset SourceIdFIFOed : UInt<65>, clock, reset, UInt<65>(0h0) wire SourceIdSet : UInt<65> connect SourceIdSet, UInt<65>(0h0) wire SourceIdClear : UInt<65> connect SourceIdClear, UInt<65>(0h0) node _T_5 = and(anonIn.a.ready, anonIn.a.valid) node _T_6 = and(a_first, _T_5) node _T_7 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_8 = and(_T_6, _T_7) when _T_8 : node _SourceIdSet_T = dshl(UInt<1>(0h1), anonIn.a.bits.source) connect SourceIdSet, _SourceIdSet_T node _T_9 = and(anonIn.d.ready, anonIn.d.valid) node _T_10 = and(d_first, _T_9) when _T_10 : node _SourceIdClear_T = dshl(UInt<1>(0h1), anonIn.d.bits.source) connect SourceIdClear, _SourceIdClear_T node _SourceIdFIFOed_T = or(SourceIdFIFOed, SourceIdSet) connect SourceIdFIFOed, _SourceIdFIFOed_T node _allIDs_FIFOed_T = mux(UInt<1>(0h1), UInt<65>(0h1ffffffffffffffff), UInt<65>(0h0)) node allIDs_FIFOed = eq(SourceIdFIFOed, _allIDs_FIFOed_T) node _T_11 = or(flight[0], flight[1]) node _T_12 = or(_T_11, flight[2]) node _T_13 = or(_T_12, flight[3]) node _T_14 = or(_T_13, flight[4]) node _T_15 = or(_T_14, flight[5]) node _T_16 = or(_T_15, flight[6]) node _T_17 = or(_T_16, flight[7]) node _T_18 = or(_T_17, flight[8]) node _T_19 = or(_T_18, flight[9]) node _T_20 = or(_T_19, flight[10]) node _T_21 = or(_T_20, flight[11]) node _T_22 = or(_T_21, flight[12]) node _T_23 = or(_T_22, flight[13]) node _T_24 = or(_T_23, flight[14]) node _T_25 = or(_T_24, flight[15]) node _T_26 = or(_T_25, flight[16]) node _T_27 = or(_T_26, flight[17]) node _T_28 = or(_T_27, flight[18]) node _T_29 = or(_T_28, flight[19]) node _T_30 = or(_T_29, flight[20]) node _T_31 = or(_T_30, flight[21]) node _T_32 = or(_T_31, flight[22]) node _T_33 = or(_T_32, flight[23]) node _T_34 = or(_T_33, flight[24]) node _T_35 = or(_T_34, flight[25]) node _T_36 = or(_T_35, flight[26]) node _T_37 = or(_T_36, flight[27]) node _T_38 = or(_T_37, flight[28]) node _T_39 = or(_T_38, flight[29]) node _T_40 = or(_T_39, flight[30]) node _T_41 = or(_T_40, flight[31]) node _T_42 = or(_T_41, flight[32]) node _T_43 = or(_T_42, flight[33]) node _T_44 = or(_T_43, flight[34]) node _T_45 = or(_T_44, flight[35]) node _T_46 = or(_T_45, flight[36]) node _T_47 = or(_T_46, flight[37]) node _T_48 = or(_T_47, flight[38]) node _T_49 = or(_T_48, flight[39]) node _T_50 = or(_T_49, flight[40]) node _T_51 = or(_T_50, flight[41]) node _T_52 = or(_T_51, flight[42]) node _T_53 = or(_T_52, flight[43]) node _T_54 = or(_T_53, flight[44]) node _T_55 = or(_T_54, flight[45]) node _T_56 = or(_T_55, flight[46]) node _T_57 = or(_T_56, flight[47]) node _T_58 = or(_T_57, flight[48]) node _T_59 = or(_T_58, flight[49]) node _T_60 = or(_T_59, flight[50]) node _T_61 = or(_T_60, flight[51]) node _T_62 = or(_T_61, flight[52]) node _T_63 = or(_T_62, flight[53]) node _T_64 = or(_T_63, flight[54]) node _T_65 = or(_T_64, flight[55]) node _T_66 = or(_T_65, flight[56]) node _T_67 = or(_T_66, flight[57]) node _T_68 = or(_T_67, flight[58]) node _T_69 = or(_T_68, flight[59]) node _T_70 = or(_T_69, flight[60]) node _T_71 = or(_T_70, flight[61]) node _T_72 = or(_T_71, flight[62]) node _T_73 = or(_T_72, flight[63]) node _T_74 = or(_T_73, flight[64]) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = gt(SourceIdSet, UInt<1>(0h0)) node _T_77 = gt(SourceIdClear, UInt<1>(0h0)) extmodule plusarg_reader_66 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_67 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLFIFOFixer_3( // @[FIFOFixer.scala:50:9] input clock, // @[FIFOFixer.scala:50:9] input reset, // @[FIFOFixer.scala:50:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9] wire [20:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9] wire [6:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9] wire [21:0] _a_notFIFO_T_2 = 22'h0; // @[Parameters.scala:137:46] wire [21:0] _a_notFIFO_T_3 = 22'h0; // @[Parameters.scala:137:46] wire _a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _flight_T = 1'h1; // @[FIFOFixer.scala:80:65] wire _stalls_a_sel_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _stalls_a_sel_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _stalls_id_T_2 = 1'h1; // @[FIFOFixer.scala:85:59] wire [64:0] _allIDs_FIFOed_T = 65'h1FFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48] wire auto_anon_in_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_d_bits_sink = 1'h0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_d_bits_denied = 1'h0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_d_bits_corrupt = 1'h0; // @[FIFOFixer.scala:50:9] wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17] wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire _flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35] wire _flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35] wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[FIFOFixer.scala:50:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[FIFOFixer.scala:50:9] wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[FIFOFixer.scala:50:9] wire [20:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[FIFOFixer.scala:50:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[FIFOFixer.scala:50:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[FIFOFixer.scala:50:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[FIFOFixer.scala:50:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[FIFOFixer.scala:50:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [20:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[FIFOFixer.scala:50:9] wire [6:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[FIFOFixer.scala:50:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_a_ready_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[FIFOFixer.scala:50:9] wire [6:0] auto_anon_in_d_bits_source_0; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[FIFOFixer.scala:50:9] wire auto_anon_in_d_valid_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[FIFOFixer.scala:50:9] wire [2:0] auto_anon_out_a_bits_size_0; // @[FIFOFixer.scala:50:9] wire [6:0] auto_anon_out_a_bits_source_0; // @[FIFOFixer.scala:50:9] wire [20:0] auto_anon_out_a_bits_address_0; // @[FIFOFixer.scala:50:9] wire [7:0] auto_anon_out_a_bits_mask_0; // @[FIFOFixer.scala:50:9] wire [63:0] auto_anon_out_a_bits_data_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_a_valid_0; // @[FIFOFixer.scala:50:9] wire auto_anon_out_d_ready_0; // @[FIFOFixer.scala:50:9] wire _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[FIFOFixer.scala:50:9] assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_param = anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_source = anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] wire [6:0] _stalls_a_sel_uncommonBits_T = anonIn_a_bits_source; // @[Parameters.scala:52:29] assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [20:0] _a_notFIFO_T = anonIn_a_bits_address; // @[Parameters.scala:137:31] wire [20:0] _a_id_T = anonIn_a_bits_address; // @[Parameters.scala:137:31] assign anonOut_a_bits_mask = anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_corrupt = anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign anonOut_d_ready = anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[FIFOFixer.scala:50:9] wire _anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[FIFOFixer.scala:50:9] assign anonIn_d_valid = anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [21:0] _a_notFIFO_T_1 = {1'h0, _a_notFIFO_T}; // @[Parameters.scala:137:{31,41}] wire [21:0] _a_id_T_1 = {1'h0, _a_id_T}; // @[Parameters.scala:137:{31,41}] wire [21:0] _a_id_T_2 = _a_id_T_1 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _a_id_T_3 = _a_id_T_2; // @[Parameters.scala:137:46] wire _a_id_T_4 = _a_id_T_3 == 22'h0; // @[Parameters.scala:137:{46,59}] wire _a_id_T_10 = _a_id_T_4; // @[Mux.scala:30:73] wire [20:0] _a_id_T_5 = {anonIn_a_bits_address[20:17], anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [21:0] _a_id_T_6 = {1'h0, _a_id_T_5}; // @[Parameters.scala:137:{31,41}] wire [21:0] _a_id_T_7 = _a_id_T_6 & 22'h10000; // @[Parameters.scala:137:{41,46}] wire [21:0] _a_id_T_8 = _a_id_T_7; // @[Parameters.scala:137:46] wire _a_id_T_9 = _a_id_T_8 == 22'h0; // @[Parameters.scala:137:{46,59}] wire [1:0] _a_id_T_11 = {_a_id_T_9, 1'h0}; // @[Mux.scala:30:73] wire [1:0] _a_id_T_12 = {1'h0, _a_id_T_10} \| _a_id_T_11; // @[Mux.scala:30:73] wire [1:0] a_id = _a_id_T_12; // @[Mux.scala:30:73] wire a_noDomain = a_id == 2'h0; // @[Mux.scala:30:73] wire _T_5 = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_5; // @[Decoupled.scala:51:35] wire _stalls_id_T; // @[Decoupled.scala:51:35] assign _stalls_id_T = _T_5; // @[Decoupled.scala:51:35] wire [12:0] _a_first_beats1_decode_T = 13'h3F << anonIn_a_bits_size; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _d_first_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35] wire [12:0] _d_first_beats1_decode_T = 13'h3F << anonOut_d_bits_size; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _d_first_T_1 = anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63] wire d_first = d_first_first & _d_first_T_1; // @[FIFOFixer.scala:75:{42,63}] reg flight_0; // @[FIFOFixer.scala:79:27] reg flight_1; // @[FIFOFixer.scala:79:27] reg flight_2; // @[FIFOFixer.scala:79:27] reg flight_3; // @[FIFOFixer.scala:79:27] reg flight_4; // @[FIFOFixer.scala:79:27] reg flight_5; // @[FIFOFixer.scala:79:27] reg flight_6; // @[FIFOFixer.scala:79:27] reg flight_7; // @[FIFOFixer.scala:79:27] reg flight_8; // @[FIFOFixer.scala:79:27] reg flight_9; // @[FIFOFixer.scala:79:27] reg flight_10; // @[FIFOFixer.scala:79:27] reg flight_11; // @[FIFOFixer.scala:79:27] reg flight_12; // @[FIFOFixer.scala:79:27] reg flight_13; // @[FIFOFixer.scala:79:27] reg flight_14; // @[FIFOFixer.scala:79:27] reg flight_15; // @[FIFOFixer.scala:79:27] reg flight_16; // @[FIFOFixer.scala:79:27] reg flight_17; // @[FIFOFixer.scala:79:27] reg flight_18; // @[FIFOFixer.scala:79:27] reg flight_19; // @[FIFOFixer.scala:79:27] reg flight_20; // @[FIFOFixer.scala:79:27] reg flight_21; // @[FIFOFixer.scala:79:27] reg flight_22; // @[FIFOFixer.scala:79:27] reg flight_23; // @[FIFOFixer.scala:79:27] reg flight_24; // @[FIFOFixer.scala:79:27] reg flight_25; // @[FIFOFixer.scala:79:27] reg flight_26; // @[FIFOFixer.scala:79:27] reg flight_27; // @[FIFOFixer.scala:79:27] reg flight_28; // @[FIFOFixer.scala:79:27] reg flight_29; // @[FIFOFixer.scala:79:27] reg flight_30; // @[FIFOFixer.scala:79:27] reg flight_31; // @[FIFOFixer.scala:79:27] reg flight_32; // @[FIFOFixer.scala:79:27] reg flight_33; // @[FIFOFixer.scala:79:27] reg flight_34; // @[FIFOFixer.scala:79:27] reg flight_35; // @[FIFOFixer.scala:79:27] reg flight_36; // @[FIFOFixer.scala:79:27] reg flight_37; // @[FIFOFixer.scala:79:27] reg flight_38; // @[FIFOFixer.scala:79:27] reg flight_39; // @[FIFOFixer.scala:79:27] reg flight_40; // @[FIFOFixer.scala:79:27] reg flight_41; // @[FIFOFixer.scala:79:27] reg flight_42; // @[FIFOFixer.scala:79:27] reg flight_43; // @[FIFOFixer.scala:79:27] reg flight_44; // @[FIFOFixer.scala:79:27] reg flight_45; // @[FIFOFixer.scala:79:27] reg flight_46; // @[FIFOFixer.scala:79:27] reg flight_47; // @[FIFOFixer.scala:79:27] reg flight_48; // @[FIFOFixer.scala:79:27] reg flight_49; // @[FIFOFixer.scala:79:27] reg flight_50; // @[FIFOFixer.scala:79:27] reg flight_51; // @[FIFOFixer.scala:79:27] reg flight_52; // @[FIFOFixer.scala:79:27] reg flight_53; // @[FIFOFixer.scala:79:27] reg flight_54; // @[FIFOFixer.scala:79:27] reg flight_55; // @[FIFOFixer.scala:79:27] reg flight_56; // @[FIFOFixer.scala:79:27] reg flight_57; // @[FIFOFixer.scala:79:27] reg flight_58; // @[FIFOFixer.scala:79:27] reg flight_59; // @[FIFOFixer.scala:79:27] reg flight_60; // @[FIFOFixer.scala:79:27] reg flight_61; // @[FIFOFixer.scala:79:27] reg flight_62; // @[FIFOFixer.scala:79:27] reg flight_63; // @[FIFOFixer.scala:79:27] reg flight_64; // @[FIFOFixer.scala:79:27] wire _T_9 = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35] wire [2:0] stalls_a_sel_uncommonBits = _stalls_a_sel_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _stalls_a_sel_T = anonIn_a_bits_source[6:3]; // @[Parameters.scala:54:10] wire _stalls_a_sel_T_1 = _stalls_a_sel_T == 4'h1; // @[Parameters.scala:54:{10,32}] wire _stalls_a_sel_T_3 = _stalls_a_sel_T_1; // @[Parameters.scala:54:{32,67}] wire stalls_a_sel = _stalls_a_sel_T_3; // @[Parameters.scala:54:67, :56:48] wire _stalls_id_T_1 = _stalls_id_T & stalls_a_sel; // @[Decoupled.scala:51:35] wire _stalls_id_T_3 = _stalls_id_T_1; // @[FIFOFixer.scala:85:{47,56}] reg [1:0] stalls_id; // @[FIFOFixer.scala:85:30] wire _stalls_T = stalls_a_sel & a_first; // @[FIFOFixer.scala:88:15] wire _stalls_T_1 = flight_8 \| flight_9; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_2 = _stalls_T_1 \| flight_10; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_3 = _stalls_T_2 \| flight_11; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_4 = _stalls_T_3 \| flight_12; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_5 = _stalls_T_4 \| flight_13; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_6 = _stalls_T_5 \| flight_14; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_7 = _stalls_T_6 \| flight_15; // @[FIFOFixer.scala:79:27, :88:44] wire _stalls_T_8 = _stalls_T & _stalls_T_7; // @[FIFOFixer.scala:88:{15,26,44}] wire _stalls_T_9 = stalls_id != a_id; // @[Mux.scala:30:73] wire _stalls_T_10 = a_noDomain \| _stalls_T_9; // @[FIFOFixer.scala:63:29, :88:{65,71}] wire stalls_0 = _stalls_T_8 & _stalls_T_10; // @[FIFOFixer.scala:88:{26,50,65}] wire stall = stalls_0; // @[FIFOFixer.scala:88:50, :91:45] wire _anonOut_a_valid_T = ~stall; // @[FIFOFixer.scala:91:45, :95:50] wire _anonOut_a_valid_T_1 = _anonOut_a_valid_T; // @[FIFOFixer.scala:95:{47,50}] assign _anonOut_a_valid_T_2 = anonIn_a_valid & _anonOut_a_valid_T_1; // @[FIFOFixer.scala:95:{33,47}] assign anonOut_a_valid = _anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33] wire _anonIn_a_ready_T = ~stall; // @[FIFOFixer.scala:91:45, :95:50, :96:50] wire _anonIn_a_ready_T_1 = _anonIn_a_ready_T; // @[FIFOFixer.scala:96:{47,50}] assign _anonIn_a_ready_T_2 = anonOut_a_ready & _anonIn_a_ready_T_1; // @[FIFOFixer.scala:96:{33,47}] assign anonIn_a_ready = _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33] reg [64:0] SourceIdFIFOed; // @[FIFOFixer.scala:115:35] wire [64:0] SourceIdSet; // @[FIFOFixer.scala:116:36] wire [64:0] SourceIdClear; // @[FIFOFixer.scala:117:38] wire [127:0] _SourceIdSet_T = 128'h1 << anonIn_a_bits_source; // @[OneHot.scala:58:35] assign SourceIdSet = a_first & _T_5 ? _SourceIdSet_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [127:0] _SourceIdClear_T = 128'h1 << anonIn_d_bits_source; // @[OneHot.scala:58:35] assign SourceIdClear = d_first & _T_9 ? _SourceIdClear_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [64:0] _SourceIdFIFOed_T = SourceIdFIFOed \| SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40] wire allIDs_FIFOed = &SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41] wire _T_1 = a_first & _T_5; // @[Decoupled.scala:51:35] wire _T_3 = d_first & _T_9; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[FIFOFixer.scala:50:9] if (reset) begin // @[FIFOFixer.scala:50:9] a_first_counter <= 3'h0; // @[Edges.scala:229:27] d_first_counter <= 3'h0; // @[Edges.scala:229:27] flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27] flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27] SourceIdFIFOed <= 65'h0; // @[FIFOFixer.scala:115:35] end else begin // @[FIFOFixer.scala:50:9] if (_a_first_T) // @[Decoupled.scala:51:35] a_first_counter <= _a_first_counter_T; // @[Edges.scala:229:27, :236:21] if (_d_first_T) // @[Decoupled.scala:51:35] d_first_counter <= _d_first_counter_T; // @[Edges.scala:229:27, :236:21] flight_0 <= ~(_T_3 & anonIn_d_bits_source == 7'h0) & (_T_1 & anonIn_a_bits_source == 7'h0 \| flight_0); // @[package.scala:243:71] flight_1 <= ~(_T_3 & anonIn_d_bits_source == 7'h1) & (_T_1 & anonIn_a_bits_source == 7'h1 \| flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_2 <= ~(_T_3 & anonIn_d_bits_source == 7'h2) & (_T_1 & anonIn_a_bits_source == 7'h2 \| flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_3 <= ~(_T_3 & anonIn_d_bits_source == 7'h3) & (_T_1 & anonIn_a_bits_source == 7'h3 \| flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_4 <= ~(_T_3 & anonIn_d_bits_source == 7'h4) & (_T_1 & anonIn_a_bits_source == 7'h4 \| flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_5 <= ~(_T_3 & anonIn_d_bits_source == 7'h5) & (_T_1 & anonIn_a_bits_source == 7'h5 \| flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_6 <= ~(_T_3 & anonIn_d_bits_source == 7'h6) & (_T_1 & anonIn_a_bits_source == 7'h6 \| flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_7 <= ~(_T_3 & anonIn_d_bits_source == 7'h7) & (_T_1 & anonIn_a_bits_source == 7'h7 \| flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_8 <= ~(_T_3 & anonIn_d_bits_source == 7'h8) & (_T_1 & anonIn_a_bits_source == 7'h8 \| flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_9 <= ~(_T_3 & anonIn_d_bits_source == 7'h9) & (_T_1 & anonIn_a_bits_source == 7'h9 \| flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_10 <= ~(_T_3 & anonIn_d_bits_source == 7'hA) & (_T_1 & anonIn_a_bits_source == 7'hA \| flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_11 <= ~(_T_3 & anonIn_d_bits_source == 7'hB) & (_T_1 & anonIn_a_bits_source == 7'hB \| flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_12 <= ~(_T_3 & anonIn_d_bits_source == 7'hC) & (_T_1 & anonIn_a_bits_source == 7'hC \| flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_13 <= ~(_T_3 & anonIn_d_bits_source == 7'hD) & (_T_1 & anonIn_a_bits_source == 7'hD \| flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_14 <= ~(_T_3 & anonIn_d_bits_source == 7'hE) & (_T_1 & anonIn_a_bits_source == 7'hE \| flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_15 <= ~(_T_3 & anonIn_d_bits_source == 7'hF) & (_T_1 & anonIn_a_bits_source == 7'hF \| flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_16 <= ~(_T_3 & anonIn_d_bits_source == 7'h10) & (_T_1 & anonIn_a_bits_source == 7'h10 \| flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_17 <= ~(_T_3 & anonIn_d_bits_source == 7'h11) & (_T_1 & anonIn_a_bits_source == 7'h11 \| flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_18 <= ~(_T_3 & anonIn_d_bits_source == 7'h12) & (_T_1 & anonIn_a_bits_source == 7'h12 \| flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_19 <= ~(_T_3 & anonIn_d_bits_source == 7'h13) & (_T_1 & anonIn_a_bits_source == 7'h13 \| flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_20 <= ~(_T_3 & anonIn_d_bits_source == 7'h14) & (_T_1 & anonIn_a_bits_source == 7'h14 \| flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_21 <= ~(_T_3 & anonIn_d_bits_source == 7'h15) & (_T_1 & anonIn_a_bits_source == 7'h15 \| flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_22 <= ~(_T_3 & anonIn_d_bits_source == 7'h16) & (_T_1 & anonIn_a_bits_source == 7'h16 \| flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_23 <= ~(_T_3 & anonIn_d_bits_source == 7'h17) & (_T_1 & anonIn_a_bits_source == 7'h17 \| flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_24 <= ~(_T_3 & anonIn_d_bits_source == 7'h18) & (_T_1 & anonIn_a_bits_source == 7'h18 \| flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_25 <= ~(_T_3 & anonIn_d_bits_source == 7'h19) & (_T_1 & anonIn_a_bits_source == 7'h19 \| flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_26 <= ~(_T_3 & anonIn_d_bits_source == 7'h1A) & (_T_1 & anonIn_a_bits_source == 7'h1A \| flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_27 <= ~(_T_3 & anonIn_d_bits_source == 7'h1B) & (_T_1 & anonIn_a_bits_source == 7'h1B \| flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_28 <= ~(_T_3 & anonIn_d_bits_source == 7'h1C) & (_T_1 & anonIn_a_bits_source == 7'h1C \| flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_29 <= ~(_T_3 & anonIn_d_bits_source == 7'h1D) & (_T_1 & anonIn_a_bits_source == 7'h1D \| flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_30 <= ~(_T_3 & anonIn_d_bits_source == 7'h1E) & (_T_1 & anonIn_a_bits_source == 7'h1E \| flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_31 <= ~(_T_3 & anonIn_d_bits_source == 7'h1F) & (_T_1 & anonIn_a_bits_source == 7'h1F \| flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_32 <= ~(_T_3 & anonIn_d_bits_source == 7'h20) & (_T_1 & anonIn_a_bits_source == 7'h20 \| flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_33 <= ~(_T_3 & anonIn_d_bits_source == 7'h21) & (_T_1 & anonIn_a_bits_source == 7'h21 \| flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_34 <= ~(_T_3 & anonIn_d_bits_source == 7'h22) & (_T_1 & anonIn_a_bits_source == 7'h22 \| flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_35 <= ~(_T_3 & anonIn_d_bits_source == 7'h23) & (_T_1 & anonIn_a_bits_source == 7'h23 \| flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_36 <= ~(_T_3 & anonIn_d_bits_source == 7'h24) & (_T_1 & anonIn_a_bits_source == 7'h24 \| flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_37 <= ~(_T_3 & anonIn_d_bits_source == 7'h25) & (_T_1 & anonIn_a_bits_source == 7'h25 \| flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_38 <= ~(_T_3 & anonIn_d_bits_source == 7'h26) & (_T_1 & anonIn_a_bits_source == 7'h26 \| flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_39 <= ~(_T_3 & anonIn_d_bits_source == 7'h27) & (_T_1 & anonIn_a_bits_source == 7'h27 \| flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_40 <= ~(_T_3 & anonIn_d_bits_source == 7'h28) & (_T_1 & anonIn_a_bits_source == 7'h28 \| flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_41 <= ~(_T_3 & anonIn_d_bits_source == 7'h29) & (_T_1 & anonIn_a_bits_source == 7'h29 \| flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_42 <= ~(_T_3 & anonIn_d_bits_source == 7'h2A) & (_T_1 & anonIn_a_bits_source == 7'h2A \| flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_43 <= ~(_T_3 & anonIn_d_bits_source == 7'h2B) & (_T_1 & anonIn_a_bits_source == 7'h2B \| flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_44 <= ~(_T_3 & anonIn_d_bits_source == 7'h2C) & (_T_1 & anonIn_a_bits_source == 7'h2C \| flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_45 <= ~(_T_3 & anonIn_d_bits_source == 7'h2D) & (_T_1 & anonIn_a_bits_source == 7'h2D \| flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_46 <= ~(_T_3 & anonIn_d_bits_source == 7'h2E) & (_T_1 & anonIn_a_bits_source == 7'h2E \| flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_47 <= ~(_T_3 & anonIn_d_bits_source == 7'h2F) & (_T_1 & anonIn_a_bits_source == 7'h2F \| flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_48 <= ~(_T_3 & anonIn_d_bits_source == 7'h30) & (_T_1 & anonIn_a_bits_source == 7'h30 \| flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_49 <= ~(_T_3 & anonIn_d_bits_source == 7'h31) & (_T_1 & anonIn_a_bits_source == 7'h31 \| flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_50 <= ~(_T_3 & anonIn_d_bits_source == 7'h32) & (_T_1 & anonIn_a_bits_source == 7'h32 \| flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_51 <= ~(_T_3 & anonIn_d_bits_source == 7'h33) & (_T_1 & anonIn_a_bits_source == 7'h33 \| flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_52 <= ~(_T_3 & anonIn_d_bits_source == 7'h34) & (_T_1 & anonIn_a_bits_source == 7'h34 \| flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_53 <= ~(_T_3 & anonIn_d_bits_source == 7'h35) & (_T_1 & anonIn_a_bits_source == 7'h35 \| flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_54 <= ~(_T_3 & anonIn_d_bits_source == 7'h36) & (_T_1 & anonIn_a_bits_source == 7'h36 \| flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_55 <= ~(_T_3 & anonIn_d_bits_source == 7'h37) & (_T_1 & anonIn_a_bits_source == 7'h37 \| flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_56 <= ~(_T_3 & anonIn_d_bits_source == 7'h38) & (_T_1 & anonIn_a_bits_source == 7'h38 \| flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_57 <= ~(_T_3 & anonIn_d_bits_source == 7'h39) & (_T_1 & anonIn_a_bits_source == 7'h39 \| flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_58 <= ~(_T_3 & anonIn_d_bits_source == 7'h3A) & (_T_1 & anonIn_a_bits_source == 7'h3A \| flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_59 <= ~(_T_3 & anonIn_d_bits_source == 7'h3B) & (_T_1 & anonIn_a_bits_source == 7'h3B \| flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_60 <= ~(_T_3 & anonIn_d_bits_source == 7'h3C) & (_T_1 & anonIn_a_bits_source == 7'h3C \| flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_61 <= ~(_T_3 & anonIn_d_bits_source == 7'h3D) & (_T_1 & anonIn_a_bits_source == 7'h3D \| flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_62 <= ~(_T_3 & anonIn_d_bits_source == 7'h3E) & (_T_1 & anonIn_a_bits_source == 7'h3E \| flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_63 <= ~(_T_3 & anonIn_d_bits_source == 7'h3F) & (_T_1 & anonIn_a_bits_source == 7'h3F \| flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] flight_64 <= ~(_T_3 & anonIn_d_bits_source == 7'h40) & (_T_1 & anonIn_a_bits_source == 7'h40 \| flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}] SourceIdFIFOed <= _SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40] end if (_stalls_id_T_3) // @[FIFOFixer.scala:85:56] stalls_id <= a_id; // @[Mux.scala:30:73] always @(posedge) TLMonitor_32 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[FIFOFixer.scala:50:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[FIFOFixer.scala:50:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_105 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_173 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_105( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_173 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_159 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_279 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_159( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_279 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter : input clock : Clock input reset : Reset output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate tlNodeIn.d.bits.corrupt invalidate tlNodeIn.d.bits.data invalidate tlNodeIn.d.bits.denied invalidate tlNodeIn.d.bits.sink invalidate tlNodeIn.d.bits.source invalidate tlNodeIn.d.bits.size invalidate tlNodeIn.d.bits.param invalidate tlNodeIn.d.bits.opcode invalidate tlNodeIn.d.valid invalidate tlNodeIn.d.ready invalidate tlNodeIn.a.bits.corrupt invalidate tlNodeIn.a.bits.data invalidate tlNodeIn.a.bits.mask invalidate tlNodeIn.a.bits.address invalidate tlNodeIn.a.bits.source invalidate tlNodeIn.a.bits.size invalidate tlNodeIn.a.bits.param invalidate tlNodeIn.a.bits.opcode invalidate tlNodeIn.a.valid invalidate tlNodeIn.a.ready inst monitor of TLMonitor_69 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode connect monitor.io.in.d.valid, tlNodeIn.d.valid connect monitor.io.in.d.ready, tlNodeIn.d.ready connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode connect monitor.io.in.a.valid, tlNodeIn.a.valid connect monitor.io.in.a.ready, tlNodeIn.a.ready wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeOut.member.allClocks_uncore.reset invalidate clockNodeOut.member.allClocks_uncore.clock wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clockNodeIn.member.allClocks_uncore.reset invalidate clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut, clockNodeIn connect tlNodeIn, auto.tl_in connect auto.clock_out, clockNodeOut connect clockNodeIn, auto.clock_in wire tile_async_resets : Reset[1] node _tile_async_resets_0_T = asAsyncReset(UInt<1>(0h1)) connect tile_async_resets[0], _tile_async_resets_0_T inst r_tile_resets_0 of AsyncResetRegVec_w1_i0_6 connect r_tile_resets_0.clock, clock connect r_tile_resets_0.reset, tile_async_resets[0] wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(tlNodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, tlNodeIn.a.bits.data connect in.bits.mask, tlNodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect r_tile_resets_0.io.en, out_f_woready connect r_tile_resets_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(r_tile_resets_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, tlNodeIn.a.valid connect tlNodeIn.a.ready, in.ready connect tlNodeIn.d.valid, out.valid connect out.ready, tlNodeIn.d.ready wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0) connect tlNodeIn_d_bits_d.param, UInt<1>(0h0) connect tlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect tlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0) connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate tlNodeIn_d_bits_d.data connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode connect tlNodeIn.d.bits.data, out.bits.data node _tlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset extmodule plusarg_reader_143 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_144 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TileResetSetter( // @[TileResetSetter.scala:26:25] input clock, // @[TileResetSetter.scala:26:25] input reset, // @[TileResetSetter.scala:26:25] input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25] ); wire [2:0] tlNodeIn_d_bits_opcode = {2'h0, auto_tl_in_a_bits_opcode == 3'h4}; // @[RegisterRouter.scala:74:36, :105:19] TLMonitor_69 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_tl_in_d_ready), .io_in_a_valid (auto_tl_in_a_valid), .io_in_a_bits_opcode (auto_tl_in_a_bits_opcode), .io_in_a_bits_param (auto_tl_in_a_bits_param), .io_in_a_bits_size (auto_tl_in_a_bits_size), .io_in_a_bits_source (auto_tl_in_a_bits_source), .io_in_a_bits_address (auto_tl_in_a_bits_address), .io_in_a_bits_mask (auto_tl_in_a_bits_mask), .io_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt), .io_in_d_ready (auto_tl_in_d_ready), .io_in_d_valid (auto_tl_in_a_valid), .io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[RegisterRouter.scala:105:19] .io_in_d_bits_size (auto_tl_in_a_bits_size), .io_in_d_bits_source (auto_tl_in_a_bits_source) ); // @[Nodes.scala:27:25] assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25] assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25] assign auto_tl_in_a_ready = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_valid = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_opcode = tlNodeIn_d_bits_opcode; // @[RegisterRouter.scala:105:19] assign auto_tl_in_d_bits_size = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25] assign auto_tl_in_d_bits_source = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_96 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_184 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_96( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_184 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_1 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_15 = cvt(_T_14) node _T_16 = and(_T_15, asSInt(UInt<1>(0h0))) node _T_17 = asSInt(_T_16) node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0))) node _T_19 = or(_T_13, _T_18) node _T_20 = and(_T_11, _T_19) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_20, UInt<1>(0h1), "") : assert_1 node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_24 : node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_30 = or(_T_28, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_35 = cvt(_T_34) node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000))) node _T_37 = asSInt(_T_36) node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0))) node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_40 = cvt(_T_39) node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000))) node _T_42 = asSInt(_T_41) node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0))) node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_45 = cvt(_T_44) node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000))) node _T_47 = asSInt(_T_46) node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0))) node _T_49 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_50 = cvt(_T_49) node _T_51 = and(_T_50, asSInt(UInt<18>(0h2f000))) node _T_52 = asSInt(_T_51) node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0))) node _T_54 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<27>(0h4000000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = or(_T_38, _T_43) node _T_75 = or(_T_74, _T_48) node _T_76 = or(_T_75, _T_53) node _T_77 = or(_T_76, _T_58) node _T_78 = or(_T_77, _T_63) node _T_79 = or(_T_78, _T_68) node _T_80 = or(_T_79, _T_73) node _T_81 = and(_T_33, _T_80) node _T_82 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_83 = or(UInt<1>(0h0), _T_82) node _T_84 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<17>(0h10000))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<29>(0h10000000))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = or(_T_88, _T_93) node _T_95 = and(_T_83, _T_94) node _T_96 = or(UInt<1>(0h0), _T_81) node _T_97 = or(_T_96, _T_95) node _T_98 = and(_T_32, _T_97) node _T_99 = asUInt(reset) node _T_100 = eq(_T_99, UInt<1>(0h0)) when _T_100 : node _T_101 = eq(_T_98, UInt<1>(0h0)) when _T_101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_98, UInt<1>(0h1), "") : assert_2 node _T_102 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_103 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE : UInt<1>[2] connect _WIRE[0], _T_102 connect _WIRE[1], _T_103 node _T_104 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_105 = mux(_WIRE[0], _T_104, UInt<1>(0h0)) node _T_106 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = or(_T_105, _T_106) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_107 node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_110 = and(_T_108, _T_109) node _T_111 = or(UInt<1>(0h0), _T_110) node _T_112 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<14>(0h2000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<13>(0h1000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<17>(0h10000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<18>(0h2f000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<17>(0h10000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<13>(0h1000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<17>(0h10000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<27>(0h4000000))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<29>(0h10000000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = or(_T_116, _T_121) node _T_163 = or(_T_162, _T_126) node _T_164 = or(_T_163, _T_131) node _T_165 = or(_T_164, _T_136) node _T_166 = or(_T_165, _T_141) node _T_167 = or(_T_166, _T_146) node _T_168 = or(_T_167, _T_151) node _T_169 = or(_T_168, _T_156) node _T_170 = or(_T_169, _T_161) node _T_171 = and(_T_111, _T_170) node _T_172 = or(UInt<1>(0h0), _T_171) node _T_173 = and(_WIRE_1, _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_173, UInt<1>(0h1), "") : assert_3 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(source_ok, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_180 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_180, UInt<1>(0h1), "") : assert_5 node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(is_aligned, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_187 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_187, UInt<1>(0h1), "") : assert_7 node _T_191 = not(io.in.a.bits.mask) node _T_192 = eq(_T_191, UInt<1>(0h0)) node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_T_192, UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_192, UInt<1>(0h1), "") : assert_8 node _T_196 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_197 = asUInt(reset) node _T_198 = eq(_T_197, UInt<1>(0h0)) when _T_198 : node _T_199 = eq(_T_196, UInt<1>(0h0)) when _T_199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_196, UInt<1>(0h1), "") : assert_9 node _T_200 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_200 : node _T_201 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_202 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_205 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_206 = or(_T_204, _T_205) node _T_207 = and(_T_203, _T_206) node _T_208 = or(UInt<1>(0h0), _T_207) node _T_209 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<14>(0h2000))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_221 = cvt(_T_220) node _T_222 = and(_T_221, asSInt(UInt<17>(0h10000))) node _T_223 = asSInt(_T_222) node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0))) node _T_225 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_226 = cvt(_T_225) node _T_227 = and(_T_226, asSInt(UInt<18>(0h2f000))) node _T_228 = asSInt(_T_227) node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0))) node _T_230 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_231 = cvt(_T_230) node _T_232 = and(_T_231, asSInt(UInt<17>(0h10000))) node _T_233 = asSInt(_T_232) node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0))) node _T_235 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_236 = cvt(_T_235) node _T_237 = and(_T_236, asSInt(UInt<13>(0h1000))) node _T_238 = asSInt(_T_237) node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0))) node _T_240 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<27>(0h4000000))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<13>(0h1000))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = or(_T_214, _T_219) node _T_251 = or(_T_250, _T_224) node _T_252 = or(_T_251, _T_229) node _T_253 = or(_T_252, _T_234) node _T_254 = or(_T_253, _T_239) node _T_255 = or(_T_254, _T_244) node _T_256 = or(_T_255, _T_249) node _T_257 = and(_T_209, _T_256) node _T_258 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_259 = or(UInt<1>(0h0), _T_258) node _T_260 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_261 = cvt(_T_260) node _T_262 = and(_T_261, asSInt(UInt<17>(0h10000))) node _T_263 = asSInt(_T_262) node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0))) node _T_265 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_266 = cvt(_T_265) node _T_267 = and(_T_266, asSInt(UInt<29>(0h10000000))) node _T_268 = asSInt(_T_267) node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0))) node _T_270 = or(_T_264, _T_269) node _T_271 = and(_T_259, _T_270) node _T_272 = or(UInt<1>(0h0), _T_257) node _T_273 = or(_T_272, _T_271) node _T_274 = and(_T_208, _T_273) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_274, UInt<1>(0h1), "") : assert_10 node _T_278 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h1)) wire _WIRE_2 : UInt<1>[2] connect _WIRE_2[0], _T_278 connect _WIRE_2[1], _T_279 node _T_280 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_281 = mux(_WIRE_2[0], _T_280, UInt<1>(0h0)) node _T_282 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = or(_T_281, _T_282) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_283 node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_285 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_286 = and(_T_284, _T_285) node _T_287 = or(UInt<1>(0h0), _T_286) node _T_288 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<14>(0h2000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<13>(0h1000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<18>(0h2f000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<13>(0h1000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<17>(0h10000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<27>(0h4000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<29>(0h10000000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = or(_T_292, _T_297) node _T_339 = or(_T_338, _T_302) node _T_340 = or(_T_339, _T_307) node _T_341 = or(_T_340, _T_312) node _T_342 = or(_T_341, _T_317) node _T_343 = or(_T_342, _T_322) node _T_344 = or(_T_343, _T_327) node _T_345 = or(_T_344, _T_332) node _T_346 = or(_T_345, _T_337) node _T_347 = and(_T_287, _T_346) node _T_348 = or(UInt<1>(0h0), _T_347) node _T_349 = and(_WIRE_3, _T_348) node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(_T_349, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_349, UInt<1>(0h1), "") : assert_11 node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(source_ok, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_356 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_357 = asUInt(reset) node _T_358 = eq(_T_357, UInt<1>(0h0)) when _T_358 : node _T_359 = eq(_T_356, UInt<1>(0h0)) when _T_359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_356, UInt<1>(0h1), "") : assert_13 node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(is_aligned, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_363 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_363, UInt<1>(0h1), "") : assert_15 node _T_367 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_367, UInt<1>(0h1), "") : assert_16 node _T_371 = not(io.in.a.bits.mask) node _T_372 = eq(_T_371, UInt<1>(0h0)) node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_T_372, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_372, UInt<1>(0h1), "") : assert_17 node _T_376 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_377 = asUInt(reset) node _T_378 = eq(_T_377, UInt<1>(0h0)) when _T_378 : node _T_379 = eq(_T_376, UInt<1>(0h0)) when _T_379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_376, UInt<1>(0h1), "") : assert_18 node _T_380 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_380 : node _T_381 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_382 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_383 = and(_T_381, _T_382) node _T_384 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_385 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_386 = or(_T_384, _T_385) node _T_387 = and(_T_383, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(_T_388, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_388, UInt<1>(0h1), "") : assert_19 node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_394 = and(_T_392, _T_393) node _T_395 = or(UInt<1>(0h0), _T_394) node _T_396 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_397 = cvt(_T_396) node _T_398 = and(_T_397, asSInt(UInt<13>(0h1000))) node _T_399 = asSInt(_T_398) node _T_400 = eq(_T_399, asSInt(UInt<1>(0h0))) node _T_401 = and(_T_395, _T_400) node _T_402 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_403 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_404 = and(_T_402, _T_403) node _T_405 = or(UInt<1>(0h0), _T_404) node _T_406 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_407 = cvt(_T_406) node _T_408 = and(_T_407, asSInt(UInt<14>(0h2000))) node _T_409 = asSInt(_T_408) node _T_410 = eq(_T_409, asSInt(UInt<1>(0h0))) node _T_411 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_412 = cvt(_T_411) node _T_413 = and(_T_412, asSInt(UInt<17>(0h10000))) node _T_414 = asSInt(_T_413) node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0))) node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_417 = cvt(_T_416) node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000))) node _T_419 = asSInt(_T_418) node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0))) node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_422 = cvt(_T_421) node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000))) node _T_424 = asSInt(_T_423) node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0))) node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<17>(0h10000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<27>(0h4000000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_447 = cvt(_T_446) node _T_448 = and(_T_447, asSInt(UInt<29>(0h10000000))) node _T_449 = asSInt(_T_448) node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0))) node _T_451 = or(_T_410, _T_415) node _T_452 = or(_T_451, _T_420) node _T_453 = or(_T_452, _T_425) node _T_454 = or(_T_453, _T_430) node _T_455 = or(_T_454, _T_435) node _T_456 = or(_T_455, _T_440) node _T_457 = or(_T_456, _T_445) node _T_458 = or(_T_457, _T_450) node _T_459 = and(_T_405, _T_458) node _T_460 = or(UInt<1>(0h0), _T_401) node _T_461 = or(_T_460, _T_459) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_461, UInt<1>(0h1), "") : assert_20 node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(source_ok, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(is_aligned, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_471 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_471, UInt<1>(0h1), "") : assert_23 node _T_475 = eq(io.in.a.bits.mask, mask) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_475, UInt<1>(0h1), "") : assert_24 node _T_479 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_479, UInt<1>(0h1), "") : assert_25 node _T_483 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_483 : node _T_484 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_485 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_486 = and(_T_484, _T_485) node _T_487 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_488 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_489 = or(_T_487, _T_488) node _T_490 = and(_T_486, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_493 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_494 = and(_T_492, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_497 = cvt(_T_496) node _T_498 = and(_T_497, asSInt(UInt<13>(0h1000))) node _T_499 = asSInt(_T_498) node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0))) node _T_501 = and(_T_495, _T_500) node _T_502 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_503 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_504 = and(_T_502, _T_503) node _T_505 = or(UInt<1>(0h0), _T_504) node _T_506 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<14>(0h2000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<18>(0h2f000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<17>(0h10000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<27>(0h4000000))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<13>(0h1000))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_542 = cvt(_T_541) node _T_543 = and(_T_542, asSInt(UInt<29>(0h10000000))) node _T_544 = asSInt(_T_543) node _T_545 = eq(_T_544, asSInt(UInt<1>(0h0))) node _T_546 = or(_T_510, _T_515) node _T_547 = or(_T_546, _T_520) node _T_548 = or(_T_547, _T_525) node _T_549 = or(_T_548, _T_530) node _T_550 = or(_T_549, _T_535) node _T_551 = or(_T_550, _T_540) node _T_552 = or(_T_551, _T_545) node _T_553 = and(_T_505, _T_552) node _T_554 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_555 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_556 = cvt(_T_555) node _T_557 = and(_T_556, asSInt(UInt<17>(0h10000))) node _T_558 = asSInt(_T_557) node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0))) node _T_560 = and(_T_554, _T_559) node _T_561 = or(UInt<1>(0h0), _T_501) node _T_562 = or(_T_561, _T_553) node _T_563 = or(_T_562, _T_560) node _T_564 = and(_T_491, _T_563) node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(_T_564, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_564, UInt<1>(0h1), "") : assert_26 node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(source_ok, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(is_aligned, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_574 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_574, UInt<1>(0h1), "") : assert_29 node _T_578 = eq(io.in.a.bits.mask, mask) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_578, UInt<1>(0h1), "") : assert_30 node _T_582 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_582 : node _T_583 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_584 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_585 = and(_T_583, _T_584) node _T_586 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_587 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(_T_585, _T_588) node _T_590 = or(UInt<1>(0h0), _T_589) node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_592 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_593 = and(_T_591, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_596 = cvt(_T_595) node _T_597 = and(_T_596, asSInt(UInt<13>(0h1000))) node _T_598 = asSInt(_T_597) node _T_599 = eq(_T_598, asSInt(UInt<1>(0h0))) node _T_600 = and(_T_594, _T_599) node _T_601 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_602 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_603 = and(_T_601, _T_602) node _T_604 = or(UInt<1>(0h0), _T_603) node _T_605 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_606 = cvt(_T_605) node _T_607 = and(_T_606, asSInt(UInt<14>(0h2000))) node _T_608 = asSInt(_T_607) node _T_609 = eq(_T_608, asSInt(UInt<1>(0h0))) node _T_610 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_611 = cvt(_T_610) node _T_612 = and(_T_611, asSInt(UInt<18>(0h2f000))) node _T_613 = asSInt(_T_612) node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0))) node _T_615 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_616 = cvt(_T_615) node _T_617 = and(_T_616, asSInt(UInt<17>(0h10000))) node _T_618 = asSInt(_T_617) node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0))) node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_621 = cvt(_T_620) node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000))) node _T_623 = asSInt(_T_622) node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0))) node _T_625 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_626 = cvt(_T_625) node _T_627 = and(_T_626, asSInt(UInt<17>(0h10000))) node _T_628 = asSInt(_T_627) node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0))) node _T_630 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<27>(0h4000000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<29>(0h10000000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = or(_T_609, _T_614) node _T_646 = or(_T_645, _T_619) node _T_647 = or(_T_646, _T_624) node _T_648 = or(_T_647, _T_629) node _T_649 = or(_T_648, _T_634) node _T_650 = or(_T_649, _T_639) node _T_651 = or(_T_650, _T_644) node _T_652 = and(_T_604, _T_651) node _T_653 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_654 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_655 = cvt(_T_654) node _T_656 = and(_T_655, asSInt(UInt<17>(0h10000))) node _T_657 = asSInt(_T_656) node _T_658 = eq(_T_657, asSInt(UInt<1>(0h0))) node _T_659 = and(_T_653, _T_658) node _T_660 = or(UInt<1>(0h0), _T_600) node _T_661 = or(_T_660, _T_652) node _T_662 = or(_T_661, _T_659) node _T_663 = and(_T_590, _T_662) node _T_664 = asUInt(reset) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(_T_663, UInt<1>(0h0)) when _T_666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_663, UInt<1>(0h1), "") : assert_31 node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(source_ok, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(is_aligned, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_673 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_673, UInt<1>(0h1), "") : assert_34 node _T_677 = not(mask) node _T_678 = and(io.in.a.bits.mask, _T_677) node _T_679 = eq(_T_678, UInt<1>(0h0)) node _T_680 = asUInt(reset) node _T_681 = eq(_T_680, UInt<1>(0h0)) when _T_681 : node _T_682 = eq(_T_679, UInt<1>(0h0)) when _T_682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_679, UInt<1>(0h1), "") : assert_35 node _T_683 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_683 : node _T_684 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_685 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_686 = and(_T_684, _T_685) node _T_687 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_688 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_689 = or(_T_687, _T_688) node _T_690 = and(_T_686, _T_689) node _T_691 = or(UInt<1>(0h0), _T_690) node _T_692 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_693 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_694 = and(_T_692, _T_693) node _T_695 = or(UInt<1>(0h0), _T_694) node _T_696 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<14>(0h2000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_702 = cvt(_T_701) node _T_703 = and(_T_702, asSInt(UInt<13>(0h1000))) node _T_704 = asSInt(_T_703) node _T_705 = eq(_T_704, asSInt(UInt<1>(0h0))) node _T_706 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<18>(0h2f000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_712 = cvt(_T_711) node _T_713 = and(_T_712, asSInt(UInt<17>(0h10000))) node _T_714 = asSInt(_T_713) node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0))) node _T_716 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<13>(0h1000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<17>(0h10000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_727 = cvt(_T_726) node _T_728 = and(_T_727, asSInt(UInt<27>(0h4000000))) node _T_729 = asSInt(_T_728) node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0))) node _T_731 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<29>(0h10000000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = or(_T_700, _T_705) node _T_742 = or(_T_741, _T_710) node _T_743 = or(_T_742, _T_715) node _T_744 = or(_T_743, _T_720) node _T_745 = or(_T_744, _T_725) node _T_746 = or(_T_745, _T_730) node _T_747 = or(_T_746, _T_735) node _T_748 = or(_T_747, _T_740) node _T_749 = and(_T_695, _T_748) node _T_750 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_751 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = and(_T_750, _T_755) node _T_757 = or(UInt<1>(0h0), _T_749) node _T_758 = or(_T_757, _T_756) node _T_759 = and(_T_691, _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_759, UInt<1>(0h1), "") : assert_36 node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(source_ok, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(is_aligned, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_769 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_770 = asUInt(reset) node _T_771 = eq(_T_770, UInt<1>(0h0)) when _T_771 : node _T_772 = eq(_T_769, UInt<1>(0h0)) when _T_772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_769, UInt<1>(0h1), "") : assert_39 node _T_773 = eq(io.in.a.bits.mask, mask) node _T_774 = asUInt(reset) node _T_775 = eq(_T_774, UInt<1>(0h0)) when _T_775 : node _T_776 = eq(_T_773, UInt<1>(0h0)) when _T_776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_773, UInt<1>(0h1), "") : assert_40 node _T_777 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_777 : node _T_778 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_779 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_780 = and(_T_778, _T_779) node _T_781 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_782 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_783 = or(_T_781, _T_782) node _T_784 = and(_T_780, _T_783) node _T_785 = or(UInt<1>(0h0), _T_784) node _T_786 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_787 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_788 = and(_T_786, _T_787) node _T_789 = or(UInt<1>(0h0), _T_788) node _T_790 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<14>(0h2000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<13>(0h1000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<18>(0h2f000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<17>(0h10000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<17>(0h10000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<27>(0h4000000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<29>(0h10000000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = or(_T_794, _T_799) node _T_836 = or(_T_835, _T_804) node _T_837 = or(_T_836, _T_809) node _T_838 = or(_T_837, _T_814) node _T_839 = or(_T_838, _T_819) node _T_840 = or(_T_839, _T_824) node _T_841 = or(_T_840, _T_829) node _T_842 = or(_T_841, _T_834) node _T_843 = and(_T_789, _T_842) node _T_844 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_845 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_846 = cvt(_T_845) node _T_847 = and(_T_846, asSInt(UInt<17>(0h10000))) node _T_848 = asSInt(_T_847) node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0))) node _T_850 = and(_T_844, _T_849) node _T_851 = or(UInt<1>(0h0), _T_843) node _T_852 = or(_T_851, _T_850) node _T_853 = and(_T_785, _T_852) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_853, UInt<1>(0h1), "") : assert_41 node _T_857 = asUInt(reset) node _T_858 = eq(_T_857, UInt<1>(0h0)) when _T_858 : node _T_859 = eq(source_ok, UInt<1>(0h0)) when _T_859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(is_aligned, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_863 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_863, UInt<1>(0h1), "") : assert_44 node _T_867 = eq(io.in.a.bits.mask, mask) node _T_868 = asUInt(reset) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(_T_867, UInt<1>(0h0)) when _T_870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_867, UInt<1>(0h1), "") : assert_45 node _T_871 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_871 : node _T_872 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_873 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_874 = and(_T_872, _T_873) node _T_875 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_876 = eq(io.in.a.bits.source, UInt<1>(0h1)) node _T_877 = or(_T_875, _T_876) node _T_878 = and(_T_874, _T_877) node _T_879 = or(UInt<1>(0h0), _T_878) node _T_880 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_881 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_882 = and(_T_880, _T_881) node _T_883 = or(UInt<1>(0h0), _T_882) node _T_884 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = and(_T_883, _T_888) node _T_890 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_891 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<14>(0h2000))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<17>(0h10000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<18>(0h2f000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<17>(0h10000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_912 = cvt(_T_911) node _T_913 = and(_T_912, asSInt(UInt<13>(0h1000))) node _T_914 = asSInt(_T_913) node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_917 = cvt(_T_916) node _T_918 = and(_T_917, asSInt(UInt<27>(0h4000000))) node _T_919 = asSInt(_T_918) node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0))) node _T_921 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<13>(0h1000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = or(_T_895, _T_900) node _T_927 = or(_T_926, _T_905) node _T_928 = or(_T_927, _T_910) node _T_929 = or(_T_928, _T_915) node _T_930 = or(_T_929, _T_920) node _T_931 = or(_T_930, _T_925) node _T_932 = and(_T_890, _T_931) node _T_933 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_934 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_935 = and(_T_933, _T_934) node _T_936 = or(UInt<1>(0h0), _T_935) node _T_937 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_938 = cvt(_T_937) node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000))) node _T_940 = asSInt(_T_939) node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0))) node _T_942 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_943 = cvt(_T_942) node _T_944 = and(_T_943, asSInt(UInt<29>(0h10000000))) node _T_945 = asSInt(_T_944) node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0))) node _T_947 = or(_T_941, _T_946) node _T_948 = and(_T_936, _T_947) node _T_949 = or(UInt<1>(0h0), _T_889) node _T_950 = or(_T_949, _T_932) node _T_951 = or(_T_950, _T_948) node _T_952 = and(_T_879, _T_951) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_952, UInt<1>(0h1), "") : assert_46 node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(source_ok, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(is_aligned, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_962 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(_T_962, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_962, UInt<1>(0h1), "") : assert_49 node _T_966 = eq(io.in.a.bits.mask, mask) node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(_T_966, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_966, UInt<1>(0h1), "") : assert_50 node _T_970 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_970, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_974 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_974, UInt<1>(0h1), "") : assert_52 node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0)) node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_2 connect _source_ok_WIRE_1[1], _source_ok_T_3 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_978 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_978 : node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(source_ok_1, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_982 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_982, UInt<1>(0h1), "") : assert_54 node _T_986 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_986, UInt<1>(0h1), "") : assert_55 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_990, UInt<1>(0h1), "") : assert_56 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_994, UInt<1>(0h1), "") : assert_57 node _T_998 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_998 : node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(source_ok_1, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(sink_ok, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1005 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_60 node _T_1009 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_61 node _T_1013 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_62 node _T_1017 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_63 node _T_1021 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1022 = or(UInt<1>(0h1), _T_1021) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_64 node _T_1026 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1026 : node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(source_ok_1, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(sink_ok, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1033 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1034 = asUInt(reset) node _T_1035 = eq(_T_1034, UInt<1>(0h0)) when _T_1035 : node _T_1036 = eq(_T_1033, UInt<1>(0h0)) when _T_1036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1033, UInt<1>(0h1), "") : assert_67 node _T_1037 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_68 node _T_1041 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_69 node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1046 = or(_T_1045, io.in.d.bits.corrupt) node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(_T_1046, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1046, UInt<1>(0h1), "") : assert_70 node _T_1050 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1051 = or(UInt<1>(0h1), _T_1050) node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(_T_1051, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1051, UInt<1>(0h1), "") : assert_71 node _T_1055 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1055 : node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(source_ok_1, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1059 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_73 node _T_1063 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_74 node _T_1067 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1068 = or(UInt<1>(0h1), _T_1067) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_75 node _T_1072 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1072 : node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(source_ok_1, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1076 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_77 node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1081 = or(_T_1080, io.in.d.bits.corrupt) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_78 node _T_1085 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1086 = or(UInt<1>(0h1), _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_79 node _T_1090 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1090 : node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(source_ok_1, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1094 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_81 node _T_1098 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_82 node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1103 = or(UInt<1>(0h1), _T_1102) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1107 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_T_1107, UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1107, UInt<1>(0h1), "") : assert_84 node _T_1111 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) node _T_1113 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1114 = cvt(_T_1113) node _T_1115 = and(_T_1114, asSInt(UInt<1>(0h0))) node _T_1116 = asSInt(_T_1115) node _T_1117 = eq(_T_1116, asSInt(UInt<1>(0h0))) node _T_1118 = or(_T_1112, _T_1117) node _T_1119 = eq(io.in.b.bits.source, UInt<1>(0h1)) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) node _T_1121 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1122 = cvt(_T_1121) node _T_1123 = and(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = asSInt(_T_1123) node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0))) node _T_1126 = or(_T_1120, _T_1125) node _T_1127 = and(_T_1118, _T_1126) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0)) node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _legal_source_WIRE : UInt<1>[2] connect _legal_source_WIRE[0], _legal_source_T connect _legal_source_WIRE[1], _legal_source_T_1 node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0)) node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3) wire _legal_source_WIRE_1 : UInt<1> connect _legal_source_WIRE_1, _legal_source_T_4 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1131 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1131 : node _T_1132 = eq(io.in.b.bits.source, UInt<1>(0h0)) node _T_1133 = eq(io.in.b.bits.source, UInt<1>(0h1)) wire _WIRE_4 : UInt<1>[2] connect _WIRE_4[0], _T_1132 connect _WIRE_4[1], _T_1133 node _T_1134 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1135 = mux(_WIRE_4[0], _T_1134, UInt<1>(0h0)) node _T_1136 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1137 = or(_T_1135, _T_1136) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1137 node _T_1138 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1139 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1140 = and(_T_1138, _T_1139) node _T_1141 = or(UInt<1>(0h0), _T_1140) node _T_1142 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1143 = cvt(_T_1142) node _T_1144 = and(_T_1143, asSInt(UInt<14>(0h2000))) node _T_1145 = asSInt(_T_1144) node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0))) node _T_1147 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1148 = cvt(_T_1147) node _T_1149 = and(_T_1148, asSInt(UInt<13>(0h1000))) node _T_1150 = asSInt(_T_1149) node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0))) node _T_1152 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1153 = cvt(_T_1152) node _T_1154 = and(_T_1153, asSInt(UInt<17>(0h10000))) node _T_1155 = asSInt(_T_1154) node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0))) node _T_1157 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1158 = cvt(_T_1157) node _T_1159 = and(_T_1158, asSInt(UInt<18>(0h2f000))) node _T_1160 = asSInt(_T_1159) node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0))) node _T_1162 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1163 = cvt(_T_1162) node _T_1164 = and(_T_1163, asSInt(UInt<17>(0h10000))) node _T_1165 = asSInt(_T_1164) node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0))) node _T_1167 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1168 = cvt(_T_1167) node _T_1169 = and(_T_1168, asSInt(UInt<13>(0h1000))) node _T_1170 = asSInt(_T_1169) node _T_1171 = eq(_T_1170, asSInt(UInt<1>(0h0))) node _T_1172 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1173 = cvt(_T_1172) node _T_1174 = and(_T_1173, asSInt(UInt<17>(0h10000))) node _T_1175 = asSInt(_T_1174) node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0))) node _T_1177 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1178 = cvt(_T_1177) node _T_1179 = and(_T_1178, asSInt(UInt<27>(0h4000000))) node _T_1180 = asSInt(_T_1179) node _T_1181 = eq(_T_1180, asSInt(UInt<1>(0h0))) node _T_1182 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1183 = cvt(_T_1182) node _T_1184 = and(_T_1183, asSInt(UInt<13>(0h1000))) node _T_1185 = asSInt(_T_1184) node _T_1186 = eq(_T_1185, asSInt(UInt<1>(0h0))) node _T_1187 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1188 = cvt(_T_1187) node _T_1189 = and(_T_1188, asSInt(UInt<29>(0h10000000))) node _T_1190 = asSInt(_T_1189) node _T_1191 = eq(_T_1190, asSInt(UInt<1>(0h0))) node _T_1192 = or(_T_1146, _T_1151) node _T_1193 = or(_T_1192, _T_1156) node _T_1194 = or(_T_1193, _T_1161) node _T_1195 = or(_T_1194, _T_1166) node _T_1196 = or(_T_1195, _T_1171) node _T_1197 = or(_T_1196, _T_1176) node _T_1198 = or(_T_1197, _T_1181) node _T_1199 = or(_T_1198, _T_1186) node _T_1200 = or(_T_1199, _T_1191) node _T_1201 = and(_T_1141, _T_1200) node _T_1202 = or(UInt<1>(0h0), _T_1201) node _T_1203 = and(_WIRE_5, _T_1202) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_86 node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(address_ok, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(legal_source, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1216 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_90 node _T_1220 = eq(io.in.b.bits.mask, mask_1) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_91 node _T_1224 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1225 = asUInt(reset) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) when _T_1226 : node _T_1227 = eq(_T_1224, UInt<1>(0h0)) when _T_1227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1224, UInt<1>(0h1), "") : assert_92 node _T_1228 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1228 : node _T_1229 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1230 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1231 = and(_T_1229, _T_1230) node _T_1232 = or(UInt<1>(0h0), _T_1231) node _T_1233 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1234 = cvt(_T_1233) node _T_1235 = and(_T_1234, asSInt(UInt<14>(0h2000))) node _T_1236 = asSInt(_T_1235) node _T_1237 = eq(_T_1236, asSInt(UInt<1>(0h0))) node _T_1238 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1239 = cvt(_T_1238) node _T_1240 = and(_T_1239, asSInt(UInt<13>(0h1000))) node _T_1241 = asSInt(_T_1240) node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0))) node _T_1243 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1244 = cvt(_T_1243) node _T_1245 = and(_T_1244, asSInt(UInt<17>(0h10000))) node _T_1246 = asSInt(_T_1245) node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0))) node _T_1248 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1249 = cvt(_T_1248) node _T_1250 = and(_T_1249, asSInt(UInt<18>(0h2f000))) node _T_1251 = asSInt(_T_1250) node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0))) node _T_1253 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1254 = cvt(_T_1253) node _T_1255 = and(_T_1254, asSInt(UInt<17>(0h10000))) node _T_1256 = asSInt(_T_1255) node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0))) node _T_1258 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1259 = cvt(_T_1258) node _T_1260 = and(_T_1259, asSInt(UInt<13>(0h1000))) node _T_1261 = asSInt(_T_1260) node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0))) node _T_1263 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1264 = cvt(_T_1263) node _T_1265 = and(_T_1264, asSInt(UInt<17>(0h10000))) node _T_1266 = asSInt(_T_1265) node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0))) node _T_1268 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1269 = cvt(_T_1268) node _T_1270 = and(_T_1269, asSInt(UInt<27>(0h4000000))) node _T_1271 = asSInt(_T_1270) node _T_1272 = eq(_T_1271, asSInt(UInt<1>(0h0))) node _T_1273 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1274 = cvt(_T_1273) node _T_1275 = and(_T_1274, asSInt(UInt<13>(0h1000))) node _T_1276 = asSInt(_T_1275) node _T_1277 = eq(_T_1276, asSInt(UInt<1>(0h0))) node _T_1278 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1279 = cvt(_T_1278) node _T_1280 = and(_T_1279, asSInt(UInt<29>(0h10000000))) node _T_1281 = asSInt(_T_1280) node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0))) node _T_1283 = or(_T_1237, _T_1242) node _T_1284 = or(_T_1283, _T_1247) node _T_1285 = or(_T_1284, _T_1252) node _T_1286 = or(_T_1285, _T_1257) node _T_1287 = or(_T_1286, _T_1262) node _T_1288 = or(_T_1287, _T_1267) node _T_1289 = or(_T_1288, _T_1272) node _T_1290 = or(_T_1289, _T_1277) node _T_1291 = or(_T_1290, _T_1282) node _T_1292 = and(_T_1232, _T_1291) node _T_1293 = or(UInt<1>(0h0), _T_1292) node _T_1294 = and(UInt<1>(0h0), _T_1293) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_93 node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(address_ok, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(legal_source, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1307 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(_T_1307, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1307, UInt<1>(0h1), "") : assert_97 node _T_1311 = eq(io.in.b.bits.mask, mask_1) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_98 node _T_1315 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_99 node _T_1319 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1319 : node _T_1320 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1321 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1322 = and(_T_1320, _T_1321) node _T_1323 = or(UInt<1>(0h0), _T_1322) node _T_1324 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1325 = cvt(_T_1324) node _T_1326 = and(_T_1325, asSInt(UInt<14>(0h2000))) node _T_1327 = asSInt(_T_1326) node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0))) node _T_1329 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1330 = cvt(_T_1329) node _T_1331 = and(_T_1330, asSInt(UInt<13>(0h1000))) node _T_1332 = asSInt(_T_1331) node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0))) node _T_1334 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1335 = cvt(_T_1334) node _T_1336 = and(_T_1335, asSInt(UInt<17>(0h10000))) node _T_1337 = asSInt(_T_1336) node _T_1338 = eq(_T_1337, asSInt(UInt<1>(0h0))) node _T_1339 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1340 = cvt(_T_1339) node _T_1341 = and(_T_1340, asSInt(UInt<18>(0h2f000))) node _T_1342 = asSInt(_T_1341) node _T_1343 = eq(_T_1342, asSInt(UInt<1>(0h0))) node _T_1344 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1345 = cvt(_T_1344) node _T_1346 = and(_T_1345, asSInt(UInt<17>(0h10000))) node _T_1347 = asSInt(_T_1346) node _T_1348 = eq(_T_1347, asSInt(UInt<1>(0h0))) node _T_1349 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1350 = cvt(_T_1349) node _T_1351 = and(_T_1350, asSInt(UInt<13>(0h1000))) node _T_1352 = asSInt(_T_1351) node _T_1353 = eq(_T_1352, asSInt(UInt<1>(0h0))) node _T_1354 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1355 = cvt(_T_1354) node _T_1356 = and(_T_1355, asSInt(UInt<17>(0h10000))) node _T_1357 = asSInt(_T_1356) node _T_1358 = eq(_T_1357, asSInt(UInt<1>(0h0))) node _T_1359 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1360 = cvt(_T_1359) node _T_1361 = and(_T_1360, asSInt(UInt<27>(0h4000000))) node _T_1362 = asSInt(_T_1361) node _T_1363 = eq(_T_1362, asSInt(UInt<1>(0h0))) node _T_1364 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1365 = cvt(_T_1364) node _T_1366 = and(_T_1365, asSInt(UInt<13>(0h1000))) node _T_1367 = asSInt(_T_1366) node _T_1368 = eq(_T_1367, asSInt(UInt<1>(0h0))) node _T_1369 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1370 = cvt(_T_1369) node _T_1371 = and(_T_1370, asSInt(UInt<29>(0h10000000))) node _T_1372 = asSInt(_T_1371) node _T_1373 = eq(_T_1372, asSInt(UInt<1>(0h0))) node _T_1374 = or(_T_1328, _T_1333) node _T_1375 = or(_T_1374, _T_1338) node _T_1376 = or(_T_1375, _T_1343) node _T_1377 = or(_T_1376, _T_1348) node _T_1378 = or(_T_1377, _T_1353) node _T_1379 = or(_T_1378, _T_1358) node _T_1380 = or(_T_1379, _T_1363) node _T_1381 = or(_T_1380, _T_1368) node _T_1382 = or(_T_1381, _T_1373) node _T_1383 = and(_T_1323, _T_1382) node _T_1384 = or(UInt<1>(0h0), _T_1383) node _T_1385 = and(UInt<1>(0h0), _T_1384) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_100 node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(address_ok, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1392 = asUInt(reset) node _T_1393 = eq(_T_1392, UInt<1>(0h0)) when _T_1393 : node _T_1394 = eq(legal_source, UInt<1>(0h0)) when _T_1394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1395 = asUInt(reset) node _T_1396 = eq(_T_1395, UInt<1>(0h0)) when _T_1396 : node _T_1397 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1398 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_104 node _T_1402 = eq(io.in.b.bits.mask, mask_1) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_105 node _T_1406 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1406 : node _T_1407 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1408 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1409 = and(_T_1407, _T_1408) node _T_1410 = or(UInt<1>(0h0), _T_1409) node _T_1411 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1412 = cvt(_T_1411) node _T_1413 = and(_T_1412, asSInt(UInt<14>(0h2000))) node _T_1414 = asSInt(_T_1413) node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0))) node _T_1416 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1422 = cvt(_T_1421) node _T_1423 = and(_T_1422, asSInt(UInt<17>(0h10000))) node _T_1424 = asSInt(_T_1423) node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0))) node _T_1426 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1427 = cvt(_T_1426) node _T_1428 = and(_T_1427, asSInt(UInt<18>(0h2f000))) node _T_1429 = asSInt(_T_1428) node _T_1430 = eq(_T_1429, asSInt(UInt<1>(0h0))) node _T_1431 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1432 = cvt(_T_1431) node _T_1433 = and(_T_1432, asSInt(UInt<17>(0h10000))) node _T_1434 = asSInt(_T_1433) node _T_1435 = eq(_T_1434, asSInt(UInt<1>(0h0))) node _T_1436 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1437 = cvt(_T_1436) node _T_1438 = and(_T_1437, asSInt(UInt<13>(0h1000))) node _T_1439 = asSInt(_T_1438) node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0))) node _T_1441 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1442 = cvt(_T_1441) node _T_1443 = and(_T_1442, asSInt(UInt<17>(0h10000))) node _T_1444 = asSInt(_T_1443) node _T_1445 = eq(_T_1444, asSInt(UInt<1>(0h0))) node _T_1446 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1447 = cvt(_T_1446) node _T_1448 = and(_T_1447, asSInt(UInt<27>(0h4000000))) node _T_1449 = asSInt(_T_1448) node _T_1450 = eq(_T_1449, asSInt(UInt<1>(0h0))) node _T_1451 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1452 = cvt(_T_1451) node _T_1453 = and(_T_1452, asSInt(UInt<13>(0h1000))) node _T_1454 = asSInt(_T_1453) node _T_1455 = eq(_T_1454, asSInt(UInt<1>(0h0))) node _T_1456 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1457 = cvt(_T_1456) node _T_1458 = and(_T_1457, asSInt(UInt<29>(0h10000000))) node _T_1459 = asSInt(_T_1458) node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0))) node _T_1461 = or(_T_1415, _T_1420) node _T_1462 = or(_T_1461, _T_1425) node _T_1463 = or(_T_1462, _T_1430) node _T_1464 = or(_T_1463, _T_1435) node _T_1465 = or(_T_1464, _T_1440) node _T_1466 = or(_T_1465, _T_1445) node _T_1467 = or(_T_1466, _T_1450) node _T_1468 = or(_T_1467, _T_1455) node _T_1469 = or(_T_1468, _T_1460) node _T_1470 = and(_T_1410, _T_1469) node _T_1471 = or(UInt<1>(0h0), _T_1470) node _T_1472 = and(UInt<1>(0h0), _T_1471) node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(_T_1472, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1472, UInt<1>(0h1), "") : assert_106 node _T_1476 = asUInt(reset) node _T_1477 = eq(_T_1476, UInt<1>(0h0)) when _T_1477 : node _T_1478 = eq(address_ok, UInt<1>(0h0)) when _T_1478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1479 = asUInt(reset) node _T_1480 = eq(_T_1479, UInt<1>(0h0)) when _T_1480 : node _T_1481 = eq(legal_source, UInt<1>(0h0)) when _T_1481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1485 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_110 node _T_1489 = not(mask_1) node _T_1490 = and(io.in.b.bits.mask, _T_1489) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(_T_1491, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1491, UInt<1>(0h1), "") : assert_111 node _T_1495 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1495 : node _T_1496 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1497 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1498 = and(_T_1496, _T_1497) node _T_1499 = or(UInt<1>(0h0), _T_1498) node _T_1500 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1501 = cvt(_T_1500) node _T_1502 = and(_T_1501, asSInt(UInt<14>(0h2000))) node _T_1503 = asSInt(_T_1502) node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0))) node _T_1505 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1506 = cvt(_T_1505) node _T_1507 = and(_T_1506, asSInt(UInt<13>(0h1000))) node _T_1508 = asSInt(_T_1507) node _T_1509 = eq(_T_1508, asSInt(UInt<1>(0h0))) node _T_1510 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1511 = cvt(_T_1510) node _T_1512 = and(_T_1511, asSInt(UInt<17>(0h10000))) node _T_1513 = asSInt(_T_1512) node _T_1514 = eq(_T_1513, asSInt(UInt<1>(0h0))) node _T_1515 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1516 = cvt(_T_1515) node _T_1517 = and(_T_1516, asSInt(UInt<18>(0h2f000))) node _T_1518 = asSInt(_T_1517) node _T_1519 = eq(_T_1518, asSInt(UInt<1>(0h0))) node _T_1520 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1521 = cvt(_T_1520) node _T_1522 = and(_T_1521, asSInt(UInt<17>(0h10000))) node _T_1523 = asSInt(_T_1522) node _T_1524 = eq(_T_1523, asSInt(UInt<1>(0h0))) node _T_1525 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1526 = cvt(_T_1525) node _T_1527 = and(_T_1526, asSInt(UInt<13>(0h1000))) node _T_1528 = asSInt(_T_1527) node _T_1529 = eq(_T_1528, asSInt(UInt<1>(0h0))) node _T_1530 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1531 = cvt(_T_1530) node _T_1532 = and(_T_1531, asSInt(UInt<17>(0h10000))) node _T_1533 = asSInt(_T_1532) node _T_1534 = eq(_T_1533, asSInt(UInt<1>(0h0))) node _T_1535 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1536 = cvt(_T_1535) node _T_1537 = and(_T_1536, asSInt(UInt<27>(0h4000000))) node _T_1538 = asSInt(_T_1537) node _T_1539 = eq(_T_1538, asSInt(UInt<1>(0h0))) node _T_1540 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1541 = cvt(_T_1540) node _T_1542 = and(_T_1541, asSInt(UInt<13>(0h1000))) node _T_1543 = asSInt(_T_1542) node _T_1544 = eq(_T_1543, asSInt(UInt<1>(0h0))) node _T_1545 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1546 = cvt(_T_1545) node _T_1547 = and(_T_1546, asSInt(UInt<29>(0h10000000))) node _T_1548 = asSInt(_T_1547) node _T_1549 = eq(_T_1548, asSInt(UInt<1>(0h0))) node _T_1550 = or(_T_1504, _T_1509) node _T_1551 = or(_T_1550, _T_1514) node _T_1552 = or(_T_1551, _T_1519) node _T_1553 = or(_T_1552, _T_1524) node _T_1554 = or(_T_1553, _T_1529) node _T_1555 = or(_T_1554, _T_1534) node _T_1556 = or(_T_1555, _T_1539) node _T_1557 = or(_T_1556, _T_1544) node _T_1558 = or(_T_1557, _T_1549) node _T_1559 = and(_T_1499, _T_1558) node _T_1560 = or(UInt<1>(0h0), _T_1559) node _T_1561 = and(UInt<1>(0h0), _T_1560) node _T_1562 = asUInt(reset) node _T_1563 = eq(_T_1562, UInt<1>(0h0)) when _T_1563 : node _T_1564 = eq(_T_1561, UInt<1>(0h0)) when _T_1564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1561, UInt<1>(0h1), "") : assert_112 node _T_1565 = asUInt(reset) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(address_ok, UInt<1>(0h0)) when _T_1567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1568 = asUInt(reset) node _T_1569 = eq(_T_1568, UInt<1>(0h0)) when _T_1569 : node _T_1570 = eq(legal_source, UInt<1>(0h0)) when _T_1570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1571 = asUInt(reset) node _T_1572 = eq(_T_1571, UInt<1>(0h0)) when _T_1572 : node _T_1573 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1574 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1575 = asUInt(reset) node _T_1576 = eq(_T_1575, UInt<1>(0h0)) when _T_1576 : node _T_1577 = eq(_T_1574, UInt<1>(0h0)) when _T_1577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1574, UInt<1>(0h1), "") : assert_116 node _T_1578 = eq(io.in.b.bits.mask, mask_1) node _T_1579 = asUInt(reset) node _T_1580 = eq(_T_1579, UInt<1>(0h0)) when _T_1580 : node _T_1581 = eq(_T_1578, UInt<1>(0h0)) when _T_1581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1578, UInt<1>(0h1), "") : assert_117 node _T_1582 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1582 : node _T_1583 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1584 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1585 = and(_T_1583, _T_1584) node _T_1586 = or(UInt<1>(0h0), _T_1585) node _T_1587 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1588 = cvt(_T_1587) node _T_1589 = and(_T_1588, asSInt(UInt<14>(0h2000))) node _T_1590 = asSInt(_T_1589) node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0))) node _T_1592 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1593 = cvt(_T_1592) node _T_1594 = and(_T_1593, asSInt(UInt<13>(0h1000))) node _T_1595 = asSInt(_T_1594) node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0))) node _T_1597 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1598 = cvt(_T_1597) node _T_1599 = and(_T_1598, asSInt(UInt<17>(0h10000))) node _T_1600 = asSInt(_T_1599) node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0))) node _T_1602 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1603 = cvt(_T_1602) node _T_1604 = and(_T_1603, asSInt(UInt<18>(0h2f000))) node _T_1605 = asSInt(_T_1604) node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0))) node _T_1607 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1608 = cvt(_T_1607) node _T_1609 = and(_T_1608, asSInt(UInt<17>(0h10000))) node _T_1610 = asSInt(_T_1609) node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0))) node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1613 = cvt(_T_1612) node _T_1614 = and(_T_1613, asSInt(UInt<13>(0h1000))) node _T_1615 = asSInt(_T_1614) node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0))) node _T_1617 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1618 = cvt(_T_1617) node _T_1619 = and(_T_1618, asSInt(UInt<17>(0h10000))) node _T_1620 = asSInt(_T_1619) node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0))) node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1623 = cvt(_T_1622) node _T_1624 = and(_T_1623, asSInt(UInt<27>(0h4000000))) node _T_1625 = asSInt(_T_1624) node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0))) node _T_1627 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1628 = cvt(_T_1627) node _T_1629 = and(_T_1628, asSInt(UInt<13>(0h1000))) node _T_1630 = asSInt(_T_1629) node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0))) node _T_1632 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1633 = cvt(_T_1632) node _T_1634 = and(_T_1633, asSInt(UInt<29>(0h10000000))) node _T_1635 = asSInt(_T_1634) node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0))) node _T_1637 = or(_T_1591, _T_1596) node _T_1638 = or(_T_1637, _T_1601) node _T_1639 = or(_T_1638, _T_1606) node _T_1640 = or(_T_1639, _T_1611) node _T_1641 = or(_T_1640, _T_1616) node _T_1642 = or(_T_1641, _T_1621) node _T_1643 = or(_T_1642, _T_1626) node _T_1644 = or(_T_1643, _T_1631) node _T_1645 = or(_T_1644, _T_1636) node _T_1646 = and(_T_1586, _T_1645) node _T_1647 = or(UInt<1>(0h0), _T_1646) node _T_1648 = and(UInt<1>(0h0), _T_1647) node _T_1649 = asUInt(reset) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(_T_1648, UInt<1>(0h0)) when _T_1651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1648, UInt<1>(0h1), "") : assert_118 node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(address_ok, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1655 = asUInt(reset) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) when _T_1656 : node _T_1657 = eq(legal_source, UInt<1>(0h0)) when _T_1657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1658 = asUInt(reset) node _T_1659 = eq(_T_1658, UInt<1>(0h0)) when _T_1659 : node _T_1660 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1661 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1662 = asUInt(reset) node _T_1663 = eq(_T_1662, UInt<1>(0h0)) when _T_1663 : node _T_1664 = eq(_T_1661, UInt<1>(0h0)) when _T_1664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1661, UInt<1>(0h1), "") : assert_122 node _T_1665 = eq(io.in.b.bits.mask, mask_1) node _T_1666 = asUInt(reset) node _T_1667 = eq(_T_1666, UInt<1>(0h0)) when _T_1667 : node _T_1668 = eq(_T_1665, UInt<1>(0h0)) when _T_1668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1665, UInt<1>(0h1), "") : assert_123 node _T_1669 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1669 : node _T_1670 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1671 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1672 = and(_T_1670, _T_1671) node _T_1673 = or(UInt<1>(0h0), _T_1672) node _T_1674 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1675 = cvt(_T_1674) node _T_1676 = and(_T_1675, asSInt(UInt<14>(0h2000))) node _T_1677 = asSInt(_T_1676) node _T_1678 = eq(_T_1677, asSInt(UInt<1>(0h0))) node _T_1679 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1680 = cvt(_T_1679) node _T_1681 = and(_T_1680, asSInt(UInt<13>(0h1000))) node _T_1682 = asSInt(_T_1681) node _T_1683 = eq(_T_1682, asSInt(UInt<1>(0h0))) node _T_1684 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1685 = cvt(_T_1684) node _T_1686 = and(_T_1685, asSInt(UInt<17>(0h10000))) node _T_1687 = asSInt(_T_1686) node _T_1688 = eq(_T_1687, asSInt(UInt<1>(0h0))) node _T_1689 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1690 = cvt(_T_1689) node _T_1691 = and(_T_1690, asSInt(UInt<18>(0h2f000))) node _T_1692 = asSInt(_T_1691) node _T_1693 = eq(_T_1692, asSInt(UInt<1>(0h0))) node _T_1694 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1695 = cvt(_T_1694) node _T_1696 = and(_T_1695, asSInt(UInt<17>(0h10000))) node _T_1697 = asSInt(_T_1696) node _T_1698 = eq(_T_1697, asSInt(UInt<1>(0h0))) node _T_1699 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1700 = cvt(_T_1699) node _T_1701 = and(_T_1700, asSInt(UInt<13>(0h1000))) node _T_1702 = asSInt(_T_1701) node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0))) node _T_1704 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1705 = cvt(_T_1704) node _T_1706 = and(_T_1705, asSInt(UInt<17>(0h10000))) node _T_1707 = asSInt(_T_1706) node _T_1708 = eq(_T_1707, asSInt(UInt<1>(0h0))) node _T_1709 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1710 = cvt(_T_1709) node _T_1711 = and(_T_1710, asSInt(UInt<27>(0h4000000))) node _T_1712 = asSInt(_T_1711) node _T_1713 = eq(_T_1712, asSInt(UInt<1>(0h0))) node _T_1714 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1715 = cvt(_T_1714) node _T_1716 = and(_T_1715, asSInt(UInt<13>(0h1000))) node _T_1717 = asSInt(_T_1716) node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0))) node _T_1719 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1720 = cvt(_T_1719) node _T_1721 = and(_T_1720, asSInt(UInt<29>(0h10000000))) node _T_1722 = asSInt(_T_1721) node _T_1723 = eq(_T_1722, asSInt(UInt<1>(0h0))) node _T_1724 = or(_T_1678, _T_1683) node _T_1725 = or(_T_1724, _T_1688) node _T_1726 = or(_T_1725, _T_1693) node _T_1727 = or(_T_1726, _T_1698) node _T_1728 = or(_T_1727, _T_1703) node _T_1729 = or(_T_1728, _T_1708) node _T_1730 = or(_T_1729, _T_1713) node _T_1731 = or(_T_1730, _T_1718) node _T_1732 = or(_T_1731, _T_1723) node _T_1733 = and(_T_1673, _T_1732) node _T_1734 = or(UInt<1>(0h0), _T_1733) node _T_1735 = and(UInt<1>(0h0), _T_1734) node _T_1736 = asUInt(reset) node _T_1737 = eq(_T_1736, UInt<1>(0h0)) when _T_1737 : node _T_1738 = eq(_T_1735, UInt<1>(0h0)) when _T_1738 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1735, UInt<1>(0h1), "") : assert_124 node _T_1739 = asUInt(reset) node _T_1740 = eq(_T_1739, UInt<1>(0h0)) when _T_1740 : node _T_1741 = eq(address_ok, UInt<1>(0h0)) when _T_1741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1742 = asUInt(reset) node _T_1743 = eq(_T_1742, UInt<1>(0h0)) when _T_1743 : node _T_1744 = eq(legal_source, UInt<1>(0h0)) when _T_1744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1745 = asUInt(reset) node _T_1746 = eq(_T_1745, UInt<1>(0h0)) when _T_1746 : node _T_1747 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1748 = eq(io.in.b.bits.mask, mask_1) node _T_1749 = asUInt(reset) node _T_1750 = eq(_T_1749, UInt<1>(0h0)) when _T_1750 : node _T_1751 = eq(_T_1748, UInt<1>(0h0)) when _T_1751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1748, UInt<1>(0h1), "") : assert_128 node _T_1752 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1753 = asUInt(reset) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) when _T_1754 : node _T_1755 = eq(_T_1752, UInt<1>(0h0)) when _T_1755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1752, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1756 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_130 node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _source_ok_WIRE_2 : UInt<1>[2] connect _source_ok_WIRE_2[0], _source_ok_T_4 connect _source_ok_WIRE_2[1], _source_ok_T_5 node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _T_1760 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1763 = cvt(_T_1762) node _T_1764 = and(_T_1763, asSInt(UInt<1>(0h0))) node _T_1765 = asSInt(_T_1764) node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0))) node _T_1767 = or(_T_1761, _T_1766) node _T_1768 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1771 = cvt(_T_1770) node _T_1772 = and(_T_1771, asSInt(UInt<1>(0h0))) node _T_1773 = asSInt(_T_1772) node _T_1774 = eq(_T_1773, asSInt(UInt<1>(0h0))) node _T_1775 = or(_T_1769, _T_1774) node _T_1776 = and(_T_1767, _T_1775) node _T_1777 = asUInt(reset) node _T_1778 = eq(_T_1777, UInt<1>(0h0)) when _T_1778 : node _T_1779 = eq(_T_1776, UInt<1>(0h0)) when _T_1779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1776, UInt<1>(0h1), "") : assert_131 node _T_1780 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1780 : node _T_1781 = asUInt(reset) node _T_1782 = eq(_T_1781, UInt<1>(0h0)) when _T_1782 : node _T_1783 = eq(address_ok_1, UInt<1>(0h0)) when _T_1783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1784 = asUInt(reset) node _T_1785 = eq(_T_1784, UInt<1>(0h0)) when _T_1785 : node _T_1786 = eq(source_ok_2, UInt<1>(0h0)) when _T_1786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1787 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1788 = asUInt(reset) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) when _T_1789 : node _T_1790 = eq(_T_1787, UInt<1>(0h0)) when _T_1790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1787, UInt<1>(0h1), "") : assert_134 node _T_1791 = asUInt(reset) node _T_1792 = eq(_T_1791, UInt<1>(0h0)) when _T_1792 : node _T_1793 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1794 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(_T_1794, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1794, UInt<1>(0h1), "") : assert_136 node _T_1798 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1799 = asUInt(reset) node _T_1800 = eq(_T_1799, UInt<1>(0h0)) when _T_1800 : node _T_1801 = eq(_T_1798, UInt<1>(0h0)) when _T_1801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1798, UInt<1>(0h1), "") : assert_137 node _T_1802 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1802 : node _T_1803 = asUInt(reset) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) when _T_1804 : node _T_1805 = eq(address_ok_1, UInt<1>(0h0)) when _T_1805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1806 = asUInt(reset) node _T_1807 = eq(_T_1806, UInt<1>(0h0)) when _T_1807 : node _T_1808 = eq(source_ok_2, UInt<1>(0h0)) when _T_1808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1809 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1810 = asUInt(reset) node _T_1811 = eq(_T_1810, UInt<1>(0h0)) when _T_1811 : node _T_1812 = eq(_T_1809, UInt<1>(0h0)) when _T_1812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1809, UInt<1>(0h1), "") : assert_140 node _T_1813 = asUInt(reset) node _T_1814 = eq(_T_1813, UInt<1>(0h0)) when _T_1814 : node _T_1815 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1816 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1817 = asUInt(reset) node _T_1818 = eq(_T_1817, UInt<1>(0h0)) when _T_1818 : node _T_1819 = eq(_T_1816, UInt<1>(0h0)) when _T_1819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1816, UInt<1>(0h1), "") : assert_142 node _T_1820 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1820 : node _T_1821 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1822 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1823 = and(_T_1821, _T_1822) node _T_1824 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1825 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1826 = or(_T_1824, _T_1825) node _T_1827 = and(_T_1823, _T_1826) node _T_1828 = or(UInt<1>(0h0), _T_1827) node _T_1829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1830 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1831 = cvt(_T_1830) node _T_1832 = and(_T_1831, asSInt(UInt<14>(0h2000))) node _T_1833 = asSInt(_T_1832) node _T_1834 = eq(_T_1833, asSInt(UInt<1>(0h0))) node _T_1835 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1836 = cvt(_T_1835) node _T_1837 = and(_T_1836, asSInt(UInt<13>(0h1000))) node _T_1838 = asSInt(_T_1837) node _T_1839 = eq(_T_1838, asSInt(UInt<1>(0h0))) node _T_1840 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1841 = cvt(_T_1840) node _T_1842 = and(_T_1841, asSInt(UInt<17>(0h10000))) node _T_1843 = asSInt(_T_1842) node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0))) node _T_1845 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1846 = cvt(_T_1845) node _T_1847 = and(_T_1846, asSInt(UInt<18>(0h2f000))) node _T_1848 = asSInt(_T_1847) node _T_1849 = eq(_T_1848, asSInt(UInt<1>(0h0))) node _T_1850 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1851 = cvt(_T_1850) node _T_1852 = and(_T_1851, asSInt(UInt<17>(0h10000))) node _T_1853 = asSInt(_T_1852) node _T_1854 = eq(_T_1853, asSInt(UInt<1>(0h0))) node _T_1855 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1856 = cvt(_T_1855) node _T_1857 = and(_T_1856, asSInt(UInt<13>(0h1000))) node _T_1858 = asSInt(_T_1857) node _T_1859 = eq(_T_1858, asSInt(UInt<1>(0h0))) node _T_1860 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1861 = cvt(_T_1860) node _T_1862 = and(_T_1861, asSInt(UInt<27>(0h4000000))) node _T_1863 = asSInt(_T_1862) node _T_1864 = eq(_T_1863, asSInt(UInt<1>(0h0))) node _T_1865 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1866 = cvt(_T_1865) node _T_1867 = and(_T_1866, asSInt(UInt<13>(0h1000))) node _T_1868 = asSInt(_T_1867) node _T_1869 = eq(_T_1868, asSInt(UInt<1>(0h0))) node _T_1870 = or(_T_1834, _T_1839) node _T_1871 = or(_T_1870, _T_1844) node _T_1872 = or(_T_1871, _T_1849) node _T_1873 = or(_T_1872, _T_1854) node _T_1874 = or(_T_1873, _T_1859) node _T_1875 = or(_T_1874, _T_1864) node _T_1876 = or(_T_1875, _T_1869) node _T_1877 = and(_T_1829, _T_1876) node _T_1878 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1879 = or(UInt<1>(0h0), _T_1878) node _T_1880 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1881 = cvt(_T_1880) node _T_1882 = and(_T_1881, asSInt(UInt<17>(0h10000))) node _T_1883 = asSInt(_T_1882) node _T_1884 = eq(_T_1883, asSInt(UInt<1>(0h0))) node _T_1885 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1886 = cvt(_T_1885) node _T_1887 = and(_T_1886, asSInt(UInt<29>(0h10000000))) node _T_1888 = asSInt(_T_1887) node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0))) node _T_1890 = or(_T_1884, _T_1889) node _T_1891 = and(_T_1879, _T_1890) node _T_1892 = or(UInt<1>(0h0), _T_1877) node _T_1893 = or(_T_1892, _T_1891) node _T_1894 = and(_T_1828, _T_1893) node _T_1895 = asUInt(reset) node _T_1896 = eq(_T_1895, UInt<1>(0h0)) when _T_1896 : node _T_1897 = eq(_T_1894, UInt<1>(0h0)) when _T_1897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_1894, UInt<1>(0h1), "") : assert_143 node _T_1898 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1899 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_6 : UInt<1>[2] connect _WIRE_6[0], _T_1898 connect _WIRE_6[1], _T_1899 node _T_1900 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1901 = mux(_WIRE_6[0], _T_1900, UInt<1>(0h0)) node _T_1902 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1903 = or(_T_1901, _T_1902) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_1903 node _T_1904 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1905 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1906 = and(_T_1904, _T_1905) node _T_1907 = or(UInt<1>(0h0), _T_1906) node _T_1908 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1909 = cvt(_T_1908) node _T_1910 = and(_T_1909, asSInt(UInt<14>(0h2000))) node _T_1911 = asSInt(_T_1910) node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0))) node _T_1913 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1914 = cvt(_T_1913) node _T_1915 = and(_T_1914, asSInt(UInt<13>(0h1000))) node _T_1916 = asSInt(_T_1915) node _T_1917 = eq(_T_1916, asSInt(UInt<1>(0h0))) node _T_1918 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1919 = cvt(_T_1918) node _T_1920 = and(_T_1919, asSInt(UInt<17>(0h10000))) node _T_1921 = asSInt(_T_1920) node _T_1922 = eq(_T_1921, asSInt(UInt<1>(0h0))) node _T_1923 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1924 = cvt(_T_1923) node _T_1925 = and(_T_1924, asSInt(UInt<18>(0h2f000))) node _T_1926 = asSInt(_T_1925) node _T_1927 = eq(_T_1926, asSInt(UInt<1>(0h0))) node _T_1928 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1929 = cvt(_T_1928) node _T_1930 = and(_T_1929, asSInt(UInt<17>(0h10000))) node _T_1931 = asSInt(_T_1930) node _T_1932 = eq(_T_1931, asSInt(UInt<1>(0h0))) node _T_1933 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1934 = cvt(_T_1933) node _T_1935 = and(_T_1934, asSInt(UInt<13>(0h1000))) node _T_1936 = asSInt(_T_1935) node _T_1937 = eq(_T_1936, asSInt(UInt<1>(0h0))) node _T_1938 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1939 = cvt(_T_1938) node _T_1940 = and(_T_1939, asSInt(UInt<17>(0h10000))) node _T_1941 = asSInt(_T_1940) node _T_1942 = eq(_T_1941, asSInt(UInt<1>(0h0))) node _T_1943 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1944 = cvt(_T_1943) node _T_1945 = and(_T_1944, asSInt(UInt<27>(0h4000000))) node _T_1946 = asSInt(_T_1945) node _T_1947 = eq(_T_1946, asSInt(UInt<1>(0h0))) node _T_1948 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1949 = cvt(_T_1948) node _T_1950 = and(_T_1949, asSInt(UInt<13>(0h1000))) node _T_1951 = asSInt(_T_1950) node _T_1952 = eq(_T_1951, asSInt(UInt<1>(0h0))) node _T_1953 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1954 = cvt(_T_1953) node _T_1955 = and(_T_1954, asSInt(UInt<29>(0h10000000))) node _T_1956 = asSInt(_T_1955) node _T_1957 = eq(_T_1956, asSInt(UInt<1>(0h0))) node _T_1958 = or(_T_1912, _T_1917) node _T_1959 = or(_T_1958, _T_1922) node _T_1960 = or(_T_1959, _T_1927) node _T_1961 = or(_T_1960, _T_1932) node _T_1962 = or(_T_1961, _T_1937) node _T_1963 = or(_T_1962, _T_1942) node _T_1964 = or(_T_1963, _T_1947) node _T_1965 = or(_T_1964, _T_1952) node _T_1966 = or(_T_1965, _T_1957) node _T_1967 = and(_T_1907, _T_1966) node _T_1968 = or(UInt<1>(0h0), _T_1967) node _T_1969 = and(_WIRE_7, _T_1968) node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(_T_1969, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1969, UInt<1>(0h1), "") : assert_144 node _T_1973 = asUInt(reset) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(source_ok_2, UInt<1>(0h0)) when _T_1975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_1976 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1977 = asUInt(reset) node _T_1978 = eq(_T_1977, UInt<1>(0h0)) when _T_1978 : node _T_1979 = eq(_T_1976, UInt<1>(0h0)) when _T_1979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1976, UInt<1>(0h1), "") : assert_146 node _T_1980 = asUInt(reset) node _T_1981 = eq(_T_1980, UInt<1>(0h0)) when _T_1981 : node _T_1982 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1983 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_148 node _T_1987 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(_T_1987, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1987, UInt<1>(0h1), "") : assert_149 node _T_1991 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1991 : node _T_1992 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1993 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1994 = and(_T_1992, _T_1993) node _T_1995 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_1996 = eq(io.in.c.bits.source, UInt<1>(0h1)) node _T_1997 = or(_T_1995, _T_1996) node _T_1998 = and(_T_1994, _T_1997) node _T_1999 = or(UInt<1>(0h0), _T_1998) node _T_2000 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2001 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2002 = cvt(_T_2001) node _T_2003 = and(_T_2002, asSInt(UInt<14>(0h2000))) node _T_2004 = asSInt(_T_2003) node _T_2005 = eq(_T_2004, asSInt(UInt<1>(0h0))) node _T_2006 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2007 = cvt(_T_2006) node _T_2008 = and(_T_2007, asSInt(UInt<13>(0h1000))) node _T_2009 = asSInt(_T_2008) node _T_2010 = eq(_T_2009, asSInt(UInt<1>(0h0))) node _T_2011 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2012 = cvt(_T_2011) node _T_2013 = and(_T_2012, asSInt(UInt<17>(0h10000))) node _T_2014 = asSInt(_T_2013) node _T_2015 = eq(_T_2014, asSInt(UInt<1>(0h0))) node _T_2016 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2017 = cvt(_T_2016) node _T_2018 = and(_T_2017, asSInt(UInt<18>(0h2f000))) node _T_2019 = asSInt(_T_2018) node _T_2020 = eq(_T_2019, asSInt(UInt<1>(0h0))) node _T_2021 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2022 = cvt(_T_2021) node _T_2023 = and(_T_2022, asSInt(UInt<17>(0h10000))) node _T_2024 = asSInt(_T_2023) node _T_2025 = eq(_T_2024, asSInt(UInt<1>(0h0))) node _T_2026 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2027 = cvt(_T_2026) node _T_2028 = and(_T_2027, asSInt(UInt<13>(0h1000))) node _T_2029 = asSInt(_T_2028) node _T_2030 = eq(_T_2029, asSInt(UInt<1>(0h0))) node _T_2031 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2032 = cvt(_T_2031) node _T_2033 = and(_T_2032, asSInt(UInt<27>(0h4000000))) node _T_2034 = asSInt(_T_2033) node _T_2035 = eq(_T_2034, asSInt(UInt<1>(0h0))) node _T_2036 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2037 = cvt(_T_2036) node _T_2038 = and(_T_2037, asSInt(UInt<13>(0h1000))) node _T_2039 = asSInt(_T_2038) node _T_2040 = eq(_T_2039, asSInt(UInt<1>(0h0))) node _T_2041 = or(_T_2005, _T_2010) node _T_2042 = or(_T_2041, _T_2015) node _T_2043 = or(_T_2042, _T_2020) node _T_2044 = or(_T_2043, _T_2025) node _T_2045 = or(_T_2044, _T_2030) node _T_2046 = or(_T_2045, _T_2035) node _T_2047 = or(_T_2046, _T_2040) node _T_2048 = and(_T_2000, _T_2047) node _T_2049 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2050 = or(UInt<1>(0h0), _T_2049) node _T_2051 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2052 = cvt(_T_2051) node _T_2053 = and(_T_2052, asSInt(UInt<17>(0h10000))) node _T_2054 = asSInt(_T_2053) node _T_2055 = eq(_T_2054, asSInt(UInt<1>(0h0))) node _T_2056 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2057 = cvt(_T_2056) node _T_2058 = and(_T_2057, asSInt(UInt<29>(0h10000000))) node _T_2059 = asSInt(_T_2058) node _T_2060 = eq(_T_2059, asSInt(UInt<1>(0h0))) node _T_2061 = or(_T_2055, _T_2060) node _T_2062 = and(_T_2050, _T_2061) node _T_2063 = or(UInt<1>(0h0), _T_2048) node _T_2064 = or(_T_2063, _T_2062) node _T_2065 = and(_T_1999, _T_2064) node _T_2066 = asUInt(reset) node _T_2067 = eq(_T_2066, UInt<1>(0h0)) when _T_2067 : node _T_2068 = eq(_T_2065, UInt<1>(0h0)) when _T_2068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2065, UInt<1>(0h1), "") : assert_150 node _T_2069 = eq(io.in.c.bits.source, UInt<1>(0h0)) node _T_2070 = eq(io.in.c.bits.source, UInt<1>(0h1)) wire _WIRE_8 : UInt<1>[2] connect _WIRE_8[0], _T_2069 connect _WIRE_8[1], _T_2070 node _T_2071 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2072 = mux(_WIRE_8[0], _T_2071, UInt<1>(0h0)) node _T_2073 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2074 = or(_T_2072, _T_2073) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2074 node _T_2075 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2076 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2077 = and(_T_2075, _T_2076) node _T_2078 = or(UInt<1>(0h0), _T_2077) node _T_2079 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2080 = cvt(_T_2079) node _T_2081 = and(_T_2080, asSInt(UInt<14>(0h2000))) node _T_2082 = asSInt(_T_2081) node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0))) node _T_2084 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2085 = cvt(_T_2084) node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000))) node _T_2087 = asSInt(_T_2086) node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0))) node _T_2089 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2090 = cvt(_T_2089) node _T_2091 = and(_T_2090, asSInt(UInt<17>(0h10000))) node _T_2092 = asSInt(_T_2091) node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0))) node _T_2094 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2095 = cvt(_T_2094) node _T_2096 = and(_T_2095, asSInt(UInt<18>(0h2f000))) node _T_2097 = asSInt(_T_2096) node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0))) node _T_2099 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2100 = cvt(_T_2099) node _T_2101 = and(_T_2100, asSInt(UInt<17>(0h10000))) node _T_2102 = asSInt(_T_2101) node _T_2103 = eq(_T_2102, asSInt(UInt<1>(0h0))) node _T_2104 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2105 = cvt(_T_2104) node _T_2106 = and(_T_2105, asSInt(UInt<13>(0h1000))) node _T_2107 = asSInt(_T_2106) node _T_2108 = eq(_T_2107, asSInt(UInt<1>(0h0))) node _T_2109 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2110 = cvt(_T_2109) node _T_2111 = and(_T_2110, asSInt(UInt<17>(0h10000))) node _T_2112 = asSInt(_T_2111) node _T_2113 = eq(_T_2112, asSInt(UInt<1>(0h0))) node _T_2114 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2115 = cvt(_T_2114) node _T_2116 = and(_T_2115, asSInt(UInt<27>(0h4000000))) node _T_2117 = asSInt(_T_2116) node _T_2118 = eq(_T_2117, asSInt(UInt<1>(0h0))) node _T_2119 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2120 = cvt(_T_2119) node _T_2121 = and(_T_2120, asSInt(UInt<13>(0h1000))) node _T_2122 = asSInt(_T_2121) node _T_2123 = eq(_T_2122, asSInt(UInt<1>(0h0))) node _T_2124 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2125 = cvt(_T_2124) node _T_2126 = and(_T_2125, asSInt(UInt<29>(0h10000000))) node _T_2127 = asSInt(_T_2126) node _T_2128 = eq(_T_2127, asSInt(UInt<1>(0h0))) node _T_2129 = or(_T_2083, _T_2088) node _T_2130 = or(_T_2129, _T_2093) node _T_2131 = or(_T_2130, _T_2098) node _T_2132 = or(_T_2131, _T_2103) node _T_2133 = or(_T_2132, _T_2108) node _T_2134 = or(_T_2133, _T_2113) node _T_2135 = or(_T_2134, _T_2118) node _T_2136 = or(_T_2135, _T_2123) node _T_2137 = or(_T_2136, _T_2128) node _T_2138 = and(_T_2078, _T_2137) node _T_2139 = or(UInt<1>(0h0), _T_2138) node _T_2140 = and(_WIRE_9, _T_2139) node _T_2141 = asUInt(reset) node _T_2142 = eq(_T_2141, UInt<1>(0h0)) when _T_2142 : node _T_2143 = eq(_T_2140, UInt<1>(0h0)) when _T_2143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2140, UInt<1>(0h1), "") : assert_151 node _T_2144 = asUInt(reset) node _T_2145 = eq(_T_2144, UInt<1>(0h0)) when _T_2145 : node _T_2146 = eq(source_ok_2, UInt<1>(0h0)) when _T_2146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2147 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2148 = asUInt(reset) node _T_2149 = eq(_T_2148, UInt<1>(0h0)) when _T_2149 : node _T_2150 = eq(_T_2147, UInt<1>(0h0)) when _T_2150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2147, UInt<1>(0h1), "") : assert_153 node _T_2151 = asUInt(reset) node _T_2152 = eq(_T_2151, UInt<1>(0h0)) when _T_2152 : node _T_2153 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2154 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2155 = asUInt(reset) node _T_2156 = eq(_T_2155, UInt<1>(0h0)) when _T_2156 : node _T_2157 = eq(_T_2154, UInt<1>(0h0)) when _T_2157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2154, UInt<1>(0h1), "") : assert_155 node _T_2158 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2158 : node _T_2159 = asUInt(reset) node _T_2160 = eq(_T_2159, UInt<1>(0h0)) when _T_2160 : node _T_2161 = eq(address_ok_1, UInt<1>(0h0)) when _T_2161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2162 = asUInt(reset) node _T_2163 = eq(_T_2162, UInt<1>(0h0)) when _T_2163 : node _T_2164 = eq(source_ok_2, UInt<1>(0h0)) when _T_2164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2165 = asUInt(reset) node _T_2166 = eq(_T_2165, UInt<1>(0h0)) when _T_2166 : node _T_2167 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2168 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2169 = asUInt(reset) node _T_2170 = eq(_T_2169, UInt<1>(0h0)) when _T_2170 : node _T_2171 = eq(_T_2168, UInt<1>(0h0)) when _T_2171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2168, UInt<1>(0h1), "") : assert_159 node _T_2172 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2173 = asUInt(reset) node _T_2174 = eq(_T_2173, UInt<1>(0h0)) when _T_2174 : node _T_2175 = eq(_T_2172, UInt<1>(0h0)) when _T_2175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2172, UInt<1>(0h1), "") : assert_160 node _T_2176 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2176 : node _T_2177 = asUInt(reset) node _T_2178 = eq(_T_2177, UInt<1>(0h0)) when _T_2178 : node _T_2179 = eq(address_ok_1, UInt<1>(0h0)) when _T_2179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(source_ok_2, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2183 = asUInt(reset) node _T_2184 = eq(_T_2183, UInt<1>(0h0)) when _T_2184 : node _T_2185 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2186 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2187 = asUInt(reset) node _T_2188 = eq(_T_2187, UInt<1>(0h0)) when _T_2188 : node _T_2189 = eq(_T_2186, UInt<1>(0h0)) when _T_2189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2186, UInt<1>(0h1), "") : assert_164 node _T_2190 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2190 : node _T_2191 = asUInt(reset) node _T_2192 = eq(_T_2191, UInt<1>(0h0)) when _T_2192 : node _T_2193 = eq(address_ok_1, UInt<1>(0h0)) when _T_2193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2194 = asUInt(reset) node _T_2195 = eq(_T_2194, UInt<1>(0h0)) when _T_2195 : node _T_2196 = eq(source_ok_2, UInt<1>(0h0)) when _T_2196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2197 = asUInt(reset) node _T_2198 = eq(_T_2197, UInt<1>(0h0)) when _T_2198 : node _T_2199 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2200 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2201 = asUInt(reset) node _T_2202 = eq(_T_2201, UInt<1>(0h0)) when _T_2202 : node _T_2203 = eq(_T_2200, UInt<1>(0h0)) when _T_2203 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2200, UInt<1>(0h1), "") : assert_168 node _T_2204 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2205 = asUInt(reset) node _T_2206 = eq(_T_2205, UInt<1>(0h0)) when _T_2206 : node _T_2207 = eq(_T_2204, UInt<1>(0h0)) when _T_2207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2204, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : node _T_2210 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2210 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2211 = eq(a_first, UInt<1>(0h0)) node _T_2212 = and(io.in.a.valid, _T_2211) when _T_2212 : node _T_2213 = eq(io.in.a.bits.opcode, opcode) node _T_2214 = asUInt(reset) node _T_2215 = eq(_T_2214, UInt<1>(0h0)) when _T_2215 : node _T_2216 = eq(_T_2213, UInt<1>(0h0)) when _T_2216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2213, UInt<1>(0h1), "") : assert_171 node _T_2217 = eq(io.in.a.bits.param, param) node _T_2218 = asUInt(reset) node _T_2219 = eq(_T_2218, UInt<1>(0h0)) when _T_2219 : node _T_2220 = eq(_T_2217, UInt<1>(0h0)) when _T_2220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2217, UInt<1>(0h1), "") : assert_172 node _T_2221 = eq(io.in.a.bits.size, size) node _T_2222 = asUInt(reset) node _T_2223 = eq(_T_2222, UInt<1>(0h0)) when _T_2223 : node _T_2224 = eq(_T_2221, UInt<1>(0h0)) when _T_2224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2221, UInt<1>(0h1), "") : assert_173 node _T_2225 = eq(io.in.a.bits.source, source) node _T_2226 = asUInt(reset) node _T_2227 = eq(_T_2226, UInt<1>(0h0)) when _T_2227 : node _T_2228 = eq(_T_2225, UInt<1>(0h0)) when _T_2228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2225, UInt<1>(0h1), "") : assert_174 node _T_2229 = eq(io.in.a.bits.address, address) node _T_2230 = asUInt(reset) node _T_2231 = eq(_T_2230, UInt<1>(0h0)) when _T_2231 : node _T_2232 = eq(_T_2229, UInt<1>(0h0)) when _T_2232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2229, UInt<1>(0h1), "") : assert_175 node _T_2233 = and(io.in.a.ready, io.in.a.valid) node _T_2234 = and(_T_2233, a_first) when _T_2234 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2235 = eq(d_first, UInt<1>(0h0)) node _T_2236 = and(io.in.d.valid, _T_2235) when _T_2236 : node _T_2237 = eq(io.in.d.bits.opcode, opcode_1) node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : node _T_2240 = eq(_T_2237, UInt<1>(0h0)) when _T_2240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2237, UInt<1>(0h1), "") : assert_176 node _T_2241 = eq(io.in.d.bits.param, param_1) node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : node _T_2244 = eq(_T_2241, UInt<1>(0h0)) when _T_2244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2241, UInt<1>(0h1), "") : assert_177 node _T_2245 = eq(io.in.d.bits.size, size_1) node _T_2246 = asUInt(reset) node _T_2247 = eq(_T_2246, UInt<1>(0h0)) when _T_2247 : node _T_2248 = eq(_T_2245, UInt<1>(0h0)) when _T_2248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2245, UInt<1>(0h1), "") : assert_178 node _T_2249 = eq(io.in.d.bits.source, source_1) node _T_2250 = asUInt(reset) node _T_2251 = eq(_T_2250, UInt<1>(0h0)) when _T_2251 : node _T_2252 = eq(_T_2249, UInt<1>(0h0)) when _T_2252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2249, UInt<1>(0h1), "") : assert_179 node _T_2253 = eq(io.in.d.bits.sink, sink) node _T_2254 = asUInt(reset) node _T_2255 = eq(_T_2254, UInt<1>(0h0)) when _T_2255 : node _T_2256 = eq(_T_2253, UInt<1>(0h0)) when _T_2256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2253, UInt<1>(0h1), "") : assert_180 node _T_2257 = eq(io.in.d.bits.denied, denied) node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : node _T_2260 = eq(_T_2257, UInt<1>(0h0)) when _T_2260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2257, UInt<1>(0h1), "") : assert_181 node _T_2261 = and(io.in.d.ready, io.in.d.valid) node _T_2262 = and(_T_2261, d_first) when _T_2262 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2263 = eq(b_first, UInt<1>(0h0)) node _T_2264 = and(io.in.b.valid, _T_2263) when _T_2264 : node _T_2265 = eq(io.in.b.bits.opcode, opcode_2) node _T_2266 = asUInt(reset) node _T_2267 = eq(_T_2266, UInt<1>(0h0)) when _T_2267 : node _T_2268 = eq(_T_2265, UInt<1>(0h0)) when _T_2268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2265, UInt<1>(0h1), "") : assert_182 node _T_2269 = eq(io.in.b.bits.param, param_2) node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : node _T_2272 = eq(_T_2269, UInt<1>(0h0)) when _T_2272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2269, UInt<1>(0h1), "") : assert_183 node _T_2273 = eq(io.in.b.bits.size, size_2) node _T_2274 = asUInt(reset) node _T_2275 = eq(_T_2274, UInt<1>(0h0)) when _T_2275 : node _T_2276 = eq(_T_2273, UInt<1>(0h0)) when _T_2276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2273, UInt<1>(0h1), "") : assert_184 node _T_2277 = eq(io.in.b.bits.source, source_2) node _T_2278 = asUInt(reset) node _T_2279 = eq(_T_2278, UInt<1>(0h0)) when _T_2279 : node _T_2280 = eq(_T_2277, UInt<1>(0h0)) when _T_2280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2277, UInt<1>(0h1), "") : assert_185 node _T_2281 = eq(io.in.b.bits.address, address_1) node _T_2282 = asUInt(reset) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : node _T_2284 = eq(_T_2281, UInt<1>(0h0)) when _T_2284 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2281, UInt<1>(0h1), "") : assert_186 node _T_2285 = and(io.in.b.ready, io.in.b.valid) node _T_2286 = and(_T_2285, b_first) when _T_2286 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2287 = eq(c_first, UInt<1>(0h0)) node _T_2288 = and(io.in.c.valid, _T_2287) when _T_2288 : node _T_2289 = eq(io.in.c.bits.opcode, opcode_3) node _T_2290 = asUInt(reset) node _T_2291 = eq(_T_2290, UInt<1>(0h0)) when _T_2291 : node _T_2292 = eq(_T_2289, UInt<1>(0h0)) when _T_2292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2289, UInt<1>(0h1), "") : assert_187 node _T_2293 = eq(io.in.c.bits.param, param_3) node _T_2294 = asUInt(reset) node _T_2295 = eq(_T_2294, UInt<1>(0h0)) when _T_2295 : node _T_2296 = eq(_T_2293, UInt<1>(0h0)) when _T_2296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2293, UInt<1>(0h1), "") : assert_188 node _T_2297 = eq(io.in.c.bits.size, size_3) node _T_2298 = asUInt(reset) node _T_2299 = eq(_T_2298, UInt<1>(0h0)) when _T_2299 : node _T_2300 = eq(_T_2297, UInt<1>(0h0)) when _T_2300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2297, UInt<1>(0h1), "") : assert_189 node _T_2301 = eq(io.in.c.bits.source, source_3) node _T_2302 = asUInt(reset) node _T_2303 = eq(_T_2302, UInt<1>(0h0)) when _T_2303 : node _T_2304 = eq(_T_2301, UInt<1>(0h0)) when _T_2304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2301, UInt<1>(0h1), "") : assert_190 node _T_2305 = eq(io.in.c.bits.address, address_2) node _T_2306 = asUInt(reset) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) when _T_2307 : node _T_2308 = eq(_T_2305, UInt<1>(0h0)) when _T_2308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2305, UInt<1>(0h1), "") : assert_191 node _T_2309 = and(io.in.c.ready, io.in.c.valid) node _T_2310 = and(_T_2309, c_first) when _T_2310 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<2> connect a_set, UInt<2>(0h0) wire a_set_wo_ready : UInt<2> connect a_set_wo_ready, UInt<2>(0h0) wire a_opcodes_set : UInt<8> connect a_opcodes_set, UInt<8>(0h0) wire a_sizes_set : UInt<16> connect a_sizes_set, UInt<16>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2311 = and(io.in.a.valid, a_first_1) node _T_2312 = and(_T_2311, UInt<1>(0h1)) when _T_2312 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2313 = and(io.in.a.ready, io.in.a.valid) node _T_2314 = and(_T_2313, a_first_1) node _T_2315 = and(_T_2314, UInt<1>(0h1)) when _T_2315 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2316 = dshr(inflight, io.in.a.bits.source) node _T_2317 = bits(_T_2316, 0, 0) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) node _T_2319 = asUInt(reset) node _T_2320 = eq(_T_2319, UInt<1>(0h0)) when _T_2320 : node _T_2321 = eq(_T_2318, UInt<1>(0h0)) when _T_2321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2318, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<2> connect d_clr, UInt<2>(0h0) wire d_clr_wo_ready : UInt<2> connect d_clr_wo_ready, UInt<2>(0h0) wire d_opcodes_clr : UInt<8> connect d_opcodes_clr, UInt<8>(0h0) wire d_sizes_clr : UInt<16> connect d_sizes_clr, UInt<16>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2322 = and(io.in.d.valid, d_first_1) node _T_2323 = and(_T_2322, UInt<1>(0h1)) node _T_2324 = eq(d_release_ack, UInt<1>(0h0)) node _T_2325 = and(_T_2323, _T_2324) when _T_2325 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2326 = and(io.in.d.ready, io.in.d.valid) node _T_2327 = and(_T_2326, d_first_1) node _T_2328 = and(_T_2327, UInt<1>(0h1)) node _T_2329 = eq(d_release_ack, UInt<1>(0h0)) node _T_2330 = and(_T_2328, _T_2329) when _T_2330 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2331 = and(io.in.d.valid, d_first_1) node _T_2332 = and(_T_2331, UInt<1>(0h1)) node _T_2333 = eq(d_release_ack, UInt<1>(0h0)) node _T_2334 = and(_T_2332, _T_2333) when _T_2334 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2335 = dshr(inflight, io.in.d.bits.source) node _T_2336 = bits(_T_2335, 0, 0) node _T_2337 = or(_T_2336, same_cycle_resp) node _T_2338 = asUInt(reset) node _T_2339 = eq(_T_2338, UInt<1>(0h0)) when _T_2339 : node _T_2340 = eq(_T_2337, UInt<1>(0h0)) when _T_2340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2337, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2341 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2342 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2343 = or(_T_2341, _T_2342) node _T_2344 = asUInt(reset) node _T_2345 = eq(_T_2344, UInt<1>(0h0)) when _T_2345 : node _T_2346 = eq(_T_2343, UInt<1>(0h0)) when _T_2346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2343, UInt<1>(0h1), "") : assert_194 node _T_2347 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2348 = asUInt(reset) node _T_2349 = eq(_T_2348, UInt<1>(0h0)) when _T_2349 : node _T_2350 = eq(_T_2347, UInt<1>(0h0)) when _T_2350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2347, UInt<1>(0h1), "") : assert_195 else : node _T_2351 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2352 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2353 = or(_T_2351, _T_2352) node _T_2354 = asUInt(reset) node _T_2355 = eq(_T_2354, UInt<1>(0h0)) when _T_2355 : node _T_2356 = eq(_T_2353, UInt<1>(0h0)) when _T_2356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2353, UInt<1>(0h1), "") : assert_196 node _T_2357 = eq(io.in.d.bits.size, a_size_lookup) node _T_2358 = asUInt(reset) node _T_2359 = eq(_T_2358, UInt<1>(0h0)) when _T_2359 : node _T_2360 = eq(_T_2357, UInt<1>(0h0)) when _T_2360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2357, UInt<1>(0h1), "") : assert_197 node _T_2361 = and(io.in.d.valid, d_first_1) node _T_2362 = and(_T_2361, a_first_1) node _T_2363 = and(_T_2362, io.in.a.valid) node _T_2364 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2365 = and(_T_2363, _T_2364) node _T_2366 = eq(d_release_ack, UInt<1>(0h0)) node _T_2367 = and(_T_2365, _T_2366) when _T_2367 : node _T_2368 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2369 = or(_T_2368, io.in.a.ready) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(_T_2369, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2369, UInt<1>(0h1), "") : assert_198 node _T_2373 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2374 = orr(a_set_wo_ready) node _T_2375 = eq(_T_2374, UInt<1>(0h0)) node _T_2376 = or(_T_2373, _T_2375) node _T_2377 = asUInt(reset) node _T_2378 = eq(_T_2377, UInt<1>(0h0)) when _T_2378 : node _T_2379 = eq(_T_2376, UInt<1>(0h0)) when _T_2379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2376, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_112 node _T_2380 = orr(inflight) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) node _T_2382 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2383 = or(_T_2381, _T_2382) node _T_2384 = lt(watchdog, plusarg_reader.out) node _T_2385 = or(_T_2383, _T_2384) node _T_2386 = asUInt(reset) node _T_2387 = eq(_T_2386, UInt<1>(0h0)) when _T_2387 : node _T_2388 = eq(_T_2385, UInt<1>(0h0)) when _T_2388 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2385, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2389 = and(io.in.a.ready, io.in.a.valid) node _T_2390 = and(io.in.d.ready, io.in.d.valid) node _T_2391 = or(_T_2389, _T_2390) when _T_2391 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0) regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<2> connect c_set, UInt<2>(0h0) wire c_set_wo_ready : UInt<2> connect c_set_wo_ready, UInt<2>(0h0) wire c_opcodes_set : UInt<8> connect c_opcodes_set, UInt<8>(0h0) wire c_sizes_set : UInt<16> connect c_sizes_set, UInt<16>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2392 = and(io.in.c.valid, c_first_1) node _T_2393 = bits(io.in.c.bits.opcode, 2, 2) node _T_2394 = bits(io.in.c.bits.opcode, 1, 1) node _T_2395 = and(_T_2393, _T_2394) node _T_2396 = and(_T_2392, _T_2395) when _T_2396 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2397 = and(io.in.c.ready, io.in.c.valid) node _T_2398 = and(_T_2397, c_first_1) node _T_2399 = bits(io.in.c.bits.opcode, 2, 2) node _T_2400 = bits(io.in.c.bits.opcode, 1, 1) node _T_2401 = and(_T_2399, _T_2400) node _T_2402 = and(_T_2398, _T_2401) when _T_2402 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2403 = dshr(inflight_1, io.in.c.bits.source) node _T_2404 = bits(_T_2403, 0, 0) node _T_2405 = eq(_T_2404, UInt<1>(0h0)) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<2> connect d_clr_1, UInt<2>(0h0) wire d_clr_wo_ready_1 : UInt<2> connect d_clr_wo_ready_1, UInt<2>(0h0) wire d_opcodes_clr_1 : UInt<8> connect d_opcodes_clr_1, UInt<8>(0h0) wire d_sizes_clr_1 : UInt<16> connect d_sizes_clr_1, UInt<16>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2409 = and(io.in.d.valid, d_first_2) node _T_2410 = and(_T_2409, UInt<1>(0h1)) node _T_2411 = and(_T_2410, d_release_ack_1) when _T_2411 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2412 = and(io.in.d.ready, io.in.d.valid) node _T_2413 = and(_T_2412, d_first_2) node _T_2414 = and(_T_2413, UInt<1>(0h1)) node _T_2415 = and(_T_2414, d_release_ack_1) when _T_2415 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2416 = and(io.in.d.valid, d_first_2) node _T_2417 = and(_T_2416, UInt<1>(0h1)) node _T_2418 = and(_T_2417, d_release_ack_1) when _T_2418 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2419 = dshr(inflight_1, io.in.d.bits.source) node _T_2420 = bits(_T_2419, 0, 0) node _T_2421 = or(_T_2420, same_cycle_resp_1) node _T_2422 = asUInt(reset) node _T_2423 = eq(_T_2422, UInt<1>(0h0)) when _T_2423 : node _T_2424 = eq(_T_2421, UInt<1>(0h0)) when _T_2424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2421, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2425 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(_T_2425, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2425, UInt<1>(0h1), "") : assert_203 else : node _T_2429 = eq(io.in.d.bits.size, c_size_lookup) node _T_2430 = asUInt(reset) node _T_2431 = eq(_T_2430, UInt<1>(0h0)) when _T_2431 : node _T_2432 = eq(_T_2429, UInt<1>(0h0)) when _T_2432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2429, UInt<1>(0h1), "") : assert_204 node _T_2433 = and(io.in.d.valid, d_first_2) node _T_2434 = and(_T_2433, c_first_1) node _T_2435 = and(_T_2434, io.in.c.valid) node _T_2436 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2437 = and(_T_2435, _T_2436) node _T_2438 = and(_T_2437, d_release_ack_1) node _T_2439 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2440 = and(_T_2438, _T_2439) when _T_2440 : node _T_2441 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2442 = or(_T_2441, io.in.c.ready) node _T_2443 = asUInt(reset) node _T_2444 = eq(_T_2443, UInt<1>(0h0)) when _T_2444 : node _T_2445 = eq(_T_2442, UInt<1>(0h0)) when _T_2445 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2442, UInt<1>(0h1), "") : assert_205 node _T_2446 = orr(c_set_wo_ready) when _T_2446 : node _T_2447 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2448 = asUInt(reset) node _T_2449 = eq(_T_2448, UInt<1>(0h0)) when _T_2449 : node _T_2450 = eq(_T_2447, UInt<1>(0h0)) when _T_2450 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2447, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_113 node _T_2451 = orr(inflight_1) node _T_2452 = eq(_T_2451, UInt<1>(0h0)) node _T_2453 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2454 = or(_T_2452, _T_2453) node _T_2455 = lt(watchdog_1, plusarg_reader_1.out) node _T_2456 = or(_T_2454, _T_2455) node _T_2457 = asUInt(reset) node _T_2458 = eq(_T_2457, UInt<1>(0h0)) when _T_2458 : node _T_2459 = eq(_T_2456, UInt<1>(0h0)) when _T_2459 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2456, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2460 = and(io.in.c.ready, io.in.c.valid) node _T_2461 = and(io.in.d.ready, io.in.d.valid) node _T_2462 = or(_T_2460, _T_2461) when _T_2462 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2463 = and(io.in.d.ready, io.in.d.valid) node _T_2464 = and(_T_2463, d_first_3) node _T_2465 = bits(io.in.d.bits.opcode, 2, 2) node _T_2466 = bits(io.in.d.bits.opcode, 1, 1) node _T_2467 = eq(_T_2466, UInt<1>(0h0)) node _T_2468 = and(_T_2465, _T_2467) node _T_2469 = and(_T_2464, _T_2468) when _T_2469 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2470 = dshr(inflight_2, io.in.d.bits.sink) node _T_2471 = bits(_T_2470, 0, 0) node _T_2472 = eq(_T_2471, UInt<1>(0h0)) node _T_2473 = asUInt(reset) node _T_2474 = eq(_T_2473, UInt<1>(0h0)) when _T_2474 : node _T_2475 = eq(_T_2472, UInt<1>(0h0)) when _T_2475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2472, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2476 = and(io.in.e.ready, io.in.e.valid) node _T_2477 = and(_T_2476, UInt<1>(0h1)) node _T_2478 = and(_T_2477, UInt<1>(0h1)) when _T_2478 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2479 = or(d_set, inflight_2) node _T_2480 = dshr(_T_2479, io.in.e.bits.sink) node _T_2481 = bits(_T_2480, 0, 0) node _T_2482 = asUInt(reset) node _T_2483 = eq(_T_2482, UInt<1>(0h0)) when _T_2483 : node _T_2484 = eq(_T_2481, UInt<1>(0h0)) when _T_2484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2481, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8 extmodule plusarg_reader_114 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_115 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_56( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 \| _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 \| _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 \| _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 \| _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 \| _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 \| _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 \| _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 \| _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 \| _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 \| _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 \| _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 \| _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 \| _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 \| _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 \| _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 \| _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 \| _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 \| _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 \| _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 \| _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 \| _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 \| _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31] wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73] wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73] wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31] wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire source_ok_2 = _source_ok_WIRE_2_0 \| _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 \| _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 \| _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 \| _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 \| _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 \| _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 \| _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 \| _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 \| _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 \| _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 \| _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 \| _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire _T_2389 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2389; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2389; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2463 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2463; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2463; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2460 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2460; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2460; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T \| _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [15:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] a_set; // @[Monitor.scala:626:34] wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [15:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_21 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_22 = 2'h1 << _GEN_21; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2315 = _T_2389 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2315 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2315 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2315 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2315 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_2315 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [1:0] d_clr; // @[Monitor.scala:664:34] wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46] wire _T_2361 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_24 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_25 = 2'h1 << _GEN_24; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2361 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2330 = _T_2463 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2330 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2330 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2330 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [7:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [15:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 \| _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [1:0] c_set; // @[Monitor.scala:738:34] wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [15:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [1:0] _GEN_26 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_27 = 2'h1 << _GEN_26; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35] wire [1:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35] wire _T_2402 = _T_2460 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2402 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2402 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2402 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}] assign c_opcodes_set = _T_2402 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}] assign c_sizes_set = _T_2402 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T \| _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [1:0] d_clr_1; // @[Monitor.scala:774:34] wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2433 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2433 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35] wire _T_2415 = _T_2463 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2415 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2415 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2415 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [1:0] _inflight_T_3 = inflight_1 \| c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 \| c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 \| c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 \| _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2469 = _T_2463 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_28 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_28; // @[OneHot.scala:58:35] assign d_set = _T_2469 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2478 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_29 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_29; // @[OneHot.scala:58:35] assign e_clr = _T_2478 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_197 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_197( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_28 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_56 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_28 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h18), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _T_4 = eq(UInt<5>(0h1b), io.in.bits.egress_id) node _T_5 = or(_T, _T_1) node _T_6 = or(_T_5, _T_2) node _T_7 = or(_T_6, _T_3) node _T_8 = or(_T_7, _T_4) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = and(io.in.valid, _T_9) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_11, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0hb) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<3>(0h4) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h18), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<5>(0h1b), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<2>(0h3), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h18), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<5>(0h1b), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0hb)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_15 = and(io.in.ready, io.in.valid) node _T_16 = and(_T_15, io.in.bits.head) node _T_17 = and(_T_16, at_dest) when _T_17 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_18 = eq(UInt<4>(0hc), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_19 = eq(UInt<4>(0hd), io.in.bits.egress_id) when _T_19 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_20 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_21 = and(route_q.io.enq.valid, _T_20) node _T_22 = eq(_T_21, UInt<1>(0h0)) node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(_T_22, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_22, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_57 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_28 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_26 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_27 = and(vcalloc_q.io.enq.valid, _T_26) node _T_28 = eq(_T_27, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_10) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_12 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_28( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _GEN; // @[Decoupled.scala:51:35] wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h18; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h1E; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h1B; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_11 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h6 : 3'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h5 : 3'h0)} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_13 = {_route_buffer_io_enq_bits_flow_egress_node_T_11[3:2], _route_buffer_io_enq_bits_flow_egress_node_T_11[1:0] \| {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_3}}} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 4'h9 : 4'h0); // @[Mux.scala:30:73] assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 == 4'hB; // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_13 != 4'hB; // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_46 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_58 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_46( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_58 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_4 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>} regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock wire next_valid : UInt<1> connect next_valid, slot_valid wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop_out, slot_uop node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T) connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1 wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect next_uop, next_uop_out node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _killed_T_1 = neq(_killed_T, UInt<1>(0h0)) node killed = or(_killed_T_1, io.kill) connect io.valid, slot_valid connect io.out_uop, next_uop node _io_will_be_valid_T = eq(killed, UInt<1>(0h0)) node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T) connect io.will_be_valid, _io_will_be_valid_T_1 when io.kill : connect slot_valid, UInt<1>(0h0) else : when io.in_uop.valid : connect slot_valid, UInt<1>(0h1) else : when io.clear : connect slot_valid, UInt<1>(0h0) else : node _slot_valid_T = eq(killed, UInt<1>(0h0)) node _slot_valid_T_1 = and(next_valid, _slot_valid_T) connect slot_valid, _slot_valid_T_1 when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T = eq(slot_valid, UInt<1>(0h0)) node _T_1 = or(_T, io.clear) node _T_2 = or(_T_1, io.kill) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid \|\| io.clear \|\| io.kill)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert else : connect slot_uop, next_uop connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0) connect next_uop.iw_p1_speculative_child, UInt<1>(0h0) connect next_uop.iw_p2_speculative_child, UInt<1>(0h0) wire rebusied_prs1 : UInt<1> connect rebusied_prs1, UInt<1>(0h0) wire rebusied_prs2 : UInt<1> connect rebusied_prs2, UInt<1>(0h0) node rebusied = or(rebusied_prs1, rebusied_prs2) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1) when _T_6 : connect next_uop.prs1_busy, UInt<1>(0h0) node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p1_speculative_child_T_2 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1) wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_2 connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p1_bypass_hint_T_2 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1) wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_2 connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE node _T_7 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_8 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child) node _T_9 = neq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_7, _T_9) node _T_11 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0)) node _T_12 = and(_T_10, _T_11) when _T_12 : connect next_uop.prs1_busy, UInt<1>(0h1) connect rebusied_prs1, UInt<1>(0h1) node _T_13 = or(prs2_wakeups_0, prs2_wakeups_1) when _T_13 : connect next_uop.prs2_busy, UInt<1>(0h0) node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _next_uop_iw_p2_speculative_child_T_2 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1) wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3> connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_2 connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p2_bypass_hint_T_2 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1) wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_2 connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE node _T_14 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_15 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child) node _T_16 = neq(_T_15, UInt<1>(0h0)) node _T_17 = or(_T_14, _T_16) node _T_18 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0)) node _T_19 = and(_T_17, _T_18) when _T_19 : connect next_uop.prs2_busy, UInt<1>(0h1) connect rebusied_prs2, UInt<1>(0h1) node _T_20 = or(prs3_wakeups_0, prs3_wakeups_1) when _T_20 : connect next_uop.prs3_busy, UInt<1>(0h0) node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _next_uop_iw_p3_bypass_hint_T_2 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1) wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1> connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_2 connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE node _T_21 = eq(io.pred_wakeup_port.bits, slot_uop.ppred) node _T_22 = and(io.pred_wakeup_port.valid, _T_21) when _T_22 : connect next_uop.ppred_busy, UInt<1>(0h0) node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1) node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0)) node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4) node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h1)) node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0)) node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7) node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0)) node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T) node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0)) node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3) node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0)) node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0)) node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T) node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1)) node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0)) node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3) node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0)) node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0)) node _io_request_T_1 = and(slot_valid, _io_request_T) node _io_request_T_2 = or(iss_ready, agen_ready) node _io_request_T_3 = or(_io_request_T_2, dgen_ready) node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3) connect io.request, _io_request_T_4 connect io.iss_uop, slot_uop connect next_uop.iw_issued, UInt<1>(0h0) connect next_uop.iw_issued_partial_agen, UInt<1>(0h0) connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0) node _T_23 = eq(io.squash_grant, UInt<1>(0h0)) node _T_24 = and(io.grant, _T_23) when _T_24 : connect next_uop.iw_issued, UInt<1>(0h1) node _T_25 = and(slot_valid, slot_uop.iw_issued) when _T_25 : connect next_valid, rebusied	module IssueSlot_4( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc // @[issue-slot.scala:52:14] ); wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire rebusied_prs1 = 1'h0; // @[issue-slot.scala:92:31] wire rebusied_prs2 = 1'h0; // @[issue-slot.scala:93:31] wire rebusied = 1'h0; // @[issue-slot.scala:94:32] wire prs1_rebusys_0 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_0 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [2:0] io_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] io_child_rebusys = 3'h0; // @[issue-slot.scala:49:7] wire [2:0] next_uop_iw_p1_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] next_uop_iw_p2_speculative_child = 3'h0; // @[issue-slot.scala:59:28] wire [2:0] _next_uop_iw_p1_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p1_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_T_2 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _next_uop_iw_p2_speculative_child_WIRE = 3'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] wire _iss_ready_T_6 = slot_uop_prs3_busy; // @[issue-slot.scala:56:21, :136:131] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_283 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_527 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_283( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_527 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_11 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_22 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_11 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<5>(0h1b), io.in.bits.egress_id) node _T_1 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id) node _T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _T_4 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _T_5 = or(_T, _T_1) node _T_6 = or(_T_5, _T_2) node _T_7 = or(_T_6, _T_3) node _T_8 = or(_T_7, _T_4) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = and(io.in.valid, _T_9) node _T_11 = eq(_T_10, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_11, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<3>(0h4) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<3>(0h4) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h1b), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0h9), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0ha), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<2>(0h3), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h1b), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h18), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h12), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<5>(0h15), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h4)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] node _T_15 = and(io.in.ready, io.in.valid) node _T_16 = and(_T_15, io.in.bits.head) node _T_17 = and(_T_16, at_dest) when _T_17 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) node _T_18 = eq(UInt<3>(0h6), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_19 = eq(UInt<3>(0h7), io.in.bits.egress_id) when _T_19 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_20 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_21 = and(route_q.io.enq.valid, _T_20) node _T_22 = eq(_T_21, UInt<1>(0h0)) node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : node _T_25 = eq(_T_22, UInt<1>(0h0)) when _T_25 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_22, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_23 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_11 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] node _T_26 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_27 = and(vcalloc_q.io.enq.valid, _T_26) node _T_28 = eq(_T_27, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node _c_T_1 = cat(c_hi_1, _c_T) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_1) node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _c_T_3 = cat(c_hi_3, _c_T_2) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_10) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_12 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_11( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _GEN; // @[Decoupled.scala:51:35] wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h1B; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h18; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h1E; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_11 = {_route_buffer_io_enq_bits_flow_egress_node_id_T, {2'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0)} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hA : 4'h0); // @[Mux.scala:30:73] wire [2:0] _GEN_0 = {_route_buffer_io_enq_bits_flow_egress_node_T_11[2], _route_buffer_io_enq_bits_flow_egress_node_T_11[1:0] \| {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_3}}} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0); // @[Mux.scala:30:73] wire [3:0] _GEN_1 = {_route_buffer_io_enq_bits_flow_egress_node_T_11[3], _GEN_0}; // @[Mux.scala:30:73] assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_1 == 4'h4; // @[Decoupled.scala:51:35] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_1 != 4'h4; // @[Decoupled.scala:51:35] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_87 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_143 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_87( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_143 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_pbus : output auto : { coupler_to_device_named_uart_0_control_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out : { clock : Clock, reset : Reset}, flip pbus_clock_groups_in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst pbus_clock_groups of ClockGroupAggregator_pbus inst clockGroup of ClockGroup_1 inst fixedClockNode of FixedClockBroadcast_2 inst broadcast of BundleBridgeNexus_NoOutput_1 inst fixer of TLFIFOFixer_1 connect fixer.clock, childClock connect fixer.reset, childReset inst in_xbar of TLXbar_pbus_in_i1_o1_a29d64s7k1z3u connect in_xbar.clock, childClock connect in_xbar.reset, childReset inst out_xbar of TLXbar_pbus_out_i1_o2_a29d64s7k1z3u connect out_xbar.clock, childClock connect out_xbar.reset, childReset inst buffer of TLBuffer_a29d64s7k1z3u connect buffer.clock, childClock connect buffer.reset, childReset inst atomics of TLAtomicAutomata_pbus connect atomics.clock, childClock connect atomics.reset, childReset inst buffer_1 of TLBuffer_a29d64s7k1z3u_1 connect buffer_1.clock, childClock connect buffer_1.reset, childReset inst coupler_to_bootaddressreg of TLInterconnectCoupler_pbus_to_bootaddressreg connect coupler_to_bootaddressreg.clock, childClock connect coupler_to_bootaddressreg.reset, childReset inst coupler_to_device_named_uart_0 of TLInterconnectCoupler_pbus_to_device_named_uart_0 connect coupler_to_device_named_uart_0.clock, childClock connect coupler_to_device_named_uart_0.reset, childReset wire clockSinkNodeIn : { clock : Clock, reset : Reset} invalidate clockSinkNodeIn.reset invalidate clockSinkNodeIn.clock wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingOut.d.bits.corrupt invalidate bus_xingOut.d.bits.data invalidate bus_xingOut.d.bits.denied invalidate bus_xingOut.d.bits.sink invalidate bus_xingOut.d.bits.source invalidate bus_xingOut.d.bits.size invalidate bus_xingOut.d.bits.param invalidate bus_xingOut.d.bits.opcode invalidate bus_xingOut.d.valid invalidate bus_xingOut.d.ready invalidate bus_xingOut.a.bits.corrupt invalidate bus_xingOut.a.bits.data invalidate bus_xingOut.a.bits.mask invalidate bus_xingOut.a.bits.address invalidate bus_xingOut.a.bits.source invalidate bus_xingOut.a.bits.size invalidate bus_xingOut.a.bits.param invalidate bus_xingOut.a.bits.opcode invalidate bus_xingOut.a.valid invalidate bus_xingOut.a.ready wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate bus_xingIn.d.bits.corrupt invalidate bus_xingIn.d.bits.data invalidate bus_xingIn.d.bits.denied invalidate bus_xingIn.d.bits.sink invalidate bus_xingIn.d.bits.source invalidate bus_xingIn.d.bits.size invalidate bus_xingIn.d.bits.param invalidate bus_xingIn.d.bits.opcode invalidate bus_xingIn.d.valid invalidate bus_xingIn.d.ready invalidate bus_xingIn.a.bits.corrupt invalidate bus_xingIn.a.bits.data invalidate bus_xingIn.a.bits.mask invalidate bus_xingIn.a.bits.address invalidate bus_xingIn.a.bits.source invalidate bus_xingIn.a.bits.size invalidate bus_xingIn.a.bits.param invalidate bus_xingIn.a.bits.opcode invalidate bus_xingIn.a.valid invalidate bus_xingIn.a.ready connect bus_xingOut, bus_xingIn wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_8 connect monitor.clock, childClock connect monitor.reset, childReset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect clockGroup.auto.in, pbus_clock_groups.auto.out connect fixedClockNode.auto.anon_in, clockGroup.auto.out connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0 connect out_xbar.auto.anon_in, fixer.auto.anon_out connect atomics.auto.in, in_xbar.auto.anon_out connect coupler_to_bootaddressreg.auto.tl_in, out_xbar.auto.anon_out_0 connect coupler_to_device_named_uart_0.auto.tl_in, out_xbar.auto.anon_out_1 connect fixer.auto.anon_in, buffer.auto.out connect buffer.auto.in, atomics.auto.out connect in_xbar.auto.anon_in, buffer_1.auto.out connect buffer_1.auto.in, bus_xingOut connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.d, nodeIn.d connect nodeIn.a.bits, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.bits connect nodeIn.a.valid, coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.valid connect coupler_to_bootaddressreg.auto.fragmenter_anon_out.a.ready, nodeIn.a.ready connect bus_xingIn, auto.bus_xing_in connect pbus_clock_groups.auto.in, auto.pbus_clock_groups_in connect auto.fixedClockNode_anon_out, fixedClockNode.auto.anon_out_1 connect coupler_to_device_named_uart_0.auto.control_xing_out.d, auto.coupler_to_device_named_uart_0_control_xing_out.d connect auto.coupler_to_device_named_uart_0_control_xing_out.a.bits, coupler_to_device_named_uart_0.auto.control_xing_out.a.bits connect auto.coupler_to_device_named_uart_0_control_xing_out.a.valid, coupler_to_device_named_uart_0.auto.control_xing_out.a.valid connect coupler_to_device_named_uart_0.auto.control_xing_out.a.ready, auto.coupler_to_device_named_uart_0_control_xing_out.a.ready regreset bootAddrReg : UInt<64>, childClock, childReset, UInt<64>(0h80000000) node pad = or(bootAddrReg, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node bootAddrReg_lo_lo = cat(newBytes[1], newBytes[0]) node bootAddrReg_lo_hi = cat(newBytes[3], newBytes[2]) node bootAddrReg_lo = cat(bootAddrReg_lo_hi, bootAddrReg_lo_lo) node bootAddrReg_hi_lo = cat(newBytes[5], newBytes[4]) node bootAddrReg_hi_hi = cat(newBytes[7], newBytes[6]) node bootAddrReg_hi = cat(bootAddrReg_hi_hi, bootAddrReg_hi_lo) node _bootAddrReg_T = cat(bootAddrReg_hi, bootAddrReg_lo) connect bootAddrReg, _bootAddrReg_T wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[8] wire out_wivalid : UInt<1>[8] wire out_roready : UInt<1>[8] wire out_woready : UInt<1>[8] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 7, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 7, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 7, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 7, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready when out_f_woready : connect newBytes[0], _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_8 = bits(_out_T_7, 7, 0) node _out_rimask_T_1 = bits(out_frontMask, 15, 8) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 15, 8) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 15, 8) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 15, 8) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_9 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_1 when out_f_woready_1 : connect newBytes[1], _out_T_9 node _out_T_10 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_11 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_12 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_13 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_8, UInt<8>(0h0)) node out_prepend = cat(oldBytes[1], _out_prepend_T) node _out_T_14 = or(out_prepend, UInt<16>(0h0)) node _out_T_15 = bits(_out_T_14, 15, 0) node _out_rimask_T_2 = bits(out_frontMask, 23, 16) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 23, 16) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 23, 16) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 23, 16) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_16 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_2 when out_f_woready_2 : connect newBytes[2], _out_T_16 node _out_T_17 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_18 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_19 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_20 = eq(out_womask_2, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_15, UInt<16>(0h0)) node out_prepend_1 = cat(oldBytes[2], _out_prepend_T_1) node _out_T_21 = or(out_prepend_1, UInt<24>(0h0)) node _out_T_22 = bits(_out_T_21, 23, 0) node _out_rimask_T_3 = bits(out_frontMask, 31, 24) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 31, 24) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 31, 24) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 31, 24) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_23 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_3 when out_f_woready_3 : connect newBytes[3], _out_T_23 node _out_T_24 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_25 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_26 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_27 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_22, UInt<24>(0h0)) node out_prepend_2 = cat(oldBytes[3], _out_prepend_T_2) node _out_T_28 = or(out_prepend_2, UInt<32>(0h0)) node _out_T_29 = bits(_out_T_28, 31, 0) node _out_rimask_T_4 = bits(out_frontMask, 39, 32) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 39, 32) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 39, 32) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 39, 32) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_30 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_4 when out_f_woready_4 : connect newBytes[4], _out_T_30 node _out_T_31 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_29, UInt<32>(0h0)) node out_prepend_3 = cat(oldBytes[4], _out_prepend_T_3) node _out_T_35 = or(out_prepend_3, UInt<40>(0h0)) node _out_T_36 = bits(_out_T_35, 39, 0) node _out_rimask_T_5 = bits(out_frontMask, 47, 40) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 47, 40) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 47, 40) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 47, 40) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_37 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_5 when out_f_woready_5 : connect newBytes[5], _out_T_37 node _out_T_38 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_39 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_40 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_41 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_36, UInt<40>(0h0)) node out_prepend_4 = cat(oldBytes[5], _out_prepend_T_4) node _out_T_42 = or(out_prepend_4, UInt<48>(0h0)) node _out_T_43 = bits(_out_T_42, 47, 0) node _out_rimask_T_6 = bits(out_frontMask, 55, 48) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 55, 48) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 55, 48) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 55, 48) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_44 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_6 when out_f_woready_6 : connect newBytes[6], _out_T_44 node _out_T_45 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_46 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_47 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_48 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_43, UInt<48>(0h0)) node out_prepend_5 = cat(oldBytes[6], _out_prepend_T_5) node _out_T_49 = or(out_prepend_5, UInt<56>(0h0)) node _out_T_50 = bits(_out_T_49, 55, 0) node _out_rimask_T_7 = bits(out_frontMask, 63, 56) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 63, 56) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 63, 56) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 63, 56) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_51 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_7 when out_f_woready_7 : connect newBytes[7], _out_T_51 node _out_T_52 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_53 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_54 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_55 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_50, UInt<56>(0h0)) node out_prepend_6 = cat(oldBytes[7], _out_prepend_T_6) node _out_T_56 = or(out_prepend_6, UInt<64>(0h0)) node _out_T_57 = bits(_out_T_56, 63, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[7], _out_rifireMux_T_3 connect out_rivalid[6], _out_rifireMux_T_3 connect out_rivalid[5], _out_rifireMux_T_3 connect out_rivalid[4], _out_rifireMux_T_3 connect out_rivalid[3], _out_rifireMux_T_3 connect out_rivalid[2], _out_rifireMux_T_3 connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[7], _out_wifireMux_T_4 connect out_wivalid[6], _out_wifireMux_T_4 connect out_wivalid[5], _out_wifireMux_T_4 connect out_wivalid[4], _out_wifireMux_T_4 connect out_wivalid[3], _out_wifireMux_T_4 connect out_wivalid[2], _out_wifireMux_T_4 connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[7], _out_rofireMux_T_3 connect out_roready[6], _out_rofireMux_T_3 connect out_roready[5], _out_rofireMux_T_3 connect out_roready[4], _out_rofireMux_T_3 connect out_roready[3], _out_rofireMux_T_3 connect out_roready[2], _out_rofireMux_T_3 connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[7], _out_wofireMux_T_4 connect out_woready[6], _out_wofireMux_T_4 connect out_woready[5], _out_wofireMux_T_4 connect out_woready[4], _out_wofireMux_T_4 connect out_woready[3], _out_wofireMux_T_4 connect out_woready[2], _out_wofireMux_T_4 connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<64>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_57 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<13>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<13>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect childClock, clockSinkNodeIn.clock connect childReset, clockSinkNodeIn.reset connect clock, clockSinkNodeIn.clock connect reset, clockSinkNodeIn.reset	module PeripheryBus_pbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_device_named_uart_0_control_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_device_named_uart_0_control_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_device_named_uart_0_control_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_pbus_clock_groups_in_member_pbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_woready_7; // @[RegisterRouter.scala:87:24] wire _coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_param; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_size; // @[LazyScope.scala:98:27] wire [10:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_source; // @[LazyScope.scala:98:27] wire [12:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_fragmenter_anon_out_d_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootaddressreg_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootaddressreg_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _buffer_1_auto_out_a_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_out_a_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_out_a_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_1_auto_out_a_bits_source; // @[Buffer.scala:75:28] wire [28:0] _buffer_1_auto_out_a_bits_address; // @[Buffer.scala:75:28] wire [7:0] _buffer_1_auto_out_a_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_1_auto_out_a_bits_data; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_1_auto_out_d_ready; // @[Buffer.scala:75:28] wire _atomics_auto_in_a_ready; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [1:0] _atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28] wire [28:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28] wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_in_a_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_in_d_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_in_d_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_in_d_bits_source; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_in_d_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [28:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [12:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] reg [63:0] pad; // @[BootAddrReg.scala:27:34] wire in_bits_read = _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_1 = _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_address[11:3] == 9'h0; // @[RegisterRouter.scala:75:19, :87:24] wire valids_0 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire valids_1 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire valids_2 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire valids_3 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire valids_4 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire valids_5 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire valids_6 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire valids_7 = out_woready_7 & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_mask[7]; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_valid & _coupler_to_bootaddressreg_auto_fragmenter_anon_out_d_ready & ~in_bits_read & _out_T_1; // @[RegisterRouter.scala:74:36, :87:24] wire [2:0] nodeIn_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] always @(posedge _fixedClockNode_auto_anon_out_0_clock) begin // @[ClockGroup.scala:115:114] if (_fixedClockNode_auto_anon_out_0_reset) // @[ClockGroup.scala:115:114] pad <= 64'h80000000; // @[BootAddrReg.scala:27:34] else if (valids_0 \| valids_1 \| valids_2 \| valids_3 \| valids_4 \| valids_5 \| valids_6 \| valids_7) // @[RegisterRouter.scala:87:24] pad <= {valids_7 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[63:56] : pad[63:56], valids_6 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[55:48] : pad[55:48], valids_5 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[47:40] : pad[47:40], valids_4 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[39:32] : pad[39:32], valids_3 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[31:24] : pad[31:24], valids_2 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[23:16] : pad[23:16], valids_1 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[15:8] : pad[15:8], valids_0 ? _coupler_to_bootaddressreg_auto_fragmenter_anon_out_a_bits_data[7:0] : pad[7:0]}; // @[BootAddrReg.scala:27:34] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_10 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg	module AsyncResetRegVec_w1_i0_10( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset // @[AsyncResetReg.scala:56:7] ); wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7] wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_2 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_return : UInt<10>, vc_free : UInt<10>}} wire _in_flight_WIRE : UInt<1>[10] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) connect _in_flight_WIRE[8], UInt<1>(0h0) connect _in_flight_WIRE[9], UInt<1>(0h0) regreset in_flight : UInt<1>[10], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_33 = and(_T_31, _T_32) node _T_34 = or(_T_12, _T_19) node _T_35 = or(_T_34, _T_26) node _T_36 = or(_T_35, _T_33) node _T_37 = or(_T_5, _T_36) node _T_38 = asUInt(reset) node _T_39 = eq(_T_38, UInt<1>(0h0)) when _T_39 : node _T_40 = eq(_T_37, UInt<1>(0h0)) when _T_40 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_37, UInt<1>(0h1), "") : assert_1 node _T_41 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_43 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_50 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_55 = and(_T_53, _T_54) node _T_56 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_57 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_62 = and(_T_60, _T_61) node _T_63 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_64 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_71 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_76 = and(_T_74, _T_75) node _T_77 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_78 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_79 = and(_T_77, _T_78) node _T_80 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_81 = and(_T_79, _T_80) node _T_82 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_83 = and(_T_81, _T_82) node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_85 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_86 = and(_T_84, _T_85) node _T_87 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_88 = and(_T_86, _T_87) node _T_89 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_90 = and(_T_88, _T_89) node _T_91 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_92 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_93 = and(_T_91, _T_92) node _T_94 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2)) node _T_95 = and(_T_93, _T_94) node _T_96 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_97 = and(_T_95, _T_96) node _T_98 = or(_T_48, _T_55) node _T_99 = or(_T_98, _T_62) node _T_100 = or(_T_99, _T_69) node _T_101 = or(_T_100, _T_76) node _T_102 = or(_T_101, _T_83) node _T_103 = or(_T_102, _T_90) node _T_104 = or(_T_103, _T_97) node _T_105 = or(_T_41, _T_104) node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_T_105, UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_105, UInt<1>(0h1), "") : assert_2 node _T_109 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_110 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_111 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_112 = and(_T_110, _T_111) node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_114 = and(_T_112, _T_113) node _T_115 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_116 = and(_T_114, _T_115) node _T_117 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_118 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_121 = and(_T_119, _T_120) node _T_122 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_123 = and(_T_121, _T_122) node _T_124 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_125 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_126 = and(_T_124, _T_125) node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_132 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_139 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_142 = and(_T_140, _T_141) node _T_143 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_144 = and(_T_142, _T_143) node _T_145 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_146 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_149 = and(_T_147, _T_148) node _T_150 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_151 = and(_T_149, _T_150) node _T_152 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_153 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_156 = and(_T_154, _T_155) node _T_157 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_158 = and(_T_156, _T_157) node _T_159 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_160 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_165 = and(_T_163, _T_164) node _T_166 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_167 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_170 = and(_T_168, _T_169) node _T_171 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_172 = and(_T_170, _T_171) node _T_173 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_174 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_177 = and(_T_175, _T_176) node _T_178 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_179 = and(_T_177, _T_178) node _T_180 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_181 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_184 = and(_T_182, _T_183) node _T_185 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_188 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_191 = and(_T_189, _T_190) node _T_192 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_193 = and(_T_191, _T_192) node _T_194 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_195 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_198 = and(_T_196, _T_197) node _T_199 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_200 = and(_T_198, _T_199) node _T_201 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_202 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_205 = and(_T_203, _T_204) node _T_206 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_207 = and(_T_205, _T_206) node _T_208 = or(_T_116, _T_123) node _T_209 = or(_T_208, _T_130) node _T_210 = or(_T_209, _T_137) node _T_211 = or(_T_210, _T_144) node _T_212 = or(_T_211, _T_151) node _T_213 = or(_T_212, _T_158) node _T_214 = or(_T_213, _T_165) node _T_215 = or(_T_214, _T_172) node _T_216 = or(_T_215, _T_179) node _T_217 = or(_T_216, _T_186) node _T_218 = or(_T_217, _T_193) node _T_219 = or(_T_218, _T_200) node _T_220 = or(_T_219, _T_207) node _T_221 = or(_T_109, _T_220) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_221, UInt<1>(0h1), "") : assert_3 node _T_225 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_226 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_227 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_230 = and(_T_228, _T_229) node _T_231 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_234 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_235 = and(_T_233, _T_234) node _T_236 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_239 = and(_T_237, _T_238) node _T_240 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_241 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_242 = and(_T_240, _T_241) node _T_243 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_244 = and(_T_242, _T_243) node _T_245 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_246 = and(_T_244, _T_245) node _T_247 = or(_T_232, _T_239) node _T_248 = or(_T_247, _T_246) node _T_249 = or(_T_225, _T_248) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_249, UInt<1>(0h1), "") : assert_4 node _T_253 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_255 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_256 = and(_T_254, _T_255) node _T_257 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_258 = and(_T_256, _T_257) node _T_259 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_262 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_263 = and(_T_261, _T_262) node _T_264 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_269 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_272 = and(_T_270, _T_271) node _T_273 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_276 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_277 = and(_T_275, _T_276) node _T_278 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_279 = and(_T_277, _T_278) node _T_280 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_281 = and(_T_279, _T_280) node _T_282 = or(_T_260, _T_267) node _T_283 = or(_T_282, _T_274) node _T_284 = or(_T_283, _T_281) node _T_285 = or(_T_253, _T_284) node _T_286 = asUInt(reset) node _T_287 = eq(_T_286, UInt<1>(0h0)) when _T_287 : node _T_288 = eq(_T_285, UInt<1>(0h0)) when _T_288 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_285, UInt<1>(0h1), "") : assert_5 node _T_289 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_290 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_291 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_292 = and(_T_290, _T_291) node _T_293 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_294 = and(_T_292, _T_293) node _T_295 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_298 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_301 = and(_T_299, _T_300) node _T_302 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_303 = and(_T_301, _T_302) node _T_304 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_305 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_306 = and(_T_304, _T_305) node _T_307 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_308 = and(_T_306, _T_307) node _T_309 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_310 = and(_T_308, _T_309) node _T_311 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_312 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_313 = and(_T_311, _T_312) node _T_314 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_315 = and(_T_313, _T_314) node _T_316 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_317 = and(_T_315, _T_316) node _T_318 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_319 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_320 = and(_T_318, _T_319) node _T_321 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_322 = and(_T_320, _T_321) node _T_323 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_326 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_329 = and(_T_327, _T_328) node _T_330 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_331 = and(_T_329, _T_330) node _T_332 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_333 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_338 = and(_T_336, _T_337) node _T_339 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_340 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_341 = and(_T_339, _T_340) node _T_342 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_345 = and(_T_343, _T_344) node _T_346 = or(_T_296, _T_303) node _T_347 = or(_T_346, _T_310) node _T_348 = or(_T_347, _T_317) node _T_349 = or(_T_348, _T_324) node _T_350 = or(_T_349, _T_331) node _T_351 = or(_T_350, _T_338) node _T_352 = or(_T_351, _T_345) node _T_353 = or(_T_289, _T_352) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_353, UInt<1>(0h1), "") : assert_6 node _T_357 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_358 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_359 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_360 = and(_T_358, _T_359) node _T_361 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_362 = and(_T_360, _T_361) node _T_363 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_364 = and(_T_362, _T_363) node _T_365 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_366 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_367 = and(_T_365, _T_366) node _T_368 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_369 = and(_T_367, _T_368) node _T_370 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_371 = and(_T_369, _T_370) node _T_372 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7)) node _T_373 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_374 = and(_T_372, _T_373) node _T_375 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_376 = and(_T_374, _T_375) node _T_377 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_378 = and(_T_376, _T_377) node _T_379 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_380 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_381 = and(_T_379, _T_380) node _T_382 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_383 = and(_T_381, _T_382) node _T_384 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_385 = and(_T_383, _T_384) node _T_386 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_387 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_388 = and(_T_386, _T_387) node _T_389 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_390 = and(_T_388, _T_389) node _T_391 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_392 = and(_T_390, _T_391) node _T_393 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_394 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_395 = and(_T_393, _T_394) node _T_396 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_397 = and(_T_395, _T_396) node _T_398 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_399 = and(_T_397, _T_398) node _T_400 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_401 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_402 = and(_T_400, _T_401) node _T_403 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_404 = and(_T_402, _T_403) node _T_405 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_406 = and(_T_404, _T_405) node _T_407 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_408 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_411 = and(_T_409, _T_410) node _T_412 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_413 = and(_T_411, _T_412) node _T_414 = or(_T_364, _T_371) node _T_415 = or(_T_414, _T_378) node _T_416 = or(_T_415, _T_385) node _T_417 = or(_T_416, _T_392) node _T_418 = or(_T_417, _T_399) node _T_419 = or(_T_418, _T_406) node _T_420 = or(_T_419, _T_413) node _T_421 = or(_T_357, _T_420) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_421, UInt<1>(0h1), "") : assert_7 node _T_425 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_426 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_427 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_428 = and(_T_426, _T_427) node _T_429 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_430 = and(_T_428, _T_429) node _T_431 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_434 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_435 = and(_T_433, _T_434) node _T_436 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_437 = and(_T_435, _T_436) node _T_438 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(_T_432, _T_439) node _T_441 = or(_T_425, _T_440) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_441, UInt<1>(0h1), "") : assert_8 node _T_445 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_446 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_447 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_448 = and(_T_446, _T_447) node _T_449 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_452 = and(_T_450, _T_451) node _T_453 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_454 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_455 = and(_T_453, _T_454) node _T_456 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_457 = and(_T_455, _T_456) node _T_458 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_461 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_462 = and(_T_460, _T_461) node _T_463 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_464 = and(_T_462, _T_463) node _T_465 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_466 = and(_T_464, _T_465) node _T_467 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_468 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_469 = and(_T_467, _T_468) node _T_470 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_473 = and(_T_471, _T_472) node _T_474 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_475 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_476 = and(_T_474, _T_475) node _T_477 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_480 = and(_T_478, _T_479) node _T_481 = or(_T_452, _T_459) node _T_482 = or(_T_481, _T_466) node _T_483 = or(_T_482, _T_473) node _T_484 = or(_T_483, _T_480) node _T_485 = or(_T_445, _T_484) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_9 assert(clock, _T_485, UInt<1>(0h1), "") : assert_9 node _T_489 = neq(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h9)) node _T_490 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_491 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_492 = and(_T_490, _T_491) node _T_493 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_496 = and(_T_494, _T_495) node _T_497 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_498 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_499 = and(_T_497, _T_498) node _T_500 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_503 = and(_T_501, _T_502) node _T_504 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_505 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_506 = and(_T_504, _T_505) node _T_507 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_510 = and(_T_508, _T_509) node _T_511 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_512 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_513 = and(_T_511, _T_512) node _T_514 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_517 = and(_T_515, _T_516) node _T_518 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_519 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_520 = and(_T_518, _T_519) node _T_521 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_522 = and(_T_520, _T_521) node _T_523 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_524 = and(_T_522, _T_523) node _T_525 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_526 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_527 = and(_T_525, _T_526) node _T_528 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_529 = and(_T_527, _T_528) node _T_530 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_531 = and(_T_529, _T_530) node _T_532 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_533 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_534 = and(_T_532, _T_533) node _T_535 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_536 = and(_T_534, _T_535) node _T_537 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_538 = and(_T_536, _T_537) node _T_539 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_540 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_541 = and(_T_539, _T_540) node _T_542 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_545 = and(_T_543, _T_544) node _T_546 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_547 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_548 = and(_T_546, _T_547) node _T_549 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) node _T_551 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_552 = and(_T_550, _T_551) node _T_553 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1)) node _T_554 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_555 = and(_T_553, _T_554) node _T_556 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_557 = and(_T_555, _T_556) node _T_558 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2)) node _T_559 = and(_T_557, _T_558) node _T_560 = or(_T_496, _T_503) node _T_561 = or(_T_560, _T_510) node _T_562 = or(_T_561, _T_517) node _T_563 = or(_T_562, _T_524) node _T_564 = or(_T_563, _T_531) node _T_565 = or(_T_564, _T_538) node _T_566 = or(_T_565, _T_545) node _T_567 = or(_T_566, _T_552) node _T_568 = or(_T_567, _T_559) node _T_569 = or(_T_489, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_10 assert(clock, _T_569, UInt<1>(0h1), "") : assert_10	module NoCMonitor_2( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] reg in_flight_8; // @[Monitor.scala:16:26] reg in_flight_9; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_39 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_49 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_39( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_49 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_9 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h3)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_24 = shr(io.in.a.bits.source, 2) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_37, _T_42) node _T_74 = or(_T_73, _T_47) node _T_75 = or(_T_74, _T_52) node _T_76 = or(_T_75, _T_57) node _T_77 = or(_T_76, _T_62) node _T_78 = or(_T_77, _T_67) node _T_79 = or(_T_78, _T_72) node _T_80 = and(_T_32, _T_79) node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_82 = or(UInt<1>(0h0), _T_81) node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_84 = cvt(_T_83) node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000))) node _T_86 = asSInt(_T_85) node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0))) node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_89 = cvt(_T_88) node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000))) node _T_91 = asSInt(_T_90) node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = or(_T_87, _T_92) node _T_94 = and(_T_82, _T_93) node _T_95 = or(UInt<1>(0h0), _T_80) node _T_96 = or(_T_95, _T_94) node _T_97 = and(_T_31, _T_96) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_97, UInt<1>(0h1), "") : assert_2 node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_103 = and(_T_101, _T_102) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_151 = cvt(_T_150) node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000))) node _T_153 = asSInt(_T_152) node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0))) node _T_155 = or(_T_109, _T_114) node _T_156 = or(_T_155, _T_119) node _T_157 = or(_T_156, _T_124) node _T_158 = or(_T_157, _T_129) node _T_159 = or(_T_158, _T_134) node _T_160 = or(_T_159, _T_139) node _T_161 = or(_T_160, _T_144) node _T_162 = or(_T_161, _T_149) node _T_163 = or(_T_162, _T_154) node _T_164 = and(_T_104, _T_163) node _T_165 = or(UInt<1>(0h0), _T_164) node _T_166 = and(UInt<1>(0h0), _T_165) node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(_T_166, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_166, UInt<1>(0h1), "") : assert_3 node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_173 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_173, UInt<1>(0h1), "") : assert_5 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(is_aligned, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_180, UInt<1>(0h1), "") : assert_7 node _T_184 = not(io.in.a.bits.mask) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_185, UInt<1>(0h1), "") : assert_8 node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_189, UInt<1>(0h1), "") : assert_9 node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_193 : node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_197 = shr(io.in.a.bits.source, 2) node _T_198 = eq(_T_197, UInt<1>(0h0)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_2) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_202 = and(_T_200, _T_201) node _T_203 = and(_T_196, _T_202) node _T_204 = or(UInt<1>(0h0), _T_203) node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = or(_T_210, _T_215) node _T_247 = or(_T_246, _T_220) node _T_248 = or(_T_247, _T_225) node _T_249 = or(_T_248, _T_230) node _T_250 = or(_T_249, _T_235) node _T_251 = or(_T_250, _T_240) node _T_252 = or(_T_251, _T_245) node _T_253 = and(_T_205, _T_252) node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_255 = or(UInt<1>(0h0), _T_254) node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = or(_T_260, _T_265) node _T_267 = and(_T_255, _T_266) node _T_268 = or(UInt<1>(0h0), _T_253) node _T_269 = or(_T_268, _T_267) node _T_270 = and(_T_204, _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_270, UInt<1>(0h1), "") : assert_10 node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _T_277 = or(UInt<1>(0h0), _T_276) node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = or(_T_282, _T_287) node _T_329 = or(_T_328, _T_292) node _T_330 = or(_T_329, _T_297) node _T_331 = or(_T_330, _T_302) node _T_332 = or(_T_331, _T_307) node _T_333 = or(_T_332, _T_312) node _T_334 = or(_T_333, _T_317) node _T_335 = or(_T_334, _T_322) node _T_336 = or(_T_335, _T_327) node _T_337 = and(_T_277, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = and(UInt<1>(0h0), _T_338) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_339, UInt<1>(0h1), "") : assert_11 node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_346 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_346, UInt<1>(0h1), "") : assert_13 node _T_350 = asUInt(reset) node _T_351 = eq(_T_350, UInt<1>(0h0)) when _T_351 : node _T_352 = eq(is_aligned, UInt<1>(0h0)) when _T_352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_354 = asUInt(reset) node _T_355 = eq(_T_354, UInt<1>(0h0)) when _T_355 : node _T_356 = eq(_T_353, UInt<1>(0h0)) when _T_356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_353, UInt<1>(0h1), "") : assert_15 node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_358 = asUInt(reset) node _T_359 = eq(_T_358, UInt<1>(0h0)) when _T_359 : node _T_360 = eq(_T_357, UInt<1>(0h0)) when _T_360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_357, UInt<1>(0h1), "") : assert_16 node _T_361 = not(io.in.a.bits.mask) node _T_362 = eq(_T_361, UInt<1>(0h0)) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_362, UInt<1>(0h1), "") : assert_17 node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_366, UInt<1>(0h1), "") : assert_18 node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_370 : node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_374 = shr(io.in.a.bits.source, 2) node _T_375 = eq(_T_374, UInt<1>(0h0)) node _T_376 = leq(UInt<1>(0h0), uncommonBits_3) node _T_377 = and(_T_375, _T_376) node _T_378 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_379 = and(_T_377, _T_378) node _T_380 = and(_T_373, _T_379) node _T_381 = or(UInt<1>(0h0), _T_380) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_381, UInt<1>(0h1), "") : assert_19 node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = and(_T_388, _T_393) node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_397 = and(_T_395, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_430 = cvt(_T_429) node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000))) node _T_432 = asSInt(_T_431) node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0))) node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = or(_T_403, _T_408) node _T_445 = or(_T_444, _T_413) node _T_446 = or(_T_445, _T_418) node _T_447 = or(_T_446, _T_423) node _T_448 = or(_T_447, _T_428) node _T_449 = or(_T_448, _T_433) node _T_450 = or(_T_449, _T_438) node _T_451 = or(_T_450, _T_443) node _T_452 = and(_T_398, _T_451) node _T_453 = or(UInt<1>(0h0), _T_394) node _T_454 = or(_T_453, _T_452) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_454, UInt<1>(0h1), "") : assert_20 node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(is_aligned, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_464, UInt<1>(0h1), "") : assert_23 node _T_468 = eq(io.in.a.bits.mask, mask) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_468, UInt<1>(0h1), "") : assert_24 node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_472, UInt<1>(0h1), "") : assert_25 node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_476 : node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_479 = and(_T_477, _T_478) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_480 = shr(io.in.a.bits.source, 2) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = leq(UInt<1>(0h0), uncommonBits_4) node _T_483 = and(_T_481, _T_482) node _T_484 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_485 = and(_T_483, _T_484) node _T_486 = and(_T_479, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_500 = and(_T_498, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_518 = cvt(_T_517) node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000))) node _T_520 = asSInt(_T_519) node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0))) node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_523 = cvt(_T_522) node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000))) node _T_525 = asSInt(_T_524) node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0))) node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_533 = cvt(_T_532) node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000))) node _T_535 = asSInt(_T_534) node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0))) node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = or(_T_506, _T_511) node _T_543 = or(_T_542, _T_516) node _T_544 = or(_T_543, _T_521) node _T_545 = or(_T_544, _T_526) node _T_546 = or(_T_545, _T_531) node _T_547 = or(_T_546, _T_536) node _T_548 = or(_T_547, _T_541) node _T_549 = and(_T_501, _T_548) node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_497) node _T_558 = or(_T_557, _T_549) node _T_559 = or(_T_558, _T_556) node _T_560 = and(_T_487, _T_559) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_560, UInt<1>(0h1), "") : assert_26 node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(is_aligned, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_570, UInt<1>(0h1), "") : assert_29 node _T_574 = eq(io.in.a.bits.mask, mask) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_574, UInt<1>(0h1), "") : assert_30 node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_578 : node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_581 = and(_T_579, _T_580) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_582 = shr(io.in.a.bits.source, 2) node _T_583 = eq(_T_582, UInt<1>(0h0)) node _T_584 = leq(UInt<1>(0h0), uncommonBits_5) node _T_585 = and(_T_583, _T_584) node _T_586 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_587 = and(_T_585, _T_586) node _T_588 = and(_T_581, _T_587) node _T_589 = or(UInt<1>(0h0), _T_588) node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_592 = and(_T_590, _T_591) node _T_593 = or(UInt<1>(0h0), _T_592) node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = and(_T_593, _T_598) node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_602 = and(_T_600, _T_601) node _T_603 = or(UInt<1>(0h0), _T_602) node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_615 = cvt(_T_614) node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000))) node _T_617 = asSInt(_T_616) node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_620 = cvt(_T_619) node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) node _T_622 = asSInt(_T_621) node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_635 = cvt(_T_634) node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000))) node _T_637 = asSInt(_T_636) node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0))) node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_640 = cvt(_T_639) node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000))) node _T_642 = asSInt(_T_641) node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) node _T_644 = or(_T_608, _T_613) node _T_645 = or(_T_644, _T_618) node _T_646 = or(_T_645, _T_623) node _T_647 = or(_T_646, _T_628) node _T_648 = or(_T_647, _T_633) node _T_649 = or(_T_648, _T_638) node _T_650 = or(_T_649, _T_643) node _T_651 = and(_T_603, _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_599) node _T_660 = or(_T_659, _T_651) node _T_661 = or(_T_660, _T_658) node _T_662 = and(_T_589, _T_661) node _T_663 = asUInt(reset) node _T_664 = eq(_T_663, UInt<1>(0h0)) when _T_664 : node _T_665 = eq(_T_662, UInt<1>(0h0)) when _T_665 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_662, UInt<1>(0h1), "") : assert_31 node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(is_aligned, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_673 = asUInt(reset) node _T_674 = eq(_T_673, UInt<1>(0h0)) when _T_674 : node _T_675 = eq(_T_672, UInt<1>(0h0)) when _T_675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_672, UInt<1>(0h1), "") : assert_34 node _T_676 = not(mask) node _T_677 = and(io.in.a.bits.mask, _T_676) node _T_678 = eq(_T_677, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_678, UInt<1>(0h1), "") : assert_35 node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_682 : node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_685 = and(_T_683, _T_684) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_686 = shr(io.in.a.bits.source, 2) node _T_687 = eq(_T_686, UInt<1>(0h0)) node _T_688 = leq(UInt<1>(0h0), uncommonBits_6) node _T_689 = and(_T_687, _T_688) node _T_690 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_691 = and(_T_689, _T_690) node _T_692 = and(_T_685, _T_691) node _T_693 = or(UInt<1>(0h0), _T_692) node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _T_697 = or(UInt<1>(0h0), _T_696) node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_709 = cvt(_T_708) node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000))) node _T_711 = asSInt(_T_710) node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0))) node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_714 = cvt(_T_713) node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000))) node _T_716 = asSInt(_T_715) node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0))) node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_724 = cvt(_T_723) node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000))) node _T_726 = asSInt(_T_725) node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0))) node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_729 = cvt(_T_728) node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000))) node _T_731 = asSInt(_T_730) node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0))) node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_739 = cvt(_T_738) node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000))) node _T_741 = asSInt(_T_740) node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0))) node _T_743 = or(_T_702, _T_707) node _T_744 = or(_T_743, _T_712) node _T_745 = or(_T_744, _T_717) node _T_746 = or(_T_745, _T_722) node _T_747 = or(_T_746, _T_727) node _T_748 = or(_T_747, _T_732) node _T_749 = or(_T_748, _T_737) node _T_750 = or(_T_749, _T_742) node _T_751 = and(_T_697, _T_750) node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_754 = cvt(_T_753) node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000))) node _T_756 = asSInt(_T_755) node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0))) node _T_758 = and(_T_752, _T_757) node _T_759 = or(UInt<1>(0h0), _T_751) node _T_760 = or(_T_759, _T_758) node _T_761 = and(_T_693, _T_760) node _T_762 = asUInt(reset) node _T_763 = eq(_T_762, UInt<1>(0h0)) when _T_763 : node _T_764 = eq(_T_761, UInt<1>(0h0)) when _T_764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_761, UInt<1>(0h1), "") : assert_36 node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(is_aligned, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_771, UInt<1>(0h1), "") : assert_39 node _T_775 = eq(io.in.a.bits.mask, mask) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_775, UInt<1>(0h1), "") : assert_40 node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_779 : node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_783 = shr(io.in.a.bits.source, 2) node _T_784 = eq(_T_783, UInt<1>(0h0)) node _T_785 = leq(UInt<1>(0h0), uncommonBits_7) node _T_786 = and(_T_784, _T_785) node _T_787 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_788 = and(_T_786, _T_787) node _T_789 = and(_T_782, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_793 = and(_T_791, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_816 = cvt(_T_815) node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000))) node _T_818 = asSInt(_T_817) node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0))) node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_821 = cvt(_T_820) node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000))) node _T_823 = asSInt(_T_822) node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0))) node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_826 = cvt(_T_825) node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000))) node _T_828 = asSInt(_T_827) node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0))) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_836 = cvt(_T_835) node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000))) node _T_838 = asSInt(_T_837) node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0))) node _T_840 = or(_T_799, _T_804) node _T_841 = or(_T_840, _T_809) node _T_842 = or(_T_841, _T_814) node _T_843 = or(_T_842, _T_819) node _T_844 = or(_T_843, _T_824) node _T_845 = or(_T_844, _T_829) node _T_846 = or(_T_845, _T_834) node _T_847 = or(_T_846, _T_839) node _T_848 = and(_T_794, _T_847) node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_851 = cvt(_T_850) node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000))) node _T_853 = asSInt(_T_852) node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0))) node _T_855 = and(_T_849, _T_854) node _T_856 = or(UInt<1>(0h0), _T_848) node _T_857 = or(_T_856, _T_855) node _T_858 = and(_T_790, _T_857) node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_T_858, UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_858, UInt<1>(0h1), "") : assert_41 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(is_aligned, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_868, UInt<1>(0h1), "") : assert_44 node _T_872 = eq(io.in.a.bits.mask, mask) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_872, UInt<1>(0h1), "") : assert_45 node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_876 : node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_879 = and(_T_877, _T_878) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_880 = shr(io.in.a.bits.source, 2) node _T_881 = eq(_T_880, UInt<1>(0h0)) node _T_882 = leq(UInt<1>(0h0), uncommonBits_8) node _T_883 = and(_T_881, _T_882) node _T_884 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _T_886 = and(_T_879, _T_885) node _T_887 = or(UInt<1>(0h0), _T_886) node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_890 = and(_T_888, _T_889) node _T_891 = or(UInt<1>(0h0), _T_890) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = and(_T_891, _T_896) node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_915 = cvt(_T_914) node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000))) node _T_917 = asSInt(_T_916) node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0))) node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_930 = cvt(_T_929) node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000))) node _T_932 = asSInt(_T_931) node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0))) node _T_934 = or(_T_903, _T_908) node _T_935 = or(_T_934, _T_913) node _T_936 = or(_T_935, _T_918) node _T_937 = or(_T_936, _T_923) node _T_938 = or(_T_937, _T_928) node _T_939 = or(_T_938, _T_933) node _T_940 = and(_T_898, _T_939) node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_943 = and(_T_941, _T_942) node _T_944 = or(UInt<1>(0h0), _T_943) node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_951 = cvt(_T_950) node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000))) node _T_953 = asSInt(_T_952) node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) node _T_955 = or(_T_949, _T_954) node _T_956 = and(_T_944, _T_955) node _T_957 = or(UInt<1>(0h0), _T_897) node _T_958 = or(_T_957, _T_940) node _T_959 = or(_T_958, _T_956) node _T_960 = and(_T_887, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_960, UInt<1>(0h1), "") : assert_46 node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(is_aligned, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_970, UInt<1>(0h1), "") : assert_49 node _T_974 = eq(io.in.a.bits.mask, mask) node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_T_974, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_974, UInt<1>(0h1), "") : assert_50 node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_978, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_982, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 2) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_986 : node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_990 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_990, UInt<1>(0h1), "") : assert_54 node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_994, UInt<1>(0h1), "") : assert_55 node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_998, UInt<1>(0h1), "") : assert_56 node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57 node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(sink_ok, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1013 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60 node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61 node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1022 = asUInt(reset) node _T_1023 = eq(_T_1022, UInt<1>(0h0)) when _T_1023 : node _T_1024 = eq(_T_1021, UInt<1>(0h0)) when _T_1024 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62 node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1026 = asUInt(reset) node _T_1027 = eq(_T_1026, UInt<1>(0h0)) when _T_1027 : node _T_1028 = eq(_T_1025, UInt<1>(0h0)) when _T_1028 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63 node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1030 = or(UInt<1>(0h1), _T_1029) node _T_1031 = asUInt(reset) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) when _T_1032 : node _T_1033 = eq(_T_1030, UInt<1>(0h0)) when _T_1033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64 node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1034 : node _T_1035 = asUInt(reset) node _T_1036 = eq(_T_1035, UInt<1>(0h0)) when _T_1036 : node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(sink_ok, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1041 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67 node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68 node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71 node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75 node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1080 : node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77 node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1089 = or(_T_1088, io.in.d.bits.corrupt) node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_T_1089, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78 node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1094 = or(UInt<1>(0h1), _T_1093) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79 node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1098 : node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81 node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82 node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1111 = or(UInt<1>(0h1), _T_1110) node _T_1112 = asUInt(reset) node _T_1113 = eq(_T_1112, UInt<1>(0h0)) when _T_1113 : node _T_1114 = eq(_T_1111, UInt<1>(0h0)) when _T_1114 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<2>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<2>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1127 = eq(a_first, UInt<1>(0h0)) node _T_1128 = and(io.in.a.valid, _T_1127) when _T_1128 : node _T_1129 = eq(io.in.a.bits.opcode, opcode) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87 node _T_1133 = eq(io.in.a.bits.param, param) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88 node _T_1137 = eq(io.in.a.bits.size, size) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89 node _T_1141 = eq(io.in.a.bits.source, source) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90 node _T_1145 = eq(io.in.a.bits.address, address) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91 node _T_1149 = and(io.in.a.ready, io.in.a.valid) node _T_1150 = and(_T_1149, a_first) when _T_1150 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1151 = eq(d_first, UInt<1>(0h0)) node _T_1152 = and(io.in.d.valid, _T_1151) when _T_1152 : node _T_1153 = eq(io.in.d.bits.opcode, opcode_1) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(_T_1153, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92 node _T_1157 = eq(io.in.d.bits.param, param_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93 node _T_1161 = eq(io.in.d.bits.size, size_1) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94 node _T_1165 = eq(io.in.d.bits.source, source_1) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95 node _T_1169 = eq(io.in.d.bits.sink, sink) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96 node _T_1173 = eq(io.in.d.bits.denied, denied) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97 node _T_1177 = and(io.in.d.ready, io.in.d.valid) node _T_1178 = and(_T_1177, d_first) when _T_1178 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes : UInt<32>, clock, reset, UInt<32>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<4> connect a_set, UInt<4>(0h0) wire a_set_wo_ready : UInt<4> connect a_set_wo_ready, UInt<4>(0h0) wire a_opcodes_set : UInt<16> connect a_opcodes_set, UInt<16>(0h0) wire a_sizes_set : UInt<32> connect a_sizes_set, UInt<32>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1179 = and(io.in.a.valid, a_first_1) node _T_1180 = and(_T_1179, UInt<1>(0h1)) when _T_1180 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1181 = and(io.in.a.ready, io.in.a.valid) node _T_1182 = and(_T_1181, a_first_1) node _T_1183 = and(_T_1182, UInt<1>(0h1)) when _T_1183 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1184 = dshr(inflight, io.in.a.bits.source) node _T_1185 = bits(_T_1184, 0, 0) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<4> connect d_clr, UInt<4>(0h0) wire d_clr_wo_ready : UInt<4> connect d_clr_wo_ready, UInt<4>(0h0) wire d_opcodes_clr : UInt<16> connect d_opcodes_clr, UInt<16>(0h0) wire d_sizes_clr : UInt<32> connect d_sizes_clr, UInt<32>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1190 = and(io.in.d.valid, d_first_1) node _T_1191 = and(_T_1190, UInt<1>(0h1)) node _T_1192 = eq(d_release_ack, UInt<1>(0h0)) node _T_1193 = and(_T_1191, _T_1192) when _T_1193 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1194 = and(io.in.d.ready, io.in.d.valid) node _T_1195 = and(_T_1194, d_first_1) node _T_1196 = and(_T_1195, UInt<1>(0h1)) node _T_1197 = eq(d_release_ack, UInt<1>(0h0)) node _T_1198 = and(_T_1196, _T_1197) when _T_1198 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1199 = and(io.in.d.valid, d_first_1) node _T_1200 = and(_T_1199, UInt<1>(0h1)) node _T_1201 = eq(d_release_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1203 = dshr(inflight, io.in.d.bits.source) node _T_1204 = bits(_T_1203, 0, 0) node _T_1205 = or(_T_1204, same_cycle_resp) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1211 = or(_T_1209, _T_1210) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100 node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101 else : node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1221 = or(_T_1219, _T_1220) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102 node _T_1225 = eq(io.in.d.bits.size, a_size_lookup) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103 node _T_1229 = and(io.in.d.valid, d_first_1) node _T_1230 = and(_T_1229, a_first_1) node _T_1231 = and(_T_1230, io.in.a.valid) node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1233 = and(_T_1231, _T_1232) node _T_1234 = eq(d_release_ack, UInt<1>(0h0)) node _T_1235 = and(_T_1233, _T_1234) when _T_1235 : node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1237 = or(_T_1236, io.in.a.ready) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104 node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1242 = orr(a_set_wo_ready) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1243) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_18 node _T_1248 = orr(inflight) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1251 = or(_T_1249, _T_1250) node _T_1252 = lt(watchdog, plusarg_reader.out) node _T_1253 = or(_T_1251, _T_1252) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1257 = and(io.in.a.ready, io.in.a.valid) node _T_1258 = and(io.in.d.ready, io.in.d.valid) node _T_1259 = or(_T_1257, _T_1258) when _T_1259 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_opcodes_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_sizes_1 : UInt<32>, clock, reset, UInt<32>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<2>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<2>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<4> connect c_set, UInt<4>(0h0) wire c_set_wo_ready : UInt<4> connect c_set_wo_ready, UInt<4>(0h0) wire c_opcodes_set : UInt<16> connect c_opcodes_set, UInt<16>(0h0) wire c_sizes_set : UInt<32> connect c_sizes_set, UInt<32>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<2>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1260 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<2>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = and(_T_1260, _T_1263) when _T_1264 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<2>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1266 = and(_T_1265, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<2>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1269 = and(_T_1267, _T_1268) node _T_1270 = and(_T_1266, _T_1269) when _T_1270 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<2>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<2>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1272 = bits(_T_1271, 0, 0) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(_T_1273, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<4> connect d_clr_1, UInt<4>(0h0) wire d_clr_wo_ready_1 : UInt<4> connect d_clr_wo_ready_1, UInt<4>(0h0) wire d_opcodes_clr_1 : UInt<16> connect d_opcodes_clr_1, UInt<16>(0h0) wire d_sizes_clr_1 : UInt<32> connect d_sizes_clr_1, UInt<32>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1277 = and(io.in.d.valid, d_first_2) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = and(_T_1278, d_release_ack_1) when _T_1279 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1280 = and(io.in.d.ready, io.in.d.valid) node _T_1281 = and(_T_1280, d_first_2) node _T_1282 = and(_T_1281, UInt<1>(0h1)) node _T_1283 = and(_T_1282, d_release_ack_1) when _T_1283 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1284 = and(io.in.d.valid, d_first_2) node _T_1285 = and(_T_1284, UInt<1>(0h1)) node _T_1286 = and(_T_1285, d_release_ack_1) when _T_1286 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1287 = dshr(inflight_1, io.in.d.bits.source) node _T_1288 = bits(_T_1287, 0, 0) node _T_1289 = or(_T_1288, same_cycle_resp_1) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<2>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109 else : node _T_1297 = eq(io.in.d.bits.size, c_size_lookup) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110 node _T_1301 = and(io.in.d.valid, d_first_2) node _T_1302 = and(_T_1301, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<2>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1303 = and(_T_1302, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<2>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1305 = and(_T_1303, _T_1304) node _T_1306 = and(_T_1305, d_release_ack_1) node _T_1307 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1308 = and(_T_1306, _T_1307) when _T_1308 : node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<2>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1310 = or(_T_1309, _WIRE_23.ready) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111 node _T_1314 = orr(c_set_wo_ready) when _T_1314 : node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_19 node _T_1319 = orr(inflight_1) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1322 = or(_T_1320, _T_1321) node _T_1323 = lt(watchdog_1, plusarg_reader_1.out) node _T_1324 = or(_T_1322, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<2>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1329 = and(io.in.d.ready, io.in.d.valid) node _T_1330 = or(_T_1328, _T_1329) when _T_1330 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_20 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_21 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_9( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_sizes_set = 32'h0; // @[Monitor.scala:741:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_source = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_source = 2'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_set = 4'h0; // @[Monitor.scala:738:34] wire [3:0] c_set_wo_ready = 4'h0; // @[Monitor.scala:739:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [35:0] _c_sizes_set_T_1 = 36'h0; // @[Monitor.scala:768:52] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_T = 5'h0; // @[Monitor.scala:767:79] wire [4:0] _c_sizes_set_T = 5'h0; // @[Monitor.scala:768:77] wire [34:0] _c_opcodes_set_T_1 = 35'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_set_wo_ready_T = 4'h1; // @[OneHot.scala:58:35] wire [3:0] _c_set_T = 4'h1; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] c_opcodes_set = 16'h0; // @[Monitor.scala:740:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [1:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [1:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [1:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [3:0] inflight; // @[Monitor.scala:614:27] reg [15:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [31:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] a_set; // @[Monitor.scala:626:34] wire [3:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [15:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [31:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [4:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [4:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [31:0] _a_size_lookup_T_6 = {24'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [31:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [3:0] _GEN_3 = {2'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_4 = 4'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [3:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1183 ? _a_set_T : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [3:0] d_clr; // @[Monitor.scala:664:34] wire [3:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [15:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [31:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [3:0] _GEN_6 = {2'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [3:0] _GEN_7 = 4'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 4'h0; // @[OneHot.scala:58:35] wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1198 ? _d_clr_T : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[31:0] : 32'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [3:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [15:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [31:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [3:0] inflight_1; // @[Monitor.scala:726:35] wire [3:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [15:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [15:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [31:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [31:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = _c_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [31:0] _c_size_lookup_T_6 = {24'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [31:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] d_clr_1; // @[Monitor.scala:774:34] wire [3:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [15:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [31:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 4'h0; // @[OneHot.scala:58:35] wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 4'h0; // @[OneHot.scala:58:35] wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[31:0] : 32'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7, :795:113] wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [3:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [15:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [15:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [31:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_347 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_91 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_347( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_91 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_28 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_28 connect io_out_sink_valid_0.clock, clock connect io_out_sink_valid_0.reset, reset connect io_out_sink_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_28( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_28 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueUnitCollapsing : input clock : Clock input reset : Reset output io : { flip dis_uops : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[2], iss_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[1], flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>, flip fu_types : UInt<1>[10][1], flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip flush_pipeline : UInt<1>, flip squash_grant : UInt<1>, flip tsc_reg : UInt<64>} wire _WIRE : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} wire _WIRE_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect _WIRE, io.dis_uops[0].bits connect _WIRE.iw_issued, UInt<1>(0h0) connect _WIRE.iw_issued_partial_agen, UInt<1>(0h0) connect _WIRE.iw_issued_partial_dgen, UInt<1>(0h0) connect _WIRE.iw_p1_bypass_hint, UInt<1>(0h0) connect _WIRE.iw_p2_bypass_hint, UInt<1>(0h0) connect _WIRE.iw_p3_bypass_hint, UInt<1>(0h0) node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs1) node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs1) node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs2) node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs2) node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[0].bits.prs3) node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[0].bits.prs3) node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0) node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1) node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0) node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1) node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0) node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1) node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0) node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1) node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0) node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1) node _T = or(prs1_wakeups_0, prs1_wakeups_1) when _T : connect _WIRE.prs1_busy, UInt<1>(0h0) node _T_1 = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_2 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_3 = or(_T_1, _T_2) wire _WIRE_2 : UInt<2> connect _WIRE_2, _T_3 connect _WIRE.iw_p1_speculative_child, _WIRE_2 node _T_4 = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_5 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_6 = or(_T_4, _T_5) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_6 connect _WIRE.iw_p1_bypass_hint, _WIRE_3 node _T_7 = or(prs1_rebusys_0, prs1_rebusys_1) node _T_8 = and(io.child_rebusys, io.dis_uops[0].bits.iw_p1_speculative_child) node _T_9 = neq(_T_8, UInt<1>(0h0)) node _T_10 = or(_T_7, _T_9) when _T_10 : node _T_11 = eq(io.dis_uops[0].bits.lrs1_rtype, UInt<2>(0h0)) connect _WIRE.prs1_busy, _T_11 node _T_12 = or(prs2_wakeups_0, prs2_wakeups_1) when _T_12 : connect _WIRE.prs2_busy, UInt<1>(0h0) node _T_13 = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_14 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_15 = or(_T_13, _T_14) wire _WIRE_4 : UInt<2> connect _WIRE_4, _T_15 connect _WIRE.iw_p2_speculative_child, _WIRE_4 node _T_16 = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_17 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_18 = or(_T_16, _T_17) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_18 connect _WIRE.iw_p2_bypass_hint, _WIRE_5 node _T_19 = or(prs2_rebusys_0, prs2_rebusys_1) node _T_20 = and(io.child_rebusys, io.dis_uops[0].bits.iw_p2_speculative_child) node _T_21 = neq(_T_20, UInt<1>(0h0)) node _T_22 = or(_T_19, _T_21) when _T_22 : node _T_23 = eq(io.dis_uops[0].bits.lrs2_rtype, UInt<2>(0h0)) connect _WIRE.prs2_busy, _T_23 node _T_24 = or(prs3_wakeups_0, prs3_wakeups_1) when _T_24 : connect _WIRE.prs3_busy, UInt<1>(0h0) node _T_25 = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_26 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_27 = or(_T_25, _T_26) wire _WIRE_6 : UInt<1> connect _WIRE_6, _T_27 connect _WIRE.iw_p3_bypass_hint, _WIRE_6 node _T_28 = eq(io.pred_wakeup_port.bits, io.dis_uops[0].bits.ppred) node _T_29 = and(io.pred_wakeup_port.valid, _T_28) when _T_29 : connect _WIRE.ppred_busy, UInt<1>(0h0) when io.dis_uops[0].bits.uses_stq : connect _WIRE.lrs1_rtype, UInt<2>(0h2) connect _WIRE.prs1_busy, UInt<1>(0h0) node _T_30 = and(io.dis_uops[0].bits.ppred_busy, io.dis_uops[0].valid) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : node _T_34 = eq(_T_31, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:110 assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid))\n") : printf assert(clock, _T_31, UInt<1>(0h1), "") : assert connect _WIRE.ppred_busy, UInt<1>(0h0) connect _WIRE_1, io.dis_uops[1].bits connect _WIRE_1.iw_issued, UInt<1>(0h0) connect _WIRE_1.iw_issued_partial_agen, UInt<1>(0h0) connect _WIRE_1.iw_issued_partial_dgen, UInt<1>(0h0) connect _WIRE_1.iw_p1_bypass_hint, UInt<1>(0h0) connect _WIRE_1.iw_p2_bypass_hint, UInt<1>(0h0) connect _WIRE_1.iw_p3_bypass_hint, UInt<1>(0h0) node prs1_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs1) node prs1_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs1) node prs2_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs2) node prs2_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs2) node prs3_matches_0_1 = eq(io.wakeup_ports[0].bits.uop.pdst, io.dis_uops[1].bits.prs3) node prs3_matches_1_1 = eq(io.wakeup_ports[1].bits.uop.pdst, io.dis_uops[1].bits.prs3) node prs1_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs1_matches_0_1) node prs1_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs1_matches_1_1) node prs2_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs2_matches_0_1) node prs2_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs2_matches_1_1) node prs3_wakeups_0_1 = and(io.wakeup_ports[0].valid, prs3_matches_0_1) node prs3_wakeups_1_1 = and(io.wakeup_ports[1].valid, prs3_matches_1_1) node prs1_rebusys_0_1 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0_1) node prs1_rebusys_1_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1_1) node prs2_rebusys_0_1 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0_1) node prs2_rebusys_1_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1_1) node _T_35 = or(prs1_wakeups_0_1, prs1_wakeups_1_1) when _T_35 : connect _WIRE_1.prs1_busy, UInt<1>(0h0) node _T_36 = mux(prs1_wakeups_0_1, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_37 = mux(prs1_wakeups_1_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_38 = or(_T_36, _T_37) wire _WIRE_7 : UInt<2> connect _WIRE_7, _T_38 connect _WIRE_1.iw_p1_speculative_child, _WIRE_7 node _T_39 = mux(prs1_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_40 = mux(prs1_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_41 = or(_T_39, _T_40) wire _WIRE_8 : UInt<1> connect _WIRE_8, _T_41 connect _WIRE_1.iw_p1_bypass_hint, _WIRE_8 node _T_42 = or(prs1_rebusys_0_1, prs1_rebusys_1_1) node _T_43 = and(io.child_rebusys, io.dis_uops[1].bits.iw_p1_speculative_child) node _T_44 = neq(_T_43, UInt<1>(0h0)) node _T_45 = or(_T_42, _T_44) when _T_45 : node _T_46 = eq(io.dis_uops[1].bits.lrs1_rtype, UInt<2>(0h0)) connect _WIRE_1.prs1_busy, _T_46 node _T_47 = or(prs2_wakeups_0_1, prs2_wakeups_1_1) when _T_47 : connect _WIRE_1.prs2_busy, UInt<1>(0h0) node _T_48 = mux(prs2_wakeups_0_1, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0)) node _T_49 = mux(prs2_wakeups_1_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0)) node _T_50 = or(_T_48, _T_49) wire _WIRE_9 : UInt<2> connect _WIRE_9, _T_50 connect _WIRE_1.iw_p2_speculative_child, _WIRE_9 node _T_51 = mux(prs2_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_52 = mux(prs2_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_53 = or(_T_51, _T_52) wire _WIRE_10 : UInt<1> connect _WIRE_10, _T_53 connect _WIRE_1.iw_p2_bypass_hint, _WIRE_10 node _T_54 = or(prs2_rebusys_0_1, prs2_rebusys_1_1) node _T_55 = and(io.child_rebusys, io.dis_uops[1].bits.iw_p2_speculative_child) node _T_56 = neq(_T_55, UInt<1>(0h0)) node _T_57 = or(_T_54, _T_56) when _T_57 : node _T_58 = eq(io.dis_uops[1].bits.lrs2_rtype, UInt<2>(0h0)) connect _WIRE_1.prs2_busy, _T_58 node _T_59 = or(prs3_wakeups_0_1, prs3_wakeups_1_1) when _T_59 : connect _WIRE_1.prs3_busy, UInt<1>(0h0) node _T_60 = mux(prs3_wakeups_0_1, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0)) node _T_61 = mux(prs3_wakeups_1_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0)) node _T_62 = or(_T_60, _T_61) wire _WIRE_11 : UInt<1> connect _WIRE_11, _T_62 connect _WIRE_1.iw_p3_bypass_hint, _WIRE_11 node _T_63 = eq(io.pred_wakeup_port.bits, io.dis_uops[1].bits.ppred) node _T_64 = and(io.pred_wakeup_port.valid, _T_63) when _T_64 : connect _WIRE_1.ppred_busy, UInt<1>(0h0) when io.dis_uops[1].bits.uses_stq : connect _WIRE_1.lrs1_rtype, UInt<2>(0h2) connect _WIRE_1.prs1_busy, UInt<1>(0h0) node _T_65 = and(io.dis_uops[1].bits.ppred_busy, io.dis_uops[1].valid) node _T_66 = eq(_T_65, UInt<1>(0h0)) node _T_67 = asUInt(reset) node _T_68 = eq(_T_67, UInt<1>(0h0)) when _T_68 : node _T_69 = eq(_T_66, UInt<1>(0h0)) when _T_69 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:110 assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid))\n") : printf_1 assert(clock, _T_66, UInt<1>(0h1), "") : assert_1 connect _WIRE_1.ppred_busy, UInt<1>(0h0) inst slots_0 of IssueSlot connect slots_0.clock, clock connect slots_0.reset, reset inst slots_1 of IssueSlot_1 connect slots_1.clock, clock connect slots_1.reset, reset inst slots_2 of IssueSlot_2 connect slots_2.clock, clock connect slots_2.reset, reset inst slots_3 of IssueSlot_3 connect slots_3.clock, clock connect slots_3.reset, reset inst slots_4 of IssueSlot_4 connect slots_4.clock, clock connect slots_4.reset, reset inst slots_5 of IssueSlot_5 connect slots_5.clock, clock connect slots_5.reset, reset inst slots_6 of IssueSlot_6 connect slots_6.clock, clock connect slots_6.reset, reset inst slots_7 of IssueSlot_7 connect slots_7.clock, clock connect slots_7.reset, reset inst slots_8 of IssueSlot_8 connect slots_8.clock, clock connect slots_8.reset, reset inst slots_9 of IssueSlot_9 connect slots_9.clock, clock connect slots_9.reset, reset inst slots_10 of IssueSlot_10 connect slots_10.clock, clock connect slots_10.reset, reset inst slots_11 of IssueSlot_11 connect slots_11.clock, clock connect slots_11.reset, reset wire issue_slots : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>}[12] connect slots_0.io.child_rebusys, issue_slots[0].child_rebusys connect slots_0.io.pred_wakeup_port.bits, issue_slots[0].pred_wakeup_port.bits connect slots_0.io.pred_wakeup_port.valid, issue_slots[0].pred_wakeup_port.valid connect slots_0.io.wakeup_ports[0].bits.rebusy, issue_slots[0].wakeup_ports[0].bits.rebusy connect slots_0.io.wakeup_ports[0].bits.speculative_mask, issue_slots[0].wakeup_ports[0].bits.speculative_mask connect slots_0.io.wakeup_ports[0].bits.bypassable, issue_slots[0].wakeup_ports[0].bits.bypassable connect slots_0.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[0].bits.uop.debug_tsrc connect slots_0.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[0].bits.uop.debug_fsrc connect slots_0.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_0.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[0].bits.uop.bp_debug_if connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_0.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_0.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[0].wakeup_ports[0].bits.uop.fp_typ connect slots_0.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[0].wakeup_ports[0].bits.uop.fp_rm connect slots_0.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[0].wakeup_ports[0].bits.uop.fp_val connect slots_0.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[0].wakeup_ports[0].bits.uop.fcn_op connect slots_0.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[0].bits.uop.fcn_dw connect slots_0.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[0].wakeup_ports[0].bits.uop.frs3_en connect slots_0.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_0.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_0.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[0].bits.uop.dst_rtype connect slots_0.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[0].wakeup_ports[0].bits.uop.lrs3 connect slots_0.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[0].wakeup_ports[0].bits.uop.lrs2 connect slots_0.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[0].wakeup_ports[0].bits.uop.lrs1 connect slots_0.io.wakeup_ports[0].bits.uop.ldst, issue_slots[0].wakeup_ports[0].bits.uop.ldst connect slots_0.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_0.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[0].bits.uop.csr_cmd connect slots_0.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[0].bits.uop.flush_on_commit connect slots_0.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[0].wakeup_ports[0].bits.uop.is_unique connect slots_0.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[0].wakeup_ports[0].bits.uop.uses_stq connect slots_0.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[0].bits.uop.uses_ldq connect slots_0.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[0].wakeup_ports[0].bits.uop.mem_signed connect slots_0.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[0].wakeup_ports[0].bits.uop.mem_size connect slots_0.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[0].bits.uop.mem_cmd connect slots_0.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[0].wakeup_ports[0].bits.uop.exc_cause connect slots_0.io.wakeup_ports[0].bits.uop.exception, issue_slots[0].wakeup_ports[0].bits.uop.exception connect slots_0.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[0].bits.uop.stale_pdst connect slots_0.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[0].bits.uop.ppred_busy connect slots_0.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs3_busy connect slots_0.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs2_busy connect slots_0.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[0].bits.uop.prs1_busy connect slots_0.io.wakeup_ports[0].bits.uop.ppred, issue_slots[0].wakeup_ports[0].bits.uop.ppred connect slots_0.io.wakeup_ports[0].bits.uop.prs3, issue_slots[0].wakeup_ports[0].bits.uop.prs3 connect slots_0.io.wakeup_ports[0].bits.uop.prs2, issue_slots[0].wakeup_ports[0].bits.uop.prs2 connect slots_0.io.wakeup_ports[0].bits.uop.prs1, issue_slots[0].wakeup_ports[0].bits.uop.prs1 connect slots_0.io.wakeup_ports[0].bits.uop.pdst, issue_slots[0].wakeup_ports[0].bits.uop.pdst connect slots_0.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[0].bits.uop.rxq_idx connect slots_0.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[0].wakeup_ports[0].bits.uop.stq_idx connect slots_0.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[0].bits.uop.ldq_idx connect slots_0.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[0].wakeup_ports[0].bits.uop.rob_idx connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_0.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_0.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[0].wakeup_ports[0].bits.uop.op2_sel connect slots_0.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[0].wakeup_ports[0].bits.uop.op1_sel connect slots_0.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[0].wakeup_ports[0].bits.uop.imm_packed connect slots_0.io.wakeup_ports[0].bits.uop.pimm, issue_slots[0].wakeup_ports[0].bits.uop.pimm connect slots_0.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[0].wakeup_ports[0].bits.uop.imm_sel connect slots_0.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[0].wakeup_ports[0].bits.uop.imm_rename connect slots_0.io.wakeup_ports[0].bits.uop.taken, issue_slots[0].wakeup_ports[0].bits.uop.taken connect slots_0.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[0].wakeup_ports[0].bits.uop.pc_lob connect slots_0.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[0].wakeup_ports[0].bits.uop.edge_inst connect slots_0.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[0].bits.uop.ftq_idx connect slots_0.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[0].wakeup_ports[0].bits.uop.is_mov connect slots_0.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[0].wakeup_ports[0].bits.uop.is_rocc connect slots_0.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_0.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[0].wakeup_ports[0].bits.uop.is_eret connect slots_0.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[0].wakeup_ports[0].bits.uop.is_amo connect slots_0.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[0].wakeup_ports[0].bits.uop.is_sfence connect slots_0.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[0].wakeup_ports[0].bits.uop.is_fencei connect slots_0.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[0].wakeup_ports[0].bits.uop.is_fence connect slots_0.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[0].wakeup_ports[0].bits.uop.is_sfb connect slots_0.io.wakeup_ports[0].bits.uop.br_type, issue_slots[0].wakeup_ports[0].bits.uop.br_type connect slots_0.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[0].wakeup_ports[0].bits.uop.br_tag connect slots_0.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[0].wakeup_ports[0].bits.uop.br_mask connect slots_0.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[0].bits.uop.dis_col_sel connect slots_0.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_0.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_0.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_0.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_0.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_0.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[0].wakeup_ports[0].bits.uop.iw_issued connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[0] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[1] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[2] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[3] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[4] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[5] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[6] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[7] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[8] connect slots_0.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[0].bits.uop.fu_code[9] connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[0] connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[1] connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[2] connect slots_0.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[0].bits.uop.iq_type[3] connect slots_0.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[0].wakeup_ports[0].bits.uop.debug_pc connect slots_0.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[0].wakeup_ports[0].bits.uop.is_rvc connect slots_0.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[0].wakeup_ports[0].bits.uop.debug_inst connect slots_0.io.wakeup_ports[0].bits.uop.inst, issue_slots[0].wakeup_ports[0].bits.uop.inst connect slots_0.io.wakeup_ports[0].valid, issue_slots[0].wakeup_ports[0].valid connect slots_0.io.wakeup_ports[1].bits.rebusy, issue_slots[0].wakeup_ports[1].bits.rebusy connect slots_0.io.wakeup_ports[1].bits.speculative_mask, issue_slots[0].wakeup_ports[1].bits.speculative_mask connect slots_0.io.wakeup_ports[1].bits.bypassable, issue_slots[0].wakeup_ports[1].bits.bypassable connect slots_0.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[0].wakeup_ports[1].bits.uop.debug_tsrc connect slots_0.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[0].wakeup_ports[1].bits.uop.debug_fsrc connect slots_0.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[0].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_0.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[0].wakeup_ports[1].bits.uop.bp_debug_if connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_0.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[0].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_0.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[0].wakeup_ports[1].bits.uop.fp_typ connect slots_0.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[0].wakeup_ports[1].bits.uop.fp_rm connect slots_0.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[0].wakeup_ports[1].bits.uop.fp_val connect slots_0.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[0].wakeup_ports[1].bits.uop.fcn_op connect slots_0.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[0].wakeup_ports[1].bits.uop.fcn_dw connect slots_0.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[0].wakeup_ports[1].bits.uop.frs3_en connect slots_0.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[0].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_0.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[0].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_0.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[0].wakeup_ports[1].bits.uop.dst_rtype connect slots_0.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[0].wakeup_ports[1].bits.uop.lrs3 connect slots_0.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[0].wakeup_ports[1].bits.uop.lrs2 connect slots_0.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[0].wakeup_ports[1].bits.uop.lrs1 connect slots_0.io.wakeup_ports[1].bits.uop.ldst, issue_slots[0].wakeup_ports[1].bits.uop.ldst connect slots_0.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[0].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_0.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[0].wakeup_ports[1].bits.uop.csr_cmd connect slots_0.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[0].wakeup_ports[1].bits.uop.flush_on_commit connect slots_0.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[0].wakeup_ports[1].bits.uop.is_unique connect slots_0.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[0].wakeup_ports[1].bits.uop.uses_stq connect slots_0.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[0].wakeup_ports[1].bits.uop.uses_ldq connect slots_0.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[0].wakeup_ports[1].bits.uop.mem_signed connect slots_0.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[0].wakeup_ports[1].bits.uop.mem_size connect slots_0.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[0].wakeup_ports[1].bits.uop.mem_cmd connect slots_0.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[0].wakeup_ports[1].bits.uop.exc_cause connect slots_0.io.wakeup_ports[1].bits.uop.exception, issue_slots[0].wakeup_ports[1].bits.uop.exception connect slots_0.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[0].wakeup_ports[1].bits.uop.stale_pdst connect slots_0.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[0].wakeup_ports[1].bits.uop.ppred_busy connect slots_0.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs3_busy connect slots_0.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs2_busy connect slots_0.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[0].wakeup_ports[1].bits.uop.prs1_busy connect slots_0.io.wakeup_ports[1].bits.uop.ppred, issue_slots[0].wakeup_ports[1].bits.uop.ppred connect slots_0.io.wakeup_ports[1].bits.uop.prs3, issue_slots[0].wakeup_ports[1].bits.uop.prs3 connect slots_0.io.wakeup_ports[1].bits.uop.prs2, issue_slots[0].wakeup_ports[1].bits.uop.prs2 connect slots_0.io.wakeup_ports[1].bits.uop.prs1, issue_slots[0].wakeup_ports[1].bits.uop.prs1 connect slots_0.io.wakeup_ports[1].bits.uop.pdst, issue_slots[0].wakeup_ports[1].bits.uop.pdst connect slots_0.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[0].wakeup_ports[1].bits.uop.rxq_idx connect slots_0.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[0].wakeup_ports[1].bits.uop.stq_idx connect slots_0.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[0].wakeup_ports[1].bits.uop.ldq_idx connect slots_0.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[0].wakeup_ports[1].bits.uop.rob_idx connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_0.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_0.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[0].wakeup_ports[1].bits.uop.op2_sel connect slots_0.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[0].wakeup_ports[1].bits.uop.op1_sel connect slots_0.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[0].wakeup_ports[1].bits.uop.imm_packed connect slots_0.io.wakeup_ports[1].bits.uop.pimm, issue_slots[0].wakeup_ports[1].bits.uop.pimm connect slots_0.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[0].wakeup_ports[1].bits.uop.imm_sel connect slots_0.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[0].wakeup_ports[1].bits.uop.imm_rename connect slots_0.io.wakeup_ports[1].bits.uop.taken, issue_slots[0].wakeup_ports[1].bits.uop.taken connect slots_0.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[0].wakeup_ports[1].bits.uop.pc_lob connect slots_0.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[0].wakeup_ports[1].bits.uop.edge_inst connect slots_0.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[0].wakeup_ports[1].bits.uop.ftq_idx connect slots_0.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[0].wakeup_ports[1].bits.uop.is_mov connect slots_0.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[0].wakeup_ports[1].bits.uop.is_rocc connect slots_0.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[0].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_0.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[0].wakeup_ports[1].bits.uop.is_eret connect slots_0.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[0].wakeup_ports[1].bits.uop.is_amo connect slots_0.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[0].wakeup_ports[1].bits.uop.is_sfence connect slots_0.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[0].wakeup_ports[1].bits.uop.is_fencei connect slots_0.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[0].wakeup_ports[1].bits.uop.is_fence connect slots_0.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[0].wakeup_ports[1].bits.uop.is_sfb connect slots_0.io.wakeup_ports[1].bits.uop.br_type, issue_slots[0].wakeup_ports[1].bits.uop.br_type connect slots_0.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[0].wakeup_ports[1].bits.uop.br_tag connect slots_0.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[0].wakeup_ports[1].bits.uop.br_mask connect slots_0.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[0].wakeup_ports[1].bits.uop.dis_col_sel connect slots_0.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_0.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_0.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_0.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_0.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_0.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[0].wakeup_ports[1].bits.uop.iw_issued connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[0] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[1] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[2] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[3] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[4] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[5] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[6] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[7] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[8] connect slots_0.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[0].wakeup_ports[1].bits.uop.fu_code[9] connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[0] connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[1] connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[2] connect slots_0.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[0].wakeup_ports[1].bits.uop.iq_type[3] connect slots_0.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[0].wakeup_ports[1].bits.uop.debug_pc connect slots_0.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[0].wakeup_ports[1].bits.uop.is_rvc connect slots_0.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[0].wakeup_ports[1].bits.uop.debug_inst connect slots_0.io.wakeup_ports[1].bits.uop.inst, issue_slots[0].wakeup_ports[1].bits.uop.inst connect slots_0.io.wakeup_ports[1].valid, issue_slots[0].wakeup_ports[1].valid connect slots_0.io.squash_grant, issue_slots[0].squash_grant connect slots_0.io.clear, issue_slots[0].clear connect slots_0.io.kill, issue_slots[0].kill connect slots_0.io.brupdate.b2.target_offset, issue_slots[0].brupdate.b2.target_offset connect slots_0.io.brupdate.b2.jalr_target, issue_slots[0].brupdate.b2.jalr_target connect slots_0.io.brupdate.b2.pc_sel, issue_slots[0].brupdate.b2.pc_sel connect slots_0.io.brupdate.b2.cfi_type, issue_slots[0].brupdate.b2.cfi_type connect slots_0.io.brupdate.b2.taken, issue_slots[0].brupdate.b2.taken connect slots_0.io.brupdate.b2.mispredict, issue_slots[0].brupdate.b2.mispredict connect slots_0.io.brupdate.b2.uop.debug_tsrc, issue_slots[0].brupdate.b2.uop.debug_tsrc connect slots_0.io.brupdate.b2.uop.debug_fsrc, issue_slots[0].brupdate.b2.uop.debug_fsrc connect slots_0.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[0].brupdate.b2.uop.bp_xcpt_if connect slots_0.io.brupdate.b2.uop.bp_debug_if, issue_slots[0].brupdate.b2.uop.bp_debug_if connect slots_0.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[0].brupdate.b2.uop.xcpt_ma_if connect slots_0.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[0].brupdate.b2.uop.xcpt_ae_if connect slots_0.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[0].brupdate.b2.uop.xcpt_pf_if connect slots_0.io.brupdate.b2.uop.fp_typ, issue_slots[0].brupdate.b2.uop.fp_typ connect slots_0.io.brupdate.b2.uop.fp_rm, issue_slots[0].brupdate.b2.uop.fp_rm connect slots_0.io.brupdate.b2.uop.fp_val, issue_slots[0].brupdate.b2.uop.fp_val connect slots_0.io.brupdate.b2.uop.fcn_op, issue_slots[0].brupdate.b2.uop.fcn_op connect slots_0.io.brupdate.b2.uop.fcn_dw, issue_slots[0].brupdate.b2.uop.fcn_dw connect slots_0.io.brupdate.b2.uop.frs3_en, issue_slots[0].brupdate.b2.uop.frs3_en connect slots_0.io.brupdate.b2.uop.lrs2_rtype, issue_slots[0].brupdate.b2.uop.lrs2_rtype connect slots_0.io.brupdate.b2.uop.lrs1_rtype, issue_slots[0].brupdate.b2.uop.lrs1_rtype connect slots_0.io.brupdate.b2.uop.dst_rtype, issue_slots[0].brupdate.b2.uop.dst_rtype connect slots_0.io.brupdate.b2.uop.lrs3, issue_slots[0].brupdate.b2.uop.lrs3 connect slots_0.io.brupdate.b2.uop.lrs2, issue_slots[0].brupdate.b2.uop.lrs2 connect slots_0.io.brupdate.b2.uop.lrs1, issue_slots[0].brupdate.b2.uop.lrs1 connect slots_0.io.brupdate.b2.uop.ldst, issue_slots[0].brupdate.b2.uop.ldst connect slots_0.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[0].brupdate.b2.uop.ldst_is_rs1 connect slots_0.io.brupdate.b2.uop.csr_cmd, issue_slots[0].brupdate.b2.uop.csr_cmd connect slots_0.io.brupdate.b2.uop.flush_on_commit, issue_slots[0].brupdate.b2.uop.flush_on_commit connect slots_0.io.brupdate.b2.uop.is_unique, issue_slots[0].brupdate.b2.uop.is_unique connect slots_0.io.brupdate.b2.uop.uses_stq, issue_slots[0].brupdate.b2.uop.uses_stq connect slots_0.io.brupdate.b2.uop.uses_ldq, issue_slots[0].brupdate.b2.uop.uses_ldq connect slots_0.io.brupdate.b2.uop.mem_signed, issue_slots[0].brupdate.b2.uop.mem_signed connect slots_0.io.brupdate.b2.uop.mem_size, issue_slots[0].brupdate.b2.uop.mem_size connect slots_0.io.brupdate.b2.uop.mem_cmd, issue_slots[0].brupdate.b2.uop.mem_cmd connect slots_0.io.brupdate.b2.uop.exc_cause, issue_slots[0].brupdate.b2.uop.exc_cause connect slots_0.io.brupdate.b2.uop.exception, issue_slots[0].brupdate.b2.uop.exception connect slots_0.io.brupdate.b2.uop.stale_pdst, issue_slots[0].brupdate.b2.uop.stale_pdst connect slots_0.io.brupdate.b2.uop.ppred_busy, issue_slots[0].brupdate.b2.uop.ppred_busy connect slots_0.io.brupdate.b2.uop.prs3_busy, issue_slots[0].brupdate.b2.uop.prs3_busy connect slots_0.io.brupdate.b2.uop.prs2_busy, issue_slots[0].brupdate.b2.uop.prs2_busy connect slots_0.io.brupdate.b2.uop.prs1_busy, issue_slots[0].brupdate.b2.uop.prs1_busy connect slots_0.io.brupdate.b2.uop.ppred, issue_slots[0].brupdate.b2.uop.ppred connect slots_0.io.brupdate.b2.uop.prs3, issue_slots[0].brupdate.b2.uop.prs3 connect slots_0.io.brupdate.b2.uop.prs2, issue_slots[0].brupdate.b2.uop.prs2 connect slots_0.io.brupdate.b2.uop.prs1, issue_slots[0].brupdate.b2.uop.prs1 connect slots_0.io.brupdate.b2.uop.pdst, issue_slots[0].brupdate.b2.uop.pdst connect slots_0.io.brupdate.b2.uop.rxq_idx, issue_slots[0].brupdate.b2.uop.rxq_idx connect slots_0.io.brupdate.b2.uop.stq_idx, issue_slots[0].brupdate.b2.uop.stq_idx connect slots_0.io.brupdate.b2.uop.ldq_idx, issue_slots[0].brupdate.b2.uop.ldq_idx connect slots_0.io.brupdate.b2.uop.rob_idx, issue_slots[0].brupdate.b2.uop.rob_idx connect slots_0.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[0].brupdate.b2.uop.fp_ctrl.vec connect slots_0.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[0].brupdate.b2.uop.fp_ctrl.wflags connect slots_0.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[0].brupdate.b2.uop.fp_ctrl.sqrt connect slots_0.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[0].brupdate.b2.uop.fp_ctrl.div connect slots_0.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[0].brupdate.b2.uop.fp_ctrl.fma connect slots_0.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[0].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_0.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[0].brupdate.b2.uop.fp_ctrl.toint connect slots_0.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[0].brupdate.b2.uop.fp_ctrl.fromint connect slots_0.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_0.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_0.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[0].brupdate.b2.uop.fp_ctrl.swap23 connect slots_0.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[0].brupdate.b2.uop.fp_ctrl.swap12 connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren3 connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren2 connect slots_0.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[0].brupdate.b2.uop.fp_ctrl.ren1 connect slots_0.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[0].brupdate.b2.uop.fp_ctrl.wen connect slots_0.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[0].brupdate.b2.uop.fp_ctrl.ldst connect slots_0.io.brupdate.b2.uop.op2_sel, issue_slots[0].brupdate.b2.uop.op2_sel connect slots_0.io.brupdate.b2.uop.op1_sel, issue_slots[0].brupdate.b2.uop.op1_sel connect slots_0.io.brupdate.b2.uop.imm_packed, issue_slots[0].brupdate.b2.uop.imm_packed connect slots_0.io.brupdate.b2.uop.pimm, issue_slots[0].brupdate.b2.uop.pimm connect slots_0.io.brupdate.b2.uop.imm_sel, issue_slots[0].brupdate.b2.uop.imm_sel connect slots_0.io.brupdate.b2.uop.imm_rename, issue_slots[0].brupdate.b2.uop.imm_rename connect slots_0.io.brupdate.b2.uop.taken, issue_slots[0].brupdate.b2.uop.taken connect slots_0.io.brupdate.b2.uop.pc_lob, issue_slots[0].brupdate.b2.uop.pc_lob connect slots_0.io.brupdate.b2.uop.edge_inst, issue_slots[0].brupdate.b2.uop.edge_inst connect slots_0.io.brupdate.b2.uop.ftq_idx, issue_slots[0].brupdate.b2.uop.ftq_idx connect slots_0.io.brupdate.b2.uop.is_mov, issue_slots[0].brupdate.b2.uop.is_mov connect slots_0.io.brupdate.b2.uop.is_rocc, issue_slots[0].brupdate.b2.uop.is_rocc connect slots_0.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[0].brupdate.b2.uop.is_sys_pc2epc connect slots_0.io.brupdate.b2.uop.is_eret, issue_slots[0].brupdate.b2.uop.is_eret connect slots_0.io.brupdate.b2.uop.is_amo, issue_slots[0].brupdate.b2.uop.is_amo connect slots_0.io.brupdate.b2.uop.is_sfence, issue_slots[0].brupdate.b2.uop.is_sfence connect slots_0.io.brupdate.b2.uop.is_fencei, issue_slots[0].brupdate.b2.uop.is_fencei connect slots_0.io.brupdate.b2.uop.is_fence, issue_slots[0].brupdate.b2.uop.is_fence connect slots_0.io.brupdate.b2.uop.is_sfb, issue_slots[0].brupdate.b2.uop.is_sfb connect slots_0.io.brupdate.b2.uop.br_type, issue_slots[0].brupdate.b2.uop.br_type connect slots_0.io.brupdate.b2.uop.br_tag, issue_slots[0].brupdate.b2.uop.br_tag connect slots_0.io.brupdate.b2.uop.br_mask, issue_slots[0].brupdate.b2.uop.br_mask connect slots_0.io.brupdate.b2.uop.dis_col_sel, issue_slots[0].brupdate.b2.uop.dis_col_sel connect slots_0.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p3_bypass_hint connect slots_0.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p2_bypass_hint connect slots_0.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[0].brupdate.b2.uop.iw_p1_bypass_hint connect slots_0.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[0].brupdate.b2.uop.iw_p2_speculative_child connect slots_0.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[0].brupdate.b2.uop.iw_p1_speculative_child connect slots_0.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[0].brupdate.b2.uop.iw_issued_partial_dgen connect slots_0.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[0].brupdate.b2.uop.iw_issued_partial_agen connect slots_0.io.brupdate.b2.uop.iw_issued, issue_slots[0].brupdate.b2.uop.iw_issued connect slots_0.io.brupdate.b2.uop.fu_code[0], issue_slots[0].brupdate.b2.uop.fu_code[0] connect slots_0.io.brupdate.b2.uop.fu_code[1], issue_slots[0].brupdate.b2.uop.fu_code[1] connect slots_0.io.brupdate.b2.uop.fu_code[2], issue_slots[0].brupdate.b2.uop.fu_code[2] connect slots_0.io.brupdate.b2.uop.fu_code[3], issue_slots[0].brupdate.b2.uop.fu_code[3] connect slots_0.io.brupdate.b2.uop.fu_code[4], issue_slots[0].brupdate.b2.uop.fu_code[4] connect slots_0.io.brupdate.b2.uop.fu_code[5], issue_slots[0].brupdate.b2.uop.fu_code[5] connect slots_0.io.brupdate.b2.uop.fu_code[6], issue_slots[0].brupdate.b2.uop.fu_code[6] connect slots_0.io.brupdate.b2.uop.fu_code[7], issue_slots[0].brupdate.b2.uop.fu_code[7] connect slots_0.io.brupdate.b2.uop.fu_code[8], issue_slots[0].brupdate.b2.uop.fu_code[8] connect slots_0.io.brupdate.b2.uop.fu_code[9], issue_slots[0].brupdate.b2.uop.fu_code[9] connect slots_0.io.brupdate.b2.uop.iq_type[0], issue_slots[0].brupdate.b2.uop.iq_type[0] connect slots_0.io.brupdate.b2.uop.iq_type[1], issue_slots[0].brupdate.b2.uop.iq_type[1] connect slots_0.io.brupdate.b2.uop.iq_type[2], issue_slots[0].brupdate.b2.uop.iq_type[2] connect slots_0.io.brupdate.b2.uop.iq_type[3], issue_slots[0].brupdate.b2.uop.iq_type[3] connect slots_0.io.brupdate.b2.uop.debug_pc, issue_slots[0].brupdate.b2.uop.debug_pc connect slots_0.io.brupdate.b2.uop.is_rvc, issue_slots[0].brupdate.b2.uop.is_rvc connect slots_0.io.brupdate.b2.uop.debug_inst, issue_slots[0].brupdate.b2.uop.debug_inst connect slots_0.io.brupdate.b2.uop.inst, issue_slots[0].brupdate.b2.uop.inst connect slots_0.io.brupdate.b1.mispredict_mask, issue_slots[0].brupdate.b1.mispredict_mask connect slots_0.io.brupdate.b1.resolve_mask, issue_slots[0].brupdate.b1.resolve_mask connect issue_slots[0].out_uop.debug_tsrc, slots_0.io.out_uop.debug_tsrc connect issue_slots[0].out_uop.debug_fsrc, slots_0.io.out_uop.debug_fsrc connect issue_slots[0].out_uop.bp_xcpt_if, slots_0.io.out_uop.bp_xcpt_if connect issue_slots[0].out_uop.bp_debug_if, slots_0.io.out_uop.bp_debug_if connect issue_slots[0].out_uop.xcpt_ma_if, slots_0.io.out_uop.xcpt_ma_if connect issue_slots[0].out_uop.xcpt_ae_if, slots_0.io.out_uop.xcpt_ae_if connect issue_slots[0].out_uop.xcpt_pf_if, slots_0.io.out_uop.xcpt_pf_if connect issue_slots[0].out_uop.fp_typ, slots_0.io.out_uop.fp_typ connect issue_slots[0].out_uop.fp_rm, slots_0.io.out_uop.fp_rm connect issue_slots[0].out_uop.fp_val, slots_0.io.out_uop.fp_val connect issue_slots[0].out_uop.fcn_op, slots_0.io.out_uop.fcn_op connect issue_slots[0].out_uop.fcn_dw, slots_0.io.out_uop.fcn_dw connect issue_slots[0].out_uop.frs3_en, slots_0.io.out_uop.frs3_en connect issue_slots[0].out_uop.lrs2_rtype, slots_0.io.out_uop.lrs2_rtype connect issue_slots[0].out_uop.lrs1_rtype, slots_0.io.out_uop.lrs1_rtype connect issue_slots[0].out_uop.dst_rtype, slots_0.io.out_uop.dst_rtype connect issue_slots[0].out_uop.lrs3, slots_0.io.out_uop.lrs3 connect issue_slots[0].out_uop.lrs2, slots_0.io.out_uop.lrs2 connect issue_slots[0].out_uop.lrs1, slots_0.io.out_uop.lrs1 connect issue_slots[0].out_uop.ldst, slots_0.io.out_uop.ldst connect issue_slots[0].out_uop.ldst_is_rs1, slots_0.io.out_uop.ldst_is_rs1 connect issue_slots[0].out_uop.csr_cmd, slots_0.io.out_uop.csr_cmd connect issue_slots[0].out_uop.flush_on_commit, slots_0.io.out_uop.flush_on_commit connect issue_slots[0].out_uop.is_unique, slots_0.io.out_uop.is_unique connect issue_slots[0].out_uop.uses_stq, slots_0.io.out_uop.uses_stq connect issue_slots[0].out_uop.uses_ldq, slots_0.io.out_uop.uses_ldq connect issue_slots[0].out_uop.mem_signed, slots_0.io.out_uop.mem_signed connect issue_slots[0].out_uop.mem_size, slots_0.io.out_uop.mem_size connect issue_slots[0].out_uop.mem_cmd, slots_0.io.out_uop.mem_cmd connect issue_slots[0].out_uop.exc_cause, slots_0.io.out_uop.exc_cause connect issue_slots[0].out_uop.exception, slots_0.io.out_uop.exception connect issue_slots[0].out_uop.stale_pdst, slots_0.io.out_uop.stale_pdst connect issue_slots[0].out_uop.ppred_busy, slots_0.io.out_uop.ppred_busy connect issue_slots[0].out_uop.prs3_busy, slots_0.io.out_uop.prs3_busy connect issue_slots[0].out_uop.prs2_busy, slots_0.io.out_uop.prs2_busy connect issue_slots[0].out_uop.prs1_busy, slots_0.io.out_uop.prs1_busy connect issue_slots[0].out_uop.ppred, slots_0.io.out_uop.ppred connect issue_slots[0].out_uop.prs3, slots_0.io.out_uop.prs3 connect issue_slots[0].out_uop.prs2, slots_0.io.out_uop.prs2 connect issue_slots[0].out_uop.prs1, slots_0.io.out_uop.prs1 connect issue_slots[0].out_uop.pdst, slots_0.io.out_uop.pdst connect issue_slots[0].out_uop.rxq_idx, slots_0.io.out_uop.rxq_idx connect issue_slots[0].out_uop.stq_idx, slots_0.io.out_uop.stq_idx connect issue_slots[0].out_uop.ldq_idx, slots_0.io.out_uop.ldq_idx connect issue_slots[0].out_uop.rob_idx, slots_0.io.out_uop.rob_idx connect issue_slots[0].out_uop.fp_ctrl.vec, slots_0.io.out_uop.fp_ctrl.vec connect issue_slots[0].out_uop.fp_ctrl.wflags, slots_0.io.out_uop.fp_ctrl.wflags connect issue_slots[0].out_uop.fp_ctrl.sqrt, slots_0.io.out_uop.fp_ctrl.sqrt connect issue_slots[0].out_uop.fp_ctrl.div, slots_0.io.out_uop.fp_ctrl.div connect issue_slots[0].out_uop.fp_ctrl.fma, slots_0.io.out_uop.fp_ctrl.fma connect issue_slots[0].out_uop.fp_ctrl.fastpipe, slots_0.io.out_uop.fp_ctrl.fastpipe connect issue_slots[0].out_uop.fp_ctrl.toint, slots_0.io.out_uop.fp_ctrl.toint connect issue_slots[0].out_uop.fp_ctrl.fromint, slots_0.io.out_uop.fp_ctrl.fromint connect issue_slots[0].out_uop.fp_ctrl.typeTagOut, slots_0.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[0].out_uop.fp_ctrl.typeTagIn, slots_0.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[0].out_uop.fp_ctrl.swap23, slots_0.io.out_uop.fp_ctrl.swap23 connect issue_slots[0].out_uop.fp_ctrl.swap12, slots_0.io.out_uop.fp_ctrl.swap12 connect issue_slots[0].out_uop.fp_ctrl.ren3, slots_0.io.out_uop.fp_ctrl.ren3 connect issue_slots[0].out_uop.fp_ctrl.ren2, slots_0.io.out_uop.fp_ctrl.ren2 connect issue_slots[0].out_uop.fp_ctrl.ren1, slots_0.io.out_uop.fp_ctrl.ren1 connect issue_slots[0].out_uop.fp_ctrl.wen, slots_0.io.out_uop.fp_ctrl.wen connect issue_slots[0].out_uop.fp_ctrl.ldst, slots_0.io.out_uop.fp_ctrl.ldst connect issue_slots[0].out_uop.op2_sel, slots_0.io.out_uop.op2_sel connect issue_slots[0].out_uop.op1_sel, slots_0.io.out_uop.op1_sel connect issue_slots[0].out_uop.imm_packed, slots_0.io.out_uop.imm_packed connect issue_slots[0].out_uop.pimm, slots_0.io.out_uop.pimm connect issue_slots[0].out_uop.imm_sel, slots_0.io.out_uop.imm_sel connect issue_slots[0].out_uop.imm_rename, slots_0.io.out_uop.imm_rename connect issue_slots[0].out_uop.taken, slots_0.io.out_uop.taken connect issue_slots[0].out_uop.pc_lob, slots_0.io.out_uop.pc_lob connect issue_slots[0].out_uop.edge_inst, slots_0.io.out_uop.edge_inst connect issue_slots[0].out_uop.ftq_idx, slots_0.io.out_uop.ftq_idx connect issue_slots[0].out_uop.is_mov, slots_0.io.out_uop.is_mov connect issue_slots[0].out_uop.is_rocc, slots_0.io.out_uop.is_rocc connect issue_slots[0].out_uop.is_sys_pc2epc, slots_0.io.out_uop.is_sys_pc2epc connect issue_slots[0].out_uop.is_eret, slots_0.io.out_uop.is_eret connect issue_slots[0].out_uop.is_amo, slots_0.io.out_uop.is_amo connect issue_slots[0].out_uop.is_sfence, slots_0.io.out_uop.is_sfence connect issue_slots[0].out_uop.is_fencei, slots_0.io.out_uop.is_fencei connect issue_slots[0].out_uop.is_fence, slots_0.io.out_uop.is_fence connect issue_slots[0].out_uop.is_sfb, slots_0.io.out_uop.is_sfb connect issue_slots[0].out_uop.br_type, slots_0.io.out_uop.br_type connect issue_slots[0].out_uop.br_tag, slots_0.io.out_uop.br_tag connect issue_slots[0].out_uop.br_mask, slots_0.io.out_uop.br_mask connect issue_slots[0].out_uop.dis_col_sel, slots_0.io.out_uop.dis_col_sel connect issue_slots[0].out_uop.iw_p3_bypass_hint, slots_0.io.out_uop.iw_p3_bypass_hint connect issue_slots[0].out_uop.iw_p2_bypass_hint, slots_0.io.out_uop.iw_p2_bypass_hint connect issue_slots[0].out_uop.iw_p1_bypass_hint, slots_0.io.out_uop.iw_p1_bypass_hint connect issue_slots[0].out_uop.iw_p2_speculative_child, slots_0.io.out_uop.iw_p2_speculative_child connect issue_slots[0].out_uop.iw_p1_speculative_child, slots_0.io.out_uop.iw_p1_speculative_child connect issue_slots[0].out_uop.iw_issued_partial_dgen, slots_0.io.out_uop.iw_issued_partial_dgen connect issue_slots[0].out_uop.iw_issued_partial_agen, slots_0.io.out_uop.iw_issued_partial_agen connect issue_slots[0].out_uop.iw_issued, slots_0.io.out_uop.iw_issued connect issue_slots[0].out_uop.fu_code[0], slots_0.io.out_uop.fu_code[0] connect issue_slots[0].out_uop.fu_code[1], slots_0.io.out_uop.fu_code[1] connect issue_slots[0].out_uop.fu_code[2], slots_0.io.out_uop.fu_code[2] connect issue_slots[0].out_uop.fu_code[3], slots_0.io.out_uop.fu_code[3] connect issue_slots[0].out_uop.fu_code[4], slots_0.io.out_uop.fu_code[4] connect issue_slots[0].out_uop.fu_code[5], slots_0.io.out_uop.fu_code[5] connect issue_slots[0].out_uop.fu_code[6], slots_0.io.out_uop.fu_code[6] connect issue_slots[0].out_uop.fu_code[7], slots_0.io.out_uop.fu_code[7] connect issue_slots[0].out_uop.fu_code[8], slots_0.io.out_uop.fu_code[8] connect issue_slots[0].out_uop.fu_code[9], slots_0.io.out_uop.fu_code[9] connect issue_slots[0].out_uop.iq_type[0], slots_0.io.out_uop.iq_type[0] connect issue_slots[0].out_uop.iq_type[1], slots_0.io.out_uop.iq_type[1] connect issue_slots[0].out_uop.iq_type[2], slots_0.io.out_uop.iq_type[2] connect issue_slots[0].out_uop.iq_type[3], slots_0.io.out_uop.iq_type[3] connect issue_slots[0].out_uop.debug_pc, slots_0.io.out_uop.debug_pc connect issue_slots[0].out_uop.is_rvc, slots_0.io.out_uop.is_rvc connect issue_slots[0].out_uop.debug_inst, slots_0.io.out_uop.debug_inst connect issue_slots[0].out_uop.inst, slots_0.io.out_uop.inst connect slots_0.io.in_uop.bits.debug_tsrc, issue_slots[0].in_uop.bits.debug_tsrc connect slots_0.io.in_uop.bits.debug_fsrc, issue_slots[0].in_uop.bits.debug_fsrc connect slots_0.io.in_uop.bits.bp_xcpt_if, issue_slots[0].in_uop.bits.bp_xcpt_if connect slots_0.io.in_uop.bits.bp_debug_if, issue_slots[0].in_uop.bits.bp_debug_if connect slots_0.io.in_uop.bits.xcpt_ma_if, issue_slots[0].in_uop.bits.xcpt_ma_if connect slots_0.io.in_uop.bits.xcpt_ae_if, issue_slots[0].in_uop.bits.xcpt_ae_if connect slots_0.io.in_uop.bits.xcpt_pf_if, issue_slots[0].in_uop.bits.xcpt_pf_if connect slots_0.io.in_uop.bits.fp_typ, issue_slots[0].in_uop.bits.fp_typ connect slots_0.io.in_uop.bits.fp_rm, issue_slots[0].in_uop.bits.fp_rm connect slots_0.io.in_uop.bits.fp_val, issue_slots[0].in_uop.bits.fp_val connect slots_0.io.in_uop.bits.fcn_op, issue_slots[0].in_uop.bits.fcn_op connect slots_0.io.in_uop.bits.fcn_dw, issue_slots[0].in_uop.bits.fcn_dw connect slots_0.io.in_uop.bits.frs3_en, issue_slots[0].in_uop.bits.frs3_en connect slots_0.io.in_uop.bits.lrs2_rtype, issue_slots[0].in_uop.bits.lrs2_rtype connect slots_0.io.in_uop.bits.lrs1_rtype, issue_slots[0].in_uop.bits.lrs1_rtype connect slots_0.io.in_uop.bits.dst_rtype, issue_slots[0].in_uop.bits.dst_rtype connect slots_0.io.in_uop.bits.lrs3, issue_slots[0].in_uop.bits.lrs3 connect slots_0.io.in_uop.bits.lrs2, issue_slots[0].in_uop.bits.lrs2 connect slots_0.io.in_uop.bits.lrs1, issue_slots[0].in_uop.bits.lrs1 connect slots_0.io.in_uop.bits.ldst, issue_slots[0].in_uop.bits.ldst connect slots_0.io.in_uop.bits.ldst_is_rs1, issue_slots[0].in_uop.bits.ldst_is_rs1 connect slots_0.io.in_uop.bits.csr_cmd, issue_slots[0].in_uop.bits.csr_cmd connect slots_0.io.in_uop.bits.flush_on_commit, issue_slots[0].in_uop.bits.flush_on_commit connect slots_0.io.in_uop.bits.is_unique, issue_slots[0].in_uop.bits.is_unique connect slots_0.io.in_uop.bits.uses_stq, issue_slots[0].in_uop.bits.uses_stq connect slots_0.io.in_uop.bits.uses_ldq, issue_slots[0].in_uop.bits.uses_ldq connect slots_0.io.in_uop.bits.mem_signed, issue_slots[0].in_uop.bits.mem_signed connect slots_0.io.in_uop.bits.mem_size, issue_slots[0].in_uop.bits.mem_size connect slots_0.io.in_uop.bits.mem_cmd, issue_slots[0].in_uop.bits.mem_cmd connect slots_0.io.in_uop.bits.exc_cause, issue_slots[0].in_uop.bits.exc_cause connect slots_0.io.in_uop.bits.exception, issue_slots[0].in_uop.bits.exception connect slots_0.io.in_uop.bits.stale_pdst, issue_slots[0].in_uop.bits.stale_pdst connect slots_0.io.in_uop.bits.ppred_busy, issue_slots[0].in_uop.bits.ppred_busy connect slots_0.io.in_uop.bits.prs3_busy, issue_slots[0].in_uop.bits.prs3_busy connect slots_0.io.in_uop.bits.prs2_busy, issue_slots[0].in_uop.bits.prs2_busy connect slots_0.io.in_uop.bits.prs1_busy, issue_slots[0].in_uop.bits.prs1_busy connect slots_0.io.in_uop.bits.ppred, issue_slots[0].in_uop.bits.ppred connect slots_0.io.in_uop.bits.prs3, issue_slots[0].in_uop.bits.prs3 connect slots_0.io.in_uop.bits.prs2, issue_slots[0].in_uop.bits.prs2 connect slots_0.io.in_uop.bits.prs1, issue_slots[0].in_uop.bits.prs1 connect slots_0.io.in_uop.bits.pdst, issue_slots[0].in_uop.bits.pdst connect slots_0.io.in_uop.bits.rxq_idx, issue_slots[0].in_uop.bits.rxq_idx connect slots_0.io.in_uop.bits.stq_idx, issue_slots[0].in_uop.bits.stq_idx connect slots_0.io.in_uop.bits.ldq_idx, issue_slots[0].in_uop.bits.ldq_idx connect slots_0.io.in_uop.bits.rob_idx, issue_slots[0].in_uop.bits.rob_idx connect slots_0.io.in_uop.bits.fp_ctrl.vec, issue_slots[0].in_uop.bits.fp_ctrl.vec connect slots_0.io.in_uop.bits.fp_ctrl.wflags, issue_slots[0].in_uop.bits.fp_ctrl.wflags connect slots_0.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[0].in_uop.bits.fp_ctrl.sqrt connect slots_0.io.in_uop.bits.fp_ctrl.div, issue_slots[0].in_uop.bits.fp_ctrl.div connect slots_0.io.in_uop.bits.fp_ctrl.fma, issue_slots[0].in_uop.bits.fp_ctrl.fma connect slots_0.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[0].in_uop.bits.fp_ctrl.fastpipe connect slots_0.io.in_uop.bits.fp_ctrl.toint, issue_slots[0].in_uop.bits.fp_ctrl.toint connect slots_0.io.in_uop.bits.fp_ctrl.fromint, issue_slots[0].in_uop.bits.fp_ctrl.fromint connect slots_0.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut connect slots_0.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn connect slots_0.io.in_uop.bits.fp_ctrl.swap23, issue_slots[0].in_uop.bits.fp_ctrl.swap23 connect slots_0.io.in_uop.bits.fp_ctrl.swap12, issue_slots[0].in_uop.bits.fp_ctrl.swap12 connect slots_0.io.in_uop.bits.fp_ctrl.ren3, issue_slots[0].in_uop.bits.fp_ctrl.ren3 connect slots_0.io.in_uop.bits.fp_ctrl.ren2, issue_slots[0].in_uop.bits.fp_ctrl.ren2 connect slots_0.io.in_uop.bits.fp_ctrl.ren1, issue_slots[0].in_uop.bits.fp_ctrl.ren1 connect slots_0.io.in_uop.bits.fp_ctrl.wen, issue_slots[0].in_uop.bits.fp_ctrl.wen connect slots_0.io.in_uop.bits.fp_ctrl.ldst, issue_slots[0].in_uop.bits.fp_ctrl.ldst connect slots_0.io.in_uop.bits.op2_sel, issue_slots[0].in_uop.bits.op2_sel connect slots_0.io.in_uop.bits.op1_sel, issue_slots[0].in_uop.bits.op1_sel connect slots_0.io.in_uop.bits.imm_packed, issue_slots[0].in_uop.bits.imm_packed connect slots_0.io.in_uop.bits.pimm, issue_slots[0].in_uop.bits.pimm connect slots_0.io.in_uop.bits.imm_sel, issue_slots[0].in_uop.bits.imm_sel connect slots_0.io.in_uop.bits.imm_rename, issue_slots[0].in_uop.bits.imm_rename connect slots_0.io.in_uop.bits.taken, issue_slots[0].in_uop.bits.taken connect slots_0.io.in_uop.bits.pc_lob, issue_slots[0].in_uop.bits.pc_lob connect slots_0.io.in_uop.bits.edge_inst, issue_slots[0].in_uop.bits.edge_inst connect slots_0.io.in_uop.bits.ftq_idx, issue_slots[0].in_uop.bits.ftq_idx connect slots_0.io.in_uop.bits.is_mov, issue_slots[0].in_uop.bits.is_mov connect slots_0.io.in_uop.bits.is_rocc, issue_slots[0].in_uop.bits.is_rocc connect slots_0.io.in_uop.bits.is_sys_pc2epc, issue_slots[0].in_uop.bits.is_sys_pc2epc connect slots_0.io.in_uop.bits.is_eret, issue_slots[0].in_uop.bits.is_eret connect slots_0.io.in_uop.bits.is_amo, issue_slots[0].in_uop.bits.is_amo connect slots_0.io.in_uop.bits.is_sfence, issue_slots[0].in_uop.bits.is_sfence connect slots_0.io.in_uop.bits.is_fencei, issue_slots[0].in_uop.bits.is_fencei connect slots_0.io.in_uop.bits.is_fence, issue_slots[0].in_uop.bits.is_fence connect slots_0.io.in_uop.bits.is_sfb, issue_slots[0].in_uop.bits.is_sfb connect slots_0.io.in_uop.bits.br_type, issue_slots[0].in_uop.bits.br_type connect slots_0.io.in_uop.bits.br_tag, issue_slots[0].in_uop.bits.br_tag connect slots_0.io.in_uop.bits.br_mask, issue_slots[0].in_uop.bits.br_mask connect slots_0.io.in_uop.bits.dis_col_sel, issue_slots[0].in_uop.bits.dis_col_sel connect slots_0.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[0].in_uop.bits.iw_p3_bypass_hint connect slots_0.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[0].in_uop.bits.iw_p2_bypass_hint connect slots_0.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[0].in_uop.bits.iw_p1_bypass_hint connect slots_0.io.in_uop.bits.iw_p2_speculative_child, issue_slots[0].in_uop.bits.iw_p2_speculative_child connect slots_0.io.in_uop.bits.iw_p1_speculative_child, issue_slots[0].in_uop.bits.iw_p1_speculative_child connect slots_0.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[0].in_uop.bits.iw_issued_partial_dgen connect slots_0.io.in_uop.bits.iw_issued_partial_agen, issue_slots[0].in_uop.bits.iw_issued_partial_agen connect slots_0.io.in_uop.bits.iw_issued, issue_slots[0].in_uop.bits.iw_issued connect slots_0.io.in_uop.bits.fu_code[0], issue_slots[0].in_uop.bits.fu_code[0] connect slots_0.io.in_uop.bits.fu_code[1], issue_slots[0].in_uop.bits.fu_code[1] connect slots_0.io.in_uop.bits.fu_code[2], issue_slots[0].in_uop.bits.fu_code[2] connect slots_0.io.in_uop.bits.fu_code[3], issue_slots[0].in_uop.bits.fu_code[3] connect slots_0.io.in_uop.bits.fu_code[4], issue_slots[0].in_uop.bits.fu_code[4] connect slots_0.io.in_uop.bits.fu_code[5], issue_slots[0].in_uop.bits.fu_code[5] connect slots_0.io.in_uop.bits.fu_code[6], issue_slots[0].in_uop.bits.fu_code[6] connect slots_0.io.in_uop.bits.fu_code[7], issue_slots[0].in_uop.bits.fu_code[7] connect slots_0.io.in_uop.bits.fu_code[8], issue_slots[0].in_uop.bits.fu_code[8] connect slots_0.io.in_uop.bits.fu_code[9], issue_slots[0].in_uop.bits.fu_code[9] connect slots_0.io.in_uop.bits.iq_type[0], issue_slots[0].in_uop.bits.iq_type[0] connect slots_0.io.in_uop.bits.iq_type[1], issue_slots[0].in_uop.bits.iq_type[1] connect slots_0.io.in_uop.bits.iq_type[2], issue_slots[0].in_uop.bits.iq_type[2] connect slots_0.io.in_uop.bits.iq_type[3], issue_slots[0].in_uop.bits.iq_type[3] connect slots_0.io.in_uop.bits.debug_pc, issue_slots[0].in_uop.bits.debug_pc connect slots_0.io.in_uop.bits.is_rvc, issue_slots[0].in_uop.bits.is_rvc connect slots_0.io.in_uop.bits.debug_inst, issue_slots[0].in_uop.bits.debug_inst connect slots_0.io.in_uop.bits.inst, issue_slots[0].in_uop.bits.inst connect slots_0.io.in_uop.valid, issue_slots[0].in_uop.valid connect issue_slots[0].iss_uop.debug_tsrc, slots_0.io.iss_uop.debug_tsrc connect issue_slots[0].iss_uop.debug_fsrc, slots_0.io.iss_uop.debug_fsrc connect issue_slots[0].iss_uop.bp_xcpt_if, slots_0.io.iss_uop.bp_xcpt_if connect issue_slots[0].iss_uop.bp_debug_if, slots_0.io.iss_uop.bp_debug_if connect issue_slots[0].iss_uop.xcpt_ma_if, slots_0.io.iss_uop.xcpt_ma_if connect issue_slots[0].iss_uop.xcpt_ae_if, slots_0.io.iss_uop.xcpt_ae_if connect issue_slots[0].iss_uop.xcpt_pf_if, slots_0.io.iss_uop.xcpt_pf_if connect issue_slots[0].iss_uop.fp_typ, slots_0.io.iss_uop.fp_typ connect issue_slots[0].iss_uop.fp_rm, slots_0.io.iss_uop.fp_rm connect issue_slots[0].iss_uop.fp_val, slots_0.io.iss_uop.fp_val connect issue_slots[0].iss_uop.fcn_op, slots_0.io.iss_uop.fcn_op connect issue_slots[0].iss_uop.fcn_dw, slots_0.io.iss_uop.fcn_dw connect issue_slots[0].iss_uop.frs3_en, slots_0.io.iss_uop.frs3_en connect issue_slots[0].iss_uop.lrs2_rtype, slots_0.io.iss_uop.lrs2_rtype connect issue_slots[0].iss_uop.lrs1_rtype, slots_0.io.iss_uop.lrs1_rtype connect issue_slots[0].iss_uop.dst_rtype, slots_0.io.iss_uop.dst_rtype connect issue_slots[0].iss_uop.lrs3, slots_0.io.iss_uop.lrs3 connect issue_slots[0].iss_uop.lrs2, slots_0.io.iss_uop.lrs2 connect issue_slots[0].iss_uop.lrs1, slots_0.io.iss_uop.lrs1 connect issue_slots[0].iss_uop.ldst, slots_0.io.iss_uop.ldst connect issue_slots[0].iss_uop.ldst_is_rs1, slots_0.io.iss_uop.ldst_is_rs1 connect issue_slots[0].iss_uop.csr_cmd, slots_0.io.iss_uop.csr_cmd connect issue_slots[0].iss_uop.flush_on_commit, slots_0.io.iss_uop.flush_on_commit connect issue_slots[0].iss_uop.is_unique, slots_0.io.iss_uop.is_unique connect issue_slots[0].iss_uop.uses_stq, slots_0.io.iss_uop.uses_stq connect issue_slots[0].iss_uop.uses_ldq, slots_0.io.iss_uop.uses_ldq connect issue_slots[0].iss_uop.mem_signed, slots_0.io.iss_uop.mem_signed connect issue_slots[0].iss_uop.mem_size, slots_0.io.iss_uop.mem_size connect issue_slots[0].iss_uop.mem_cmd, slots_0.io.iss_uop.mem_cmd connect issue_slots[0].iss_uop.exc_cause, slots_0.io.iss_uop.exc_cause connect issue_slots[0].iss_uop.exception, slots_0.io.iss_uop.exception connect issue_slots[0].iss_uop.stale_pdst, slots_0.io.iss_uop.stale_pdst connect issue_slots[0].iss_uop.ppred_busy, slots_0.io.iss_uop.ppred_busy connect issue_slots[0].iss_uop.prs3_busy, slots_0.io.iss_uop.prs3_busy connect issue_slots[0].iss_uop.prs2_busy, slots_0.io.iss_uop.prs2_busy connect issue_slots[0].iss_uop.prs1_busy, slots_0.io.iss_uop.prs1_busy connect issue_slots[0].iss_uop.ppred, slots_0.io.iss_uop.ppred connect issue_slots[0].iss_uop.prs3, slots_0.io.iss_uop.prs3 connect issue_slots[0].iss_uop.prs2, slots_0.io.iss_uop.prs2 connect issue_slots[0].iss_uop.prs1, slots_0.io.iss_uop.prs1 connect issue_slots[0].iss_uop.pdst, slots_0.io.iss_uop.pdst connect issue_slots[0].iss_uop.rxq_idx, slots_0.io.iss_uop.rxq_idx connect issue_slots[0].iss_uop.stq_idx, slots_0.io.iss_uop.stq_idx connect issue_slots[0].iss_uop.ldq_idx, slots_0.io.iss_uop.ldq_idx connect issue_slots[0].iss_uop.rob_idx, slots_0.io.iss_uop.rob_idx connect issue_slots[0].iss_uop.fp_ctrl.vec, slots_0.io.iss_uop.fp_ctrl.vec connect issue_slots[0].iss_uop.fp_ctrl.wflags, slots_0.io.iss_uop.fp_ctrl.wflags connect issue_slots[0].iss_uop.fp_ctrl.sqrt, slots_0.io.iss_uop.fp_ctrl.sqrt connect issue_slots[0].iss_uop.fp_ctrl.div, slots_0.io.iss_uop.fp_ctrl.div connect issue_slots[0].iss_uop.fp_ctrl.fma, slots_0.io.iss_uop.fp_ctrl.fma connect issue_slots[0].iss_uop.fp_ctrl.fastpipe, slots_0.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[0].iss_uop.fp_ctrl.toint, slots_0.io.iss_uop.fp_ctrl.toint connect issue_slots[0].iss_uop.fp_ctrl.fromint, slots_0.io.iss_uop.fp_ctrl.fromint connect issue_slots[0].iss_uop.fp_ctrl.typeTagOut, slots_0.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[0].iss_uop.fp_ctrl.typeTagIn, slots_0.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[0].iss_uop.fp_ctrl.swap23, slots_0.io.iss_uop.fp_ctrl.swap23 connect issue_slots[0].iss_uop.fp_ctrl.swap12, slots_0.io.iss_uop.fp_ctrl.swap12 connect issue_slots[0].iss_uop.fp_ctrl.ren3, slots_0.io.iss_uop.fp_ctrl.ren3 connect issue_slots[0].iss_uop.fp_ctrl.ren2, slots_0.io.iss_uop.fp_ctrl.ren2 connect issue_slots[0].iss_uop.fp_ctrl.ren1, slots_0.io.iss_uop.fp_ctrl.ren1 connect issue_slots[0].iss_uop.fp_ctrl.wen, slots_0.io.iss_uop.fp_ctrl.wen connect issue_slots[0].iss_uop.fp_ctrl.ldst, slots_0.io.iss_uop.fp_ctrl.ldst connect issue_slots[0].iss_uop.op2_sel, slots_0.io.iss_uop.op2_sel connect issue_slots[0].iss_uop.op1_sel, slots_0.io.iss_uop.op1_sel connect issue_slots[0].iss_uop.imm_packed, slots_0.io.iss_uop.imm_packed connect issue_slots[0].iss_uop.pimm, slots_0.io.iss_uop.pimm connect issue_slots[0].iss_uop.imm_sel, slots_0.io.iss_uop.imm_sel connect issue_slots[0].iss_uop.imm_rename, slots_0.io.iss_uop.imm_rename connect issue_slots[0].iss_uop.taken, slots_0.io.iss_uop.taken connect issue_slots[0].iss_uop.pc_lob, slots_0.io.iss_uop.pc_lob connect issue_slots[0].iss_uop.edge_inst, slots_0.io.iss_uop.edge_inst connect issue_slots[0].iss_uop.ftq_idx, slots_0.io.iss_uop.ftq_idx connect issue_slots[0].iss_uop.is_mov, slots_0.io.iss_uop.is_mov connect issue_slots[0].iss_uop.is_rocc, slots_0.io.iss_uop.is_rocc connect issue_slots[0].iss_uop.is_sys_pc2epc, slots_0.io.iss_uop.is_sys_pc2epc connect issue_slots[0].iss_uop.is_eret, slots_0.io.iss_uop.is_eret connect issue_slots[0].iss_uop.is_amo, slots_0.io.iss_uop.is_amo connect issue_slots[0].iss_uop.is_sfence, slots_0.io.iss_uop.is_sfence connect issue_slots[0].iss_uop.is_fencei, slots_0.io.iss_uop.is_fencei connect issue_slots[0].iss_uop.is_fence, slots_0.io.iss_uop.is_fence connect issue_slots[0].iss_uop.is_sfb, slots_0.io.iss_uop.is_sfb connect issue_slots[0].iss_uop.br_type, slots_0.io.iss_uop.br_type connect issue_slots[0].iss_uop.br_tag, slots_0.io.iss_uop.br_tag connect issue_slots[0].iss_uop.br_mask, slots_0.io.iss_uop.br_mask connect issue_slots[0].iss_uop.dis_col_sel, slots_0.io.iss_uop.dis_col_sel connect issue_slots[0].iss_uop.iw_p3_bypass_hint, slots_0.io.iss_uop.iw_p3_bypass_hint connect issue_slots[0].iss_uop.iw_p2_bypass_hint, slots_0.io.iss_uop.iw_p2_bypass_hint connect issue_slots[0].iss_uop.iw_p1_bypass_hint, slots_0.io.iss_uop.iw_p1_bypass_hint connect issue_slots[0].iss_uop.iw_p2_speculative_child, slots_0.io.iss_uop.iw_p2_speculative_child connect issue_slots[0].iss_uop.iw_p1_speculative_child, slots_0.io.iss_uop.iw_p1_speculative_child connect issue_slots[0].iss_uop.iw_issued_partial_dgen, slots_0.io.iss_uop.iw_issued_partial_dgen connect issue_slots[0].iss_uop.iw_issued_partial_agen, slots_0.io.iss_uop.iw_issued_partial_agen connect issue_slots[0].iss_uop.iw_issued, slots_0.io.iss_uop.iw_issued connect issue_slots[0].iss_uop.fu_code[0], slots_0.io.iss_uop.fu_code[0] connect issue_slots[0].iss_uop.fu_code[1], slots_0.io.iss_uop.fu_code[1] connect issue_slots[0].iss_uop.fu_code[2], slots_0.io.iss_uop.fu_code[2] connect issue_slots[0].iss_uop.fu_code[3], slots_0.io.iss_uop.fu_code[3] connect issue_slots[0].iss_uop.fu_code[4], slots_0.io.iss_uop.fu_code[4] connect issue_slots[0].iss_uop.fu_code[5], slots_0.io.iss_uop.fu_code[5] connect issue_slots[0].iss_uop.fu_code[6], slots_0.io.iss_uop.fu_code[6] connect issue_slots[0].iss_uop.fu_code[7], slots_0.io.iss_uop.fu_code[7] connect issue_slots[0].iss_uop.fu_code[8], slots_0.io.iss_uop.fu_code[8] connect issue_slots[0].iss_uop.fu_code[9], slots_0.io.iss_uop.fu_code[9] connect issue_slots[0].iss_uop.iq_type[0], slots_0.io.iss_uop.iq_type[0] connect issue_slots[0].iss_uop.iq_type[1], slots_0.io.iss_uop.iq_type[1] connect issue_slots[0].iss_uop.iq_type[2], slots_0.io.iss_uop.iq_type[2] connect issue_slots[0].iss_uop.iq_type[3], slots_0.io.iss_uop.iq_type[3] connect issue_slots[0].iss_uop.debug_pc, slots_0.io.iss_uop.debug_pc connect issue_slots[0].iss_uop.is_rvc, slots_0.io.iss_uop.is_rvc connect issue_slots[0].iss_uop.debug_inst, slots_0.io.iss_uop.debug_inst connect issue_slots[0].iss_uop.inst, slots_0.io.iss_uop.inst connect slots_0.io.grant, issue_slots[0].grant connect issue_slots[0].request, slots_0.io.request connect issue_slots[0].will_be_valid, slots_0.io.will_be_valid connect issue_slots[0].valid, slots_0.io.valid connect slots_1.io.child_rebusys, issue_slots[1].child_rebusys connect slots_1.io.pred_wakeup_port.bits, issue_slots[1].pred_wakeup_port.bits connect slots_1.io.pred_wakeup_port.valid, issue_slots[1].pred_wakeup_port.valid connect slots_1.io.wakeup_ports[0].bits.rebusy, issue_slots[1].wakeup_ports[0].bits.rebusy connect slots_1.io.wakeup_ports[0].bits.speculative_mask, issue_slots[1].wakeup_ports[0].bits.speculative_mask connect slots_1.io.wakeup_ports[0].bits.bypassable, issue_slots[1].wakeup_ports[0].bits.bypassable connect slots_1.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[0].bits.uop.debug_tsrc connect slots_1.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[0].bits.uop.debug_fsrc connect slots_1.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_1.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[0].bits.uop.bp_debug_if connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_1.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_1.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[1].wakeup_ports[0].bits.uop.fp_typ connect slots_1.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[1].wakeup_ports[0].bits.uop.fp_rm connect slots_1.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[1].wakeup_ports[0].bits.uop.fp_val connect slots_1.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[1].wakeup_ports[0].bits.uop.fcn_op connect slots_1.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[0].bits.uop.fcn_dw connect slots_1.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[1].wakeup_ports[0].bits.uop.frs3_en connect slots_1.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_1.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_1.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[0].bits.uop.dst_rtype connect slots_1.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[1].wakeup_ports[0].bits.uop.lrs3 connect slots_1.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[1].wakeup_ports[0].bits.uop.lrs2 connect slots_1.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[1].wakeup_ports[0].bits.uop.lrs1 connect slots_1.io.wakeup_ports[0].bits.uop.ldst, issue_slots[1].wakeup_ports[0].bits.uop.ldst connect slots_1.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_1.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[0].bits.uop.csr_cmd connect slots_1.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[0].bits.uop.flush_on_commit connect slots_1.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[1].wakeup_ports[0].bits.uop.is_unique connect slots_1.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[1].wakeup_ports[0].bits.uop.uses_stq connect slots_1.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[0].bits.uop.uses_ldq connect slots_1.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[1].wakeup_ports[0].bits.uop.mem_signed connect slots_1.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[1].wakeup_ports[0].bits.uop.mem_size connect slots_1.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[0].bits.uop.mem_cmd connect slots_1.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[1].wakeup_ports[0].bits.uop.exc_cause connect slots_1.io.wakeup_ports[0].bits.uop.exception, issue_slots[1].wakeup_ports[0].bits.uop.exception connect slots_1.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[0].bits.uop.stale_pdst connect slots_1.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[0].bits.uop.ppred_busy connect slots_1.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs3_busy connect slots_1.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs2_busy connect slots_1.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[0].bits.uop.prs1_busy connect slots_1.io.wakeup_ports[0].bits.uop.ppred, issue_slots[1].wakeup_ports[0].bits.uop.ppred connect slots_1.io.wakeup_ports[0].bits.uop.prs3, issue_slots[1].wakeup_ports[0].bits.uop.prs3 connect slots_1.io.wakeup_ports[0].bits.uop.prs2, issue_slots[1].wakeup_ports[0].bits.uop.prs2 connect slots_1.io.wakeup_ports[0].bits.uop.prs1, issue_slots[1].wakeup_ports[0].bits.uop.prs1 connect slots_1.io.wakeup_ports[0].bits.uop.pdst, issue_slots[1].wakeup_ports[0].bits.uop.pdst connect slots_1.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[0].bits.uop.rxq_idx connect slots_1.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[1].wakeup_ports[0].bits.uop.stq_idx connect slots_1.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[0].bits.uop.ldq_idx connect slots_1.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[1].wakeup_ports[0].bits.uop.rob_idx connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_1.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_1.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[1].wakeup_ports[0].bits.uop.op2_sel connect slots_1.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[1].wakeup_ports[0].bits.uop.op1_sel connect slots_1.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[1].wakeup_ports[0].bits.uop.imm_packed connect slots_1.io.wakeup_ports[0].bits.uop.pimm, issue_slots[1].wakeup_ports[0].bits.uop.pimm connect slots_1.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[1].wakeup_ports[0].bits.uop.imm_sel connect slots_1.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[1].wakeup_ports[0].bits.uop.imm_rename connect slots_1.io.wakeup_ports[0].bits.uop.taken, issue_slots[1].wakeup_ports[0].bits.uop.taken connect slots_1.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[1].wakeup_ports[0].bits.uop.pc_lob connect slots_1.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[1].wakeup_ports[0].bits.uop.edge_inst connect slots_1.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[0].bits.uop.ftq_idx connect slots_1.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[1].wakeup_ports[0].bits.uop.is_mov connect slots_1.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[1].wakeup_ports[0].bits.uop.is_rocc connect slots_1.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_1.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[1].wakeup_ports[0].bits.uop.is_eret connect slots_1.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[1].wakeup_ports[0].bits.uop.is_amo connect slots_1.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[1].wakeup_ports[0].bits.uop.is_sfence connect slots_1.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[1].wakeup_ports[0].bits.uop.is_fencei connect slots_1.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[1].wakeup_ports[0].bits.uop.is_fence connect slots_1.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[1].wakeup_ports[0].bits.uop.is_sfb connect slots_1.io.wakeup_ports[0].bits.uop.br_type, issue_slots[1].wakeup_ports[0].bits.uop.br_type connect slots_1.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[1].wakeup_ports[0].bits.uop.br_tag connect slots_1.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[1].wakeup_ports[0].bits.uop.br_mask connect slots_1.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[0].bits.uop.dis_col_sel connect slots_1.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_1.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_1.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_1.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_1.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_1.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[1].wakeup_ports[0].bits.uop.iw_issued connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[0] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[1] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[2] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[3] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[4] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[5] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[6] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[7] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[8] connect slots_1.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[0].bits.uop.fu_code[9] connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[0] connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[1] connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[2] connect slots_1.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[0].bits.uop.iq_type[3] connect slots_1.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[1].wakeup_ports[0].bits.uop.debug_pc connect slots_1.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[1].wakeup_ports[0].bits.uop.is_rvc connect slots_1.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[1].wakeup_ports[0].bits.uop.debug_inst connect slots_1.io.wakeup_ports[0].bits.uop.inst, issue_slots[1].wakeup_ports[0].bits.uop.inst connect slots_1.io.wakeup_ports[0].valid, issue_slots[1].wakeup_ports[0].valid connect slots_1.io.wakeup_ports[1].bits.rebusy, issue_slots[1].wakeup_ports[1].bits.rebusy connect slots_1.io.wakeup_ports[1].bits.speculative_mask, issue_slots[1].wakeup_ports[1].bits.speculative_mask connect slots_1.io.wakeup_ports[1].bits.bypassable, issue_slots[1].wakeup_ports[1].bits.bypassable connect slots_1.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[1].wakeup_ports[1].bits.uop.debug_tsrc connect slots_1.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[1].wakeup_ports[1].bits.uop.debug_fsrc connect slots_1.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[1].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_1.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[1].wakeup_ports[1].bits.uop.bp_debug_if connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_1.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[1].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_1.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[1].wakeup_ports[1].bits.uop.fp_typ connect slots_1.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[1].wakeup_ports[1].bits.uop.fp_rm connect slots_1.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[1].wakeup_ports[1].bits.uop.fp_val connect slots_1.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[1].wakeup_ports[1].bits.uop.fcn_op connect slots_1.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[1].wakeup_ports[1].bits.uop.fcn_dw connect slots_1.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[1].wakeup_ports[1].bits.uop.frs3_en connect slots_1.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[1].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_1.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[1].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_1.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[1].wakeup_ports[1].bits.uop.dst_rtype connect slots_1.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[1].wakeup_ports[1].bits.uop.lrs3 connect slots_1.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[1].wakeup_ports[1].bits.uop.lrs2 connect slots_1.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[1].wakeup_ports[1].bits.uop.lrs1 connect slots_1.io.wakeup_ports[1].bits.uop.ldst, issue_slots[1].wakeup_ports[1].bits.uop.ldst connect slots_1.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[1].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_1.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[1].wakeup_ports[1].bits.uop.csr_cmd connect slots_1.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[1].wakeup_ports[1].bits.uop.flush_on_commit connect slots_1.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[1].wakeup_ports[1].bits.uop.is_unique connect slots_1.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[1].wakeup_ports[1].bits.uop.uses_stq connect slots_1.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[1].wakeup_ports[1].bits.uop.uses_ldq connect slots_1.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[1].wakeup_ports[1].bits.uop.mem_signed connect slots_1.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[1].wakeup_ports[1].bits.uop.mem_size connect slots_1.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[1].wakeup_ports[1].bits.uop.mem_cmd connect slots_1.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[1].wakeup_ports[1].bits.uop.exc_cause connect slots_1.io.wakeup_ports[1].bits.uop.exception, issue_slots[1].wakeup_ports[1].bits.uop.exception connect slots_1.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[1].wakeup_ports[1].bits.uop.stale_pdst connect slots_1.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[1].wakeup_ports[1].bits.uop.ppred_busy connect slots_1.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs3_busy connect slots_1.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs2_busy connect slots_1.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[1].wakeup_ports[1].bits.uop.prs1_busy connect slots_1.io.wakeup_ports[1].bits.uop.ppred, issue_slots[1].wakeup_ports[1].bits.uop.ppred connect slots_1.io.wakeup_ports[1].bits.uop.prs3, issue_slots[1].wakeup_ports[1].bits.uop.prs3 connect slots_1.io.wakeup_ports[1].bits.uop.prs2, issue_slots[1].wakeup_ports[1].bits.uop.prs2 connect slots_1.io.wakeup_ports[1].bits.uop.prs1, issue_slots[1].wakeup_ports[1].bits.uop.prs1 connect slots_1.io.wakeup_ports[1].bits.uop.pdst, issue_slots[1].wakeup_ports[1].bits.uop.pdst connect slots_1.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[1].wakeup_ports[1].bits.uop.rxq_idx connect slots_1.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[1].wakeup_ports[1].bits.uop.stq_idx connect slots_1.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[1].wakeup_ports[1].bits.uop.ldq_idx connect slots_1.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[1].wakeup_ports[1].bits.uop.rob_idx connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_1.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_1.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[1].wakeup_ports[1].bits.uop.op2_sel connect slots_1.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[1].wakeup_ports[1].bits.uop.op1_sel connect slots_1.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[1].wakeup_ports[1].bits.uop.imm_packed connect slots_1.io.wakeup_ports[1].bits.uop.pimm, issue_slots[1].wakeup_ports[1].bits.uop.pimm connect slots_1.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[1].wakeup_ports[1].bits.uop.imm_sel connect slots_1.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[1].wakeup_ports[1].bits.uop.imm_rename connect slots_1.io.wakeup_ports[1].bits.uop.taken, issue_slots[1].wakeup_ports[1].bits.uop.taken connect slots_1.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[1].wakeup_ports[1].bits.uop.pc_lob connect slots_1.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[1].wakeup_ports[1].bits.uop.edge_inst connect slots_1.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[1].wakeup_ports[1].bits.uop.ftq_idx connect slots_1.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[1].wakeup_ports[1].bits.uop.is_mov connect slots_1.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[1].wakeup_ports[1].bits.uop.is_rocc connect slots_1.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[1].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_1.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[1].wakeup_ports[1].bits.uop.is_eret connect slots_1.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[1].wakeup_ports[1].bits.uop.is_amo connect slots_1.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[1].wakeup_ports[1].bits.uop.is_sfence connect slots_1.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[1].wakeup_ports[1].bits.uop.is_fencei connect slots_1.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[1].wakeup_ports[1].bits.uop.is_fence connect slots_1.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[1].wakeup_ports[1].bits.uop.is_sfb connect slots_1.io.wakeup_ports[1].bits.uop.br_type, issue_slots[1].wakeup_ports[1].bits.uop.br_type connect slots_1.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[1].wakeup_ports[1].bits.uop.br_tag connect slots_1.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[1].wakeup_ports[1].bits.uop.br_mask connect slots_1.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[1].wakeup_ports[1].bits.uop.dis_col_sel connect slots_1.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_1.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_1.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_1.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_1.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_1.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[1].wakeup_ports[1].bits.uop.iw_issued connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[0] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[1] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[2] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[3] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[4] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[5] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[6] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[7] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[8] connect slots_1.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[1].wakeup_ports[1].bits.uop.fu_code[9] connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[0] connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[1] connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[2] connect slots_1.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[1].wakeup_ports[1].bits.uop.iq_type[3] connect slots_1.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[1].wakeup_ports[1].bits.uop.debug_pc connect slots_1.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[1].wakeup_ports[1].bits.uop.is_rvc connect slots_1.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[1].wakeup_ports[1].bits.uop.debug_inst connect slots_1.io.wakeup_ports[1].bits.uop.inst, issue_slots[1].wakeup_ports[1].bits.uop.inst connect slots_1.io.wakeup_ports[1].valid, issue_slots[1].wakeup_ports[1].valid connect slots_1.io.squash_grant, issue_slots[1].squash_grant connect slots_1.io.clear, issue_slots[1].clear connect slots_1.io.kill, issue_slots[1].kill connect slots_1.io.brupdate.b2.target_offset, issue_slots[1].brupdate.b2.target_offset connect slots_1.io.brupdate.b2.jalr_target, issue_slots[1].brupdate.b2.jalr_target connect slots_1.io.brupdate.b2.pc_sel, issue_slots[1].brupdate.b2.pc_sel connect slots_1.io.brupdate.b2.cfi_type, issue_slots[1].brupdate.b2.cfi_type connect slots_1.io.brupdate.b2.taken, issue_slots[1].brupdate.b2.taken connect slots_1.io.brupdate.b2.mispredict, issue_slots[1].brupdate.b2.mispredict connect slots_1.io.brupdate.b2.uop.debug_tsrc, issue_slots[1].brupdate.b2.uop.debug_tsrc connect slots_1.io.brupdate.b2.uop.debug_fsrc, issue_slots[1].brupdate.b2.uop.debug_fsrc connect slots_1.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[1].brupdate.b2.uop.bp_xcpt_if connect slots_1.io.brupdate.b2.uop.bp_debug_if, issue_slots[1].brupdate.b2.uop.bp_debug_if connect slots_1.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[1].brupdate.b2.uop.xcpt_ma_if connect slots_1.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[1].brupdate.b2.uop.xcpt_ae_if connect slots_1.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[1].brupdate.b2.uop.xcpt_pf_if connect slots_1.io.brupdate.b2.uop.fp_typ, issue_slots[1].brupdate.b2.uop.fp_typ connect slots_1.io.brupdate.b2.uop.fp_rm, issue_slots[1].brupdate.b2.uop.fp_rm connect slots_1.io.brupdate.b2.uop.fp_val, issue_slots[1].brupdate.b2.uop.fp_val connect slots_1.io.brupdate.b2.uop.fcn_op, issue_slots[1].brupdate.b2.uop.fcn_op connect slots_1.io.brupdate.b2.uop.fcn_dw, issue_slots[1].brupdate.b2.uop.fcn_dw connect slots_1.io.brupdate.b2.uop.frs3_en, issue_slots[1].brupdate.b2.uop.frs3_en connect slots_1.io.brupdate.b2.uop.lrs2_rtype, issue_slots[1].brupdate.b2.uop.lrs2_rtype connect slots_1.io.brupdate.b2.uop.lrs1_rtype, issue_slots[1].brupdate.b2.uop.lrs1_rtype connect slots_1.io.brupdate.b2.uop.dst_rtype, issue_slots[1].brupdate.b2.uop.dst_rtype connect slots_1.io.brupdate.b2.uop.lrs3, issue_slots[1].brupdate.b2.uop.lrs3 connect slots_1.io.brupdate.b2.uop.lrs2, issue_slots[1].brupdate.b2.uop.lrs2 connect slots_1.io.brupdate.b2.uop.lrs1, issue_slots[1].brupdate.b2.uop.lrs1 connect slots_1.io.brupdate.b2.uop.ldst, issue_slots[1].brupdate.b2.uop.ldst connect slots_1.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[1].brupdate.b2.uop.ldst_is_rs1 connect slots_1.io.brupdate.b2.uop.csr_cmd, issue_slots[1].brupdate.b2.uop.csr_cmd connect slots_1.io.brupdate.b2.uop.flush_on_commit, issue_slots[1].brupdate.b2.uop.flush_on_commit connect slots_1.io.brupdate.b2.uop.is_unique, issue_slots[1].brupdate.b2.uop.is_unique connect slots_1.io.brupdate.b2.uop.uses_stq, issue_slots[1].brupdate.b2.uop.uses_stq connect slots_1.io.brupdate.b2.uop.uses_ldq, issue_slots[1].brupdate.b2.uop.uses_ldq connect slots_1.io.brupdate.b2.uop.mem_signed, issue_slots[1].brupdate.b2.uop.mem_signed connect slots_1.io.brupdate.b2.uop.mem_size, issue_slots[1].brupdate.b2.uop.mem_size connect slots_1.io.brupdate.b2.uop.mem_cmd, issue_slots[1].brupdate.b2.uop.mem_cmd connect slots_1.io.brupdate.b2.uop.exc_cause, issue_slots[1].brupdate.b2.uop.exc_cause connect slots_1.io.brupdate.b2.uop.exception, issue_slots[1].brupdate.b2.uop.exception connect slots_1.io.brupdate.b2.uop.stale_pdst, issue_slots[1].brupdate.b2.uop.stale_pdst connect slots_1.io.brupdate.b2.uop.ppred_busy, issue_slots[1].brupdate.b2.uop.ppred_busy connect slots_1.io.brupdate.b2.uop.prs3_busy, issue_slots[1].brupdate.b2.uop.prs3_busy connect slots_1.io.brupdate.b2.uop.prs2_busy, issue_slots[1].brupdate.b2.uop.prs2_busy connect slots_1.io.brupdate.b2.uop.prs1_busy, issue_slots[1].brupdate.b2.uop.prs1_busy connect slots_1.io.brupdate.b2.uop.ppred, issue_slots[1].brupdate.b2.uop.ppred connect slots_1.io.brupdate.b2.uop.prs3, issue_slots[1].brupdate.b2.uop.prs3 connect slots_1.io.brupdate.b2.uop.prs2, issue_slots[1].brupdate.b2.uop.prs2 connect slots_1.io.brupdate.b2.uop.prs1, issue_slots[1].brupdate.b2.uop.prs1 connect slots_1.io.brupdate.b2.uop.pdst, issue_slots[1].brupdate.b2.uop.pdst connect slots_1.io.brupdate.b2.uop.rxq_idx, issue_slots[1].brupdate.b2.uop.rxq_idx connect slots_1.io.brupdate.b2.uop.stq_idx, issue_slots[1].brupdate.b2.uop.stq_idx connect slots_1.io.brupdate.b2.uop.ldq_idx, issue_slots[1].brupdate.b2.uop.ldq_idx connect slots_1.io.brupdate.b2.uop.rob_idx, issue_slots[1].brupdate.b2.uop.rob_idx connect slots_1.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[1].brupdate.b2.uop.fp_ctrl.vec connect slots_1.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[1].brupdate.b2.uop.fp_ctrl.wflags connect slots_1.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[1].brupdate.b2.uop.fp_ctrl.sqrt connect slots_1.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[1].brupdate.b2.uop.fp_ctrl.div connect slots_1.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[1].brupdate.b2.uop.fp_ctrl.fma connect slots_1.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[1].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_1.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[1].brupdate.b2.uop.fp_ctrl.toint connect slots_1.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[1].brupdate.b2.uop.fp_ctrl.fromint connect slots_1.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_1.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_1.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[1].brupdate.b2.uop.fp_ctrl.swap23 connect slots_1.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[1].brupdate.b2.uop.fp_ctrl.swap12 connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren3 connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren2 connect slots_1.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[1].brupdate.b2.uop.fp_ctrl.ren1 connect slots_1.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[1].brupdate.b2.uop.fp_ctrl.wen connect slots_1.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[1].brupdate.b2.uop.fp_ctrl.ldst connect slots_1.io.brupdate.b2.uop.op2_sel, issue_slots[1].brupdate.b2.uop.op2_sel connect slots_1.io.brupdate.b2.uop.op1_sel, issue_slots[1].brupdate.b2.uop.op1_sel connect slots_1.io.brupdate.b2.uop.imm_packed, issue_slots[1].brupdate.b2.uop.imm_packed connect slots_1.io.brupdate.b2.uop.pimm, issue_slots[1].brupdate.b2.uop.pimm connect slots_1.io.brupdate.b2.uop.imm_sel, issue_slots[1].brupdate.b2.uop.imm_sel connect slots_1.io.brupdate.b2.uop.imm_rename, issue_slots[1].brupdate.b2.uop.imm_rename connect slots_1.io.brupdate.b2.uop.taken, issue_slots[1].brupdate.b2.uop.taken connect slots_1.io.brupdate.b2.uop.pc_lob, issue_slots[1].brupdate.b2.uop.pc_lob connect slots_1.io.brupdate.b2.uop.edge_inst, issue_slots[1].brupdate.b2.uop.edge_inst connect slots_1.io.brupdate.b2.uop.ftq_idx, issue_slots[1].brupdate.b2.uop.ftq_idx connect slots_1.io.brupdate.b2.uop.is_mov, issue_slots[1].brupdate.b2.uop.is_mov connect slots_1.io.brupdate.b2.uop.is_rocc, issue_slots[1].brupdate.b2.uop.is_rocc connect slots_1.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[1].brupdate.b2.uop.is_sys_pc2epc connect slots_1.io.brupdate.b2.uop.is_eret, issue_slots[1].brupdate.b2.uop.is_eret connect slots_1.io.brupdate.b2.uop.is_amo, issue_slots[1].brupdate.b2.uop.is_amo connect slots_1.io.brupdate.b2.uop.is_sfence, issue_slots[1].brupdate.b2.uop.is_sfence connect slots_1.io.brupdate.b2.uop.is_fencei, issue_slots[1].brupdate.b2.uop.is_fencei connect slots_1.io.brupdate.b2.uop.is_fence, issue_slots[1].brupdate.b2.uop.is_fence connect slots_1.io.brupdate.b2.uop.is_sfb, issue_slots[1].brupdate.b2.uop.is_sfb connect slots_1.io.brupdate.b2.uop.br_type, issue_slots[1].brupdate.b2.uop.br_type connect slots_1.io.brupdate.b2.uop.br_tag, issue_slots[1].brupdate.b2.uop.br_tag connect slots_1.io.brupdate.b2.uop.br_mask, issue_slots[1].brupdate.b2.uop.br_mask connect slots_1.io.brupdate.b2.uop.dis_col_sel, issue_slots[1].brupdate.b2.uop.dis_col_sel connect slots_1.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p3_bypass_hint connect slots_1.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p2_bypass_hint connect slots_1.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[1].brupdate.b2.uop.iw_p1_bypass_hint connect slots_1.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[1].brupdate.b2.uop.iw_p2_speculative_child connect slots_1.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[1].brupdate.b2.uop.iw_p1_speculative_child connect slots_1.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[1].brupdate.b2.uop.iw_issued_partial_dgen connect slots_1.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[1].brupdate.b2.uop.iw_issued_partial_agen connect slots_1.io.brupdate.b2.uop.iw_issued, issue_slots[1].brupdate.b2.uop.iw_issued connect slots_1.io.brupdate.b2.uop.fu_code[0], issue_slots[1].brupdate.b2.uop.fu_code[0] connect slots_1.io.brupdate.b2.uop.fu_code[1], issue_slots[1].brupdate.b2.uop.fu_code[1] connect slots_1.io.brupdate.b2.uop.fu_code[2], issue_slots[1].brupdate.b2.uop.fu_code[2] connect slots_1.io.brupdate.b2.uop.fu_code[3], issue_slots[1].brupdate.b2.uop.fu_code[3] connect slots_1.io.brupdate.b2.uop.fu_code[4], issue_slots[1].brupdate.b2.uop.fu_code[4] connect slots_1.io.brupdate.b2.uop.fu_code[5], issue_slots[1].brupdate.b2.uop.fu_code[5] connect slots_1.io.brupdate.b2.uop.fu_code[6], issue_slots[1].brupdate.b2.uop.fu_code[6] connect slots_1.io.brupdate.b2.uop.fu_code[7], issue_slots[1].brupdate.b2.uop.fu_code[7] connect slots_1.io.brupdate.b2.uop.fu_code[8], issue_slots[1].brupdate.b2.uop.fu_code[8] connect slots_1.io.brupdate.b2.uop.fu_code[9], issue_slots[1].brupdate.b2.uop.fu_code[9] connect slots_1.io.brupdate.b2.uop.iq_type[0], issue_slots[1].brupdate.b2.uop.iq_type[0] connect slots_1.io.brupdate.b2.uop.iq_type[1], issue_slots[1].brupdate.b2.uop.iq_type[1] connect slots_1.io.brupdate.b2.uop.iq_type[2], issue_slots[1].brupdate.b2.uop.iq_type[2] connect slots_1.io.brupdate.b2.uop.iq_type[3], issue_slots[1].brupdate.b2.uop.iq_type[3] connect slots_1.io.brupdate.b2.uop.debug_pc, issue_slots[1].brupdate.b2.uop.debug_pc connect slots_1.io.brupdate.b2.uop.is_rvc, issue_slots[1].brupdate.b2.uop.is_rvc connect slots_1.io.brupdate.b2.uop.debug_inst, issue_slots[1].brupdate.b2.uop.debug_inst connect slots_1.io.brupdate.b2.uop.inst, issue_slots[1].brupdate.b2.uop.inst connect slots_1.io.brupdate.b1.mispredict_mask, issue_slots[1].brupdate.b1.mispredict_mask connect slots_1.io.brupdate.b1.resolve_mask, issue_slots[1].brupdate.b1.resolve_mask connect issue_slots[1].out_uop.debug_tsrc, slots_1.io.out_uop.debug_tsrc connect issue_slots[1].out_uop.debug_fsrc, slots_1.io.out_uop.debug_fsrc connect issue_slots[1].out_uop.bp_xcpt_if, slots_1.io.out_uop.bp_xcpt_if connect issue_slots[1].out_uop.bp_debug_if, slots_1.io.out_uop.bp_debug_if connect issue_slots[1].out_uop.xcpt_ma_if, slots_1.io.out_uop.xcpt_ma_if connect issue_slots[1].out_uop.xcpt_ae_if, slots_1.io.out_uop.xcpt_ae_if connect issue_slots[1].out_uop.xcpt_pf_if, slots_1.io.out_uop.xcpt_pf_if connect issue_slots[1].out_uop.fp_typ, slots_1.io.out_uop.fp_typ connect issue_slots[1].out_uop.fp_rm, slots_1.io.out_uop.fp_rm connect issue_slots[1].out_uop.fp_val, slots_1.io.out_uop.fp_val connect issue_slots[1].out_uop.fcn_op, slots_1.io.out_uop.fcn_op connect issue_slots[1].out_uop.fcn_dw, slots_1.io.out_uop.fcn_dw connect issue_slots[1].out_uop.frs3_en, slots_1.io.out_uop.frs3_en connect issue_slots[1].out_uop.lrs2_rtype, slots_1.io.out_uop.lrs2_rtype connect issue_slots[1].out_uop.lrs1_rtype, slots_1.io.out_uop.lrs1_rtype connect issue_slots[1].out_uop.dst_rtype, slots_1.io.out_uop.dst_rtype connect issue_slots[1].out_uop.lrs3, slots_1.io.out_uop.lrs3 connect issue_slots[1].out_uop.lrs2, slots_1.io.out_uop.lrs2 connect issue_slots[1].out_uop.lrs1, slots_1.io.out_uop.lrs1 connect issue_slots[1].out_uop.ldst, slots_1.io.out_uop.ldst connect issue_slots[1].out_uop.ldst_is_rs1, slots_1.io.out_uop.ldst_is_rs1 connect issue_slots[1].out_uop.csr_cmd, slots_1.io.out_uop.csr_cmd connect issue_slots[1].out_uop.flush_on_commit, slots_1.io.out_uop.flush_on_commit connect issue_slots[1].out_uop.is_unique, slots_1.io.out_uop.is_unique connect issue_slots[1].out_uop.uses_stq, slots_1.io.out_uop.uses_stq connect issue_slots[1].out_uop.uses_ldq, slots_1.io.out_uop.uses_ldq connect issue_slots[1].out_uop.mem_signed, slots_1.io.out_uop.mem_signed connect issue_slots[1].out_uop.mem_size, slots_1.io.out_uop.mem_size connect issue_slots[1].out_uop.mem_cmd, slots_1.io.out_uop.mem_cmd connect issue_slots[1].out_uop.exc_cause, slots_1.io.out_uop.exc_cause connect issue_slots[1].out_uop.exception, slots_1.io.out_uop.exception connect issue_slots[1].out_uop.stale_pdst, slots_1.io.out_uop.stale_pdst connect issue_slots[1].out_uop.ppred_busy, slots_1.io.out_uop.ppred_busy connect issue_slots[1].out_uop.prs3_busy, slots_1.io.out_uop.prs3_busy connect issue_slots[1].out_uop.prs2_busy, slots_1.io.out_uop.prs2_busy connect issue_slots[1].out_uop.prs1_busy, slots_1.io.out_uop.prs1_busy connect issue_slots[1].out_uop.ppred, slots_1.io.out_uop.ppred connect issue_slots[1].out_uop.prs3, slots_1.io.out_uop.prs3 connect issue_slots[1].out_uop.prs2, slots_1.io.out_uop.prs2 connect issue_slots[1].out_uop.prs1, slots_1.io.out_uop.prs1 connect issue_slots[1].out_uop.pdst, slots_1.io.out_uop.pdst connect issue_slots[1].out_uop.rxq_idx, slots_1.io.out_uop.rxq_idx connect issue_slots[1].out_uop.stq_idx, slots_1.io.out_uop.stq_idx connect issue_slots[1].out_uop.ldq_idx, slots_1.io.out_uop.ldq_idx connect issue_slots[1].out_uop.rob_idx, slots_1.io.out_uop.rob_idx connect issue_slots[1].out_uop.fp_ctrl.vec, slots_1.io.out_uop.fp_ctrl.vec connect issue_slots[1].out_uop.fp_ctrl.wflags, slots_1.io.out_uop.fp_ctrl.wflags connect issue_slots[1].out_uop.fp_ctrl.sqrt, slots_1.io.out_uop.fp_ctrl.sqrt connect issue_slots[1].out_uop.fp_ctrl.div, slots_1.io.out_uop.fp_ctrl.div connect issue_slots[1].out_uop.fp_ctrl.fma, slots_1.io.out_uop.fp_ctrl.fma connect issue_slots[1].out_uop.fp_ctrl.fastpipe, slots_1.io.out_uop.fp_ctrl.fastpipe connect issue_slots[1].out_uop.fp_ctrl.toint, slots_1.io.out_uop.fp_ctrl.toint connect issue_slots[1].out_uop.fp_ctrl.fromint, slots_1.io.out_uop.fp_ctrl.fromint connect issue_slots[1].out_uop.fp_ctrl.typeTagOut, slots_1.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[1].out_uop.fp_ctrl.typeTagIn, slots_1.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[1].out_uop.fp_ctrl.swap23, slots_1.io.out_uop.fp_ctrl.swap23 connect issue_slots[1].out_uop.fp_ctrl.swap12, slots_1.io.out_uop.fp_ctrl.swap12 connect issue_slots[1].out_uop.fp_ctrl.ren3, slots_1.io.out_uop.fp_ctrl.ren3 connect issue_slots[1].out_uop.fp_ctrl.ren2, slots_1.io.out_uop.fp_ctrl.ren2 connect issue_slots[1].out_uop.fp_ctrl.ren1, slots_1.io.out_uop.fp_ctrl.ren1 connect issue_slots[1].out_uop.fp_ctrl.wen, slots_1.io.out_uop.fp_ctrl.wen connect issue_slots[1].out_uop.fp_ctrl.ldst, slots_1.io.out_uop.fp_ctrl.ldst connect issue_slots[1].out_uop.op2_sel, slots_1.io.out_uop.op2_sel connect issue_slots[1].out_uop.op1_sel, slots_1.io.out_uop.op1_sel connect issue_slots[1].out_uop.imm_packed, slots_1.io.out_uop.imm_packed connect issue_slots[1].out_uop.pimm, slots_1.io.out_uop.pimm connect issue_slots[1].out_uop.imm_sel, slots_1.io.out_uop.imm_sel connect issue_slots[1].out_uop.imm_rename, slots_1.io.out_uop.imm_rename connect issue_slots[1].out_uop.taken, slots_1.io.out_uop.taken connect issue_slots[1].out_uop.pc_lob, slots_1.io.out_uop.pc_lob connect issue_slots[1].out_uop.edge_inst, slots_1.io.out_uop.edge_inst connect issue_slots[1].out_uop.ftq_idx, slots_1.io.out_uop.ftq_idx connect issue_slots[1].out_uop.is_mov, slots_1.io.out_uop.is_mov connect issue_slots[1].out_uop.is_rocc, slots_1.io.out_uop.is_rocc connect issue_slots[1].out_uop.is_sys_pc2epc, slots_1.io.out_uop.is_sys_pc2epc connect issue_slots[1].out_uop.is_eret, slots_1.io.out_uop.is_eret connect issue_slots[1].out_uop.is_amo, slots_1.io.out_uop.is_amo connect issue_slots[1].out_uop.is_sfence, slots_1.io.out_uop.is_sfence connect issue_slots[1].out_uop.is_fencei, slots_1.io.out_uop.is_fencei connect issue_slots[1].out_uop.is_fence, slots_1.io.out_uop.is_fence connect issue_slots[1].out_uop.is_sfb, slots_1.io.out_uop.is_sfb connect issue_slots[1].out_uop.br_type, slots_1.io.out_uop.br_type connect issue_slots[1].out_uop.br_tag, slots_1.io.out_uop.br_tag connect issue_slots[1].out_uop.br_mask, slots_1.io.out_uop.br_mask connect issue_slots[1].out_uop.dis_col_sel, slots_1.io.out_uop.dis_col_sel connect issue_slots[1].out_uop.iw_p3_bypass_hint, slots_1.io.out_uop.iw_p3_bypass_hint connect issue_slots[1].out_uop.iw_p2_bypass_hint, slots_1.io.out_uop.iw_p2_bypass_hint connect issue_slots[1].out_uop.iw_p1_bypass_hint, slots_1.io.out_uop.iw_p1_bypass_hint connect issue_slots[1].out_uop.iw_p2_speculative_child, slots_1.io.out_uop.iw_p2_speculative_child connect issue_slots[1].out_uop.iw_p1_speculative_child, slots_1.io.out_uop.iw_p1_speculative_child connect issue_slots[1].out_uop.iw_issued_partial_dgen, slots_1.io.out_uop.iw_issued_partial_dgen connect issue_slots[1].out_uop.iw_issued_partial_agen, slots_1.io.out_uop.iw_issued_partial_agen connect issue_slots[1].out_uop.iw_issued, slots_1.io.out_uop.iw_issued connect issue_slots[1].out_uop.fu_code[0], slots_1.io.out_uop.fu_code[0] connect issue_slots[1].out_uop.fu_code[1], slots_1.io.out_uop.fu_code[1] connect issue_slots[1].out_uop.fu_code[2], slots_1.io.out_uop.fu_code[2] connect issue_slots[1].out_uop.fu_code[3], slots_1.io.out_uop.fu_code[3] connect issue_slots[1].out_uop.fu_code[4], slots_1.io.out_uop.fu_code[4] connect issue_slots[1].out_uop.fu_code[5], slots_1.io.out_uop.fu_code[5] connect issue_slots[1].out_uop.fu_code[6], slots_1.io.out_uop.fu_code[6] connect issue_slots[1].out_uop.fu_code[7], slots_1.io.out_uop.fu_code[7] connect issue_slots[1].out_uop.fu_code[8], slots_1.io.out_uop.fu_code[8] connect issue_slots[1].out_uop.fu_code[9], slots_1.io.out_uop.fu_code[9] connect issue_slots[1].out_uop.iq_type[0], slots_1.io.out_uop.iq_type[0] connect issue_slots[1].out_uop.iq_type[1], slots_1.io.out_uop.iq_type[1] connect issue_slots[1].out_uop.iq_type[2], slots_1.io.out_uop.iq_type[2] connect issue_slots[1].out_uop.iq_type[3], slots_1.io.out_uop.iq_type[3] connect issue_slots[1].out_uop.debug_pc, slots_1.io.out_uop.debug_pc connect issue_slots[1].out_uop.is_rvc, slots_1.io.out_uop.is_rvc connect issue_slots[1].out_uop.debug_inst, slots_1.io.out_uop.debug_inst connect issue_slots[1].out_uop.inst, slots_1.io.out_uop.inst connect slots_1.io.in_uop.bits.debug_tsrc, issue_slots[1].in_uop.bits.debug_tsrc connect slots_1.io.in_uop.bits.debug_fsrc, issue_slots[1].in_uop.bits.debug_fsrc connect slots_1.io.in_uop.bits.bp_xcpt_if, issue_slots[1].in_uop.bits.bp_xcpt_if connect slots_1.io.in_uop.bits.bp_debug_if, issue_slots[1].in_uop.bits.bp_debug_if connect slots_1.io.in_uop.bits.xcpt_ma_if, issue_slots[1].in_uop.bits.xcpt_ma_if connect slots_1.io.in_uop.bits.xcpt_ae_if, issue_slots[1].in_uop.bits.xcpt_ae_if connect slots_1.io.in_uop.bits.xcpt_pf_if, issue_slots[1].in_uop.bits.xcpt_pf_if connect slots_1.io.in_uop.bits.fp_typ, issue_slots[1].in_uop.bits.fp_typ connect slots_1.io.in_uop.bits.fp_rm, issue_slots[1].in_uop.bits.fp_rm connect slots_1.io.in_uop.bits.fp_val, issue_slots[1].in_uop.bits.fp_val connect slots_1.io.in_uop.bits.fcn_op, issue_slots[1].in_uop.bits.fcn_op connect slots_1.io.in_uop.bits.fcn_dw, issue_slots[1].in_uop.bits.fcn_dw connect slots_1.io.in_uop.bits.frs3_en, issue_slots[1].in_uop.bits.frs3_en connect slots_1.io.in_uop.bits.lrs2_rtype, issue_slots[1].in_uop.bits.lrs2_rtype connect slots_1.io.in_uop.bits.lrs1_rtype, issue_slots[1].in_uop.bits.lrs1_rtype connect slots_1.io.in_uop.bits.dst_rtype, issue_slots[1].in_uop.bits.dst_rtype connect slots_1.io.in_uop.bits.lrs3, issue_slots[1].in_uop.bits.lrs3 connect slots_1.io.in_uop.bits.lrs2, issue_slots[1].in_uop.bits.lrs2 connect slots_1.io.in_uop.bits.lrs1, issue_slots[1].in_uop.bits.lrs1 connect slots_1.io.in_uop.bits.ldst, issue_slots[1].in_uop.bits.ldst connect slots_1.io.in_uop.bits.ldst_is_rs1, issue_slots[1].in_uop.bits.ldst_is_rs1 connect slots_1.io.in_uop.bits.csr_cmd, issue_slots[1].in_uop.bits.csr_cmd connect slots_1.io.in_uop.bits.flush_on_commit, issue_slots[1].in_uop.bits.flush_on_commit connect slots_1.io.in_uop.bits.is_unique, issue_slots[1].in_uop.bits.is_unique connect slots_1.io.in_uop.bits.uses_stq, issue_slots[1].in_uop.bits.uses_stq connect slots_1.io.in_uop.bits.uses_ldq, issue_slots[1].in_uop.bits.uses_ldq connect slots_1.io.in_uop.bits.mem_signed, issue_slots[1].in_uop.bits.mem_signed connect slots_1.io.in_uop.bits.mem_size, issue_slots[1].in_uop.bits.mem_size connect slots_1.io.in_uop.bits.mem_cmd, issue_slots[1].in_uop.bits.mem_cmd connect slots_1.io.in_uop.bits.exc_cause, issue_slots[1].in_uop.bits.exc_cause connect slots_1.io.in_uop.bits.exception, issue_slots[1].in_uop.bits.exception connect slots_1.io.in_uop.bits.stale_pdst, issue_slots[1].in_uop.bits.stale_pdst connect slots_1.io.in_uop.bits.ppred_busy, issue_slots[1].in_uop.bits.ppred_busy connect slots_1.io.in_uop.bits.prs3_busy, issue_slots[1].in_uop.bits.prs3_busy connect slots_1.io.in_uop.bits.prs2_busy, issue_slots[1].in_uop.bits.prs2_busy connect slots_1.io.in_uop.bits.prs1_busy, issue_slots[1].in_uop.bits.prs1_busy connect slots_1.io.in_uop.bits.ppred, issue_slots[1].in_uop.bits.ppred connect slots_1.io.in_uop.bits.prs3, issue_slots[1].in_uop.bits.prs3 connect slots_1.io.in_uop.bits.prs2, issue_slots[1].in_uop.bits.prs2 connect slots_1.io.in_uop.bits.prs1, issue_slots[1].in_uop.bits.prs1 connect slots_1.io.in_uop.bits.pdst, issue_slots[1].in_uop.bits.pdst connect slots_1.io.in_uop.bits.rxq_idx, issue_slots[1].in_uop.bits.rxq_idx connect slots_1.io.in_uop.bits.stq_idx, issue_slots[1].in_uop.bits.stq_idx connect slots_1.io.in_uop.bits.ldq_idx, issue_slots[1].in_uop.bits.ldq_idx connect slots_1.io.in_uop.bits.rob_idx, issue_slots[1].in_uop.bits.rob_idx connect slots_1.io.in_uop.bits.fp_ctrl.vec, issue_slots[1].in_uop.bits.fp_ctrl.vec connect slots_1.io.in_uop.bits.fp_ctrl.wflags, issue_slots[1].in_uop.bits.fp_ctrl.wflags connect slots_1.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[1].in_uop.bits.fp_ctrl.sqrt connect slots_1.io.in_uop.bits.fp_ctrl.div, issue_slots[1].in_uop.bits.fp_ctrl.div connect slots_1.io.in_uop.bits.fp_ctrl.fma, issue_slots[1].in_uop.bits.fp_ctrl.fma connect slots_1.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].in_uop.bits.fp_ctrl.fastpipe connect slots_1.io.in_uop.bits.fp_ctrl.toint, issue_slots[1].in_uop.bits.fp_ctrl.toint connect slots_1.io.in_uop.bits.fp_ctrl.fromint, issue_slots[1].in_uop.bits.fp_ctrl.fromint connect slots_1.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut connect slots_1.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn connect slots_1.io.in_uop.bits.fp_ctrl.swap23, issue_slots[1].in_uop.bits.fp_ctrl.swap23 connect slots_1.io.in_uop.bits.fp_ctrl.swap12, issue_slots[1].in_uop.bits.fp_ctrl.swap12 connect slots_1.io.in_uop.bits.fp_ctrl.ren3, issue_slots[1].in_uop.bits.fp_ctrl.ren3 connect slots_1.io.in_uop.bits.fp_ctrl.ren2, issue_slots[1].in_uop.bits.fp_ctrl.ren2 connect slots_1.io.in_uop.bits.fp_ctrl.ren1, issue_slots[1].in_uop.bits.fp_ctrl.ren1 connect slots_1.io.in_uop.bits.fp_ctrl.wen, issue_slots[1].in_uop.bits.fp_ctrl.wen connect slots_1.io.in_uop.bits.fp_ctrl.ldst, issue_slots[1].in_uop.bits.fp_ctrl.ldst connect slots_1.io.in_uop.bits.op2_sel, issue_slots[1].in_uop.bits.op2_sel connect slots_1.io.in_uop.bits.op1_sel, issue_slots[1].in_uop.bits.op1_sel connect slots_1.io.in_uop.bits.imm_packed, issue_slots[1].in_uop.bits.imm_packed connect slots_1.io.in_uop.bits.pimm, issue_slots[1].in_uop.bits.pimm connect slots_1.io.in_uop.bits.imm_sel, issue_slots[1].in_uop.bits.imm_sel connect slots_1.io.in_uop.bits.imm_rename, issue_slots[1].in_uop.bits.imm_rename connect slots_1.io.in_uop.bits.taken, issue_slots[1].in_uop.bits.taken connect slots_1.io.in_uop.bits.pc_lob, issue_slots[1].in_uop.bits.pc_lob connect slots_1.io.in_uop.bits.edge_inst, issue_slots[1].in_uop.bits.edge_inst connect slots_1.io.in_uop.bits.ftq_idx, issue_slots[1].in_uop.bits.ftq_idx connect slots_1.io.in_uop.bits.is_mov, issue_slots[1].in_uop.bits.is_mov connect slots_1.io.in_uop.bits.is_rocc, issue_slots[1].in_uop.bits.is_rocc connect slots_1.io.in_uop.bits.is_sys_pc2epc, issue_slots[1].in_uop.bits.is_sys_pc2epc connect slots_1.io.in_uop.bits.is_eret, issue_slots[1].in_uop.bits.is_eret connect slots_1.io.in_uop.bits.is_amo, issue_slots[1].in_uop.bits.is_amo connect slots_1.io.in_uop.bits.is_sfence, issue_slots[1].in_uop.bits.is_sfence connect slots_1.io.in_uop.bits.is_fencei, issue_slots[1].in_uop.bits.is_fencei connect slots_1.io.in_uop.bits.is_fence, issue_slots[1].in_uop.bits.is_fence connect slots_1.io.in_uop.bits.is_sfb, issue_slots[1].in_uop.bits.is_sfb connect slots_1.io.in_uop.bits.br_type, issue_slots[1].in_uop.bits.br_type connect slots_1.io.in_uop.bits.br_tag, issue_slots[1].in_uop.bits.br_tag connect slots_1.io.in_uop.bits.br_mask, issue_slots[1].in_uop.bits.br_mask connect slots_1.io.in_uop.bits.dis_col_sel, issue_slots[1].in_uop.bits.dis_col_sel connect slots_1.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[1].in_uop.bits.iw_p3_bypass_hint connect slots_1.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[1].in_uop.bits.iw_p2_bypass_hint connect slots_1.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[1].in_uop.bits.iw_p1_bypass_hint connect slots_1.io.in_uop.bits.iw_p2_speculative_child, issue_slots[1].in_uop.bits.iw_p2_speculative_child connect slots_1.io.in_uop.bits.iw_p1_speculative_child, issue_slots[1].in_uop.bits.iw_p1_speculative_child connect slots_1.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[1].in_uop.bits.iw_issued_partial_dgen connect slots_1.io.in_uop.bits.iw_issued_partial_agen, issue_slots[1].in_uop.bits.iw_issued_partial_agen connect slots_1.io.in_uop.bits.iw_issued, issue_slots[1].in_uop.bits.iw_issued connect slots_1.io.in_uop.bits.fu_code[0], issue_slots[1].in_uop.bits.fu_code[0] connect slots_1.io.in_uop.bits.fu_code[1], issue_slots[1].in_uop.bits.fu_code[1] connect slots_1.io.in_uop.bits.fu_code[2], issue_slots[1].in_uop.bits.fu_code[2] connect slots_1.io.in_uop.bits.fu_code[3], issue_slots[1].in_uop.bits.fu_code[3] connect slots_1.io.in_uop.bits.fu_code[4], issue_slots[1].in_uop.bits.fu_code[4] connect slots_1.io.in_uop.bits.fu_code[5], issue_slots[1].in_uop.bits.fu_code[5] connect slots_1.io.in_uop.bits.fu_code[6], issue_slots[1].in_uop.bits.fu_code[6] connect slots_1.io.in_uop.bits.fu_code[7], issue_slots[1].in_uop.bits.fu_code[7] connect slots_1.io.in_uop.bits.fu_code[8], issue_slots[1].in_uop.bits.fu_code[8] connect slots_1.io.in_uop.bits.fu_code[9], issue_slots[1].in_uop.bits.fu_code[9] connect slots_1.io.in_uop.bits.iq_type[0], issue_slots[1].in_uop.bits.iq_type[0] connect slots_1.io.in_uop.bits.iq_type[1], issue_slots[1].in_uop.bits.iq_type[1] connect slots_1.io.in_uop.bits.iq_type[2], issue_slots[1].in_uop.bits.iq_type[2] connect slots_1.io.in_uop.bits.iq_type[3], issue_slots[1].in_uop.bits.iq_type[3] connect slots_1.io.in_uop.bits.debug_pc, issue_slots[1].in_uop.bits.debug_pc connect slots_1.io.in_uop.bits.is_rvc, issue_slots[1].in_uop.bits.is_rvc connect slots_1.io.in_uop.bits.debug_inst, issue_slots[1].in_uop.bits.debug_inst connect slots_1.io.in_uop.bits.inst, issue_slots[1].in_uop.bits.inst connect slots_1.io.in_uop.valid, issue_slots[1].in_uop.valid connect issue_slots[1].iss_uop.debug_tsrc, slots_1.io.iss_uop.debug_tsrc connect issue_slots[1].iss_uop.debug_fsrc, slots_1.io.iss_uop.debug_fsrc connect issue_slots[1].iss_uop.bp_xcpt_if, slots_1.io.iss_uop.bp_xcpt_if connect issue_slots[1].iss_uop.bp_debug_if, slots_1.io.iss_uop.bp_debug_if connect issue_slots[1].iss_uop.xcpt_ma_if, slots_1.io.iss_uop.xcpt_ma_if connect issue_slots[1].iss_uop.xcpt_ae_if, slots_1.io.iss_uop.xcpt_ae_if connect issue_slots[1].iss_uop.xcpt_pf_if, slots_1.io.iss_uop.xcpt_pf_if connect issue_slots[1].iss_uop.fp_typ, slots_1.io.iss_uop.fp_typ connect issue_slots[1].iss_uop.fp_rm, slots_1.io.iss_uop.fp_rm connect issue_slots[1].iss_uop.fp_val, slots_1.io.iss_uop.fp_val connect issue_slots[1].iss_uop.fcn_op, slots_1.io.iss_uop.fcn_op connect issue_slots[1].iss_uop.fcn_dw, slots_1.io.iss_uop.fcn_dw connect issue_slots[1].iss_uop.frs3_en, slots_1.io.iss_uop.frs3_en connect issue_slots[1].iss_uop.lrs2_rtype, slots_1.io.iss_uop.lrs2_rtype connect issue_slots[1].iss_uop.lrs1_rtype, slots_1.io.iss_uop.lrs1_rtype connect issue_slots[1].iss_uop.dst_rtype, slots_1.io.iss_uop.dst_rtype connect issue_slots[1].iss_uop.lrs3, slots_1.io.iss_uop.lrs3 connect issue_slots[1].iss_uop.lrs2, slots_1.io.iss_uop.lrs2 connect issue_slots[1].iss_uop.lrs1, slots_1.io.iss_uop.lrs1 connect issue_slots[1].iss_uop.ldst, slots_1.io.iss_uop.ldst connect issue_slots[1].iss_uop.ldst_is_rs1, slots_1.io.iss_uop.ldst_is_rs1 connect issue_slots[1].iss_uop.csr_cmd, slots_1.io.iss_uop.csr_cmd connect issue_slots[1].iss_uop.flush_on_commit, slots_1.io.iss_uop.flush_on_commit connect issue_slots[1].iss_uop.is_unique, slots_1.io.iss_uop.is_unique connect issue_slots[1].iss_uop.uses_stq, slots_1.io.iss_uop.uses_stq connect issue_slots[1].iss_uop.uses_ldq, slots_1.io.iss_uop.uses_ldq connect issue_slots[1].iss_uop.mem_signed, slots_1.io.iss_uop.mem_signed connect issue_slots[1].iss_uop.mem_size, slots_1.io.iss_uop.mem_size connect issue_slots[1].iss_uop.mem_cmd, slots_1.io.iss_uop.mem_cmd connect issue_slots[1].iss_uop.exc_cause, slots_1.io.iss_uop.exc_cause connect issue_slots[1].iss_uop.exception, slots_1.io.iss_uop.exception connect issue_slots[1].iss_uop.stale_pdst, slots_1.io.iss_uop.stale_pdst connect issue_slots[1].iss_uop.ppred_busy, slots_1.io.iss_uop.ppred_busy connect issue_slots[1].iss_uop.prs3_busy, slots_1.io.iss_uop.prs3_busy connect issue_slots[1].iss_uop.prs2_busy, slots_1.io.iss_uop.prs2_busy connect issue_slots[1].iss_uop.prs1_busy, slots_1.io.iss_uop.prs1_busy connect issue_slots[1].iss_uop.ppred, slots_1.io.iss_uop.ppred connect issue_slots[1].iss_uop.prs3, slots_1.io.iss_uop.prs3 connect issue_slots[1].iss_uop.prs2, slots_1.io.iss_uop.prs2 connect issue_slots[1].iss_uop.prs1, slots_1.io.iss_uop.prs1 connect issue_slots[1].iss_uop.pdst, slots_1.io.iss_uop.pdst connect issue_slots[1].iss_uop.rxq_idx, slots_1.io.iss_uop.rxq_idx connect issue_slots[1].iss_uop.stq_idx, slots_1.io.iss_uop.stq_idx connect issue_slots[1].iss_uop.ldq_idx, slots_1.io.iss_uop.ldq_idx connect issue_slots[1].iss_uop.rob_idx, slots_1.io.iss_uop.rob_idx connect issue_slots[1].iss_uop.fp_ctrl.vec, slots_1.io.iss_uop.fp_ctrl.vec connect issue_slots[1].iss_uop.fp_ctrl.wflags, slots_1.io.iss_uop.fp_ctrl.wflags connect issue_slots[1].iss_uop.fp_ctrl.sqrt, slots_1.io.iss_uop.fp_ctrl.sqrt connect issue_slots[1].iss_uop.fp_ctrl.div, slots_1.io.iss_uop.fp_ctrl.div connect issue_slots[1].iss_uop.fp_ctrl.fma, slots_1.io.iss_uop.fp_ctrl.fma connect issue_slots[1].iss_uop.fp_ctrl.fastpipe, slots_1.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[1].iss_uop.fp_ctrl.toint, slots_1.io.iss_uop.fp_ctrl.toint connect issue_slots[1].iss_uop.fp_ctrl.fromint, slots_1.io.iss_uop.fp_ctrl.fromint connect issue_slots[1].iss_uop.fp_ctrl.typeTagOut, slots_1.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[1].iss_uop.fp_ctrl.typeTagIn, slots_1.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[1].iss_uop.fp_ctrl.swap23, slots_1.io.iss_uop.fp_ctrl.swap23 connect issue_slots[1].iss_uop.fp_ctrl.swap12, slots_1.io.iss_uop.fp_ctrl.swap12 connect issue_slots[1].iss_uop.fp_ctrl.ren3, slots_1.io.iss_uop.fp_ctrl.ren3 connect issue_slots[1].iss_uop.fp_ctrl.ren2, slots_1.io.iss_uop.fp_ctrl.ren2 connect issue_slots[1].iss_uop.fp_ctrl.ren1, slots_1.io.iss_uop.fp_ctrl.ren1 connect issue_slots[1].iss_uop.fp_ctrl.wen, slots_1.io.iss_uop.fp_ctrl.wen connect issue_slots[1].iss_uop.fp_ctrl.ldst, slots_1.io.iss_uop.fp_ctrl.ldst connect issue_slots[1].iss_uop.op2_sel, slots_1.io.iss_uop.op2_sel connect issue_slots[1].iss_uop.op1_sel, slots_1.io.iss_uop.op1_sel connect issue_slots[1].iss_uop.imm_packed, slots_1.io.iss_uop.imm_packed connect issue_slots[1].iss_uop.pimm, slots_1.io.iss_uop.pimm connect issue_slots[1].iss_uop.imm_sel, slots_1.io.iss_uop.imm_sel connect issue_slots[1].iss_uop.imm_rename, slots_1.io.iss_uop.imm_rename connect issue_slots[1].iss_uop.taken, slots_1.io.iss_uop.taken connect issue_slots[1].iss_uop.pc_lob, slots_1.io.iss_uop.pc_lob connect issue_slots[1].iss_uop.edge_inst, slots_1.io.iss_uop.edge_inst connect issue_slots[1].iss_uop.ftq_idx, slots_1.io.iss_uop.ftq_idx connect issue_slots[1].iss_uop.is_mov, slots_1.io.iss_uop.is_mov connect issue_slots[1].iss_uop.is_rocc, slots_1.io.iss_uop.is_rocc connect issue_slots[1].iss_uop.is_sys_pc2epc, slots_1.io.iss_uop.is_sys_pc2epc connect issue_slots[1].iss_uop.is_eret, slots_1.io.iss_uop.is_eret connect issue_slots[1].iss_uop.is_amo, slots_1.io.iss_uop.is_amo connect issue_slots[1].iss_uop.is_sfence, slots_1.io.iss_uop.is_sfence connect issue_slots[1].iss_uop.is_fencei, slots_1.io.iss_uop.is_fencei connect issue_slots[1].iss_uop.is_fence, slots_1.io.iss_uop.is_fence connect issue_slots[1].iss_uop.is_sfb, slots_1.io.iss_uop.is_sfb connect issue_slots[1].iss_uop.br_type, slots_1.io.iss_uop.br_type connect issue_slots[1].iss_uop.br_tag, slots_1.io.iss_uop.br_tag connect issue_slots[1].iss_uop.br_mask, slots_1.io.iss_uop.br_mask connect issue_slots[1].iss_uop.dis_col_sel, slots_1.io.iss_uop.dis_col_sel connect issue_slots[1].iss_uop.iw_p3_bypass_hint, slots_1.io.iss_uop.iw_p3_bypass_hint connect issue_slots[1].iss_uop.iw_p2_bypass_hint, slots_1.io.iss_uop.iw_p2_bypass_hint connect issue_slots[1].iss_uop.iw_p1_bypass_hint, slots_1.io.iss_uop.iw_p1_bypass_hint connect issue_slots[1].iss_uop.iw_p2_speculative_child, slots_1.io.iss_uop.iw_p2_speculative_child connect issue_slots[1].iss_uop.iw_p1_speculative_child, slots_1.io.iss_uop.iw_p1_speculative_child connect issue_slots[1].iss_uop.iw_issued_partial_dgen, slots_1.io.iss_uop.iw_issued_partial_dgen connect issue_slots[1].iss_uop.iw_issued_partial_agen, slots_1.io.iss_uop.iw_issued_partial_agen connect issue_slots[1].iss_uop.iw_issued, slots_1.io.iss_uop.iw_issued connect issue_slots[1].iss_uop.fu_code[0], slots_1.io.iss_uop.fu_code[0] connect issue_slots[1].iss_uop.fu_code[1], slots_1.io.iss_uop.fu_code[1] connect issue_slots[1].iss_uop.fu_code[2], slots_1.io.iss_uop.fu_code[2] connect issue_slots[1].iss_uop.fu_code[3], slots_1.io.iss_uop.fu_code[3] connect issue_slots[1].iss_uop.fu_code[4], slots_1.io.iss_uop.fu_code[4] connect issue_slots[1].iss_uop.fu_code[5], slots_1.io.iss_uop.fu_code[5] connect issue_slots[1].iss_uop.fu_code[6], slots_1.io.iss_uop.fu_code[6] connect issue_slots[1].iss_uop.fu_code[7], slots_1.io.iss_uop.fu_code[7] connect issue_slots[1].iss_uop.fu_code[8], slots_1.io.iss_uop.fu_code[8] connect issue_slots[1].iss_uop.fu_code[9], slots_1.io.iss_uop.fu_code[9] connect issue_slots[1].iss_uop.iq_type[0], slots_1.io.iss_uop.iq_type[0] connect issue_slots[1].iss_uop.iq_type[1], slots_1.io.iss_uop.iq_type[1] connect issue_slots[1].iss_uop.iq_type[2], slots_1.io.iss_uop.iq_type[2] connect issue_slots[1].iss_uop.iq_type[3], slots_1.io.iss_uop.iq_type[3] connect issue_slots[1].iss_uop.debug_pc, slots_1.io.iss_uop.debug_pc connect issue_slots[1].iss_uop.is_rvc, slots_1.io.iss_uop.is_rvc connect issue_slots[1].iss_uop.debug_inst, slots_1.io.iss_uop.debug_inst connect issue_slots[1].iss_uop.inst, slots_1.io.iss_uop.inst connect slots_1.io.grant, issue_slots[1].grant connect issue_slots[1].request, slots_1.io.request connect issue_slots[1].will_be_valid, slots_1.io.will_be_valid connect issue_slots[1].valid, slots_1.io.valid connect slots_2.io.child_rebusys, issue_slots[2].child_rebusys connect slots_2.io.pred_wakeup_port.bits, issue_slots[2].pred_wakeup_port.bits connect slots_2.io.pred_wakeup_port.valid, issue_slots[2].pred_wakeup_port.valid connect slots_2.io.wakeup_ports[0].bits.rebusy, issue_slots[2].wakeup_ports[0].bits.rebusy connect slots_2.io.wakeup_ports[0].bits.speculative_mask, issue_slots[2].wakeup_ports[0].bits.speculative_mask connect slots_2.io.wakeup_ports[0].bits.bypassable, issue_slots[2].wakeup_ports[0].bits.bypassable connect slots_2.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[0].bits.uop.debug_tsrc connect slots_2.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[0].bits.uop.debug_fsrc connect slots_2.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_2.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[0].bits.uop.bp_debug_if connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_2.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_2.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[2].wakeup_ports[0].bits.uop.fp_typ connect slots_2.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[2].wakeup_ports[0].bits.uop.fp_rm connect slots_2.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[2].wakeup_ports[0].bits.uop.fp_val connect slots_2.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[2].wakeup_ports[0].bits.uop.fcn_op connect slots_2.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[0].bits.uop.fcn_dw connect slots_2.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[2].wakeup_ports[0].bits.uop.frs3_en connect slots_2.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_2.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_2.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[0].bits.uop.dst_rtype connect slots_2.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[2].wakeup_ports[0].bits.uop.lrs3 connect slots_2.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[2].wakeup_ports[0].bits.uop.lrs2 connect slots_2.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[2].wakeup_ports[0].bits.uop.lrs1 connect slots_2.io.wakeup_ports[0].bits.uop.ldst, issue_slots[2].wakeup_ports[0].bits.uop.ldst connect slots_2.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_2.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[0].bits.uop.csr_cmd connect slots_2.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[0].bits.uop.flush_on_commit connect slots_2.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[2].wakeup_ports[0].bits.uop.is_unique connect slots_2.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[2].wakeup_ports[0].bits.uop.uses_stq connect slots_2.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[0].bits.uop.uses_ldq connect slots_2.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[2].wakeup_ports[0].bits.uop.mem_signed connect slots_2.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[2].wakeup_ports[0].bits.uop.mem_size connect slots_2.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[0].bits.uop.mem_cmd connect slots_2.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[2].wakeup_ports[0].bits.uop.exc_cause connect slots_2.io.wakeup_ports[0].bits.uop.exception, issue_slots[2].wakeup_ports[0].bits.uop.exception connect slots_2.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[0].bits.uop.stale_pdst connect slots_2.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[0].bits.uop.ppred_busy connect slots_2.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs3_busy connect slots_2.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs2_busy connect slots_2.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[0].bits.uop.prs1_busy connect slots_2.io.wakeup_ports[0].bits.uop.ppred, issue_slots[2].wakeup_ports[0].bits.uop.ppred connect slots_2.io.wakeup_ports[0].bits.uop.prs3, issue_slots[2].wakeup_ports[0].bits.uop.prs3 connect slots_2.io.wakeup_ports[0].bits.uop.prs2, issue_slots[2].wakeup_ports[0].bits.uop.prs2 connect slots_2.io.wakeup_ports[0].bits.uop.prs1, issue_slots[2].wakeup_ports[0].bits.uop.prs1 connect slots_2.io.wakeup_ports[0].bits.uop.pdst, issue_slots[2].wakeup_ports[0].bits.uop.pdst connect slots_2.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[0].bits.uop.rxq_idx connect slots_2.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[2].wakeup_ports[0].bits.uop.stq_idx connect slots_2.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[0].bits.uop.ldq_idx connect slots_2.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[2].wakeup_ports[0].bits.uop.rob_idx connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_2.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_2.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[2].wakeup_ports[0].bits.uop.op2_sel connect slots_2.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[2].wakeup_ports[0].bits.uop.op1_sel connect slots_2.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[2].wakeup_ports[0].bits.uop.imm_packed connect slots_2.io.wakeup_ports[0].bits.uop.pimm, issue_slots[2].wakeup_ports[0].bits.uop.pimm connect slots_2.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[2].wakeup_ports[0].bits.uop.imm_sel connect slots_2.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[2].wakeup_ports[0].bits.uop.imm_rename connect slots_2.io.wakeup_ports[0].bits.uop.taken, issue_slots[2].wakeup_ports[0].bits.uop.taken connect slots_2.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[2].wakeup_ports[0].bits.uop.pc_lob connect slots_2.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[2].wakeup_ports[0].bits.uop.edge_inst connect slots_2.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[0].bits.uop.ftq_idx connect slots_2.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[2].wakeup_ports[0].bits.uop.is_mov connect slots_2.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[2].wakeup_ports[0].bits.uop.is_rocc connect slots_2.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_2.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[2].wakeup_ports[0].bits.uop.is_eret connect slots_2.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[2].wakeup_ports[0].bits.uop.is_amo connect slots_2.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[2].wakeup_ports[0].bits.uop.is_sfence connect slots_2.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[2].wakeup_ports[0].bits.uop.is_fencei connect slots_2.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[2].wakeup_ports[0].bits.uop.is_fence connect slots_2.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[2].wakeup_ports[0].bits.uop.is_sfb connect slots_2.io.wakeup_ports[0].bits.uop.br_type, issue_slots[2].wakeup_ports[0].bits.uop.br_type connect slots_2.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[2].wakeup_ports[0].bits.uop.br_tag connect slots_2.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[2].wakeup_ports[0].bits.uop.br_mask connect slots_2.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[0].bits.uop.dis_col_sel connect slots_2.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_2.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_2.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_2.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_2.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_2.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[2].wakeup_ports[0].bits.uop.iw_issued connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[0] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[1] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[2] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[3] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[4] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[5] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[6] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[7] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[8] connect slots_2.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[0].bits.uop.fu_code[9] connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[0] connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[1] connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[2] connect slots_2.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[0].bits.uop.iq_type[3] connect slots_2.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[2].wakeup_ports[0].bits.uop.debug_pc connect slots_2.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[2].wakeup_ports[0].bits.uop.is_rvc connect slots_2.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[2].wakeup_ports[0].bits.uop.debug_inst connect slots_2.io.wakeup_ports[0].bits.uop.inst, issue_slots[2].wakeup_ports[0].bits.uop.inst connect slots_2.io.wakeup_ports[0].valid, issue_slots[2].wakeup_ports[0].valid connect slots_2.io.wakeup_ports[1].bits.rebusy, issue_slots[2].wakeup_ports[1].bits.rebusy connect slots_2.io.wakeup_ports[1].bits.speculative_mask, issue_slots[2].wakeup_ports[1].bits.speculative_mask connect slots_2.io.wakeup_ports[1].bits.bypassable, issue_slots[2].wakeup_ports[1].bits.bypassable connect slots_2.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[2].wakeup_ports[1].bits.uop.debug_tsrc connect slots_2.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[2].wakeup_ports[1].bits.uop.debug_fsrc connect slots_2.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[2].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_2.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[2].wakeup_ports[1].bits.uop.bp_debug_if connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_2.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[2].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_2.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[2].wakeup_ports[1].bits.uop.fp_typ connect slots_2.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[2].wakeup_ports[1].bits.uop.fp_rm connect slots_2.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[2].wakeup_ports[1].bits.uop.fp_val connect slots_2.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[2].wakeup_ports[1].bits.uop.fcn_op connect slots_2.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[2].wakeup_ports[1].bits.uop.fcn_dw connect slots_2.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[2].wakeup_ports[1].bits.uop.frs3_en connect slots_2.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[2].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_2.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[2].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_2.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[2].wakeup_ports[1].bits.uop.dst_rtype connect slots_2.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[2].wakeup_ports[1].bits.uop.lrs3 connect slots_2.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[2].wakeup_ports[1].bits.uop.lrs2 connect slots_2.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[2].wakeup_ports[1].bits.uop.lrs1 connect slots_2.io.wakeup_ports[1].bits.uop.ldst, issue_slots[2].wakeup_ports[1].bits.uop.ldst connect slots_2.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[2].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_2.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[2].wakeup_ports[1].bits.uop.csr_cmd connect slots_2.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[2].wakeup_ports[1].bits.uop.flush_on_commit connect slots_2.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[2].wakeup_ports[1].bits.uop.is_unique connect slots_2.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[2].wakeup_ports[1].bits.uop.uses_stq connect slots_2.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[2].wakeup_ports[1].bits.uop.uses_ldq connect slots_2.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[2].wakeup_ports[1].bits.uop.mem_signed connect slots_2.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[2].wakeup_ports[1].bits.uop.mem_size connect slots_2.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[2].wakeup_ports[1].bits.uop.mem_cmd connect slots_2.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[2].wakeup_ports[1].bits.uop.exc_cause connect slots_2.io.wakeup_ports[1].bits.uop.exception, issue_slots[2].wakeup_ports[1].bits.uop.exception connect slots_2.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[2].wakeup_ports[1].bits.uop.stale_pdst connect slots_2.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[2].wakeup_ports[1].bits.uop.ppred_busy connect slots_2.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs3_busy connect slots_2.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs2_busy connect slots_2.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[2].wakeup_ports[1].bits.uop.prs1_busy connect slots_2.io.wakeup_ports[1].bits.uop.ppred, issue_slots[2].wakeup_ports[1].bits.uop.ppred connect slots_2.io.wakeup_ports[1].bits.uop.prs3, issue_slots[2].wakeup_ports[1].bits.uop.prs3 connect slots_2.io.wakeup_ports[1].bits.uop.prs2, issue_slots[2].wakeup_ports[1].bits.uop.prs2 connect slots_2.io.wakeup_ports[1].bits.uop.prs1, issue_slots[2].wakeup_ports[1].bits.uop.prs1 connect slots_2.io.wakeup_ports[1].bits.uop.pdst, issue_slots[2].wakeup_ports[1].bits.uop.pdst connect slots_2.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[2].wakeup_ports[1].bits.uop.rxq_idx connect slots_2.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[2].wakeup_ports[1].bits.uop.stq_idx connect slots_2.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[2].wakeup_ports[1].bits.uop.ldq_idx connect slots_2.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[2].wakeup_ports[1].bits.uop.rob_idx connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_2.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_2.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[2].wakeup_ports[1].bits.uop.op2_sel connect slots_2.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[2].wakeup_ports[1].bits.uop.op1_sel connect slots_2.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[2].wakeup_ports[1].bits.uop.imm_packed connect slots_2.io.wakeup_ports[1].bits.uop.pimm, issue_slots[2].wakeup_ports[1].bits.uop.pimm connect slots_2.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[2].wakeup_ports[1].bits.uop.imm_sel connect slots_2.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[2].wakeup_ports[1].bits.uop.imm_rename connect slots_2.io.wakeup_ports[1].bits.uop.taken, issue_slots[2].wakeup_ports[1].bits.uop.taken connect slots_2.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[2].wakeup_ports[1].bits.uop.pc_lob connect slots_2.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[2].wakeup_ports[1].bits.uop.edge_inst connect slots_2.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[2].wakeup_ports[1].bits.uop.ftq_idx connect slots_2.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[2].wakeup_ports[1].bits.uop.is_mov connect slots_2.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[2].wakeup_ports[1].bits.uop.is_rocc connect slots_2.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[2].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_2.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[2].wakeup_ports[1].bits.uop.is_eret connect slots_2.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[2].wakeup_ports[1].bits.uop.is_amo connect slots_2.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[2].wakeup_ports[1].bits.uop.is_sfence connect slots_2.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[2].wakeup_ports[1].bits.uop.is_fencei connect slots_2.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[2].wakeup_ports[1].bits.uop.is_fence connect slots_2.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[2].wakeup_ports[1].bits.uop.is_sfb connect slots_2.io.wakeup_ports[1].bits.uop.br_type, issue_slots[2].wakeup_ports[1].bits.uop.br_type connect slots_2.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[2].wakeup_ports[1].bits.uop.br_tag connect slots_2.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[2].wakeup_ports[1].bits.uop.br_mask connect slots_2.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[2].wakeup_ports[1].bits.uop.dis_col_sel connect slots_2.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_2.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_2.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_2.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_2.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_2.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[2].wakeup_ports[1].bits.uop.iw_issued connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[0] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[1] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[2] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[3] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[4] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[5] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[6] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[7] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[8] connect slots_2.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[2].wakeup_ports[1].bits.uop.fu_code[9] connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[0] connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[1] connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[2] connect slots_2.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[2].wakeup_ports[1].bits.uop.iq_type[3] connect slots_2.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[2].wakeup_ports[1].bits.uop.debug_pc connect slots_2.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[2].wakeup_ports[1].bits.uop.is_rvc connect slots_2.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[2].wakeup_ports[1].bits.uop.debug_inst connect slots_2.io.wakeup_ports[1].bits.uop.inst, issue_slots[2].wakeup_ports[1].bits.uop.inst connect slots_2.io.wakeup_ports[1].valid, issue_slots[2].wakeup_ports[1].valid connect slots_2.io.squash_grant, issue_slots[2].squash_grant connect slots_2.io.clear, issue_slots[2].clear connect slots_2.io.kill, issue_slots[2].kill connect slots_2.io.brupdate.b2.target_offset, issue_slots[2].brupdate.b2.target_offset connect slots_2.io.brupdate.b2.jalr_target, issue_slots[2].brupdate.b2.jalr_target connect slots_2.io.brupdate.b2.pc_sel, issue_slots[2].brupdate.b2.pc_sel connect slots_2.io.brupdate.b2.cfi_type, issue_slots[2].brupdate.b2.cfi_type connect slots_2.io.brupdate.b2.taken, issue_slots[2].brupdate.b2.taken connect slots_2.io.brupdate.b2.mispredict, issue_slots[2].brupdate.b2.mispredict connect slots_2.io.brupdate.b2.uop.debug_tsrc, issue_slots[2].brupdate.b2.uop.debug_tsrc connect slots_2.io.brupdate.b2.uop.debug_fsrc, issue_slots[2].brupdate.b2.uop.debug_fsrc connect slots_2.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[2].brupdate.b2.uop.bp_xcpt_if connect slots_2.io.brupdate.b2.uop.bp_debug_if, issue_slots[2].brupdate.b2.uop.bp_debug_if connect slots_2.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[2].brupdate.b2.uop.xcpt_ma_if connect slots_2.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[2].brupdate.b2.uop.xcpt_ae_if connect slots_2.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[2].brupdate.b2.uop.xcpt_pf_if connect slots_2.io.brupdate.b2.uop.fp_typ, issue_slots[2].brupdate.b2.uop.fp_typ connect slots_2.io.brupdate.b2.uop.fp_rm, issue_slots[2].brupdate.b2.uop.fp_rm connect slots_2.io.brupdate.b2.uop.fp_val, issue_slots[2].brupdate.b2.uop.fp_val connect slots_2.io.brupdate.b2.uop.fcn_op, issue_slots[2].brupdate.b2.uop.fcn_op connect slots_2.io.brupdate.b2.uop.fcn_dw, issue_slots[2].brupdate.b2.uop.fcn_dw connect slots_2.io.brupdate.b2.uop.frs3_en, issue_slots[2].brupdate.b2.uop.frs3_en connect slots_2.io.brupdate.b2.uop.lrs2_rtype, issue_slots[2].brupdate.b2.uop.lrs2_rtype connect slots_2.io.brupdate.b2.uop.lrs1_rtype, issue_slots[2].brupdate.b2.uop.lrs1_rtype connect slots_2.io.brupdate.b2.uop.dst_rtype, issue_slots[2].brupdate.b2.uop.dst_rtype connect slots_2.io.brupdate.b2.uop.lrs3, issue_slots[2].brupdate.b2.uop.lrs3 connect slots_2.io.brupdate.b2.uop.lrs2, issue_slots[2].brupdate.b2.uop.lrs2 connect slots_2.io.brupdate.b2.uop.lrs1, issue_slots[2].brupdate.b2.uop.lrs1 connect slots_2.io.brupdate.b2.uop.ldst, issue_slots[2].brupdate.b2.uop.ldst connect slots_2.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[2].brupdate.b2.uop.ldst_is_rs1 connect slots_2.io.brupdate.b2.uop.csr_cmd, issue_slots[2].brupdate.b2.uop.csr_cmd connect slots_2.io.brupdate.b2.uop.flush_on_commit, issue_slots[2].brupdate.b2.uop.flush_on_commit connect slots_2.io.brupdate.b2.uop.is_unique, issue_slots[2].brupdate.b2.uop.is_unique connect slots_2.io.brupdate.b2.uop.uses_stq, issue_slots[2].brupdate.b2.uop.uses_stq connect slots_2.io.brupdate.b2.uop.uses_ldq, issue_slots[2].brupdate.b2.uop.uses_ldq connect slots_2.io.brupdate.b2.uop.mem_signed, issue_slots[2].brupdate.b2.uop.mem_signed connect slots_2.io.brupdate.b2.uop.mem_size, issue_slots[2].brupdate.b2.uop.mem_size connect slots_2.io.brupdate.b2.uop.mem_cmd, issue_slots[2].brupdate.b2.uop.mem_cmd connect slots_2.io.brupdate.b2.uop.exc_cause, issue_slots[2].brupdate.b2.uop.exc_cause connect slots_2.io.brupdate.b2.uop.exception, issue_slots[2].brupdate.b2.uop.exception connect slots_2.io.brupdate.b2.uop.stale_pdst, issue_slots[2].brupdate.b2.uop.stale_pdst connect slots_2.io.brupdate.b2.uop.ppred_busy, issue_slots[2].brupdate.b2.uop.ppred_busy connect slots_2.io.brupdate.b2.uop.prs3_busy, issue_slots[2].brupdate.b2.uop.prs3_busy connect slots_2.io.brupdate.b2.uop.prs2_busy, issue_slots[2].brupdate.b2.uop.prs2_busy connect slots_2.io.brupdate.b2.uop.prs1_busy, issue_slots[2].brupdate.b2.uop.prs1_busy connect slots_2.io.brupdate.b2.uop.ppred, issue_slots[2].brupdate.b2.uop.ppred connect slots_2.io.brupdate.b2.uop.prs3, issue_slots[2].brupdate.b2.uop.prs3 connect slots_2.io.brupdate.b2.uop.prs2, issue_slots[2].brupdate.b2.uop.prs2 connect slots_2.io.brupdate.b2.uop.prs1, issue_slots[2].brupdate.b2.uop.prs1 connect slots_2.io.brupdate.b2.uop.pdst, issue_slots[2].brupdate.b2.uop.pdst connect slots_2.io.brupdate.b2.uop.rxq_idx, issue_slots[2].brupdate.b2.uop.rxq_idx connect slots_2.io.brupdate.b2.uop.stq_idx, issue_slots[2].brupdate.b2.uop.stq_idx connect slots_2.io.brupdate.b2.uop.ldq_idx, issue_slots[2].brupdate.b2.uop.ldq_idx connect slots_2.io.brupdate.b2.uop.rob_idx, issue_slots[2].brupdate.b2.uop.rob_idx connect slots_2.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[2].brupdate.b2.uop.fp_ctrl.vec connect slots_2.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[2].brupdate.b2.uop.fp_ctrl.wflags connect slots_2.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[2].brupdate.b2.uop.fp_ctrl.sqrt connect slots_2.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[2].brupdate.b2.uop.fp_ctrl.div connect slots_2.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[2].brupdate.b2.uop.fp_ctrl.fma connect slots_2.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[2].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_2.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[2].brupdate.b2.uop.fp_ctrl.toint connect slots_2.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[2].brupdate.b2.uop.fp_ctrl.fromint connect slots_2.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_2.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_2.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[2].brupdate.b2.uop.fp_ctrl.swap23 connect slots_2.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[2].brupdate.b2.uop.fp_ctrl.swap12 connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren3 connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren2 connect slots_2.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[2].brupdate.b2.uop.fp_ctrl.ren1 connect slots_2.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[2].brupdate.b2.uop.fp_ctrl.wen connect slots_2.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[2].brupdate.b2.uop.fp_ctrl.ldst connect slots_2.io.brupdate.b2.uop.op2_sel, issue_slots[2].brupdate.b2.uop.op2_sel connect slots_2.io.brupdate.b2.uop.op1_sel, issue_slots[2].brupdate.b2.uop.op1_sel connect slots_2.io.brupdate.b2.uop.imm_packed, issue_slots[2].brupdate.b2.uop.imm_packed connect slots_2.io.brupdate.b2.uop.pimm, issue_slots[2].brupdate.b2.uop.pimm connect slots_2.io.brupdate.b2.uop.imm_sel, issue_slots[2].brupdate.b2.uop.imm_sel connect slots_2.io.brupdate.b2.uop.imm_rename, issue_slots[2].brupdate.b2.uop.imm_rename connect slots_2.io.brupdate.b2.uop.taken, issue_slots[2].brupdate.b2.uop.taken connect slots_2.io.brupdate.b2.uop.pc_lob, issue_slots[2].brupdate.b2.uop.pc_lob connect slots_2.io.brupdate.b2.uop.edge_inst, issue_slots[2].brupdate.b2.uop.edge_inst connect slots_2.io.brupdate.b2.uop.ftq_idx, issue_slots[2].brupdate.b2.uop.ftq_idx connect slots_2.io.brupdate.b2.uop.is_mov, issue_slots[2].brupdate.b2.uop.is_mov connect slots_2.io.brupdate.b2.uop.is_rocc, issue_slots[2].brupdate.b2.uop.is_rocc connect slots_2.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[2].brupdate.b2.uop.is_sys_pc2epc connect slots_2.io.brupdate.b2.uop.is_eret, issue_slots[2].brupdate.b2.uop.is_eret connect slots_2.io.brupdate.b2.uop.is_amo, issue_slots[2].brupdate.b2.uop.is_amo connect slots_2.io.brupdate.b2.uop.is_sfence, issue_slots[2].brupdate.b2.uop.is_sfence connect slots_2.io.brupdate.b2.uop.is_fencei, issue_slots[2].brupdate.b2.uop.is_fencei connect slots_2.io.brupdate.b2.uop.is_fence, issue_slots[2].brupdate.b2.uop.is_fence connect slots_2.io.brupdate.b2.uop.is_sfb, issue_slots[2].brupdate.b2.uop.is_sfb connect slots_2.io.brupdate.b2.uop.br_type, issue_slots[2].brupdate.b2.uop.br_type connect slots_2.io.brupdate.b2.uop.br_tag, issue_slots[2].brupdate.b2.uop.br_tag connect slots_2.io.brupdate.b2.uop.br_mask, issue_slots[2].brupdate.b2.uop.br_mask connect slots_2.io.brupdate.b2.uop.dis_col_sel, issue_slots[2].brupdate.b2.uop.dis_col_sel connect slots_2.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p3_bypass_hint connect slots_2.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p2_bypass_hint connect slots_2.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[2].brupdate.b2.uop.iw_p1_bypass_hint connect slots_2.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[2].brupdate.b2.uop.iw_p2_speculative_child connect slots_2.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[2].brupdate.b2.uop.iw_p1_speculative_child connect slots_2.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[2].brupdate.b2.uop.iw_issued_partial_dgen connect slots_2.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[2].brupdate.b2.uop.iw_issued_partial_agen connect slots_2.io.brupdate.b2.uop.iw_issued, issue_slots[2].brupdate.b2.uop.iw_issued connect slots_2.io.brupdate.b2.uop.fu_code[0], issue_slots[2].brupdate.b2.uop.fu_code[0] connect slots_2.io.brupdate.b2.uop.fu_code[1], issue_slots[2].brupdate.b2.uop.fu_code[1] connect slots_2.io.brupdate.b2.uop.fu_code[2], issue_slots[2].brupdate.b2.uop.fu_code[2] connect slots_2.io.brupdate.b2.uop.fu_code[3], issue_slots[2].brupdate.b2.uop.fu_code[3] connect slots_2.io.brupdate.b2.uop.fu_code[4], issue_slots[2].brupdate.b2.uop.fu_code[4] connect slots_2.io.brupdate.b2.uop.fu_code[5], issue_slots[2].brupdate.b2.uop.fu_code[5] connect slots_2.io.brupdate.b2.uop.fu_code[6], issue_slots[2].brupdate.b2.uop.fu_code[6] connect slots_2.io.brupdate.b2.uop.fu_code[7], issue_slots[2].brupdate.b2.uop.fu_code[7] connect slots_2.io.brupdate.b2.uop.fu_code[8], issue_slots[2].brupdate.b2.uop.fu_code[8] connect slots_2.io.brupdate.b2.uop.fu_code[9], issue_slots[2].brupdate.b2.uop.fu_code[9] connect slots_2.io.brupdate.b2.uop.iq_type[0], issue_slots[2].brupdate.b2.uop.iq_type[0] connect slots_2.io.brupdate.b2.uop.iq_type[1], issue_slots[2].brupdate.b2.uop.iq_type[1] connect slots_2.io.brupdate.b2.uop.iq_type[2], issue_slots[2].brupdate.b2.uop.iq_type[2] connect slots_2.io.brupdate.b2.uop.iq_type[3], issue_slots[2].brupdate.b2.uop.iq_type[3] connect slots_2.io.brupdate.b2.uop.debug_pc, issue_slots[2].brupdate.b2.uop.debug_pc connect slots_2.io.brupdate.b2.uop.is_rvc, issue_slots[2].brupdate.b2.uop.is_rvc connect slots_2.io.brupdate.b2.uop.debug_inst, issue_slots[2].brupdate.b2.uop.debug_inst connect slots_2.io.brupdate.b2.uop.inst, issue_slots[2].brupdate.b2.uop.inst connect slots_2.io.brupdate.b1.mispredict_mask, issue_slots[2].brupdate.b1.mispredict_mask connect slots_2.io.brupdate.b1.resolve_mask, issue_slots[2].brupdate.b1.resolve_mask connect issue_slots[2].out_uop.debug_tsrc, slots_2.io.out_uop.debug_tsrc connect issue_slots[2].out_uop.debug_fsrc, slots_2.io.out_uop.debug_fsrc connect issue_slots[2].out_uop.bp_xcpt_if, slots_2.io.out_uop.bp_xcpt_if connect issue_slots[2].out_uop.bp_debug_if, slots_2.io.out_uop.bp_debug_if connect issue_slots[2].out_uop.xcpt_ma_if, slots_2.io.out_uop.xcpt_ma_if connect issue_slots[2].out_uop.xcpt_ae_if, slots_2.io.out_uop.xcpt_ae_if connect issue_slots[2].out_uop.xcpt_pf_if, slots_2.io.out_uop.xcpt_pf_if connect issue_slots[2].out_uop.fp_typ, slots_2.io.out_uop.fp_typ connect issue_slots[2].out_uop.fp_rm, slots_2.io.out_uop.fp_rm connect issue_slots[2].out_uop.fp_val, slots_2.io.out_uop.fp_val connect issue_slots[2].out_uop.fcn_op, slots_2.io.out_uop.fcn_op connect issue_slots[2].out_uop.fcn_dw, slots_2.io.out_uop.fcn_dw connect issue_slots[2].out_uop.frs3_en, slots_2.io.out_uop.frs3_en connect issue_slots[2].out_uop.lrs2_rtype, slots_2.io.out_uop.lrs2_rtype connect issue_slots[2].out_uop.lrs1_rtype, slots_2.io.out_uop.lrs1_rtype connect issue_slots[2].out_uop.dst_rtype, slots_2.io.out_uop.dst_rtype connect issue_slots[2].out_uop.lrs3, slots_2.io.out_uop.lrs3 connect issue_slots[2].out_uop.lrs2, slots_2.io.out_uop.lrs2 connect issue_slots[2].out_uop.lrs1, slots_2.io.out_uop.lrs1 connect issue_slots[2].out_uop.ldst, slots_2.io.out_uop.ldst connect issue_slots[2].out_uop.ldst_is_rs1, slots_2.io.out_uop.ldst_is_rs1 connect issue_slots[2].out_uop.csr_cmd, slots_2.io.out_uop.csr_cmd connect issue_slots[2].out_uop.flush_on_commit, slots_2.io.out_uop.flush_on_commit connect issue_slots[2].out_uop.is_unique, slots_2.io.out_uop.is_unique connect issue_slots[2].out_uop.uses_stq, slots_2.io.out_uop.uses_stq connect issue_slots[2].out_uop.uses_ldq, slots_2.io.out_uop.uses_ldq connect issue_slots[2].out_uop.mem_signed, slots_2.io.out_uop.mem_signed connect issue_slots[2].out_uop.mem_size, slots_2.io.out_uop.mem_size connect issue_slots[2].out_uop.mem_cmd, slots_2.io.out_uop.mem_cmd connect issue_slots[2].out_uop.exc_cause, slots_2.io.out_uop.exc_cause connect issue_slots[2].out_uop.exception, slots_2.io.out_uop.exception connect issue_slots[2].out_uop.stale_pdst, slots_2.io.out_uop.stale_pdst connect issue_slots[2].out_uop.ppred_busy, slots_2.io.out_uop.ppred_busy connect issue_slots[2].out_uop.prs3_busy, slots_2.io.out_uop.prs3_busy connect issue_slots[2].out_uop.prs2_busy, slots_2.io.out_uop.prs2_busy connect issue_slots[2].out_uop.prs1_busy, slots_2.io.out_uop.prs1_busy connect issue_slots[2].out_uop.ppred, slots_2.io.out_uop.ppred connect issue_slots[2].out_uop.prs3, slots_2.io.out_uop.prs3 connect issue_slots[2].out_uop.prs2, slots_2.io.out_uop.prs2 connect issue_slots[2].out_uop.prs1, slots_2.io.out_uop.prs1 connect issue_slots[2].out_uop.pdst, slots_2.io.out_uop.pdst connect issue_slots[2].out_uop.rxq_idx, slots_2.io.out_uop.rxq_idx connect issue_slots[2].out_uop.stq_idx, slots_2.io.out_uop.stq_idx connect issue_slots[2].out_uop.ldq_idx, slots_2.io.out_uop.ldq_idx connect issue_slots[2].out_uop.rob_idx, slots_2.io.out_uop.rob_idx connect issue_slots[2].out_uop.fp_ctrl.vec, slots_2.io.out_uop.fp_ctrl.vec connect issue_slots[2].out_uop.fp_ctrl.wflags, slots_2.io.out_uop.fp_ctrl.wflags connect issue_slots[2].out_uop.fp_ctrl.sqrt, slots_2.io.out_uop.fp_ctrl.sqrt connect issue_slots[2].out_uop.fp_ctrl.div, slots_2.io.out_uop.fp_ctrl.div connect issue_slots[2].out_uop.fp_ctrl.fma, slots_2.io.out_uop.fp_ctrl.fma connect issue_slots[2].out_uop.fp_ctrl.fastpipe, slots_2.io.out_uop.fp_ctrl.fastpipe connect issue_slots[2].out_uop.fp_ctrl.toint, slots_2.io.out_uop.fp_ctrl.toint connect issue_slots[2].out_uop.fp_ctrl.fromint, slots_2.io.out_uop.fp_ctrl.fromint connect issue_slots[2].out_uop.fp_ctrl.typeTagOut, slots_2.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[2].out_uop.fp_ctrl.typeTagIn, slots_2.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[2].out_uop.fp_ctrl.swap23, slots_2.io.out_uop.fp_ctrl.swap23 connect issue_slots[2].out_uop.fp_ctrl.swap12, slots_2.io.out_uop.fp_ctrl.swap12 connect issue_slots[2].out_uop.fp_ctrl.ren3, slots_2.io.out_uop.fp_ctrl.ren3 connect issue_slots[2].out_uop.fp_ctrl.ren2, slots_2.io.out_uop.fp_ctrl.ren2 connect issue_slots[2].out_uop.fp_ctrl.ren1, slots_2.io.out_uop.fp_ctrl.ren1 connect issue_slots[2].out_uop.fp_ctrl.wen, slots_2.io.out_uop.fp_ctrl.wen connect issue_slots[2].out_uop.fp_ctrl.ldst, slots_2.io.out_uop.fp_ctrl.ldst connect issue_slots[2].out_uop.op2_sel, slots_2.io.out_uop.op2_sel connect issue_slots[2].out_uop.op1_sel, slots_2.io.out_uop.op1_sel connect issue_slots[2].out_uop.imm_packed, slots_2.io.out_uop.imm_packed connect issue_slots[2].out_uop.pimm, slots_2.io.out_uop.pimm connect issue_slots[2].out_uop.imm_sel, slots_2.io.out_uop.imm_sel connect issue_slots[2].out_uop.imm_rename, slots_2.io.out_uop.imm_rename connect issue_slots[2].out_uop.taken, slots_2.io.out_uop.taken connect issue_slots[2].out_uop.pc_lob, slots_2.io.out_uop.pc_lob connect issue_slots[2].out_uop.edge_inst, slots_2.io.out_uop.edge_inst connect issue_slots[2].out_uop.ftq_idx, slots_2.io.out_uop.ftq_idx connect issue_slots[2].out_uop.is_mov, slots_2.io.out_uop.is_mov connect issue_slots[2].out_uop.is_rocc, slots_2.io.out_uop.is_rocc connect issue_slots[2].out_uop.is_sys_pc2epc, slots_2.io.out_uop.is_sys_pc2epc connect issue_slots[2].out_uop.is_eret, slots_2.io.out_uop.is_eret connect issue_slots[2].out_uop.is_amo, slots_2.io.out_uop.is_amo connect issue_slots[2].out_uop.is_sfence, slots_2.io.out_uop.is_sfence connect issue_slots[2].out_uop.is_fencei, slots_2.io.out_uop.is_fencei connect issue_slots[2].out_uop.is_fence, slots_2.io.out_uop.is_fence connect issue_slots[2].out_uop.is_sfb, slots_2.io.out_uop.is_sfb connect issue_slots[2].out_uop.br_type, slots_2.io.out_uop.br_type connect issue_slots[2].out_uop.br_tag, slots_2.io.out_uop.br_tag connect issue_slots[2].out_uop.br_mask, slots_2.io.out_uop.br_mask connect issue_slots[2].out_uop.dis_col_sel, slots_2.io.out_uop.dis_col_sel connect issue_slots[2].out_uop.iw_p3_bypass_hint, slots_2.io.out_uop.iw_p3_bypass_hint connect issue_slots[2].out_uop.iw_p2_bypass_hint, slots_2.io.out_uop.iw_p2_bypass_hint connect issue_slots[2].out_uop.iw_p1_bypass_hint, slots_2.io.out_uop.iw_p1_bypass_hint connect issue_slots[2].out_uop.iw_p2_speculative_child, slots_2.io.out_uop.iw_p2_speculative_child connect issue_slots[2].out_uop.iw_p1_speculative_child, slots_2.io.out_uop.iw_p1_speculative_child connect issue_slots[2].out_uop.iw_issued_partial_dgen, slots_2.io.out_uop.iw_issued_partial_dgen connect issue_slots[2].out_uop.iw_issued_partial_agen, slots_2.io.out_uop.iw_issued_partial_agen connect issue_slots[2].out_uop.iw_issued, slots_2.io.out_uop.iw_issued connect issue_slots[2].out_uop.fu_code[0], slots_2.io.out_uop.fu_code[0] connect issue_slots[2].out_uop.fu_code[1], slots_2.io.out_uop.fu_code[1] connect issue_slots[2].out_uop.fu_code[2], slots_2.io.out_uop.fu_code[2] connect issue_slots[2].out_uop.fu_code[3], slots_2.io.out_uop.fu_code[3] connect issue_slots[2].out_uop.fu_code[4], slots_2.io.out_uop.fu_code[4] connect issue_slots[2].out_uop.fu_code[5], slots_2.io.out_uop.fu_code[5] connect issue_slots[2].out_uop.fu_code[6], slots_2.io.out_uop.fu_code[6] connect issue_slots[2].out_uop.fu_code[7], slots_2.io.out_uop.fu_code[7] connect issue_slots[2].out_uop.fu_code[8], slots_2.io.out_uop.fu_code[8] connect issue_slots[2].out_uop.fu_code[9], slots_2.io.out_uop.fu_code[9] connect issue_slots[2].out_uop.iq_type[0], slots_2.io.out_uop.iq_type[0] connect issue_slots[2].out_uop.iq_type[1], slots_2.io.out_uop.iq_type[1] connect issue_slots[2].out_uop.iq_type[2], slots_2.io.out_uop.iq_type[2] connect issue_slots[2].out_uop.iq_type[3], slots_2.io.out_uop.iq_type[3] connect issue_slots[2].out_uop.debug_pc, slots_2.io.out_uop.debug_pc connect issue_slots[2].out_uop.is_rvc, slots_2.io.out_uop.is_rvc connect issue_slots[2].out_uop.debug_inst, slots_2.io.out_uop.debug_inst connect issue_slots[2].out_uop.inst, slots_2.io.out_uop.inst connect slots_2.io.in_uop.bits.debug_tsrc, issue_slots[2].in_uop.bits.debug_tsrc connect slots_2.io.in_uop.bits.debug_fsrc, issue_slots[2].in_uop.bits.debug_fsrc connect slots_2.io.in_uop.bits.bp_xcpt_if, issue_slots[2].in_uop.bits.bp_xcpt_if connect slots_2.io.in_uop.bits.bp_debug_if, issue_slots[2].in_uop.bits.bp_debug_if connect slots_2.io.in_uop.bits.xcpt_ma_if, issue_slots[2].in_uop.bits.xcpt_ma_if connect slots_2.io.in_uop.bits.xcpt_ae_if, issue_slots[2].in_uop.bits.xcpt_ae_if connect slots_2.io.in_uop.bits.xcpt_pf_if, issue_slots[2].in_uop.bits.xcpt_pf_if connect slots_2.io.in_uop.bits.fp_typ, issue_slots[2].in_uop.bits.fp_typ connect slots_2.io.in_uop.bits.fp_rm, issue_slots[2].in_uop.bits.fp_rm connect slots_2.io.in_uop.bits.fp_val, issue_slots[2].in_uop.bits.fp_val connect slots_2.io.in_uop.bits.fcn_op, issue_slots[2].in_uop.bits.fcn_op connect slots_2.io.in_uop.bits.fcn_dw, issue_slots[2].in_uop.bits.fcn_dw connect slots_2.io.in_uop.bits.frs3_en, issue_slots[2].in_uop.bits.frs3_en connect slots_2.io.in_uop.bits.lrs2_rtype, issue_slots[2].in_uop.bits.lrs2_rtype connect slots_2.io.in_uop.bits.lrs1_rtype, issue_slots[2].in_uop.bits.lrs1_rtype connect slots_2.io.in_uop.bits.dst_rtype, issue_slots[2].in_uop.bits.dst_rtype connect slots_2.io.in_uop.bits.lrs3, issue_slots[2].in_uop.bits.lrs3 connect slots_2.io.in_uop.bits.lrs2, issue_slots[2].in_uop.bits.lrs2 connect slots_2.io.in_uop.bits.lrs1, issue_slots[2].in_uop.bits.lrs1 connect slots_2.io.in_uop.bits.ldst, issue_slots[2].in_uop.bits.ldst connect slots_2.io.in_uop.bits.ldst_is_rs1, issue_slots[2].in_uop.bits.ldst_is_rs1 connect slots_2.io.in_uop.bits.csr_cmd, issue_slots[2].in_uop.bits.csr_cmd connect slots_2.io.in_uop.bits.flush_on_commit, issue_slots[2].in_uop.bits.flush_on_commit connect slots_2.io.in_uop.bits.is_unique, issue_slots[2].in_uop.bits.is_unique connect slots_2.io.in_uop.bits.uses_stq, issue_slots[2].in_uop.bits.uses_stq connect slots_2.io.in_uop.bits.uses_ldq, issue_slots[2].in_uop.bits.uses_ldq connect slots_2.io.in_uop.bits.mem_signed, issue_slots[2].in_uop.bits.mem_signed connect slots_2.io.in_uop.bits.mem_size, issue_slots[2].in_uop.bits.mem_size connect slots_2.io.in_uop.bits.mem_cmd, issue_slots[2].in_uop.bits.mem_cmd connect slots_2.io.in_uop.bits.exc_cause, issue_slots[2].in_uop.bits.exc_cause connect slots_2.io.in_uop.bits.exception, issue_slots[2].in_uop.bits.exception connect slots_2.io.in_uop.bits.stale_pdst, issue_slots[2].in_uop.bits.stale_pdst connect slots_2.io.in_uop.bits.ppred_busy, issue_slots[2].in_uop.bits.ppred_busy connect slots_2.io.in_uop.bits.prs3_busy, issue_slots[2].in_uop.bits.prs3_busy connect slots_2.io.in_uop.bits.prs2_busy, issue_slots[2].in_uop.bits.prs2_busy connect slots_2.io.in_uop.bits.prs1_busy, issue_slots[2].in_uop.bits.prs1_busy connect slots_2.io.in_uop.bits.ppred, issue_slots[2].in_uop.bits.ppred connect slots_2.io.in_uop.bits.prs3, issue_slots[2].in_uop.bits.prs3 connect slots_2.io.in_uop.bits.prs2, issue_slots[2].in_uop.bits.prs2 connect slots_2.io.in_uop.bits.prs1, issue_slots[2].in_uop.bits.prs1 connect slots_2.io.in_uop.bits.pdst, issue_slots[2].in_uop.bits.pdst connect slots_2.io.in_uop.bits.rxq_idx, issue_slots[2].in_uop.bits.rxq_idx connect slots_2.io.in_uop.bits.stq_idx, issue_slots[2].in_uop.bits.stq_idx connect slots_2.io.in_uop.bits.ldq_idx, issue_slots[2].in_uop.bits.ldq_idx connect slots_2.io.in_uop.bits.rob_idx, issue_slots[2].in_uop.bits.rob_idx connect slots_2.io.in_uop.bits.fp_ctrl.vec, issue_slots[2].in_uop.bits.fp_ctrl.vec connect slots_2.io.in_uop.bits.fp_ctrl.wflags, issue_slots[2].in_uop.bits.fp_ctrl.wflags connect slots_2.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[2].in_uop.bits.fp_ctrl.sqrt connect slots_2.io.in_uop.bits.fp_ctrl.div, issue_slots[2].in_uop.bits.fp_ctrl.div connect slots_2.io.in_uop.bits.fp_ctrl.fma, issue_slots[2].in_uop.bits.fp_ctrl.fma connect slots_2.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].in_uop.bits.fp_ctrl.fastpipe connect slots_2.io.in_uop.bits.fp_ctrl.toint, issue_slots[2].in_uop.bits.fp_ctrl.toint connect slots_2.io.in_uop.bits.fp_ctrl.fromint, issue_slots[2].in_uop.bits.fp_ctrl.fromint connect slots_2.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut connect slots_2.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn connect slots_2.io.in_uop.bits.fp_ctrl.swap23, issue_slots[2].in_uop.bits.fp_ctrl.swap23 connect slots_2.io.in_uop.bits.fp_ctrl.swap12, issue_slots[2].in_uop.bits.fp_ctrl.swap12 connect slots_2.io.in_uop.bits.fp_ctrl.ren3, issue_slots[2].in_uop.bits.fp_ctrl.ren3 connect slots_2.io.in_uop.bits.fp_ctrl.ren2, issue_slots[2].in_uop.bits.fp_ctrl.ren2 connect slots_2.io.in_uop.bits.fp_ctrl.ren1, issue_slots[2].in_uop.bits.fp_ctrl.ren1 connect slots_2.io.in_uop.bits.fp_ctrl.wen, issue_slots[2].in_uop.bits.fp_ctrl.wen connect slots_2.io.in_uop.bits.fp_ctrl.ldst, issue_slots[2].in_uop.bits.fp_ctrl.ldst connect slots_2.io.in_uop.bits.op2_sel, issue_slots[2].in_uop.bits.op2_sel connect slots_2.io.in_uop.bits.op1_sel, issue_slots[2].in_uop.bits.op1_sel connect slots_2.io.in_uop.bits.imm_packed, issue_slots[2].in_uop.bits.imm_packed connect slots_2.io.in_uop.bits.pimm, issue_slots[2].in_uop.bits.pimm connect slots_2.io.in_uop.bits.imm_sel, issue_slots[2].in_uop.bits.imm_sel connect slots_2.io.in_uop.bits.imm_rename, issue_slots[2].in_uop.bits.imm_rename connect slots_2.io.in_uop.bits.taken, issue_slots[2].in_uop.bits.taken connect slots_2.io.in_uop.bits.pc_lob, issue_slots[2].in_uop.bits.pc_lob connect slots_2.io.in_uop.bits.edge_inst, issue_slots[2].in_uop.bits.edge_inst connect slots_2.io.in_uop.bits.ftq_idx, issue_slots[2].in_uop.bits.ftq_idx connect slots_2.io.in_uop.bits.is_mov, issue_slots[2].in_uop.bits.is_mov connect slots_2.io.in_uop.bits.is_rocc, issue_slots[2].in_uop.bits.is_rocc connect slots_2.io.in_uop.bits.is_sys_pc2epc, issue_slots[2].in_uop.bits.is_sys_pc2epc connect slots_2.io.in_uop.bits.is_eret, issue_slots[2].in_uop.bits.is_eret connect slots_2.io.in_uop.bits.is_amo, issue_slots[2].in_uop.bits.is_amo connect slots_2.io.in_uop.bits.is_sfence, issue_slots[2].in_uop.bits.is_sfence connect slots_2.io.in_uop.bits.is_fencei, issue_slots[2].in_uop.bits.is_fencei connect slots_2.io.in_uop.bits.is_fence, issue_slots[2].in_uop.bits.is_fence connect slots_2.io.in_uop.bits.is_sfb, issue_slots[2].in_uop.bits.is_sfb connect slots_2.io.in_uop.bits.br_type, issue_slots[2].in_uop.bits.br_type connect slots_2.io.in_uop.bits.br_tag, issue_slots[2].in_uop.bits.br_tag connect slots_2.io.in_uop.bits.br_mask, issue_slots[2].in_uop.bits.br_mask connect slots_2.io.in_uop.bits.dis_col_sel, issue_slots[2].in_uop.bits.dis_col_sel connect slots_2.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[2].in_uop.bits.iw_p3_bypass_hint connect slots_2.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[2].in_uop.bits.iw_p2_bypass_hint connect slots_2.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[2].in_uop.bits.iw_p1_bypass_hint connect slots_2.io.in_uop.bits.iw_p2_speculative_child, issue_slots[2].in_uop.bits.iw_p2_speculative_child connect slots_2.io.in_uop.bits.iw_p1_speculative_child, issue_slots[2].in_uop.bits.iw_p1_speculative_child connect slots_2.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[2].in_uop.bits.iw_issued_partial_dgen connect slots_2.io.in_uop.bits.iw_issued_partial_agen, issue_slots[2].in_uop.bits.iw_issued_partial_agen connect slots_2.io.in_uop.bits.iw_issued, issue_slots[2].in_uop.bits.iw_issued connect slots_2.io.in_uop.bits.fu_code[0], issue_slots[2].in_uop.bits.fu_code[0] connect slots_2.io.in_uop.bits.fu_code[1], issue_slots[2].in_uop.bits.fu_code[1] connect slots_2.io.in_uop.bits.fu_code[2], issue_slots[2].in_uop.bits.fu_code[2] connect slots_2.io.in_uop.bits.fu_code[3], issue_slots[2].in_uop.bits.fu_code[3] connect slots_2.io.in_uop.bits.fu_code[4], issue_slots[2].in_uop.bits.fu_code[4] connect slots_2.io.in_uop.bits.fu_code[5], issue_slots[2].in_uop.bits.fu_code[5] connect slots_2.io.in_uop.bits.fu_code[6], issue_slots[2].in_uop.bits.fu_code[6] connect slots_2.io.in_uop.bits.fu_code[7], issue_slots[2].in_uop.bits.fu_code[7] connect slots_2.io.in_uop.bits.fu_code[8], issue_slots[2].in_uop.bits.fu_code[8] connect slots_2.io.in_uop.bits.fu_code[9], issue_slots[2].in_uop.bits.fu_code[9] connect slots_2.io.in_uop.bits.iq_type[0], issue_slots[2].in_uop.bits.iq_type[0] connect slots_2.io.in_uop.bits.iq_type[1], issue_slots[2].in_uop.bits.iq_type[1] connect slots_2.io.in_uop.bits.iq_type[2], issue_slots[2].in_uop.bits.iq_type[2] connect slots_2.io.in_uop.bits.iq_type[3], issue_slots[2].in_uop.bits.iq_type[3] connect slots_2.io.in_uop.bits.debug_pc, issue_slots[2].in_uop.bits.debug_pc connect slots_2.io.in_uop.bits.is_rvc, issue_slots[2].in_uop.bits.is_rvc connect slots_2.io.in_uop.bits.debug_inst, issue_slots[2].in_uop.bits.debug_inst connect slots_2.io.in_uop.bits.inst, issue_slots[2].in_uop.bits.inst connect slots_2.io.in_uop.valid, issue_slots[2].in_uop.valid connect issue_slots[2].iss_uop.debug_tsrc, slots_2.io.iss_uop.debug_tsrc connect issue_slots[2].iss_uop.debug_fsrc, slots_2.io.iss_uop.debug_fsrc connect issue_slots[2].iss_uop.bp_xcpt_if, slots_2.io.iss_uop.bp_xcpt_if connect issue_slots[2].iss_uop.bp_debug_if, slots_2.io.iss_uop.bp_debug_if connect issue_slots[2].iss_uop.xcpt_ma_if, slots_2.io.iss_uop.xcpt_ma_if connect issue_slots[2].iss_uop.xcpt_ae_if, slots_2.io.iss_uop.xcpt_ae_if connect issue_slots[2].iss_uop.xcpt_pf_if, slots_2.io.iss_uop.xcpt_pf_if connect issue_slots[2].iss_uop.fp_typ, slots_2.io.iss_uop.fp_typ connect issue_slots[2].iss_uop.fp_rm, slots_2.io.iss_uop.fp_rm connect issue_slots[2].iss_uop.fp_val, slots_2.io.iss_uop.fp_val connect issue_slots[2].iss_uop.fcn_op, slots_2.io.iss_uop.fcn_op connect issue_slots[2].iss_uop.fcn_dw, slots_2.io.iss_uop.fcn_dw connect issue_slots[2].iss_uop.frs3_en, slots_2.io.iss_uop.frs3_en connect issue_slots[2].iss_uop.lrs2_rtype, slots_2.io.iss_uop.lrs2_rtype connect issue_slots[2].iss_uop.lrs1_rtype, slots_2.io.iss_uop.lrs1_rtype connect issue_slots[2].iss_uop.dst_rtype, slots_2.io.iss_uop.dst_rtype connect issue_slots[2].iss_uop.lrs3, slots_2.io.iss_uop.lrs3 connect issue_slots[2].iss_uop.lrs2, slots_2.io.iss_uop.lrs2 connect issue_slots[2].iss_uop.lrs1, slots_2.io.iss_uop.lrs1 connect issue_slots[2].iss_uop.ldst, slots_2.io.iss_uop.ldst connect issue_slots[2].iss_uop.ldst_is_rs1, slots_2.io.iss_uop.ldst_is_rs1 connect issue_slots[2].iss_uop.csr_cmd, slots_2.io.iss_uop.csr_cmd connect issue_slots[2].iss_uop.flush_on_commit, slots_2.io.iss_uop.flush_on_commit connect issue_slots[2].iss_uop.is_unique, slots_2.io.iss_uop.is_unique connect issue_slots[2].iss_uop.uses_stq, slots_2.io.iss_uop.uses_stq connect issue_slots[2].iss_uop.uses_ldq, slots_2.io.iss_uop.uses_ldq connect issue_slots[2].iss_uop.mem_signed, slots_2.io.iss_uop.mem_signed connect issue_slots[2].iss_uop.mem_size, slots_2.io.iss_uop.mem_size connect issue_slots[2].iss_uop.mem_cmd, slots_2.io.iss_uop.mem_cmd connect issue_slots[2].iss_uop.exc_cause, slots_2.io.iss_uop.exc_cause connect issue_slots[2].iss_uop.exception, slots_2.io.iss_uop.exception connect issue_slots[2].iss_uop.stale_pdst, slots_2.io.iss_uop.stale_pdst connect issue_slots[2].iss_uop.ppred_busy, slots_2.io.iss_uop.ppred_busy connect issue_slots[2].iss_uop.prs3_busy, slots_2.io.iss_uop.prs3_busy connect issue_slots[2].iss_uop.prs2_busy, slots_2.io.iss_uop.prs2_busy connect issue_slots[2].iss_uop.prs1_busy, slots_2.io.iss_uop.prs1_busy connect issue_slots[2].iss_uop.ppred, slots_2.io.iss_uop.ppred connect issue_slots[2].iss_uop.prs3, slots_2.io.iss_uop.prs3 connect issue_slots[2].iss_uop.prs2, slots_2.io.iss_uop.prs2 connect issue_slots[2].iss_uop.prs1, slots_2.io.iss_uop.prs1 connect issue_slots[2].iss_uop.pdst, slots_2.io.iss_uop.pdst connect issue_slots[2].iss_uop.rxq_idx, slots_2.io.iss_uop.rxq_idx connect issue_slots[2].iss_uop.stq_idx, slots_2.io.iss_uop.stq_idx connect issue_slots[2].iss_uop.ldq_idx, slots_2.io.iss_uop.ldq_idx connect issue_slots[2].iss_uop.rob_idx, slots_2.io.iss_uop.rob_idx connect issue_slots[2].iss_uop.fp_ctrl.vec, slots_2.io.iss_uop.fp_ctrl.vec connect issue_slots[2].iss_uop.fp_ctrl.wflags, slots_2.io.iss_uop.fp_ctrl.wflags connect issue_slots[2].iss_uop.fp_ctrl.sqrt, slots_2.io.iss_uop.fp_ctrl.sqrt connect issue_slots[2].iss_uop.fp_ctrl.div, slots_2.io.iss_uop.fp_ctrl.div connect issue_slots[2].iss_uop.fp_ctrl.fma, slots_2.io.iss_uop.fp_ctrl.fma connect issue_slots[2].iss_uop.fp_ctrl.fastpipe, slots_2.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[2].iss_uop.fp_ctrl.toint, slots_2.io.iss_uop.fp_ctrl.toint connect issue_slots[2].iss_uop.fp_ctrl.fromint, slots_2.io.iss_uop.fp_ctrl.fromint connect issue_slots[2].iss_uop.fp_ctrl.typeTagOut, slots_2.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[2].iss_uop.fp_ctrl.typeTagIn, slots_2.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[2].iss_uop.fp_ctrl.swap23, slots_2.io.iss_uop.fp_ctrl.swap23 connect issue_slots[2].iss_uop.fp_ctrl.swap12, slots_2.io.iss_uop.fp_ctrl.swap12 connect issue_slots[2].iss_uop.fp_ctrl.ren3, slots_2.io.iss_uop.fp_ctrl.ren3 connect issue_slots[2].iss_uop.fp_ctrl.ren2, slots_2.io.iss_uop.fp_ctrl.ren2 connect issue_slots[2].iss_uop.fp_ctrl.ren1, slots_2.io.iss_uop.fp_ctrl.ren1 connect issue_slots[2].iss_uop.fp_ctrl.wen, slots_2.io.iss_uop.fp_ctrl.wen connect issue_slots[2].iss_uop.fp_ctrl.ldst, slots_2.io.iss_uop.fp_ctrl.ldst connect issue_slots[2].iss_uop.op2_sel, slots_2.io.iss_uop.op2_sel connect issue_slots[2].iss_uop.op1_sel, slots_2.io.iss_uop.op1_sel connect issue_slots[2].iss_uop.imm_packed, slots_2.io.iss_uop.imm_packed connect issue_slots[2].iss_uop.pimm, slots_2.io.iss_uop.pimm connect issue_slots[2].iss_uop.imm_sel, slots_2.io.iss_uop.imm_sel connect issue_slots[2].iss_uop.imm_rename, slots_2.io.iss_uop.imm_rename connect issue_slots[2].iss_uop.taken, slots_2.io.iss_uop.taken connect issue_slots[2].iss_uop.pc_lob, slots_2.io.iss_uop.pc_lob connect issue_slots[2].iss_uop.edge_inst, slots_2.io.iss_uop.edge_inst connect issue_slots[2].iss_uop.ftq_idx, slots_2.io.iss_uop.ftq_idx connect issue_slots[2].iss_uop.is_mov, slots_2.io.iss_uop.is_mov connect issue_slots[2].iss_uop.is_rocc, slots_2.io.iss_uop.is_rocc connect issue_slots[2].iss_uop.is_sys_pc2epc, slots_2.io.iss_uop.is_sys_pc2epc connect issue_slots[2].iss_uop.is_eret, slots_2.io.iss_uop.is_eret connect issue_slots[2].iss_uop.is_amo, slots_2.io.iss_uop.is_amo connect issue_slots[2].iss_uop.is_sfence, slots_2.io.iss_uop.is_sfence connect issue_slots[2].iss_uop.is_fencei, slots_2.io.iss_uop.is_fencei connect issue_slots[2].iss_uop.is_fence, slots_2.io.iss_uop.is_fence connect issue_slots[2].iss_uop.is_sfb, slots_2.io.iss_uop.is_sfb connect issue_slots[2].iss_uop.br_type, slots_2.io.iss_uop.br_type connect issue_slots[2].iss_uop.br_tag, slots_2.io.iss_uop.br_tag connect issue_slots[2].iss_uop.br_mask, slots_2.io.iss_uop.br_mask connect issue_slots[2].iss_uop.dis_col_sel, slots_2.io.iss_uop.dis_col_sel connect issue_slots[2].iss_uop.iw_p3_bypass_hint, slots_2.io.iss_uop.iw_p3_bypass_hint connect issue_slots[2].iss_uop.iw_p2_bypass_hint, slots_2.io.iss_uop.iw_p2_bypass_hint connect issue_slots[2].iss_uop.iw_p1_bypass_hint, slots_2.io.iss_uop.iw_p1_bypass_hint connect issue_slots[2].iss_uop.iw_p2_speculative_child, slots_2.io.iss_uop.iw_p2_speculative_child connect issue_slots[2].iss_uop.iw_p1_speculative_child, slots_2.io.iss_uop.iw_p1_speculative_child connect issue_slots[2].iss_uop.iw_issued_partial_dgen, slots_2.io.iss_uop.iw_issued_partial_dgen connect issue_slots[2].iss_uop.iw_issued_partial_agen, slots_2.io.iss_uop.iw_issued_partial_agen connect issue_slots[2].iss_uop.iw_issued, slots_2.io.iss_uop.iw_issued connect issue_slots[2].iss_uop.fu_code[0], slots_2.io.iss_uop.fu_code[0] connect issue_slots[2].iss_uop.fu_code[1], slots_2.io.iss_uop.fu_code[1] connect issue_slots[2].iss_uop.fu_code[2], slots_2.io.iss_uop.fu_code[2] connect issue_slots[2].iss_uop.fu_code[3], slots_2.io.iss_uop.fu_code[3] connect issue_slots[2].iss_uop.fu_code[4], slots_2.io.iss_uop.fu_code[4] connect issue_slots[2].iss_uop.fu_code[5], slots_2.io.iss_uop.fu_code[5] connect issue_slots[2].iss_uop.fu_code[6], slots_2.io.iss_uop.fu_code[6] connect issue_slots[2].iss_uop.fu_code[7], slots_2.io.iss_uop.fu_code[7] connect issue_slots[2].iss_uop.fu_code[8], slots_2.io.iss_uop.fu_code[8] connect issue_slots[2].iss_uop.fu_code[9], slots_2.io.iss_uop.fu_code[9] connect issue_slots[2].iss_uop.iq_type[0], slots_2.io.iss_uop.iq_type[0] connect issue_slots[2].iss_uop.iq_type[1], slots_2.io.iss_uop.iq_type[1] connect issue_slots[2].iss_uop.iq_type[2], slots_2.io.iss_uop.iq_type[2] connect issue_slots[2].iss_uop.iq_type[3], slots_2.io.iss_uop.iq_type[3] connect issue_slots[2].iss_uop.debug_pc, slots_2.io.iss_uop.debug_pc connect issue_slots[2].iss_uop.is_rvc, slots_2.io.iss_uop.is_rvc connect issue_slots[2].iss_uop.debug_inst, slots_2.io.iss_uop.debug_inst connect issue_slots[2].iss_uop.inst, slots_2.io.iss_uop.inst connect slots_2.io.grant, issue_slots[2].grant connect issue_slots[2].request, slots_2.io.request connect issue_slots[2].will_be_valid, slots_2.io.will_be_valid connect issue_slots[2].valid, slots_2.io.valid connect slots_3.io.child_rebusys, issue_slots[3].child_rebusys connect slots_3.io.pred_wakeup_port.bits, issue_slots[3].pred_wakeup_port.bits connect slots_3.io.pred_wakeup_port.valid, issue_slots[3].pred_wakeup_port.valid connect slots_3.io.wakeup_ports[0].bits.rebusy, issue_slots[3].wakeup_ports[0].bits.rebusy connect slots_3.io.wakeup_ports[0].bits.speculative_mask, issue_slots[3].wakeup_ports[0].bits.speculative_mask connect slots_3.io.wakeup_ports[0].bits.bypassable, issue_slots[3].wakeup_ports[0].bits.bypassable connect slots_3.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[0].bits.uop.debug_tsrc connect slots_3.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[0].bits.uop.debug_fsrc connect slots_3.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_3.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[0].bits.uop.bp_debug_if connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_3.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_3.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[3].wakeup_ports[0].bits.uop.fp_typ connect slots_3.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[3].wakeup_ports[0].bits.uop.fp_rm connect slots_3.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[3].wakeup_ports[0].bits.uop.fp_val connect slots_3.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[3].wakeup_ports[0].bits.uop.fcn_op connect slots_3.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[0].bits.uop.fcn_dw connect slots_3.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[3].wakeup_ports[0].bits.uop.frs3_en connect slots_3.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_3.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_3.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[0].bits.uop.dst_rtype connect slots_3.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[3].wakeup_ports[0].bits.uop.lrs3 connect slots_3.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[3].wakeup_ports[0].bits.uop.lrs2 connect slots_3.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[3].wakeup_ports[0].bits.uop.lrs1 connect slots_3.io.wakeup_ports[0].bits.uop.ldst, issue_slots[3].wakeup_ports[0].bits.uop.ldst connect slots_3.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_3.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[0].bits.uop.csr_cmd connect slots_3.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[0].bits.uop.flush_on_commit connect slots_3.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[3].wakeup_ports[0].bits.uop.is_unique connect slots_3.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[3].wakeup_ports[0].bits.uop.uses_stq connect slots_3.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[0].bits.uop.uses_ldq connect slots_3.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[3].wakeup_ports[0].bits.uop.mem_signed connect slots_3.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[3].wakeup_ports[0].bits.uop.mem_size connect slots_3.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[0].bits.uop.mem_cmd connect slots_3.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[3].wakeup_ports[0].bits.uop.exc_cause connect slots_3.io.wakeup_ports[0].bits.uop.exception, issue_slots[3].wakeup_ports[0].bits.uop.exception connect slots_3.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[0].bits.uop.stale_pdst connect slots_3.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[0].bits.uop.ppred_busy connect slots_3.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs3_busy connect slots_3.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs2_busy connect slots_3.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[0].bits.uop.prs1_busy connect slots_3.io.wakeup_ports[0].bits.uop.ppred, issue_slots[3].wakeup_ports[0].bits.uop.ppred connect slots_3.io.wakeup_ports[0].bits.uop.prs3, issue_slots[3].wakeup_ports[0].bits.uop.prs3 connect slots_3.io.wakeup_ports[0].bits.uop.prs2, issue_slots[3].wakeup_ports[0].bits.uop.prs2 connect slots_3.io.wakeup_ports[0].bits.uop.prs1, issue_slots[3].wakeup_ports[0].bits.uop.prs1 connect slots_3.io.wakeup_ports[0].bits.uop.pdst, issue_slots[3].wakeup_ports[0].bits.uop.pdst connect slots_3.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[0].bits.uop.rxq_idx connect slots_3.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[3].wakeup_ports[0].bits.uop.stq_idx connect slots_3.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[0].bits.uop.ldq_idx connect slots_3.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[3].wakeup_ports[0].bits.uop.rob_idx connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_3.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_3.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[3].wakeup_ports[0].bits.uop.op2_sel connect slots_3.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[3].wakeup_ports[0].bits.uop.op1_sel connect slots_3.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[3].wakeup_ports[0].bits.uop.imm_packed connect slots_3.io.wakeup_ports[0].bits.uop.pimm, issue_slots[3].wakeup_ports[0].bits.uop.pimm connect slots_3.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[3].wakeup_ports[0].bits.uop.imm_sel connect slots_3.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[3].wakeup_ports[0].bits.uop.imm_rename connect slots_3.io.wakeup_ports[0].bits.uop.taken, issue_slots[3].wakeup_ports[0].bits.uop.taken connect slots_3.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[3].wakeup_ports[0].bits.uop.pc_lob connect slots_3.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[3].wakeup_ports[0].bits.uop.edge_inst connect slots_3.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[0].bits.uop.ftq_idx connect slots_3.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[3].wakeup_ports[0].bits.uop.is_mov connect slots_3.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[3].wakeup_ports[0].bits.uop.is_rocc connect slots_3.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_3.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[3].wakeup_ports[0].bits.uop.is_eret connect slots_3.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[3].wakeup_ports[0].bits.uop.is_amo connect slots_3.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[3].wakeup_ports[0].bits.uop.is_sfence connect slots_3.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[3].wakeup_ports[0].bits.uop.is_fencei connect slots_3.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[3].wakeup_ports[0].bits.uop.is_fence connect slots_3.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[3].wakeup_ports[0].bits.uop.is_sfb connect slots_3.io.wakeup_ports[0].bits.uop.br_type, issue_slots[3].wakeup_ports[0].bits.uop.br_type connect slots_3.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[3].wakeup_ports[0].bits.uop.br_tag connect slots_3.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[3].wakeup_ports[0].bits.uop.br_mask connect slots_3.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[0].bits.uop.dis_col_sel connect slots_3.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_3.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_3.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_3.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_3.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_3.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[3].wakeup_ports[0].bits.uop.iw_issued connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[0] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[1] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[2] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[3] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[4] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[5] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[6] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[7] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[8] connect slots_3.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[0].bits.uop.fu_code[9] connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[0] connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[1] connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[2] connect slots_3.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[0].bits.uop.iq_type[3] connect slots_3.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[3].wakeup_ports[0].bits.uop.debug_pc connect slots_3.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[3].wakeup_ports[0].bits.uop.is_rvc connect slots_3.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[3].wakeup_ports[0].bits.uop.debug_inst connect slots_3.io.wakeup_ports[0].bits.uop.inst, issue_slots[3].wakeup_ports[0].bits.uop.inst connect slots_3.io.wakeup_ports[0].valid, issue_slots[3].wakeup_ports[0].valid connect slots_3.io.wakeup_ports[1].bits.rebusy, issue_slots[3].wakeup_ports[1].bits.rebusy connect slots_3.io.wakeup_ports[1].bits.speculative_mask, issue_slots[3].wakeup_ports[1].bits.speculative_mask connect slots_3.io.wakeup_ports[1].bits.bypassable, issue_slots[3].wakeup_ports[1].bits.bypassable connect slots_3.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[3].wakeup_ports[1].bits.uop.debug_tsrc connect slots_3.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[3].wakeup_ports[1].bits.uop.debug_fsrc connect slots_3.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[3].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_3.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[3].wakeup_ports[1].bits.uop.bp_debug_if connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_3.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[3].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_3.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[3].wakeup_ports[1].bits.uop.fp_typ connect slots_3.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[3].wakeup_ports[1].bits.uop.fp_rm connect slots_3.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[3].wakeup_ports[1].bits.uop.fp_val connect slots_3.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[3].wakeup_ports[1].bits.uop.fcn_op connect slots_3.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[3].wakeup_ports[1].bits.uop.fcn_dw connect slots_3.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[3].wakeup_ports[1].bits.uop.frs3_en connect slots_3.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[3].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_3.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[3].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_3.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[3].wakeup_ports[1].bits.uop.dst_rtype connect slots_3.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[3].wakeup_ports[1].bits.uop.lrs3 connect slots_3.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[3].wakeup_ports[1].bits.uop.lrs2 connect slots_3.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[3].wakeup_ports[1].bits.uop.lrs1 connect slots_3.io.wakeup_ports[1].bits.uop.ldst, issue_slots[3].wakeup_ports[1].bits.uop.ldst connect slots_3.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[3].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_3.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[3].wakeup_ports[1].bits.uop.csr_cmd connect slots_3.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[3].wakeup_ports[1].bits.uop.flush_on_commit connect slots_3.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[3].wakeup_ports[1].bits.uop.is_unique connect slots_3.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[3].wakeup_ports[1].bits.uop.uses_stq connect slots_3.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[3].wakeup_ports[1].bits.uop.uses_ldq connect slots_3.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[3].wakeup_ports[1].bits.uop.mem_signed connect slots_3.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[3].wakeup_ports[1].bits.uop.mem_size connect slots_3.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[3].wakeup_ports[1].bits.uop.mem_cmd connect slots_3.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[3].wakeup_ports[1].bits.uop.exc_cause connect slots_3.io.wakeup_ports[1].bits.uop.exception, issue_slots[3].wakeup_ports[1].bits.uop.exception connect slots_3.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[3].wakeup_ports[1].bits.uop.stale_pdst connect slots_3.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[3].wakeup_ports[1].bits.uop.ppred_busy connect slots_3.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs3_busy connect slots_3.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs2_busy connect slots_3.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[3].wakeup_ports[1].bits.uop.prs1_busy connect slots_3.io.wakeup_ports[1].bits.uop.ppred, issue_slots[3].wakeup_ports[1].bits.uop.ppred connect slots_3.io.wakeup_ports[1].bits.uop.prs3, issue_slots[3].wakeup_ports[1].bits.uop.prs3 connect slots_3.io.wakeup_ports[1].bits.uop.prs2, issue_slots[3].wakeup_ports[1].bits.uop.prs2 connect slots_3.io.wakeup_ports[1].bits.uop.prs1, issue_slots[3].wakeup_ports[1].bits.uop.prs1 connect slots_3.io.wakeup_ports[1].bits.uop.pdst, issue_slots[3].wakeup_ports[1].bits.uop.pdst connect slots_3.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[3].wakeup_ports[1].bits.uop.rxq_idx connect slots_3.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[3].wakeup_ports[1].bits.uop.stq_idx connect slots_3.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[3].wakeup_ports[1].bits.uop.ldq_idx connect slots_3.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[3].wakeup_ports[1].bits.uop.rob_idx connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_3.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_3.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[3].wakeup_ports[1].bits.uop.op2_sel connect slots_3.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[3].wakeup_ports[1].bits.uop.op1_sel connect slots_3.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[3].wakeup_ports[1].bits.uop.imm_packed connect slots_3.io.wakeup_ports[1].bits.uop.pimm, issue_slots[3].wakeup_ports[1].bits.uop.pimm connect slots_3.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[3].wakeup_ports[1].bits.uop.imm_sel connect slots_3.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[3].wakeup_ports[1].bits.uop.imm_rename connect slots_3.io.wakeup_ports[1].bits.uop.taken, issue_slots[3].wakeup_ports[1].bits.uop.taken connect slots_3.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[3].wakeup_ports[1].bits.uop.pc_lob connect slots_3.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[3].wakeup_ports[1].bits.uop.edge_inst connect slots_3.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[3].wakeup_ports[1].bits.uop.ftq_idx connect slots_3.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[3].wakeup_ports[1].bits.uop.is_mov connect slots_3.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[3].wakeup_ports[1].bits.uop.is_rocc connect slots_3.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[3].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_3.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[3].wakeup_ports[1].bits.uop.is_eret connect slots_3.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[3].wakeup_ports[1].bits.uop.is_amo connect slots_3.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[3].wakeup_ports[1].bits.uop.is_sfence connect slots_3.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[3].wakeup_ports[1].bits.uop.is_fencei connect slots_3.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[3].wakeup_ports[1].bits.uop.is_fence connect slots_3.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[3].wakeup_ports[1].bits.uop.is_sfb connect slots_3.io.wakeup_ports[1].bits.uop.br_type, issue_slots[3].wakeup_ports[1].bits.uop.br_type connect slots_3.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[3].wakeup_ports[1].bits.uop.br_tag connect slots_3.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[3].wakeup_ports[1].bits.uop.br_mask connect slots_3.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[3].wakeup_ports[1].bits.uop.dis_col_sel connect slots_3.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_3.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_3.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_3.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_3.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_3.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[3].wakeup_ports[1].bits.uop.iw_issued connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[0] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[1] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[2] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[3] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[4] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[5] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[6] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[7] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[8] connect slots_3.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[3].wakeup_ports[1].bits.uop.fu_code[9] connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[0] connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[1] connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[2] connect slots_3.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[3].wakeup_ports[1].bits.uop.iq_type[3] connect slots_3.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[3].wakeup_ports[1].bits.uop.debug_pc connect slots_3.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[3].wakeup_ports[1].bits.uop.is_rvc connect slots_3.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[3].wakeup_ports[1].bits.uop.debug_inst connect slots_3.io.wakeup_ports[1].bits.uop.inst, issue_slots[3].wakeup_ports[1].bits.uop.inst connect slots_3.io.wakeup_ports[1].valid, issue_slots[3].wakeup_ports[1].valid connect slots_3.io.squash_grant, issue_slots[3].squash_grant connect slots_3.io.clear, issue_slots[3].clear connect slots_3.io.kill, issue_slots[3].kill connect slots_3.io.brupdate.b2.target_offset, issue_slots[3].brupdate.b2.target_offset connect slots_3.io.brupdate.b2.jalr_target, issue_slots[3].brupdate.b2.jalr_target connect slots_3.io.brupdate.b2.pc_sel, issue_slots[3].brupdate.b2.pc_sel connect slots_3.io.brupdate.b2.cfi_type, issue_slots[3].brupdate.b2.cfi_type connect slots_3.io.brupdate.b2.taken, issue_slots[3].brupdate.b2.taken connect slots_3.io.brupdate.b2.mispredict, issue_slots[3].brupdate.b2.mispredict connect slots_3.io.brupdate.b2.uop.debug_tsrc, issue_slots[3].brupdate.b2.uop.debug_tsrc connect slots_3.io.brupdate.b2.uop.debug_fsrc, issue_slots[3].brupdate.b2.uop.debug_fsrc connect slots_3.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[3].brupdate.b2.uop.bp_xcpt_if connect slots_3.io.brupdate.b2.uop.bp_debug_if, issue_slots[3].brupdate.b2.uop.bp_debug_if connect slots_3.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[3].brupdate.b2.uop.xcpt_ma_if connect slots_3.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[3].brupdate.b2.uop.xcpt_ae_if connect slots_3.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[3].brupdate.b2.uop.xcpt_pf_if connect slots_3.io.brupdate.b2.uop.fp_typ, issue_slots[3].brupdate.b2.uop.fp_typ connect slots_3.io.brupdate.b2.uop.fp_rm, issue_slots[3].brupdate.b2.uop.fp_rm connect slots_3.io.brupdate.b2.uop.fp_val, issue_slots[3].brupdate.b2.uop.fp_val connect slots_3.io.brupdate.b2.uop.fcn_op, issue_slots[3].brupdate.b2.uop.fcn_op connect slots_3.io.brupdate.b2.uop.fcn_dw, issue_slots[3].brupdate.b2.uop.fcn_dw connect slots_3.io.brupdate.b2.uop.frs3_en, issue_slots[3].brupdate.b2.uop.frs3_en connect slots_3.io.brupdate.b2.uop.lrs2_rtype, issue_slots[3].brupdate.b2.uop.lrs2_rtype connect slots_3.io.brupdate.b2.uop.lrs1_rtype, issue_slots[3].brupdate.b2.uop.lrs1_rtype connect slots_3.io.brupdate.b2.uop.dst_rtype, issue_slots[3].brupdate.b2.uop.dst_rtype connect slots_3.io.brupdate.b2.uop.lrs3, issue_slots[3].brupdate.b2.uop.lrs3 connect slots_3.io.brupdate.b2.uop.lrs2, issue_slots[3].brupdate.b2.uop.lrs2 connect slots_3.io.brupdate.b2.uop.lrs1, issue_slots[3].brupdate.b2.uop.lrs1 connect slots_3.io.brupdate.b2.uop.ldst, issue_slots[3].brupdate.b2.uop.ldst connect slots_3.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[3].brupdate.b2.uop.ldst_is_rs1 connect slots_3.io.brupdate.b2.uop.csr_cmd, issue_slots[3].brupdate.b2.uop.csr_cmd connect slots_3.io.brupdate.b2.uop.flush_on_commit, issue_slots[3].brupdate.b2.uop.flush_on_commit connect slots_3.io.brupdate.b2.uop.is_unique, issue_slots[3].brupdate.b2.uop.is_unique connect slots_3.io.brupdate.b2.uop.uses_stq, issue_slots[3].brupdate.b2.uop.uses_stq connect slots_3.io.brupdate.b2.uop.uses_ldq, issue_slots[3].brupdate.b2.uop.uses_ldq connect slots_3.io.brupdate.b2.uop.mem_signed, issue_slots[3].brupdate.b2.uop.mem_signed connect slots_3.io.brupdate.b2.uop.mem_size, issue_slots[3].brupdate.b2.uop.mem_size connect slots_3.io.brupdate.b2.uop.mem_cmd, issue_slots[3].brupdate.b2.uop.mem_cmd connect slots_3.io.brupdate.b2.uop.exc_cause, issue_slots[3].brupdate.b2.uop.exc_cause connect slots_3.io.brupdate.b2.uop.exception, issue_slots[3].brupdate.b2.uop.exception connect slots_3.io.brupdate.b2.uop.stale_pdst, issue_slots[3].brupdate.b2.uop.stale_pdst connect slots_3.io.brupdate.b2.uop.ppred_busy, issue_slots[3].brupdate.b2.uop.ppred_busy connect slots_3.io.brupdate.b2.uop.prs3_busy, issue_slots[3].brupdate.b2.uop.prs3_busy connect slots_3.io.brupdate.b2.uop.prs2_busy, issue_slots[3].brupdate.b2.uop.prs2_busy connect slots_3.io.brupdate.b2.uop.prs1_busy, issue_slots[3].brupdate.b2.uop.prs1_busy connect slots_3.io.brupdate.b2.uop.ppred, issue_slots[3].brupdate.b2.uop.ppred connect slots_3.io.brupdate.b2.uop.prs3, issue_slots[3].brupdate.b2.uop.prs3 connect slots_3.io.brupdate.b2.uop.prs2, issue_slots[3].brupdate.b2.uop.prs2 connect slots_3.io.brupdate.b2.uop.prs1, issue_slots[3].brupdate.b2.uop.prs1 connect slots_3.io.brupdate.b2.uop.pdst, issue_slots[3].brupdate.b2.uop.pdst connect slots_3.io.brupdate.b2.uop.rxq_idx, issue_slots[3].brupdate.b2.uop.rxq_idx connect slots_3.io.brupdate.b2.uop.stq_idx, issue_slots[3].brupdate.b2.uop.stq_idx connect slots_3.io.brupdate.b2.uop.ldq_idx, issue_slots[3].brupdate.b2.uop.ldq_idx connect slots_3.io.brupdate.b2.uop.rob_idx, issue_slots[3].brupdate.b2.uop.rob_idx connect slots_3.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[3].brupdate.b2.uop.fp_ctrl.vec connect slots_3.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[3].brupdate.b2.uop.fp_ctrl.wflags connect slots_3.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[3].brupdate.b2.uop.fp_ctrl.sqrt connect slots_3.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[3].brupdate.b2.uop.fp_ctrl.div connect slots_3.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[3].brupdate.b2.uop.fp_ctrl.fma connect slots_3.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[3].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_3.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[3].brupdate.b2.uop.fp_ctrl.toint connect slots_3.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[3].brupdate.b2.uop.fp_ctrl.fromint connect slots_3.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_3.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_3.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[3].brupdate.b2.uop.fp_ctrl.swap23 connect slots_3.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[3].brupdate.b2.uop.fp_ctrl.swap12 connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren3 connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren2 connect slots_3.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[3].brupdate.b2.uop.fp_ctrl.ren1 connect slots_3.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[3].brupdate.b2.uop.fp_ctrl.wen connect slots_3.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[3].brupdate.b2.uop.fp_ctrl.ldst connect slots_3.io.brupdate.b2.uop.op2_sel, issue_slots[3].brupdate.b2.uop.op2_sel connect slots_3.io.brupdate.b2.uop.op1_sel, issue_slots[3].brupdate.b2.uop.op1_sel connect slots_3.io.brupdate.b2.uop.imm_packed, issue_slots[3].brupdate.b2.uop.imm_packed connect slots_3.io.brupdate.b2.uop.pimm, issue_slots[3].brupdate.b2.uop.pimm connect slots_3.io.brupdate.b2.uop.imm_sel, issue_slots[3].brupdate.b2.uop.imm_sel connect slots_3.io.brupdate.b2.uop.imm_rename, issue_slots[3].brupdate.b2.uop.imm_rename connect slots_3.io.brupdate.b2.uop.taken, issue_slots[3].brupdate.b2.uop.taken connect slots_3.io.brupdate.b2.uop.pc_lob, issue_slots[3].brupdate.b2.uop.pc_lob connect slots_3.io.brupdate.b2.uop.edge_inst, issue_slots[3].brupdate.b2.uop.edge_inst connect slots_3.io.brupdate.b2.uop.ftq_idx, issue_slots[3].brupdate.b2.uop.ftq_idx connect slots_3.io.brupdate.b2.uop.is_mov, issue_slots[3].brupdate.b2.uop.is_mov connect slots_3.io.brupdate.b2.uop.is_rocc, issue_slots[3].brupdate.b2.uop.is_rocc connect slots_3.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[3].brupdate.b2.uop.is_sys_pc2epc connect slots_3.io.brupdate.b2.uop.is_eret, issue_slots[3].brupdate.b2.uop.is_eret connect slots_3.io.brupdate.b2.uop.is_amo, issue_slots[3].brupdate.b2.uop.is_amo connect slots_3.io.brupdate.b2.uop.is_sfence, issue_slots[3].brupdate.b2.uop.is_sfence connect slots_3.io.brupdate.b2.uop.is_fencei, issue_slots[3].brupdate.b2.uop.is_fencei connect slots_3.io.brupdate.b2.uop.is_fence, issue_slots[3].brupdate.b2.uop.is_fence connect slots_3.io.brupdate.b2.uop.is_sfb, issue_slots[3].brupdate.b2.uop.is_sfb connect slots_3.io.brupdate.b2.uop.br_type, issue_slots[3].brupdate.b2.uop.br_type connect slots_3.io.brupdate.b2.uop.br_tag, issue_slots[3].brupdate.b2.uop.br_tag connect slots_3.io.brupdate.b2.uop.br_mask, issue_slots[3].brupdate.b2.uop.br_mask connect slots_3.io.brupdate.b2.uop.dis_col_sel, issue_slots[3].brupdate.b2.uop.dis_col_sel connect slots_3.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p3_bypass_hint connect slots_3.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p2_bypass_hint connect slots_3.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[3].brupdate.b2.uop.iw_p1_bypass_hint connect slots_3.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[3].brupdate.b2.uop.iw_p2_speculative_child connect slots_3.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[3].brupdate.b2.uop.iw_p1_speculative_child connect slots_3.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[3].brupdate.b2.uop.iw_issued_partial_dgen connect slots_3.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[3].brupdate.b2.uop.iw_issued_partial_agen connect slots_3.io.brupdate.b2.uop.iw_issued, issue_slots[3].brupdate.b2.uop.iw_issued connect slots_3.io.brupdate.b2.uop.fu_code[0], issue_slots[3].brupdate.b2.uop.fu_code[0] connect slots_3.io.brupdate.b2.uop.fu_code[1], issue_slots[3].brupdate.b2.uop.fu_code[1] connect slots_3.io.brupdate.b2.uop.fu_code[2], issue_slots[3].brupdate.b2.uop.fu_code[2] connect slots_3.io.brupdate.b2.uop.fu_code[3], issue_slots[3].brupdate.b2.uop.fu_code[3] connect slots_3.io.brupdate.b2.uop.fu_code[4], issue_slots[3].brupdate.b2.uop.fu_code[4] connect slots_3.io.brupdate.b2.uop.fu_code[5], issue_slots[3].brupdate.b2.uop.fu_code[5] connect slots_3.io.brupdate.b2.uop.fu_code[6], issue_slots[3].brupdate.b2.uop.fu_code[6] connect slots_3.io.brupdate.b2.uop.fu_code[7], issue_slots[3].brupdate.b2.uop.fu_code[7] connect slots_3.io.brupdate.b2.uop.fu_code[8], issue_slots[3].brupdate.b2.uop.fu_code[8] connect slots_3.io.brupdate.b2.uop.fu_code[9], issue_slots[3].brupdate.b2.uop.fu_code[9] connect slots_3.io.brupdate.b2.uop.iq_type[0], issue_slots[3].brupdate.b2.uop.iq_type[0] connect slots_3.io.brupdate.b2.uop.iq_type[1], issue_slots[3].brupdate.b2.uop.iq_type[1] connect slots_3.io.brupdate.b2.uop.iq_type[2], issue_slots[3].brupdate.b2.uop.iq_type[2] connect slots_3.io.brupdate.b2.uop.iq_type[3], issue_slots[3].brupdate.b2.uop.iq_type[3] connect slots_3.io.brupdate.b2.uop.debug_pc, issue_slots[3].brupdate.b2.uop.debug_pc connect slots_3.io.brupdate.b2.uop.is_rvc, issue_slots[3].brupdate.b2.uop.is_rvc connect slots_3.io.brupdate.b2.uop.debug_inst, issue_slots[3].brupdate.b2.uop.debug_inst connect slots_3.io.brupdate.b2.uop.inst, issue_slots[3].brupdate.b2.uop.inst connect slots_3.io.brupdate.b1.mispredict_mask, issue_slots[3].brupdate.b1.mispredict_mask connect slots_3.io.brupdate.b1.resolve_mask, issue_slots[3].brupdate.b1.resolve_mask connect issue_slots[3].out_uop.debug_tsrc, slots_3.io.out_uop.debug_tsrc connect issue_slots[3].out_uop.debug_fsrc, slots_3.io.out_uop.debug_fsrc connect issue_slots[3].out_uop.bp_xcpt_if, slots_3.io.out_uop.bp_xcpt_if connect issue_slots[3].out_uop.bp_debug_if, slots_3.io.out_uop.bp_debug_if connect issue_slots[3].out_uop.xcpt_ma_if, slots_3.io.out_uop.xcpt_ma_if connect issue_slots[3].out_uop.xcpt_ae_if, slots_3.io.out_uop.xcpt_ae_if connect issue_slots[3].out_uop.xcpt_pf_if, slots_3.io.out_uop.xcpt_pf_if connect issue_slots[3].out_uop.fp_typ, slots_3.io.out_uop.fp_typ connect issue_slots[3].out_uop.fp_rm, slots_3.io.out_uop.fp_rm connect issue_slots[3].out_uop.fp_val, slots_3.io.out_uop.fp_val connect issue_slots[3].out_uop.fcn_op, slots_3.io.out_uop.fcn_op connect issue_slots[3].out_uop.fcn_dw, slots_3.io.out_uop.fcn_dw connect issue_slots[3].out_uop.frs3_en, slots_3.io.out_uop.frs3_en connect issue_slots[3].out_uop.lrs2_rtype, slots_3.io.out_uop.lrs2_rtype connect issue_slots[3].out_uop.lrs1_rtype, slots_3.io.out_uop.lrs1_rtype connect issue_slots[3].out_uop.dst_rtype, slots_3.io.out_uop.dst_rtype connect issue_slots[3].out_uop.lrs3, slots_3.io.out_uop.lrs3 connect issue_slots[3].out_uop.lrs2, slots_3.io.out_uop.lrs2 connect issue_slots[3].out_uop.lrs1, slots_3.io.out_uop.lrs1 connect issue_slots[3].out_uop.ldst, slots_3.io.out_uop.ldst connect issue_slots[3].out_uop.ldst_is_rs1, slots_3.io.out_uop.ldst_is_rs1 connect issue_slots[3].out_uop.csr_cmd, slots_3.io.out_uop.csr_cmd connect issue_slots[3].out_uop.flush_on_commit, slots_3.io.out_uop.flush_on_commit connect issue_slots[3].out_uop.is_unique, slots_3.io.out_uop.is_unique connect issue_slots[3].out_uop.uses_stq, slots_3.io.out_uop.uses_stq connect issue_slots[3].out_uop.uses_ldq, slots_3.io.out_uop.uses_ldq connect issue_slots[3].out_uop.mem_signed, slots_3.io.out_uop.mem_signed connect issue_slots[3].out_uop.mem_size, slots_3.io.out_uop.mem_size connect issue_slots[3].out_uop.mem_cmd, slots_3.io.out_uop.mem_cmd connect issue_slots[3].out_uop.exc_cause, slots_3.io.out_uop.exc_cause connect issue_slots[3].out_uop.exception, slots_3.io.out_uop.exception connect issue_slots[3].out_uop.stale_pdst, slots_3.io.out_uop.stale_pdst connect issue_slots[3].out_uop.ppred_busy, slots_3.io.out_uop.ppred_busy connect issue_slots[3].out_uop.prs3_busy, slots_3.io.out_uop.prs3_busy connect issue_slots[3].out_uop.prs2_busy, slots_3.io.out_uop.prs2_busy connect issue_slots[3].out_uop.prs1_busy, slots_3.io.out_uop.prs1_busy connect issue_slots[3].out_uop.ppred, slots_3.io.out_uop.ppred connect issue_slots[3].out_uop.prs3, slots_3.io.out_uop.prs3 connect issue_slots[3].out_uop.prs2, slots_3.io.out_uop.prs2 connect issue_slots[3].out_uop.prs1, slots_3.io.out_uop.prs1 connect issue_slots[3].out_uop.pdst, slots_3.io.out_uop.pdst connect issue_slots[3].out_uop.rxq_idx, slots_3.io.out_uop.rxq_idx connect issue_slots[3].out_uop.stq_idx, slots_3.io.out_uop.stq_idx connect issue_slots[3].out_uop.ldq_idx, slots_3.io.out_uop.ldq_idx connect issue_slots[3].out_uop.rob_idx, slots_3.io.out_uop.rob_idx connect issue_slots[3].out_uop.fp_ctrl.vec, slots_3.io.out_uop.fp_ctrl.vec connect issue_slots[3].out_uop.fp_ctrl.wflags, slots_3.io.out_uop.fp_ctrl.wflags connect issue_slots[3].out_uop.fp_ctrl.sqrt, slots_3.io.out_uop.fp_ctrl.sqrt connect issue_slots[3].out_uop.fp_ctrl.div, slots_3.io.out_uop.fp_ctrl.div connect issue_slots[3].out_uop.fp_ctrl.fma, slots_3.io.out_uop.fp_ctrl.fma connect issue_slots[3].out_uop.fp_ctrl.fastpipe, slots_3.io.out_uop.fp_ctrl.fastpipe connect issue_slots[3].out_uop.fp_ctrl.toint, slots_3.io.out_uop.fp_ctrl.toint connect issue_slots[3].out_uop.fp_ctrl.fromint, slots_3.io.out_uop.fp_ctrl.fromint connect issue_slots[3].out_uop.fp_ctrl.typeTagOut, slots_3.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[3].out_uop.fp_ctrl.typeTagIn, slots_3.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[3].out_uop.fp_ctrl.swap23, slots_3.io.out_uop.fp_ctrl.swap23 connect issue_slots[3].out_uop.fp_ctrl.swap12, slots_3.io.out_uop.fp_ctrl.swap12 connect issue_slots[3].out_uop.fp_ctrl.ren3, slots_3.io.out_uop.fp_ctrl.ren3 connect issue_slots[3].out_uop.fp_ctrl.ren2, slots_3.io.out_uop.fp_ctrl.ren2 connect issue_slots[3].out_uop.fp_ctrl.ren1, slots_3.io.out_uop.fp_ctrl.ren1 connect issue_slots[3].out_uop.fp_ctrl.wen, slots_3.io.out_uop.fp_ctrl.wen connect issue_slots[3].out_uop.fp_ctrl.ldst, slots_3.io.out_uop.fp_ctrl.ldst connect issue_slots[3].out_uop.op2_sel, slots_3.io.out_uop.op2_sel connect issue_slots[3].out_uop.op1_sel, slots_3.io.out_uop.op1_sel connect issue_slots[3].out_uop.imm_packed, slots_3.io.out_uop.imm_packed connect issue_slots[3].out_uop.pimm, slots_3.io.out_uop.pimm connect issue_slots[3].out_uop.imm_sel, slots_3.io.out_uop.imm_sel connect issue_slots[3].out_uop.imm_rename, slots_3.io.out_uop.imm_rename connect issue_slots[3].out_uop.taken, slots_3.io.out_uop.taken connect issue_slots[3].out_uop.pc_lob, slots_3.io.out_uop.pc_lob connect issue_slots[3].out_uop.edge_inst, slots_3.io.out_uop.edge_inst connect issue_slots[3].out_uop.ftq_idx, slots_3.io.out_uop.ftq_idx connect issue_slots[3].out_uop.is_mov, slots_3.io.out_uop.is_mov connect issue_slots[3].out_uop.is_rocc, slots_3.io.out_uop.is_rocc connect issue_slots[3].out_uop.is_sys_pc2epc, slots_3.io.out_uop.is_sys_pc2epc connect issue_slots[3].out_uop.is_eret, slots_3.io.out_uop.is_eret connect issue_slots[3].out_uop.is_amo, slots_3.io.out_uop.is_amo connect issue_slots[3].out_uop.is_sfence, slots_3.io.out_uop.is_sfence connect issue_slots[3].out_uop.is_fencei, slots_3.io.out_uop.is_fencei connect issue_slots[3].out_uop.is_fence, slots_3.io.out_uop.is_fence connect issue_slots[3].out_uop.is_sfb, slots_3.io.out_uop.is_sfb connect issue_slots[3].out_uop.br_type, slots_3.io.out_uop.br_type connect issue_slots[3].out_uop.br_tag, slots_3.io.out_uop.br_tag connect issue_slots[3].out_uop.br_mask, slots_3.io.out_uop.br_mask connect issue_slots[3].out_uop.dis_col_sel, slots_3.io.out_uop.dis_col_sel connect issue_slots[3].out_uop.iw_p3_bypass_hint, slots_3.io.out_uop.iw_p3_bypass_hint connect issue_slots[3].out_uop.iw_p2_bypass_hint, slots_3.io.out_uop.iw_p2_bypass_hint connect issue_slots[3].out_uop.iw_p1_bypass_hint, slots_3.io.out_uop.iw_p1_bypass_hint connect issue_slots[3].out_uop.iw_p2_speculative_child, slots_3.io.out_uop.iw_p2_speculative_child connect issue_slots[3].out_uop.iw_p1_speculative_child, slots_3.io.out_uop.iw_p1_speculative_child connect issue_slots[3].out_uop.iw_issued_partial_dgen, slots_3.io.out_uop.iw_issued_partial_dgen connect issue_slots[3].out_uop.iw_issued_partial_agen, slots_3.io.out_uop.iw_issued_partial_agen connect issue_slots[3].out_uop.iw_issued, slots_3.io.out_uop.iw_issued connect issue_slots[3].out_uop.fu_code[0], slots_3.io.out_uop.fu_code[0] connect issue_slots[3].out_uop.fu_code[1], slots_3.io.out_uop.fu_code[1] connect issue_slots[3].out_uop.fu_code[2], slots_3.io.out_uop.fu_code[2] connect issue_slots[3].out_uop.fu_code[3], slots_3.io.out_uop.fu_code[3] connect issue_slots[3].out_uop.fu_code[4], slots_3.io.out_uop.fu_code[4] connect issue_slots[3].out_uop.fu_code[5], slots_3.io.out_uop.fu_code[5] connect issue_slots[3].out_uop.fu_code[6], slots_3.io.out_uop.fu_code[6] connect issue_slots[3].out_uop.fu_code[7], slots_3.io.out_uop.fu_code[7] connect issue_slots[3].out_uop.fu_code[8], slots_3.io.out_uop.fu_code[8] connect issue_slots[3].out_uop.fu_code[9], slots_3.io.out_uop.fu_code[9] connect issue_slots[3].out_uop.iq_type[0], slots_3.io.out_uop.iq_type[0] connect issue_slots[3].out_uop.iq_type[1], slots_3.io.out_uop.iq_type[1] connect issue_slots[3].out_uop.iq_type[2], slots_3.io.out_uop.iq_type[2] connect issue_slots[3].out_uop.iq_type[3], slots_3.io.out_uop.iq_type[3] connect issue_slots[3].out_uop.debug_pc, slots_3.io.out_uop.debug_pc connect issue_slots[3].out_uop.is_rvc, slots_3.io.out_uop.is_rvc connect issue_slots[3].out_uop.debug_inst, slots_3.io.out_uop.debug_inst connect issue_slots[3].out_uop.inst, slots_3.io.out_uop.inst connect slots_3.io.in_uop.bits.debug_tsrc, issue_slots[3].in_uop.bits.debug_tsrc connect slots_3.io.in_uop.bits.debug_fsrc, issue_slots[3].in_uop.bits.debug_fsrc connect slots_3.io.in_uop.bits.bp_xcpt_if, issue_slots[3].in_uop.bits.bp_xcpt_if connect slots_3.io.in_uop.bits.bp_debug_if, issue_slots[3].in_uop.bits.bp_debug_if connect slots_3.io.in_uop.bits.xcpt_ma_if, issue_slots[3].in_uop.bits.xcpt_ma_if connect slots_3.io.in_uop.bits.xcpt_ae_if, issue_slots[3].in_uop.bits.xcpt_ae_if connect slots_3.io.in_uop.bits.xcpt_pf_if, issue_slots[3].in_uop.bits.xcpt_pf_if connect slots_3.io.in_uop.bits.fp_typ, issue_slots[3].in_uop.bits.fp_typ connect slots_3.io.in_uop.bits.fp_rm, issue_slots[3].in_uop.bits.fp_rm connect slots_3.io.in_uop.bits.fp_val, issue_slots[3].in_uop.bits.fp_val connect slots_3.io.in_uop.bits.fcn_op, issue_slots[3].in_uop.bits.fcn_op connect slots_3.io.in_uop.bits.fcn_dw, issue_slots[3].in_uop.bits.fcn_dw connect slots_3.io.in_uop.bits.frs3_en, issue_slots[3].in_uop.bits.frs3_en connect slots_3.io.in_uop.bits.lrs2_rtype, issue_slots[3].in_uop.bits.lrs2_rtype connect slots_3.io.in_uop.bits.lrs1_rtype, issue_slots[3].in_uop.bits.lrs1_rtype connect slots_3.io.in_uop.bits.dst_rtype, issue_slots[3].in_uop.bits.dst_rtype connect slots_3.io.in_uop.bits.lrs3, issue_slots[3].in_uop.bits.lrs3 connect slots_3.io.in_uop.bits.lrs2, issue_slots[3].in_uop.bits.lrs2 connect slots_3.io.in_uop.bits.lrs1, issue_slots[3].in_uop.bits.lrs1 connect slots_3.io.in_uop.bits.ldst, issue_slots[3].in_uop.bits.ldst connect slots_3.io.in_uop.bits.ldst_is_rs1, issue_slots[3].in_uop.bits.ldst_is_rs1 connect slots_3.io.in_uop.bits.csr_cmd, issue_slots[3].in_uop.bits.csr_cmd connect slots_3.io.in_uop.bits.flush_on_commit, issue_slots[3].in_uop.bits.flush_on_commit connect slots_3.io.in_uop.bits.is_unique, issue_slots[3].in_uop.bits.is_unique connect slots_3.io.in_uop.bits.uses_stq, issue_slots[3].in_uop.bits.uses_stq connect slots_3.io.in_uop.bits.uses_ldq, issue_slots[3].in_uop.bits.uses_ldq connect slots_3.io.in_uop.bits.mem_signed, issue_slots[3].in_uop.bits.mem_signed connect slots_3.io.in_uop.bits.mem_size, issue_slots[3].in_uop.bits.mem_size connect slots_3.io.in_uop.bits.mem_cmd, issue_slots[3].in_uop.bits.mem_cmd connect slots_3.io.in_uop.bits.exc_cause, issue_slots[3].in_uop.bits.exc_cause connect slots_3.io.in_uop.bits.exception, issue_slots[3].in_uop.bits.exception connect slots_3.io.in_uop.bits.stale_pdst, issue_slots[3].in_uop.bits.stale_pdst connect slots_3.io.in_uop.bits.ppred_busy, issue_slots[3].in_uop.bits.ppred_busy connect slots_3.io.in_uop.bits.prs3_busy, issue_slots[3].in_uop.bits.prs3_busy connect slots_3.io.in_uop.bits.prs2_busy, issue_slots[3].in_uop.bits.prs2_busy connect slots_3.io.in_uop.bits.prs1_busy, issue_slots[3].in_uop.bits.prs1_busy connect slots_3.io.in_uop.bits.ppred, issue_slots[3].in_uop.bits.ppred connect slots_3.io.in_uop.bits.prs3, issue_slots[3].in_uop.bits.prs3 connect slots_3.io.in_uop.bits.prs2, issue_slots[3].in_uop.bits.prs2 connect slots_3.io.in_uop.bits.prs1, issue_slots[3].in_uop.bits.prs1 connect slots_3.io.in_uop.bits.pdst, issue_slots[3].in_uop.bits.pdst connect slots_3.io.in_uop.bits.rxq_idx, issue_slots[3].in_uop.bits.rxq_idx connect slots_3.io.in_uop.bits.stq_idx, issue_slots[3].in_uop.bits.stq_idx connect slots_3.io.in_uop.bits.ldq_idx, issue_slots[3].in_uop.bits.ldq_idx connect slots_3.io.in_uop.bits.rob_idx, issue_slots[3].in_uop.bits.rob_idx connect slots_3.io.in_uop.bits.fp_ctrl.vec, issue_slots[3].in_uop.bits.fp_ctrl.vec connect slots_3.io.in_uop.bits.fp_ctrl.wflags, issue_slots[3].in_uop.bits.fp_ctrl.wflags connect slots_3.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[3].in_uop.bits.fp_ctrl.sqrt connect slots_3.io.in_uop.bits.fp_ctrl.div, issue_slots[3].in_uop.bits.fp_ctrl.div connect slots_3.io.in_uop.bits.fp_ctrl.fma, issue_slots[3].in_uop.bits.fp_ctrl.fma connect slots_3.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].in_uop.bits.fp_ctrl.fastpipe connect slots_3.io.in_uop.bits.fp_ctrl.toint, issue_slots[3].in_uop.bits.fp_ctrl.toint connect slots_3.io.in_uop.bits.fp_ctrl.fromint, issue_slots[3].in_uop.bits.fp_ctrl.fromint connect slots_3.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut connect slots_3.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn connect slots_3.io.in_uop.bits.fp_ctrl.swap23, issue_slots[3].in_uop.bits.fp_ctrl.swap23 connect slots_3.io.in_uop.bits.fp_ctrl.swap12, issue_slots[3].in_uop.bits.fp_ctrl.swap12 connect slots_3.io.in_uop.bits.fp_ctrl.ren3, issue_slots[3].in_uop.bits.fp_ctrl.ren3 connect slots_3.io.in_uop.bits.fp_ctrl.ren2, issue_slots[3].in_uop.bits.fp_ctrl.ren2 connect slots_3.io.in_uop.bits.fp_ctrl.ren1, issue_slots[3].in_uop.bits.fp_ctrl.ren1 connect slots_3.io.in_uop.bits.fp_ctrl.wen, issue_slots[3].in_uop.bits.fp_ctrl.wen connect slots_3.io.in_uop.bits.fp_ctrl.ldst, issue_slots[3].in_uop.bits.fp_ctrl.ldst connect slots_3.io.in_uop.bits.op2_sel, issue_slots[3].in_uop.bits.op2_sel connect slots_3.io.in_uop.bits.op1_sel, issue_slots[3].in_uop.bits.op1_sel connect slots_3.io.in_uop.bits.imm_packed, issue_slots[3].in_uop.bits.imm_packed connect slots_3.io.in_uop.bits.pimm, issue_slots[3].in_uop.bits.pimm connect slots_3.io.in_uop.bits.imm_sel, issue_slots[3].in_uop.bits.imm_sel connect slots_3.io.in_uop.bits.imm_rename, issue_slots[3].in_uop.bits.imm_rename connect slots_3.io.in_uop.bits.taken, issue_slots[3].in_uop.bits.taken connect slots_3.io.in_uop.bits.pc_lob, issue_slots[3].in_uop.bits.pc_lob connect slots_3.io.in_uop.bits.edge_inst, issue_slots[3].in_uop.bits.edge_inst connect slots_3.io.in_uop.bits.ftq_idx, issue_slots[3].in_uop.bits.ftq_idx connect slots_3.io.in_uop.bits.is_mov, issue_slots[3].in_uop.bits.is_mov connect slots_3.io.in_uop.bits.is_rocc, issue_slots[3].in_uop.bits.is_rocc connect slots_3.io.in_uop.bits.is_sys_pc2epc, issue_slots[3].in_uop.bits.is_sys_pc2epc connect slots_3.io.in_uop.bits.is_eret, issue_slots[3].in_uop.bits.is_eret connect slots_3.io.in_uop.bits.is_amo, issue_slots[3].in_uop.bits.is_amo connect slots_3.io.in_uop.bits.is_sfence, issue_slots[3].in_uop.bits.is_sfence connect slots_3.io.in_uop.bits.is_fencei, issue_slots[3].in_uop.bits.is_fencei connect slots_3.io.in_uop.bits.is_fence, issue_slots[3].in_uop.bits.is_fence connect slots_3.io.in_uop.bits.is_sfb, issue_slots[3].in_uop.bits.is_sfb connect slots_3.io.in_uop.bits.br_type, issue_slots[3].in_uop.bits.br_type connect slots_3.io.in_uop.bits.br_tag, issue_slots[3].in_uop.bits.br_tag connect slots_3.io.in_uop.bits.br_mask, issue_slots[3].in_uop.bits.br_mask connect slots_3.io.in_uop.bits.dis_col_sel, issue_slots[3].in_uop.bits.dis_col_sel connect slots_3.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[3].in_uop.bits.iw_p3_bypass_hint connect slots_3.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[3].in_uop.bits.iw_p2_bypass_hint connect slots_3.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[3].in_uop.bits.iw_p1_bypass_hint connect slots_3.io.in_uop.bits.iw_p2_speculative_child, issue_slots[3].in_uop.bits.iw_p2_speculative_child connect slots_3.io.in_uop.bits.iw_p1_speculative_child, issue_slots[3].in_uop.bits.iw_p1_speculative_child connect slots_3.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[3].in_uop.bits.iw_issued_partial_dgen connect slots_3.io.in_uop.bits.iw_issued_partial_agen, issue_slots[3].in_uop.bits.iw_issued_partial_agen connect slots_3.io.in_uop.bits.iw_issued, issue_slots[3].in_uop.bits.iw_issued connect slots_3.io.in_uop.bits.fu_code[0], issue_slots[3].in_uop.bits.fu_code[0] connect slots_3.io.in_uop.bits.fu_code[1], issue_slots[3].in_uop.bits.fu_code[1] connect slots_3.io.in_uop.bits.fu_code[2], issue_slots[3].in_uop.bits.fu_code[2] connect slots_3.io.in_uop.bits.fu_code[3], issue_slots[3].in_uop.bits.fu_code[3] connect slots_3.io.in_uop.bits.fu_code[4], issue_slots[3].in_uop.bits.fu_code[4] connect slots_3.io.in_uop.bits.fu_code[5], issue_slots[3].in_uop.bits.fu_code[5] connect slots_3.io.in_uop.bits.fu_code[6], issue_slots[3].in_uop.bits.fu_code[6] connect slots_3.io.in_uop.bits.fu_code[7], issue_slots[3].in_uop.bits.fu_code[7] connect slots_3.io.in_uop.bits.fu_code[8], issue_slots[3].in_uop.bits.fu_code[8] connect slots_3.io.in_uop.bits.fu_code[9], issue_slots[3].in_uop.bits.fu_code[9] connect slots_3.io.in_uop.bits.iq_type[0], issue_slots[3].in_uop.bits.iq_type[0] connect slots_3.io.in_uop.bits.iq_type[1], issue_slots[3].in_uop.bits.iq_type[1] connect slots_3.io.in_uop.bits.iq_type[2], issue_slots[3].in_uop.bits.iq_type[2] connect slots_3.io.in_uop.bits.iq_type[3], issue_slots[3].in_uop.bits.iq_type[3] connect slots_3.io.in_uop.bits.debug_pc, issue_slots[3].in_uop.bits.debug_pc connect slots_3.io.in_uop.bits.is_rvc, issue_slots[3].in_uop.bits.is_rvc connect slots_3.io.in_uop.bits.debug_inst, issue_slots[3].in_uop.bits.debug_inst connect slots_3.io.in_uop.bits.inst, issue_slots[3].in_uop.bits.inst connect slots_3.io.in_uop.valid, issue_slots[3].in_uop.valid connect issue_slots[3].iss_uop.debug_tsrc, slots_3.io.iss_uop.debug_tsrc connect issue_slots[3].iss_uop.debug_fsrc, slots_3.io.iss_uop.debug_fsrc connect issue_slots[3].iss_uop.bp_xcpt_if, slots_3.io.iss_uop.bp_xcpt_if connect issue_slots[3].iss_uop.bp_debug_if, slots_3.io.iss_uop.bp_debug_if connect issue_slots[3].iss_uop.xcpt_ma_if, slots_3.io.iss_uop.xcpt_ma_if connect issue_slots[3].iss_uop.xcpt_ae_if, slots_3.io.iss_uop.xcpt_ae_if connect issue_slots[3].iss_uop.xcpt_pf_if, slots_3.io.iss_uop.xcpt_pf_if connect issue_slots[3].iss_uop.fp_typ, slots_3.io.iss_uop.fp_typ connect issue_slots[3].iss_uop.fp_rm, slots_3.io.iss_uop.fp_rm connect issue_slots[3].iss_uop.fp_val, slots_3.io.iss_uop.fp_val connect issue_slots[3].iss_uop.fcn_op, slots_3.io.iss_uop.fcn_op connect issue_slots[3].iss_uop.fcn_dw, slots_3.io.iss_uop.fcn_dw connect issue_slots[3].iss_uop.frs3_en, slots_3.io.iss_uop.frs3_en connect issue_slots[3].iss_uop.lrs2_rtype, slots_3.io.iss_uop.lrs2_rtype connect issue_slots[3].iss_uop.lrs1_rtype, slots_3.io.iss_uop.lrs1_rtype connect issue_slots[3].iss_uop.dst_rtype, slots_3.io.iss_uop.dst_rtype connect issue_slots[3].iss_uop.lrs3, slots_3.io.iss_uop.lrs3 connect issue_slots[3].iss_uop.lrs2, slots_3.io.iss_uop.lrs2 connect issue_slots[3].iss_uop.lrs1, slots_3.io.iss_uop.lrs1 connect issue_slots[3].iss_uop.ldst, slots_3.io.iss_uop.ldst connect issue_slots[3].iss_uop.ldst_is_rs1, slots_3.io.iss_uop.ldst_is_rs1 connect issue_slots[3].iss_uop.csr_cmd, slots_3.io.iss_uop.csr_cmd connect issue_slots[3].iss_uop.flush_on_commit, slots_3.io.iss_uop.flush_on_commit connect issue_slots[3].iss_uop.is_unique, slots_3.io.iss_uop.is_unique connect issue_slots[3].iss_uop.uses_stq, slots_3.io.iss_uop.uses_stq connect issue_slots[3].iss_uop.uses_ldq, slots_3.io.iss_uop.uses_ldq connect issue_slots[3].iss_uop.mem_signed, slots_3.io.iss_uop.mem_signed connect issue_slots[3].iss_uop.mem_size, slots_3.io.iss_uop.mem_size connect issue_slots[3].iss_uop.mem_cmd, slots_3.io.iss_uop.mem_cmd connect issue_slots[3].iss_uop.exc_cause, slots_3.io.iss_uop.exc_cause connect issue_slots[3].iss_uop.exception, slots_3.io.iss_uop.exception connect issue_slots[3].iss_uop.stale_pdst, slots_3.io.iss_uop.stale_pdst connect issue_slots[3].iss_uop.ppred_busy, slots_3.io.iss_uop.ppred_busy connect issue_slots[3].iss_uop.prs3_busy, slots_3.io.iss_uop.prs3_busy connect issue_slots[3].iss_uop.prs2_busy, slots_3.io.iss_uop.prs2_busy connect issue_slots[3].iss_uop.prs1_busy, slots_3.io.iss_uop.prs1_busy connect issue_slots[3].iss_uop.ppred, slots_3.io.iss_uop.ppred connect issue_slots[3].iss_uop.prs3, slots_3.io.iss_uop.prs3 connect issue_slots[3].iss_uop.prs2, slots_3.io.iss_uop.prs2 connect issue_slots[3].iss_uop.prs1, slots_3.io.iss_uop.prs1 connect issue_slots[3].iss_uop.pdst, slots_3.io.iss_uop.pdst connect issue_slots[3].iss_uop.rxq_idx, slots_3.io.iss_uop.rxq_idx connect issue_slots[3].iss_uop.stq_idx, slots_3.io.iss_uop.stq_idx connect issue_slots[3].iss_uop.ldq_idx, slots_3.io.iss_uop.ldq_idx connect issue_slots[3].iss_uop.rob_idx, slots_3.io.iss_uop.rob_idx connect issue_slots[3].iss_uop.fp_ctrl.vec, slots_3.io.iss_uop.fp_ctrl.vec connect issue_slots[3].iss_uop.fp_ctrl.wflags, slots_3.io.iss_uop.fp_ctrl.wflags connect issue_slots[3].iss_uop.fp_ctrl.sqrt, slots_3.io.iss_uop.fp_ctrl.sqrt connect issue_slots[3].iss_uop.fp_ctrl.div, slots_3.io.iss_uop.fp_ctrl.div connect issue_slots[3].iss_uop.fp_ctrl.fma, slots_3.io.iss_uop.fp_ctrl.fma connect issue_slots[3].iss_uop.fp_ctrl.fastpipe, slots_3.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[3].iss_uop.fp_ctrl.toint, slots_3.io.iss_uop.fp_ctrl.toint connect issue_slots[3].iss_uop.fp_ctrl.fromint, slots_3.io.iss_uop.fp_ctrl.fromint connect issue_slots[3].iss_uop.fp_ctrl.typeTagOut, slots_3.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[3].iss_uop.fp_ctrl.typeTagIn, slots_3.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[3].iss_uop.fp_ctrl.swap23, slots_3.io.iss_uop.fp_ctrl.swap23 connect issue_slots[3].iss_uop.fp_ctrl.swap12, slots_3.io.iss_uop.fp_ctrl.swap12 connect issue_slots[3].iss_uop.fp_ctrl.ren3, slots_3.io.iss_uop.fp_ctrl.ren3 connect issue_slots[3].iss_uop.fp_ctrl.ren2, slots_3.io.iss_uop.fp_ctrl.ren2 connect issue_slots[3].iss_uop.fp_ctrl.ren1, slots_3.io.iss_uop.fp_ctrl.ren1 connect issue_slots[3].iss_uop.fp_ctrl.wen, slots_3.io.iss_uop.fp_ctrl.wen connect issue_slots[3].iss_uop.fp_ctrl.ldst, slots_3.io.iss_uop.fp_ctrl.ldst connect issue_slots[3].iss_uop.op2_sel, slots_3.io.iss_uop.op2_sel connect issue_slots[3].iss_uop.op1_sel, slots_3.io.iss_uop.op1_sel connect issue_slots[3].iss_uop.imm_packed, slots_3.io.iss_uop.imm_packed connect issue_slots[3].iss_uop.pimm, slots_3.io.iss_uop.pimm connect issue_slots[3].iss_uop.imm_sel, slots_3.io.iss_uop.imm_sel connect issue_slots[3].iss_uop.imm_rename, slots_3.io.iss_uop.imm_rename connect issue_slots[3].iss_uop.taken, slots_3.io.iss_uop.taken connect issue_slots[3].iss_uop.pc_lob, slots_3.io.iss_uop.pc_lob connect issue_slots[3].iss_uop.edge_inst, slots_3.io.iss_uop.edge_inst connect issue_slots[3].iss_uop.ftq_idx, slots_3.io.iss_uop.ftq_idx connect issue_slots[3].iss_uop.is_mov, slots_3.io.iss_uop.is_mov connect issue_slots[3].iss_uop.is_rocc, slots_3.io.iss_uop.is_rocc connect issue_slots[3].iss_uop.is_sys_pc2epc, slots_3.io.iss_uop.is_sys_pc2epc connect issue_slots[3].iss_uop.is_eret, slots_3.io.iss_uop.is_eret connect issue_slots[3].iss_uop.is_amo, slots_3.io.iss_uop.is_amo connect issue_slots[3].iss_uop.is_sfence, slots_3.io.iss_uop.is_sfence connect issue_slots[3].iss_uop.is_fencei, slots_3.io.iss_uop.is_fencei connect issue_slots[3].iss_uop.is_fence, slots_3.io.iss_uop.is_fence connect issue_slots[3].iss_uop.is_sfb, slots_3.io.iss_uop.is_sfb connect issue_slots[3].iss_uop.br_type, slots_3.io.iss_uop.br_type connect issue_slots[3].iss_uop.br_tag, slots_3.io.iss_uop.br_tag connect issue_slots[3].iss_uop.br_mask, slots_3.io.iss_uop.br_mask connect issue_slots[3].iss_uop.dis_col_sel, slots_3.io.iss_uop.dis_col_sel connect issue_slots[3].iss_uop.iw_p3_bypass_hint, slots_3.io.iss_uop.iw_p3_bypass_hint connect issue_slots[3].iss_uop.iw_p2_bypass_hint, slots_3.io.iss_uop.iw_p2_bypass_hint connect issue_slots[3].iss_uop.iw_p1_bypass_hint, slots_3.io.iss_uop.iw_p1_bypass_hint connect issue_slots[3].iss_uop.iw_p2_speculative_child, slots_3.io.iss_uop.iw_p2_speculative_child connect issue_slots[3].iss_uop.iw_p1_speculative_child, slots_3.io.iss_uop.iw_p1_speculative_child connect issue_slots[3].iss_uop.iw_issued_partial_dgen, slots_3.io.iss_uop.iw_issued_partial_dgen connect issue_slots[3].iss_uop.iw_issued_partial_agen, slots_3.io.iss_uop.iw_issued_partial_agen connect issue_slots[3].iss_uop.iw_issued, slots_3.io.iss_uop.iw_issued connect issue_slots[3].iss_uop.fu_code[0], slots_3.io.iss_uop.fu_code[0] connect issue_slots[3].iss_uop.fu_code[1], slots_3.io.iss_uop.fu_code[1] connect issue_slots[3].iss_uop.fu_code[2], slots_3.io.iss_uop.fu_code[2] connect issue_slots[3].iss_uop.fu_code[3], slots_3.io.iss_uop.fu_code[3] connect issue_slots[3].iss_uop.fu_code[4], slots_3.io.iss_uop.fu_code[4] connect issue_slots[3].iss_uop.fu_code[5], slots_3.io.iss_uop.fu_code[5] connect issue_slots[3].iss_uop.fu_code[6], slots_3.io.iss_uop.fu_code[6] connect issue_slots[3].iss_uop.fu_code[7], slots_3.io.iss_uop.fu_code[7] connect issue_slots[3].iss_uop.fu_code[8], slots_3.io.iss_uop.fu_code[8] connect issue_slots[3].iss_uop.fu_code[9], slots_3.io.iss_uop.fu_code[9] connect issue_slots[3].iss_uop.iq_type[0], slots_3.io.iss_uop.iq_type[0] connect issue_slots[3].iss_uop.iq_type[1], slots_3.io.iss_uop.iq_type[1] connect issue_slots[3].iss_uop.iq_type[2], slots_3.io.iss_uop.iq_type[2] connect issue_slots[3].iss_uop.iq_type[3], slots_3.io.iss_uop.iq_type[3] connect issue_slots[3].iss_uop.debug_pc, slots_3.io.iss_uop.debug_pc connect issue_slots[3].iss_uop.is_rvc, slots_3.io.iss_uop.is_rvc connect issue_slots[3].iss_uop.debug_inst, slots_3.io.iss_uop.debug_inst connect issue_slots[3].iss_uop.inst, slots_3.io.iss_uop.inst connect slots_3.io.grant, issue_slots[3].grant connect issue_slots[3].request, slots_3.io.request connect issue_slots[3].will_be_valid, slots_3.io.will_be_valid connect issue_slots[3].valid, slots_3.io.valid connect slots_4.io.child_rebusys, issue_slots[4].child_rebusys connect slots_4.io.pred_wakeup_port.bits, issue_slots[4].pred_wakeup_port.bits connect slots_4.io.pred_wakeup_port.valid, issue_slots[4].pred_wakeup_port.valid connect slots_4.io.wakeup_ports[0].bits.rebusy, issue_slots[4].wakeup_ports[0].bits.rebusy connect slots_4.io.wakeup_ports[0].bits.speculative_mask, issue_slots[4].wakeup_ports[0].bits.speculative_mask connect slots_4.io.wakeup_ports[0].bits.bypassable, issue_slots[4].wakeup_ports[0].bits.bypassable connect slots_4.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[0].bits.uop.debug_tsrc connect slots_4.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[0].bits.uop.debug_fsrc connect slots_4.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_4.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[0].bits.uop.bp_debug_if connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_4.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_4.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[4].wakeup_ports[0].bits.uop.fp_typ connect slots_4.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[4].wakeup_ports[0].bits.uop.fp_rm connect slots_4.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[4].wakeup_ports[0].bits.uop.fp_val connect slots_4.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[4].wakeup_ports[0].bits.uop.fcn_op connect slots_4.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[0].bits.uop.fcn_dw connect slots_4.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[4].wakeup_ports[0].bits.uop.frs3_en connect slots_4.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_4.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_4.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[0].bits.uop.dst_rtype connect slots_4.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[4].wakeup_ports[0].bits.uop.lrs3 connect slots_4.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[4].wakeup_ports[0].bits.uop.lrs2 connect slots_4.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[4].wakeup_ports[0].bits.uop.lrs1 connect slots_4.io.wakeup_ports[0].bits.uop.ldst, issue_slots[4].wakeup_ports[0].bits.uop.ldst connect slots_4.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_4.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[0].bits.uop.csr_cmd connect slots_4.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[0].bits.uop.flush_on_commit connect slots_4.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[4].wakeup_ports[0].bits.uop.is_unique connect slots_4.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[4].wakeup_ports[0].bits.uop.uses_stq connect slots_4.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[0].bits.uop.uses_ldq connect slots_4.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[4].wakeup_ports[0].bits.uop.mem_signed connect slots_4.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[4].wakeup_ports[0].bits.uop.mem_size connect slots_4.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[0].bits.uop.mem_cmd connect slots_4.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[4].wakeup_ports[0].bits.uop.exc_cause connect slots_4.io.wakeup_ports[0].bits.uop.exception, issue_slots[4].wakeup_ports[0].bits.uop.exception connect slots_4.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[0].bits.uop.stale_pdst connect slots_4.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[0].bits.uop.ppred_busy connect slots_4.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs3_busy connect slots_4.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs2_busy connect slots_4.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[0].bits.uop.prs1_busy connect slots_4.io.wakeup_ports[0].bits.uop.ppred, issue_slots[4].wakeup_ports[0].bits.uop.ppred connect slots_4.io.wakeup_ports[0].bits.uop.prs3, issue_slots[4].wakeup_ports[0].bits.uop.prs3 connect slots_4.io.wakeup_ports[0].bits.uop.prs2, issue_slots[4].wakeup_ports[0].bits.uop.prs2 connect slots_4.io.wakeup_ports[0].bits.uop.prs1, issue_slots[4].wakeup_ports[0].bits.uop.prs1 connect slots_4.io.wakeup_ports[0].bits.uop.pdst, issue_slots[4].wakeup_ports[0].bits.uop.pdst connect slots_4.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[0].bits.uop.rxq_idx connect slots_4.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[4].wakeup_ports[0].bits.uop.stq_idx connect slots_4.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[0].bits.uop.ldq_idx connect slots_4.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[4].wakeup_ports[0].bits.uop.rob_idx connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_4.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_4.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[4].wakeup_ports[0].bits.uop.op2_sel connect slots_4.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[4].wakeup_ports[0].bits.uop.op1_sel connect slots_4.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[4].wakeup_ports[0].bits.uop.imm_packed connect slots_4.io.wakeup_ports[0].bits.uop.pimm, issue_slots[4].wakeup_ports[0].bits.uop.pimm connect slots_4.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[4].wakeup_ports[0].bits.uop.imm_sel connect slots_4.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[4].wakeup_ports[0].bits.uop.imm_rename connect slots_4.io.wakeup_ports[0].bits.uop.taken, issue_slots[4].wakeup_ports[0].bits.uop.taken connect slots_4.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[4].wakeup_ports[0].bits.uop.pc_lob connect slots_4.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[4].wakeup_ports[0].bits.uop.edge_inst connect slots_4.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[0].bits.uop.ftq_idx connect slots_4.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[4].wakeup_ports[0].bits.uop.is_mov connect slots_4.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[4].wakeup_ports[0].bits.uop.is_rocc connect slots_4.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_4.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[4].wakeup_ports[0].bits.uop.is_eret connect slots_4.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[4].wakeup_ports[0].bits.uop.is_amo connect slots_4.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[4].wakeup_ports[0].bits.uop.is_sfence connect slots_4.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[4].wakeup_ports[0].bits.uop.is_fencei connect slots_4.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[4].wakeup_ports[0].bits.uop.is_fence connect slots_4.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[4].wakeup_ports[0].bits.uop.is_sfb connect slots_4.io.wakeup_ports[0].bits.uop.br_type, issue_slots[4].wakeup_ports[0].bits.uop.br_type connect slots_4.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[4].wakeup_ports[0].bits.uop.br_tag connect slots_4.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[4].wakeup_ports[0].bits.uop.br_mask connect slots_4.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[0].bits.uop.dis_col_sel connect slots_4.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_4.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_4.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_4.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_4.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_4.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[4].wakeup_ports[0].bits.uop.iw_issued connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[0] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[1] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[2] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[3] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[4] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[5] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[6] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[7] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[8] connect slots_4.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[0].bits.uop.fu_code[9] connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[0] connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[1] connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[2] connect slots_4.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[0].bits.uop.iq_type[3] connect slots_4.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[4].wakeup_ports[0].bits.uop.debug_pc connect slots_4.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[4].wakeup_ports[0].bits.uop.is_rvc connect slots_4.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[4].wakeup_ports[0].bits.uop.debug_inst connect slots_4.io.wakeup_ports[0].bits.uop.inst, issue_slots[4].wakeup_ports[0].bits.uop.inst connect slots_4.io.wakeup_ports[0].valid, issue_slots[4].wakeup_ports[0].valid connect slots_4.io.wakeup_ports[1].bits.rebusy, issue_slots[4].wakeup_ports[1].bits.rebusy connect slots_4.io.wakeup_ports[1].bits.speculative_mask, issue_slots[4].wakeup_ports[1].bits.speculative_mask connect slots_4.io.wakeup_ports[1].bits.bypassable, issue_slots[4].wakeup_ports[1].bits.bypassable connect slots_4.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[4].wakeup_ports[1].bits.uop.debug_tsrc connect slots_4.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[4].wakeup_ports[1].bits.uop.debug_fsrc connect slots_4.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[4].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_4.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[4].wakeup_ports[1].bits.uop.bp_debug_if connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_4.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[4].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_4.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[4].wakeup_ports[1].bits.uop.fp_typ connect slots_4.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[4].wakeup_ports[1].bits.uop.fp_rm connect slots_4.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[4].wakeup_ports[1].bits.uop.fp_val connect slots_4.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[4].wakeup_ports[1].bits.uop.fcn_op connect slots_4.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[4].wakeup_ports[1].bits.uop.fcn_dw connect slots_4.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[4].wakeup_ports[1].bits.uop.frs3_en connect slots_4.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[4].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_4.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[4].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_4.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[4].wakeup_ports[1].bits.uop.dst_rtype connect slots_4.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[4].wakeup_ports[1].bits.uop.lrs3 connect slots_4.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[4].wakeup_ports[1].bits.uop.lrs2 connect slots_4.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[4].wakeup_ports[1].bits.uop.lrs1 connect slots_4.io.wakeup_ports[1].bits.uop.ldst, issue_slots[4].wakeup_ports[1].bits.uop.ldst connect slots_4.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[4].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_4.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[4].wakeup_ports[1].bits.uop.csr_cmd connect slots_4.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[4].wakeup_ports[1].bits.uop.flush_on_commit connect slots_4.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[4].wakeup_ports[1].bits.uop.is_unique connect slots_4.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[4].wakeup_ports[1].bits.uop.uses_stq connect slots_4.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[4].wakeup_ports[1].bits.uop.uses_ldq connect slots_4.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[4].wakeup_ports[1].bits.uop.mem_signed connect slots_4.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[4].wakeup_ports[1].bits.uop.mem_size connect slots_4.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[4].wakeup_ports[1].bits.uop.mem_cmd connect slots_4.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[4].wakeup_ports[1].bits.uop.exc_cause connect slots_4.io.wakeup_ports[1].bits.uop.exception, issue_slots[4].wakeup_ports[1].bits.uop.exception connect slots_4.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[4].wakeup_ports[1].bits.uop.stale_pdst connect slots_4.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[4].wakeup_ports[1].bits.uop.ppred_busy connect slots_4.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs3_busy connect slots_4.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs2_busy connect slots_4.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[4].wakeup_ports[1].bits.uop.prs1_busy connect slots_4.io.wakeup_ports[1].bits.uop.ppred, issue_slots[4].wakeup_ports[1].bits.uop.ppred connect slots_4.io.wakeup_ports[1].bits.uop.prs3, issue_slots[4].wakeup_ports[1].bits.uop.prs3 connect slots_4.io.wakeup_ports[1].bits.uop.prs2, issue_slots[4].wakeup_ports[1].bits.uop.prs2 connect slots_4.io.wakeup_ports[1].bits.uop.prs1, issue_slots[4].wakeup_ports[1].bits.uop.prs1 connect slots_4.io.wakeup_ports[1].bits.uop.pdst, issue_slots[4].wakeup_ports[1].bits.uop.pdst connect slots_4.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[4].wakeup_ports[1].bits.uop.rxq_idx connect slots_4.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[4].wakeup_ports[1].bits.uop.stq_idx connect slots_4.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[4].wakeup_ports[1].bits.uop.ldq_idx connect slots_4.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[4].wakeup_ports[1].bits.uop.rob_idx connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_4.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_4.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[4].wakeup_ports[1].bits.uop.op2_sel connect slots_4.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[4].wakeup_ports[1].bits.uop.op1_sel connect slots_4.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[4].wakeup_ports[1].bits.uop.imm_packed connect slots_4.io.wakeup_ports[1].bits.uop.pimm, issue_slots[4].wakeup_ports[1].bits.uop.pimm connect slots_4.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[4].wakeup_ports[1].bits.uop.imm_sel connect slots_4.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[4].wakeup_ports[1].bits.uop.imm_rename connect slots_4.io.wakeup_ports[1].bits.uop.taken, issue_slots[4].wakeup_ports[1].bits.uop.taken connect slots_4.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[4].wakeup_ports[1].bits.uop.pc_lob connect slots_4.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[4].wakeup_ports[1].bits.uop.edge_inst connect slots_4.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[4].wakeup_ports[1].bits.uop.ftq_idx connect slots_4.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[4].wakeup_ports[1].bits.uop.is_mov connect slots_4.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[4].wakeup_ports[1].bits.uop.is_rocc connect slots_4.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[4].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_4.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[4].wakeup_ports[1].bits.uop.is_eret connect slots_4.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[4].wakeup_ports[1].bits.uop.is_amo connect slots_4.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[4].wakeup_ports[1].bits.uop.is_sfence connect slots_4.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[4].wakeup_ports[1].bits.uop.is_fencei connect slots_4.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[4].wakeup_ports[1].bits.uop.is_fence connect slots_4.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[4].wakeup_ports[1].bits.uop.is_sfb connect slots_4.io.wakeup_ports[1].bits.uop.br_type, issue_slots[4].wakeup_ports[1].bits.uop.br_type connect slots_4.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[4].wakeup_ports[1].bits.uop.br_tag connect slots_4.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[4].wakeup_ports[1].bits.uop.br_mask connect slots_4.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[4].wakeup_ports[1].bits.uop.dis_col_sel connect slots_4.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_4.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_4.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_4.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_4.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_4.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[4].wakeup_ports[1].bits.uop.iw_issued connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[0] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[1] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[2] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[3] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[4] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[5] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[6] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[7] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[8] connect slots_4.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[4].wakeup_ports[1].bits.uop.fu_code[9] connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[0] connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[1] connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[2] connect slots_4.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[4].wakeup_ports[1].bits.uop.iq_type[3] connect slots_4.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[4].wakeup_ports[1].bits.uop.debug_pc connect slots_4.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[4].wakeup_ports[1].bits.uop.is_rvc connect slots_4.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[4].wakeup_ports[1].bits.uop.debug_inst connect slots_4.io.wakeup_ports[1].bits.uop.inst, issue_slots[4].wakeup_ports[1].bits.uop.inst connect slots_4.io.wakeup_ports[1].valid, issue_slots[4].wakeup_ports[1].valid connect slots_4.io.squash_grant, issue_slots[4].squash_grant connect slots_4.io.clear, issue_slots[4].clear connect slots_4.io.kill, issue_slots[4].kill connect slots_4.io.brupdate.b2.target_offset, issue_slots[4].brupdate.b2.target_offset connect slots_4.io.brupdate.b2.jalr_target, issue_slots[4].brupdate.b2.jalr_target connect slots_4.io.brupdate.b2.pc_sel, issue_slots[4].brupdate.b2.pc_sel connect slots_4.io.brupdate.b2.cfi_type, issue_slots[4].brupdate.b2.cfi_type connect slots_4.io.brupdate.b2.taken, issue_slots[4].brupdate.b2.taken connect slots_4.io.brupdate.b2.mispredict, issue_slots[4].brupdate.b2.mispredict connect slots_4.io.brupdate.b2.uop.debug_tsrc, issue_slots[4].brupdate.b2.uop.debug_tsrc connect slots_4.io.brupdate.b2.uop.debug_fsrc, issue_slots[4].brupdate.b2.uop.debug_fsrc connect slots_4.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[4].brupdate.b2.uop.bp_xcpt_if connect slots_4.io.brupdate.b2.uop.bp_debug_if, issue_slots[4].brupdate.b2.uop.bp_debug_if connect slots_4.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[4].brupdate.b2.uop.xcpt_ma_if connect slots_4.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[4].brupdate.b2.uop.xcpt_ae_if connect slots_4.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[4].brupdate.b2.uop.xcpt_pf_if connect slots_4.io.brupdate.b2.uop.fp_typ, issue_slots[4].brupdate.b2.uop.fp_typ connect slots_4.io.brupdate.b2.uop.fp_rm, issue_slots[4].brupdate.b2.uop.fp_rm connect slots_4.io.brupdate.b2.uop.fp_val, issue_slots[4].brupdate.b2.uop.fp_val connect slots_4.io.brupdate.b2.uop.fcn_op, issue_slots[4].brupdate.b2.uop.fcn_op connect slots_4.io.brupdate.b2.uop.fcn_dw, issue_slots[4].brupdate.b2.uop.fcn_dw connect slots_4.io.brupdate.b2.uop.frs3_en, issue_slots[4].brupdate.b2.uop.frs3_en connect slots_4.io.brupdate.b2.uop.lrs2_rtype, issue_slots[4].brupdate.b2.uop.lrs2_rtype connect slots_4.io.brupdate.b2.uop.lrs1_rtype, issue_slots[4].brupdate.b2.uop.lrs1_rtype connect slots_4.io.brupdate.b2.uop.dst_rtype, issue_slots[4].brupdate.b2.uop.dst_rtype connect slots_4.io.brupdate.b2.uop.lrs3, issue_slots[4].brupdate.b2.uop.lrs3 connect slots_4.io.brupdate.b2.uop.lrs2, issue_slots[4].brupdate.b2.uop.lrs2 connect slots_4.io.brupdate.b2.uop.lrs1, issue_slots[4].brupdate.b2.uop.lrs1 connect slots_4.io.brupdate.b2.uop.ldst, issue_slots[4].brupdate.b2.uop.ldst connect slots_4.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[4].brupdate.b2.uop.ldst_is_rs1 connect slots_4.io.brupdate.b2.uop.csr_cmd, issue_slots[4].brupdate.b2.uop.csr_cmd connect slots_4.io.brupdate.b2.uop.flush_on_commit, issue_slots[4].brupdate.b2.uop.flush_on_commit connect slots_4.io.brupdate.b2.uop.is_unique, issue_slots[4].brupdate.b2.uop.is_unique connect slots_4.io.brupdate.b2.uop.uses_stq, issue_slots[4].brupdate.b2.uop.uses_stq connect slots_4.io.brupdate.b2.uop.uses_ldq, issue_slots[4].brupdate.b2.uop.uses_ldq connect slots_4.io.brupdate.b2.uop.mem_signed, issue_slots[4].brupdate.b2.uop.mem_signed connect slots_4.io.brupdate.b2.uop.mem_size, issue_slots[4].brupdate.b2.uop.mem_size connect slots_4.io.brupdate.b2.uop.mem_cmd, issue_slots[4].brupdate.b2.uop.mem_cmd connect slots_4.io.brupdate.b2.uop.exc_cause, issue_slots[4].brupdate.b2.uop.exc_cause connect slots_4.io.brupdate.b2.uop.exception, issue_slots[4].brupdate.b2.uop.exception connect slots_4.io.brupdate.b2.uop.stale_pdst, issue_slots[4].brupdate.b2.uop.stale_pdst connect slots_4.io.brupdate.b2.uop.ppred_busy, issue_slots[4].brupdate.b2.uop.ppred_busy connect slots_4.io.brupdate.b2.uop.prs3_busy, issue_slots[4].brupdate.b2.uop.prs3_busy connect slots_4.io.brupdate.b2.uop.prs2_busy, issue_slots[4].brupdate.b2.uop.prs2_busy connect slots_4.io.brupdate.b2.uop.prs1_busy, issue_slots[4].brupdate.b2.uop.prs1_busy connect slots_4.io.brupdate.b2.uop.ppred, issue_slots[4].brupdate.b2.uop.ppred connect slots_4.io.brupdate.b2.uop.prs3, issue_slots[4].brupdate.b2.uop.prs3 connect slots_4.io.brupdate.b2.uop.prs2, issue_slots[4].brupdate.b2.uop.prs2 connect slots_4.io.brupdate.b2.uop.prs1, issue_slots[4].brupdate.b2.uop.prs1 connect slots_4.io.brupdate.b2.uop.pdst, issue_slots[4].brupdate.b2.uop.pdst connect slots_4.io.brupdate.b2.uop.rxq_idx, issue_slots[4].brupdate.b2.uop.rxq_idx connect slots_4.io.brupdate.b2.uop.stq_idx, issue_slots[4].brupdate.b2.uop.stq_idx connect slots_4.io.brupdate.b2.uop.ldq_idx, issue_slots[4].brupdate.b2.uop.ldq_idx connect slots_4.io.brupdate.b2.uop.rob_idx, issue_slots[4].brupdate.b2.uop.rob_idx connect slots_4.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[4].brupdate.b2.uop.fp_ctrl.vec connect slots_4.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[4].brupdate.b2.uop.fp_ctrl.wflags connect slots_4.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[4].brupdate.b2.uop.fp_ctrl.sqrt connect slots_4.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[4].brupdate.b2.uop.fp_ctrl.div connect slots_4.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[4].brupdate.b2.uop.fp_ctrl.fma connect slots_4.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[4].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_4.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[4].brupdate.b2.uop.fp_ctrl.toint connect slots_4.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[4].brupdate.b2.uop.fp_ctrl.fromint connect slots_4.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_4.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_4.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[4].brupdate.b2.uop.fp_ctrl.swap23 connect slots_4.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[4].brupdate.b2.uop.fp_ctrl.swap12 connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren3 connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren2 connect slots_4.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[4].brupdate.b2.uop.fp_ctrl.ren1 connect slots_4.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[4].brupdate.b2.uop.fp_ctrl.wen connect slots_4.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[4].brupdate.b2.uop.fp_ctrl.ldst connect slots_4.io.brupdate.b2.uop.op2_sel, issue_slots[4].brupdate.b2.uop.op2_sel connect slots_4.io.brupdate.b2.uop.op1_sel, issue_slots[4].brupdate.b2.uop.op1_sel connect slots_4.io.brupdate.b2.uop.imm_packed, issue_slots[4].brupdate.b2.uop.imm_packed connect slots_4.io.brupdate.b2.uop.pimm, issue_slots[4].brupdate.b2.uop.pimm connect slots_4.io.brupdate.b2.uop.imm_sel, issue_slots[4].brupdate.b2.uop.imm_sel connect slots_4.io.brupdate.b2.uop.imm_rename, issue_slots[4].brupdate.b2.uop.imm_rename connect slots_4.io.brupdate.b2.uop.taken, issue_slots[4].brupdate.b2.uop.taken connect slots_4.io.brupdate.b2.uop.pc_lob, issue_slots[4].brupdate.b2.uop.pc_lob connect slots_4.io.brupdate.b2.uop.edge_inst, issue_slots[4].brupdate.b2.uop.edge_inst connect slots_4.io.brupdate.b2.uop.ftq_idx, issue_slots[4].brupdate.b2.uop.ftq_idx connect slots_4.io.brupdate.b2.uop.is_mov, issue_slots[4].brupdate.b2.uop.is_mov connect slots_4.io.brupdate.b2.uop.is_rocc, issue_slots[4].brupdate.b2.uop.is_rocc connect slots_4.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[4].brupdate.b2.uop.is_sys_pc2epc connect slots_4.io.brupdate.b2.uop.is_eret, issue_slots[4].brupdate.b2.uop.is_eret connect slots_4.io.brupdate.b2.uop.is_amo, issue_slots[4].brupdate.b2.uop.is_amo connect slots_4.io.brupdate.b2.uop.is_sfence, issue_slots[4].brupdate.b2.uop.is_sfence connect slots_4.io.brupdate.b2.uop.is_fencei, issue_slots[4].brupdate.b2.uop.is_fencei connect slots_4.io.brupdate.b2.uop.is_fence, issue_slots[4].brupdate.b2.uop.is_fence connect slots_4.io.brupdate.b2.uop.is_sfb, issue_slots[4].brupdate.b2.uop.is_sfb connect slots_4.io.brupdate.b2.uop.br_type, issue_slots[4].brupdate.b2.uop.br_type connect slots_4.io.brupdate.b2.uop.br_tag, issue_slots[4].brupdate.b2.uop.br_tag connect slots_4.io.brupdate.b2.uop.br_mask, issue_slots[4].brupdate.b2.uop.br_mask connect slots_4.io.brupdate.b2.uop.dis_col_sel, issue_slots[4].brupdate.b2.uop.dis_col_sel connect slots_4.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p3_bypass_hint connect slots_4.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p2_bypass_hint connect slots_4.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[4].brupdate.b2.uop.iw_p1_bypass_hint connect slots_4.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[4].brupdate.b2.uop.iw_p2_speculative_child connect slots_4.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[4].brupdate.b2.uop.iw_p1_speculative_child connect slots_4.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[4].brupdate.b2.uop.iw_issued_partial_dgen connect slots_4.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[4].brupdate.b2.uop.iw_issued_partial_agen connect slots_4.io.brupdate.b2.uop.iw_issued, issue_slots[4].brupdate.b2.uop.iw_issued connect slots_4.io.brupdate.b2.uop.fu_code[0], issue_slots[4].brupdate.b2.uop.fu_code[0] connect slots_4.io.brupdate.b2.uop.fu_code[1], issue_slots[4].brupdate.b2.uop.fu_code[1] connect slots_4.io.brupdate.b2.uop.fu_code[2], issue_slots[4].brupdate.b2.uop.fu_code[2] connect slots_4.io.brupdate.b2.uop.fu_code[3], issue_slots[4].brupdate.b2.uop.fu_code[3] connect slots_4.io.brupdate.b2.uop.fu_code[4], issue_slots[4].brupdate.b2.uop.fu_code[4] connect slots_4.io.brupdate.b2.uop.fu_code[5], issue_slots[4].brupdate.b2.uop.fu_code[5] connect slots_4.io.brupdate.b2.uop.fu_code[6], issue_slots[4].brupdate.b2.uop.fu_code[6] connect slots_4.io.brupdate.b2.uop.fu_code[7], issue_slots[4].brupdate.b2.uop.fu_code[7] connect slots_4.io.brupdate.b2.uop.fu_code[8], issue_slots[4].brupdate.b2.uop.fu_code[8] connect slots_4.io.brupdate.b2.uop.fu_code[9], issue_slots[4].brupdate.b2.uop.fu_code[9] connect slots_4.io.brupdate.b2.uop.iq_type[0], issue_slots[4].brupdate.b2.uop.iq_type[0] connect slots_4.io.brupdate.b2.uop.iq_type[1], issue_slots[4].brupdate.b2.uop.iq_type[1] connect slots_4.io.brupdate.b2.uop.iq_type[2], issue_slots[4].brupdate.b2.uop.iq_type[2] connect slots_4.io.brupdate.b2.uop.iq_type[3], issue_slots[4].brupdate.b2.uop.iq_type[3] connect slots_4.io.brupdate.b2.uop.debug_pc, issue_slots[4].brupdate.b2.uop.debug_pc connect slots_4.io.brupdate.b2.uop.is_rvc, issue_slots[4].brupdate.b2.uop.is_rvc connect slots_4.io.brupdate.b2.uop.debug_inst, issue_slots[4].brupdate.b2.uop.debug_inst connect slots_4.io.brupdate.b2.uop.inst, issue_slots[4].brupdate.b2.uop.inst connect slots_4.io.brupdate.b1.mispredict_mask, issue_slots[4].brupdate.b1.mispredict_mask connect slots_4.io.brupdate.b1.resolve_mask, issue_slots[4].brupdate.b1.resolve_mask connect issue_slots[4].out_uop.debug_tsrc, slots_4.io.out_uop.debug_tsrc connect issue_slots[4].out_uop.debug_fsrc, slots_4.io.out_uop.debug_fsrc connect issue_slots[4].out_uop.bp_xcpt_if, slots_4.io.out_uop.bp_xcpt_if connect issue_slots[4].out_uop.bp_debug_if, slots_4.io.out_uop.bp_debug_if connect issue_slots[4].out_uop.xcpt_ma_if, slots_4.io.out_uop.xcpt_ma_if connect issue_slots[4].out_uop.xcpt_ae_if, slots_4.io.out_uop.xcpt_ae_if connect issue_slots[4].out_uop.xcpt_pf_if, slots_4.io.out_uop.xcpt_pf_if connect issue_slots[4].out_uop.fp_typ, slots_4.io.out_uop.fp_typ connect issue_slots[4].out_uop.fp_rm, slots_4.io.out_uop.fp_rm connect issue_slots[4].out_uop.fp_val, slots_4.io.out_uop.fp_val connect issue_slots[4].out_uop.fcn_op, slots_4.io.out_uop.fcn_op connect issue_slots[4].out_uop.fcn_dw, slots_4.io.out_uop.fcn_dw connect issue_slots[4].out_uop.frs3_en, slots_4.io.out_uop.frs3_en connect issue_slots[4].out_uop.lrs2_rtype, slots_4.io.out_uop.lrs2_rtype connect issue_slots[4].out_uop.lrs1_rtype, slots_4.io.out_uop.lrs1_rtype connect issue_slots[4].out_uop.dst_rtype, slots_4.io.out_uop.dst_rtype connect issue_slots[4].out_uop.lrs3, slots_4.io.out_uop.lrs3 connect issue_slots[4].out_uop.lrs2, slots_4.io.out_uop.lrs2 connect issue_slots[4].out_uop.lrs1, slots_4.io.out_uop.lrs1 connect issue_slots[4].out_uop.ldst, slots_4.io.out_uop.ldst connect issue_slots[4].out_uop.ldst_is_rs1, slots_4.io.out_uop.ldst_is_rs1 connect issue_slots[4].out_uop.csr_cmd, slots_4.io.out_uop.csr_cmd connect issue_slots[4].out_uop.flush_on_commit, slots_4.io.out_uop.flush_on_commit connect issue_slots[4].out_uop.is_unique, slots_4.io.out_uop.is_unique connect issue_slots[4].out_uop.uses_stq, slots_4.io.out_uop.uses_stq connect issue_slots[4].out_uop.uses_ldq, slots_4.io.out_uop.uses_ldq connect issue_slots[4].out_uop.mem_signed, slots_4.io.out_uop.mem_signed connect issue_slots[4].out_uop.mem_size, slots_4.io.out_uop.mem_size connect issue_slots[4].out_uop.mem_cmd, slots_4.io.out_uop.mem_cmd connect issue_slots[4].out_uop.exc_cause, slots_4.io.out_uop.exc_cause connect issue_slots[4].out_uop.exception, slots_4.io.out_uop.exception connect issue_slots[4].out_uop.stale_pdst, slots_4.io.out_uop.stale_pdst connect issue_slots[4].out_uop.ppred_busy, slots_4.io.out_uop.ppred_busy connect issue_slots[4].out_uop.prs3_busy, slots_4.io.out_uop.prs3_busy connect issue_slots[4].out_uop.prs2_busy, slots_4.io.out_uop.prs2_busy connect issue_slots[4].out_uop.prs1_busy, slots_4.io.out_uop.prs1_busy connect issue_slots[4].out_uop.ppred, slots_4.io.out_uop.ppred connect issue_slots[4].out_uop.prs3, slots_4.io.out_uop.prs3 connect issue_slots[4].out_uop.prs2, slots_4.io.out_uop.prs2 connect issue_slots[4].out_uop.prs1, slots_4.io.out_uop.prs1 connect issue_slots[4].out_uop.pdst, slots_4.io.out_uop.pdst connect issue_slots[4].out_uop.rxq_idx, slots_4.io.out_uop.rxq_idx connect issue_slots[4].out_uop.stq_idx, slots_4.io.out_uop.stq_idx connect issue_slots[4].out_uop.ldq_idx, slots_4.io.out_uop.ldq_idx connect issue_slots[4].out_uop.rob_idx, slots_4.io.out_uop.rob_idx connect issue_slots[4].out_uop.fp_ctrl.vec, slots_4.io.out_uop.fp_ctrl.vec connect issue_slots[4].out_uop.fp_ctrl.wflags, slots_4.io.out_uop.fp_ctrl.wflags connect issue_slots[4].out_uop.fp_ctrl.sqrt, slots_4.io.out_uop.fp_ctrl.sqrt connect issue_slots[4].out_uop.fp_ctrl.div, slots_4.io.out_uop.fp_ctrl.div connect issue_slots[4].out_uop.fp_ctrl.fma, slots_4.io.out_uop.fp_ctrl.fma connect issue_slots[4].out_uop.fp_ctrl.fastpipe, slots_4.io.out_uop.fp_ctrl.fastpipe connect issue_slots[4].out_uop.fp_ctrl.toint, slots_4.io.out_uop.fp_ctrl.toint connect issue_slots[4].out_uop.fp_ctrl.fromint, slots_4.io.out_uop.fp_ctrl.fromint connect issue_slots[4].out_uop.fp_ctrl.typeTagOut, slots_4.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[4].out_uop.fp_ctrl.typeTagIn, slots_4.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[4].out_uop.fp_ctrl.swap23, slots_4.io.out_uop.fp_ctrl.swap23 connect issue_slots[4].out_uop.fp_ctrl.swap12, slots_4.io.out_uop.fp_ctrl.swap12 connect issue_slots[4].out_uop.fp_ctrl.ren3, slots_4.io.out_uop.fp_ctrl.ren3 connect issue_slots[4].out_uop.fp_ctrl.ren2, slots_4.io.out_uop.fp_ctrl.ren2 connect issue_slots[4].out_uop.fp_ctrl.ren1, slots_4.io.out_uop.fp_ctrl.ren1 connect issue_slots[4].out_uop.fp_ctrl.wen, slots_4.io.out_uop.fp_ctrl.wen connect issue_slots[4].out_uop.fp_ctrl.ldst, slots_4.io.out_uop.fp_ctrl.ldst connect issue_slots[4].out_uop.op2_sel, slots_4.io.out_uop.op2_sel connect issue_slots[4].out_uop.op1_sel, slots_4.io.out_uop.op1_sel connect issue_slots[4].out_uop.imm_packed, slots_4.io.out_uop.imm_packed connect issue_slots[4].out_uop.pimm, slots_4.io.out_uop.pimm connect issue_slots[4].out_uop.imm_sel, slots_4.io.out_uop.imm_sel connect issue_slots[4].out_uop.imm_rename, slots_4.io.out_uop.imm_rename connect issue_slots[4].out_uop.taken, slots_4.io.out_uop.taken connect issue_slots[4].out_uop.pc_lob, slots_4.io.out_uop.pc_lob connect issue_slots[4].out_uop.edge_inst, slots_4.io.out_uop.edge_inst connect issue_slots[4].out_uop.ftq_idx, slots_4.io.out_uop.ftq_idx connect issue_slots[4].out_uop.is_mov, slots_4.io.out_uop.is_mov connect issue_slots[4].out_uop.is_rocc, slots_4.io.out_uop.is_rocc connect issue_slots[4].out_uop.is_sys_pc2epc, slots_4.io.out_uop.is_sys_pc2epc connect issue_slots[4].out_uop.is_eret, slots_4.io.out_uop.is_eret connect issue_slots[4].out_uop.is_amo, slots_4.io.out_uop.is_amo connect issue_slots[4].out_uop.is_sfence, slots_4.io.out_uop.is_sfence connect issue_slots[4].out_uop.is_fencei, slots_4.io.out_uop.is_fencei connect issue_slots[4].out_uop.is_fence, slots_4.io.out_uop.is_fence connect issue_slots[4].out_uop.is_sfb, slots_4.io.out_uop.is_sfb connect issue_slots[4].out_uop.br_type, slots_4.io.out_uop.br_type connect issue_slots[4].out_uop.br_tag, slots_4.io.out_uop.br_tag connect issue_slots[4].out_uop.br_mask, slots_4.io.out_uop.br_mask connect issue_slots[4].out_uop.dis_col_sel, slots_4.io.out_uop.dis_col_sel connect issue_slots[4].out_uop.iw_p3_bypass_hint, slots_4.io.out_uop.iw_p3_bypass_hint connect issue_slots[4].out_uop.iw_p2_bypass_hint, slots_4.io.out_uop.iw_p2_bypass_hint connect issue_slots[4].out_uop.iw_p1_bypass_hint, slots_4.io.out_uop.iw_p1_bypass_hint connect issue_slots[4].out_uop.iw_p2_speculative_child, slots_4.io.out_uop.iw_p2_speculative_child connect issue_slots[4].out_uop.iw_p1_speculative_child, slots_4.io.out_uop.iw_p1_speculative_child connect issue_slots[4].out_uop.iw_issued_partial_dgen, slots_4.io.out_uop.iw_issued_partial_dgen connect issue_slots[4].out_uop.iw_issued_partial_agen, slots_4.io.out_uop.iw_issued_partial_agen connect issue_slots[4].out_uop.iw_issued, slots_4.io.out_uop.iw_issued connect issue_slots[4].out_uop.fu_code[0], slots_4.io.out_uop.fu_code[0] connect issue_slots[4].out_uop.fu_code[1], slots_4.io.out_uop.fu_code[1] connect issue_slots[4].out_uop.fu_code[2], slots_4.io.out_uop.fu_code[2] connect issue_slots[4].out_uop.fu_code[3], slots_4.io.out_uop.fu_code[3] connect issue_slots[4].out_uop.fu_code[4], slots_4.io.out_uop.fu_code[4] connect issue_slots[4].out_uop.fu_code[5], slots_4.io.out_uop.fu_code[5] connect issue_slots[4].out_uop.fu_code[6], slots_4.io.out_uop.fu_code[6] connect issue_slots[4].out_uop.fu_code[7], slots_4.io.out_uop.fu_code[7] connect issue_slots[4].out_uop.fu_code[8], slots_4.io.out_uop.fu_code[8] connect issue_slots[4].out_uop.fu_code[9], slots_4.io.out_uop.fu_code[9] connect issue_slots[4].out_uop.iq_type[0], slots_4.io.out_uop.iq_type[0] connect issue_slots[4].out_uop.iq_type[1], slots_4.io.out_uop.iq_type[1] connect issue_slots[4].out_uop.iq_type[2], slots_4.io.out_uop.iq_type[2] connect issue_slots[4].out_uop.iq_type[3], slots_4.io.out_uop.iq_type[3] connect issue_slots[4].out_uop.debug_pc, slots_4.io.out_uop.debug_pc connect issue_slots[4].out_uop.is_rvc, slots_4.io.out_uop.is_rvc connect issue_slots[4].out_uop.debug_inst, slots_4.io.out_uop.debug_inst connect issue_slots[4].out_uop.inst, slots_4.io.out_uop.inst connect slots_4.io.in_uop.bits.debug_tsrc, issue_slots[4].in_uop.bits.debug_tsrc connect slots_4.io.in_uop.bits.debug_fsrc, issue_slots[4].in_uop.bits.debug_fsrc connect slots_4.io.in_uop.bits.bp_xcpt_if, issue_slots[4].in_uop.bits.bp_xcpt_if connect slots_4.io.in_uop.bits.bp_debug_if, issue_slots[4].in_uop.bits.bp_debug_if connect slots_4.io.in_uop.bits.xcpt_ma_if, issue_slots[4].in_uop.bits.xcpt_ma_if connect slots_4.io.in_uop.bits.xcpt_ae_if, issue_slots[4].in_uop.bits.xcpt_ae_if connect slots_4.io.in_uop.bits.xcpt_pf_if, issue_slots[4].in_uop.bits.xcpt_pf_if connect slots_4.io.in_uop.bits.fp_typ, issue_slots[4].in_uop.bits.fp_typ connect slots_4.io.in_uop.bits.fp_rm, issue_slots[4].in_uop.bits.fp_rm connect slots_4.io.in_uop.bits.fp_val, issue_slots[4].in_uop.bits.fp_val connect slots_4.io.in_uop.bits.fcn_op, issue_slots[4].in_uop.bits.fcn_op connect slots_4.io.in_uop.bits.fcn_dw, issue_slots[4].in_uop.bits.fcn_dw connect slots_4.io.in_uop.bits.frs3_en, issue_slots[4].in_uop.bits.frs3_en connect slots_4.io.in_uop.bits.lrs2_rtype, issue_slots[4].in_uop.bits.lrs2_rtype connect slots_4.io.in_uop.bits.lrs1_rtype, issue_slots[4].in_uop.bits.lrs1_rtype connect slots_4.io.in_uop.bits.dst_rtype, issue_slots[4].in_uop.bits.dst_rtype connect slots_4.io.in_uop.bits.lrs3, issue_slots[4].in_uop.bits.lrs3 connect slots_4.io.in_uop.bits.lrs2, issue_slots[4].in_uop.bits.lrs2 connect slots_4.io.in_uop.bits.lrs1, issue_slots[4].in_uop.bits.lrs1 connect slots_4.io.in_uop.bits.ldst, issue_slots[4].in_uop.bits.ldst connect slots_4.io.in_uop.bits.ldst_is_rs1, issue_slots[4].in_uop.bits.ldst_is_rs1 connect slots_4.io.in_uop.bits.csr_cmd, issue_slots[4].in_uop.bits.csr_cmd connect slots_4.io.in_uop.bits.flush_on_commit, issue_slots[4].in_uop.bits.flush_on_commit connect slots_4.io.in_uop.bits.is_unique, issue_slots[4].in_uop.bits.is_unique connect slots_4.io.in_uop.bits.uses_stq, issue_slots[4].in_uop.bits.uses_stq connect slots_4.io.in_uop.bits.uses_ldq, issue_slots[4].in_uop.bits.uses_ldq connect slots_4.io.in_uop.bits.mem_signed, issue_slots[4].in_uop.bits.mem_signed connect slots_4.io.in_uop.bits.mem_size, issue_slots[4].in_uop.bits.mem_size connect slots_4.io.in_uop.bits.mem_cmd, issue_slots[4].in_uop.bits.mem_cmd connect slots_4.io.in_uop.bits.exc_cause, issue_slots[4].in_uop.bits.exc_cause connect slots_4.io.in_uop.bits.exception, issue_slots[4].in_uop.bits.exception connect slots_4.io.in_uop.bits.stale_pdst, issue_slots[4].in_uop.bits.stale_pdst connect slots_4.io.in_uop.bits.ppred_busy, issue_slots[4].in_uop.bits.ppred_busy connect slots_4.io.in_uop.bits.prs3_busy, issue_slots[4].in_uop.bits.prs3_busy connect slots_4.io.in_uop.bits.prs2_busy, issue_slots[4].in_uop.bits.prs2_busy connect slots_4.io.in_uop.bits.prs1_busy, issue_slots[4].in_uop.bits.prs1_busy connect slots_4.io.in_uop.bits.ppred, issue_slots[4].in_uop.bits.ppred connect slots_4.io.in_uop.bits.prs3, issue_slots[4].in_uop.bits.prs3 connect slots_4.io.in_uop.bits.prs2, issue_slots[4].in_uop.bits.prs2 connect slots_4.io.in_uop.bits.prs1, issue_slots[4].in_uop.bits.prs1 connect slots_4.io.in_uop.bits.pdst, issue_slots[4].in_uop.bits.pdst connect slots_4.io.in_uop.bits.rxq_idx, issue_slots[4].in_uop.bits.rxq_idx connect slots_4.io.in_uop.bits.stq_idx, issue_slots[4].in_uop.bits.stq_idx connect slots_4.io.in_uop.bits.ldq_idx, issue_slots[4].in_uop.bits.ldq_idx connect slots_4.io.in_uop.bits.rob_idx, issue_slots[4].in_uop.bits.rob_idx connect slots_4.io.in_uop.bits.fp_ctrl.vec, issue_slots[4].in_uop.bits.fp_ctrl.vec connect slots_4.io.in_uop.bits.fp_ctrl.wflags, issue_slots[4].in_uop.bits.fp_ctrl.wflags connect slots_4.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[4].in_uop.bits.fp_ctrl.sqrt connect slots_4.io.in_uop.bits.fp_ctrl.div, issue_slots[4].in_uop.bits.fp_ctrl.div connect slots_4.io.in_uop.bits.fp_ctrl.fma, issue_slots[4].in_uop.bits.fp_ctrl.fma connect slots_4.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].in_uop.bits.fp_ctrl.fastpipe connect slots_4.io.in_uop.bits.fp_ctrl.toint, issue_slots[4].in_uop.bits.fp_ctrl.toint connect slots_4.io.in_uop.bits.fp_ctrl.fromint, issue_slots[4].in_uop.bits.fp_ctrl.fromint connect slots_4.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut connect slots_4.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn connect slots_4.io.in_uop.bits.fp_ctrl.swap23, issue_slots[4].in_uop.bits.fp_ctrl.swap23 connect slots_4.io.in_uop.bits.fp_ctrl.swap12, issue_slots[4].in_uop.bits.fp_ctrl.swap12 connect slots_4.io.in_uop.bits.fp_ctrl.ren3, issue_slots[4].in_uop.bits.fp_ctrl.ren3 connect slots_4.io.in_uop.bits.fp_ctrl.ren2, issue_slots[4].in_uop.bits.fp_ctrl.ren2 connect slots_4.io.in_uop.bits.fp_ctrl.ren1, issue_slots[4].in_uop.bits.fp_ctrl.ren1 connect slots_4.io.in_uop.bits.fp_ctrl.wen, issue_slots[4].in_uop.bits.fp_ctrl.wen connect slots_4.io.in_uop.bits.fp_ctrl.ldst, issue_slots[4].in_uop.bits.fp_ctrl.ldst connect slots_4.io.in_uop.bits.op2_sel, issue_slots[4].in_uop.bits.op2_sel connect slots_4.io.in_uop.bits.op1_sel, issue_slots[4].in_uop.bits.op1_sel connect slots_4.io.in_uop.bits.imm_packed, issue_slots[4].in_uop.bits.imm_packed connect slots_4.io.in_uop.bits.pimm, issue_slots[4].in_uop.bits.pimm connect slots_4.io.in_uop.bits.imm_sel, issue_slots[4].in_uop.bits.imm_sel connect slots_4.io.in_uop.bits.imm_rename, issue_slots[4].in_uop.bits.imm_rename connect slots_4.io.in_uop.bits.taken, issue_slots[4].in_uop.bits.taken connect slots_4.io.in_uop.bits.pc_lob, issue_slots[4].in_uop.bits.pc_lob connect slots_4.io.in_uop.bits.edge_inst, issue_slots[4].in_uop.bits.edge_inst connect slots_4.io.in_uop.bits.ftq_idx, issue_slots[4].in_uop.bits.ftq_idx connect slots_4.io.in_uop.bits.is_mov, issue_slots[4].in_uop.bits.is_mov connect slots_4.io.in_uop.bits.is_rocc, issue_slots[4].in_uop.bits.is_rocc connect slots_4.io.in_uop.bits.is_sys_pc2epc, issue_slots[4].in_uop.bits.is_sys_pc2epc connect slots_4.io.in_uop.bits.is_eret, issue_slots[4].in_uop.bits.is_eret connect slots_4.io.in_uop.bits.is_amo, issue_slots[4].in_uop.bits.is_amo connect slots_4.io.in_uop.bits.is_sfence, issue_slots[4].in_uop.bits.is_sfence connect slots_4.io.in_uop.bits.is_fencei, issue_slots[4].in_uop.bits.is_fencei connect slots_4.io.in_uop.bits.is_fence, issue_slots[4].in_uop.bits.is_fence connect slots_4.io.in_uop.bits.is_sfb, issue_slots[4].in_uop.bits.is_sfb connect slots_4.io.in_uop.bits.br_type, issue_slots[4].in_uop.bits.br_type connect slots_4.io.in_uop.bits.br_tag, issue_slots[4].in_uop.bits.br_tag connect slots_4.io.in_uop.bits.br_mask, issue_slots[4].in_uop.bits.br_mask connect slots_4.io.in_uop.bits.dis_col_sel, issue_slots[4].in_uop.bits.dis_col_sel connect slots_4.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[4].in_uop.bits.iw_p3_bypass_hint connect slots_4.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[4].in_uop.bits.iw_p2_bypass_hint connect slots_4.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[4].in_uop.bits.iw_p1_bypass_hint connect slots_4.io.in_uop.bits.iw_p2_speculative_child, issue_slots[4].in_uop.bits.iw_p2_speculative_child connect slots_4.io.in_uop.bits.iw_p1_speculative_child, issue_slots[4].in_uop.bits.iw_p1_speculative_child connect slots_4.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[4].in_uop.bits.iw_issued_partial_dgen connect slots_4.io.in_uop.bits.iw_issued_partial_agen, issue_slots[4].in_uop.bits.iw_issued_partial_agen connect slots_4.io.in_uop.bits.iw_issued, issue_slots[4].in_uop.bits.iw_issued connect slots_4.io.in_uop.bits.fu_code[0], issue_slots[4].in_uop.bits.fu_code[0] connect slots_4.io.in_uop.bits.fu_code[1], issue_slots[4].in_uop.bits.fu_code[1] connect slots_4.io.in_uop.bits.fu_code[2], issue_slots[4].in_uop.bits.fu_code[2] connect slots_4.io.in_uop.bits.fu_code[3], issue_slots[4].in_uop.bits.fu_code[3] connect slots_4.io.in_uop.bits.fu_code[4], issue_slots[4].in_uop.bits.fu_code[4] connect slots_4.io.in_uop.bits.fu_code[5], issue_slots[4].in_uop.bits.fu_code[5] connect slots_4.io.in_uop.bits.fu_code[6], issue_slots[4].in_uop.bits.fu_code[6] connect slots_4.io.in_uop.bits.fu_code[7], issue_slots[4].in_uop.bits.fu_code[7] connect slots_4.io.in_uop.bits.fu_code[8], issue_slots[4].in_uop.bits.fu_code[8] connect slots_4.io.in_uop.bits.fu_code[9], issue_slots[4].in_uop.bits.fu_code[9] connect slots_4.io.in_uop.bits.iq_type[0], issue_slots[4].in_uop.bits.iq_type[0] connect slots_4.io.in_uop.bits.iq_type[1], issue_slots[4].in_uop.bits.iq_type[1] connect slots_4.io.in_uop.bits.iq_type[2], issue_slots[4].in_uop.bits.iq_type[2] connect slots_4.io.in_uop.bits.iq_type[3], issue_slots[4].in_uop.bits.iq_type[3] connect slots_4.io.in_uop.bits.debug_pc, issue_slots[4].in_uop.bits.debug_pc connect slots_4.io.in_uop.bits.is_rvc, issue_slots[4].in_uop.bits.is_rvc connect slots_4.io.in_uop.bits.debug_inst, issue_slots[4].in_uop.bits.debug_inst connect slots_4.io.in_uop.bits.inst, issue_slots[4].in_uop.bits.inst connect slots_4.io.in_uop.valid, issue_slots[4].in_uop.valid connect issue_slots[4].iss_uop.debug_tsrc, slots_4.io.iss_uop.debug_tsrc connect issue_slots[4].iss_uop.debug_fsrc, slots_4.io.iss_uop.debug_fsrc connect issue_slots[4].iss_uop.bp_xcpt_if, slots_4.io.iss_uop.bp_xcpt_if connect issue_slots[4].iss_uop.bp_debug_if, slots_4.io.iss_uop.bp_debug_if connect issue_slots[4].iss_uop.xcpt_ma_if, slots_4.io.iss_uop.xcpt_ma_if connect issue_slots[4].iss_uop.xcpt_ae_if, slots_4.io.iss_uop.xcpt_ae_if connect issue_slots[4].iss_uop.xcpt_pf_if, slots_4.io.iss_uop.xcpt_pf_if connect issue_slots[4].iss_uop.fp_typ, slots_4.io.iss_uop.fp_typ connect issue_slots[4].iss_uop.fp_rm, slots_4.io.iss_uop.fp_rm connect issue_slots[4].iss_uop.fp_val, slots_4.io.iss_uop.fp_val connect issue_slots[4].iss_uop.fcn_op, slots_4.io.iss_uop.fcn_op connect issue_slots[4].iss_uop.fcn_dw, slots_4.io.iss_uop.fcn_dw connect issue_slots[4].iss_uop.frs3_en, slots_4.io.iss_uop.frs3_en connect issue_slots[4].iss_uop.lrs2_rtype, slots_4.io.iss_uop.lrs2_rtype connect issue_slots[4].iss_uop.lrs1_rtype, slots_4.io.iss_uop.lrs1_rtype connect issue_slots[4].iss_uop.dst_rtype, slots_4.io.iss_uop.dst_rtype connect issue_slots[4].iss_uop.lrs3, slots_4.io.iss_uop.lrs3 connect issue_slots[4].iss_uop.lrs2, slots_4.io.iss_uop.lrs2 connect issue_slots[4].iss_uop.lrs1, slots_4.io.iss_uop.lrs1 connect issue_slots[4].iss_uop.ldst, slots_4.io.iss_uop.ldst connect issue_slots[4].iss_uop.ldst_is_rs1, slots_4.io.iss_uop.ldst_is_rs1 connect issue_slots[4].iss_uop.csr_cmd, slots_4.io.iss_uop.csr_cmd connect issue_slots[4].iss_uop.flush_on_commit, slots_4.io.iss_uop.flush_on_commit connect issue_slots[4].iss_uop.is_unique, slots_4.io.iss_uop.is_unique connect issue_slots[4].iss_uop.uses_stq, slots_4.io.iss_uop.uses_stq connect issue_slots[4].iss_uop.uses_ldq, slots_4.io.iss_uop.uses_ldq connect issue_slots[4].iss_uop.mem_signed, slots_4.io.iss_uop.mem_signed connect issue_slots[4].iss_uop.mem_size, slots_4.io.iss_uop.mem_size connect issue_slots[4].iss_uop.mem_cmd, slots_4.io.iss_uop.mem_cmd connect issue_slots[4].iss_uop.exc_cause, slots_4.io.iss_uop.exc_cause connect issue_slots[4].iss_uop.exception, slots_4.io.iss_uop.exception connect issue_slots[4].iss_uop.stale_pdst, slots_4.io.iss_uop.stale_pdst connect issue_slots[4].iss_uop.ppred_busy, slots_4.io.iss_uop.ppred_busy connect issue_slots[4].iss_uop.prs3_busy, slots_4.io.iss_uop.prs3_busy connect issue_slots[4].iss_uop.prs2_busy, slots_4.io.iss_uop.prs2_busy connect issue_slots[4].iss_uop.prs1_busy, slots_4.io.iss_uop.prs1_busy connect issue_slots[4].iss_uop.ppred, slots_4.io.iss_uop.ppred connect issue_slots[4].iss_uop.prs3, slots_4.io.iss_uop.prs3 connect issue_slots[4].iss_uop.prs2, slots_4.io.iss_uop.prs2 connect issue_slots[4].iss_uop.prs1, slots_4.io.iss_uop.prs1 connect issue_slots[4].iss_uop.pdst, slots_4.io.iss_uop.pdst connect issue_slots[4].iss_uop.rxq_idx, slots_4.io.iss_uop.rxq_idx connect issue_slots[4].iss_uop.stq_idx, slots_4.io.iss_uop.stq_idx connect issue_slots[4].iss_uop.ldq_idx, slots_4.io.iss_uop.ldq_idx connect issue_slots[4].iss_uop.rob_idx, slots_4.io.iss_uop.rob_idx connect issue_slots[4].iss_uop.fp_ctrl.vec, slots_4.io.iss_uop.fp_ctrl.vec connect issue_slots[4].iss_uop.fp_ctrl.wflags, slots_4.io.iss_uop.fp_ctrl.wflags connect issue_slots[4].iss_uop.fp_ctrl.sqrt, slots_4.io.iss_uop.fp_ctrl.sqrt connect issue_slots[4].iss_uop.fp_ctrl.div, slots_4.io.iss_uop.fp_ctrl.div connect issue_slots[4].iss_uop.fp_ctrl.fma, slots_4.io.iss_uop.fp_ctrl.fma connect issue_slots[4].iss_uop.fp_ctrl.fastpipe, slots_4.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[4].iss_uop.fp_ctrl.toint, slots_4.io.iss_uop.fp_ctrl.toint connect issue_slots[4].iss_uop.fp_ctrl.fromint, slots_4.io.iss_uop.fp_ctrl.fromint connect issue_slots[4].iss_uop.fp_ctrl.typeTagOut, slots_4.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[4].iss_uop.fp_ctrl.typeTagIn, slots_4.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[4].iss_uop.fp_ctrl.swap23, slots_4.io.iss_uop.fp_ctrl.swap23 connect issue_slots[4].iss_uop.fp_ctrl.swap12, slots_4.io.iss_uop.fp_ctrl.swap12 connect issue_slots[4].iss_uop.fp_ctrl.ren3, slots_4.io.iss_uop.fp_ctrl.ren3 connect issue_slots[4].iss_uop.fp_ctrl.ren2, slots_4.io.iss_uop.fp_ctrl.ren2 connect issue_slots[4].iss_uop.fp_ctrl.ren1, slots_4.io.iss_uop.fp_ctrl.ren1 connect issue_slots[4].iss_uop.fp_ctrl.wen, slots_4.io.iss_uop.fp_ctrl.wen connect issue_slots[4].iss_uop.fp_ctrl.ldst, slots_4.io.iss_uop.fp_ctrl.ldst connect issue_slots[4].iss_uop.op2_sel, slots_4.io.iss_uop.op2_sel connect issue_slots[4].iss_uop.op1_sel, slots_4.io.iss_uop.op1_sel connect issue_slots[4].iss_uop.imm_packed, slots_4.io.iss_uop.imm_packed connect issue_slots[4].iss_uop.pimm, slots_4.io.iss_uop.pimm connect issue_slots[4].iss_uop.imm_sel, slots_4.io.iss_uop.imm_sel connect issue_slots[4].iss_uop.imm_rename, slots_4.io.iss_uop.imm_rename connect issue_slots[4].iss_uop.taken, slots_4.io.iss_uop.taken connect issue_slots[4].iss_uop.pc_lob, slots_4.io.iss_uop.pc_lob connect issue_slots[4].iss_uop.edge_inst, slots_4.io.iss_uop.edge_inst connect issue_slots[4].iss_uop.ftq_idx, slots_4.io.iss_uop.ftq_idx connect issue_slots[4].iss_uop.is_mov, slots_4.io.iss_uop.is_mov connect issue_slots[4].iss_uop.is_rocc, slots_4.io.iss_uop.is_rocc connect issue_slots[4].iss_uop.is_sys_pc2epc, slots_4.io.iss_uop.is_sys_pc2epc connect issue_slots[4].iss_uop.is_eret, slots_4.io.iss_uop.is_eret connect issue_slots[4].iss_uop.is_amo, slots_4.io.iss_uop.is_amo connect issue_slots[4].iss_uop.is_sfence, slots_4.io.iss_uop.is_sfence connect issue_slots[4].iss_uop.is_fencei, slots_4.io.iss_uop.is_fencei connect issue_slots[4].iss_uop.is_fence, slots_4.io.iss_uop.is_fence connect issue_slots[4].iss_uop.is_sfb, slots_4.io.iss_uop.is_sfb connect issue_slots[4].iss_uop.br_type, slots_4.io.iss_uop.br_type connect issue_slots[4].iss_uop.br_tag, slots_4.io.iss_uop.br_tag connect issue_slots[4].iss_uop.br_mask, slots_4.io.iss_uop.br_mask connect issue_slots[4].iss_uop.dis_col_sel, slots_4.io.iss_uop.dis_col_sel connect issue_slots[4].iss_uop.iw_p3_bypass_hint, slots_4.io.iss_uop.iw_p3_bypass_hint connect issue_slots[4].iss_uop.iw_p2_bypass_hint, slots_4.io.iss_uop.iw_p2_bypass_hint connect issue_slots[4].iss_uop.iw_p1_bypass_hint, slots_4.io.iss_uop.iw_p1_bypass_hint connect issue_slots[4].iss_uop.iw_p2_speculative_child, slots_4.io.iss_uop.iw_p2_speculative_child connect issue_slots[4].iss_uop.iw_p1_speculative_child, slots_4.io.iss_uop.iw_p1_speculative_child connect issue_slots[4].iss_uop.iw_issued_partial_dgen, slots_4.io.iss_uop.iw_issued_partial_dgen connect issue_slots[4].iss_uop.iw_issued_partial_agen, slots_4.io.iss_uop.iw_issued_partial_agen connect issue_slots[4].iss_uop.iw_issued, slots_4.io.iss_uop.iw_issued connect issue_slots[4].iss_uop.fu_code[0], slots_4.io.iss_uop.fu_code[0] connect issue_slots[4].iss_uop.fu_code[1], slots_4.io.iss_uop.fu_code[1] connect issue_slots[4].iss_uop.fu_code[2], slots_4.io.iss_uop.fu_code[2] connect issue_slots[4].iss_uop.fu_code[3], slots_4.io.iss_uop.fu_code[3] connect issue_slots[4].iss_uop.fu_code[4], slots_4.io.iss_uop.fu_code[4] connect issue_slots[4].iss_uop.fu_code[5], slots_4.io.iss_uop.fu_code[5] connect issue_slots[4].iss_uop.fu_code[6], slots_4.io.iss_uop.fu_code[6] connect issue_slots[4].iss_uop.fu_code[7], slots_4.io.iss_uop.fu_code[7] connect issue_slots[4].iss_uop.fu_code[8], slots_4.io.iss_uop.fu_code[8] connect issue_slots[4].iss_uop.fu_code[9], slots_4.io.iss_uop.fu_code[9] connect issue_slots[4].iss_uop.iq_type[0], slots_4.io.iss_uop.iq_type[0] connect issue_slots[4].iss_uop.iq_type[1], slots_4.io.iss_uop.iq_type[1] connect issue_slots[4].iss_uop.iq_type[2], slots_4.io.iss_uop.iq_type[2] connect issue_slots[4].iss_uop.iq_type[3], slots_4.io.iss_uop.iq_type[3] connect issue_slots[4].iss_uop.debug_pc, slots_4.io.iss_uop.debug_pc connect issue_slots[4].iss_uop.is_rvc, slots_4.io.iss_uop.is_rvc connect issue_slots[4].iss_uop.debug_inst, slots_4.io.iss_uop.debug_inst connect issue_slots[4].iss_uop.inst, slots_4.io.iss_uop.inst connect slots_4.io.grant, issue_slots[4].grant connect issue_slots[4].request, slots_4.io.request connect issue_slots[4].will_be_valid, slots_4.io.will_be_valid connect issue_slots[4].valid, slots_4.io.valid connect slots_5.io.child_rebusys, issue_slots[5].child_rebusys connect slots_5.io.pred_wakeup_port.bits, issue_slots[5].pred_wakeup_port.bits connect slots_5.io.pred_wakeup_port.valid, issue_slots[5].pred_wakeup_port.valid connect slots_5.io.wakeup_ports[0].bits.rebusy, issue_slots[5].wakeup_ports[0].bits.rebusy connect slots_5.io.wakeup_ports[0].bits.speculative_mask, issue_slots[5].wakeup_ports[0].bits.speculative_mask connect slots_5.io.wakeup_ports[0].bits.bypassable, issue_slots[5].wakeup_ports[0].bits.bypassable connect slots_5.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[0].bits.uop.debug_tsrc connect slots_5.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[0].bits.uop.debug_fsrc connect slots_5.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_5.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[0].bits.uop.bp_debug_if connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_5.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_5.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[5].wakeup_ports[0].bits.uop.fp_typ connect slots_5.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[5].wakeup_ports[0].bits.uop.fp_rm connect slots_5.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[5].wakeup_ports[0].bits.uop.fp_val connect slots_5.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[5].wakeup_ports[0].bits.uop.fcn_op connect slots_5.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[0].bits.uop.fcn_dw connect slots_5.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[5].wakeup_ports[0].bits.uop.frs3_en connect slots_5.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_5.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_5.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[0].bits.uop.dst_rtype connect slots_5.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[5].wakeup_ports[0].bits.uop.lrs3 connect slots_5.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[5].wakeup_ports[0].bits.uop.lrs2 connect slots_5.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[5].wakeup_ports[0].bits.uop.lrs1 connect slots_5.io.wakeup_ports[0].bits.uop.ldst, issue_slots[5].wakeup_ports[0].bits.uop.ldst connect slots_5.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_5.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[0].bits.uop.csr_cmd connect slots_5.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[0].bits.uop.flush_on_commit connect slots_5.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[5].wakeup_ports[0].bits.uop.is_unique connect slots_5.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[5].wakeup_ports[0].bits.uop.uses_stq connect slots_5.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[0].bits.uop.uses_ldq connect slots_5.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[5].wakeup_ports[0].bits.uop.mem_signed connect slots_5.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[5].wakeup_ports[0].bits.uop.mem_size connect slots_5.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[0].bits.uop.mem_cmd connect slots_5.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[5].wakeup_ports[0].bits.uop.exc_cause connect slots_5.io.wakeup_ports[0].bits.uop.exception, issue_slots[5].wakeup_ports[0].bits.uop.exception connect slots_5.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[0].bits.uop.stale_pdst connect slots_5.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[0].bits.uop.ppred_busy connect slots_5.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs3_busy connect slots_5.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs2_busy connect slots_5.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[0].bits.uop.prs1_busy connect slots_5.io.wakeup_ports[0].bits.uop.ppred, issue_slots[5].wakeup_ports[0].bits.uop.ppred connect slots_5.io.wakeup_ports[0].bits.uop.prs3, issue_slots[5].wakeup_ports[0].bits.uop.prs3 connect slots_5.io.wakeup_ports[0].bits.uop.prs2, issue_slots[5].wakeup_ports[0].bits.uop.prs2 connect slots_5.io.wakeup_ports[0].bits.uop.prs1, issue_slots[5].wakeup_ports[0].bits.uop.prs1 connect slots_5.io.wakeup_ports[0].bits.uop.pdst, issue_slots[5].wakeup_ports[0].bits.uop.pdst connect slots_5.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[0].bits.uop.rxq_idx connect slots_5.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[5].wakeup_ports[0].bits.uop.stq_idx connect slots_5.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[0].bits.uop.ldq_idx connect slots_5.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[5].wakeup_ports[0].bits.uop.rob_idx connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_5.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_5.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[5].wakeup_ports[0].bits.uop.op2_sel connect slots_5.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[5].wakeup_ports[0].bits.uop.op1_sel connect slots_5.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[5].wakeup_ports[0].bits.uop.imm_packed connect slots_5.io.wakeup_ports[0].bits.uop.pimm, issue_slots[5].wakeup_ports[0].bits.uop.pimm connect slots_5.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[5].wakeup_ports[0].bits.uop.imm_sel connect slots_5.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[5].wakeup_ports[0].bits.uop.imm_rename connect slots_5.io.wakeup_ports[0].bits.uop.taken, issue_slots[5].wakeup_ports[0].bits.uop.taken connect slots_5.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[5].wakeup_ports[0].bits.uop.pc_lob connect slots_5.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[5].wakeup_ports[0].bits.uop.edge_inst connect slots_5.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[0].bits.uop.ftq_idx connect slots_5.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[5].wakeup_ports[0].bits.uop.is_mov connect slots_5.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[5].wakeup_ports[0].bits.uop.is_rocc connect slots_5.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_5.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[5].wakeup_ports[0].bits.uop.is_eret connect slots_5.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[5].wakeup_ports[0].bits.uop.is_amo connect slots_5.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[5].wakeup_ports[0].bits.uop.is_sfence connect slots_5.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[5].wakeup_ports[0].bits.uop.is_fencei connect slots_5.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[5].wakeup_ports[0].bits.uop.is_fence connect slots_5.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[5].wakeup_ports[0].bits.uop.is_sfb connect slots_5.io.wakeup_ports[0].bits.uop.br_type, issue_slots[5].wakeup_ports[0].bits.uop.br_type connect slots_5.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[5].wakeup_ports[0].bits.uop.br_tag connect slots_5.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[5].wakeup_ports[0].bits.uop.br_mask connect slots_5.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[0].bits.uop.dis_col_sel connect slots_5.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_5.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_5.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_5.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_5.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_5.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[5].wakeup_ports[0].bits.uop.iw_issued connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[0] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[1] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[2] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[3] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[4] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[5] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[6] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[7] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[8] connect slots_5.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[0].bits.uop.fu_code[9] connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[0] connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[1] connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[2] connect slots_5.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[0].bits.uop.iq_type[3] connect slots_5.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[5].wakeup_ports[0].bits.uop.debug_pc connect slots_5.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[5].wakeup_ports[0].bits.uop.is_rvc connect slots_5.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[5].wakeup_ports[0].bits.uop.debug_inst connect slots_5.io.wakeup_ports[0].bits.uop.inst, issue_slots[5].wakeup_ports[0].bits.uop.inst connect slots_5.io.wakeup_ports[0].valid, issue_slots[5].wakeup_ports[0].valid connect slots_5.io.wakeup_ports[1].bits.rebusy, issue_slots[5].wakeup_ports[1].bits.rebusy connect slots_5.io.wakeup_ports[1].bits.speculative_mask, issue_slots[5].wakeup_ports[1].bits.speculative_mask connect slots_5.io.wakeup_ports[1].bits.bypassable, issue_slots[5].wakeup_ports[1].bits.bypassable connect slots_5.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[5].wakeup_ports[1].bits.uop.debug_tsrc connect slots_5.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[5].wakeup_ports[1].bits.uop.debug_fsrc connect slots_5.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[5].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_5.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[5].wakeup_ports[1].bits.uop.bp_debug_if connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_5.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[5].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_5.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[5].wakeup_ports[1].bits.uop.fp_typ connect slots_5.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[5].wakeup_ports[1].bits.uop.fp_rm connect slots_5.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[5].wakeup_ports[1].bits.uop.fp_val connect slots_5.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[5].wakeup_ports[1].bits.uop.fcn_op connect slots_5.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[5].wakeup_ports[1].bits.uop.fcn_dw connect slots_5.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[5].wakeup_ports[1].bits.uop.frs3_en connect slots_5.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[5].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_5.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[5].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_5.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[5].wakeup_ports[1].bits.uop.dst_rtype connect slots_5.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[5].wakeup_ports[1].bits.uop.lrs3 connect slots_5.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[5].wakeup_ports[1].bits.uop.lrs2 connect slots_5.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[5].wakeup_ports[1].bits.uop.lrs1 connect slots_5.io.wakeup_ports[1].bits.uop.ldst, issue_slots[5].wakeup_ports[1].bits.uop.ldst connect slots_5.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[5].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_5.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[5].wakeup_ports[1].bits.uop.csr_cmd connect slots_5.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[5].wakeup_ports[1].bits.uop.flush_on_commit connect slots_5.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[5].wakeup_ports[1].bits.uop.is_unique connect slots_5.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[5].wakeup_ports[1].bits.uop.uses_stq connect slots_5.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[5].wakeup_ports[1].bits.uop.uses_ldq connect slots_5.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[5].wakeup_ports[1].bits.uop.mem_signed connect slots_5.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[5].wakeup_ports[1].bits.uop.mem_size connect slots_5.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[5].wakeup_ports[1].bits.uop.mem_cmd connect slots_5.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[5].wakeup_ports[1].bits.uop.exc_cause connect slots_5.io.wakeup_ports[1].bits.uop.exception, issue_slots[5].wakeup_ports[1].bits.uop.exception connect slots_5.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[5].wakeup_ports[1].bits.uop.stale_pdst connect slots_5.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[5].wakeup_ports[1].bits.uop.ppred_busy connect slots_5.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs3_busy connect slots_5.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs2_busy connect slots_5.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[5].wakeup_ports[1].bits.uop.prs1_busy connect slots_5.io.wakeup_ports[1].bits.uop.ppred, issue_slots[5].wakeup_ports[1].bits.uop.ppred connect slots_5.io.wakeup_ports[1].bits.uop.prs3, issue_slots[5].wakeup_ports[1].bits.uop.prs3 connect slots_5.io.wakeup_ports[1].bits.uop.prs2, issue_slots[5].wakeup_ports[1].bits.uop.prs2 connect slots_5.io.wakeup_ports[1].bits.uop.prs1, issue_slots[5].wakeup_ports[1].bits.uop.prs1 connect slots_5.io.wakeup_ports[1].bits.uop.pdst, issue_slots[5].wakeup_ports[1].bits.uop.pdst connect slots_5.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[5].wakeup_ports[1].bits.uop.rxq_idx connect slots_5.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[5].wakeup_ports[1].bits.uop.stq_idx connect slots_5.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[5].wakeup_ports[1].bits.uop.ldq_idx connect slots_5.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[5].wakeup_ports[1].bits.uop.rob_idx connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_5.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_5.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[5].wakeup_ports[1].bits.uop.op2_sel connect slots_5.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[5].wakeup_ports[1].bits.uop.op1_sel connect slots_5.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[5].wakeup_ports[1].bits.uop.imm_packed connect slots_5.io.wakeup_ports[1].bits.uop.pimm, issue_slots[5].wakeup_ports[1].bits.uop.pimm connect slots_5.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[5].wakeup_ports[1].bits.uop.imm_sel connect slots_5.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[5].wakeup_ports[1].bits.uop.imm_rename connect slots_5.io.wakeup_ports[1].bits.uop.taken, issue_slots[5].wakeup_ports[1].bits.uop.taken connect slots_5.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[5].wakeup_ports[1].bits.uop.pc_lob connect slots_5.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[5].wakeup_ports[1].bits.uop.edge_inst connect slots_5.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[5].wakeup_ports[1].bits.uop.ftq_idx connect slots_5.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[5].wakeup_ports[1].bits.uop.is_mov connect slots_5.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[5].wakeup_ports[1].bits.uop.is_rocc connect slots_5.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[5].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_5.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[5].wakeup_ports[1].bits.uop.is_eret connect slots_5.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[5].wakeup_ports[1].bits.uop.is_amo connect slots_5.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[5].wakeup_ports[1].bits.uop.is_sfence connect slots_5.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[5].wakeup_ports[1].bits.uop.is_fencei connect slots_5.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[5].wakeup_ports[1].bits.uop.is_fence connect slots_5.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[5].wakeup_ports[1].bits.uop.is_sfb connect slots_5.io.wakeup_ports[1].bits.uop.br_type, issue_slots[5].wakeup_ports[1].bits.uop.br_type connect slots_5.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[5].wakeup_ports[1].bits.uop.br_tag connect slots_5.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[5].wakeup_ports[1].bits.uop.br_mask connect slots_5.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[5].wakeup_ports[1].bits.uop.dis_col_sel connect slots_5.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_5.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_5.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_5.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_5.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_5.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[5].wakeup_ports[1].bits.uop.iw_issued connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[0] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[1] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[2] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[3] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[4] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[5] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[6] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[7] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[8] connect slots_5.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[5].wakeup_ports[1].bits.uop.fu_code[9] connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[0] connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[1] connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[2] connect slots_5.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[5].wakeup_ports[1].bits.uop.iq_type[3] connect slots_5.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[5].wakeup_ports[1].bits.uop.debug_pc connect slots_5.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[5].wakeup_ports[1].bits.uop.is_rvc connect slots_5.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[5].wakeup_ports[1].bits.uop.debug_inst connect slots_5.io.wakeup_ports[1].bits.uop.inst, issue_slots[5].wakeup_ports[1].bits.uop.inst connect slots_5.io.wakeup_ports[1].valid, issue_slots[5].wakeup_ports[1].valid connect slots_5.io.squash_grant, issue_slots[5].squash_grant connect slots_5.io.clear, issue_slots[5].clear connect slots_5.io.kill, issue_slots[5].kill connect slots_5.io.brupdate.b2.target_offset, issue_slots[5].brupdate.b2.target_offset connect slots_5.io.brupdate.b2.jalr_target, issue_slots[5].brupdate.b2.jalr_target connect slots_5.io.brupdate.b2.pc_sel, issue_slots[5].brupdate.b2.pc_sel connect slots_5.io.brupdate.b2.cfi_type, issue_slots[5].brupdate.b2.cfi_type connect slots_5.io.brupdate.b2.taken, issue_slots[5].brupdate.b2.taken connect slots_5.io.brupdate.b2.mispredict, issue_slots[5].brupdate.b2.mispredict connect slots_5.io.brupdate.b2.uop.debug_tsrc, issue_slots[5].brupdate.b2.uop.debug_tsrc connect slots_5.io.brupdate.b2.uop.debug_fsrc, issue_slots[5].brupdate.b2.uop.debug_fsrc connect slots_5.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[5].brupdate.b2.uop.bp_xcpt_if connect slots_5.io.brupdate.b2.uop.bp_debug_if, issue_slots[5].brupdate.b2.uop.bp_debug_if connect slots_5.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[5].brupdate.b2.uop.xcpt_ma_if connect slots_5.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[5].brupdate.b2.uop.xcpt_ae_if connect slots_5.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[5].brupdate.b2.uop.xcpt_pf_if connect slots_5.io.brupdate.b2.uop.fp_typ, issue_slots[5].brupdate.b2.uop.fp_typ connect slots_5.io.brupdate.b2.uop.fp_rm, issue_slots[5].brupdate.b2.uop.fp_rm connect slots_5.io.brupdate.b2.uop.fp_val, issue_slots[5].brupdate.b2.uop.fp_val connect slots_5.io.brupdate.b2.uop.fcn_op, issue_slots[5].brupdate.b2.uop.fcn_op connect slots_5.io.brupdate.b2.uop.fcn_dw, issue_slots[5].brupdate.b2.uop.fcn_dw connect slots_5.io.brupdate.b2.uop.frs3_en, issue_slots[5].brupdate.b2.uop.frs3_en connect slots_5.io.brupdate.b2.uop.lrs2_rtype, issue_slots[5].brupdate.b2.uop.lrs2_rtype connect slots_5.io.brupdate.b2.uop.lrs1_rtype, issue_slots[5].brupdate.b2.uop.lrs1_rtype connect slots_5.io.brupdate.b2.uop.dst_rtype, issue_slots[5].brupdate.b2.uop.dst_rtype connect slots_5.io.brupdate.b2.uop.lrs3, issue_slots[5].brupdate.b2.uop.lrs3 connect slots_5.io.brupdate.b2.uop.lrs2, issue_slots[5].brupdate.b2.uop.lrs2 connect slots_5.io.brupdate.b2.uop.lrs1, issue_slots[5].brupdate.b2.uop.lrs1 connect slots_5.io.brupdate.b2.uop.ldst, issue_slots[5].brupdate.b2.uop.ldst connect slots_5.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[5].brupdate.b2.uop.ldst_is_rs1 connect slots_5.io.brupdate.b2.uop.csr_cmd, issue_slots[5].brupdate.b2.uop.csr_cmd connect slots_5.io.brupdate.b2.uop.flush_on_commit, issue_slots[5].brupdate.b2.uop.flush_on_commit connect slots_5.io.brupdate.b2.uop.is_unique, issue_slots[5].brupdate.b2.uop.is_unique connect slots_5.io.brupdate.b2.uop.uses_stq, issue_slots[5].brupdate.b2.uop.uses_stq connect slots_5.io.brupdate.b2.uop.uses_ldq, issue_slots[5].brupdate.b2.uop.uses_ldq connect slots_5.io.brupdate.b2.uop.mem_signed, issue_slots[5].brupdate.b2.uop.mem_signed connect slots_5.io.brupdate.b2.uop.mem_size, issue_slots[5].brupdate.b2.uop.mem_size connect slots_5.io.brupdate.b2.uop.mem_cmd, issue_slots[5].brupdate.b2.uop.mem_cmd connect slots_5.io.brupdate.b2.uop.exc_cause, issue_slots[5].brupdate.b2.uop.exc_cause connect slots_5.io.brupdate.b2.uop.exception, issue_slots[5].brupdate.b2.uop.exception connect slots_5.io.brupdate.b2.uop.stale_pdst, issue_slots[5].brupdate.b2.uop.stale_pdst connect slots_5.io.brupdate.b2.uop.ppred_busy, issue_slots[5].brupdate.b2.uop.ppred_busy connect slots_5.io.brupdate.b2.uop.prs3_busy, issue_slots[5].brupdate.b2.uop.prs3_busy connect slots_5.io.brupdate.b2.uop.prs2_busy, issue_slots[5].brupdate.b2.uop.prs2_busy connect slots_5.io.brupdate.b2.uop.prs1_busy, issue_slots[5].brupdate.b2.uop.prs1_busy connect slots_5.io.brupdate.b2.uop.ppred, issue_slots[5].brupdate.b2.uop.ppred connect slots_5.io.brupdate.b2.uop.prs3, issue_slots[5].brupdate.b2.uop.prs3 connect slots_5.io.brupdate.b2.uop.prs2, issue_slots[5].brupdate.b2.uop.prs2 connect slots_5.io.brupdate.b2.uop.prs1, issue_slots[5].brupdate.b2.uop.prs1 connect slots_5.io.brupdate.b2.uop.pdst, issue_slots[5].brupdate.b2.uop.pdst connect slots_5.io.brupdate.b2.uop.rxq_idx, issue_slots[5].brupdate.b2.uop.rxq_idx connect slots_5.io.brupdate.b2.uop.stq_idx, issue_slots[5].brupdate.b2.uop.stq_idx connect slots_5.io.brupdate.b2.uop.ldq_idx, issue_slots[5].brupdate.b2.uop.ldq_idx connect slots_5.io.brupdate.b2.uop.rob_idx, issue_slots[5].brupdate.b2.uop.rob_idx connect slots_5.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[5].brupdate.b2.uop.fp_ctrl.vec connect slots_5.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[5].brupdate.b2.uop.fp_ctrl.wflags connect slots_5.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[5].brupdate.b2.uop.fp_ctrl.sqrt connect slots_5.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[5].brupdate.b2.uop.fp_ctrl.div connect slots_5.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[5].brupdate.b2.uop.fp_ctrl.fma connect slots_5.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[5].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_5.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[5].brupdate.b2.uop.fp_ctrl.toint connect slots_5.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[5].brupdate.b2.uop.fp_ctrl.fromint connect slots_5.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_5.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_5.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[5].brupdate.b2.uop.fp_ctrl.swap23 connect slots_5.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[5].brupdate.b2.uop.fp_ctrl.swap12 connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren3 connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren2 connect slots_5.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[5].brupdate.b2.uop.fp_ctrl.ren1 connect slots_5.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[5].brupdate.b2.uop.fp_ctrl.wen connect slots_5.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[5].brupdate.b2.uop.fp_ctrl.ldst connect slots_5.io.brupdate.b2.uop.op2_sel, issue_slots[5].brupdate.b2.uop.op2_sel connect slots_5.io.brupdate.b2.uop.op1_sel, issue_slots[5].brupdate.b2.uop.op1_sel connect slots_5.io.brupdate.b2.uop.imm_packed, issue_slots[5].brupdate.b2.uop.imm_packed connect slots_5.io.brupdate.b2.uop.pimm, issue_slots[5].brupdate.b2.uop.pimm connect slots_5.io.brupdate.b2.uop.imm_sel, issue_slots[5].brupdate.b2.uop.imm_sel connect slots_5.io.brupdate.b2.uop.imm_rename, issue_slots[5].brupdate.b2.uop.imm_rename connect slots_5.io.brupdate.b2.uop.taken, issue_slots[5].brupdate.b2.uop.taken connect slots_5.io.brupdate.b2.uop.pc_lob, issue_slots[5].brupdate.b2.uop.pc_lob connect slots_5.io.brupdate.b2.uop.edge_inst, issue_slots[5].brupdate.b2.uop.edge_inst connect slots_5.io.brupdate.b2.uop.ftq_idx, issue_slots[5].brupdate.b2.uop.ftq_idx connect slots_5.io.brupdate.b2.uop.is_mov, issue_slots[5].brupdate.b2.uop.is_mov connect slots_5.io.brupdate.b2.uop.is_rocc, issue_slots[5].brupdate.b2.uop.is_rocc connect slots_5.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[5].brupdate.b2.uop.is_sys_pc2epc connect slots_5.io.brupdate.b2.uop.is_eret, issue_slots[5].brupdate.b2.uop.is_eret connect slots_5.io.brupdate.b2.uop.is_amo, issue_slots[5].brupdate.b2.uop.is_amo connect slots_5.io.brupdate.b2.uop.is_sfence, issue_slots[5].brupdate.b2.uop.is_sfence connect slots_5.io.brupdate.b2.uop.is_fencei, issue_slots[5].brupdate.b2.uop.is_fencei connect slots_5.io.brupdate.b2.uop.is_fence, issue_slots[5].brupdate.b2.uop.is_fence connect slots_5.io.brupdate.b2.uop.is_sfb, issue_slots[5].brupdate.b2.uop.is_sfb connect slots_5.io.brupdate.b2.uop.br_type, issue_slots[5].brupdate.b2.uop.br_type connect slots_5.io.brupdate.b2.uop.br_tag, issue_slots[5].brupdate.b2.uop.br_tag connect slots_5.io.brupdate.b2.uop.br_mask, issue_slots[5].brupdate.b2.uop.br_mask connect slots_5.io.brupdate.b2.uop.dis_col_sel, issue_slots[5].brupdate.b2.uop.dis_col_sel connect slots_5.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p3_bypass_hint connect slots_5.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p2_bypass_hint connect slots_5.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[5].brupdate.b2.uop.iw_p1_bypass_hint connect slots_5.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[5].brupdate.b2.uop.iw_p2_speculative_child connect slots_5.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[5].brupdate.b2.uop.iw_p1_speculative_child connect slots_5.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[5].brupdate.b2.uop.iw_issued_partial_dgen connect slots_5.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[5].brupdate.b2.uop.iw_issued_partial_agen connect slots_5.io.brupdate.b2.uop.iw_issued, issue_slots[5].brupdate.b2.uop.iw_issued connect slots_5.io.brupdate.b2.uop.fu_code[0], issue_slots[5].brupdate.b2.uop.fu_code[0] connect slots_5.io.brupdate.b2.uop.fu_code[1], issue_slots[5].brupdate.b2.uop.fu_code[1] connect slots_5.io.brupdate.b2.uop.fu_code[2], issue_slots[5].brupdate.b2.uop.fu_code[2] connect slots_5.io.brupdate.b2.uop.fu_code[3], issue_slots[5].brupdate.b2.uop.fu_code[3] connect slots_5.io.brupdate.b2.uop.fu_code[4], issue_slots[5].brupdate.b2.uop.fu_code[4] connect slots_5.io.brupdate.b2.uop.fu_code[5], issue_slots[5].brupdate.b2.uop.fu_code[5] connect slots_5.io.brupdate.b2.uop.fu_code[6], issue_slots[5].brupdate.b2.uop.fu_code[6] connect slots_5.io.brupdate.b2.uop.fu_code[7], issue_slots[5].brupdate.b2.uop.fu_code[7] connect slots_5.io.brupdate.b2.uop.fu_code[8], issue_slots[5].brupdate.b2.uop.fu_code[8] connect slots_5.io.brupdate.b2.uop.fu_code[9], issue_slots[5].brupdate.b2.uop.fu_code[9] connect slots_5.io.brupdate.b2.uop.iq_type[0], issue_slots[5].brupdate.b2.uop.iq_type[0] connect slots_5.io.brupdate.b2.uop.iq_type[1], issue_slots[5].brupdate.b2.uop.iq_type[1] connect slots_5.io.brupdate.b2.uop.iq_type[2], issue_slots[5].brupdate.b2.uop.iq_type[2] connect slots_5.io.brupdate.b2.uop.iq_type[3], issue_slots[5].brupdate.b2.uop.iq_type[3] connect slots_5.io.brupdate.b2.uop.debug_pc, issue_slots[5].brupdate.b2.uop.debug_pc connect slots_5.io.brupdate.b2.uop.is_rvc, issue_slots[5].brupdate.b2.uop.is_rvc connect slots_5.io.brupdate.b2.uop.debug_inst, issue_slots[5].brupdate.b2.uop.debug_inst connect slots_5.io.brupdate.b2.uop.inst, issue_slots[5].brupdate.b2.uop.inst connect slots_5.io.brupdate.b1.mispredict_mask, issue_slots[5].brupdate.b1.mispredict_mask connect slots_5.io.brupdate.b1.resolve_mask, issue_slots[5].brupdate.b1.resolve_mask connect issue_slots[5].out_uop.debug_tsrc, slots_5.io.out_uop.debug_tsrc connect issue_slots[5].out_uop.debug_fsrc, slots_5.io.out_uop.debug_fsrc connect issue_slots[5].out_uop.bp_xcpt_if, slots_5.io.out_uop.bp_xcpt_if connect issue_slots[5].out_uop.bp_debug_if, slots_5.io.out_uop.bp_debug_if connect issue_slots[5].out_uop.xcpt_ma_if, slots_5.io.out_uop.xcpt_ma_if connect issue_slots[5].out_uop.xcpt_ae_if, slots_5.io.out_uop.xcpt_ae_if connect issue_slots[5].out_uop.xcpt_pf_if, slots_5.io.out_uop.xcpt_pf_if connect issue_slots[5].out_uop.fp_typ, slots_5.io.out_uop.fp_typ connect issue_slots[5].out_uop.fp_rm, slots_5.io.out_uop.fp_rm connect issue_slots[5].out_uop.fp_val, slots_5.io.out_uop.fp_val connect issue_slots[5].out_uop.fcn_op, slots_5.io.out_uop.fcn_op connect issue_slots[5].out_uop.fcn_dw, slots_5.io.out_uop.fcn_dw connect issue_slots[5].out_uop.frs3_en, slots_5.io.out_uop.frs3_en connect issue_slots[5].out_uop.lrs2_rtype, slots_5.io.out_uop.lrs2_rtype connect issue_slots[5].out_uop.lrs1_rtype, slots_5.io.out_uop.lrs1_rtype connect issue_slots[5].out_uop.dst_rtype, slots_5.io.out_uop.dst_rtype connect issue_slots[5].out_uop.lrs3, slots_5.io.out_uop.lrs3 connect issue_slots[5].out_uop.lrs2, slots_5.io.out_uop.lrs2 connect issue_slots[5].out_uop.lrs1, slots_5.io.out_uop.lrs1 connect issue_slots[5].out_uop.ldst, slots_5.io.out_uop.ldst connect issue_slots[5].out_uop.ldst_is_rs1, slots_5.io.out_uop.ldst_is_rs1 connect issue_slots[5].out_uop.csr_cmd, slots_5.io.out_uop.csr_cmd connect issue_slots[5].out_uop.flush_on_commit, slots_5.io.out_uop.flush_on_commit connect issue_slots[5].out_uop.is_unique, slots_5.io.out_uop.is_unique connect issue_slots[5].out_uop.uses_stq, slots_5.io.out_uop.uses_stq connect issue_slots[5].out_uop.uses_ldq, slots_5.io.out_uop.uses_ldq connect issue_slots[5].out_uop.mem_signed, slots_5.io.out_uop.mem_signed connect issue_slots[5].out_uop.mem_size, slots_5.io.out_uop.mem_size connect issue_slots[5].out_uop.mem_cmd, slots_5.io.out_uop.mem_cmd connect issue_slots[5].out_uop.exc_cause, slots_5.io.out_uop.exc_cause connect issue_slots[5].out_uop.exception, slots_5.io.out_uop.exception connect issue_slots[5].out_uop.stale_pdst, slots_5.io.out_uop.stale_pdst connect issue_slots[5].out_uop.ppred_busy, slots_5.io.out_uop.ppred_busy connect issue_slots[5].out_uop.prs3_busy, slots_5.io.out_uop.prs3_busy connect issue_slots[5].out_uop.prs2_busy, slots_5.io.out_uop.prs2_busy connect issue_slots[5].out_uop.prs1_busy, slots_5.io.out_uop.prs1_busy connect issue_slots[5].out_uop.ppred, slots_5.io.out_uop.ppred connect issue_slots[5].out_uop.prs3, slots_5.io.out_uop.prs3 connect issue_slots[5].out_uop.prs2, slots_5.io.out_uop.prs2 connect issue_slots[5].out_uop.prs1, slots_5.io.out_uop.prs1 connect issue_slots[5].out_uop.pdst, slots_5.io.out_uop.pdst connect issue_slots[5].out_uop.rxq_idx, slots_5.io.out_uop.rxq_idx connect issue_slots[5].out_uop.stq_idx, slots_5.io.out_uop.stq_idx connect issue_slots[5].out_uop.ldq_idx, slots_5.io.out_uop.ldq_idx connect issue_slots[5].out_uop.rob_idx, slots_5.io.out_uop.rob_idx connect issue_slots[5].out_uop.fp_ctrl.vec, slots_5.io.out_uop.fp_ctrl.vec connect issue_slots[5].out_uop.fp_ctrl.wflags, slots_5.io.out_uop.fp_ctrl.wflags connect issue_slots[5].out_uop.fp_ctrl.sqrt, slots_5.io.out_uop.fp_ctrl.sqrt connect issue_slots[5].out_uop.fp_ctrl.div, slots_5.io.out_uop.fp_ctrl.div connect issue_slots[5].out_uop.fp_ctrl.fma, slots_5.io.out_uop.fp_ctrl.fma connect issue_slots[5].out_uop.fp_ctrl.fastpipe, slots_5.io.out_uop.fp_ctrl.fastpipe connect issue_slots[5].out_uop.fp_ctrl.toint, slots_5.io.out_uop.fp_ctrl.toint connect issue_slots[5].out_uop.fp_ctrl.fromint, slots_5.io.out_uop.fp_ctrl.fromint connect issue_slots[5].out_uop.fp_ctrl.typeTagOut, slots_5.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[5].out_uop.fp_ctrl.typeTagIn, slots_5.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[5].out_uop.fp_ctrl.swap23, slots_5.io.out_uop.fp_ctrl.swap23 connect issue_slots[5].out_uop.fp_ctrl.swap12, slots_5.io.out_uop.fp_ctrl.swap12 connect issue_slots[5].out_uop.fp_ctrl.ren3, slots_5.io.out_uop.fp_ctrl.ren3 connect issue_slots[5].out_uop.fp_ctrl.ren2, slots_5.io.out_uop.fp_ctrl.ren2 connect issue_slots[5].out_uop.fp_ctrl.ren1, slots_5.io.out_uop.fp_ctrl.ren1 connect issue_slots[5].out_uop.fp_ctrl.wen, slots_5.io.out_uop.fp_ctrl.wen connect issue_slots[5].out_uop.fp_ctrl.ldst, slots_5.io.out_uop.fp_ctrl.ldst connect issue_slots[5].out_uop.op2_sel, slots_5.io.out_uop.op2_sel connect issue_slots[5].out_uop.op1_sel, slots_5.io.out_uop.op1_sel connect issue_slots[5].out_uop.imm_packed, slots_5.io.out_uop.imm_packed connect issue_slots[5].out_uop.pimm, slots_5.io.out_uop.pimm connect issue_slots[5].out_uop.imm_sel, slots_5.io.out_uop.imm_sel connect issue_slots[5].out_uop.imm_rename, slots_5.io.out_uop.imm_rename connect issue_slots[5].out_uop.taken, slots_5.io.out_uop.taken connect issue_slots[5].out_uop.pc_lob, slots_5.io.out_uop.pc_lob connect issue_slots[5].out_uop.edge_inst, slots_5.io.out_uop.edge_inst connect issue_slots[5].out_uop.ftq_idx, slots_5.io.out_uop.ftq_idx connect issue_slots[5].out_uop.is_mov, slots_5.io.out_uop.is_mov connect issue_slots[5].out_uop.is_rocc, slots_5.io.out_uop.is_rocc connect issue_slots[5].out_uop.is_sys_pc2epc, slots_5.io.out_uop.is_sys_pc2epc connect issue_slots[5].out_uop.is_eret, slots_5.io.out_uop.is_eret connect issue_slots[5].out_uop.is_amo, slots_5.io.out_uop.is_amo connect issue_slots[5].out_uop.is_sfence, slots_5.io.out_uop.is_sfence connect issue_slots[5].out_uop.is_fencei, slots_5.io.out_uop.is_fencei connect issue_slots[5].out_uop.is_fence, slots_5.io.out_uop.is_fence connect issue_slots[5].out_uop.is_sfb, slots_5.io.out_uop.is_sfb connect issue_slots[5].out_uop.br_type, slots_5.io.out_uop.br_type connect issue_slots[5].out_uop.br_tag, slots_5.io.out_uop.br_tag connect issue_slots[5].out_uop.br_mask, slots_5.io.out_uop.br_mask connect issue_slots[5].out_uop.dis_col_sel, slots_5.io.out_uop.dis_col_sel connect issue_slots[5].out_uop.iw_p3_bypass_hint, slots_5.io.out_uop.iw_p3_bypass_hint connect issue_slots[5].out_uop.iw_p2_bypass_hint, slots_5.io.out_uop.iw_p2_bypass_hint connect issue_slots[5].out_uop.iw_p1_bypass_hint, slots_5.io.out_uop.iw_p1_bypass_hint connect issue_slots[5].out_uop.iw_p2_speculative_child, slots_5.io.out_uop.iw_p2_speculative_child connect issue_slots[5].out_uop.iw_p1_speculative_child, slots_5.io.out_uop.iw_p1_speculative_child connect issue_slots[5].out_uop.iw_issued_partial_dgen, slots_5.io.out_uop.iw_issued_partial_dgen connect issue_slots[5].out_uop.iw_issued_partial_agen, slots_5.io.out_uop.iw_issued_partial_agen connect issue_slots[5].out_uop.iw_issued, slots_5.io.out_uop.iw_issued connect issue_slots[5].out_uop.fu_code[0], slots_5.io.out_uop.fu_code[0] connect issue_slots[5].out_uop.fu_code[1], slots_5.io.out_uop.fu_code[1] connect issue_slots[5].out_uop.fu_code[2], slots_5.io.out_uop.fu_code[2] connect issue_slots[5].out_uop.fu_code[3], slots_5.io.out_uop.fu_code[3] connect issue_slots[5].out_uop.fu_code[4], slots_5.io.out_uop.fu_code[4] connect issue_slots[5].out_uop.fu_code[5], slots_5.io.out_uop.fu_code[5] connect issue_slots[5].out_uop.fu_code[6], slots_5.io.out_uop.fu_code[6] connect issue_slots[5].out_uop.fu_code[7], slots_5.io.out_uop.fu_code[7] connect issue_slots[5].out_uop.fu_code[8], slots_5.io.out_uop.fu_code[8] connect issue_slots[5].out_uop.fu_code[9], slots_5.io.out_uop.fu_code[9] connect issue_slots[5].out_uop.iq_type[0], slots_5.io.out_uop.iq_type[0] connect issue_slots[5].out_uop.iq_type[1], slots_5.io.out_uop.iq_type[1] connect issue_slots[5].out_uop.iq_type[2], slots_5.io.out_uop.iq_type[2] connect issue_slots[5].out_uop.iq_type[3], slots_5.io.out_uop.iq_type[3] connect issue_slots[5].out_uop.debug_pc, slots_5.io.out_uop.debug_pc connect issue_slots[5].out_uop.is_rvc, slots_5.io.out_uop.is_rvc connect issue_slots[5].out_uop.debug_inst, slots_5.io.out_uop.debug_inst connect issue_slots[5].out_uop.inst, slots_5.io.out_uop.inst connect slots_5.io.in_uop.bits.debug_tsrc, issue_slots[5].in_uop.bits.debug_tsrc connect slots_5.io.in_uop.bits.debug_fsrc, issue_slots[5].in_uop.bits.debug_fsrc connect slots_5.io.in_uop.bits.bp_xcpt_if, issue_slots[5].in_uop.bits.bp_xcpt_if connect slots_5.io.in_uop.bits.bp_debug_if, issue_slots[5].in_uop.bits.bp_debug_if connect slots_5.io.in_uop.bits.xcpt_ma_if, issue_slots[5].in_uop.bits.xcpt_ma_if connect slots_5.io.in_uop.bits.xcpt_ae_if, issue_slots[5].in_uop.bits.xcpt_ae_if connect slots_5.io.in_uop.bits.xcpt_pf_if, issue_slots[5].in_uop.bits.xcpt_pf_if connect slots_5.io.in_uop.bits.fp_typ, issue_slots[5].in_uop.bits.fp_typ connect slots_5.io.in_uop.bits.fp_rm, issue_slots[5].in_uop.bits.fp_rm connect slots_5.io.in_uop.bits.fp_val, issue_slots[5].in_uop.bits.fp_val connect slots_5.io.in_uop.bits.fcn_op, issue_slots[5].in_uop.bits.fcn_op connect slots_5.io.in_uop.bits.fcn_dw, issue_slots[5].in_uop.bits.fcn_dw connect slots_5.io.in_uop.bits.frs3_en, issue_slots[5].in_uop.bits.frs3_en connect slots_5.io.in_uop.bits.lrs2_rtype, issue_slots[5].in_uop.bits.lrs2_rtype connect slots_5.io.in_uop.bits.lrs1_rtype, issue_slots[5].in_uop.bits.lrs1_rtype connect slots_5.io.in_uop.bits.dst_rtype, issue_slots[5].in_uop.bits.dst_rtype connect slots_5.io.in_uop.bits.lrs3, issue_slots[5].in_uop.bits.lrs3 connect slots_5.io.in_uop.bits.lrs2, issue_slots[5].in_uop.bits.lrs2 connect slots_5.io.in_uop.bits.lrs1, issue_slots[5].in_uop.bits.lrs1 connect slots_5.io.in_uop.bits.ldst, issue_slots[5].in_uop.bits.ldst connect slots_5.io.in_uop.bits.ldst_is_rs1, issue_slots[5].in_uop.bits.ldst_is_rs1 connect slots_5.io.in_uop.bits.csr_cmd, issue_slots[5].in_uop.bits.csr_cmd connect slots_5.io.in_uop.bits.flush_on_commit, issue_slots[5].in_uop.bits.flush_on_commit connect slots_5.io.in_uop.bits.is_unique, issue_slots[5].in_uop.bits.is_unique connect slots_5.io.in_uop.bits.uses_stq, issue_slots[5].in_uop.bits.uses_stq connect slots_5.io.in_uop.bits.uses_ldq, issue_slots[5].in_uop.bits.uses_ldq connect slots_5.io.in_uop.bits.mem_signed, issue_slots[5].in_uop.bits.mem_signed connect slots_5.io.in_uop.bits.mem_size, issue_slots[5].in_uop.bits.mem_size connect slots_5.io.in_uop.bits.mem_cmd, issue_slots[5].in_uop.bits.mem_cmd connect slots_5.io.in_uop.bits.exc_cause, issue_slots[5].in_uop.bits.exc_cause connect slots_5.io.in_uop.bits.exception, issue_slots[5].in_uop.bits.exception connect slots_5.io.in_uop.bits.stale_pdst, issue_slots[5].in_uop.bits.stale_pdst connect slots_5.io.in_uop.bits.ppred_busy, issue_slots[5].in_uop.bits.ppred_busy connect slots_5.io.in_uop.bits.prs3_busy, issue_slots[5].in_uop.bits.prs3_busy connect slots_5.io.in_uop.bits.prs2_busy, issue_slots[5].in_uop.bits.prs2_busy connect slots_5.io.in_uop.bits.prs1_busy, issue_slots[5].in_uop.bits.prs1_busy connect slots_5.io.in_uop.bits.ppred, issue_slots[5].in_uop.bits.ppred connect slots_5.io.in_uop.bits.prs3, issue_slots[5].in_uop.bits.prs3 connect slots_5.io.in_uop.bits.prs2, issue_slots[5].in_uop.bits.prs2 connect slots_5.io.in_uop.bits.prs1, issue_slots[5].in_uop.bits.prs1 connect slots_5.io.in_uop.bits.pdst, issue_slots[5].in_uop.bits.pdst connect slots_5.io.in_uop.bits.rxq_idx, issue_slots[5].in_uop.bits.rxq_idx connect slots_5.io.in_uop.bits.stq_idx, issue_slots[5].in_uop.bits.stq_idx connect slots_5.io.in_uop.bits.ldq_idx, issue_slots[5].in_uop.bits.ldq_idx connect slots_5.io.in_uop.bits.rob_idx, issue_slots[5].in_uop.bits.rob_idx connect slots_5.io.in_uop.bits.fp_ctrl.vec, issue_slots[5].in_uop.bits.fp_ctrl.vec connect slots_5.io.in_uop.bits.fp_ctrl.wflags, issue_slots[5].in_uop.bits.fp_ctrl.wflags connect slots_5.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[5].in_uop.bits.fp_ctrl.sqrt connect slots_5.io.in_uop.bits.fp_ctrl.div, issue_slots[5].in_uop.bits.fp_ctrl.div connect slots_5.io.in_uop.bits.fp_ctrl.fma, issue_slots[5].in_uop.bits.fp_ctrl.fma connect slots_5.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].in_uop.bits.fp_ctrl.fastpipe connect slots_5.io.in_uop.bits.fp_ctrl.toint, issue_slots[5].in_uop.bits.fp_ctrl.toint connect slots_5.io.in_uop.bits.fp_ctrl.fromint, issue_slots[5].in_uop.bits.fp_ctrl.fromint connect slots_5.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut connect slots_5.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn connect slots_5.io.in_uop.bits.fp_ctrl.swap23, issue_slots[5].in_uop.bits.fp_ctrl.swap23 connect slots_5.io.in_uop.bits.fp_ctrl.swap12, issue_slots[5].in_uop.bits.fp_ctrl.swap12 connect slots_5.io.in_uop.bits.fp_ctrl.ren3, issue_slots[5].in_uop.bits.fp_ctrl.ren3 connect slots_5.io.in_uop.bits.fp_ctrl.ren2, issue_slots[5].in_uop.bits.fp_ctrl.ren2 connect slots_5.io.in_uop.bits.fp_ctrl.ren1, issue_slots[5].in_uop.bits.fp_ctrl.ren1 connect slots_5.io.in_uop.bits.fp_ctrl.wen, issue_slots[5].in_uop.bits.fp_ctrl.wen connect slots_5.io.in_uop.bits.fp_ctrl.ldst, issue_slots[5].in_uop.bits.fp_ctrl.ldst connect slots_5.io.in_uop.bits.op2_sel, issue_slots[5].in_uop.bits.op2_sel connect slots_5.io.in_uop.bits.op1_sel, issue_slots[5].in_uop.bits.op1_sel connect slots_5.io.in_uop.bits.imm_packed, issue_slots[5].in_uop.bits.imm_packed connect slots_5.io.in_uop.bits.pimm, issue_slots[5].in_uop.bits.pimm connect slots_5.io.in_uop.bits.imm_sel, issue_slots[5].in_uop.bits.imm_sel connect slots_5.io.in_uop.bits.imm_rename, issue_slots[5].in_uop.bits.imm_rename connect slots_5.io.in_uop.bits.taken, issue_slots[5].in_uop.bits.taken connect slots_5.io.in_uop.bits.pc_lob, issue_slots[5].in_uop.bits.pc_lob connect slots_5.io.in_uop.bits.edge_inst, issue_slots[5].in_uop.bits.edge_inst connect slots_5.io.in_uop.bits.ftq_idx, issue_slots[5].in_uop.bits.ftq_idx connect slots_5.io.in_uop.bits.is_mov, issue_slots[5].in_uop.bits.is_mov connect slots_5.io.in_uop.bits.is_rocc, issue_slots[5].in_uop.bits.is_rocc connect slots_5.io.in_uop.bits.is_sys_pc2epc, issue_slots[5].in_uop.bits.is_sys_pc2epc connect slots_5.io.in_uop.bits.is_eret, issue_slots[5].in_uop.bits.is_eret connect slots_5.io.in_uop.bits.is_amo, issue_slots[5].in_uop.bits.is_amo connect slots_5.io.in_uop.bits.is_sfence, issue_slots[5].in_uop.bits.is_sfence connect slots_5.io.in_uop.bits.is_fencei, issue_slots[5].in_uop.bits.is_fencei connect slots_5.io.in_uop.bits.is_fence, issue_slots[5].in_uop.bits.is_fence connect slots_5.io.in_uop.bits.is_sfb, issue_slots[5].in_uop.bits.is_sfb connect slots_5.io.in_uop.bits.br_type, issue_slots[5].in_uop.bits.br_type connect slots_5.io.in_uop.bits.br_tag, issue_slots[5].in_uop.bits.br_tag connect slots_5.io.in_uop.bits.br_mask, issue_slots[5].in_uop.bits.br_mask connect slots_5.io.in_uop.bits.dis_col_sel, issue_slots[5].in_uop.bits.dis_col_sel connect slots_5.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[5].in_uop.bits.iw_p3_bypass_hint connect slots_5.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[5].in_uop.bits.iw_p2_bypass_hint connect slots_5.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[5].in_uop.bits.iw_p1_bypass_hint connect slots_5.io.in_uop.bits.iw_p2_speculative_child, issue_slots[5].in_uop.bits.iw_p2_speculative_child connect slots_5.io.in_uop.bits.iw_p1_speculative_child, issue_slots[5].in_uop.bits.iw_p1_speculative_child connect slots_5.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[5].in_uop.bits.iw_issued_partial_dgen connect slots_5.io.in_uop.bits.iw_issued_partial_agen, issue_slots[5].in_uop.bits.iw_issued_partial_agen connect slots_5.io.in_uop.bits.iw_issued, issue_slots[5].in_uop.bits.iw_issued connect slots_5.io.in_uop.bits.fu_code[0], issue_slots[5].in_uop.bits.fu_code[0] connect slots_5.io.in_uop.bits.fu_code[1], issue_slots[5].in_uop.bits.fu_code[1] connect slots_5.io.in_uop.bits.fu_code[2], issue_slots[5].in_uop.bits.fu_code[2] connect slots_5.io.in_uop.bits.fu_code[3], issue_slots[5].in_uop.bits.fu_code[3] connect slots_5.io.in_uop.bits.fu_code[4], issue_slots[5].in_uop.bits.fu_code[4] connect slots_5.io.in_uop.bits.fu_code[5], issue_slots[5].in_uop.bits.fu_code[5] connect slots_5.io.in_uop.bits.fu_code[6], issue_slots[5].in_uop.bits.fu_code[6] connect slots_5.io.in_uop.bits.fu_code[7], issue_slots[5].in_uop.bits.fu_code[7] connect slots_5.io.in_uop.bits.fu_code[8], issue_slots[5].in_uop.bits.fu_code[8] connect slots_5.io.in_uop.bits.fu_code[9], issue_slots[5].in_uop.bits.fu_code[9] connect slots_5.io.in_uop.bits.iq_type[0], issue_slots[5].in_uop.bits.iq_type[0] connect slots_5.io.in_uop.bits.iq_type[1], issue_slots[5].in_uop.bits.iq_type[1] connect slots_5.io.in_uop.bits.iq_type[2], issue_slots[5].in_uop.bits.iq_type[2] connect slots_5.io.in_uop.bits.iq_type[3], issue_slots[5].in_uop.bits.iq_type[3] connect slots_5.io.in_uop.bits.debug_pc, issue_slots[5].in_uop.bits.debug_pc connect slots_5.io.in_uop.bits.is_rvc, issue_slots[5].in_uop.bits.is_rvc connect slots_5.io.in_uop.bits.debug_inst, issue_slots[5].in_uop.bits.debug_inst connect slots_5.io.in_uop.bits.inst, issue_slots[5].in_uop.bits.inst connect slots_5.io.in_uop.valid, issue_slots[5].in_uop.valid connect issue_slots[5].iss_uop.debug_tsrc, slots_5.io.iss_uop.debug_tsrc connect issue_slots[5].iss_uop.debug_fsrc, slots_5.io.iss_uop.debug_fsrc connect issue_slots[5].iss_uop.bp_xcpt_if, slots_5.io.iss_uop.bp_xcpt_if connect issue_slots[5].iss_uop.bp_debug_if, slots_5.io.iss_uop.bp_debug_if connect issue_slots[5].iss_uop.xcpt_ma_if, slots_5.io.iss_uop.xcpt_ma_if connect issue_slots[5].iss_uop.xcpt_ae_if, slots_5.io.iss_uop.xcpt_ae_if connect issue_slots[5].iss_uop.xcpt_pf_if, slots_5.io.iss_uop.xcpt_pf_if connect issue_slots[5].iss_uop.fp_typ, slots_5.io.iss_uop.fp_typ connect issue_slots[5].iss_uop.fp_rm, slots_5.io.iss_uop.fp_rm connect issue_slots[5].iss_uop.fp_val, slots_5.io.iss_uop.fp_val connect issue_slots[5].iss_uop.fcn_op, slots_5.io.iss_uop.fcn_op connect issue_slots[5].iss_uop.fcn_dw, slots_5.io.iss_uop.fcn_dw connect issue_slots[5].iss_uop.frs3_en, slots_5.io.iss_uop.frs3_en connect issue_slots[5].iss_uop.lrs2_rtype, slots_5.io.iss_uop.lrs2_rtype connect issue_slots[5].iss_uop.lrs1_rtype, slots_5.io.iss_uop.lrs1_rtype connect issue_slots[5].iss_uop.dst_rtype, slots_5.io.iss_uop.dst_rtype connect issue_slots[5].iss_uop.lrs3, slots_5.io.iss_uop.lrs3 connect issue_slots[5].iss_uop.lrs2, slots_5.io.iss_uop.lrs2 connect issue_slots[5].iss_uop.lrs1, slots_5.io.iss_uop.lrs1 connect issue_slots[5].iss_uop.ldst, slots_5.io.iss_uop.ldst connect issue_slots[5].iss_uop.ldst_is_rs1, slots_5.io.iss_uop.ldst_is_rs1 connect issue_slots[5].iss_uop.csr_cmd, slots_5.io.iss_uop.csr_cmd connect issue_slots[5].iss_uop.flush_on_commit, slots_5.io.iss_uop.flush_on_commit connect issue_slots[5].iss_uop.is_unique, slots_5.io.iss_uop.is_unique connect issue_slots[5].iss_uop.uses_stq, slots_5.io.iss_uop.uses_stq connect issue_slots[5].iss_uop.uses_ldq, slots_5.io.iss_uop.uses_ldq connect issue_slots[5].iss_uop.mem_signed, slots_5.io.iss_uop.mem_signed connect issue_slots[5].iss_uop.mem_size, slots_5.io.iss_uop.mem_size connect issue_slots[5].iss_uop.mem_cmd, slots_5.io.iss_uop.mem_cmd connect issue_slots[5].iss_uop.exc_cause, slots_5.io.iss_uop.exc_cause connect issue_slots[5].iss_uop.exception, slots_5.io.iss_uop.exception connect issue_slots[5].iss_uop.stale_pdst, slots_5.io.iss_uop.stale_pdst connect issue_slots[5].iss_uop.ppred_busy, slots_5.io.iss_uop.ppred_busy connect issue_slots[5].iss_uop.prs3_busy, slots_5.io.iss_uop.prs3_busy connect issue_slots[5].iss_uop.prs2_busy, slots_5.io.iss_uop.prs2_busy connect issue_slots[5].iss_uop.prs1_busy, slots_5.io.iss_uop.prs1_busy connect issue_slots[5].iss_uop.ppred, slots_5.io.iss_uop.ppred connect issue_slots[5].iss_uop.prs3, slots_5.io.iss_uop.prs3 connect issue_slots[5].iss_uop.prs2, slots_5.io.iss_uop.prs2 connect issue_slots[5].iss_uop.prs1, slots_5.io.iss_uop.prs1 connect issue_slots[5].iss_uop.pdst, slots_5.io.iss_uop.pdst connect issue_slots[5].iss_uop.rxq_idx, slots_5.io.iss_uop.rxq_idx connect issue_slots[5].iss_uop.stq_idx, slots_5.io.iss_uop.stq_idx connect issue_slots[5].iss_uop.ldq_idx, slots_5.io.iss_uop.ldq_idx connect issue_slots[5].iss_uop.rob_idx, slots_5.io.iss_uop.rob_idx connect issue_slots[5].iss_uop.fp_ctrl.vec, slots_5.io.iss_uop.fp_ctrl.vec connect issue_slots[5].iss_uop.fp_ctrl.wflags, slots_5.io.iss_uop.fp_ctrl.wflags connect issue_slots[5].iss_uop.fp_ctrl.sqrt, slots_5.io.iss_uop.fp_ctrl.sqrt connect issue_slots[5].iss_uop.fp_ctrl.div, slots_5.io.iss_uop.fp_ctrl.div connect issue_slots[5].iss_uop.fp_ctrl.fma, slots_5.io.iss_uop.fp_ctrl.fma connect issue_slots[5].iss_uop.fp_ctrl.fastpipe, slots_5.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[5].iss_uop.fp_ctrl.toint, slots_5.io.iss_uop.fp_ctrl.toint connect issue_slots[5].iss_uop.fp_ctrl.fromint, slots_5.io.iss_uop.fp_ctrl.fromint connect issue_slots[5].iss_uop.fp_ctrl.typeTagOut, slots_5.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[5].iss_uop.fp_ctrl.typeTagIn, slots_5.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[5].iss_uop.fp_ctrl.swap23, slots_5.io.iss_uop.fp_ctrl.swap23 connect issue_slots[5].iss_uop.fp_ctrl.swap12, slots_5.io.iss_uop.fp_ctrl.swap12 connect issue_slots[5].iss_uop.fp_ctrl.ren3, slots_5.io.iss_uop.fp_ctrl.ren3 connect issue_slots[5].iss_uop.fp_ctrl.ren2, slots_5.io.iss_uop.fp_ctrl.ren2 connect issue_slots[5].iss_uop.fp_ctrl.ren1, slots_5.io.iss_uop.fp_ctrl.ren1 connect issue_slots[5].iss_uop.fp_ctrl.wen, slots_5.io.iss_uop.fp_ctrl.wen connect issue_slots[5].iss_uop.fp_ctrl.ldst, slots_5.io.iss_uop.fp_ctrl.ldst connect issue_slots[5].iss_uop.op2_sel, slots_5.io.iss_uop.op2_sel connect issue_slots[5].iss_uop.op1_sel, slots_5.io.iss_uop.op1_sel connect issue_slots[5].iss_uop.imm_packed, slots_5.io.iss_uop.imm_packed connect issue_slots[5].iss_uop.pimm, slots_5.io.iss_uop.pimm connect issue_slots[5].iss_uop.imm_sel, slots_5.io.iss_uop.imm_sel connect issue_slots[5].iss_uop.imm_rename, slots_5.io.iss_uop.imm_rename connect issue_slots[5].iss_uop.taken, slots_5.io.iss_uop.taken connect issue_slots[5].iss_uop.pc_lob, slots_5.io.iss_uop.pc_lob connect issue_slots[5].iss_uop.edge_inst, slots_5.io.iss_uop.edge_inst connect issue_slots[5].iss_uop.ftq_idx, slots_5.io.iss_uop.ftq_idx connect issue_slots[5].iss_uop.is_mov, slots_5.io.iss_uop.is_mov connect issue_slots[5].iss_uop.is_rocc, slots_5.io.iss_uop.is_rocc connect issue_slots[5].iss_uop.is_sys_pc2epc, slots_5.io.iss_uop.is_sys_pc2epc connect issue_slots[5].iss_uop.is_eret, slots_5.io.iss_uop.is_eret connect issue_slots[5].iss_uop.is_amo, slots_5.io.iss_uop.is_amo connect issue_slots[5].iss_uop.is_sfence, slots_5.io.iss_uop.is_sfence connect issue_slots[5].iss_uop.is_fencei, slots_5.io.iss_uop.is_fencei connect issue_slots[5].iss_uop.is_fence, slots_5.io.iss_uop.is_fence connect issue_slots[5].iss_uop.is_sfb, slots_5.io.iss_uop.is_sfb connect issue_slots[5].iss_uop.br_type, slots_5.io.iss_uop.br_type connect issue_slots[5].iss_uop.br_tag, slots_5.io.iss_uop.br_tag connect issue_slots[5].iss_uop.br_mask, slots_5.io.iss_uop.br_mask connect issue_slots[5].iss_uop.dis_col_sel, slots_5.io.iss_uop.dis_col_sel connect issue_slots[5].iss_uop.iw_p3_bypass_hint, slots_5.io.iss_uop.iw_p3_bypass_hint connect issue_slots[5].iss_uop.iw_p2_bypass_hint, slots_5.io.iss_uop.iw_p2_bypass_hint connect issue_slots[5].iss_uop.iw_p1_bypass_hint, slots_5.io.iss_uop.iw_p1_bypass_hint connect issue_slots[5].iss_uop.iw_p2_speculative_child, slots_5.io.iss_uop.iw_p2_speculative_child connect issue_slots[5].iss_uop.iw_p1_speculative_child, slots_5.io.iss_uop.iw_p1_speculative_child connect issue_slots[5].iss_uop.iw_issued_partial_dgen, slots_5.io.iss_uop.iw_issued_partial_dgen connect issue_slots[5].iss_uop.iw_issued_partial_agen, slots_5.io.iss_uop.iw_issued_partial_agen connect issue_slots[5].iss_uop.iw_issued, slots_5.io.iss_uop.iw_issued connect issue_slots[5].iss_uop.fu_code[0], slots_5.io.iss_uop.fu_code[0] connect issue_slots[5].iss_uop.fu_code[1], slots_5.io.iss_uop.fu_code[1] connect issue_slots[5].iss_uop.fu_code[2], slots_5.io.iss_uop.fu_code[2] connect issue_slots[5].iss_uop.fu_code[3], slots_5.io.iss_uop.fu_code[3] connect issue_slots[5].iss_uop.fu_code[4], slots_5.io.iss_uop.fu_code[4] connect issue_slots[5].iss_uop.fu_code[5], slots_5.io.iss_uop.fu_code[5] connect issue_slots[5].iss_uop.fu_code[6], slots_5.io.iss_uop.fu_code[6] connect issue_slots[5].iss_uop.fu_code[7], slots_5.io.iss_uop.fu_code[7] connect issue_slots[5].iss_uop.fu_code[8], slots_5.io.iss_uop.fu_code[8] connect issue_slots[5].iss_uop.fu_code[9], slots_5.io.iss_uop.fu_code[9] connect issue_slots[5].iss_uop.iq_type[0], slots_5.io.iss_uop.iq_type[0] connect issue_slots[5].iss_uop.iq_type[1], slots_5.io.iss_uop.iq_type[1] connect issue_slots[5].iss_uop.iq_type[2], slots_5.io.iss_uop.iq_type[2] connect issue_slots[5].iss_uop.iq_type[3], slots_5.io.iss_uop.iq_type[3] connect issue_slots[5].iss_uop.debug_pc, slots_5.io.iss_uop.debug_pc connect issue_slots[5].iss_uop.is_rvc, slots_5.io.iss_uop.is_rvc connect issue_slots[5].iss_uop.debug_inst, slots_5.io.iss_uop.debug_inst connect issue_slots[5].iss_uop.inst, slots_5.io.iss_uop.inst connect slots_5.io.grant, issue_slots[5].grant connect issue_slots[5].request, slots_5.io.request connect issue_slots[5].will_be_valid, slots_5.io.will_be_valid connect issue_slots[5].valid, slots_5.io.valid connect slots_6.io.child_rebusys, issue_slots[6].child_rebusys connect slots_6.io.pred_wakeup_port.bits, issue_slots[6].pred_wakeup_port.bits connect slots_6.io.pred_wakeup_port.valid, issue_slots[6].pred_wakeup_port.valid connect slots_6.io.wakeup_ports[0].bits.rebusy, issue_slots[6].wakeup_ports[0].bits.rebusy connect slots_6.io.wakeup_ports[0].bits.speculative_mask, issue_slots[6].wakeup_ports[0].bits.speculative_mask connect slots_6.io.wakeup_ports[0].bits.bypassable, issue_slots[6].wakeup_ports[0].bits.bypassable connect slots_6.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[0].bits.uop.debug_tsrc connect slots_6.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[0].bits.uop.debug_fsrc connect slots_6.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_6.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[0].bits.uop.bp_debug_if connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_6.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_6.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[6].wakeup_ports[0].bits.uop.fp_typ connect slots_6.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[6].wakeup_ports[0].bits.uop.fp_rm connect slots_6.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[6].wakeup_ports[0].bits.uop.fp_val connect slots_6.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[6].wakeup_ports[0].bits.uop.fcn_op connect slots_6.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[0].bits.uop.fcn_dw connect slots_6.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[6].wakeup_ports[0].bits.uop.frs3_en connect slots_6.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_6.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_6.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[0].bits.uop.dst_rtype connect slots_6.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[6].wakeup_ports[0].bits.uop.lrs3 connect slots_6.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[6].wakeup_ports[0].bits.uop.lrs2 connect slots_6.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[6].wakeup_ports[0].bits.uop.lrs1 connect slots_6.io.wakeup_ports[0].bits.uop.ldst, issue_slots[6].wakeup_ports[0].bits.uop.ldst connect slots_6.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_6.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[0].bits.uop.csr_cmd connect slots_6.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[0].bits.uop.flush_on_commit connect slots_6.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[6].wakeup_ports[0].bits.uop.is_unique connect slots_6.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[6].wakeup_ports[0].bits.uop.uses_stq connect slots_6.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[0].bits.uop.uses_ldq connect slots_6.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[6].wakeup_ports[0].bits.uop.mem_signed connect slots_6.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[6].wakeup_ports[0].bits.uop.mem_size connect slots_6.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[0].bits.uop.mem_cmd connect slots_6.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[6].wakeup_ports[0].bits.uop.exc_cause connect slots_6.io.wakeup_ports[0].bits.uop.exception, issue_slots[6].wakeup_ports[0].bits.uop.exception connect slots_6.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[0].bits.uop.stale_pdst connect slots_6.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[0].bits.uop.ppred_busy connect slots_6.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs3_busy connect slots_6.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs2_busy connect slots_6.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[0].bits.uop.prs1_busy connect slots_6.io.wakeup_ports[0].bits.uop.ppred, issue_slots[6].wakeup_ports[0].bits.uop.ppred connect slots_6.io.wakeup_ports[0].bits.uop.prs3, issue_slots[6].wakeup_ports[0].bits.uop.prs3 connect slots_6.io.wakeup_ports[0].bits.uop.prs2, issue_slots[6].wakeup_ports[0].bits.uop.prs2 connect slots_6.io.wakeup_ports[0].bits.uop.prs1, issue_slots[6].wakeup_ports[0].bits.uop.prs1 connect slots_6.io.wakeup_ports[0].bits.uop.pdst, issue_slots[6].wakeup_ports[0].bits.uop.pdst connect slots_6.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[0].bits.uop.rxq_idx connect slots_6.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[6].wakeup_ports[0].bits.uop.stq_idx connect slots_6.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[0].bits.uop.ldq_idx connect slots_6.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[6].wakeup_ports[0].bits.uop.rob_idx connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_6.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_6.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[6].wakeup_ports[0].bits.uop.op2_sel connect slots_6.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[6].wakeup_ports[0].bits.uop.op1_sel connect slots_6.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[6].wakeup_ports[0].bits.uop.imm_packed connect slots_6.io.wakeup_ports[0].bits.uop.pimm, issue_slots[6].wakeup_ports[0].bits.uop.pimm connect slots_6.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[6].wakeup_ports[0].bits.uop.imm_sel connect slots_6.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[6].wakeup_ports[0].bits.uop.imm_rename connect slots_6.io.wakeup_ports[0].bits.uop.taken, issue_slots[6].wakeup_ports[0].bits.uop.taken connect slots_6.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[6].wakeup_ports[0].bits.uop.pc_lob connect slots_6.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[6].wakeup_ports[0].bits.uop.edge_inst connect slots_6.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[0].bits.uop.ftq_idx connect slots_6.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[6].wakeup_ports[0].bits.uop.is_mov connect slots_6.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[6].wakeup_ports[0].bits.uop.is_rocc connect slots_6.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_6.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[6].wakeup_ports[0].bits.uop.is_eret connect slots_6.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[6].wakeup_ports[0].bits.uop.is_amo connect slots_6.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[6].wakeup_ports[0].bits.uop.is_sfence connect slots_6.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[6].wakeup_ports[0].bits.uop.is_fencei connect slots_6.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[6].wakeup_ports[0].bits.uop.is_fence connect slots_6.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[6].wakeup_ports[0].bits.uop.is_sfb connect slots_6.io.wakeup_ports[0].bits.uop.br_type, issue_slots[6].wakeup_ports[0].bits.uop.br_type connect slots_6.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[6].wakeup_ports[0].bits.uop.br_tag connect slots_6.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[6].wakeup_ports[0].bits.uop.br_mask connect slots_6.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[0].bits.uop.dis_col_sel connect slots_6.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_6.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_6.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_6.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_6.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_6.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[6].wakeup_ports[0].bits.uop.iw_issued connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[0] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[1] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[2] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[3] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[4] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[5] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[6] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[7] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[8] connect slots_6.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[0].bits.uop.fu_code[9] connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[0] connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[1] connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[2] connect slots_6.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[0].bits.uop.iq_type[3] connect slots_6.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[6].wakeup_ports[0].bits.uop.debug_pc connect slots_6.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[6].wakeup_ports[0].bits.uop.is_rvc connect slots_6.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[6].wakeup_ports[0].bits.uop.debug_inst connect slots_6.io.wakeup_ports[0].bits.uop.inst, issue_slots[6].wakeup_ports[0].bits.uop.inst connect slots_6.io.wakeup_ports[0].valid, issue_slots[6].wakeup_ports[0].valid connect slots_6.io.wakeup_ports[1].bits.rebusy, issue_slots[6].wakeup_ports[1].bits.rebusy connect slots_6.io.wakeup_ports[1].bits.speculative_mask, issue_slots[6].wakeup_ports[1].bits.speculative_mask connect slots_6.io.wakeup_ports[1].bits.bypassable, issue_slots[6].wakeup_ports[1].bits.bypassable connect slots_6.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[6].wakeup_ports[1].bits.uop.debug_tsrc connect slots_6.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[6].wakeup_ports[1].bits.uop.debug_fsrc connect slots_6.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[6].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_6.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[6].wakeup_ports[1].bits.uop.bp_debug_if connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_6.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[6].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_6.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[6].wakeup_ports[1].bits.uop.fp_typ connect slots_6.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[6].wakeup_ports[1].bits.uop.fp_rm connect slots_6.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[6].wakeup_ports[1].bits.uop.fp_val connect slots_6.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[6].wakeup_ports[1].bits.uop.fcn_op connect slots_6.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[6].wakeup_ports[1].bits.uop.fcn_dw connect slots_6.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[6].wakeup_ports[1].bits.uop.frs3_en connect slots_6.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[6].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_6.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[6].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_6.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[6].wakeup_ports[1].bits.uop.dst_rtype connect slots_6.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[6].wakeup_ports[1].bits.uop.lrs3 connect slots_6.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[6].wakeup_ports[1].bits.uop.lrs2 connect slots_6.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[6].wakeup_ports[1].bits.uop.lrs1 connect slots_6.io.wakeup_ports[1].bits.uop.ldst, issue_slots[6].wakeup_ports[1].bits.uop.ldst connect slots_6.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[6].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_6.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[6].wakeup_ports[1].bits.uop.csr_cmd connect slots_6.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[6].wakeup_ports[1].bits.uop.flush_on_commit connect slots_6.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[6].wakeup_ports[1].bits.uop.is_unique connect slots_6.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[6].wakeup_ports[1].bits.uop.uses_stq connect slots_6.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[6].wakeup_ports[1].bits.uop.uses_ldq connect slots_6.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[6].wakeup_ports[1].bits.uop.mem_signed connect slots_6.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[6].wakeup_ports[1].bits.uop.mem_size connect slots_6.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[6].wakeup_ports[1].bits.uop.mem_cmd connect slots_6.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[6].wakeup_ports[1].bits.uop.exc_cause connect slots_6.io.wakeup_ports[1].bits.uop.exception, issue_slots[6].wakeup_ports[1].bits.uop.exception connect slots_6.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[6].wakeup_ports[1].bits.uop.stale_pdst connect slots_6.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[6].wakeup_ports[1].bits.uop.ppred_busy connect slots_6.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs3_busy connect slots_6.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs2_busy connect slots_6.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[6].wakeup_ports[1].bits.uop.prs1_busy connect slots_6.io.wakeup_ports[1].bits.uop.ppred, issue_slots[6].wakeup_ports[1].bits.uop.ppred connect slots_6.io.wakeup_ports[1].bits.uop.prs3, issue_slots[6].wakeup_ports[1].bits.uop.prs3 connect slots_6.io.wakeup_ports[1].bits.uop.prs2, issue_slots[6].wakeup_ports[1].bits.uop.prs2 connect slots_6.io.wakeup_ports[1].bits.uop.prs1, issue_slots[6].wakeup_ports[1].bits.uop.prs1 connect slots_6.io.wakeup_ports[1].bits.uop.pdst, issue_slots[6].wakeup_ports[1].bits.uop.pdst connect slots_6.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[6].wakeup_ports[1].bits.uop.rxq_idx connect slots_6.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[6].wakeup_ports[1].bits.uop.stq_idx connect slots_6.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[6].wakeup_ports[1].bits.uop.ldq_idx connect slots_6.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[6].wakeup_ports[1].bits.uop.rob_idx connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_6.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_6.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[6].wakeup_ports[1].bits.uop.op2_sel connect slots_6.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[6].wakeup_ports[1].bits.uop.op1_sel connect slots_6.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[6].wakeup_ports[1].bits.uop.imm_packed connect slots_6.io.wakeup_ports[1].bits.uop.pimm, issue_slots[6].wakeup_ports[1].bits.uop.pimm connect slots_6.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[6].wakeup_ports[1].bits.uop.imm_sel connect slots_6.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[6].wakeup_ports[1].bits.uop.imm_rename connect slots_6.io.wakeup_ports[1].bits.uop.taken, issue_slots[6].wakeup_ports[1].bits.uop.taken connect slots_6.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[6].wakeup_ports[1].bits.uop.pc_lob connect slots_6.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[6].wakeup_ports[1].bits.uop.edge_inst connect slots_6.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[6].wakeup_ports[1].bits.uop.ftq_idx connect slots_6.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[6].wakeup_ports[1].bits.uop.is_mov connect slots_6.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[6].wakeup_ports[1].bits.uop.is_rocc connect slots_6.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[6].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_6.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[6].wakeup_ports[1].bits.uop.is_eret connect slots_6.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[6].wakeup_ports[1].bits.uop.is_amo connect slots_6.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[6].wakeup_ports[1].bits.uop.is_sfence connect slots_6.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[6].wakeup_ports[1].bits.uop.is_fencei connect slots_6.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[6].wakeup_ports[1].bits.uop.is_fence connect slots_6.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[6].wakeup_ports[1].bits.uop.is_sfb connect slots_6.io.wakeup_ports[1].bits.uop.br_type, issue_slots[6].wakeup_ports[1].bits.uop.br_type connect slots_6.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[6].wakeup_ports[1].bits.uop.br_tag connect slots_6.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[6].wakeup_ports[1].bits.uop.br_mask connect slots_6.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[6].wakeup_ports[1].bits.uop.dis_col_sel connect slots_6.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_6.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_6.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_6.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_6.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_6.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[6].wakeup_ports[1].bits.uop.iw_issued connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[0] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[1] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[2] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[3] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[4] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[5] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[6] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[7] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[8] connect slots_6.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[6].wakeup_ports[1].bits.uop.fu_code[9] connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[0] connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[1] connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[2] connect slots_6.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[6].wakeup_ports[1].bits.uop.iq_type[3] connect slots_6.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[6].wakeup_ports[1].bits.uop.debug_pc connect slots_6.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[6].wakeup_ports[1].bits.uop.is_rvc connect slots_6.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[6].wakeup_ports[1].bits.uop.debug_inst connect slots_6.io.wakeup_ports[1].bits.uop.inst, issue_slots[6].wakeup_ports[1].bits.uop.inst connect slots_6.io.wakeup_ports[1].valid, issue_slots[6].wakeup_ports[1].valid connect slots_6.io.squash_grant, issue_slots[6].squash_grant connect slots_6.io.clear, issue_slots[6].clear connect slots_6.io.kill, issue_slots[6].kill connect slots_6.io.brupdate.b2.target_offset, issue_slots[6].brupdate.b2.target_offset connect slots_6.io.brupdate.b2.jalr_target, issue_slots[6].brupdate.b2.jalr_target connect slots_6.io.brupdate.b2.pc_sel, issue_slots[6].brupdate.b2.pc_sel connect slots_6.io.brupdate.b2.cfi_type, issue_slots[6].brupdate.b2.cfi_type connect slots_6.io.brupdate.b2.taken, issue_slots[6].brupdate.b2.taken connect slots_6.io.brupdate.b2.mispredict, issue_slots[6].brupdate.b2.mispredict connect slots_6.io.brupdate.b2.uop.debug_tsrc, issue_slots[6].brupdate.b2.uop.debug_tsrc connect slots_6.io.brupdate.b2.uop.debug_fsrc, issue_slots[6].brupdate.b2.uop.debug_fsrc connect slots_6.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[6].brupdate.b2.uop.bp_xcpt_if connect slots_6.io.brupdate.b2.uop.bp_debug_if, issue_slots[6].brupdate.b2.uop.bp_debug_if connect slots_6.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[6].brupdate.b2.uop.xcpt_ma_if connect slots_6.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[6].brupdate.b2.uop.xcpt_ae_if connect slots_6.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[6].brupdate.b2.uop.xcpt_pf_if connect slots_6.io.brupdate.b2.uop.fp_typ, issue_slots[6].brupdate.b2.uop.fp_typ connect slots_6.io.brupdate.b2.uop.fp_rm, issue_slots[6].brupdate.b2.uop.fp_rm connect slots_6.io.brupdate.b2.uop.fp_val, issue_slots[6].brupdate.b2.uop.fp_val connect slots_6.io.brupdate.b2.uop.fcn_op, issue_slots[6].brupdate.b2.uop.fcn_op connect slots_6.io.brupdate.b2.uop.fcn_dw, issue_slots[6].brupdate.b2.uop.fcn_dw connect slots_6.io.brupdate.b2.uop.frs3_en, issue_slots[6].brupdate.b2.uop.frs3_en connect slots_6.io.brupdate.b2.uop.lrs2_rtype, issue_slots[6].brupdate.b2.uop.lrs2_rtype connect slots_6.io.brupdate.b2.uop.lrs1_rtype, issue_slots[6].brupdate.b2.uop.lrs1_rtype connect slots_6.io.brupdate.b2.uop.dst_rtype, issue_slots[6].brupdate.b2.uop.dst_rtype connect slots_6.io.brupdate.b2.uop.lrs3, issue_slots[6].brupdate.b2.uop.lrs3 connect slots_6.io.brupdate.b2.uop.lrs2, issue_slots[6].brupdate.b2.uop.lrs2 connect slots_6.io.brupdate.b2.uop.lrs1, issue_slots[6].brupdate.b2.uop.lrs1 connect slots_6.io.brupdate.b2.uop.ldst, issue_slots[6].brupdate.b2.uop.ldst connect slots_6.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[6].brupdate.b2.uop.ldst_is_rs1 connect slots_6.io.brupdate.b2.uop.csr_cmd, issue_slots[6].brupdate.b2.uop.csr_cmd connect slots_6.io.brupdate.b2.uop.flush_on_commit, issue_slots[6].brupdate.b2.uop.flush_on_commit connect slots_6.io.brupdate.b2.uop.is_unique, issue_slots[6].brupdate.b2.uop.is_unique connect slots_6.io.brupdate.b2.uop.uses_stq, issue_slots[6].brupdate.b2.uop.uses_stq connect slots_6.io.brupdate.b2.uop.uses_ldq, issue_slots[6].brupdate.b2.uop.uses_ldq connect slots_6.io.brupdate.b2.uop.mem_signed, issue_slots[6].brupdate.b2.uop.mem_signed connect slots_6.io.brupdate.b2.uop.mem_size, issue_slots[6].brupdate.b2.uop.mem_size connect slots_6.io.brupdate.b2.uop.mem_cmd, issue_slots[6].brupdate.b2.uop.mem_cmd connect slots_6.io.brupdate.b2.uop.exc_cause, issue_slots[6].brupdate.b2.uop.exc_cause connect slots_6.io.brupdate.b2.uop.exception, issue_slots[6].brupdate.b2.uop.exception connect slots_6.io.brupdate.b2.uop.stale_pdst, issue_slots[6].brupdate.b2.uop.stale_pdst connect slots_6.io.brupdate.b2.uop.ppred_busy, issue_slots[6].brupdate.b2.uop.ppred_busy connect slots_6.io.brupdate.b2.uop.prs3_busy, issue_slots[6].brupdate.b2.uop.prs3_busy connect slots_6.io.brupdate.b2.uop.prs2_busy, issue_slots[6].brupdate.b2.uop.prs2_busy connect slots_6.io.brupdate.b2.uop.prs1_busy, issue_slots[6].brupdate.b2.uop.prs1_busy connect slots_6.io.brupdate.b2.uop.ppred, issue_slots[6].brupdate.b2.uop.ppred connect slots_6.io.brupdate.b2.uop.prs3, issue_slots[6].brupdate.b2.uop.prs3 connect slots_6.io.brupdate.b2.uop.prs2, issue_slots[6].brupdate.b2.uop.prs2 connect slots_6.io.brupdate.b2.uop.prs1, issue_slots[6].brupdate.b2.uop.prs1 connect slots_6.io.brupdate.b2.uop.pdst, issue_slots[6].brupdate.b2.uop.pdst connect slots_6.io.brupdate.b2.uop.rxq_idx, issue_slots[6].brupdate.b2.uop.rxq_idx connect slots_6.io.brupdate.b2.uop.stq_idx, issue_slots[6].brupdate.b2.uop.stq_idx connect slots_6.io.brupdate.b2.uop.ldq_idx, issue_slots[6].brupdate.b2.uop.ldq_idx connect slots_6.io.brupdate.b2.uop.rob_idx, issue_slots[6].brupdate.b2.uop.rob_idx connect slots_6.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[6].brupdate.b2.uop.fp_ctrl.vec connect slots_6.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[6].brupdate.b2.uop.fp_ctrl.wflags connect slots_6.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[6].brupdate.b2.uop.fp_ctrl.sqrt connect slots_6.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[6].brupdate.b2.uop.fp_ctrl.div connect slots_6.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[6].brupdate.b2.uop.fp_ctrl.fma connect slots_6.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[6].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_6.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[6].brupdate.b2.uop.fp_ctrl.toint connect slots_6.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[6].brupdate.b2.uop.fp_ctrl.fromint connect slots_6.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_6.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_6.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[6].brupdate.b2.uop.fp_ctrl.swap23 connect slots_6.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[6].brupdate.b2.uop.fp_ctrl.swap12 connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren3 connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren2 connect slots_6.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[6].brupdate.b2.uop.fp_ctrl.ren1 connect slots_6.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[6].brupdate.b2.uop.fp_ctrl.wen connect slots_6.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[6].brupdate.b2.uop.fp_ctrl.ldst connect slots_6.io.brupdate.b2.uop.op2_sel, issue_slots[6].brupdate.b2.uop.op2_sel connect slots_6.io.brupdate.b2.uop.op1_sel, issue_slots[6].brupdate.b2.uop.op1_sel connect slots_6.io.brupdate.b2.uop.imm_packed, issue_slots[6].brupdate.b2.uop.imm_packed connect slots_6.io.brupdate.b2.uop.pimm, issue_slots[6].brupdate.b2.uop.pimm connect slots_6.io.brupdate.b2.uop.imm_sel, issue_slots[6].brupdate.b2.uop.imm_sel connect slots_6.io.brupdate.b2.uop.imm_rename, issue_slots[6].brupdate.b2.uop.imm_rename connect slots_6.io.brupdate.b2.uop.taken, issue_slots[6].brupdate.b2.uop.taken connect slots_6.io.brupdate.b2.uop.pc_lob, issue_slots[6].brupdate.b2.uop.pc_lob connect slots_6.io.brupdate.b2.uop.edge_inst, issue_slots[6].brupdate.b2.uop.edge_inst connect slots_6.io.brupdate.b2.uop.ftq_idx, issue_slots[6].brupdate.b2.uop.ftq_idx connect slots_6.io.brupdate.b2.uop.is_mov, issue_slots[6].brupdate.b2.uop.is_mov connect slots_6.io.brupdate.b2.uop.is_rocc, issue_slots[6].brupdate.b2.uop.is_rocc connect slots_6.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[6].brupdate.b2.uop.is_sys_pc2epc connect slots_6.io.brupdate.b2.uop.is_eret, issue_slots[6].brupdate.b2.uop.is_eret connect slots_6.io.brupdate.b2.uop.is_amo, issue_slots[6].brupdate.b2.uop.is_amo connect slots_6.io.brupdate.b2.uop.is_sfence, issue_slots[6].brupdate.b2.uop.is_sfence connect slots_6.io.brupdate.b2.uop.is_fencei, issue_slots[6].brupdate.b2.uop.is_fencei connect slots_6.io.brupdate.b2.uop.is_fence, issue_slots[6].brupdate.b2.uop.is_fence connect slots_6.io.brupdate.b2.uop.is_sfb, issue_slots[6].brupdate.b2.uop.is_sfb connect slots_6.io.brupdate.b2.uop.br_type, issue_slots[6].brupdate.b2.uop.br_type connect slots_6.io.brupdate.b2.uop.br_tag, issue_slots[6].brupdate.b2.uop.br_tag connect slots_6.io.brupdate.b2.uop.br_mask, issue_slots[6].brupdate.b2.uop.br_mask connect slots_6.io.brupdate.b2.uop.dis_col_sel, issue_slots[6].brupdate.b2.uop.dis_col_sel connect slots_6.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p3_bypass_hint connect slots_6.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p2_bypass_hint connect slots_6.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[6].brupdate.b2.uop.iw_p1_bypass_hint connect slots_6.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[6].brupdate.b2.uop.iw_p2_speculative_child connect slots_6.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[6].brupdate.b2.uop.iw_p1_speculative_child connect slots_6.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[6].brupdate.b2.uop.iw_issued_partial_dgen connect slots_6.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[6].brupdate.b2.uop.iw_issued_partial_agen connect slots_6.io.brupdate.b2.uop.iw_issued, issue_slots[6].brupdate.b2.uop.iw_issued connect slots_6.io.brupdate.b2.uop.fu_code[0], issue_slots[6].brupdate.b2.uop.fu_code[0] connect slots_6.io.brupdate.b2.uop.fu_code[1], issue_slots[6].brupdate.b2.uop.fu_code[1] connect slots_6.io.brupdate.b2.uop.fu_code[2], issue_slots[6].brupdate.b2.uop.fu_code[2] connect slots_6.io.brupdate.b2.uop.fu_code[3], issue_slots[6].brupdate.b2.uop.fu_code[3] connect slots_6.io.brupdate.b2.uop.fu_code[4], issue_slots[6].brupdate.b2.uop.fu_code[4] connect slots_6.io.brupdate.b2.uop.fu_code[5], issue_slots[6].brupdate.b2.uop.fu_code[5] connect slots_6.io.brupdate.b2.uop.fu_code[6], issue_slots[6].brupdate.b2.uop.fu_code[6] connect slots_6.io.brupdate.b2.uop.fu_code[7], issue_slots[6].brupdate.b2.uop.fu_code[7] connect slots_6.io.brupdate.b2.uop.fu_code[8], issue_slots[6].brupdate.b2.uop.fu_code[8] connect slots_6.io.brupdate.b2.uop.fu_code[9], issue_slots[6].brupdate.b2.uop.fu_code[9] connect slots_6.io.brupdate.b2.uop.iq_type[0], issue_slots[6].brupdate.b2.uop.iq_type[0] connect slots_6.io.brupdate.b2.uop.iq_type[1], issue_slots[6].brupdate.b2.uop.iq_type[1] connect slots_6.io.brupdate.b2.uop.iq_type[2], issue_slots[6].brupdate.b2.uop.iq_type[2] connect slots_6.io.brupdate.b2.uop.iq_type[3], issue_slots[6].brupdate.b2.uop.iq_type[3] connect slots_6.io.brupdate.b2.uop.debug_pc, issue_slots[6].brupdate.b2.uop.debug_pc connect slots_6.io.brupdate.b2.uop.is_rvc, issue_slots[6].brupdate.b2.uop.is_rvc connect slots_6.io.brupdate.b2.uop.debug_inst, issue_slots[6].brupdate.b2.uop.debug_inst connect slots_6.io.brupdate.b2.uop.inst, issue_slots[6].brupdate.b2.uop.inst connect slots_6.io.brupdate.b1.mispredict_mask, issue_slots[6].brupdate.b1.mispredict_mask connect slots_6.io.brupdate.b1.resolve_mask, issue_slots[6].brupdate.b1.resolve_mask connect issue_slots[6].out_uop.debug_tsrc, slots_6.io.out_uop.debug_tsrc connect issue_slots[6].out_uop.debug_fsrc, slots_6.io.out_uop.debug_fsrc connect issue_slots[6].out_uop.bp_xcpt_if, slots_6.io.out_uop.bp_xcpt_if connect issue_slots[6].out_uop.bp_debug_if, slots_6.io.out_uop.bp_debug_if connect issue_slots[6].out_uop.xcpt_ma_if, slots_6.io.out_uop.xcpt_ma_if connect issue_slots[6].out_uop.xcpt_ae_if, slots_6.io.out_uop.xcpt_ae_if connect issue_slots[6].out_uop.xcpt_pf_if, slots_6.io.out_uop.xcpt_pf_if connect issue_slots[6].out_uop.fp_typ, slots_6.io.out_uop.fp_typ connect issue_slots[6].out_uop.fp_rm, slots_6.io.out_uop.fp_rm connect issue_slots[6].out_uop.fp_val, slots_6.io.out_uop.fp_val connect issue_slots[6].out_uop.fcn_op, slots_6.io.out_uop.fcn_op connect issue_slots[6].out_uop.fcn_dw, slots_6.io.out_uop.fcn_dw connect issue_slots[6].out_uop.frs3_en, slots_6.io.out_uop.frs3_en connect issue_slots[6].out_uop.lrs2_rtype, slots_6.io.out_uop.lrs2_rtype connect issue_slots[6].out_uop.lrs1_rtype, slots_6.io.out_uop.lrs1_rtype connect issue_slots[6].out_uop.dst_rtype, slots_6.io.out_uop.dst_rtype connect issue_slots[6].out_uop.lrs3, slots_6.io.out_uop.lrs3 connect issue_slots[6].out_uop.lrs2, slots_6.io.out_uop.lrs2 connect issue_slots[6].out_uop.lrs1, slots_6.io.out_uop.lrs1 connect issue_slots[6].out_uop.ldst, slots_6.io.out_uop.ldst connect issue_slots[6].out_uop.ldst_is_rs1, slots_6.io.out_uop.ldst_is_rs1 connect issue_slots[6].out_uop.csr_cmd, slots_6.io.out_uop.csr_cmd connect issue_slots[6].out_uop.flush_on_commit, slots_6.io.out_uop.flush_on_commit connect issue_slots[6].out_uop.is_unique, slots_6.io.out_uop.is_unique connect issue_slots[6].out_uop.uses_stq, slots_6.io.out_uop.uses_stq connect issue_slots[6].out_uop.uses_ldq, slots_6.io.out_uop.uses_ldq connect issue_slots[6].out_uop.mem_signed, slots_6.io.out_uop.mem_signed connect issue_slots[6].out_uop.mem_size, slots_6.io.out_uop.mem_size connect issue_slots[6].out_uop.mem_cmd, slots_6.io.out_uop.mem_cmd connect issue_slots[6].out_uop.exc_cause, slots_6.io.out_uop.exc_cause connect issue_slots[6].out_uop.exception, slots_6.io.out_uop.exception connect issue_slots[6].out_uop.stale_pdst, slots_6.io.out_uop.stale_pdst connect issue_slots[6].out_uop.ppred_busy, slots_6.io.out_uop.ppred_busy connect issue_slots[6].out_uop.prs3_busy, slots_6.io.out_uop.prs3_busy connect issue_slots[6].out_uop.prs2_busy, slots_6.io.out_uop.prs2_busy connect issue_slots[6].out_uop.prs1_busy, slots_6.io.out_uop.prs1_busy connect issue_slots[6].out_uop.ppred, slots_6.io.out_uop.ppred connect issue_slots[6].out_uop.prs3, slots_6.io.out_uop.prs3 connect issue_slots[6].out_uop.prs2, slots_6.io.out_uop.prs2 connect issue_slots[6].out_uop.prs1, slots_6.io.out_uop.prs1 connect issue_slots[6].out_uop.pdst, slots_6.io.out_uop.pdst connect issue_slots[6].out_uop.rxq_idx, slots_6.io.out_uop.rxq_idx connect issue_slots[6].out_uop.stq_idx, slots_6.io.out_uop.stq_idx connect issue_slots[6].out_uop.ldq_idx, slots_6.io.out_uop.ldq_idx connect issue_slots[6].out_uop.rob_idx, slots_6.io.out_uop.rob_idx connect issue_slots[6].out_uop.fp_ctrl.vec, slots_6.io.out_uop.fp_ctrl.vec connect issue_slots[6].out_uop.fp_ctrl.wflags, slots_6.io.out_uop.fp_ctrl.wflags connect issue_slots[6].out_uop.fp_ctrl.sqrt, slots_6.io.out_uop.fp_ctrl.sqrt connect issue_slots[6].out_uop.fp_ctrl.div, slots_6.io.out_uop.fp_ctrl.div connect issue_slots[6].out_uop.fp_ctrl.fma, slots_6.io.out_uop.fp_ctrl.fma connect issue_slots[6].out_uop.fp_ctrl.fastpipe, slots_6.io.out_uop.fp_ctrl.fastpipe connect issue_slots[6].out_uop.fp_ctrl.toint, slots_6.io.out_uop.fp_ctrl.toint connect issue_slots[6].out_uop.fp_ctrl.fromint, slots_6.io.out_uop.fp_ctrl.fromint connect issue_slots[6].out_uop.fp_ctrl.typeTagOut, slots_6.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[6].out_uop.fp_ctrl.typeTagIn, slots_6.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[6].out_uop.fp_ctrl.swap23, slots_6.io.out_uop.fp_ctrl.swap23 connect issue_slots[6].out_uop.fp_ctrl.swap12, slots_6.io.out_uop.fp_ctrl.swap12 connect issue_slots[6].out_uop.fp_ctrl.ren3, slots_6.io.out_uop.fp_ctrl.ren3 connect issue_slots[6].out_uop.fp_ctrl.ren2, slots_6.io.out_uop.fp_ctrl.ren2 connect issue_slots[6].out_uop.fp_ctrl.ren1, slots_6.io.out_uop.fp_ctrl.ren1 connect issue_slots[6].out_uop.fp_ctrl.wen, slots_6.io.out_uop.fp_ctrl.wen connect issue_slots[6].out_uop.fp_ctrl.ldst, slots_6.io.out_uop.fp_ctrl.ldst connect issue_slots[6].out_uop.op2_sel, slots_6.io.out_uop.op2_sel connect issue_slots[6].out_uop.op1_sel, slots_6.io.out_uop.op1_sel connect issue_slots[6].out_uop.imm_packed, slots_6.io.out_uop.imm_packed connect issue_slots[6].out_uop.pimm, slots_6.io.out_uop.pimm connect issue_slots[6].out_uop.imm_sel, slots_6.io.out_uop.imm_sel connect issue_slots[6].out_uop.imm_rename, slots_6.io.out_uop.imm_rename connect issue_slots[6].out_uop.taken, slots_6.io.out_uop.taken connect issue_slots[6].out_uop.pc_lob, slots_6.io.out_uop.pc_lob connect issue_slots[6].out_uop.edge_inst, slots_6.io.out_uop.edge_inst connect issue_slots[6].out_uop.ftq_idx, slots_6.io.out_uop.ftq_idx connect issue_slots[6].out_uop.is_mov, slots_6.io.out_uop.is_mov connect issue_slots[6].out_uop.is_rocc, slots_6.io.out_uop.is_rocc connect issue_slots[6].out_uop.is_sys_pc2epc, slots_6.io.out_uop.is_sys_pc2epc connect issue_slots[6].out_uop.is_eret, slots_6.io.out_uop.is_eret connect issue_slots[6].out_uop.is_amo, slots_6.io.out_uop.is_amo connect issue_slots[6].out_uop.is_sfence, slots_6.io.out_uop.is_sfence connect issue_slots[6].out_uop.is_fencei, slots_6.io.out_uop.is_fencei connect issue_slots[6].out_uop.is_fence, slots_6.io.out_uop.is_fence connect issue_slots[6].out_uop.is_sfb, slots_6.io.out_uop.is_sfb connect issue_slots[6].out_uop.br_type, slots_6.io.out_uop.br_type connect issue_slots[6].out_uop.br_tag, slots_6.io.out_uop.br_tag connect issue_slots[6].out_uop.br_mask, slots_6.io.out_uop.br_mask connect issue_slots[6].out_uop.dis_col_sel, slots_6.io.out_uop.dis_col_sel connect issue_slots[6].out_uop.iw_p3_bypass_hint, slots_6.io.out_uop.iw_p3_bypass_hint connect issue_slots[6].out_uop.iw_p2_bypass_hint, slots_6.io.out_uop.iw_p2_bypass_hint connect issue_slots[6].out_uop.iw_p1_bypass_hint, slots_6.io.out_uop.iw_p1_bypass_hint connect issue_slots[6].out_uop.iw_p2_speculative_child, slots_6.io.out_uop.iw_p2_speculative_child connect issue_slots[6].out_uop.iw_p1_speculative_child, slots_6.io.out_uop.iw_p1_speculative_child connect issue_slots[6].out_uop.iw_issued_partial_dgen, slots_6.io.out_uop.iw_issued_partial_dgen connect issue_slots[6].out_uop.iw_issued_partial_agen, slots_6.io.out_uop.iw_issued_partial_agen connect issue_slots[6].out_uop.iw_issued, slots_6.io.out_uop.iw_issued connect issue_slots[6].out_uop.fu_code[0], slots_6.io.out_uop.fu_code[0] connect issue_slots[6].out_uop.fu_code[1], slots_6.io.out_uop.fu_code[1] connect issue_slots[6].out_uop.fu_code[2], slots_6.io.out_uop.fu_code[2] connect issue_slots[6].out_uop.fu_code[3], slots_6.io.out_uop.fu_code[3] connect issue_slots[6].out_uop.fu_code[4], slots_6.io.out_uop.fu_code[4] connect issue_slots[6].out_uop.fu_code[5], slots_6.io.out_uop.fu_code[5] connect issue_slots[6].out_uop.fu_code[6], slots_6.io.out_uop.fu_code[6] connect issue_slots[6].out_uop.fu_code[7], slots_6.io.out_uop.fu_code[7] connect issue_slots[6].out_uop.fu_code[8], slots_6.io.out_uop.fu_code[8] connect issue_slots[6].out_uop.fu_code[9], slots_6.io.out_uop.fu_code[9] connect issue_slots[6].out_uop.iq_type[0], slots_6.io.out_uop.iq_type[0] connect issue_slots[6].out_uop.iq_type[1], slots_6.io.out_uop.iq_type[1] connect issue_slots[6].out_uop.iq_type[2], slots_6.io.out_uop.iq_type[2] connect issue_slots[6].out_uop.iq_type[3], slots_6.io.out_uop.iq_type[3] connect issue_slots[6].out_uop.debug_pc, slots_6.io.out_uop.debug_pc connect issue_slots[6].out_uop.is_rvc, slots_6.io.out_uop.is_rvc connect issue_slots[6].out_uop.debug_inst, slots_6.io.out_uop.debug_inst connect issue_slots[6].out_uop.inst, slots_6.io.out_uop.inst connect slots_6.io.in_uop.bits.debug_tsrc, issue_slots[6].in_uop.bits.debug_tsrc connect slots_6.io.in_uop.bits.debug_fsrc, issue_slots[6].in_uop.bits.debug_fsrc connect slots_6.io.in_uop.bits.bp_xcpt_if, issue_slots[6].in_uop.bits.bp_xcpt_if connect slots_6.io.in_uop.bits.bp_debug_if, issue_slots[6].in_uop.bits.bp_debug_if connect slots_6.io.in_uop.bits.xcpt_ma_if, issue_slots[6].in_uop.bits.xcpt_ma_if connect slots_6.io.in_uop.bits.xcpt_ae_if, issue_slots[6].in_uop.bits.xcpt_ae_if connect slots_6.io.in_uop.bits.xcpt_pf_if, issue_slots[6].in_uop.bits.xcpt_pf_if connect slots_6.io.in_uop.bits.fp_typ, issue_slots[6].in_uop.bits.fp_typ connect slots_6.io.in_uop.bits.fp_rm, issue_slots[6].in_uop.bits.fp_rm connect slots_6.io.in_uop.bits.fp_val, issue_slots[6].in_uop.bits.fp_val connect slots_6.io.in_uop.bits.fcn_op, issue_slots[6].in_uop.bits.fcn_op connect slots_6.io.in_uop.bits.fcn_dw, issue_slots[6].in_uop.bits.fcn_dw connect slots_6.io.in_uop.bits.frs3_en, issue_slots[6].in_uop.bits.frs3_en connect slots_6.io.in_uop.bits.lrs2_rtype, issue_slots[6].in_uop.bits.lrs2_rtype connect slots_6.io.in_uop.bits.lrs1_rtype, issue_slots[6].in_uop.bits.lrs1_rtype connect slots_6.io.in_uop.bits.dst_rtype, issue_slots[6].in_uop.bits.dst_rtype connect slots_6.io.in_uop.bits.lrs3, issue_slots[6].in_uop.bits.lrs3 connect slots_6.io.in_uop.bits.lrs2, issue_slots[6].in_uop.bits.lrs2 connect slots_6.io.in_uop.bits.lrs1, issue_slots[6].in_uop.bits.lrs1 connect slots_6.io.in_uop.bits.ldst, issue_slots[6].in_uop.bits.ldst connect slots_6.io.in_uop.bits.ldst_is_rs1, issue_slots[6].in_uop.bits.ldst_is_rs1 connect slots_6.io.in_uop.bits.csr_cmd, issue_slots[6].in_uop.bits.csr_cmd connect slots_6.io.in_uop.bits.flush_on_commit, issue_slots[6].in_uop.bits.flush_on_commit connect slots_6.io.in_uop.bits.is_unique, issue_slots[6].in_uop.bits.is_unique connect slots_6.io.in_uop.bits.uses_stq, issue_slots[6].in_uop.bits.uses_stq connect slots_6.io.in_uop.bits.uses_ldq, issue_slots[6].in_uop.bits.uses_ldq connect slots_6.io.in_uop.bits.mem_signed, issue_slots[6].in_uop.bits.mem_signed connect slots_6.io.in_uop.bits.mem_size, issue_slots[6].in_uop.bits.mem_size connect slots_6.io.in_uop.bits.mem_cmd, issue_slots[6].in_uop.bits.mem_cmd connect slots_6.io.in_uop.bits.exc_cause, issue_slots[6].in_uop.bits.exc_cause connect slots_6.io.in_uop.bits.exception, issue_slots[6].in_uop.bits.exception connect slots_6.io.in_uop.bits.stale_pdst, issue_slots[6].in_uop.bits.stale_pdst connect slots_6.io.in_uop.bits.ppred_busy, issue_slots[6].in_uop.bits.ppred_busy connect slots_6.io.in_uop.bits.prs3_busy, issue_slots[6].in_uop.bits.prs3_busy connect slots_6.io.in_uop.bits.prs2_busy, issue_slots[6].in_uop.bits.prs2_busy connect slots_6.io.in_uop.bits.prs1_busy, issue_slots[6].in_uop.bits.prs1_busy connect slots_6.io.in_uop.bits.ppred, issue_slots[6].in_uop.bits.ppred connect slots_6.io.in_uop.bits.prs3, issue_slots[6].in_uop.bits.prs3 connect slots_6.io.in_uop.bits.prs2, issue_slots[6].in_uop.bits.prs2 connect slots_6.io.in_uop.bits.prs1, issue_slots[6].in_uop.bits.prs1 connect slots_6.io.in_uop.bits.pdst, issue_slots[6].in_uop.bits.pdst connect slots_6.io.in_uop.bits.rxq_idx, issue_slots[6].in_uop.bits.rxq_idx connect slots_6.io.in_uop.bits.stq_idx, issue_slots[6].in_uop.bits.stq_idx connect slots_6.io.in_uop.bits.ldq_idx, issue_slots[6].in_uop.bits.ldq_idx connect slots_6.io.in_uop.bits.rob_idx, issue_slots[6].in_uop.bits.rob_idx connect slots_6.io.in_uop.bits.fp_ctrl.vec, issue_slots[6].in_uop.bits.fp_ctrl.vec connect slots_6.io.in_uop.bits.fp_ctrl.wflags, issue_slots[6].in_uop.bits.fp_ctrl.wflags connect slots_6.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[6].in_uop.bits.fp_ctrl.sqrt connect slots_6.io.in_uop.bits.fp_ctrl.div, issue_slots[6].in_uop.bits.fp_ctrl.div connect slots_6.io.in_uop.bits.fp_ctrl.fma, issue_slots[6].in_uop.bits.fp_ctrl.fma connect slots_6.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].in_uop.bits.fp_ctrl.fastpipe connect slots_6.io.in_uop.bits.fp_ctrl.toint, issue_slots[6].in_uop.bits.fp_ctrl.toint connect slots_6.io.in_uop.bits.fp_ctrl.fromint, issue_slots[6].in_uop.bits.fp_ctrl.fromint connect slots_6.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut connect slots_6.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn connect slots_6.io.in_uop.bits.fp_ctrl.swap23, issue_slots[6].in_uop.bits.fp_ctrl.swap23 connect slots_6.io.in_uop.bits.fp_ctrl.swap12, issue_slots[6].in_uop.bits.fp_ctrl.swap12 connect slots_6.io.in_uop.bits.fp_ctrl.ren3, issue_slots[6].in_uop.bits.fp_ctrl.ren3 connect slots_6.io.in_uop.bits.fp_ctrl.ren2, issue_slots[6].in_uop.bits.fp_ctrl.ren2 connect slots_6.io.in_uop.bits.fp_ctrl.ren1, issue_slots[6].in_uop.bits.fp_ctrl.ren1 connect slots_6.io.in_uop.bits.fp_ctrl.wen, issue_slots[6].in_uop.bits.fp_ctrl.wen connect slots_6.io.in_uop.bits.fp_ctrl.ldst, issue_slots[6].in_uop.bits.fp_ctrl.ldst connect slots_6.io.in_uop.bits.op2_sel, issue_slots[6].in_uop.bits.op2_sel connect slots_6.io.in_uop.bits.op1_sel, issue_slots[6].in_uop.bits.op1_sel connect slots_6.io.in_uop.bits.imm_packed, issue_slots[6].in_uop.bits.imm_packed connect slots_6.io.in_uop.bits.pimm, issue_slots[6].in_uop.bits.pimm connect slots_6.io.in_uop.bits.imm_sel, issue_slots[6].in_uop.bits.imm_sel connect slots_6.io.in_uop.bits.imm_rename, issue_slots[6].in_uop.bits.imm_rename connect slots_6.io.in_uop.bits.taken, issue_slots[6].in_uop.bits.taken connect slots_6.io.in_uop.bits.pc_lob, issue_slots[6].in_uop.bits.pc_lob connect slots_6.io.in_uop.bits.edge_inst, issue_slots[6].in_uop.bits.edge_inst connect slots_6.io.in_uop.bits.ftq_idx, issue_slots[6].in_uop.bits.ftq_idx connect slots_6.io.in_uop.bits.is_mov, issue_slots[6].in_uop.bits.is_mov connect slots_6.io.in_uop.bits.is_rocc, issue_slots[6].in_uop.bits.is_rocc connect slots_6.io.in_uop.bits.is_sys_pc2epc, issue_slots[6].in_uop.bits.is_sys_pc2epc connect slots_6.io.in_uop.bits.is_eret, issue_slots[6].in_uop.bits.is_eret connect slots_6.io.in_uop.bits.is_amo, issue_slots[6].in_uop.bits.is_amo connect slots_6.io.in_uop.bits.is_sfence, issue_slots[6].in_uop.bits.is_sfence connect slots_6.io.in_uop.bits.is_fencei, issue_slots[6].in_uop.bits.is_fencei connect slots_6.io.in_uop.bits.is_fence, issue_slots[6].in_uop.bits.is_fence connect slots_6.io.in_uop.bits.is_sfb, issue_slots[6].in_uop.bits.is_sfb connect slots_6.io.in_uop.bits.br_type, issue_slots[6].in_uop.bits.br_type connect slots_6.io.in_uop.bits.br_tag, issue_slots[6].in_uop.bits.br_tag connect slots_6.io.in_uop.bits.br_mask, issue_slots[6].in_uop.bits.br_mask connect slots_6.io.in_uop.bits.dis_col_sel, issue_slots[6].in_uop.bits.dis_col_sel connect slots_6.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[6].in_uop.bits.iw_p3_bypass_hint connect slots_6.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[6].in_uop.bits.iw_p2_bypass_hint connect slots_6.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[6].in_uop.bits.iw_p1_bypass_hint connect slots_6.io.in_uop.bits.iw_p2_speculative_child, issue_slots[6].in_uop.bits.iw_p2_speculative_child connect slots_6.io.in_uop.bits.iw_p1_speculative_child, issue_slots[6].in_uop.bits.iw_p1_speculative_child connect slots_6.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[6].in_uop.bits.iw_issued_partial_dgen connect slots_6.io.in_uop.bits.iw_issued_partial_agen, issue_slots[6].in_uop.bits.iw_issued_partial_agen connect slots_6.io.in_uop.bits.iw_issued, issue_slots[6].in_uop.bits.iw_issued connect slots_6.io.in_uop.bits.fu_code[0], issue_slots[6].in_uop.bits.fu_code[0] connect slots_6.io.in_uop.bits.fu_code[1], issue_slots[6].in_uop.bits.fu_code[1] connect slots_6.io.in_uop.bits.fu_code[2], issue_slots[6].in_uop.bits.fu_code[2] connect slots_6.io.in_uop.bits.fu_code[3], issue_slots[6].in_uop.bits.fu_code[3] connect slots_6.io.in_uop.bits.fu_code[4], issue_slots[6].in_uop.bits.fu_code[4] connect slots_6.io.in_uop.bits.fu_code[5], issue_slots[6].in_uop.bits.fu_code[5] connect slots_6.io.in_uop.bits.fu_code[6], issue_slots[6].in_uop.bits.fu_code[6] connect slots_6.io.in_uop.bits.fu_code[7], issue_slots[6].in_uop.bits.fu_code[7] connect slots_6.io.in_uop.bits.fu_code[8], issue_slots[6].in_uop.bits.fu_code[8] connect slots_6.io.in_uop.bits.fu_code[9], issue_slots[6].in_uop.bits.fu_code[9] connect slots_6.io.in_uop.bits.iq_type[0], issue_slots[6].in_uop.bits.iq_type[0] connect slots_6.io.in_uop.bits.iq_type[1], issue_slots[6].in_uop.bits.iq_type[1] connect slots_6.io.in_uop.bits.iq_type[2], issue_slots[6].in_uop.bits.iq_type[2] connect slots_6.io.in_uop.bits.iq_type[3], issue_slots[6].in_uop.bits.iq_type[3] connect slots_6.io.in_uop.bits.debug_pc, issue_slots[6].in_uop.bits.debug_pc connect slots_6.io.in_uop.bits.is_rvc, issue_slots[6].in_uop.bits.is_rvc connect slots_6.io.in_uop.bits.debug_inst, issue_slots[6].in_uop.bits.debug_inst connect slots_6.io.in_uop.bits.inst, issue_slots[6].in_uop.bits.inst connect slots_6.io.in_uop.valid, issue_slots[6].in_uop.valid connect issue_slots[6].iss_uop.debug_tsrc, slots_6.io.iss_uop.debug_tsrc connect issue_slots[6].iss_uop.debug_fsrc, slots_6.io.iss_uop.debug_fsrc connect issue_slots[6].iss_uop.bp_xcpt_if, slots_6.io.iss_uop.bp_xcpt_if connect issue_slots[6].iss_uop.bp_debug_if, slots_6.io.iss_uop.bp_debug_if connect issue_slots[6].iss_uop.xcpt_ma_if, slots_6.io.iss_uop.xcpt_ma_if connect issue_slots[6].iss_uop.xcpt_ae_if, slots_6.io.iss_uop.xcpt_ae_if connect issue_slots[6].iss_uop.xcpt_pf_if, slots_6.io.iss_uop.xcpt_pf_if connect issue_slots[6].iss_uop.fp_typ, slots_6.io.iss_uop.fp_typ connect issue_slots[6].iss_uop.fp_rm, slots_6.io.iss_uop.fp_rm connect issue_slots[6].iss_uop.fp_val, slots_6.io.iss_uop.fp_val connect issue_slots[6].iss_uop.fcn_op, slots_6.io.iss_uop.fcn_op connect issue_slots[6].iss_uop.fcn_dw, slots_6.io.iss_uop.fcn_dw connect issue_slots[6].iss_uop.frs3_en, slots_6.io.iss_uop.frs3_en connect issue_slots[6].iss_uop.lrs2_rtype, slots_6.io.iss_uop.lrs2_rtype connect issue_slots[6].iss_uop.lrs1_rtype, slots_6.io.iss_uop.lrs1_rtype connect issue_slots[6].iss_uop.dst_rtype, slots_6.io.iss_uop.dst_rtype connect issue_slots[6].iss_uop.lrs3, slots_6.io.iss_uop.lrs3 connect issue_slots[6].iss_uop.lrs2, slots_6.io.iss_uop.lrs2 connect issue_slots[6].iss_uop.lrs1, slots_6.io.iss_uop.lrs1 connect issue_slots[6].iss_uop.ldst, slots_6.io.iss_uop.ldst connect issue_slots[6].iss_uop.ldst_is_rs1, slots_6.io.iss_uop.ldst_is_rs1 connect issue_slots[6].iss_uop.csr_cmd, slots_6.io.iss_uop.csr_cmd connect issue_slots[6].iss_uop.flush_on_commit, slots_6.io.iss_uop.flush_on_commit connect issue_slots[6].iss_uop.is_unique, slots_6.io.iss_uop.is_unique connect issue_slots[6].iss_uop.uses_stq, slots_6.io.iss_uop.uses_stq connect issue_slots[6].iss_uop.uses_ldq, slots_6.io.iss_uop.uses_ldq connect issue_slots[6].iss_uop.mem_signed, slots_6.io.iss_uop.mem_signed connect issue_slots[6].iss_uop.mem_size, slots_6.io.iss_uop.mem_size connect issue_slots[6].iss_uop.mem_cmd, slots_6.io.iss_uop.mem_cmd connect issue_slots[6].iss_uop.exc_cause, slots_6.io.iss_uop.exc_cause connect issue_slots[6].iss_uop.exception, slots_6.io.iss_uop.exception connect issue_slots[6].iss_uop.stale_pdst, slots_6.io.iss_uop.stale_pdst connect issue_slots[6].iss_uop.ppred_busy, slots_6.io.iss_uop.ppred_busy connect issue_slots[6].iss_uop.prs3_busy, slots_6.io.iss_uop.prs3_busy connect issue_slots[6].iss_uop.prs2_busy, slots_6.io.iss_uop.prs2_busy connect issue_slots[6].iss_uop.prs1_busy, slots_6.io.iss_uop.prs1_busy connect issue_slots[6].iss_uop.ppred, slots_6.io.iss_uop.ppred connect issue_slots[6].iss_uop.prs3, slots_6.io.iss_uop.prs3 connect issue_slots[6].iss_uop.prs2, slots_6.io.iss_uop.prs2 connect issue_slots[6].iss_uop.prs1, slots_6.io.iss_uop.prs1 connect issue_slots[6].iss_uop.pdst, slots_6.io.iss_uop.pdst connect issue_slots[6].iss_uop.rxq_idx, slots_6.io.iss_uop.rxq_idx connect issue_slots[6].iss_uop.stq_idx, slots_6.io.iss_uop.stq_idx connect issue_slots[6].iss_uop.ldq_idx, slots_6.io.iss_uop.ldq_idx connect issue_slots[6].iss_uop.rob_idx, slots_6.io.iss_uop.rob_idx connect issue_slots[6].iss_uop.fp_ctrl.vec, slots_6.io.iss_uop.fp_ctrl.vec connect issue_slots[6].iss_uop.fp_ctrl.wflags, slots_6.io.iss_uop.fp_ctrl.wflags connect issue_slots[6].iss_uop.fp_ctrl.sqrt, slots_6.io.iss_uop.fp_ctrl.sqrt connect issue_slots[6].iss_uop.fp_ctrl.div, slots_6.io.iss_uop.fp_ctrl.div connect issue_slots[6].iss_uop.fp_ctrl.fma, slots_6.io.iss_uop.fp_ctrl.fma connect issue_slots[6].iss_uop.fp_ctrl.fastpipe, slots_6.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[6].iss_uop.fp_ctrl.toint, slots_6.io.iss_uop.fp_ctrl.toint connect issue_slots[6].iss_uop.fp_ctrl.fromint, slots_6.io.iss_uop.fp_ctrl.fromint connect issue_slots[6].iss_uop.fp_ctrl.typeTagOut, slots_6.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[6].iss_uop.fp_ctrl.typeTagIn, slots_6.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[6].iss_uop.fp_ctrl.swap23, slots_6.io.iss_uop.fp_ctrl.swap23 connect issue_slots[6].iss_uop.fp_ctrl.swap12, slots_6.io.iss_uop.fp_ctrl.swap12 connect issue_slots[6].iss_uop.fp_ctrl.ren3, slots_6.io.iss_uop.fp_ctrl.ren3 connect issue_slots[6].iss_uop.fp_ctrl.ren2, slots_6.io.iss_uop.fp_ctrl.ren2 connect issue_slots[6].iss_uop.fp_ctrl.ren1, slots_6.io.iss_uop.fp_ctrl.ren1 connect issue_slots[6].iss_uop.fp_ctrl.wen, slots_6.io.iss_uop.fp_ctrl.wen connect issue_slots[6].iss_uop.fp_ctrl.ldst, slots_6.io.iss_uop.fp_ctrl.ldst connect issue_slots[6].iss_uop.op2_sel, slots_6.io.iss_uop.op2_sel connect issue_slots[6].iss_uop.op1_sel, slots_6.io.iss_uop.op1_sel connect issue_slots[6].iss_uop.imm_packed, slots_6.io.iss_uop.imm_packed connect issue_slots[6].iss_uop.pimm, slots_6.io.iss_uop.pimm connect issue_slots[6].iss_uop.imm_sel, slots_6.io.iss_uop.imm_sel connect issue_slots[6].iss_uop.imm_rename, slots_6.io.iss_uop.imm_rename connect issue_slots[6].iss_uop.taken, slots_6.io.iss_uop.taken connect issue_slots[6].iss_uop.pc_lob, slots_6.io.iss_uop.pc_lob connect issue_slots[6].iss_uop.edge_inst, slots_6.io.iss_uop.edge_inst connect issue_slots[6].iss_uop.ftq_idx, slots_6.io.iss_uop.ftq_idx connect issue_slots[6].iss_uop.is_mov, slots_6.io.iss_uop.is_mov connect issue_slots[6].iss_uop.is_rocc, slots_6.io.iss_uop.is_rocc connect issue_slots[6].iss_uop.is_sys_pc2epc, slots_6.io.iss_uop.is_sys_pc2epc connect issue_slots[6].iss_uop.is_eret, slots_6.io.iss_uop.is_eret connect issue_slots[6].iss_uop.is_amo, slots_6.io.iss_uop.is_amo connect issue_slots[6].iss_uop.is_sfence, slots_6.io.iss_uop.is_sfence connect issue_slots[6].iss_uop.is_fencei, slots_6.io.iss_uop.is_fencei connect issue_slots[6].iss_uop.is_fence, slots_6.io.iss_uop.is_fence connect issue_slots[6].iss_uop.is_sfb, slots_6.io.iss_uop.is_sfb connect issue_slots[6].iss_uop.br_type, slots_6.io.iss_uop.br_type connect issue_slots[6].iss_uop.br_tag, slots_6.io.iss_uop.br_tag connect issue_slots[6].iss_uop.br_mask, slots_6.io.iss_uop.br_mask connect issue_slots[6].iss_uop.dis_col_sel, slots_6.io.iss_uop.dis_col_sel connect issue_slots[6].iss_uop.iw_p3_bypass_hint, slots_6.io.iss_uop.iw_p3_bypass_hint connect issue_slots[6].iss_uop.iw_p2_bypass_hint, slots_6.io.iss_uop.iw_p2_bypass_hint connect issue_slots[6].iss_uop.iw_p1_bypass_hint, slots_6.io.iss_uop.iw_p1_bypass_hint connect issue_slots[6].iss_uop.iw_p2_speculative_child, slots_6.io.iss_uop.iw_p2_speculative_child connect issue_slots[6].iss_uop.iw_p1_speculative_child, slots_6.io.iss_uop.iw_p1_speculative_child connect issue_slots[6].iss_uop.iw_issued_partial_dgen, slots_6.io.iss_uop.iw_issued_partial_dgen connect issue_slots[6].iss_uop.iw_issued_partial_agen, slots_6.io.iss_uop.iw_issued_partial_agen connect issue_slots[6].iss_uop.iw_issued, slots_6.io.iss_uop.iw_issued connect issue_slots[6].iss_uop.fu_code[0], slots_6.io.iss_uop.fu_code[0] connect issue_slots[6].iss_uop.fu_code[1], slots_6.io.iss_uop.fu_code[1] connect issue_slots[6].iss_uop.fu_code[2], slots_6.io.iss_uop.fu_code[2] connect issue_slots[6].iss_uop.fu_code[3], slots_6.io.iss_uop.fu_code[3] connect issue_slots[6].iss_uop.fu_code[4], slots_6.io.iss_uop.fu_code[4] connect issue_slots[6].iss_uop.fu_code[5], slots_6.io.iss_uop.fu_code[5] connect issue_slots[6].iss_uop.fu_code[6], slots_6.io.iss_uop.fu_code[6] connect issue_slots[6].iss_uop.fu_code[7], slots_6.io.iss_uop.fu_code[7] connect issue_slots[6].iss_uop.fu_code[8], slots_6.io.iss_uop.fu_code[8] connect issue_slots[6].iss_uop.fu_code[9], slots_6.io.iss_uop.fu_code[9] connect issue_slots[6].iss_uop.iq_type[0], slots_6.io.iss_uop.iq_type[0] connect issue_slots[6].iss_uop.iq_type[1], slots_6.io.iss_uop.iq_type[1] connect issue_slots[6].iss_uop.iq_type[2], slots_6.io.iss_uop.iq_type[2] connect issue_slots[6].iss_uop.iq_type[3], slots_6.io.iss_uop.iq_type[3] connect issue_slots[6].iss_uop.debug_pc, slots_6.io.iss_uop.debug_pc connect issue_slots[6].iss_uop.is_rvc, slots_6.io.iss_uop.is_rvc connect issue_slots[6].iss_uop.debug_inst, slots_6.io.iss_uop.debug_inst connect issue_slots[6].iss_uop.inst, slots_6.io.iss_uop.inst connect slots_6.io.grant, issue_slots[6].grant connect issue_slots[6].request, slots_6.io.request connect issue_slots[6].will_be_valid, slots_6.io.will_be_valid connect issue_slots[6].valid, slots_6.io.valid connect slots_7.io.child_rebusys, issue_slots[7].child_rebusys connect slots_7.io.pred_wakeup_port.bits, issue_slots[7].pred_wakeup_port.bits connect slots_7.io.pred_wakeup_port.valid, issue_slots[7].pred_wakeup_port.valid connect slots_7.io.wakeup_ports[0].bits.rebusy, issue_slots[7].wakeup_ports[0].bits.rebusy connect slots_7.io.wakeup_ports[0].bits.speculative_mask, issue_slots[7].wakeup_ports[0].bits.speculative_mask connect slots_7.io.wakeup_ports[0].bits.bypassable, issue_slots[7].wakeup_ports[0].bits.bypassable connect slots_7.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[0].bits.uop.debug_tsrc connect slots_7.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[0].bits.uop.debug_fsrc connect slots_7.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_7.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[0].bits.uop.bp_debug_if connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_7.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_7.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[7].wakeup_ports[0].bits.uop.fp_typ connect slots_7.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[7].wakeup_ports[0].bits.uop.fp_rm connect slots_7.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[7].wakeup_ports[0].bits.uop.fp_val connect slots_7.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[7].wakeup_ports[0].bits.uop.fcn_op connect slots_7.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[0].bits.uop.fcn_dw connect slots_7.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[7].wakeup_ports[0].bits.uop.frs3_en connect slots_7.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_7.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_7.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[0].bits.uop.dst_rtype connect slots_7.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[7].wakeup_ports[0].bits.uop.lrs3 connect slots_7.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[7].wakeup_ports[0].bits.uop.lrs2 connect slots_7.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[7].wakeup_ports[0].bits.uop.lrs1 connect slots_7.io.wakeup_ports[0].bits.uop.ldst, issue_slots[7].wakeup_ports[0].bits.uop.ldst connect slots_7.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_7.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[0].bits.uop.csr_cmd connect slots_7.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[0].bits.uop.flush_on_commit connect slots_7.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[7].wakeup_ports[0].bits.uop.is_unique connect slots_7.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[7].wakeup_ports[0].bits.uop.uses_stq connect slots_7.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[0].bits.uop.uses_ldq connect slots_7.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[7].wakeup_ports[0].bits.uop.mem_signed connect slots_7.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[7].wakeup_ports[0].bits.uop.mem_size connect slots_7.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[0].bits.uop.mem_cmd connect slots_7.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[7].wakeup_ports[0].bits.uop.exc_cause connect slots_7.io.wakeup_ports[0].bits.uop.exception, issue_slots[7].wakeup_ports[0].bits.uop.exception connect slots_7.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[0].bits.uop.stale_pdst connect slots_7.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[0].bits.uop.ppred_busy connect slots_7.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs3_busy connect slots_7.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs2_busy connect slots_7.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[0].bits.uop.prs1_busy connect slots_7.io.wakeup_ports[0].bits.uop.ppred, issue_slots[7].wakeup_ports[0].bits.uop.ppred connect slots_7.io.wakeup_ports[0].bits.uop.prs3, issue_slots[7].wakeup_ports[0].bits.uop.prs3 connect slots_7.io.wakeup_ports[0].bits.uop.prs2, issue_slots[7].wakeup_ports[0].bits.uop.prs2 connect slots_7.io.wakeup_ports[0].bits.uop.prs1, issue_slots[7].wakeup_ports[0].bits.uop.prs1 connect slots_7.io.wakeup_ports[0].bits.uop.pdst, issue_slots[7].wakeup_ports[0].bits.uop.pdst connect slots_7.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[0].bits.uop.rxq_idx connect slots_7.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[7].wakeup_ports[0].bits.uop.stq_idx connect slots_7.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[0].bits.uop.ldq_idx connect slots_7.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[7].wakeup_ports[0].bits.uop.rob_idx connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_7.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_7.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[7].wakeup_ports[0].bits.uop.op2_sel connect slots_7.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[7].wakeup_ports[0].bits.uop.op1_sel connect slots_7.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[7].wakeup_ports[0].bits.uop.imm_packed connect slots_7.io.wakeup_ports[0].bits.uop.pimm, issue_slots[7].wakeup_ports[0].bits.uop.pimm connect slots_7.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[7].wakeup_ports[0].bits.uop.imm_sel connect slots_7.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[7].wakeup_ports[0].bits.uop.imm_rename connect slots_7.io.wakeup_ports[0].bits.uop.taken, issue_slots[7].wakeup_ports[0].bits.uop.taken connect slots_7.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[7].wakeup_ports[0].bits.uop.pc_lob connect slots_7.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[7].wakeup_ports[0].bits.uop.edge_inst connect slots_7.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[0].bits.uop.ftq_idx connect slots_7.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[7].wakeup_ports[0].bits.uop.is_mov connect slots_7.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[7].wakeup_ports[0].bits.uop.is_rocc connect slots_7.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_7.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[7].wakeup_ports[0].bits.uop.is_eret connect slots_7.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[7].wakeup_ports[0].bits.uop.is_amo connect slots_7.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[7].wakeup_ports[0].bits.uop.is_sfence connect slots_7.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[7].wakeup_ports[0].bits.uop.is_fencei connect slots_7.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[7].wakeup_ports[0].bits.uop.is_fence connect slots_7.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[7].wakeup_ports[0].bits.uop.is_sfb connect slots_7.io.wakeup_ports[0].bits.uop.br_type, issue_slots[7].wakeup_ports[0].bits.uop.br_type connect slots_7.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[7].wakeup_ports[0].bits.uop.br_tag connect slots_7.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[7].wakeup_ports[0].bits.uop.br_mask connect slots_7.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[0].bits.uop.dis_col_sel connect slots_7.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_7.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_7.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_7.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_7.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_7.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[7].wakeup_ports[0].bits.uop.iw_issued connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[0] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[1] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[2] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[3] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[4] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[5] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[6] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[7] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[8] connect slots_7.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[0].bits.uop.fu_code[9] connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[0] connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[1] connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[2] connect slots_7.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[0].bits.uop.iq_type[3] connect slots_7.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[7].wakeup_ports[0].bits.uop.debug_pc connect slots_7.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[7].wakeup_ports[0].bits.uop.is_rvc connect slots_7.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[7].wakeup_ports[0].bits.uop.debug_inst connect slots_7.io.wakeup_ports[0].bits.uop.inst, issue_slots[7].wakeup_ports[0].bits.uop.inst connect slots_7.io.wakeup_ports[0].valid, issue_slots[7].wakeup_ports[0].valid connect slots_7.io.wakeup_ports[1].bits.rebusy, issue_slots[7].wakeup_ports[1].bits.rebusy connect slots_7.io.wakeup_ports[1].bits.speculative_mask, issue_slots[7].wakeup_ports[1].bits.speculative_mask connect slots_7.io.wakeup_ports[1].bits.bypassable, issue_slots[7].wakeup_ports[1].bits.bypassable connect slots_7.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[7].wakeup_ports[1].bits.uop.debug_tsrc connect slots_7.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[7].wakeup_ports[1].bits.uop.debug_fsrc connect slots_7.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[7].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_7.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[7].wakeup_ports[1].bits.uop.bp_debug_if connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_7.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[7].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_7.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[7].wakeup_ports[1].bits.uop.fp_typ connect slots_7.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[7].wakeup_ports[1].bits.uop.fp_rm connect slots_7.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[7].wakeup_ports[1].bits.uop.fp_val connect slots_7.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[7].wakeup_ports[1].bits.uop.fcn_op connect slots_7.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[7].wakeup_ports[1].bits.uop.fcn_dw connect slots_7.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[7].wakeup_ports[1].bits.uop.frs3_en connect slots_7.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[7].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_7.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[7].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_7.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[7].wakeup_ports[1].bits.uop.dst_rtype connect slots_7.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[7].wakeup_ports[1].bits.uop.lrs3 connect slots_7.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[7].wakeup_ports[1].bits.uop.lrs2 connect slots_7.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[7].wakeup_ports[1].bits.uop.lrs1 connect slots_7.io.wakeup_ports[1].bits.uop.ldst, issue_slots[7].wakeup_ports[1].bits.uop.ldst connect slots_7.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[7].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_7.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[7].wakeup_ports[1].bits.uop.csr_cmd connect slots_7.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[7].wakeup_ports[1].bits.uop.flush_on_commit connect slots_7.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[7].wakeup_ports[1].bits.uop.is_unique connect slots_7.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[7].wakeup_ports[1].bits.uop.uses_stq connect slots_7.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[7].wakeup_ports[1].bits.uop.uses_ldq connect slots_7.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[7].wakeup_ports[1].bits.uop.mem_signed connect slots_7.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[7].wakeup_ports[1].bits.uop.mem_size connect slots_7.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[7].wakeup_ports[1].bits.uop.mem_cmd connect slots_7.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[7].wakeup_ports[1].bits.uop.exc_cause connect slots_7.io.wakeup_ports[1].bits.uop.exception, issue_slots[7].wakeup_ports[1].bits.uop.exception connect slots_7.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[7].wakeup_ports[1].bits.uop.stale_pdst connect slots_7.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[7].wakeup_ports[1].bits.uop.ppred_busy connect slots_7.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs3_busy connect slots_7.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs2_busy connect slots_7.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[7].wakeup_ports[1].bits.uop.prs1_busy connect slots_7.io.wakeup_ports[1].bits.uop.ppred, issue_slots[7].wakeup_ports[1].bits.uop.ppred connect slots_7.io.wakeup_ports[1].bits.uop.prs3, issue_slots[7].wakeup_ports[1].bits.uop.prs3 connect slots_7.io.wakeup_ports[1].bits.uop.prs2, issue_slots[7].wakeup_ports[1].bits.uop.prs2 connect slots_7.io.wakeup_ports[1].bits.uop.prs1, issue_slots[7].wakeup_ports[1].bits.uop.prs1 connect slots_7.io.wakeup_ports[1].bits.uop.pdst, issue_slots[7].wakeup_ports[1].bits.uop.pdst connect slots_7.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[7].wakeup_ports[1].bits.uop.rxq_idx connect slots_7.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[7].wakeup_ports[1].bits.uop.stq_idx connect slots_7.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[7].wakeup_ports[1].bits.uop.ldq_idx connect slots_7.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[7].wakeup_ports[1].bits.uop.rob_idx connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_7.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_7.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[7].wakeup_ports[1].bits.uop.op2_sel connect slots_7.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[7].wakeup_ports[1].bits.uop.op1_sel connect slots_7.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[7].wakeup_ports[1].bits.uop.imm_packed connect slots_7.io.wakeup_ports[1].bits.uop.pimm, issue_slots[7].wakeup_ports[1].bits.uop.pimm connect slots_7.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[7].wakeup_ports[1].bits.uop.imm_sel connect slots_7.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[7].wakeup_ports[1].bits.uop.imm_rename connect slots_7.io.wakeup_ports[1].bits.uop.taken, issue_slots[7].wakeup_ports[1].bits.uop.taken connect slots_7.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[7].wakeup_ports[1].bits.uop.pc_lob connect slots_7.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[7].wakeup_ports[1].bits.uop.edge_inst connect slots_7.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[7].wakeup_ports[1].bits.uop.ftq_idx connect slots_7.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[7].wakeup_ports[1].bits.uop.is_mov connect slots_7.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[7].wakeup_ports[1].bits.uop.is_rocc connect slots_7.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[7].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_7.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[7].wakeup_ports[1].bits.uop.is_eret connect slots_7.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[7].wakeup_ports[1].bits.uop.is_amo connect slots_7.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[7].wakeup_ports[1].bits.uop.is_sfence connect slots_7.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[7].wakeup_ports[1].bits.uop.is_fencei connect slots_7.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[7].wakeup_ports[1].bits.uop.is_fence connect slots_7.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[7].wakeup_ports[1].bits.uop.is_sfb connect slots_7.io.wakeup_ports[1].bits.uop.br_type, issue_slots[7].wakeup_ports[1].bits.uop.br_type connect slots_7.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[7].wakeup_ports[1].bits.uop.br_tag connect slots_7.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[7].wakeup_ports[1].bits.uop.br_mask connect slots_7.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[7].wakeup_ports[1].bits.uop.dis_col_sel connect slots_7.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_7.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_7.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_7.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_7.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_7.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[7].wakeup_ports[1].bits.uop.iw_issued connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[0] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[1] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[2] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[3] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[4] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[5] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[6] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[7] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[8] connect slots_7.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[7].wakeup_ports[1].bits.uop.fu_code[9] connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[0] connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[1] connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[2] connect slots_7.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[7].wakeup_ports[1].bits.uop.iq_type[3] connect slots_7.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[7].wakeup_ports[1].bits.uop.debug_pc connect slots_7.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[7].wakeup_ports[1].bits.uop.is_rvc connect slots_7.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[7].wakeup_ports[1].bits.uop.debug_inst connect slots_7.io.wakeup_ports[1].bits.uop.inst, issue_slots[7].wakeup_ports[1].bits.uop.inst connect slots_7.io.wakeup_ports[1].valid, issue_slots[7].wakeup_ports[1].valid connect slots_7.io.squash_grant, issue_slots[7].squash_grant connect slots_7.io.clear, issue_slots[7].clear connect slots_7.io.kill, issue_slots[7].kill connect slots_7.io.brupdate.b2.target_offset, issue_slots[7].brupdate.b2.target_offset connect slots_7.io.brupdate.b2.jalr_target, issue_slots[7].brupdate.b2.jalr_target connect slots_7.io.brupdate.b2.pc_sel, issue_slots[7].brupdate.b2.pc_sel connect slots_7.io.brupdate.b2.cfi_type, issue_slots[7].brupdate.b2.cfi_type connect slots_7.io.brupdate.b2.taken, issue_slots[7].brupdate.b2.taken connect slots_7.io.brupdate.b2.mispredict, issue_slots[7].brupdate.b2.mispredict connect slots_7.io.brupdate.b2.uop.debug_tsrc, issue_slots[7].brupdate.b2.uop.debug_tsrc connect slots_7.io.brupdate.b2.uop.debug_fsrc, issue_slots[7].brupdate.b2.uop.debug_fsrc connect slots_7.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[7].brupdate.b2.uop.bp_xcpt_if connect slots_7.io.brupdate.b2.uop.bp_debug_if, issue_slots[7].brupdate.b2.uop.bp_debug_if connect slots_7.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[7].brupdate.b2.uop.xcpt_ma_if connect slots_7.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[7].brupdate.b2.uop.xcpt_ae_if connect slots_7.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[7].brupdate.b2.uop.xcpt_pf_if connect slots_7.io.brupdate.b2.uop.fp_typ, issue_slots[7].brupdate.b2.uop.fp_typ connect slots_7.io.brupdate.b2.uop.fp_rm, issue_slots[7].brupdate.b2.uop.fp_rm connect slots_7.io.brupdate.b2.uop.fp_val, issue_slots[7].brupdate.b2.uop.fp_val connect slots_7.io.brupdate.b2.uop.fcn_op, issue_slots[7].brupdate.b2.uop.fcn_op connect slots_7.io.brupdate.b2.uop.fcn_dw, issue_slots[7].brupdate.b2.uop.fcn_dw connect slots_7.io.brupdate.b2.uop.frs3_en, issue_slots[7].brupdate.b2.uop.frs3_en connect slots_7.io.brupdate.b2.uop.lrs2_rtype, issue_slots[7].brupdate.b2.uop.lrs2_rtype connect slots_7.io.brupdate.b2.uop.lrs1_rtype, issue_slots[7].brupdate.b2.uop.lrs1_rtype connect slots_7.io.brupdate.b2.uop.dst_rtype, issue_slots[7].brupdate.b2.uop.dst_rtype connect slots_7.io.brupdate.b2.uop.lrs3, issue_slots[7].brupdate.b2.uop.lrs3 connect slots_7.io.brupdate.b2.uop.lrs2, issue_slots[7].brupdate.b2.uop.lrs2 connect slots_7.io.brupdate.b2.uop.lrs1, issue_slots[7].brupdate.b2.uop.lrs1 connect slots_7.io.brupdate.b2.uop.ldst, issue_slots[7].brupdate.b2.uop.ldst connect slots_7.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[7].brupdate.b2.uop.ldst_is_rs1 connect slots_7.io.brupdate.b2.uop.csr_cmd, issue_slots[7].brupdate.b2.uop.csr_cmd connect slots_7.io.brupdate.b2.uop.flush_on_commit, issue_slots[7].brupdate.b2.uop.flush_on_commit connect slots_7.io.brupdate.b2.uop.is_unique, issue_slots[7].brupdate.b2.uop.is_unique connect slots_7.io.brupdate.b2.uop.uses_stq, issue_slots[7].brupdate.b2.uop.uses_stq connect slots_7.io.brupdate.b2.uop.uses_ldq, issue_slots[7].brupdate.b2.uop.uses_ldq connect slots_7.io.brupdate.b2.uop.mem_signed, issue_slots[7].brupdate.b2.uop.mem_signed connect slots_7.io.brupdate.b2.uop.mem_size, issue_slots[7].brupdate.b2.uop.mem_size connect slots_7.io.brupdate.b2.uop.mem_cmd, issue_slots[7].brupdate.b2.uop.mem_cmd connect slots_7.io.brupdate.b2.uop.exc_cause, issue_slots[7].brupdate.b2.uop.exc_cause connect slots_7.io.brupdate.b2.uop.exception, issue_slots[7].brupdate.b2.uop.exception connect slots_7.io.brupdate.b2.uop.stale_pdst, issue_slots[7].brupdate.b2.uop.stale_pdst connect slots_7.io.brupdate.b2.uop.ppred_busy, issue_slots[7].brupdate.b2.uop.ppred_busy connect slots_7.io.brupdate.b2.uop.prs3_busy, issue_slots[7].brupdate.b2.uop.prs3_busy connect slots_7.io.brupdate.b2.uop.prs2_busy, issue_slots[7].brupdate.b2.uop.prs2_busy connect slots_7.io.brupdate.b2.uop.prs1_busy, issue_slots[7].brupdate.b2.uop.prs1_busy connect slots_7.io.brupdate.b2.uop.ppred, issue_slots[7].brupdate.b2.uop.ppred connect slots_7.io.brupdate.b2.uop.prs3, issue_slots[7].brupdate.b2.uop.prs3 connect slots_7.io.brupdate.b2.uop.prs2, issue_slots[7].brupdate.b2.uop.prs2 connect slots_7.io.brupdate.b2.uop.prs1, issue_slots[7].brupdate.b2.uop.prs1 connect slots_7.io.brupdate.b2.uop.pdst, issue_slots[7].brupdate.b2.uop.pdst connect slots_7.io.brupdate.b2.uop.rxq_idx, issue_slots[7].brupdate.b2.uop.rxq_idx connect slots_7.io.brupdate.b2.uop.stq_idx, issue_slots[7].brupdate.b2.uop.stq_idx connect slots_7.io.brupdate.b2.uop.ldq_idx, issue_slots[7].brupdate.b2.uop.ldq_idx connect slots_7.io.brupdate.b2.uop.rob_idx, issue_slots[7].brupdate.b2.uop.rob_idx connect slots_7.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[7].brupdate.b2.uop.fp_ctrl.vec connect slots_7.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[7].brupdate.b2.uop.fp_ctrl.wflags connect slots_7.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[7].brupdate.b2.uop.fp_ctrl.sqrt connect slots_7.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[7].brupdate.b2.uop.fp_ctrl.div connect slots_7.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[7].brupdate.b2.uop.fp_ctrl.fma connect slots_7.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[7].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_7.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[7].brupdate.b2.uop.fp_ctrl.toint connect slots_7.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[7].brupdate.b2.uop.fp_ctrl.fromint connect slots_7.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_7.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_7.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[7].brupdate.b2.uop.fp_ctrl.swap23 connect slots_7.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[7].brupdate.b2.uop.fp_ctrl.swap12 connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren3 connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren2 connect slots_7.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[7].brupdate.b2.uop.fp_ctrl.ren1 connect slots_7.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[7].brupdate.b2.uop.fp_ctrl.wen connect slots_7.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[7].brupdate.b2.uop.fp_ctrl.ldst connect slots_7.io.brupdate.b2.uop.op2_sel, issue_slots[7].brupdate.b2.uop.op2_sel connect slots_7.io.brupdate.b2.uop.op1_sel, issue_slots[7].brupdate.b2.uop.op1_sel connect slots_7.io.brupdate.b2.uop.imm_packed, issue_slots[7].brupdate.b2.uop.imm_packed connect slots_7.io.brupdate.b2.uop.pimm, issue_slots[7].brupdate.b2.uop.pimm connect slots_7.io.brupdate.b2.uop.imm_sel, issue_slots[7].brupdate.b2.uop.imm_sel connect slots_7.io.brupdate.b2.uop.imm_rename, issue_slots[7].brupdate.b2.uop.imm_rename connect slots_7.io.brupdate.b2.uop.taken, issue_slots[7].brupdate.b2.uop.taken connect slots_7.io.brupdate.b2.uop.pc_lob, issue_slots[7].brupdate.b2.uop.pc_lob connect slots_7.io.brupdate.b2.uop.edge_inst, issue_slots[7].brupdate.b2.uop.edge_inst connect slots_7.io.brupdate.b2.uop.ftq_idx, issue_slots[7].brupdate.b2.uop.ftq_idx connect slots_7.io.brupdate.b2.uop.is_mov, issue_slots[7].brupdate.b2.uop.is_mov connect slots_7.io.brupdate.b2.uop.is_rocc, issue_slots[7].brupdate.b2.uop.is_rocc connect slots_7.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[7].brupdate.b2.uop.is_sys_pc2epc connect slots_7.io.brupdate.b2.uop.is_eret, issue_slots[7].brupdate.b2.uop.is_eret connect slots_7.io.brupdate.b2.uop.is_amo, issue_slots[7].brupdate.b2.uop.is_amo connect slots_7.io.brupdate.b2.uop.is_sfence, issue_slots[7].brupdate.b2.uop.is_sfence connect slots_7.io.brupdate.b2.uop.is_fencei, issue_slots[7].brupdate.b2.uop.is_fencei connect slots_7.io.brupdate.b2.uop.is_fence, issue_slots[7].brupdate.b2.uop.is_fence connect slots_7.io.brupdate.b2.uop.is_sfb, issue_slots[7].brupdate.b2.uop.is_sfb connect slots_7.io.brupdate.b2.uop.br_type, issue_slots[7].brupdate.b2.uop.br_type connect slots_7.io.brupdate.b2.uop.br_tag, issue_slots[7].brupdate.b2.uop.br_tag connect slots_7.io.brupdate.b2.uop.br_mask, issue_slots[7].brupdate.b2.uop.br_mask connect slots_7.io.brupdate.b2.uop.dis_col_sel, issue_slots[7].brupdate.b2.uop.dis_col_sel connect slots_7.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p3_bypass_hint connect slots_7.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p2_bypass_hint connect slots_7.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[7].brupdate.b2.uop.iw_p1_bypass_hint connect slots_7.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[7].brupdate.b2.uop.iw_p2_speculative_child connect slots_7.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[7].brupdate.b2.uop.iw_p1_speculative_child connect slots_7.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[7].brupdate.b2.uop.iw_issued_partial_dgen connect slots_7.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[7].brupdate.b2.uop.iw_issued_partial_agen connect slots_7.io.brupdate.b2.uop.iw_issued, issue_slots[7].brupdate.b2.uop.iw_issued connect slots_7.io.brupdate.b2.uop.fu_code[0], issue_slots[7].brupdate.b2.uop.fu_code[0] connect slots_7.io.brupdate.b2.uop.fu_code[1], issue_slots[7].brupdate.b2.uop.fu_code[1] connect slots_7.io.brupdate.b2.uop.fu_code[2], issue_slots[7].brupdate.b2.uop.fu_code[2] connect slots_7.io.brupdate.b2.uop.fu_code[3], issue_slots[7].brupdate.b2.uop.fu_code[3] connect slots_7.io.brupdate.b2.uop.fu_code[4], issue_slots[7].brupdate.b2.uop.fu_code[4] connect slots_7.io.brupdate.b2.uop.fu_code[5], issue_slots[7].brupdate.b2.uop.fu_code[5] connect slots_7.io.brupdate.b2.uop.fu_code[6], issue_slots[7].brupdate.b2.uop.fu_code[6] connect slots_7.io.brupdate.b2.uop.fu_code[7], issue_slots[7].brupdate.b2.uop.fu_code[7] connect slots_7.io.brupdate.b2.uop.fu_code[8], issue_slots[7].brupdate.b2.uop.fu_code[8] connect slots_7.io.brupdate.b2.uop.fu_code[9], issue_slots[7].brupdate.b2.uop.fu_code[9] connect slots_7.io.brupdate.b2.uop.iq_type[0], issue_slots[7].brupdate.b2.uop.iq_type[0] connect slots_7.io.brupdate.b2.uop.iq_type[1], issue_slots[7].brupdate.b2.uop.iq_type[1] connect slots_7.io.brupdate.b2.uop.iq_type[2], issue_slots[7].brupdate.b2.uop.iq_type[2] connect slots_7.io.brupdate.b2.uop.iq_type[3], issue_slots[7].brupdate.b2.uop.iq_type[3] connect slots_7.io.brupdate.b2.uop.debug_pc, issue_slots[7].brupdate.b2.uop.debug_pc connect slots_7.io.brupdate.b2.uop.is_rvc, issue_slots[7].brupdate.b2.uop.is_rvc connect slots_7.io.brupdate.b2.uop.debug_inst, issue_slots[7].brupdate.b2.uop.debug_inst connect slots_7.io.brupdate.b2.uop.inst, issue_slots[7].brupdate.b2.uop.inst connect slots_7.io.brupdate.b1.mispredict_mask, issue_slots[7].brupdate.b1.mispredict_mask connect slots_7.io.brupdate.b1.resolve_mask, issue_slots[7].brupdate.b1.resolve_mask connect issue_slots[7].out_uop.debug_tsrc, slots_7.io.out_uop.debug_tsrc connect issue_slots[7].out_uop.debug_fsrc, slots_7.io.out_uop.debug_fsrc connect issue_slots[7].out_uop.bp_xcpt_if, slots_7.io.out_uop.bp_xcpt_if connect issue_slots[7].out_uop.bp_debug_if, slots_7.io.out_uop.bp_debug_if connect issue_slots[7].out_uop.xcpt_ma_if, slots_7.io.out_uop.xcpt_ma_if connect issue_slots[7].out_uop.xcpt_ae_if, slots_7.io.out_uop.xcpt_ae_if connect issue_slots[7].out_uop.xcpt_pf_if, slots_7.io.out_uop.xcpt_pf_if connect issue_slots[7].out_uop.fp_typ, slots_7.io.out_uop.fp_typ connect issue_slots[7].out_uop.fp_rm, slots_7.io.out_uop.fp_rm connect issue_slots[7].out_uop.fp_val, slots_7.io.out_uop.fp_val connect issue_slots[7].out_uop.fcn_op, slots_7.io.out_uop.fcn_op connect issue_slots[7].out_uop.fcn_dw, slots_7.io.out_uop.fcn_dw connect issue_slots[7].out_uop.frs3_en, slots_7.io.out_uop.frs3_en connect issue_slots[7].out_uop.lrs2_rtype, slots_7.io.out_uop.lrs2_rtype connect issue_slots[7].out_uop.lrs1_rtype, slots_7.io.out_uop.lrs1_rtype connect issue_slots[7].out_uop.dst_rtype, slots_7.io.out_uop.dst_rtype connect issue_slots[7].out_uop.lrs3, slots_7.io.out_uop.lrs3 connect issue_slots[7].out_uop.lrs2, slots_7.io.out_uop.lrs2 connect issue_slots[7].out_uop.lrs1, slots_7.io.out_uop.lrs1 connect issue_slots[7].out_uop.ldst, slots_7.io.out_uop.ldst connect issue_slots[7].out_uop.ldst_is_rs1, slots_7.io.out_uop.ldst_is_rs1 connect issue_slots[7].out_uop.csr_cmd, slots_7.io.out_uop.csr_cmd connect issue_slots[7].out_uop.flush_on_commit, slots_7.io.out_uop.flush_on_commit connect issue_slots[7].out_uop.is_unique, slots_7.io.out_uop.is_unique connect issue_slots[7].out_uop.uses_stq, slots_7.io.out_uop.uses_stq connect issue_slots[7].out_uop.uses_ldq, slots_7.io.out_uop.uses_ldq connect issue_slots[7].out_uop.mem_signed, slots_7.io.out_uop.mem_signed connect issue_slots[7].out_uop.mem_size, slots_7.io.out_uop.mem_size connect issue_slots[7].out_uop.mem_cmd, slots_7.io.out_uop.mem_cmd connect issue_slots[7].out_uop.exc_cause, slots_7.io.out_uop.exc_cause connect issue_slots[7].out_uop.exception, slots_7.io.out_uop.exception connect issue_slots[7].out_uop.stale_pdst, slots_7.io.out_uop.stale_pdst connect issue_slots[7].out_uop.ppred_busy, slots_7.io.out_uop.ppred_busy connect issue_slots[7].out_uop.prs3_busy, slots_7.io.out_uop.prs3_busy connect issue_slots[7].out_uop.prs2_busy, slots_7.io.out_uop.prs2_busy connect issue_slots[7].out_uop.prs1_busy, slots_7.io.out_uop.prs1_busy connect issue_slots[7].out_uop.ppred, slots_7.io.out_uop.ppred connect issue_slots[7].out_uop.prs3, slots_7.io.out_uop.prs3 connect issue_slots[7].out_uop.prs2, slots_7.io.out_uop.prs2 connect issue_slots[7].out_uop.prs1, slots_7.io.out_uop.prs1 connect issue_slots[7].out_uop.pdst, slots_7.io.out_uop.pdst connect issue_slots[7].out_uop.rxq_idx, slots_7.io.out_uop.rxq_idx connect issue_slots[7].out_uop.stq_idx, slots_7.io.out_uop.stq_idx connect issue_slots[7].out_uop.ldq_idx, slots_7.io.out_uop.ldq_idx connect issue_slots[7].out_uop.rob_idx, slots_7.io.out_uop.rob_idx connect issue_slots[7].out_uop.fp_ctrl.vec, slots_7.io.out_uop.fp_ctrl.vec connect issue_slots[7].out_uop.fp_ctrl.wflags, slots_7.io.out_uop.fp_ctrl.wflags connect issue_slots[7].out_uop.fp_ctrl.sqrt, slots_7.io.out_uop.fp_ctrl.sqrt connect issue_slots[7].out_uop.fp_ctrl.div, slots_7.io.out_uop.fp_ctrl.div connect issue_slots[7].out_uop.fp_ctrl.fma, slots_7.io.out_uop.fp_ctrl.fma connect issue_slots[7].out_uop.fp_ctrl.fastpipe, slots_7.io.out_uop.fp_ctrl.fastpipe connect issue_slots[7].out_uop.fp_ctrl.toint, slots_7.io.out_uop.fp_ctrl.toint connect issue_slots[7].out_uop.fp_ctrl.fromint, slots_7.io.out_uop.fp_ctrl.fromint connect issue_slots[7].out_uop.fp_ctrl.typeTagOut, slots_7.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[7].out_uop.fp_ctrl.typeTagIn, slots_7.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[7].out_uop.fp_ctrl.swap23, slots_7.io.out_uop.fp_ctrl.swap23 connect issue_slots[7].out_uop.fp_ctrl.swap12, slots_7.io.out_uop.fp_ctrl.swap12 connect issue_slots[7].out_uop.fp_ctrl.ren3, slots_7.io.out_uop.fp_ctrl.ren3 connect issue_slots[7].out_uop.fp_ctrl.ren2, slots_7.io.out_uop.fp_ctrl.ren2 connect issue_slots[7].out_uop.fp_ctrl.ren1, slots_7.io.out_uop.fp_ctrl.ren1 connect issue_slots[7].out_uop.fp_ctrl.wen, slots_7.io.out_uop.fp_ctrl.wen connect issue_slots[7].out_uop.fp_ctrl.ldst, slots_7.io.out_uop.fp_ctrl.ldst connect issue_slots[7].out_uop.op2_sel, slots_7.io.out_uop.op2_sel connect issue_slots[7].out_uop.op1_sel, slots_7.io.out_uop.op1_sel connect issue_slots[7].out_uop.imm_packed, slots_7.io.out_uop.imm_packed connect issue_slots[7].out_uop.pimm, slots_7.io.out_uop.pimm connect issue_slots[7].out_uop.imm_sel, slots_7.io.out_uop.imm_sel connect issue_slots[7].out_uop.imm_rename, slots_7.io.out_uop.imm_rename connect issue_slots[7].out_uop.taken, slots_7.io.out_uop.taken connect issue_slots[7].out_uop.pc_lob, slots_7.io.out_uop.pc_lob connect issue_slots[7].out_uop.edge_inst, slots_7.io.out_uop.edge_inst connect issue_slots[7].out_uop.ftq_idx, slots_7.io.out_uop.ftq_idx connect issue_slots[7].out_uop.is_mov, slots_7.io.out_uop.is_mov connect issue_slots[7].out_uop.is_rocc, slots_7.io.out_uop.is_rocc connect issue_slots[7].out_uop.is_sys_pc2epc, slots_7.io.out_uop.is_sys_pc2epc connect issue_slots[7].out_uop.is_eret, slots_7.io.out_uop.is_eret connect issue_slots[7].out_uop.is_amo, slots_7.io.out_uop.is_amo connect issue_slots[7].out_uop.is_sfence, slots_7.io.out_uop.is_sfence connect issue_slots[7].out_uop.is_fencei, slots_7.io.out_uop.is_fencei connect issue_slots[7].out_uop.is_fence, slots_7.io.out_uop.is_fence connect issue_slots[7].out_uop.is_sfb, slots_7.io.out_uop.is_sfb connect issue_slots[7].out_uop.br_type, slots_7.io.out_uop.br_type connect issue_slots[7].out_uop.br_tag, slots_7.io.out_uop.br_tag connect issue_slots[7].out_uop.br_mask, slots_7.io.out_uop.br_mask connect issue_slots[7].out_uop.dis_col_sel, slots_7.io.out_uop.dis_col_sel connect issue_slots[7].out_uop.iw_p3_bypass_hint, slots_7.io.out_uop.iw_p3_bypass_hint connect issue_slots[7].out_uop.iw_p2_bypass_hint, slots_7.io.out_uop.iw_p2_bypass_hint connect issue_slots[7].out_uop.iw_p1_bypass_hint, slots_7.io.out_uop.iw_p1_bypass_hint connect issue_slots[7].out_uop.iw_p2_speculative_child, slots_7.io.out_uop.iw_p2_speculative_child connect issue_slots[7].out_uop.iw_p1_speculative_child, slots_7.io.out_uop.iw_p1_speculative_child connect issue_slots[7].out_uop.iw_issued_partial_dgen, slots_7.io.out_uop.iw_issued_partial_dgen connect issue_slots[7].out_uop.iw_issued_partial_agen, slots_7.io.out_uop.iw_issued_partial_agen connect issue_slots[7].out_uop.iw_issued, slots_7.io.out_uop.iw_issued connect issue_slots[7].out_uop.fu_code[0], slots_7.io.out_uop.fu_code[0] connect issue_slots[7].out_uop.fu_code[1], slots_7.io.out_uop.fu_code[1] connect issue_slots[7].out_uop.fu_code[2], slots_7.io.out_uop.fu_code[2] connect issue_slots[7].out_uop.fu_code[3], slots_7.io.out_uop.fu_code[3] connect issue_slots[7].out_uop.fu_code[4], slots_7.io.out_uop.fu_code[4] connect issue_slots[7].out_uop.fu_code[5], slots_7.io.out_uop.fu_code[5] connect issue_slots[7].out_uop.fu_code[6], slots_7.io.out_uop.fu_code[6] connect issue_slots[7].out_uop.fu_code[7], slots_7.io.out_uop.fu_code[7] connect issue_slots[7].out_uop.fu_code[8], slots_7.io.out_uop.fu_code[8] connect issue_slots[7].out_uop.fu_code[9], slots_7.io.out_uop.fu_code[9] connect issue_slots[7].out_uop.iq_type[0], slots_7.io.out_uop.iq_type[0] connect issue_slots[7].out_uop.iq_type[1], slots_7.io.out_uop.iq_type[1] connect issue_slots[7].out_uop.iq_type[2], slots_7.io.out_uop.iq_type[2] connect issue_slots[7].out_uop.iq_type[3], slots_7.io.out_uop.iq_type[3] connect issue_slots[7].out_uop.debug_pc, slots_7.io.out_uop.debug_pc connect issue_slots[7].out_uop.is_rvc, slots_7.io.out_uop.is_rvc connect issue_slots[7].out_uop.debug_inst, slots_7.io.out_uop.debug_inst connect issue_slots[7].out_uop.inst, slots_7.io.out_uop.inst connect slots_7.io.in_uop.bits.debug_tsrc, issue_slots[7].in_uop.bits.debug_tsrc connect slots_7.io.in_uop.bits.debug_fsrc, issue_slots[7].in_uop.bits.debug_fsrc connect slots_7.io.in_uop.bits.bp_xcpt_if, issue_slots[7].in_uop.bits.bp_xcpt_if connect slots_7.io.in_uop.bits.bp_debug_if, issue_slots[7].in_uop.bits.bp_debug_if connect slots_7.io.in_uop.bits.xcpt_ma_if, issue_slots[7].in_uop.bits.xcpt_ma_if connect slots_7.io.in_uop.bits.xcpt_ae_if, issue_slots[7].in_uop.bits.xcpt_ae_if connect slots_7.io.in_uop.bits.xcpt_pf_if, issue_slots[7].in_uop.bits.xcpt_pf_if connect slots_7.io.in_uop.bits.fp_typ, issue_slots[7].in_uop.bits.fp_typ connect slots_7.io.in_uop.bits.fp_rm, issue_slots[7].in_uop.bits.fp_rm connect slots_7.io.in_uop.bits.fp_val, issue_slots[7].in_uop.bits.fp_val connect slots_7.io.in_uop.bits.fcn_op, issue_slots[7].in_uop.bits.fcn_op connect slots_7.io.in_uop.bits.fcn_dw, issue_slots[7].in_uop.bits.fcn_dw connect slots_7.io.in_uop.bits.frs3_en, issue_slots[7].in_uop.bits.frs3_en connect slots_7.io.in_uop.bits.lrs2_rtype, issue_slots[7].in_uop.bits.lrs2_rtype connect slots_7.io.in_uop.bits.lrs1_rtype, issue_slots[7].in_uop.bits.lrs1_rtype connect slots_7.io.in_uop.bits.dst_rtype, issue_slots[7].in_uop.bits.dst_rtype connect slots_7.io.in_uop.bits.lrs3, issue_slots[7].in_uop.bits.lrs3 connect slots_7.io.in_uop.bits.lrs2, issue_slots[7].in_uop.bits.lrs2 connect slots_7.io.in_uop.bits.lrs1, issue_slots[7].in_uop.bits.lrs1 connect slots_7.io.in_uop.bits.ldst, issue_slots[7].in_uop.bits.ldst connect slots_7.io.in_uop.bits.ldst_is_rs1, issue_slots[7].in_uop.bits.ldst_is_rs1 connect slots_7.io.in_uop.bits.csr_cmd, issue_slots[7].in_uop.bits.csr_cmd connect slots_7.io.in_uop.bits.flush_on_commit, issue_slots[7].in_uop.bits.flush_on_commit connect slots_7.io.in_uop.bits.is_unique, issue_slots[7].in_uop.bits.is_unique connect slots_7.io.in_uop.bits.uses_stq, issue_slots[7].in_uop.bits.uses_stq connect slots_7.io.in_uop.bits.uses_ldq, issue_slots[7].in_uop.bits.uses_ldq connect slots_7.io.in_uop.bits.mem_signed, issue_slots[7].in_uop.bits.mem_signed connect slots_7.io.in_uop.bits.mem_size, issue_slots[7].in_uop.bits.mem_size connect slots_7.io.in_uop.bits.mem_cmd, issue_slots[7].in_uop.bits.mem_cmd connect slots_7.io.in_uop.bits.exc_cause, issue_slots[7].in_uop.bits.exc_cause connect slots_7.io.in_uop.bits.exception, issue_slots[7].in_uop.bits.exception connect slots_7.io.in_uop.bits.stale_pdst, issue_slots[7].in_uop.bits.stale_pdst connect slots_7.io.in_uop.bits.ppred_busy, issue_slots[7].in_uop.bits.ppred_busy connect slots_7.io.in_uop.bits.prs3_busy, issue_slots[7].in_uop.bits.prs3_busy connect slots_7.io.in_uop.bits.prs2_busy, issue_slots[7].in_uop.bits.prs2_busy connect slots_7.io.in_uop.bits.prs1_busy, issue_slots[7].in_uop.bits.prs1_busy connect slots_7.io.in_uop.bits.ppred, issue_slots[7].in_uop.bits.ppred connect slots_7.io.in_uop.bits.prs3, issue_slots[7].in_uop.bits.prs3 connect slots_7.io.in_uop.bits.prs2, issue_slots[7].in_uop.bits.prs2 connect slots_7.io.in_uop.bits.prs1, issue_slots[7].in_uop.bits.prs1 connect slots_7.io.in_uop.bits.pdst, issue_slots[7].in_uop.bits.pdst connect slots_7.io.in_uop.bits.rxq_idx, issue_slots[7].in_uop.bits.rxq_idx connect slots_7.io.in_uop.bits.stq_idx, issue_slots[7].in_uop.bits.stq_idx connect slots_7.io.in_uop.bits.ldq_idx, issue_slots[7].in_uop.bits.ldq_idx connect slots_7.io.in_uop.bits.rob_idx, issue_slots[7].in_uop.bits.rob_idx connect slots_7.io.in_uop.bits.fp_ctrl.vec, issue_slots[7].in_uop.bits.fp_ctrl.vec connect slots_7.io.in_uop.bits.fp_ctrl.wflags, issue_slots[7].in_uop.bits.fp_ctrl.wflags connect slots_7.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[7].in_uop.bits.fp_ctrl.sqrt connect slots_7.io.in_uop.bits.fp_ctrl.div, issue_slots[7].in_uop.bits.fp_ctrl.div connect slots_7.io.in_uop.bits.fp_ctrl.fma, issue_slots[7].in_uop.bits.fp_ctrl.fma connect slots_7.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].in_uop.bits.fp_ctrl.fastpipe connect slots_7.io.in_uop.bits.fp_ctrl.toint, issue_slots[7].in_uop.bits.fp_ctrl.toint connect slots_7.io.in_uop.bits.fp_ctrl.fromint, issue_slots[7].in_uop.bits.fp_ctrl.fromint connect slots_7.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut connect slots_7.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn connect slots_7.io.in_uop.bits.fp_ctrl.swap23, issue_slots[7].in_uop.bits.fp_ctrl.swap23 connect slots_7.io.in_uop.bits.fp_ctrl.swap12, issue_slots[7].in_uop.bits.fp_ctrl.swap12 connect slots_7.io.in_uop.bits.fp_ctrl.ren3, issue_slots[7].in_uop.bits.fp_ctrl.ren3 connect slots_7.io.in_uop.bits.fp_ctrl.ren2, issue_slots[7].in_uop.bits.fp_ctrl.ren2 connect slots_7.io.in_uop.bits.fp_ctrl.ren1, issue_slots[7].in_uop.bits.fp_ctrl.ren1 connect slots_7.io.in_uop.bits.fp_ctrl.wen, issue_slots[7].in_uop.bits.fp_ctrl.wen connect slots_7.io.in_uop.bits.fp_ctrl.ldst, issue_slots[7].in_uop.bits.fp_ctrl.ldst connect slots_7.io.in_uop.bits.op2_sel, issue_slots[7].in_uop.bits.op2_sel connect slots_7.io.in_uop.bits.op1_sel, issue_slots[7].in_uop.bits.op1_sel connect slots_7.io.in_uop.bits.imm_packed, issue_slots[7].in_uop.bits.imm_packed connect slots_7.io.in_uop.bits.pimm, issue_slots[7].in_uop.bits.pimm connect slots_7.io.in_uop.bits.imm_sel, issue_slots[7].in_uop.bits.imm_sel connect slots_7.io.in_uop.bits.imm_rename, issue_slots[7].in_uop.bits.imm_rename connect slots_7.io.in_uop.bits.taken, issue_slots[7].in_uop.bits.taken connect slots_7.io.in_uop.bits.pc_lob, issue_slots[7].in_uop.bits.pc_lob connect slots_7.io.in_uop.bits.edge_inst, issue_slots[7].in_uop.bits.edge_inst connect slots_7.io.in_uop.bits.ftq_idx, issue_slots[7].in_uop.bits.ftq_idx connect slots_7.io.in_uop.bits.is_mov, issue_slots[7].in_uop.bits.is_mov connect slots_7.io.in_uop.bits.is_rocc, issue_slots[7].in_uop.bits.is_rocc connect slots_7.io.in_uop.bits.is_sys_pc2epc, issue_slots[7].in_uop.bits.is_sys_pc2epc connect slots_7.io.in_uop.bits.is_eret, issue_slots[7].in_uop.bits.is_eret connect slots_7.io.in_uop.bits.is_amo, issue_slots[7].in_uop.bits.is_amo connect slots_7.io.in_uop.bits.is_sfence, issue_slots[7].in_uop.bits.is_sfence connect slots_7.io.in_uop.bits.is_fencei, issue_slots[7].in_uop.bits.is_fencei connect slots_7.io.in_uop.bits.is_fence, issue_slots[7].in_uop.bits.is_fence connect slots_7.io.in_uop.bits.is_sfb, issue_slots[7].in_uop.bits.is_sfb connect slots_7.io.in_uop.bits.br_type, issue_slots[7].in_uop.bits.br_type connect slots_7.io.in_uop.bits.br_tag, issue_slots[7].in_uop.bits.br_tag connect slots_7.io.in_uop.bits.br_mask, issue_slots[7].in_uop.bits.br_mask connect slots_7.io.in_uop.bits.dis_col_sel, issue_slots[7].in_uop.bits.dis_col_sel connect slots_7.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[7].in_uop.bits.iw_p3_bypass_hint connect slots_7.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[7].in_uop.bits.iw_p2_bypass_hint connect slots_7.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[7].in_uop.bits.iw_p1_bypass_hint connect slots_7.io.in_uop.bits.iw_p2_speculative_child, issue_slots[7].in_uop.bits.iw_p2_speculative_child connect slots_7.io.in_uop.bits.iw_p1_speculative_child, issue_slots[7].in_uop.bits.iw_p1_speculative_child connect slots_7.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[7].in_uop.bits.iw_issued_partial_dgen connect slots_7.io.in_uop.bits.iw_issued_partial_agen, issue_slots[7].in_uop.bits.iw_issued_partial_agen connect slots_7.io.in_uop.bits.iw_issued, issue_slots[7].in_uop.bits.iw_issued connect slots_7.io.in_uop.bits.fu_code[0], issue_slots[7].in_uop.bits.fu_code[0] connect slots_7.io.in_uop.bits.fu_code[1], issue_slots[7].in_uop.bits.fu_code[1] connect slots_7.io.in_uop.bits.fu_code[2], issue_slots[7].in_uop.bits.fu_code[2] connect slots_7.io.in_uop.bits.fu_code[3], issue_slots[7].in_uop.bits.fu_code[3] connect slots_7.io.in_uop.bits.fu_code[4], issue_slots[7].in_uop.bits.fu_code[4] connect slots_7.io.in_uop.bits.fu_code[5], issue_slots[7].in_uop.bits.fu_code[5] connect slots_7.io.in_uop.bits.fu_code[6], issue_slots[7].in_uop.bits.fu_code[6] connect slots_7.io.in_uop.bits.fu_code[7], issue_slots[7].in_uop.bits.fu_code[7] connect slots_7.io.in_uop.bits.fu_code[8], issue_slots[7].in_uop.bits.fu_code[8] connect slots_7.io.in_uop.bits.fu_code[9], issue_slots[7].in_uop.bits.fu_code[9] connect slots_7.io.in_uop.bits.iq_type[0], issue_slots[7].in_uop.bits.iq_type[0] connect slots_7.io.in_uop.bits.iq_type[1], issue_slots[7].in_uop.bits.iq_type[1] connect slots_7.io.in_uop.bits.iq_type[2], issue_slots[7].in_uop.bits.iq_type[2] connect slots_7.io.in_uop.bits.iq_type[3], issue_slots[7].in_uop.bits.iq_type[3] connect slots_7.io.in_uop.bits.debug_pc, issue_slots[7].in_uop.bits.debug_pc connect slots_7.io.in_uop.bits.is_rvc, issue_slots[7].in_uop.bits.is_rvc connect slots_7.io.in_uop.bits.debug_inst, issue_slots[7].in_uop.bits.debug_inst connect slots_7.io.in_uop.bits.inst, issue_slots[7].in_uop.bits.inst connect slots_7.io.in_uop.valid, issue_slots[7].in_uop.valid connect issue_slots[7].iss_uop.debug_tsrc, slots_7.io.iss_uop.debug_tsrc connect issue_slots[7].iss_uop.debug_fsrc, slots_7.io.iss_uop.debug_fsrc connect issue_slots[7].iss_uop.bp_xcpt_if, slots_7.io.iss_uop.bp_xcpt_if connect issue_slots[7].iss_uop.bp_debug_if, slots_7.io.iss_uop.bp_debug_if connect issue_slots[7].iss_uop.xcpt_ma_if, slots_7.io.iss_uop.xcpt_ma_if connect issue_slots[7].iss_uop.xcpt_ae_if, slots_7.io.iss_uop.xcpt_ae_if connect issue_slots[7].iss_uop.xcpt_pf_if, slots_7.io.iss_uop.xcpt_pf_if connect issue_slots[7].iss_uop.fp_typ, slots_7.io.iss_uop.fp_typ connect issue_slots[7].iss_uop.fp_rm, slots_7.io.iss_uop.fp_rm connect issue_slots[7].iss_uop.fp_val, slots_7.io.iss_uop.fp_val connect issue_slots[7].iss_uop.fcn_op, slots_7.io.iss_uop.fcn_op connect issue_slots[7].iss_uop.fcn_dw, slots_7.io.iss_uop.fcn_dw connect issue_slots[7].iss_uop.frs3_en, slots_7.io.iss_uop.frs3_en connect issue_slots[7].iss_uop.lrs2_rtype, slots_7.io.iss_uop.lrs2_rtype connect issue_slots[7].iss_uop.lrs1_rtype, slots_7.io.iss_uop.lrs1_rtype connect issue_slots[7].iss_uop.dst_rtype, slots_7.io.iss_uop.dst_rtype connect issue_slots[7].iss_uop.lrs3, slots_7.io.iss_uop.lrs3 connect issue_slots[7].iss_uop.lrs2, slots_7.io.iss_uop.lrs2 connect issue_slots[7].iss_uop.lrs1, slots_7.io.iss_uop.lrs1 connect issue_slots[7].iss_uop.ldst, slots_7.io.iss_uop.ldst connect issue_slots[7].iss_uop.ldst_is_rs1, slots_7.io.iss_uop.ldst_is_rs1 connect issue_slots[7].iss_uop.csr_cmd, slots_7.io.iss_uop.csr_cmd connect issue_slots[7].iss_uop.flush_on_commit, slots_7.io.iss_uop.flush_on_commit connect issue_slots[7].iss_uop.is_unique, slots_7.io.iss_uop.is_unique connect issue_slots[7].iss_uop.uses_stq, slots_7.io.iss_uop.uses_stq connect issue_slots[7].iss_uop.uses_ldq, slots_7.io.iss_uop.uses_ldq connect issue_slots[7].iss_uop.mem_signed, slots_7.io.iss_uop.mem_signed connect issue_slots[7].iss_uop.mem_size, slots_7.io.iss_uop.mem_size connect issue_slots[7].iss_uop.mem_cmd, slots_7.io.iss_uop.mem_cmd connect issue_slots[7].iss_uop.exc_cause, slots_7.io.iss_uop.exc_cause connect issue_slots[7].iss_uop.exception, slots_7.io.iss_uop.exception connect issue_slots[7].iss_uop.stale_pdst, slots_7.io.iss_uop.stale_pdst connect issue_slots[7].iss_uop.ppred_busy, slots_7.io.iss_uop.ppred_busy connect issue_slots[7].iss_uop.prs3_busy, slots_7.io.iss_uop.prs3_busy connect issue_slots[7].iss_uop.prs2_busy, slots_7.io.iss_uop.prs2_busy connect issue_slots[7].iss_uop.prs1_busy, slots_7.io.iss_uop.prs1_busy connect issue_slots[7].iss_uop.ppred, slots_7.io.iss_uop.ppred connect issue_slots[7].iss_uop.prs3, slots_7.io.iss_uop.prs3 connect issue_slots[7].iss_uop.prs2, slots_7.io.iss_uop.prs2 connect issue_slots[7].iss_uop.prs1, slots_7.io.iss_uop.prs1 connect issue_slots[7].iss_uop.pdst, slots_7.io.iss_uop.pdst connect issue_slots[7].iss_uop.rxq_idx, slots_7.io.iss_uop.rxq_idx connect issue_slots[7].iss_uop.stq_idx, slots_7.io.iss_uop.stq_idx connect issue_slots[7].iss_uop.ldq_idx, slots_7.io.iss_uop.ldq_idx connect issue_slots[7].iss_uop.rob_idx, slots_7.io.iss_uop.rob_idx connect issue_slots[7].iss_uop.fp_ctrl.vec, slots_7.io.iss_uop.fp_ctrl.vec connect issue_slots[7].iss_uop.fp_ctrl.wflags, slots_7.io.iss_uop.fp_ctrl.wflags connect issue_slots[7].iss_uop.fp_ctrl.sqrt, slots_7.io.iss_uop.fp_ctrl.sqrt connect issue_slots[7].iss_uop.fp_ctrl.div, slots_7.io.iss_uop.fp_ctrl.div connect issue_slots[7].iss_uop.fp_ctrl.fma, slots_7.io.iss_uop.fp_ctrl.fma connect issue_slots[7].iss_uop.fp_ctrl.fastpipe, slots_7.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[7].iss_uop.fp_ctrl.toint, slots_7.io.iss_uop.fp_ctrl.toint connect issue_slots[7].iss_uop.fp_ctrl.fromint, slots_7.io.iss_uop.fp_ctrl.fromint connect issue_slots[7].iss_uop.fp_ctrl.typeTagOut, slots_7.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[7].iss_uop.fp_ctrl.typeTagIn, slots_7.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[7].iss_uop.fp_ctrl.swap23, slots_7.io.iss_uop.fp_ctrl.swap23 connect issue_slots[7].iss_uop.fp_ctrl.swap12, slots_7.io.iss_uop.fp_ctrl.swap12 connect issue_slots[7].iss_uop.fp_ctrl.ren3, slots_7.io.iss_uop.fp_ctrl.ren3 connect issue_slots[7].iss_uop.fp_ctrl.ren2, slots_7.io.iss_uop.fp_ctrl.ren2 connect issue_slots[7].iss_uop.fp_ctrl.ren1, slots_7.io.iss_uop.fp_ctrl.ren1 connect issue_slots[7].iss_uop.fp_ctrl.wen, slots_7.io.iss_uop.fp_ctrl.wen connect issue_slots[7].iss_uop.fp_ctrl.ldst, slots_7.io.iss_uop.fp_ctrl.ldst connect issue_slots[7].iss_uop.op2_sel, slots_7.io.iss_uop.op2_sel connect issue_slots[7].iss_uop.op1_sel, slots_7.io.iss_uop.op1_sel connect issue_slots[7].iss_uop.imm_packed, slots_7.io.iss_uop.imm_packed connect issue_slots[7].iss_uop.pimm, slots_7.io.iss_uop.pimm connect issue_slots[7].iss_uop.imm_sel, slots_7.io.iss_uop.imm_sel connect issue_slots[7].iss_uop.imm_rename, slots_7.io.iss_uop.imm_rename connect issue_slots[7].iss_uop.taken, slots_7.io.iss_uop.taken connect issue_slots[7].iss_uop.pc_lob, slots_7.io.iss_uop.pc_lob connect issue_slots[7].iss_uop.edge_inst, slots_7.io.iss_uop.edge_inst connect issue_slots[7].iss_uop.ftq_idx, slots_7.io.iss_uop.ftq_idx connect issue_slots[7].iss_uop.is_mov, slots_7.io.iss_uop.is_mov connect issue_slots[7].iss_uop.is_rocc, slots_7.io.iss_uop.is_rocc connect issue_slots[7].iss_uop.is_sys_pc2epc, slots_7.io.iss_uop.is_sys_pc2epc connect issue_slots[7].iss_uop.is_eret, slots_7.io.iss_uop.is_eret connect issue_slots[7].iss_uop.is_amo, slots_7.io.iss_uop.is_amo connect issue_slots[7].iss_uop.is_sfence, slots_7.io.iss_uop.is_sfence connect issue_slots[7].iss_uop.is_fencei, slots_7.io.iss_uop.is_fencei connect issue_slots[7].iss_uop.is_fence, slots_7.io.iss_uop.is_fence connect issue_slots[7].iss_uop.is_sfb, slots_7.io.iss_uop.is_sfb connect issue_slots[7].iss_uop.br_type, slots_7.io.iss_uop.br_type connect issue_slots[7].iss_uop.br_tag, slots_7.io.iss_uop.br_tag connect issue_slots[7].iss_uop.br_mask, slots_7.io.iss_uop.br_mask connect issue_slots[7].iss_uop.dis_col_sel, slots_7.io.iss_uop.dis_col_sel connect issue_slots[7].iss_uop.iw_p3_bypass_hint, slots_7.io.iss_uop.iw_p3_bypass_hint connect issue_slots[7].iss_uop.iw_p2_bypass_hint, slots_7.io.iss_uop.iw_p2_bypass_hint connect issue_slots[7].iss_uop.iw_p1_bypass_hint, slots_7.io.iss_uop.iw_p1_bypass_hint connect issue_slots[7].iss_uop.iw_p2_speculative_child, slots_7.io.iss_uop.iw_p2_speculative_child connect issue_slots[7].iss_uop.iw_p1_speculative_child, slots_7.io.iss_uop.iw_p1_speculative_child connect issue_slots[7].iss_uop.iw_issued_partial_dgen, slots_7.io.iss_uop.iw_issued_partial_dgen connect issue_slots[7].iss_uop.iw_issued_partial_agen, slots_7.io.iss_uop.iw_issued_partial_agen connect issue_slots[7].iss_uop.iw_issued, slots_7.io.iss_uop.iw_issued connect issue_slots[7].iss_uop.fu_code[0], slots_7.io.iss_uop.fu_code[0] connect issue_slots[7].iss_uop.fu_code[1], slots_7.io.iss_uop.fu_code[1] connect issue_slots[7].iss_uop.fu_code[2], slots_7.io.iss_uop.fu_code[2] connect issue_slots[7].iss_uop.fu_code[3], slots_7.io.iss_uop.fu_code[3] connect issue_slots[7].iss_uop.fu_code[4], slots_7.io.iss_uop.fu_code[4] connect issue_slots[7].iss_uop.fu_code[5], slots_7.io.iss_uop.fu_code[5] connect issue_slots[7].iss_uop.fu_code[6], slots_7.io.iss_uop.fu_code[6] connect issue_slots[7].iss_uop.fu_code[7], slots_7.io.iss_uop.fu_code[7] connect issue_slots[7].iss_uop.fu_code[8], slots_7.io.iss_uop.fu_code[8] connect issue_slots[7].iss_uop.fu_code[9], slots_7.io.iss_uop.fu_code[9] connect issue_slots[7].iss_uop.iq_type[0], slots_7.io.iss_uop.iq_type[0] connect issue_slots[7].iss_uop.iq_type[1], slots_7.io.iss_uop.iq_type[1] connect issue_slots[7].iss_uop.iq_type[2], slots_7.io.iss_uop.iq_type[2] connect issue_slots[7].iss_uop.iq_type[3], slots_7.io.iss_uop.iq_type[3] connect issue_slots[7].iss_uop.debug_pc, slots_7.io.iss_uop.debug_pc connect issue_slots[7].iss_uop.is_rvc, slots_7.io.iss_uop.is_rvc connect issue_slots[7].iss_uop.debug_inst, slots_7.io.iss_uop.debug_inst connect issue_slots[7].iss_uop.inst, slots_7.io.iss_uop.inst connect slots_7.io.grant, issue_slots[7].grant connect issue_slots[7].request, slots_7.io.request connect issue_slots[7].will_be_valid, slots_7.io.will_be_valid connect issue_slots[7].valid, slots_7.io.valid connect slots_8.io.child_rebusys, issue_slots[8].child_rebusys connect slots_8.io.pred_wakeup_port.bits, issue_slots[8].pred_wakeup_port.bits connect slots_8.io.pred_wakeup_port.valid, issue_slots[8].pred_wakeup_port.valid connect slots_8.io.wakeup_ports[0].bits.rebusy, issue_slots[8].wakeup_ports[0].bits.rebusy connect slots_8.io.wakeup_ports[0].bits.speculative_mask, issue_slots[8].wakeup_ports[0].bits.speculative_mask connect slots_8.io.wakeup_ports[0].bits.bypassable, issue_slots[8].wakeup_ports[0].bits.bypassable connect slots_8.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[0].bits.uop.debug_tsrc connect slots_8.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[0].bits.uop.debug_fsrc connect slots_8.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_8.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[0].bits.uop.bp_debug_if connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_8.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_8.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[8].wakeup_ports[0].bits.uop.fp_typ connect slots_8.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[8].wakeup_ports[0].bits.uop.fp_rm connect slots_8.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[8].wakeup_ports[0].bits.uop.fp_val connect slots_8.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[8].wakeup_ports[0].bits.uop.fcn_op connect slots_8.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[0].bits.uop.fcn_dw connect slots_8.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[8].wakeup_ports[0].bits.uop.frs3_en connect slots_8.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_8.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_8.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[0].bits.uop.dst_rtype connect slots_8.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[8].wakeup_ports[0].bits.uop.lrs3 connect slots_8.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[8].wakeup_ports[0].bits.uop.lrs2 connect slots_8.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[8].wakeup_ports[0].bits.uop.lrs1 connect slots_8.io.wakeup_ports[0].bits.uop.ldst, issue_slots[8].wakeup_ports[0].bits.uop.ldst connect slots_8.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_8.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[0].bits.uop.csr_cmd connect slots_8.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[0].bits.uop.flush_on_commit connect slots_8.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[8].wakeup_ports[0].bits.uop.is_unique connect slots_8.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[8].wakeup_ports[0].bits.uop.uses_stq connect slots_8.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[0].bits.uop.uses_ldq connect slots_8.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[8].wakeup_ports[0].bits.uop.mem_signed connect slots_8.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[8].wakeup_ports[0].bits.uop.mem_size connect slots_8.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[0].bits.uop.mem_cmd connect slots_8.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[8].wakeup_ports[0].bits.uop.exc_cause connect slots_8.io.wakeup_ports[0].bits.uop.exception, issue_slots[8].wakeup_ports[0].bits.uop.exception connect slots_8.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[0].bits.uop.stale_pdst connect slots_8.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[0].bits.uop.ppred_busy connect slots_8.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs3_busy connect slots_8.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs2_busy connect slots_8.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[0].bits.uop.prs1_busy connect slots_8.io.wakeup_ports[0].bits.uop.ppred, issue_slots[8].wakeup_ports[0].bits.uop.ppred connect slots_8.io.wakeup_ports[0].bits.uop.prs3, issue_slots[8].wakeup_ports[0].bits.uop.prs3 connect slots_8.io.wakeup_ports[0].bits.uop.prs2, issue_slots[8].wakeup_ports[0].bits.uop.prs2 connect slots_8.io.wakeup_ports[0].bits.uop.prs1, issue_slots[8].wakeup_ports[0].bits.uop.prs1 connect slots_8.io.wakeup_ports[0].bits.uop.pdst, issue_slots[8].wakeup_ports[0].bits.uop.pdst connect slots_8.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[0].bits.uop.rxq_idx connect slots_8.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[8].wakeup_ports[0].bits.uop.stq_idx connect slots_8.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[0].bits.uop.ldq_idx connect slots_8.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[8].wakeup_ports[0].bits.uop.rob_idx connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_8.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_8.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[8].wakeup_ports[0].bits.uop.op2_sel connect slots_8.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[8].wakeup_ports[0].bits.uop.op1_sel connect slots_8.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[8].wakeup_ports[0].bits.uop.imm_packed connect slots_8.io.wakeup_ports[0].bits.uop.pimm, issue_slots[8].wakeup_ports[0].bits.uop.pimm connect slots_8.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[8].wakeup_ports[0].bits.uop.imm_sel connect slots_8.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[8].wakeup_ports[0].bits.uop.imm_rename connect slots_8.io.wakeup_ports[0].bits.uop.taken, issue_slots[8].wakeup_ports[0].bits.uop.taken connect slots_8.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[8].wakeup_ports[0].bits.uop.pc_lob connect slots_8.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[8].wakeup_ports[0].bits.uop.edge_inst connect slots_8.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[0].bits.uop.ftq_idx connect slots_8.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[8].wakeup_ports[0].bits.uop.is_mov connect slots_8.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[8].wakeup_ports[0].bits.uop.is_rocc connect slots_8.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_8.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[8].wakeup_ports[0].bits.uop.is_eret connect slots_8.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[8].wakeup_ports[0].bits.uop.is_amo connect slots_8.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[8].wakeup_ports[0].bits.uop.is_sfence connect slots_8.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[8].wakeup_ports[0].bits.uop.is_fencei connect slots_8.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[8].wakeup_ports[0].bits.uop.is_fence connect slots_8.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[8].wakeup_ports[0].bits.uop.is_sfb connect slots_8.io.wakeup_ports[0].bits.uop.br_type, issue_slots[8].wakeup_ports[0].bits.uop.br_type connect slots_8.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[8].wakeup_ports[0].bits.uop.br_tag connect slots_8.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[8].wakeup_ports[0].bits.uop.br_mask connect slots_8.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[0].bits.uop.dis_col_sel connect slots_8.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_8.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_8.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_8.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_8.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_8.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[8].wakeup_ports[0].bits.uop.iw_issued connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[0] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[1] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[2] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[3] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[4] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[5] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[6] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[7] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[8] connect slots_8.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[0].bits.uop.fu_code[9] connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[0] connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[1] connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[2] connect slots_8.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[0].bits.uop.iq_type[3] connect slots_8.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[8].wakeup_ports[0].bits.uop.debug_pc connect slots_8.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[8].wakeup_ports[0].bits.uop.is_rvc connect slots_8.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[8].wakeup_ports[0].bits.uop.debug_inst connect slots_8.io.wakeup_ports[0].bits.uop.inst, issue_slots[8].wakeup_ports[0].bits.uop.inst connect slots_8.io.wakeup_ports[0].valid, issue_slots[8].wakeup_ports[0].valid connect slots_8.io.wakeup_ports[1].bits.rebusy, issue_slots[8].wakeup_ports[1].bits.rebusy connect slots_8.io.wakeup_ports[1].bits.speculative_mask, issue_slots[8].wakeup_ports[1].bits.speculative_mask connect slots_8.io.wakeup_ports[1].bits.bypassable, issue_slots[8].wakeup_ports[1].bits.bypassable connect slots_8.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[8].wakeup_ports[1].bits.uop.debug_tsrc connect slots_8.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[8].wakeup_ports[1].bits.uop.debug_fsrc connect slots_8.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[8].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_8.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[8].wakeup_ports[1].bits.uop.bp_debug_if connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_8.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[8].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_8.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[8].wakeup_ports[1].bits.uop.fp_typ connect slots_8.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[8].wakeup_ports[1].bits.uop.fp_rm connect slots_8.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[8].wakeup_ports[1].bits.uop.fp_val connect slots_8.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[8].wakeup_ports[1].bits.uop.fcn_op connect slots_8.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[8].wakeup_ports[1].bits.uop.fcn_dw connect slots_8.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[8].wakeup_ports[1].bits.uop.frs3_en connect slots_8.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[8].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_8.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[8].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_8.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[8].wakeup_ports[1].bits.uop.dst_rtype connect slots_8.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[8].wakeup_ports[1].bits.uop.lrs3 connect slots_8.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[8].wakeup_ports[1].bits.uop.lrs2 connect slots_8.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[8].wakeup_ports[1].bits.uop.lrs1 connect slots_8.io.wakeup_ports[1].bits.uop.ldst, issue_slots[8].wakeup_ports[1].bits.uop.ldst connect slots_8.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[8].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_8.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[8].wakeup_ports[1].bits.uop.csr_cmd connect slots_8.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[8].wakeup_ports[1].bits.uop.flush_on_commit connect slots_8.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[8].wakeup_ports[1].bits.uop.is_unique connect slots_8.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[8].wakeup_ports[1].bits.uop.uses_stq connect slots_8.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[8].wakeup_ports[1].bits.uop.uses_ldq connect slots_8.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[8].wakeup_ports[1].bits.uop.mem_signed connect slots_8.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[8].wakeup_ports[1].bits.uop.mem_size connect slots_8.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[8].wakeup_ports[1].bits.uop.mem_cmd connect slots_8.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[8].wakeup_ports[1].bits.uop.exc_cause connect slots_8.io.wakeup_ports[1].bits.uop.exception, issue_slots[8].wakeup_ports[1].bits.uop.exception connect slots_8.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[8].wakeup_ports[1].bits.uop.stale_pdst connect slots_8.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[8].wakeup_ports[1].bits.uop.ppred_busy connect slots_8.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs3_busy connect slots_8.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs2_busy connect slots_8.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[8].wakeup_ports[1].bits.uop.prs1_busy connect slots_8.io.wakeup_ports[1].bits.uop.ppred, issue_slots[8].wakeup_ports[1].bits.uop.ppred connect slots_8.io.wakeup_ports[1].bits.uop.prs3, issue_slots[8].wakeup_ports[1].bits.uop.prs3 connect slots_8.io.wakeup_ports[1].bits.uop.prs2, issue_slots[8].wakeup_ports[1].bits.uop.prs2 connect slots_8.io.wakeup_ports[1].bits.uop.prs1, issue_slots[8].wakeup_ports[1].bits.uop.prs1 connect slots_8.io.wakeup_ports[1].bits.uop.pdst, issue_slots[8].wakeup_ports[1].bits.uop.pdst connect slots_8.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[8].wakeup_ports[1].bits.uop.rxq_idx connect slots_8.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[8].wakeup_ports[1].bits.uop.stq_idx connect slots_8.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[8].wakeup_ports[1].bits.uop.ldq_idx connect slots_8.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[8].wakeup_ports[1].bits.uop.rob_idx connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_8.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_8.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[8].wakeup_ports[1].bits.uop.op2_sel connect slots_8.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[8].wakeup_ports[1].bits.uop.op1_sel connect slots_8.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[8].wakeup_ports[1].bits.uop.imm_packed connect slots_8.io.wakeup_ports[1].bits.uop.pimm, issue_slots[8].wakeup_ports[1].bits.uop.pimm connect slots_8.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[8].wakeup_ports[1].bits.uop.imm_sel connect slots_8.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[8].wakeup_ports[1].bits.uop.imm_rename connect slots_8.io.wakeup_ports[1].bits.uop.taken, issue_slots[8].wakeup_ports[1].bits.uop.taken connect slots_8.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[8].wakeup_ports[1].bits.uop.pc_lob connect slots_8.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[8].wakeup_ports[1].bits.uop.edge_inst connect slots_8.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[8].wakeup_ports[1].bits.uop.ftq_idx connect slots_8.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[8].wakeup_ports[1].bits.uop.is_mov connect slots_8.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[8].wakeup_ports[1].bits.uop.is_rocc connect slots_8.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[8].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_8.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[8].wakeup_ports[1].bits.uop.is_eret connect slots_8.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[8].wakeup_ports[1].bits.uop.is_amo connect slots_8.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[8].wakeup_ports[1].bits.uop.is_sfence connect slots_8.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[8].wakeup_ports[1].bits.uop.is_fencei connect slots_8.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[8].wakeup_ports[1].bits.uop.is_fence connect slots_8.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[8].wakeup_ports[1].bits.uop.is_sfb connect slots_8.io.wakeup_ports[1].bits.uop.br_type, issue_slots[8].wakeup_ports[1].bits.uop.br_type connect slots_8.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[8].wakeup_ports[1].bits.uop.br_tag connect slots_8.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[8].wakeup_ports[1].bits.uop.br_mask connect slots_8.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[8].wakeup_ports[1].bits.uop.dis_col_sel connect slots_8.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_8.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_8.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_8.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_8.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_8.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[8].wakeup_ports[1].bits.uop.iw_issued connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[0] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[1] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[2] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[3] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[4] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[5] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[6] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[7] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[8] connect slots_8.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[8].wakeup_ports[1].bits.uop.fu_code[9] connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[0] connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[1] connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[2] connect slots_8.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[8].wakeup_ports[1].bits.uop.iq_type[3] connect slots_8.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[8].wakeup_ports[1].bits.uop.debug_pc connect slots_8.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[8].wakeup_ports[1].bits.uop.is_rvc connect slots_8.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[8].wakeup_ports[1].bits.uop.debug_inst connect slots_8.io.wakeup_ports[1].bits.uop.inst, issue_slots[8].wakeup_ports[1].bits.uop.inst connect slots_8.io.wakeup_ports[1].valid, issue_slots[8].wakeup_ports[1].valid connect slots_8.io.squash_grant, issue_slots[8].squash_grant connect slots_8.io.clear, issue_slots[8].clear connect slots_8.io.kill, issue_slots[8].kill connect slots_8.io.brupdate.b2.target_offset, issue_slots[8].brupdate.b2.target_offset connect slots_8.io.brupdate.b2.jalr_target, issue_slots[8].brupdate.b2.jalr_target connect slots_8.io.brupdate.b2.pc_sel, issue_slots[8].brupdate.b2.pc_sel connect slots_8.io.brupdate.b2.cfi_type, issue_slots[8].brupdate.b2.cfi_type connect slots_8.io.brupdate.b2.taken, issue_slots[8].brupdate.b2.taken connect slots_8.io.brupdate.b2.mispredict, issue_slots[8].brupdate.b2.mispredict connect slots_8.io.brupdate.b2.uop.debug_tsrc, issue_slots[8].brupdate.b2.uop.debug_tsrc connect slots_8.io.brupdate.b2.uop.debug_fsrc, issue_slots[8].brupdate.b2.uop.debug_fsrc connect slots_8.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[8].brupdate.b2.uop.bp_xcpt_if connect slots_8.io.brupdate.b2.uop.bp_debug_if, issue_slots[8].brupdate.b2.uop.bp_debug_if connect slots_8.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[8].brupdate.b2.uop.xcpt_ma_if connect slots_8.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[8].brupdate.b2.uop.xcpt_ae_if connect slots_8.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[8].brupdate.b2.uop.xcpt_pf_if connect slots_8.io.brupdate.b2.uop.fp_typ, issue_slots[8].brupdate.b2.uop.fp_typ connect slots_8.io.brupdate.b2.uop.fp_rm, issue_slots[8].brupdate.b2.uop.fp_rm connect slots_8.io.brupdate.b2.uop.fp_val, issue_slots[8].brupdate.b2.uop.fp_val connect slots_8.io.brupdate.b2.uop.fcn_op, issue_slots[8].brupdate.b2.uop.fcn_op connect slots_8.io.brupdate.b2.uop.fcn_dw, issue_slots[8].brupdate.b2.uop.fcn_dw connect slots_8.io.brupdate.b2.uop.frs3_en, issue_slots[8].brupdate.b2.uop.frs3_en connect slots_8.io.brupdate.b2.uop.lrs2_rtype, issue_slots[8].brupdate.b2.uop.lrs2_rtype connect slots_8.io.brupdate.b2.uop.lrs1_rtype, issue_slots[8].brupdate.b2.uop.lrs1_rtype connect slots_8.io.brupdate.b2.uop.dst_rtype, issue_slots[8].brupdate.b2.uop.dst_rtype connect slots_8.io.brupdate.b2.uop.lrs3, issue_slots[8].brupdate.b2.uop.lrs3 connect slots_8.io.brupdate.b2.uop.lrs2, issue_slots[8].brupdate.b2.uop.lrs2 connect slots_8.io.brupdate.b2.uop.lrs1, issue_slots[8].brupdate.b2.uop.lrs1 connect slots_8.io.brupdate.b2.uop.ldst, issue_slots[8].brupdate.b2.uop.ldst connect slots_8.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[8].brupdate.b2.uop.ldst_is_rs1 connect slots_8.io.brupdate.b2.uop.csr_cmd, issue_slots[8].brupdate.b2.uop.csr_cmd connect slots_8.io.brupdate.b2.uop.flush_on_commit, issue_slots[8].brupdate.b2.uop.flush_on_commit connect slots_8.io.brupdate.b2.uop.is_unique, issue_slots[8].brupdate.b2.uop.is_unique connect slots_8.io.brupdate.b2.uop.uses_stq, issue_slots[8].brupdate.b2.uop.uses_stq connect slots_8.io.brupdate.b2.uop.uses_ldq, issue_slots[8].brupdate.b2.uop.uses_ldq connect slots_8.io.brupdate.b2.uop.mem_signed, issue_slots[8].brupdate.b2.uop.mem_signed connect slots_8.io.brupdate.b2.uop.mem_size, issue_slots[8].brupdate.b2.uop.mem_size connect slots_8.io.brupdate.b2.uop.mem_cmd, issue_slots[8].brupdate.b2.uop.mem_cmd connect slots_8.io.brupdate.b2.uop.exc_cause, issue_slots[8].brupdate.b2.uop.exc_cause connect slots_8.io.brupdate.b2.uop.exception, issue_slots[8].brupdate.b2.uop.exception connect slots_8.io.brupdate.b2.uop.stale_pdst, issue_slots[8].brupdate.b2.uop.stale_pdst connect slots_8.io.brupdate.b2.uop.ppred_busy, issue_slots[8].brupdate.b2.uop.ppred_busy connect slots_8.io.brupdate.b2.uop.prs3_busy, issue_slots[8].brupdate.b2.uop.prs3_busy connect slots_8.io.brupdate.b2.uop.prs2_busy, issue_slots[8].brupdate.b2.uop.prs2_busy connect slots_8.io.brupdate.b2.uop.prs1_busy, issue_slots[8].brupdate.b2.uop.prs1_busy connect slots_8.io.brupdate.b2.uop.ppred, issue_slots[8].brupdate.b2.uop.ppred connect slots_8.io.brupdate.b2.uop.prs3, issue_slots[8].brupdate.b2.uop.prs3 connect slots_8.io.brupdate.b2.uop.prs2, issue_slots[8].brupdate.b2.uop.prs2 connect slots_8.io.brupdate.b2.uop.prs1, issue_slots[8].brupdate.b2.uop.prs1 connect slots_8.io.brupdate.b2.uop.pdst, issue_slots[8].brupdate.b2.uop.pdst connect slots_8.io.brupdate.b2.uop.rxq_idx, issue_slots[8].brupdate.b2.uop.rxq_idx connect slots_8.io.brupdate.b2.uop.stq_idx, issue_slots[8].brupdate.b2.uop.stq_idx connect slots_8.io.brupdate.b2.uop.ldq_idx, issue_slots[8].brupdate.b2.uop.ldq_idx connect slots_8.io.brupdate.b2.uop.rob_idx, issue_slots[8].brupdate.b2.uop.rob_idx connect slots_8.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[8].brupdate.b2.uop.fp_ctrl.vec connect slots_8.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[8].brupdate.b2.uop.fp_ctrl.wflags connect slots_8.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[8].brupdate.b2.uop.fp_ctrl.sqrt connect slots_8.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[8].brupdate.b2.uop.fp_ctrl.div connect slots_8.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[8].brupdate.b2.uop.fp_ctrl.fma connect slots_8.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[8].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_8.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[8].brupdate.b2.uop.fp_ctrl.toint connect slots_8.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[8].brupdate.b2.uop.fp_ctrl.fromint connect slots_8.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_8.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_8.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[8].brupdate.b2.uop.fp_ctrl.swap23 connect slots_8.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[8].brupdate.b2.uop.fp_ctrl.swap12 connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren3 connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren2 connect slots_8.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[8].brupdate.b2.uop.fp_ctrl.ren1 connect slots_8.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[8].brupdate.b2.uop.fp_ctrl.wen connect slots_8.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[8].brupdate.b2.uop.fp_ctrl.ldst connect slots_8.io.brupdate.b2.uop.op2_sel, issue_slots[8].brupdate.b2.uop.op2_sel connect slots_8.io.brupdate.b2.uop.op1_sel, issue_slots[8].brupdate.b2.uop.op1_sel connect slots_8.io.brupdate.b2.uop.imm_packed, issue_slots[8].brupdate.b2.uop.imm_packed connect slots_8.io.brupdate.b2.uop.pimm, issue_slots[8].brupdate.b2.uop.pimm connect slots_8.io.brupdate.b2.uop.imm_sel, issue_slots[8].brupdate.b2.uop.imm_sel connect slots_8.io.brupdate.b2.uop.imm_rename, issue_slots[8].brupdate.b2.uop.imm_rename connect slots_8.io.brupdate.b2.uop.taken, issue_slots[8].brupdate.b2.uop.taken connect slots_8.io.brupdate.b2.uop.pc_lob, issue_slots[8].brupdate.b2.uop.pc_lob connect slots_8.io.brupdate.b2.uop.edge_inst, issue_slots[8].brupdate.b2.uop.edge_inst connect slots_8.io.brupdate.b2.uop.ftq_idx, issue_slots[8].brupdate.b2.uop.ftq_idx connect slots_8.io.brupdate.b2.uop.is_mov, issue_slots[8].brupdate.b2.uop.is_mov connect slots_8.io.brupdate.b2.uop.is_rocc, issue_slots[8].brupdate.b2.uop.is_rocc connect slots_8.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[8].brupdate.b2.uop.is_sys_pc2epc connect slots_8.io.brupdate.b2.uop.is_eret, issue_slots[8].brupdate.b2.uop.is_eret connect slots_8.io.brupdate.b2.uop.is_amo, issue_slots[8].brupdate.b2.uop.is_amo connect slots_8.io.brupdate.b2.uop.is_sfence, issue_slots[8].brupdate.b2.uop.is_sfence connect slots_8.io.brupdate.b2.uop.is_fencei, issue_slots[8].brupdate.b2.uop.is_fencei connect slots_8.io.brupdate.b2.uop.is_fence, issue_slots[8].brupdate.b2.uop.is_fence connect slots_8.io.brupdate.b2.uop.is_sfb, issue_slots[8].brupdate.b2.uop.is_sfb connect slots_8.io.brupdate.b2.uop.br_type, issue_slots[8].brupdate.b2.uop.br_type connect slots_8.io.brupdate.b2.uop.br_tag, issue_slots[8].brupdate.b2.uop.br_tag connect slots_8.io.brupdate.b2.uop.br_mask, issue_slots[8].brupdate.b2.uop.br_mask connect slots_8.io.brupdate.b2.uop.dis_col_sel, issue_slots[8].brupdate.b2.uop.dis_col_sel connect slots_8.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p3_bypass_hint connect slots_8.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p2_bypass_hint connect slots_8.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[8].brupdate.b2.uop.iw_p1_bypass_hint connect slots_8.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[8].brupdate.b2.uop.iw_p2_speculative_child connect slots_8.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[8].brupdate.b2.uop.iw_p1_speculative_child connect slots_8.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[8].brupdate.b2.uop.iw_issued_partial_dgen connect slots_8.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[8].brupdate.b2.uop.iw_issued_partial_agen connect slots_8.io.brupdate.b2.uop.iw_issued, issue_slots[8].brupdate.b2.uop.iw_issued connect slots_8.io.brupdate.b2.uop.fu_code[0], issue_slots[8].brupdate.b2.uop.fu_code[0] connect slots_8.io.brupdate.b2.uop.fu_code[1], issue_slots[8].brupdate.b2.uop.fu_code[1] connect slots_8.io.brupdate.b2.uop.fu_code[2], issue_slots[8].brupdate.b2.uop.fu_code[2] connect slots_8.io.brupdate.b2.uop.fu_code[3], issue_slots[8].brupdate.b2.uop.fu_code[3] connect slots_8.io.brupdate.b2.uop.fu_code[4], issue_slots[8].brupdate.b2.uop.fu_code[4] connect slots_8.io.brupdate.b2.uop.fu_code[5], issue_slots[8].brupdate.b2.uop.fu_code[5] connect slots_8.io.brupdate.b2.uop.fu_code[6], issue_slots[8].brupdate.b2.uop.fu_code[6] connect slots_8.io.brupdate.b2.uop.fu_code[7], issue_slots[8].brupdate.b2.uop.fu_code[7] connect slots_8.io.brupdate.b2.uop.fu_code[8], issue_slots[8].brupdate.b2.uop.fu_code[8] connect slots_8.io.brupdate.b2.uop.fu_code[9], issue_slots[8].brupdate.b2.uop.fu_code[9] connect slots_8.io.brupdate.b2.uop.iq_type[0], issue_slots[8].brupdate.b2.uop.iq_type[0] connect slots_8.io.brupdate.b2.uop.iq_type[1], issue_slots[8].brupdate.b2.uop.iq_type[1] connect slots_8.io.brupdate.b2.uop.iq_type[2], issue_slots[8].brupdate.b2.uop.iq_type[2] connect slots_8.io.brupdate.b2.uop.iq_type[3], issue_slots[8].brupdate.b2.uop.iq_type[3] connect slots_8.io.brupdate.b2.uop.debug_pc, issue_slots[8].brupdate.b2.uop.debug_pc connect slots_8.io.brupdate.b2.uop.is_rvc, issue_slots[8].brupdate.b2.uop.is_rvc connect slots_8.io.brupdate.b2.uop.debug_inst, issue_slots[8].brupdate.b2.uop.debug_inst connect slots_8.io.brupdate.b2.uop.inst, issue_slots[8].brupdate.b2.uop.inst connect slots_8.io.brupdate.b1.mispredict_mask, issue_slots[8].brupdate.b1.mispredict_mask connect slots_8.io.brupdate.b1.resolve_mask, issue_slots[8].brupdate.b1.resolve_mask connect issue_slots[8].out_uop.debug_tsrc, slots_8.io.out_uop.debug_tsrc connect issue_slots[8].out_uop.debug_fsrc, slots_8.io.out_uop.debug_fsrc connect issue_slots[8].out_uop.bp_xcpt_if, slots_8.io.out_uop.bp_xcpt_if connect issue_slots[8].out_uop.bp_debug_if, slots_8.io.out_uop.bp_debug_if connect issue_slots[8].out_uop.xcpt_ma_if, slots_8.io.out_uop.xcpt_ma_if connect issue_slots[8].out_uop.xcpt_ae_if, slots_8.io.out_uop.xcpt_ae_if connect issue_slots[8].out_uop.xcpt_pf_if, slots_8.io.out_uop.xcpt_pf_if connect issue_slots[8].out_uop.fp_typ, slots_8.io.out_uop.fp_typ connect issue_slots[8].out_uop.fp_rm, slots_8.io.out_uop.fp_rm connect issue_slots[8].out_uop.fp_val, slots_8.io.out_uop.fp_val connect issue_slots[8].out_uop.fcn_op, slots_8.io.out_uop.fcn_op connect issue_slots[8].out_uop.fcn_dw, slots_8.io.out_uop.fcn_dw connect issue_slots[8].out_uop.frs3_en, slots_8.io.out_uop.frs3_en connect issue_slots[8].out_uop.lrs2_rtype, slots_8.io.out_uop.lrs2_rtype connect issue_slots[8].out_uop.lrs1_rtype, slots_8.io.out_uop.lrs1_rtype connect issue_slots[8].out_uop.dst_rtype, slots_8.io.out_uop.dst_rtype connect issue_slots[8].out_uop.lrs3, slots_8.io.out_uop.lrs3 connect issue_slots[8].out_uop.lrs2, slots_8.io.out_uop.lrs2 connect issue_slots[8].out_uop.lrs1, slots_8.io.out_uop.lrs1 connect issue_slots[8].out_uop.ldst, slots_8.io.out_uop.ldst connect issue_slots[8].out_uop.ldst_is_rs1, slots_8.io.out_uop.ldst_is_rs1 connect issue_slots[8].out_uop.csr_cmd, slots_8.io.out_uop.csr_cmd connect issue_slots[8].out_uop.flush_on_commit, slots_8.io.out_uop.flush_on_commit connect issue_slots[8].out_uop.is_unique, slots_8.io.out_uop.is_unique connect issue_slots[8].out_uop.uses_stq, slots_8.io.out_uop.uses_stq connect issue_slots[8].out_uop.uses_ldq, slots_8.io.out_uop.uses_ldq connect issue_slots[8].out_uop.mem_signed, slots_8.io.out_uop.mem_signed connect issue_slots[8].out_uop.mem_size, slots_8.io.out_uop.mem_size connect issue_slots[8].out_uop.mem_cmd, slots_8.io.out_uop.mem_cmd connect issue_slots[8].out_uop.exc_cause, slots_8.io.out_uop.exc_cause connect issue_slots[8].out_uop.exception, slots_8.io.out_uop.exception connect issue_slots[8].out_uop.stale_pdst, slots_8.io.out_uop.stale_pdst connect issue_slots[8].out_uop.ppred_busy, slots_8.io.out_uop.ppred_busy connect issue_slots[8].out_uop.prs3_busy, slots_8.io.out_uop.prs3_busy connect issue_slots[8].out_uop.prs2_busy, slots_8.io.out_uop.prs2_busy connect issue_slots[8].out_uop.prs1_busy, slots_8.io.out_uop.prs1_busy connect issue_slots[8].out_uop.ppred, slots_8.io.out_uop.ppred connect issue_slots[8].out_uop.prs3, slots_8.io.out_uop.prs3 connect issue_slots[8].out_uop.prs2, slots_8.io.out_uop.prs2 connect issue_slots[8].out_uop.prs1, slots_8.io.out_uop.prs1 connect issue_slots[8].out_uop.pdst, slots_8.io.out_uop.pdst connect issue_slots[8].out_uop.rxq_idx, slots_8.io.out_uop.rxq_idx connect issue_slots[8].out_uop.stq_idx, slots_8.io.out_uop.stq_idx connect issue_slots[8].out_uop.ldq_idx, slots_8.io.out_uop.ldq_idx connect issue_slots[8].out_uop.rob_idx, slots_8.io.out_uop.rob_idx connect issue_slots[8].out_uop.fp_ctrl.vec, slots_8.io.out_uop.fp_ctrl.vec connect issue_slots[8].out_uop.fp_ctrl.wflags, slots_8.io.out_uop.fp_ctrl.wflags connect issue_slots[8].out_uop.fp_ctrl.sqrt, slots_8.io.out_uop.fp_ctrl.sqrt connect issue_slots[8].out_uop.fp_ctrl.div, slots_8.io.out_uop.fp_ctrl.div connect issue_slots[8].out_uop.fp_ctrl.fma, slots_8.io.out_uop.fp_ctrl.fma connect issue_slots[8].out_uop.fp_ctrl.fastpipe, slots_8.io.out_uop.fp_ctrl.fastpipe connect issue_slots[8].out_uop.fp_ctrl.toint, slots_8.io.out_uop.fp_ctrl.toint connect issue_slots[8].out_uop.fp_ctrl.fromint, slots_8.io.out_uop.fp_ctrl.fromint connect issue_slots[8].out_uop.fp_ctrl.typeTagOut, slots_8.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[8].out_uop.fp_ctrl.typeTagIn, slots_8.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[8].out_uop.fp_ctrl.swap23, slots_8.io.out_uop.fp_ctrl.swap23 connect issue_slots[8].out_uop.fp_ctrl.swap12, slots_8.io.out_uop.fp_ctrl.swap12 connect issue_slots[8].out_uop.fp_ctrl.ren3, slots_8.io.out_uop.fp_ctrl.ren3 connect issue_slots[8].out_uop.fp_ctrl.ren2, slots_8.io.out_uop.fp_ctrl.ren2 connect issue_slots[8].out_uop.fp_ctrl.ren1, slots_8.io.out_uop.fp_ctrl.ren1 connect issue_slots[8].out_uop.fp_ctrl.wen, slots_8.io.out_uop.fp_ctrl.wen connect issue_slots[8].out_uop.fp_ctrl.ldst, slots_8.io.out_uop.fp_ctrl.ldst connect issue_slots[8].out_uop.op2_sel, slots_8.io.out_uop.op2_sel connect issue_slots[8].out_uop.op1_sel, slots_8.io.out_uop.op1_sel connect issue_slots[8].out_uop.imm_packed, slots_8.io.out_uop.imm_packed connect issue_slots[8].out_uop.pimm, slots_8.io.out_uop.pimm connect issue_slots[8].out_uop.imm_sel, slots_8.io.out_uop.imm_sel connect issue_slots[8].out_uop.imm_rename, slots_8.io.out_uop.imm_rename connect issue_slots[8].out_uop.taken, slots_8.io.out_uop.taken connect issue_slots[8].out_uop.pc_lob, slots_8.io.out_uop.pc_lob connect issue_slots[8].out_uop.edge_inst, slots_8.io.out_uop.edge_inst connect issue_slots[8].out_uop.ftq_idx, slots_8.io.out_uop.ftq_idx connect issue_slots[8].out_uop.is_mov, slots_8.io.out_uop.is_mov connect issue_slots[8].out_uop.is_rocc, slots_8.io.out_uop.is_rocc connect issue_slots[8].out_uop.is_sys_pc2epc, slots_8.io.out_uop.is_sys_pc2epc connect issue_slots[8].out_uop.is_eret, slots_8.io.out_uop.is_eret connect issue_slots[8].out_uop.is_amo, slots_8.io.out_uop.is_amo connect issue_slots[8].out_uop.is_sfence, slots_8.io.out_uop.is_sfence connect issue_slots[8].out_uop.is_fencei, slots_8.io.out_uop.is_fencei connect issue_slots[8].out_uop.is_fence, slots_8.io.out_uop.is_fence connect issue_slots[8].out_uop.is_sfb, slots_8.io.out_uop.is_sfb connect issue_slots[8].out_uop.br_type, slots_8.io.out_uop.br_type connect issue_slots[8].out_uop.br_tag, slots_8.io.out_uop.br_tag connect issue_slots[8].out_uop.br_mask, slots_8.io.out_uop.br_mask connect issue_slots[8].out_uop.dis_col_sel, slots_8.io.out_uop.dis_col_sel connect issue_slots[8].out_uop.iw_p3_bypass_hint, slots_8.io.out_uop.iw_p3_bypass_hint connect issue_slots[8].out_uop.iw_p2_bypass_hint, slots_8.io.out_uop.iw_p2_bypass_hint connect issue_slots[8].out_uop.iw_p1_bypass_hint, slots_8.io.out_uop.iw_p1_bypass_hint connect issue_slots[8].out_uop.iw_p2_speculative_child, slots_8.io.out_uop.iw_p2_speculative_child connect issue_slots[8].out_uop.iw_p1_speculative_child, slots_8.io.out_uop.iw_p1_speculative_child connect issue_slots[8].out_uop.iw_issued_partial_dgen, slots_8.io.out_uop.iw_issued_partial_dgen connect issue_slots[8].out_uop.iw_issued_partial_agen, slots_8.io.out_uop.iw_issued_partial_agen connect issue_slots[8].out_uop.iw_issued, slots_8.io.out_uop.iw_issued connect issue_slots[8].out_uop.fu_code[0], slots_8.io.out_uop.fu_code[0] connect issue_slots[8].out_uop.fu_code[1], slots_8.io.out_uop.fu_code[1] connect issue_slots[8].out_uop.fu_code[2], slots_8.io.out_uop.fu_code[2] connect issue_slots[8].out_uop.fu_code[3], slots_8.io.out_uop.fu_code[3] connect issue_slots[8].out_uop.fu_code[4], slots_8.io.out_uop.fu_code[4] connect issue_slots[8].out_uop.fu_code[5], slots_8.io.out_uop.fu_code[5] connect issue_slots[8].out_uop.fu_code[6], slots_8.io.out_uop.fu_code[6] connect issue_slots[8].out_uop.fu_code[7], slots_8.io.out_uop.fu_code[7] connect issue_slots[8].out_uop.fu_code[8], slots_8.io.out_uop.fu_code[8] connect issue_slots[8].out_uop.fu_code[9], slots_8.io.out_uop.fu_code[9] connect issue_slots[8].out_uop.iq_type[0], slots_8.io.out_uop.iq_type[0] connect issue_slots[8].out_uop.iq_type[1], slots_8.io.out_uop.iq_type[1] connect issue_slots[8].out_uop.iq_type[2], slots_8.io.out_uop.iq_type[2] connect issue_slots[8].out_uop.iq_type[3], slots_8.io.out_uop.iq_type[3] connect issue_slots[8].out_uop.debug_pc, slots_8.io.out_uop.debug_pc connect issue_slots[8].out_uop.is_rvc, slots_8.io.out_uop.is_rvc connect issue_slots[8].out_uop.debug_inst, slots_8.io.out_uop.debug_inst connect issue_slots[8].out_uop.inst, slots_8.io.out_uop.inst connect slots_8.io.in_uop.bits.debug_tsrc, issue_slots[8].in_uop.bits.debug_tsrc connect slots_8.io.in_uop.bits.debug_fsrc, issue_slots[8].in_uop.bits.debug_fsrc connect slots_8.io.in_uop.bits.bp_xcpt_if, issue_slots[8].in_uop.bits.bp_xcpt_if connect slots_8.io.in_uop.bits.bp_debug_if, issue_slots[8].in_uop.bits.bp_debug_if connect slots_8.io.in_uop.bits.xcpt_ma_if, issue_slots[8].in_uop.bits.xcpt_ma_if connect slots_8.io.in_uop.bits.xcpt_ae_if, issue_slots[8].in_uop.bits.xcpt_ae_if connect slots_8.io.in_uop.bits.xcpt_pf_if, issue_slots[8].in_uop.bits.xcpt_pf_if connect slots_8.io.in_uop.bits.fp_typ, issue_slots[8].in_uop.bits.fp_typ connect slots_8.io.in_uop.bits.fp_rm, issue_slots[8].in_uop.bits.fp_rm connect slots_8.io.in_uop.bits.fp_val, issue_slots[8].in_uop.bits.fp_val connect slots_8.io.in_uop.bits.fcn_op, issue_slots[8].in_uop.bits.fcn_op connect slots_8.io.in_uop.bits.fcn_dw, issue_slots[8].in_uop.bits.fcn_dw connect slots_8.io.in_uop.bits.frs3_en, issue_slots[8].in_uop.bits.frs3_en connect slots_8.io.in_uop.bits.lrs2_rtype, issue_slots[8].in_uop.bits.lrs2_rtype connect slots_8.io.in_uop.bits.lrs1_rtype, issue_slots[8].in_uop.bits.lrs1_rtype connect slots_8.io.in_uop.bits.dst_rtype, issue_slots[8].in_uop.bits.dst_rtype connect slots_8.io.in_uop.bits.lrs3, issue_slots[8].in_uop.bits.lrs3 connect slots_8.io.in_uop.bits.lrs2, issue_slots[8].in_uop.bits.lrs2 connect slots_8.io.in_uop.bits.lrs1, issue_slots[8].in_uop.bits.lrs1 connect slots_8.io.in_uop.bits.ldst, issue_slots[8].in_uop.bits.ldst connect slots_8.io.in_uop.bits.ldst_is_rs1, issue_slots[8].in_uop.bits.ldst_is_rs1 connect slots_8.io.in_uop.bits.csr_cmd, issue_slots[8].in_uop.bits.csr_cmd connect slots_8.io.in_uop.bits.flush_on_commit, issue_slots[8].in_uop.bits.flush_on_commit connect slots_8.io.in_uop.bits.is_unique, issue_slots[8].in_uop.bits.is_unique connect slots_8.io.in_uop.bits.uses_stq, issue_slots[8].in_uop.bits.uses_stq connect slots_8.io.in_uop.bits.uses_ldq, issue_slots[8].in_uop.bits.uses_ldq connect slots_8.io.in_uop.bits.mem_signed, issue_slots[8].in_uop.bits.mem_signed connect slots_8.io.in_uop.bits.mem_size, issue_slots[8].in_uop.bits.mem_size connect slots_8.io.in_uop.bits.mem_cmd, issue_slots[8].in_uop.bits.mem_cmd connect slots_8.io.in_uop.bits.exc_cause, issue_slots[8].in_uop.bits.exc_cause connect slots_8.io.in_uop.bits.exception, issue_slots[8].in_uop.bits.exception connect slots_8.io.in_uop.bits.stale_pdst, issue_slots[8].in_uop.bits.stale_pdst connect slots_8.io.in_uop.bits.ppred_busy, issue_slots[8].in_uop.bits.ppred_busy connect slots_8.io.in_uop.bits.prs3_busy, issue_slots[8].in_uop.bits.prs3_busy connect slots_8.io.in_uop.bits.prs2_busy, issue_slots[8].in_uop.bits.prs2_busy connect slots_8.io.in_uop.bits.prs1_busy, issue_slots[8].in_uop.bits.prs1_busy connect slots_8.io.in_uop.bits.ppred, issue_slots[8].in_uop.bits.ppred connect slots_8.io.in_uop.bits.prs3, issue_slots[8].in_uop.bits.prs3 connect slots_8.io.in_uop.bits.prs2, issue_slots[8].in_uop.bits.prs2 connect slots_8.io.in_uop.bits.prs1, issue_slots[8].in_uop.bits.prs1 connect slots_8.io.in_uop.bits.pdst, issue_slots[8].in_uop.bits.pdst connect slots_8.io.in_uop.bits.rxq_idx, issue_slots[8].in_uop.bits.rxq_idx connect slots_8.io.in_uop.bits.stq_idx, issue_slots[8].in_uop.bits.stq_idx connect slots_8.io.in_uop.bits.ldq_idx, issue_slots[8].in_uop.bits.ldq_idx connect slots_8.io.in_uop.bits.rob_idx, issue_slots[8].in_uop.bits.rob_idx connect slots_8.io.in_uop.bits.fp_ctrl.vec, issue_slots[8].in_uop.bits.fp_ctrl.vec connect slots_8.io.in_uop.bits.fp_ctrl.wflags, issue_slots[8].in_uop.bits.fp_ctrl.wflags connect slots_8.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[8].in_uop.bits.fp_ctrl.sqrt connect slots_8.io.in_uop.bits.fp_ctrl.div, issue_slots[8].in_uop.bits.fp_ctrl.div connect slots_8.io.in_uop.bits.fp_ctrl.fma, issue_slots[8].in_uop.bits.fp_ctrl.fma connect slots_8.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].in_uop.bits.fp_ctrl.fastpipe connect slots_8.io.in_uop.bits.fp_ctrl.toint, issue_slots[8].in_uop.bits.fp_ctrl.toint connect slots_8.io.in_uop.bits.fp_ctrl.fromint, issue_slots[8].in_uop.bits.fp_ctrl.fromint connect slots_8.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut connect slots_8.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn connect slots_8.io.in_uop.bits.fp_ctrl.swap23, issue_slots[8].in_uop.bits.fp_ctrl.swap23 connect slots_8.io.in_uop.bits.fp_ctrl.swap12, issue_slots[8].in_uop.bits.fp_ctrl.swap12 connect slots_8.io.in_uop.bits.fp_ctrl.ren3, issue_slots[8].in_uop.bits.fp_ctrl.ren3 connect slots_8.io.in_uop.bits.fp_ctrl.ren2, issue_slots[8].in_uop.bits.fp_ctrl.ren2 connect slots_8.io.in_uop.bits.fp_ctrl.ren1, issue_slots[8].in_uop.bits.fp_ctrl.ren1 connect slots_8.io.in_uop.bits.fp_ctrl.wen, issue_slots[8].in_uop.bits.fp_ctrl.wen connect slots_8.io.in_uop.bits.fp_ctrl.ldst, issue_slots[8].in_uop.bits.fp_ctrl.ldst connect slots_8.io.in_uop.bits.op2_sel, issue_slots[8].in_uop.bits.op2_sel connect slots_8.io.in_uop.bits.op1_sel, issue_slots[8].in_uop.bits.op1_sel connect slots_8.io.in_uop.bits.imm_packed, issue_slots[8].in_uop.bits.imm_packed connect slots_8.io.in_uop.bits.pimm, issue_slots[8].in_uop.bits.pimm connect slots_8.io.in_uop.bits.imm_sel, issue_slots[8].in_uop.bits.imm_sel connect slots_8.io.in_uop.bits.imm_rename, issue_slots[8].in_uop.bits.imm_rename connect slots_8.io.in_uop.bits.taken, issue_slots[8].in_uop.bits.taken connect slots_8.io.in_uop.bits.pc_lob, issue_slots[8].in_uop.bits.pc_lob connect slots_8.io.in_uop.bits.edge_inst, issue_slots[8].in_uop.bits.edge_inst connect slots_8.io.in_uop.bits.ftq_idx, issue_slots[8].in_uop.bits.ftq_idx connect slots_8.io.in_uop.bits.is_mov, issue_slots[8].in_uop.bits.is_mov connect slots_8.io.in_uop.bits.is_rocc, issue_slots[8].in_uop.bits.is_rocc connect slots_8.io.in_uop.bits.is_sys_pc2epc, issue_slots[8].in_uop.bits.is_sys_pc2epc connect slots_8.io.in_uop.bits.is_eret, issue_slots[8].in_uop.bits.is_eret connect slots_8.io.in_uop.bits.is_amo, issue_slots[8].in_uop.bits.is_amo connect slots_8.io.in_uop.bits.is_sfence, issue_slots[8].in_uop.bits.is_sfence connect slots_8.io.in_uop.bits.is_fencei, issue_slots[8].in_uop.bits.is_fencei connect slots_8.io.in_uop.bits.is_fence, issue_slots[8].in_uop.bits.is_fence connect slots_8.io.in_uop.bits.is_sfb, issue_slots[8].in_uop.bits.is_sfb connect slots_8.io.in_uop.bits.br_type, issue_slots[8].in_uop.bits.br_type connect slots_8.io.in_uop.bits.br_tag, issue_slots[8].in_uop.bits.br_tag connect slots_8.io.in_uop.bits.br_mask, issue_slots[8].in_uop.bits.br_mask connect slots_8.io.in_uop.bits.dis_col_sel, issue_slots[8].in_uop.bits.dis_col_sel connect slots_8.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[8].in_uop.bits.iw_p3_bypass_hint connect slots_8.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[8].in_uop.bits.iw_p2_bypass_hint connect slots_8.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[8].in_uop.bits.iw_p1_bypass_hint connect slots_8.io.in_uop.bits.iw_p2_speculative_child, issue_slots[8].in_uop.bits.iw_p2_speculative_child connect slots_8.io.in_uop.bits.iw_p1_speculative_child, issue_slots[8].in_uop.bits.iw_p1_speculative_child connect slots_8.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[8].in_uop.bits.iw_issued_partial_dgen connect slots_8.io.in_uop.bits.iw_issued_partial_agen, issue_slots[8].in_uop.bits.iw_issued_partial_agen connect slots_8.io.in_uop.bits.iw_issued, issue_slots[8].in_uop.bits.iw_issued connect slots_8.io.in_uop.bits.fu_code[0], issue_slots[8].in_uop.bits.fu_code[0] connect slots_8.io.in_uop.bits.fu_code[1], issue_slots[8].in_uop.bits.fu_code[1] connect slots_8.io.in_uop.bits.fu_code[2], issue_slots[8].in_uop.bits.fu_code[2] connect slots_8.io.in_uop.bits.fu_code[3], issue_slots[8].in_uop.bits.fu_code[3] connect slots_8.io.in_uop.bits.fu_code[4], issue_slots[8].in_uop.bits.fu_code[4] connect slots_8.io.in_uop.bits.fu_code[5], issue_slots[8].in_uop.bits.fu_code[5] connect slots_8.io.in_uop.bits.fu_code[6], issue_slots[8].in_uop.bits.fu_code[6] connect slots_8.io.in_uop.bits.fu_code[7], issue_slots[8].in_uop.bits.fu_code[7] connect slots_8.io.in_uop.bits.fu_code[8], issue_slots[8].in_uop.bits.fu_code[8] connect slots_8.io.in_uop.bits.fu_code[9], issue_slots[8].in_uop.bits.fu_code[9] connect slots_8.io.in_uop.bits.iq_type[0], issue_slots[8].in_uop.bits.iq_type[0] connect slots_8.io.in_uop.bits.iq_type[1], issue_slots[8].in_uop.bits.iq_type[1] connect slots_8.io.in_uop.bits.iq_type[2], issue_slots[8].in_uop.bits.iq_type[2] connect slots_8.io.in_uop.bits.iq_type[3], issue_slots[8].in_uop.bits.iq_type[3] connect slots_8.io.in_uop.bits.debug_pc, issue_slots[8].in_uop.bits.debug_pc connect slots_8.io.in_uop.bits.is_rvc, issue_slots[8].in_uop.bits.is_rvc connect slots_8.io.in_uop.bits.debug_inst, issue_slots[8].in_uop.bits.debug_inst connect slots_8.io.in_uop.bits.inst, issue_slots[8].in_uop.bits.inst connect slots_8.io.in_uop.valid, issue_slots[8].in_uop.valid connect issue_slots[8].iss_uop.debug_tsrc, slots_8.io.iss_uop.debug_tsrc connect issue_slots[8].iss_uop.debug_fsrc, slots_8.io.iss_uop.debug_fsrc connect issue_slots[8].iss_uop.bp_xcpt_if, slots_8.io.iss_uop.bp_xcpt_if connect issue_slots[8].iss_uop.bp_debug_if, slots_8.io.iss_uop.bp_debug_if connect issue_slots[8].iss_uop.xcpt_ma_if, slots_8.io.iss_uop.xcpt_ma_if connect issue_slots[8].iss_uop.xcpt_ae_if, slots_8.io.iss_uop.xcpt_ae_if connect issue_slots[8].iss_uop.xcpt_pf_if, slots_8.io.iss_uop.xcpt_pf_if connect issue_slots[8].iss_uop.fp_typ, slots_8.io.iss_uop.fp_typ connect issue_slots[8].iss_uop.fp_rm, slots_8.io.iss_uop.fp_rm connect issue_slots[8].iss_uop.fp_val, slots_8.io.iss_uop.fp_val connect issue_slots[8].iss_uop.fcn_op, slots_8.io.iss_uop.fcn_op connect issue_slots[8].iss_uop.fcn_dw, slots_8.io.iss_uop.fcn_dw connect issue_slots[8].iss_uop.frs3_en, slots_8.io.iss_uop.frs3_en connect issue_slots[8].iss_uop.lrs2_rtype, slots_8.io.iss_uop.lrs2_rtype connect issue_slots[8].iss_uop.lrs1_rtype, slots_8.io.iss_uop.lrs1_rtype connect issue_slots[8].iss_uop.dst_rtype, slots_8.io.iss_uop.dst_rtype connect issue_slots[8].iss_uop.lrs3, slots_8.io.iss_uop.lrs3 connect issue_slots[8].iss_uop.lrs2, slots_8.io.iss_uop.lrs2 connect issue_slots[8].iss_uop.lrs1, slots_8.io.iss_uop.lrs1 connect issue_slots[8].iss_uop.ldst, slots_8.io.iss_uop.ldst connect issue_slots[8].iss_uop.ldst_is_rs1, slots_8.io.iss_uop.ldst_is_rs1 connect issue_slots[8].iss_uop.csr_cmd, slots_8.io.iss_uop.csr_cmd connect issue_slots[8].iss_uop.flush_on_commit, slots_8.io.iss_uop.flush_on_commit connect issue_slots[8].iss_uop.is_unique, slots_8.io.iss_uop.is_unique connect issue_slots[8].iss_uop.uses_stq, slots_8.io.iss_uop.uses_stq connect issue_slots[8].iss_uop.uses_ldq, slots_8.io.iss_uop.uses_ldq connect issue_slots[8].iss_uop.mem_signed, slots_8.io.iss_uop.mem_signed connect issue_slots[8].iss_uop.mem_size, slots_8.io.iss_uop.mem_size connect issue_slots[8].iss_uop.mem_cmd, slots_8.io.iss_uop.mem_cmd connect issue_slots[8].iss_uop.exc_cause, slots_8.io.iss_uop.exc_cause connect issue_slots[8].iss_uop.exception, slots_8.io.iss_uop.exception connect issue_slots[8].iss_uop.stale_pdst, slots_8.io.iss_uop.stale_pdst connect issue_slots[8].iss_uop.ppred_busy, slots_8.io.iss_uop.ppred_busy connect issue_slots[8].iss_uop.prs3_busy, slots_8.io.iss_uop.prs3_busy connect issue_slots[8].iss_uop.prs2_busy, slots_8.io.iss_uop.prs2_busy connect issue_slots[8].iss_uop.prs1_busy, slots_8.io.iss_uop.prs1_busy connect issue_slots[8].iss_uop.ppred, slots_8.io.iss_uop.ppred connect issue_slots[8].iss_uop.prs3, slots_8.io.iss_uop.prs3 connect issue_slots[8].iss_uop.prs2, slots_8.io.iss_uop.prs2 connect issue_slots[8].iss_uop.prs1, slots_8.io.iss_uop.prs1 connect issue_slots[8].iss_uop.pdst, slots_8.io.iss_uop.pdst connect issue_slots[8].iss_uop.rxq_idx, slots_8.io.iss_uop.rxq_idx connect issue_slots[8].iss_uop.stq_idx, slots_8.io.iss_uop.stq_idx connect issue_slots[8].iss_uop.ldq_idx, slots_8.io.iss_uop.ldq_idx connect issue_slots[8].iss_uop.rob_idx, slots_8.io.iss_uop.rob_idx connect issue_slots[8].iss_uop.fp_ctrl.vec, slots_8.io.iss_uop.fp_ctrl.vec connect issue_slots[8].iss_uop.fp_ctrl.wflags, slots_8.io.iss_uop.fp_ctrl.wflags connect issue_slots[8].iss_uop.fp_ctrl.sqrt, slots_8.io.iss_uop.fp_ctrl.sqrt connect issue_slots[8].iss_uop.fp_ctrl.div, slots_8.io.iss_uop.fp_ctrl.div connect issue_slots[8].iss_uop.fp_ctrl.fma, slots_8.io.iss_uop.fp_ctrl.fma connect issue_slots[8].iss_uop.fp_ctrl.fastpipe, slots_8.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[8].iss_uop.fp_ctrl.toint, slots_8.io.iss_uop.fp_ctrl.toint connect issue_slots[8].iss_uop.fp_ctrl.fromint, slots_8.io.iss_uop.fp_ctrl.fromint connect issue_slots[8].iss_uop.fp_ctrl.typeTagOut, slots_8.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[8].iss_uop.fp_ctrl.typeTagIn, slots_8.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[8].iss_uop.fp_ctrl.swap23, slots_8.io.iss_uop.fp_ctrl.swap23 connect issue_slots[8].iss_uop.fp_ctrl.swap12, slots_8.io.iss_uop.fp_ctrl.swap12 connect issue_slots[8].iss_uop.fp_ctrl.ren3, slots_8.io.iss_uop.fp_ctrl.ren3 connect issue_slots[8].iss_uop.fp_ctrl.ren2, slots_8.io.iss_uop.fp_ctrl.ren2 connect issue_slots[8].iss_uop.fp_ctrl.ren1, slots_8.io.iss_uop.fp_ctrl.ren1 connect issue_slots[8].iss_uop.fp_ctrl.wen, slots_8.io.iss_uop.fp_ctrl.wen connect issue_slots[8].iss_uop.fp_ctrl.ldst, slots_8.io.iss_uop.fp_ctrl.ldst connect issue_slots[8].iss_uop.op2_sel, slots_8.io.iss_uop.op2_sel connect issue_slots[8].iss_uop.op1_sel, slots_8.io.iss_uop.op1_sel connect issue_slots[8].iss_uop.imm_packed, slots_8.io.iss_uop.imm_packed connect issue_slots[8].iss_uop.pimm, slots_8.io.iss_uop.pimm connect issue_slots[8].iss_uop.imm_sel, slots_8.io.iss_uop.imm_sel connect issue_slots[8].iss_uop.imm_rename, slots_8.io.iss_uop.imm_rename connect issue_slots[8].iss_uop.taken, slots_8.io.iss_uop.taken connect issue_slots[8].iss_uop.pc_lob, slots_8.io.iss_uop.pc_lob connect issue_slots[8].iss_uop.edge_inst, slots_8.io.iss_uop.edge_inst connect issue_slots[8].iss_uop.ftq_idx, slots_8.io.iss_uop.ftq_idx connect issue_slots[8].iss_uop.is_mov, slots_8.io.iss_uop.is_mov connect issue_slots[8].iss_uop.is_rocc, slots_8.io.iss_uop.is_rocc connect issue_slots[8].iss_uop.is_sys_pc2epc, slots_8.io.iss_uop.is_sys_pc2epc connect issue_slots[8].iss_uop.is_eret, slots_8.io.iss_uop.is_eret connect issue_slots[8].iss_uop.is_amo, slots_8.io.iss_uop.is_amo connect issue_slots[8].iss_uop.is_sfence, slots_8.io.iss_uop.is_sfence connect issue_slots[8].iss_uop.is_fencei, slots_8.io.iss_uop.is_fencei connect issue_slots[8].iss_uop.is_fence, slots_8.io.iss_uop.is_fence connect issue_slots[8].iss_uop.is_sfb, slots_8.io.iss_uop.is_sfb connect issue_slots[8].iss_uop.br_type, slots_8.io.iss_uop.br_type connect issue_slots[8].iss_uop.br_tag, slots_8.io.iss_uop.br_tag connect issue_slots[8].iss_uop.br_mask, slots_8.io.iss_uop.br_mask connect issue_slots[8].iss_uop.dis_col_sel, slots_8.io.iss_uop.dis_col_sel connect issue_slots[8].iss_uop.iw_p3_bypass_hint, slots_8.io.iss_uop.iw_p3_bypass_hint connect issue_slots[8].iss_uop.iw_p2_bypass_hint, slots_8.io.iss_uop.iw_p2_bypass_hint connect issue_slots[8].iss_uop.iw_p1_bypass_hint, slots_8.io.iss_uop.iw_p1_bypass_hint connect issue_slots[8].iss_uop.iw_p2_speculative_child, slots_8.io.iss_uop.iw_p2_speculative_child connect issue_slots[8].iss_uop.iw_p1_speculative_child, slots_8.io.iss_uop.iw_p1_speculative_child connect issue_slots[8].iss_uop.iw_issued_partial_dgen, slots_8.io.iss_uop.iw_issued_partial_dgen connect issue_slots[8].iss_uop.iw_issued_partial_agen, slots_8.io.iss_uop.iw_issued_partial_agen connect issue_slots[8].iss_uop.iw_issued, slots_8.io.iss_uop.iw_issued connect issue_slots[8].iss_uop.fu_code[0], slots_8.io.iss_uop.fu_code[0] connect issue_slots[8].iss_uop.fu_code[1], slots_8.io.iss_uop.fu_code[1] connect issue_slots[8].iss_uop.fu_code[2], slots_8.io.iss_uop.fu_code[2] connect issue_slots[8].iss_uop.fu_code[3], slots_8.io.iss_uop.fu_code[3] connect issue_slots[8].iss_uop.fu_code[4], slots_8.io.iss_uop.fu_code[4] connect issue_slots[8].iss_uop.fu_code[5], slots_8.io.iss_uop.fu_code[5] connect issue_slots[8].iss_uop.fu_code[6], slots_8.io.iss_uop.fu_code[6] connect issue_slots[8].iss_uop.fu_code[7], slots_8.io.iss_uop.fu_code[7] connect issue_slots[8].iss_uop.fu_code[8], slots_8.io.iss_uop.fu_code[8] connect issue_slots[8].iss_uop.fu_code[9], slots_8.io.iss_uop.fu_code[9] connect issue_slots[8].iss_uop.iq_type[0], slots_8.io.iss_uop.iq_type[0] connect issue_slots[8].iss_uop.iq_type[1], slots_8.io.iss_uop.iq_type[1] connect issue_slots[8].iss_uop.iq_type[2], slots_8.io.iss_uop.iq_type[2] connect issue_slots[8].iss_uop.iq_type[3], slots_8.io.iss_uop.iq_type[3] connect issue_slots[8].iss_uop.debug_pc, slots_8.io.iss_uop.debug_pc connect issue_slots[8].iss_uop.is_rvc, slots_8.io.iss_uop.is_rvc connect issue_slots[8].iss_uop.debug_inst, slots_8.io.iss_uop.debug_inst connect issue_slots[8].iss_uop.inst, slots_8.io.iss_uop.inst connect slots_8.io.grant, issue_slots[8].grant connect issue_slots[8].request, slots_8.io.request connect issue_slots[8].will_be_valid, slots_8.io.will_be_valid connect issue_slots[8].valid, slots_8.io.valid connect slots_9.io.child_rebusys, issue_slots[9].child_rebusys connect slots_9.io.pred_wakeup_port.bits, issue_slots[9].pred_wakeup_port.bits connect slots_9.io.pred_wakeup_port.valid, issue_slots[9].pred_wakeup_port.valid connect slots_9.io.wakeup_ports[0].bits.rebusy, issue_slots[9].wakeup_ports[0].bits.rebusy connect slots_9.io.wakeup_ports[0].bits.speculative_mask, issue_slots[9].wakeup_ports[0].bits.speculative_mask connect slots_9.io.wakeup_ports[0].bits.bypassable, issue_slots[9].wakeup_ports[0].bits.bypassable connect slots_9.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[0].bits.uop.debug_tsrc connect slots_9.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[0].bits.uop.debug_fsrc connect slots_9.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_9.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[0].bits.uop.bp_debug_if connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_9.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_9.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[9].wakeup_ports[0].bits.uop.fp_typ connect slots_9.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[9].wakeup_ports[0].bits.uop.fp_rm connect slots_9.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[9].wakeup_ports[0].bits.uop.fp_val connect slots_9.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[9].wakeup_ports[0].bits.uop.fcn_op connect slots_9.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[0].bits.uop.fcn_dw connect slots_9.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[9].wakeup_ports[0].bits.uop.frs3_en connect slots_9.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_9.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_9.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[0].bits.uop.dst_rtype connect slots_9.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[9].wakeup_ports[0].bits.uop.lrs3 connect slots_9.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[9].wakeup_ports[0].bits.uop.lrs2 connect slots_9.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[9].wakeup_ports[0].bits.uop.lrs1 connect slots_9.io.wakeup_ports[0].bits.uop.ldst, issue_slots[9].wakeup_ports[0].bits.uop.ldst connect slots_9.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_9.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[0].bits.uop.csr_cmd connect slots_9.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[0].bits.uop.flush_on_commit connect slots_9.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[9].wakeup_ports[0].bits.uop.is_unique connect slots_9.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[9].wakeup_ports[0].bits.uop.uses_stq connect slots_9.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[0].bits.uop.uses_ldq connect slots_9.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[9].wakeup_ports[0].bits.uop.mem_signed connect slots_9.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[9].wakeup_ports[0].bits.uop.mem_size connect slots_9.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[0].bits.uop.mem_cmd connect slots_9.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[9].wakeup_ports[0].bits.uop.exc_cause connect slots_9.io.wakeup_ports[0].bits.uop.exception, issue_slots[9].wakeup_ports[0].bits.uop.exception connect slots_9.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[0].bits.uop.stale_pdst connect slots_9.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[0].bits.uop.ppred_busy connect slots_9.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs3_busy connect slots_9.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs2_busy connect slots_9.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[0].bits.uop.prs1_busy connect slots_9.io.wakeup_ports[0].bits.uop.ppred, issue_slots[9].wakeup_ports[0].bits.uop.ppred connect slots_9.io.wakeup_ports[0].bits.uop.prs3, issue_slots[9].wakeup_ports[0].bits.uop.prs3 connect slots_9.io.wakeup_ports[0].bits.uop.prs2, issue_slots[9].wakeup_ports[0].bits.uop.prs2 connect slots_9.io.wakeup_ports[0].bits.uop.prs1, issue_slots[9].wakeup_ports[0].bits.uop.prs1 connect slots_9.io.wakeup_ports[0].bits.uop.pdst, issue_slots[9].wakeup_ports[0].bits.uop.pdst connect slots_9.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[0].bits.uop.rxq_idx connect slots_9.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[9].wakeup_ports[0].bits.uop.stq_idx connect slots_9.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[0].bits.uop.ldq_idx connect slots_9.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[9].wakeup_ports[0].bits.uop.rob_idx connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_9.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_9.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[9].wakeup_ports[0].bits.uop.op2_sel connect slots_9.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[9].wakeup_ports[0].bits.uop.op1_sel connect slots_9.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[9].wakeup_ports[0].bits.uop.imm_packed connect slots_9.io.wakeup_ports[0].bits.uop.pimm, issue_slots[9].wakeup_ports[0].bits.uop.pimm connect slots_9.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[9].wakeup_ports[0].bits.uop.imm_sel connect slots_9.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[9].wakeup_ports[0].bits.uop.imm_rename connect slots_9.io.wakeup_ports[0].bits.uop.taken, issue_slots[9].wakeup_ports[0].bits.uop.taken connect slots_9.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[9].wakeup_ports[0].bits.uop.pc_lob connect slots_9.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[9].wakeup_ports[0].bits.uop.edge_inst connect slots_9.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[0].bits.uop.ftq_idx connect slots_9.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[9].wakeup_ports[0].bits.uop.is_mov connect slots_9.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[9].wakeup_ports[0].bits.uop.is_rocc connect slots_9.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_9.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[9].wakeup_ports[0].bits.uop.is_eret connect slots_9.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[9].wakeup_ports[0].bits.uop.is_amo connect slots_9.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[9].wakeup_ports[0].bits.uop.is_sfence connect slots_9.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[9].wakeup_ports[0].bits.uop.is_fencei connect slots_9.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[9].wakeup_ports[0].bits.uop.is_fence connect slots_9.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[9].wakeup_ports[0].bits.uop.is_sfb connect slots_9.io.wakeup_ports[0].bits.uop.br_type, issue_slots[9].wakeup_ports[0].bits.uop.br_type connect slots_9.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[9].wakeup_ports[0].bits.uop.br_tag connect slots_9.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[9].wakeup_ports[0].bits.uop.br_mask connect slots_9.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[0].bits.uop.dis_col_sel connect slots_9.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_9.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_9.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_9.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_9.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_9.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[9].wakeup_ports[0].bits.uop.iw_issued connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[0] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[1] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[2] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[3] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[4] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[5] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[6] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[7] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[8] connect slots_9.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[0].bits.uop.fu_code[9] connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[0] connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[1] connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[2] connect slots_9.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[0].bits.uop.iq_type[3] connect slots_9.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[9].wakeup_ports[0].bits.uop.debug_pc connect slots_9.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[9].wakeup_ports[0].bits.uop.is_rvc connect slots_9.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[9].wakeup_ports[0].bits.uop.debug_inst connect slots_9.io.wakeup_ports[0].bits.uop.inst, issue_slots[9].wakeup_ports[0].bits.uop.inst connect slots_9.io.wakeup_ports[0].valid, issue_slots[9].wakeup_ports[0].valid connect slots_9.io.wakeup_ports[1].bits.rebusy, issue_slots[9].wakeup_ports[1].bits.rebusy connect slots_9.io.wakeup_ports[1].bits.speculative_mask, issue_slots[9].wakeup_ports[1].bits.speculative_mask connect slots_9.io.wakeup_ports[1].bits.bypassable, issue_slots[9].wakeup_ports[1].bits.bypassable connect slots_9.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[9].wakeup_ports[1].bits.uop.debug_tsrc connect slots_9.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[9].wakeup_ports[1].bits.uop.debug_fsrc connect slots_9.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[9].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_9.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[9].wakeup_ports[1].bits.uop.bp_debug_if connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_9.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[9].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_9.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[9].wakeup_ports[1].bits.uop.fp_typ connect slots_9.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[9].wakeup_ports[1].bits.uop.fp_rm connect slots_9.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[9].wakeup_ports[1].bits.uop.fp_val connect slots_9.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[9].wakeup_ports[1].bits.uop.fcn_op connect slots_9.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[9].wakeup_ports[1].bits.uop.fcn_dw connect slots_9.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[9].wakeup_ports[1].bits.uop.frs3_en connect slots_9.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[9].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_9.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[9].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_9.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[9].wakeup_ports[1].bits.uop.dst_rtype connect slots_9.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[9].wakeup_ports[1].bits.uop.lrs3 connect slots_9.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[9].wakeup_ports[1].bits.uop.lrs2 connect slots_9.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[9].wakeup_ports[1].bits.uop.lrs1 connect slots_9.io.wakeup_ports[1].bits.uop.ldst, issue_slots[9].wakeup_ports[1].bits.uop.ldst connect slots_9.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[9].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_9.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[9].wakeup_ports[1].bits.uop.csr_cmd connect slots_9.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[9].wakeup_ports[1].bits.uop.flush_on_commit connect slots_9.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[9].wakeup_ports[1].bits.uop.is_unique connect slots_9.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[9].wakeup_ports[1].bits.uop.uses_stq connect slots_9.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[9].wakeup_ports[1].bits.uop.uses_ldq connect slots_9.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[9].wakeup_ports[1].bits.uop.mem_signed connect slots_9.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[9].wakeup_ports[1].bits.uop.mem_size connect slots_9.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[9].wakeup_ports[1].bits.uop.mem_cmd connect slots_9.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[9].wakeup_ports[1].bits.uop.exc_cause connect slots_9.io.wakeup_ports[1].bits.uop.exception, issue_slots[9].wakeup_ports[1].bits.uop.exception connect slots_9.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[9].wakeup_ports[1].bits.uop.stale_pdst connect slots_9.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[9].wakeup_ports[1].bits.uop.ppred_busy connect slots_9.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs3_busy connect slots_9.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs2_busy connect slots_9.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[9].wakeup_ports[1].bits.uop.prs1_busy connect slots_9.io.wakeup_ports[1].bits.uop.ppred, issue_slots[9].wakeup_ports[1].bits.uop.ppred connect slots_9.io.wakeup_ports[1].bits.uop.prs3, issue_slots[9].wakeup_ports[1].bits.uop.prs3 connect slots_9.io.wakeup_ports[1].bits.uop.prs2, issue_slots[9].wakeup_ports[1].bits.uop.prs2 connect slots_9.io.wakeup_ports[1].bits.uop.prs1, issue_slots[9].wakeup_ports[1].bits.uop.prs1 connect slots_9.io.wakeup_ports[1].bits.uop.pdst, issue_slots[9].wakeup_ports[1].bits.uop.pdst connect slots_9.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[9].wakeup_ports[1].bits.uop.rxq_idx connect slots_9.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[9].wakeup_ports[1].bits.uop.stq_idx connect slots_9.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[9].wakeup_ports[1].bits.uop.ldq_idx connect slots_9.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[9].wakeup_ports[1].bits.uop.rob_idx connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_9.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_9.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[9].wakeup_ports[1].bits.uop.op2_sel connect slots_9.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[9].wakeup_ports[1].bits.uop.op1_sel connect slots_9.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[9].wakeup_ports[1].bits.uop.imm_packed connect slots_9.io.wakeup_ports[1].bits.uop.pimm, issue_slots[9].wakeup_ports[1].bits.uop.pimm connect slots_9.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[9].wakeup_ports[1].bits.uop.imm_sel connect slots_9.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[9].wakeup_ports[1].bits.uop.imm_rename connect slots_9.io.wakeup_ports[1].bits.uop.taken, issue_slots[9].wakeup_ports[1].bits.uop.taken connect slots_9.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[9].wakeup_ports[1].bits.uop.pc_lob connect slots_9.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[9].wakeup_ports[1].bits.uop.edge_inst connect slots_9.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[9].wakeup_ports[1].bits.uop.ftq_idx connect slots_9.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[9].wakeup_ports[1].bits.uop.is_mov connect slots_9.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[9].wakeup_ports[1].bits.uop.is_rocc connect slots_9.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[9].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_9.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[9].wakeup_ports[1].bits.uop.is_eret connect slots_9.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[9].wakeup_ports[1].bits.uop.is_amo connect slots_9.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[9].wakeup_ports[1].bits.uop.is_sfence connect slots_9.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[9].wakeup_ports[1].bits.uop.is_fencei connect slots_9.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[9].wakeup_ports[1].bits.uop.is_fence connect slots_9.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[9].wakeup_ports[1].bits.uop.is_sfb connect slots_9.io.wakeup_ports[1].bits.uop.br_type, issue_slots[9].wakeup_ports[1].bits.uop.br_type connect slots_9.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[9].wakeup_ports[1].bits.uop.br_tag connect slots_9.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[9].wakeup_ports[1].bits.uop.br_mask connect slots_9.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[9].wakeup_ports[1].bits.uop.dis_col_sel connect slots_9.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_9.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_9.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_9.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_9.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_9.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[9].wakeup_ports[1].bits.uop.iw_issued connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[0] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[1] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[2] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[3] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[4] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[5] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[6] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[7] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[8] connect slots_9.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[9].wakeup_ports[1].bits.uop.fu_code[9] connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[0] connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[1] connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[2] connect slots_9.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[9].wakeup_ports[1].bits.uop.iq_type[3] connect slots_9.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[9].wakeup_ports[1].bits.uop.debug_pc connect slots_9.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[9].wakeup_ports[1].bits.uop.is_rvc connect slots_9.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[9].wakeup_ports[1].bits.uop.debug_inst connect slots_9.io.wakeup_ports[1].bits.uop.inst, issue_slots[9].wakeup_ports[1].bits.uop.inst connect slots_9.io.wakeup_ports[1].valid, issue_slots[9].wakeup_ports[1].valid connect slots_9.io.squash_grant, issue_slots[9].squash_grant connect slots_9.io.clear, issue_slots[9].clear connect slots_9.io.kill, issue_slots[9].kill connect slots_9.io.brupdate.b2.target_offset, issue_slots[9].brupdate.b2.target_offset connect slots_9.io.brupdate.b2.jalr_target, issue_slots[9].brupdate.b2.jalr_target connect slots_9.io.brupdate.b2.pc_sel, issue_slots[9].brupdate.b2.pc_sel connect slots_9.io.brupdate.b2.cfi_type, issue_slots[9].brupdate.b2.cfi_type connect slots_9.io.brupdate.b2.taken, issue_slots[9].brupdate.b2.taken connect slots_9.io.brupdate.b2.mispredict, issue_slots[9].brupdate.b2.mispredict connect slots_9.io.brupdate.b2.uop.debug_tsrc, issue_slots[9].brupdate.b2.uop.debug_tsrc connect slots_9.io.brupdate.b2.uop.debug_fsrc, issue_slots[9].brupdate.b2.uop.debug_fsrc connect slots_9.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[9].brupdate.b2.uop.bp_xcpt_if connect slots_9.io.brupdate.b2.uop.bp_debug_if, issue_slots[9].brupdate.b2.uop.bp_debug_if connect slots_9.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[9].brupdate.b2.uop.xcpt_ma_if connect slots_9.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[9].brupdate.b2.uop.xcpt_ae_if connect slots_9.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[9].brupdate.b2.uop.xcpt_pf_if connect slots_9.io.brupdate.b2.uop.fp_typ, issue_slots[9].brupdate.b2.uop.fp_typ connect slots_9.io.brupdate.b2.uop.fp_rm, issue_slots[9].brupdate.b2.uop.fp_rm connect slots_9.io.brupdate.b2.uop.fp_val, issue_slots[9].brupdate.b2.uop.fp_val connect slots_9.io.brupdate.b2.uop.fcn_op, issue_slots[9].brupdate.b2.uop.fcn_op connect slots_9.io.brupdate.b2.uop.fcn_dw, issue_slots[9].brupdate.b2.uop.fcn_dw connect slots_9.io.brupdate.b2.uop.frs3_en, issue_slots[9].brupdate.b2.uop.frs3_en connect slots_9.io.brupdate.b2.uop.lrs2_rtype, issue_slots[9].brupdate.b2.uop.lrs2_rtype connect slots_9.io.brupdate.b2.uop.lrs1_rtype, issue_slots[9].brupdate.b2.uop.lrs1_rtype connect slots_9.io.brupdate.b2.uop.dst_rtype, issue_slots[9].brupdate.b2.uop.dst_rtype connect slots_9.io.brupdate.b2.uop.lrs3, issue_slots[9].brupdate.b2.uop.lrs3 connect slots_9.io.brupdate.b2.uop.lrs2, issue_slots[9].brupdate.b2.uop.lrs2 connect slots_9.io.brupdate.b2.uop.lrs1, issue_slots[9].brupdate.b2.uop.lrs1 connect slots_9.io.brupdate.b2.uop.ldst, issue_slots[9].brupdate.b2.uop.ldst connect slots_9.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[9].brupdate.b2.uop.ldst_is_rs1 connect slots_9.io.brupdate.b2.uop.csr_cmd, issue_slots[9].brupdate.b2.uop.csr_cmd connect slots_9.io.brupdate.b2.uop.flush_on_commit, issue_slots[9].brupdate.b2.uop.flush_on_commit connect slots_9.io.brupdate.b2.uop.is_unique, issue_slots[9].brupdate.b2.uop.is_unique connect slots_9.io.brupdate.b2.uop.uses_stq, issue_slots[9].brupdate.b2.uop.uses_stq connect slots_9.io.brupdate.b2.uop.uses_ldq, issue_slots[9].brupdate.b2.uop.uses_ldq connect slots_9.io.brupdate.b2.uop.mem_signed, issue_slots[9].brupdate.b2.uop.mem_signed connect slots_9.io.brupdate.b2.uop.mem_size, issue_slots[9].brupdate.b2.uop.mem_size connect slots_9.io.brupdate.b2.uop.mem_cmd, issue_slots[9].brupdate.b2.uop.mem_cmd connect slots_9.io.brupdate.b2.uop.exc_cause, issue_slots[9].brupdate.b2.uop.exc_cause connect slots_9.io.brupdate.b2.uop.exception, issue_slots[9].brupdate.b2.uop.exception connect slots_9.io.brupdate.b2.uop.stale_pdst, issue_slots[9].brupdate.b2.uop.stale_pdst connect slots_9.io.brupdate.b2.uop.ppred_busy, issue_slots[9].brupdate.b2.uop.ppred_busy connect slots_9.io.brupdate.b2.uop.prs3_busy, issue_slots[9].brupdate.b2.uop.prs3_busy connect slots_9.io.brupdate.b2.uop.prs2_busy, issue_slots[9].brupdate.b2.uop.prs2_busy connect slots_9.io.brupdate.b2.uop.prs1_busy, issue_slots[9].brupdate.b2.uop.prs1_busy connect slots_9.io.brupdate.b2.uop.ppred, issue_slots[9].brupdate.b2.uop.ppred connect slots_9.io.brupdate.b2.uop.prs3, issue_slots[9].brupdate.b2.uop.prs3 connect slots_9.io.brupdate.b2.uop.prs2, issue_slots[9].brupdate.b2.uop.prs2 connect slots_9.io.brupdate.b2.uop.prs1, issue_slots[9].brupdate.b2.uop.prs1 connect slots_9.io.brupdate.b2.uop.pdst, issue_slots[9].brupdate.b2.uop.pdst connect slots_9.io.brupdate.b2.uop.rxq_idx, issue_slots[9].brupdate.b2.uop.rxq_idx connect slots_9.io.brupdate.b2.uop.stq_idx, issue_slots[9].brupdate.b2.uop.stq_idx connect slots_9.io.brupdate.b2.uop.ldq_idx, issue_slots[9].brupdate.b2.uop.ldq_idx connect slots_9.io.brupdate.b2.uop.rob_idx, issue_slots[9].brupdate.b2.uop.rob_idx connect slots_9.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[9].brupdate.b2.uop.fp_ctrl.vec connect slots_9.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[9].brupdate.b2.uop.fp_ctrl.wflags connect slots_9.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[9].brupdate.b2.uop.fp_ctrl.sqrt connect slots_9.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[9].brupdate.b2.uop.fp_ctrl.div connect slots_9.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[9].brupdate.b2.uop.fp_ctrl.fma connect slots_9.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[9].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_9.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[9].brupdate.b2.uop.fp_ctrl.toint connect slots_9.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[9].brupdate.b2.uop.fp_ctrl.fromint connect slots_9.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_9.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_9.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[9].brupdate.b2.uop.fp_ctrl.swap23 connect slots_9.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[9].brupdate.b2.uop.fp_ctrl.swap12 connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren3 connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren2 connect slots_9.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[9].brupdate.b2.uop.fp_ctrl.ren1 connect slots_9.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[9].brupdate.b2.uop.fp_ctrl.wen connect slots_9.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[9].brupdate.b2.uop.fp_ctrl.ldst connect slots_9.io.brupdate.b2.uop.op2_sel, issue_slots[9].brupdate.b2.uop.op2_sel connect slots_9.io.brupdate.b2.uop.op1_sel, issue_slots[9].brupdate.b2.uop.op1_sel connect slots_9.io.brupdate.b2.uop.imm_packed, issue_slots[9].brupdate.b2.uop.imm_packed connect slots_9.io.brupdate.b2.uop.pimm, issue_slots[9].brupdate.b2.uop.pimm connect slots_9.io.brupdate.b2.uop.imm_sel, issue_slots[9].brupdate.b2.uop.imm_sel connect slots_9.io.brupdate.b2.uop.imm_rename, issue_slots[9].brupdate.b2.uop.imm_rename connect slots_9.io.brupdate.b2.uop.taken, issue_slots[9].brupdate.b2.uop.taken connect slots_9.io.brupdate.b2.uop.pc_lob, issue_slots[9].brupdate.b2.uop.pc_lob connect slots_9.io.brupdate.b2.uop.edge_inst, issue_slots[9].brupdate.b2.uop.edge_inst connect slots_9.io.brupdate.b2.uop.ftq_idx, issue_slots[9].brupdate.b2.uop.ftq_idx connect slots_9.io.brupdate.b2.uop.is_mov, issue_slots[9].brupdate.b2.uop.is_mov connect slots_9.io.brupdate.b2.uop.is_rocc, issue_slots[9].brupdate.b2.uop.is_rocc connect slots_9.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[9].brupdate.b2.uop.is_sys_pc2epc connect slots_9.io.brupdate.b2.uop.is_eret, issue_slots[9].brupdate.b2.uop.is_eret connect slots_9.io.brupdate.b2.uop.is_amo, issue_slots[9].brupdate.b2.uop.is_amo connect slots_9.io.brupdate.b2.uop.is_sfence, issue_slots[9].brupdate.b2.uop.is_sfence connect slots_9.io.brupdate.b2.uop.is_fencei, issue_slots[9].brupdate.b2.uop.is_fencei connect slots_9.io.brupdate.b2.uop.is_fence, issue_slots[9].brupdate.b2.uop.is_fence connect slots_9.io.brupdate.b2.uop.is_sfb, issue_slots[9].brupdate.b2.uop.is_sfb connect slots_9.io.brupdate.b2.uop.br_type, issue_slots[9].brupdate.b2.uop.br_type connect slots_9.io.brupdate.b2.uop.br_tag, issue_slots[9].brupdate.b2.uop.br_tag connect slots_9.io.brupdate.b2.uop.br_mask, issue_slots[9].brupdate.b2.uop.br_mask connect slots_9.io.brupdate.b2.uop.dis_col_sel, issue_slots[9].brupdate.b2.uop.dis_col_sel connect slots_9.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p3_bypass_hint connect slots_9.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p2_bypass_hint connect slots_9.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[9].brupdate.b2.uop.iw_p1_bypass_hint connect slots_9.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[9].brupdate.b2.uop.iw_p2_speculative_child connect slots_9.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[9].brupdate.b2.uop.iw_p1_speculative_child connect slots_9.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[9].brupdate.b2.uop.iw_issued_partial_dgen connect slots_9.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[9].brupdate.b2.uop.iw_issued_partial_agen connect slots_9.io.brupdate.b2.uop.iw_issued, issue_slots[9].brupdate.b2.uop.iw_issued connect slots_9.io.brupdate.b2.uop.fu_code[0], issue_slots[9].brupdate.b2.uop.fu_code[0] connect slots_9.io.brupdate.b2.uop.fu_code[1], issue_slots[9].brupdate.b2.uop.fu_code[1] connect slots_9.io.brupdate.b2.uop.fu_code[2], issue_slots[9].brupdate.b2.uop.fu_code[2] connect slots_9.io.brupdate.b2.uop.fu_code[3], issue_slots[9].brupdate.b2.uop.fu_code[3] connect slots_9.io.brupdate.b2.uop.fu_code[4], issue_slots[9].brupdate.b2.uop.fu_code[4] connect slots_9.io.brupdate.b2.uop.fu_code[5], issue_slots[9].brupdate.b2.uop.fu_code[5] connect slots_9.io.brupdate.b2.uop.fu_code[6], issue_slots[9].brupdate.b2.uop.fu_code[6] connect slots_9.io.brupdate.b2.uop.fu_code[7], issue_slots[9].brupdate.b2.uop.fu_code[7] connect slots_9.io.brupdate.b2.uop.fu_code[8], issue_slots[9].brupdate.b2.uop.fu_code[8] connect slots_9.io.brupdate.b2.uop.fu_code[9], issue_slots[9].brupdate.b2.uop.fu_code[9] connect slots_9.io.brupdate.b2.uop.iq_type[0], issue_slots[9].brupdate.b2.uop.iq_type[0] connect slots_9.io.brupdate.b2.uop.iq_type[1], issue_slots[9].brupdate.b2.uop.iq_type[1] connect slots_9.io.brupdate.b2.uop.iq_type[2], issue_slots[9].brupdate.b2.uop.iq_type[2] connect slots_9.io.brupdate.b2.uop.iq_type[3], issue_slots[9].brupdate.b2.uop.iq_type[3] connect slots_9.io.brupdate.b2.uop.debug_pc, issue_slots[9].brupdate.b2.uop.debug_pc connect slots_9.io.brupdate.b2.uop.is_rvc, issue_slots[9].brupdate.b2.uop.is_rvc connect slots_9.io.brupdate.b2.uop.debug_inst, issue_slots[9].brupdate.b2.uop.debug_inst connect slots_9.io.brupdate.b2.uop.inst, issue_slots[9].brupdate.b2.uop.inst connect slots_9.io.brupdate.b1.mispredict_mask, issue_slots[9].brupdate.b1.mispredict_mask connect slots_9.io.brupdate.b1.resolve_mask, issue_slots[9].brupdate.b1.resolve_mask connect issue_slots[9].out_uop.debug_tsrc, slots_9.io.out_uop.debug_tsrc connect issue_slots[9].out_uop.debug_fsrc, slots_9.io.out_uop.debug_fsrc connect issue_slots[9].out_uop.bp_xcpt_if, slots_9.io.out_uop.bp_xcpt_if connect issue_slots[9].out_uop.bp_debug_if, slots_9.io.out_uop.bp_debug_if connect issue_slots[9].out_uop.xcpt_ma_if, slots_9.io.out_uop.xcpt_ma_if connect issue_slots[9].out_uop.xcpt_ae_if, slots_9.io.out_uop.xcpt_ae_if connect issue_slots[9].out_uop.xcpt_pf_if, slots_9.io.out_uop.xcpt_pf_if connect issue_slots[9].out_uop.fp_typ, slots_9.io.out_uop.fp_typ connect issue_slots[9].out_uop.fp_rm, slots_9.io.out_uop.fp_rm connect issue_slots[9].out_uop.fp_val, slots_9.io.out_uop.fp_val connect issue_slots[9].out_uop.fcn_op, slots_9.io.out_uop.fcn_op connect issue_slots[9].out_uop.fcn_dw, slots_9.io.out_uop.fcn_dw connect issue_slots[9].out_uop.frs3_en, slots_9.io.out_uop.frs3_en connect issue_slots[9].out_uop.lrs2_rtype, slots_9.io.out_uop.lrs2_rtype connect issue_slots[9].out_uop.lrs1_rtype, slots_9.io.out_uop.lrs1_rtype connect issue_slots[9].out_uop.dst_rtype, slots_9.io.out_uop.dst_rtype connect issue_slots[9].out_uop.lrs3, slots_9.io.out_uop.lrs3 connect issue_slots[9].out_uop.lrs2, slots_9.io.out_uop.lrs2 connect issue_slots[9].out_uop.lrs1, slots_9.io.out_uop.lrs1 connect issue_slots[9].out_uop.ldst, slots_9.io.out_uop.ldst connect issue_slots[9].out_uop.ldst_is_rs1, slots_9.io.out_uop.ldst_is_rs1 connect issue_slots[9].out_uop.csr_cmd, slots_9.io.out_uop.csr_cmd connect issue_slots[9].out_uop.flush_on_commit, slots_9.io.out_uop.flush_on_commit connect issue_slots[9].out_uop.is_unique, slots_9.io.out_uop.is_unique connect issue_slots[9].out_uop.uses_stq, slots_9.io.out_uop.uses_stq connect issue_slots[9].out_uop.uses_ldq, slots_9.io.out_uop.uses_ldq connect issue_slots[9].out_uop.mem_signed, slots_9.io.out_uop.mem_signed connect issue_slots[9].out_uop.mem_size, slots_9.io.out_uop.mem_size connect issue_slots[9].out_uop.mem_cmd, slots_9.io.out_uop.mem_cmd connect issue_slots[9].out_uop.exc_cause, slots_9.io.out_uop.exc_cause connect issue_slots[9].out_uop.exception, slots_9.io.out_uop.exception connect issue_slots[9].out_uop.stale_pdst, slots_9.io.out_uop.stale_pdst connect issue_slots[9].out_uop.ppred_busy, slots_9.io.out_uop.ppred_busy connect issue_slots[9].out_uop.prs3_busy, slots_9.io.out_uop.prs3_busy connect issue_slots[9].out_uop.prs2_busy, slots_9.io.out_uop.prs2_busy connect issue_slots[9].out_uop.prs1_busy, slots_9.io.out_uop.prs1_busy connect issue_slots[9].out_uop.ppred, slots_9.io.out_uop.ppred connect issue_slots[9].out_uop.prs3, slots_9.io.out_uop.prs3 connect issue_slots[9].out_uop.prs2, slots_9.io.out_uop.prs2 connect issue_slots[9].out_uop.prs1, slots_9.io.out_uop.prs1 connect issue_slots[9].out_uop.pdst, slots_9.io.out_uop.pdst connect issue_slots[9].out_uop.rxq_idx, slots_9.io.out_uop.rxq_idx connect issue_slots[9].out_uop.stq_idx, slots_9.io.out_uop.stq_idx connect issue_slots[9].out_uop.ldq_idx, slots_9.io.out_uop.ldq_idx connect issue_slots[9].out_uop.rob_idx, slots_9.io.out_uop.rob_idx connect issue_slots[9].out_uop.fp_ctrl.vec, slots_9.io.out_uop.fp_ctrl.vec connect issue_slots[9].out_uop.fp_ctrl.wflags, slots_9.io.out_uop.fp_ctrl.wflags connect issue_slots[9].out_uop.fp_ctrl.sqrt, slots_9.io.out_uop.fp_ctrl.sqrt connect issue_slots[9].out_uop.fp_ctrl.div, slots_9.io.out_uop.fp_ctrl.div connect issue_slots[9].out_uop.fp_ctrl.fma, slots_9.io.out_uop.fp_ctrl.fma connect issue_slots[9].out_uop.fp_ctrl.fastpipe, slots_9.io.out_uop.fp_ctrl.fastpipe connect issue_slots[9].out_uop.fp_ctrl.toint, slots_9.io.out_uop.fp_ctrl.toint connect issue_slots[9].out_uop.fp_ctrl.fromint, slots_9.io.out_uop.fp_ctrl.fromint connect issue_slots[9].out_uop.fp_ctrl.typeTagOut, slots_9.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[9].out_uop.fp_ctrl.typeTagIn, slots_9.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[9].out_uop.fp_ctrl.swap23, slots_9.io.out_uop.fp_ctrl.swap23 connect issue_slots[9].out_uop.fp_ctrl.swap12, slots_9.io.out_uop.fp_ctrl.swap12 connect issue_slots[9].out_uop.fp_ctrl.ren3, slots_9.io.out_uop.fp_ctrl.ren3 connect issue_slots[9].out_uop.fp_ctrl.ren2, slots_9.io.out_uop.fp_ctrl.ren2 connect issue_slots[9].out_uop.fp_ctrl.ren1, slots_9.io.out_uop.fp_ctrl.ren1 connect issue_slots[9].out_uop.fp_ctrl.wen, slots_9.io.out_uop.fp_ctrl.wen connect issue_slots[9].out_uop.fp_ctrl.ldst, slots_9.io.out_uop.fp_ctrl.ldst connect issue_slots[9].out_uop.op2_sel, slots_9.io.out_uop.op2_sel connect issue_slots[9].out_uop.op1_sel, slots_9.io.out_uop.op1_sel connect issue_slots[9].out_uop.imm_packed, slots_9.io.out_uop.imm_packed connect issue_slots[9].out_uop.pimm, slots_9.io.out_uop.pimm connect issue_slots[9].out_uop.imm_sel, slots_9.io.out_uop.imm_sel connect issue_slots[9].out_uop.imm_rename, slots_9.io.out_uop.imm_rename connect issue_slots[9].out_uop.taken, slots_9.io.out_uop.taken connect issue_slots[9].out_uop.pc_lob, slots_9.io.out_uop.pc_lob connect issue_slots[9].out_uop.edge_inst, slots_9.io.out_uop.edge_inst connect issue_slots[9].out_uop.ftq_idx, slots_9.io.out_uop.ftq_idx connect issue_slots[9].out_uop.is_mov, slots_9.io.out_uop.is_mov connect issue_slots[9].out_uop.is_rocc, slots_9.io.out_uop.is_rocc connect issue_slots[9].out_uop.is_sys_pc2epc, slots_9.io.out_uop.is_sys_pc2epc connect issue_slots[9].out_uop.is_eret, slots_9.io.out_uop.is_eret connect issue_slots[9].out_uop.is_amo, slots_9.io.out_uop.is_amo connect issue_slots[9].out_uop.is_sfence, slots_9.io.out_uop.is_sfence connect issue_slots[9].out_uop.is_fencei, slots_9.io.out_uop.is_fencei connect issue_slots[9].out_uop.is_fence, slots_9.io.out_uop.is_fence connect issue_slots[9].out_uop.is_sfb, slots_9.io.out_uop.is_sfb connect issue_slots[9].out_uop.br_type, slots_9.io.out_uop.br_type connect issue_slots[9].out_uop.br_tag, slots_9.io.out_uop.br_tag connect issue_slots[9].out_uop.br_mask, slots_9.io.out_uop.br_mask connect issue_slots[9].out_uop.dis_col_sel, slots_9.io.out_uop.dis_col_sel connect issue_slots[9].out_uop.iw_p3_bypass_hint, slots_9.io.out_uop.iw_p3_bypass_hint connect issue_slots[9].out_uop.iw_p2_bypass_hint, slots_9.io.out_uop.iw_p2_bypass_hint connect issue_slots[9].out_uop.iw_p1_bypass_hint, slots_9.io.out_uop.iw_p1_bypass_hint connect issue_slots[9].out_uop.iw_p2_speculative_child, slots_9.io.out_uop.iw_p2_speculative_child connect issue_slots[9].out_uop.iw_p1_speculative_child, slots_9.io.out_uop.iw_p1_speculative_child connect issue_slots[9].out_uop.iw_issued_partial_dgen, slots_9.io.out_uop.iw_issued_partial_dgen connect issue_slots[9].out_uop.iw_issued_partial_agen, slots_9.io.out_uop.iw_issued_partial_agen connect issue_slots[9].out_uop.iw_issued, slots_9.io.out_uop.iw_issued connect issue_slots[9].out_uop.fu_code[0], slots_9.io.out_uop.fu_code[0] connect issue_slots[9].out_uop.fu_code[1], slots_9.io.out_uop.fu_code[1] connect issue_slots[9].out_uop.fu_code[2], slots_9.io.out_uop.fu_code[2] connect issue_slots[9].out_uop.fu_code[3], slots_9.io.out_uop.fu_code[3] connect issue_slots[9].out_uop.fu_code[4], slots_9.io.out_uop.fu_code[4] connect issue_slots[9].out_uop.fu_code[5], slots_9.io.out_uop.fu_code[5] connect issue_slots[9].out_uop.fu_code[6], slots_9.io.out_uop.fu_code[6] connect issue_slots[9].out_uop.fu_code[7], slots_9.io.out_uop.fu_code[7] connect issue_slots[9].out_uop.fu_code[8], slots_9.io.out_uop.fu_code[8] connect issue_slots[9].out_uop.fu_code[9], slots_9.io.out_uop.fu_code[9] connect issue_slots[9].out_uop.iq_type[0], slots_9.io.out_uop.iq_type[0] connect issue_slots[9].out_uop.iq_type[1], slots_9.io.out_uop.iq_type[1] connect issue_slots[9].out_uop.iq_type[2], slots_9.io.out_uop.iq_type[2] connect issue_slots[9].out_uop.iq_type[3], slots_9.io.out_uop.iq_type[3] connect issue_slots[9].out_uop.debug_pc, slots_9.io.out_uop.debug_pc connect issue_slots[9].out_uop.is_rvc, slots_9.io.out_uop.is_rvc connect issue_slots[9].out_uop.debug_inst, slots_9.io.out_uop.debug_inst connect issue_slots[9].out_uop.inst, slots_9.io.out_uop.inst connect slots_9.io.in_uop.bits.debug_tsrc, issue_slots[9].in_uop.bits.debug_tsrc connect slots_9.io.in_uop.bits.debug_fsrc, issue_slots[9].in_uop.bits.debug_fsrc connect slots_9.io.in_uop.bits.bp_xcpt_if, issue_slots[9].in_uop.bits.bp_xcpt_if connect slots_9.io.in_uop.bits.bp_debug_if, issue_slots[9].in_uop.bits.bp_debug_if connect slots_9.io.in_uop.bits.xcpt_ma_if, issue_slots[9].in_uop.bits.xcpt_ma_if connect slots_9.io.in_uop.bits.xcpt_ae_if, issue_slots[9].in_uop.bits.xcpt_ae_if connect slots_9.io.in_uop.bits.xcpt_pf_if, issue_slots[9].in_uop.bits.xcpt_pf_if connect slots_9.io.in_uop.bits.fp_typ, issue_slots[9].in_uop.bits.fp_typ connect slots_9.io.in_uop.bits.fp_rm, issue_slots[9].in_uop.bits.fp_rm connect slots_9.io.in_uop.bits.fp_val, issue_slots[9].in_uop.bits.fp_val connect slots_9.io.in_uop.bits.fcn_op, issue_slots[9].in_uop.bits.fcn_op connect slots_9.io.in_uop.bits.fcn_dw, issue_slots[9].in_uop.bits.fcn_dw connect slots_9.io.in_uop.bits.frs3_en, issue_slots[9].in_uop.bits.frs3_en connect slots_9.io.in_uop.bits.lrs2_rtype, issue_slots[9].in_uop.bits.lrs2_rtype connect slots_9.io.in_uop.bits.lrs1_rtype, issue_slots[9].in_uop.bits.lrs1_rtype connect slots_9.io.in_uop.bits.dst_rtype, issue_slots[9].in_uop.bits.dst_rtype connect slots_9.io.in_uop.bits.lrs3, issue_slots[9].in_uop.bits.lrs3 connect slots_9.io.in_uop.bits.lrs2, issue_slots[9].in_uop.bits.lrs2 connect slots_9.io.in_uop.bits.lrs1, issue_slots[9].in_uop.bits.lrs1 connect slots_9.io.in_uop.bits.ldst, issue_slots[9].in_uop.bits.ldst connect slots_9.io.in_uop.bits.ldst_is_rs1, issue_slots[9].in_uop.bits.ldst_is_rs1 connect slots_9.io.in_uop.bits.csr_cmd, issue_slots[9].in_uop.bits.csr_cmd connect slots_9.io.in_uop.bits.flush_on_commit, issue_slots[9].in_uop.bits.flush_on_commit connect slots_9.io.in_uop.bits.is_unique, issue_slots[9].in_uop.bits.is_unique connect slots_9.io.in_uop.bits.uses_stq, issue_slots[9].in_uop.bits.uses_stq connect slots_9.io.in_uop.bits.uses_ldq, issue_slots[9].in_uop.bits.uses_ldq connect slots_9.io.in_uop.bits.mem_signed, issue_slots[9].in_uop.bits.mem_signed connect slots_9.io.in_uop.bits.mem_size, issue_slots[9].in_uop.bits.mem_size connect slots_9.io.in_uop.bits.mem_cmd, issue_slots[9].in_uop.bits.mem_cmd connect slots_9.io.in_uop.bits.exc_cause, issue_slots[9].in_uop.bits.exc_cause connect slots_9.io.in_uop.bits.exception, issue_slots[9].in_uop.bits.exception connect slots_9.io.in_uop.bits.stale_pdst, issue_slots[9].in_uop.bits.stale_pdst connect slots_9.io.in_uop.bits.ppred_busy, issue_slots[9].in_uop.bits.ppred_busy connect slots_9.io.in_uop.bits.prs3_busy, issue_slots[9].in_uop.bits.prs3_busy connect slots_9.io.in_uop.bits.prs2_busy, issue_slots[9].in_uop.bits.prs2_busy connect slots_9.io.in_uop.bits.prs1_busy, issue_slots[9].in_uop.bits.prs1_busy connect slots_9.io.in_uop.bits.ppred, issue_slots[9].in_uop.bits.ppred connect slots_9.io.in_uop.bits.prs3, issue_slots[9].in_uop.bits.prs3 connect slots_9.io.in_uop.bits.prs2, issue_slots[9].in_uop.bits.prs2 connect slots_9.io.in_uop.bits.prs1, issue_slots[9].in_uop.bits.prs1 connect slots_9.io.in_uop.bits.pdst, issue_slots[9].in_uop.bits.pdst connect slots_9.io.in_uop.bits.rxq_idx, issue_slots[9].in_uop.bits.rxq_idx connect slots_9.io.in_uop.bits.stq_idx, issue_slots[9].in_uop.bits.stq_idx connect slots_9.io.in_uop.bits.ldq_idx, issue_slots[9].in_uop.bits.ldq_idx connect slots_9.io.in_uop.bits.rob_idx, issue_slots[9].in_uop.bits.rob_idx connect slots_9.io.in_uop.bits.fp_ctrl.vec, issue_slots[9].in_uop.bits.fp_ctrl.vec connect slots_9.io.in_uop.bits.fp_ctrl.wflags, issue_slots[9].in_uop.bits.fp_ctrl.wflags connect slots_9.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[9].in_uop.bits.fp_ctrl.sqrt connect slots_9.io.in_uop.bits.fp_ctrl.div, issue_slots[9].in_uop.bits.fp_ctrl.div connect slots_9.io.in_uop.bits.fp_ctrl.fma, issue_slots[9].in_uop.bits.fp_ctrl.fma connect slots_9.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].in_uop.bits.fp_ctrl.fastpipe connect slots_9.io.in_uop.bits.fp_ctrl.toint, issue_slots[9].in_uop.bits.fp_ctrl.toint connect slots_9.io.in_uop.bits.fp_ctrl.fromint, issue_slots[9].in_uop.bits.fp_ctrl.fromint connect slots_9.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut connect slots_9.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn connect slots_9.io.in_uop.bits.fp_ctrl.swap23, issue_slots[9].in_uop.bits.fp_ctrl.swap23 connect slots_9.io.in_uop.bits.fp_ctrl.swap12, issue_slots[9].in_uop.bits.fp_ctrl.swap12 connect slots_9.io.in_uop.bits.fp_ctrl.ren3, issue_slots[9].in_uop.bits.fp_ctrl.ren3 connect slots_9.io.in_uop.bits.fp_ctrl.ren2, issue_slots[9].in_uop.bits.fp_ctrl.ren2 connect slots_9.io.in_uop.bits.fp_ctrl.ren1, issue_slots[9].in_uop.bits.fp_ctrl.ren1 connect slots_9.io.in_uop.bits.fp_ctrl.wen, issue_slots[9].in_uop.bits.fp_ctrl.wen connect slots_9.io.in_uop.bits.fp_ctrl.ldst, issue_slots[9].in_uop.bits.fp_ctrl.ldst connect slots_9.io.in_uop.bits.op2_sel, issue_slots[9].in_uop.bits.op2_sel connect slots_9.io.in_uop.bits.op1_sel, issue_slots[9].in_uop.bits.op1_sel connect slots_9.io.in_uop.bits.imm_packed, issue_slots[9].in_uop.bits.imm_packed connect slots_9.io.in_uop.bits.pimm, issue_slots[9].in_uop.bits.pimm connect slots_9.io.in_uop.bits.imm_sel, issue_slots[9].in_uop.bits.imm_sel connect slots_9.io.in_uop.bits.imm_rename, issue_slots[9].in_uop.bits.imm_rename connect slots_9.io.in_uop.bits.taken, issue_slots[9].in_uop.bits.taken connect slots_9.io.in_uop.bits.pc_lob, issue_slots[9].in_uop.bits.pc_lob connect slots_9.io.in_uop.bits.edge_inst, issue_slots[9].in_uop.bits.edge_inst connect slots_9.io.in_uop.bits.ftq_idx, issue_slots[9].in_uop.bits.ftq_idx connect slots_9.io.in_uop.bits.is_mov, issue_slots[9].in_uop.bits.is_mov connect slots_9.io.in_uop.bits.is_rocc, issue_slots[9].in_uop.bits.is_rocc connect slots_9.io.in_uop.bits.is_sys_pc2epc, issue_slots[9].in_uop.bits.is_sys_pc2epc connect slots_9.io.in_uop.bits.is_eret, issue_slots[9].in_uop.bits.is_eret connect slots_9.io.in_uop.bits.is_amo, issue_slots[9].in_uop.bits.is_amo connect slots_9.io.in_uop.bits.is_sfence, issue_slots[9].in_uop.bits.is_sfence connect slots_9.io.in_uop.bits.is_fencei, issue_slots[9].in_uop.bits.is_fencei connect slots_9.io.in_uop.bits.is_fence, issue_slots[9].in_uop.bits.is_fence connect slots_9.io.in_uop.bits.is_sfb, issue_slots[9].in_uop.bits.is_sfb connect slots_9.io.in_uop.bits.br_type, issue_slots[9].in_uop.bits.br_type connect slots_9.io.in_uop.bits.br_tag, issue_slots[9].in_uop.bits.br_tag connect slots_9.io.in_uop.bits.br_mask, issue_slots[9].in_uop.bits.br_mask connect slots_9.io.in_uop.bits.dis_col_sel, issue_slots[9].in_uop.bits.dis_col_sel connect slots_9.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[9].in_uop.bits.iw_p3_bypass_hint connect slots_9.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[9].in_uop.bits.iw_p2_bypass_hint connect slots_9.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[9].in_uop.bits.iw_p1_bypass_hint connect slots_9.io.in_uop.bits.iw_p2_speculative_child, issue_slots[9].in_uop.bits.iw_p2_speculative_child connect slots_9.io.in_uop.bits.iw_p1_speculative_child, issue_slots[9].in_uop.bits.iw_p1_speculative_child connect slots_9.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[9].in_uop.bits.iw_issued_partial_dgen connect slots_9.io.in_uop.bits.iw_issued_partial_agen, issue_slots[9].in_uop.bits.iw_issued_partial_agen connect slots_9.io.in_uop.bits.iw_issued, issue_slots[9].in_uop.bits.iw_issued connect slots_9.io.in_uop.bits.fu_code[0], issue_slots[9].in_uop.bits.fu_code[0] connect slots_9.io.in_uop.bits.fu_code[1], issue_slots[9].in_uop.bits.fu_code[1] connect slots_9.io.in_uop.bits.fu_code[2], issue_slots[9].in_uop.bits.fu_code[2] connect slots_9.io.in_uop.bits.fu_code[3], issue_slots[9].in_uop.bits.fu_code[3] connect slots_9.io.in_uop.bits.fu_code[4], issue_slots[9].in_uop.bits.fu_code[4] connect slots_9.io.in_uop.bits.fu_code[5], issue_slots[9].in_uop.bits.fu_code[5] connect slots_9.io.in_uop.bits.fu_code[6], issue_slots[9].in_uop.bits.fu_code[6] connect slots_9.io.in_uop.bits.fu_code[7], issue_slots[9].in_uop.bits.fu_code[7] connect slots_9.io.in_uop.bits.fu_code[8], issue_slots[9].in_uop.bits.fu_code[8] connect slots_9.io.in_uop.bits.fu_code[9], issue_slots[9].in_uop.bits.fu_code[9] connect slots_9.io.in_uop.bits.iq_type[0], issue_slots[9].in_uop.bits.iq_type[0] connect slots_9.io.in_uop.bits.iq_type[1], issue_slots[9].in_uop.bits.iq_type[1] connect slots_9.io.in_uop.bits.iq_type[2], issue_slots[9].in_uop.bits.iq_type[2] connect slots_9.io.in_uop.bits.iq_type[3], issue_slots[9].in_uop.bits.iq_type[3] connect slots_9.io.in_uop.bits.debug_pc, issue_slots[9].in_uop.bits.debug_pc connect slots_9.io.in_uop.bits.is_rvc, issue_slots[9].in_uop.bits.is_rvc connect slots_9.io.in_uop.bits.debug_inst, issue_slots[9].in_uop.bits.debug_inst connect slots_9.io.in_uop.bits.inst, issue_slots[9].in_uop.bits.inst connect slots_9.io.in_uop.valid, issue_slots[9].in_uop.valid connect issue_slots[9].iss_uop.debug_tsrc, slots_9.io.iss_uop.debug_tsrc connect issue_slots[9].iss_uop.debug_fsrc, slots_9.io.iss_uop.debug_fsrc connect issue_slots[9].iss_uop.bp_xcpt_if, slots_9.io.iss_uop.bp_xcpt_if connect issue_slots[9].iss_uop.bp_debug_if, slots_9.io.iss_uop.bp_debug_if connect issue_slots[9].iss_uop.xcpt_ma_if, slots_9.io.iss_uop.xcpt_ma_if connect issue_slots[9].iss_uop.xcpt_ae_if, slots_9.io.iss_uop.xcpt_ae_if connect issue_slots[9].iss_uop.xcpt_pf_if, slots_9.io.iss_uop.xcpt_pf_if connect issue_slots[9].iss_uop.fp_typ, slots_9.io.iss_uop.fp_typ connect issue_slots[9].iss_uop.fp_rm, slots_9.io.iss_uop.fp_rm connect issue_slots[9].iss_uop.fp_val, slots_9.io.iss_uop.fp_val connect issue_slots[9].iss_uop.fcn_op, slots_9.io.iss_uop.fcn_op connect issue_slots[9].iss_uop.fcn_dw, slots_9.io.iss_uop.fcn_dw connect issue_slots[9].iss_uop.frs3_en, slots_9.io.iss_uop.frs3_en connect issue_slots[9].iss_uop.lrs2_rtype, slots_9.io.iss_uop.lrs2_rtype connect issue_slots[9].iss_uop.lrs1_rtype, slots_9.io.iss_uop.lrs1_rtype connect issue_slots[9].iss_uop.dst_rtype, slots_9.io.iss_uop.dst_rtype connect issue_slots[9].iss_uop.lrs3, slots_9.io.iss_uop.lrs3 connect issue_slots[9].iss_uop.lrs2, slots_9.io.iss_uop.lrs2 connect issue_slots[9].iss_uop.lrs1, slots_9.io.iss_uop.lrs1 connect issue_slots[9].iss_uop.ldst, slots_9.io.iss_uop.ldst connect issue_slots[9].iss_uop.ldst_is_rs1, slots_9.io.iss_uop.ldst_is_rs1 connect issue_slots[9].iss_uop.csr_cmd, slots_9.io.iss_uop.csr_cmd connect issue_slots[9].iss_uop.flush_on_commit, slots_9.io.iss_uop.flush_on_commit connect issue_slots[9].iss_uop.is_unique, slots_9.io.iss_uop.is_unique connect issue_slots[9].iss_uop.uses_stq, slots_9.io.iss_uop.uses_stq connect issue_slots[9].iss_uop.uses_ldq, slots_9.io.iss_uop.uses_ldq connect issue_slots[9].iss_uop.mem_signed, slots_9.io.iss_uop.mem_signed connect issue_slots[9].iss_uop.mem_size, slots_9.io.iss_uop.mem_size connect issue_slots[9].iss_uop.mem_cmd, slots_9.io.iss_uop.mem_cmd connect issue_slots[9].iss_uop.exc_cause, slots_9.io.iss_uop.exc_cause connect issue_slots[9].iss_uop.exception, slots_9.io.iss_uop.exception connect issue_slots[9].iss_uop.stale_pdst, slots_9.io.iss_uop.stale_pdst connect issue_slots[9].iss_uop.ppred_busy, slots_9.io.iss_uop.ppred_busy connect issue_slots[9].iss_uop.prs3_busy, slots_9.io.iss_uop.prs3_busy connect issue_slots[9].iss_uop.prs2_busy, slots_9.io.iss_uop.prs2_busy connect issue_slots[9].iss_uop.prs1_busy, slots_9.io.iss_uop.prs1_busy connect issue_slots[9].iss_uop.ppred, slots_9.io.iss_uop.ppred connect issue_slots[9].iss_uop.prs3, slots_9.io.iss_uop.prs3 connect issue_slots[9].iss_uop.prs2, slots_9.io.iss_uop.prs2 connect issue_slots[9].iss_uop.prs1, slots_9.io.iss_uop.prs1 connect issue_slots[9].iss_uop.pdst, slots_9.io.iss_uop.pdst connect issue_slots[9].iss_uop.rxq_idx, slots_9.io.iss_uop.rxq_idx connect issue_slots[9].iss_uop.stq_idx, slots_9.io.iss_uop.stq_idx connect issue_slots[9].iss_uop.ldq_idx, slots_9.io.iss_uop.ldq_idx connect issue_slots[9].iss_uop.rob_idx, slots_9.io.iss_uop.rob_idx connect issue_slots[9].iss_uop.fp_ctrl.vec, slots_9.io.iss_uop.fp_ctrl.vec connect issue_slots[9].iss_uop.fp_ctrl.wflags, slots_9.io.iss_uop.fp_ctrl.wflags connect issue_slots[9].iss_uop.fp_ctrl.sqrt, slots_9.io.iss_uop.fp_ctrl.sqrt connect issue_slots[9].iss_uop.fp_ctrl.div, slots_9.io.iss_uop.fp_ctrl.div connect issue_slots[9].iss_uop.fp_ctrl.fma, slots_9.io.iss_uop.fp_ctrl.fma connect issue_slots[9].iss_uop.fp_ctrl.fastpipe, slots_9.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[9].iss_uop.fp_ctrl.toint, slots_9.io.iss_uop.fp_ctrl.toint connect issue_slots[9].iss_uop.fp_ctrl.fromint, slots_9.io.iss_uop.fp_ctrl.fromint connect issue_slots[9].iss_uop.fp_ctrl.typeTagOut, slots_9.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[9].iss_uop.fp_ctrl.typeTagIn, slots_9.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[9].iss_uop.fp_ctrl.swap23, slots_9.io.iss_uop.fp_ctrl.swap23 connect issue_slots[9].iss_uop.fp_ctrl.swap12, slots_9.io.iss_uop.fp_ctrl.swap12 connect issue_slots[9].iss_uop.fp_ctrl.ren3, slots_9.io.iss_uop.fp_ctrl.ren3 connect issue_slots[9].iss_uop.fp_ctrl.ren2, slots_9.io.iss_uop.fp_ctrl.ren2 connect issue_slots[9].iss_uop.fp_ctrl.ren1, slots_9.io.iss_uop.fp_ctrl.ren1 connect issue_slots[9].iss_uop.fp_ctrl.wen, slots_9.io.iss_uop.fp_ctrl.wen connect issue_slots[9].iss_uop.fp_ctrl.ldst, slots_9.io.iss_uop.fp_ctrl.ldst connect issue_slots[9].iss_uop.op2_sel, slots_9.io.iss_uop.op2_sel connect issue_slots[9].iss_uop.op1_sel, slots_9.io.iss_uop.op1_sel connect issue_slots[9].iss_uop.imm_packed, slots_9.io.iss_uop.imm_packed connect issue_slots[9].iss_uop.pimm, slots_9.io.iss_uop.pimm connect issue_slots[9].iss_uop.imm_sel, slots_9.io.iss_uop.imm_sel connect issue_slots[9].iss_uop.imm_rename, slots_9.io.iss_uop.imm_rename connect issue_slots[9].iss_uop.taken, slots_9.io.iss_uop.taken connect issue_slots[9].iss_uop.pc_lob, slots_9.io.iss_uop.pc_lob connect issue_slots[9].iss_uop.edge_inst, slots_9.io.iss_uop.edge_inst connect issue_slots[9].iss_uop.ftq_idx, slots_9.io.iss_uop.ftq_idx connect issue_slots[9].iss_uop.is_mov, slots_9.io.iss_uop.is_mov connect issue_slots[9].iss_uop.is_rocc, slots_9.io.iss_uop.is_rocc connect issue_slots[9].iss_uop.is_sys_pc2epc, slots_9.io.iss_uop.is_sys_pc2epc connect issue_slots[9].iss_uop.is_eret, slots_9.io.iss_uop.is_eret connect issue_slots[9].iss_uop.is_amo, slots_9.io.iss_uop.is_amo connect issue_slots[9].iss_uop.is_sfence, slots_9.io.iss_uop.is_sfence connect issue_slots[9].iss_uop.is_fencei, slots_9.io.iss_uop.is_fencei connect issue_slots[9].iss_uop.is_fence, slots_9.io.iss_uop.is_fence connect issue_slots[9].iss_uop.is_sfb, slots_9.io.iss_uop.is_sfb connect issue_slots[9].iss_uop.br_type, slots_9.io.iss_uop.br_type connect issue_slots[9].iss_uop.br_tag, slots_9.io.iss_uop.br_tag connect issue_slots[9].iss_uop.br_mask, slots_9.io.iss_uop.br_mask connect issue_slots[9].iss_uop.dis_col_sel, slots_9.io.iss_uop.dis_col_sel connect issue_slots[9].iss_uop.iw_p3_bypass_hint, slots_9.io.iss_uop.iw_p3_bypass_hint connect issue_slots[9].iss_uop.iw_p2_bypass_hint, slots_9.io.iss_uop.iw_p2_bypass_hint connect issue_slots[9].iss_uop.iw_p1_bypass_hint, slots_9.io.iss_uop.iw_p1_bypass_hint connect issue_slots[9].iss_uop.iw_p2_speculative_child, slots_9.io.iss_uop.iw_p2_speculative_child connect issue_slots[9].iss_uop.iw_p1_speculative_child, slots_9.io.iss_uop.iw_p1_speculative_child connect issue_slots[9].iss_uop.iw_issued_partial_dgen, slots_9.io.iss_uop.iw_issued_partial_dgen connect issue_slots[9].iss_uop.iw_issued_partial_agen, slots_9.io.iss_uop.iw_issued_partial_agen connect issue_slots[9].iss_uop.iw_issued, slots_9.io.iss_uop.iw_issued connect issue_slots[9].iss_uop.fu_code[0], slots_9.io.iss_uop.fu_code[0] connect issue_slots[9].iss_uop.fu_code[1], slots_9.io.iss_uop.fu_code[1] connect issue_slots[9].iss_uop.fu_code[2], slots_9.io.iss_uop.fu_code[2] connect issue_slots[9].iss_uop.fu_code[3], slots_9.io.iss_uop.fu_code[3] connect issue_slots[9].iss_uop.fu_code[4], slots_9.io.iss_uop.fu_code[4] connect issue_slots[9].iss_uop.fu_code[5], slots_9.io.iss_uop.fu_code[5] connect issue_slots[9].iss_uop.fu_code[6], slots_9.io.iss_uop.fu_code[6] connect issue_slots[9].iss_uop.fu_code[7], slots_9.io.iss_uop.fu_code[7] connect issue_slots[9].iss_uop.fu_code[8], slots_9.io.iss_uop.fu_code[8] connect issue_slots[9].iss_uop.fu_code[9], slots_9.io.iss_uop.fu_code[9] connect issue_slots[9].iss_uop.iq_type[0], slots_9.io.iss_uop.iq_type[0] connect issue_slots[9].iss_uop.iq_type[1], slots_9.io.iss_uop.iq_type[1] connect issue_slots[9].iss_uop.iq_type[2], slots_9.io.iss_uop.iq_type[2] connect issue_slots[9].iss_uop.iq_type[3], slots_9.io.iss_uop.iq_type[3] connect issue_slots[9].iss_uop.debug_pc, slots_9.io.iss_uop.debug_pc connect issue_slots[9].iss_uop.is_rvc, slots_9.io.iss_uop.is_rvc connect issue_slots[9].iss_uop.debug_inst, slots_9.io.iss_uop.debug_inst connect issue_slots[9].iss_uop.inst, slots_9.io.iss_uop.inst connect slots_9.io.grant, issue_slots[9].grant connect issue_slots[9].request, slots_9.io.request connect issue_slots[9].will_be_valid, slots_9.io.will_be_valid connect issue_slots[9].valid, slots_9.io.valid connect slots_10.io.child_rebusys, issue_slots[10].child_rebusys connect slots_10.io.pred_wakeup_port.bits, issue_slots[10].pred_wakeup_port.bits connect slots_10.io.pred_wakeup_port.valid, issue_slots[10].pred_wakeup_port.valid connect slots_10.io.wakeup_ports[0].bits.rebusy, issue_slots[10].wakeup_ports[0].bits.rebusy connect slots_10.io.wakeup_ports[0].bits.speculative_mask, issue_slots[10].wakeup_ports[0].bits.speculative_mask connect slots_10.io.wakeup_ports[0].bits.bypassable, issue_slots[10].wakeup_ports[0].bits.bypassable connect slots_10.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[0].bits.uop.debug_tsrc connect slots_10.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[0].bits.uop.debug_fsrc connect slots_10.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_10.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[0].bits.uop.bp_debug_if connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_10.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_10.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[10].wakeup_ports[0].bits.uop.fp_typ connect slots_10.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[10].wakeup_ports[0].bits.uop.fp_rm connect slots_10.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[10].wakeup_ports[0].bits.uop.fp_val connect slots_10.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[10].wakeup_ports[0].bits.uop.fcn_op connect slots_10.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[0].bits.uop.fcn_dw connect slots_10.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[10].wakeup_ports[0].bits.uop.frs3_en connect slots_10.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_10.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_10.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[0].bits.uop.dst_rtype connect slots_10.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[10].wakeup_ports[0].bits.uop.lrs3 connect slots_10.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[10].wakeup_ports[0].bits.uop.lrs2 connect slots_10.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[10].wakeup_ports[0].bits.uop.lrs1 connect slots_10.io.wakeup_ports[0].bits.uop.ldst, issue_slots[10].wakeup_ports[0].bits.uop.ldst connect slots_10.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_10.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[0].bits.uop.csr_cmd connect slots_10.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[0].bits.uop.flush_on_commit connect slots_10.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[10].wakeup_ports[0].bits.uop.is_unique connect slots_10.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[10].wakeup_ports[0].bits.uop.uses_stq connect slots_10.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[0].bits.uop.uses_ldq connect slots_10.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[10].wakeup_ports[0].bits.uop.mem_signed connect slots_10.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[10].wakeup_ports[0].bits.uop.mem_size connect slots_10.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[0].bits.uop.mem_cmd connect slots_10.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[10].wakeup_ports[0].bits.uop.exc_cause connect slots_10.io.wakeup_ports[0].bits.uop.exception, issue_slots[10].wakeup_ports[0].bits.uop.exception connect slots_10.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[0].bits.uop.stale_pdst connect slots_10.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[0].bits.uop.ppred_busy connect slots_10.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs3_busy connect slots_10.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs2_busy connect slots_10.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[0].bits.uop.prs1_busy connect slots_10.io.wakeup_ports[0].bits.uop.ppred, issue_slots[10].wakeup_ports[0].bits.uop.ppred connect slots_10.io.wakeup_ports[0].bits.uop.prs3, issue_slots[10].wakeup_ports[0].bits.uop.prs3 connect slots_10.io.wakeup_ports[0].bits.uop.prs2, issue_slots[10].wakeup_ports[0].bits.uop.prs2 connect slots_10.io.wakeup_ports[0].bits.uop.prs1, issue_slots[10].wakeup_ports[0].bits.uop.prs1 connect slots_10.io.wakeup_ports[0].bits.uop.pdst, issue_slots[10].wakeup_ports[0].bits.uop.pdst connect slots_10.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[0].bits.uop.rxq_idx connect slots_10.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[10].wakeup_ports[0].bits.uop.stq_idx connect slots_10.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[0].bits.uop.ldq_idx connect slots_10.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[10].wakeup_ports[0].bits.uop.rob_idx connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_10.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_10.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[10].wakeup_ports[0].bits.uop.op2_sel connect slots_10.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[10].wakeup_ports[0].bits.uop.op1_sel connect slots_10.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[10].wakeup_ports[0].bits.uop.imm_packed connect slots_10.io.wakeup_ports[0].bits.uop.pimm, issue_slots[10].wakeup_ports[0].bits.uop.pimm connect slots_10.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[10].wakeup_ports[0].bits.uop.imm_sel connect slots_10.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[10].wakeup_ports[0].bits.uop.imm_rename connect slots_10.io.wakeup_ports[0].bits.uop.taken, issue_slots[10].wakeup_ports[0].bits.uop.taken connect slots_10.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[10].wakeup_ports[0].bits.uop.pc_lob connect slots_10.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[10].wakeup_ports[0].bits.uop.edge_inst connect slots_10.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[0].bits.uop.ftq_idx connect slots_10.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[10].wakeup_ports[0].bits.uop.is_mov connect slots_10.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[10].wakeup_ports[0].bits.uop.is_rocc connect slots_10.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_10.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[10].wakeup_ports[0].bits.uop.is_eret connect slots_10.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[10].wakeup_ports[0].bits.uop.is_amo connect slots_10.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[10].wakeup_ports[0].bits.uop.is_sfence connect slots_10.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[10].wakeup_ports[0].bits.uop.is_fencei connect slots_10.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[10].wakeup_ports[0].bits.uop.is_fence connect slots_10.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[10].wakeup_ports[0].bits.uop.is_sfb connect slots_10.io.wakeup_ports[0].bits.uop.br_type, issue_slots[10].wakeup_ports[0].bits.uop.br_type connect slots_10.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[10].wakeup_ports[0].bits.uop.br_tag connect slots_10.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[10].wakeup_ports[0].bits.uop.br_mask connect slots_10.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[0].bits.uop.dis_col_sel connect slots_10.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_10.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_10.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_10.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_10.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_10.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[10].wakeup_ports[0].bits.uop.iw_issued connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[0] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[1] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[2] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[3] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[4] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[5] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[6] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[7] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[8] connect slots_10.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[0].bits.uop.fu_code[9] connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[0] connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[1] connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[2] connect slots_10.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[0].bits.uop.iq_type[3] connect slots_10.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[10].wakeup_ports[0].bits.uop.debug_pc connect slots_10.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[10].wakeup_ports[0].bits.uop.is_rvc connect slots_10.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[10].wakeup_ports[0].bits.uop.debug_inst connect slots_10.io.wakeup_ports[0].bits.uop.inst, issue_slots[10].wakeup_ports[0].bits.uop.inst connect slots_10.io.wakeup_ports[0].valid, issue_slots[10].wakeup_ports[0].valid connect slots_10.io.wakeup_ports[1].bits.rebusy, issue_slots[10].wakeup_ports[1].bits.rebusy connect slots_10.io.wakeup_ports[1].bits.speculative_mask, issue_slots[10].wakeup_ports[1].bits.speculative_mask connect slots_10.io.wakeup_ports[1].bits.bypassable, issue_slots[10].wakeup_ports[1].bits.bypassable connect slots_10.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[10].wakeup_ports[1].bits.uop.debug_tsrc connect slots_10.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[10].wakeup_ports[1].bits.uop.debug_fsrc connect slots_10.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[10].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_10.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[10].wakeup_ports[1].bits.uop.bp_debug_if connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_10.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[10].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_10.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[10].wakeup_ports[1].bits.uop.fp_typ connect slots_10.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[10].wakeup_ports[1].bits.uop.fp_rm connect slots_10.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[10].wakeup_ports[1].bits.uop.fp_val connect slots_10.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[10].wakeup_ports[1].bits.uop.fcn_op connect slots_10.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[10].wakeup_ports[1].bits.uop.fcn_dw connect slots_10.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[10].wakeup_ports[1].bits.uop.frs3_en connect slots_10.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[10].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_10.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[10].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_10.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[10].wakeup_ports[1].bits.uop.dst_rtype connect slots_10.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[10].wakeup_ports[1].bits.uop.lrs3 connect slots_10.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[10].wakeup_ports[1].bits.uop.lrs2 connect slots_10.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[10].wakeup_ports[1].bits.uop.lrs1 connect slots_10.io.wakeup_ports[1].bits.uop.ldst, issue_slots[10].wakeup_ports[1].bits.uop.ldst connect slots_10.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[10].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_10.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[10].wakeup_ports[1].bits.uop.csr_cmd connect slots_10.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[10].wakeup_ports[1].bits.uop.flush_on_commit connect slots_10.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[10].wakeup_ports[1].bits.uop.is_unique connect slots_10.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[10].wakeup_ports[1].bits.uop.uses_stq connect slots_10.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[10].wakeup_ports[1].bits.uop.uses_ldq connect slots_10.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[10].wakeup_ports[1].bits.uop.mem_signed connect slots_10.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[10].wakeup_ports[1].bits.uop.mem_size connect slots_10.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[10].wakeup_ports[1].bits.uop.mem_cmd connect slots_10.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[10].wakeup_ports[1].bits.uop.exc_cause connect slots_10.io.wakeup_ports[1].bits.uop.exception, issue_slots[10].wakeup_ports[1].bits.uop.exception connect slots_10.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[10].wakeup_ports[1].bits.uop.stale_pdst connect slots_10.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[10].wakeup_ports[1].bits.uop.ppred_busy connect slots_10.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs3_busy connect slots_10.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs2_busy connect slots_10.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[10].wakeup_ports[1].bits.uop.prs1_busy connect slots_10.io.wakeup_ports[1].bits.uop.ppred, issue_slots[10].wakeup_ports[1].bits.uop.ppred connect slots_10.io.wakeup_ports[1].bits.uop.prs3, issue_slots[10].wakeup_ports[1].bits.uop.prs3 connect slots_10.io.wakeup_ports[1].bits.uop.prs2, issue_slots[10].wakeup_ports[1].bits.uop.prs2 connect slots_10.io.wakeup_ports[1].bits.uop.prs1, issue_slots[10].wakeup_ports[1].bits.uop.prs1 connect slots_10.io.wakeup_ports[1].bits.uop.pdst, issue_slots[10].wakeup_ports[1].bits.uop.pdst connect slots_10.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[10].wakeup_ports[1].bits.uop.rxq_idx connect slots_10.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[10].wakeup_ports[1].bits.uop.stq_idx connect slots_10.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[10].wakeup_ports[1].bits.uop.ldq_idx connect slots_10.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[10].wakeup_ports[1].bits.uop.rob_idx connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_10.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_10.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[10].wakeup_ports[1].bits.uop.op2_sel connect slots_10.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[10].wakeup_ports[1].bits.uop.op1_sel connect slots_10.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[10].wakeup_ports[1].bits.uop.imm_packed connect slots_10.io.wakeup_ports[1].bits.uop.pimm, issue_slots[10].wakeup_ports[1].bits.uop.pimm connect slots_10.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[10].wakeup_ports[1].bits.uop.imm_sel connect slots_10.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[10].wakeup_ports[1].bits.uop.imm_rename connect slots_10.io.wakeup_ports[1].bits.uop.taken, issue_slots[10].wakeup_ports[1].bits.uop.taken connect slots_10.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[10].wakeup_ports[1].bits.uop.pc_lob connect slots_10.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[10].wakeup_ports[1].bits.uop.edge_inst connect slots_10.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[10].wakeup_ports[1].bits.uop.ftq_idx connect slots_10.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[10].wakeup_ports[1].bits.uop.is_mov connect slots_10.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[10].wakeup_ports[1].bits.uop.is_rocc connect slots_10.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[10].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_10.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[10].wakeup_ports[1].bits.uop.is_eret connect slots_10.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[10].wakeup_ports[1].bits.uop.is_amo connect slots_10.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[10].wakeup_ports[1].bits.uop.is_sfence connect slots_10.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[10].wakeup_ports[1].bits.uop.is_fencei connect slots_10.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[10].wakeup_ports[1].bits.uop.is_fence connect slots_10.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[10].wakeup_ports[1].bits.uop.is_sfb connect slots_10.io.wakeup_ports[1].bits.uop.br_type, issue_slots[10].wakeup_ports[1].bits.uop.br_type connect slots_10.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[10].wakeup_ports[1].bits.uop.br_tag connect slots_10.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[10].wakeup_ports[1].bits.uop.br_mask connect slots_10.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[10].wakeup_ports[1].bits.uop.dis_col_sel connect slots_10.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_10.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_10.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_10.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_10.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_10.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[10].wakeup_ports[1].bits.uop.iw_issued connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[0] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[1] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[2] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[3] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[4] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[5] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[6] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[7] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[8] connect slots_10.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[10].wakeup_ports[1].bits.uop.fu_code[9] connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[0] connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[1] connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[2] connect slots_10.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[10].wakeup_ports[1].bits.uop.iq_type[3] connect slots_10.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[10].wakeup_ports[1].bits.uop.debug_pc connect slots_10.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[10].wakeup_ports[1].bits.uop.is_rvc connect slots_10.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[10].wakeup_ports[1].bits.uop.debug_inst connect slots_10.io.wakeup_ports[1].bits.uop.inst, issue_slots[10].wakeup_ports[1].bits.uop.inst connect slots_10.io.wakeup_ports[1].valid, issue_slots[10].wakeup_ports[1].valid connect slots_10.io.squash_grant, issue_slots[10].squash_grant connect slots_10.io.clear, issue_slots[10].clear connect slots_10.io.kill, issue_slots[10].kill connect slots_10.io.brupdate.b2.target_offset, issue_slots[10].brupdate.b2.target_offset connect slots_10.io.brupdate.b2.jalr_target, issue_slots[10].brupdate.b2.jalr_target connect slots_10.io.brupdate.b2.pc_sel, issue_slots[10].brupdate.b2.pc_sel connect slots_10.io.brupdate.b2.cfi_type, issue_slots[10].brupdate.b2.cfi_type connect slots_10.io.brupdate.b2.taken, issue_slots[10].brupdate.b2.taken connect slots_10.io.brupdate.b2.mispredict, issue_slots[10].brupdate.b2.mispredict connect slots_10.io.brupdate.b2.uop.debug_tsrc, issue_slots[10].brupdate.b2.uop.debug_tsrc connect slots_10.io.brupdate.b2.uop.debug_fsrc, issue_slots[10].brupdate.b2.uop.debug_fsrc connect slots_10.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[10].brupdate.b2.uop.bp_xcpt_if connect slots_10.io.brupdate.b2.uop.bp_debug_if, issue_slots[10].brupdate.b2.uop.bp_debug_if connect slots_10.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[10].brupdate.b2.uop.xcpt_ma_if connect slots_10.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[10].brupdate.b2.uop.xcpt_ae_if connect slots_10.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[10].brupdate.b2.uop.xcpt_pf_if connect slots_10.io.brupdate.b2.uop.fp_typ, issue_slots[10].brupdate.b2.uop.fp_typ connect slots_10.io.brupdate.b2.uop.fp_rm, issue_slots[10].brupdate.b2.uop.fp_rm connect slots_10.io.brupdate.b2.uop.fp_val, issue_slots[10].brupdate.b2.uop.fp_val connect slots_10.io.brupdate.b2.uop.fcn_op, issue_slots[10].brupdate.b2.uop.fcn_op connect slots_10.io.brupdate.b2.uop.fcn_dw, issue_slots[10].brupdate.b2.uop.fcn_dw connect slots_10.io.brupdate.b2.uop.frs3_en, issue_slots[10].brupdate.b2.uop.frs3_en connect slots_10.io.brupdate.b2.uop.lrs2_rtype, issue_slots[10].brupdate.b2.uop.lrs2_rtype connect slots_10.io.brupdate.b2.uop.lrs1_rtype, issue_slots[10].brupdate.b2.uop.lrs1_rtype connect slots_10.io.brupdate.b2.uop.dst_rtype, issue_slots[10].brupdate.b2.uop.dst_rtype connect slots_10.io.brupdate.b2.uop.lrs3, issue_slots[10].brupdate.b2.uop.lrs3 connect slots_10.io.brupdate.b2.uop.lrs2, issue_slots[10].brupdate.b2.uop.lrs2 connect slots_10.io.brupdate.b2.uop.lrs1, issue_slots[10].brupdate.b2.uop.lrs1 connect slots_10.io.brupdate.b2.uop.ldst, issue_slots[10].brupdate.b2.uop.ldst connect slots_10.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[10].brupdate.b2.uop.ldst_is_rs1 connect slots_10.io.brupdate.b2.uop.csr_cmd, issue_slots[10].brupdate.b2.uop.csr_cmd connect slots_10.io.brupdate.b2.uop.flush_on_commit, issue_slots[10].brupdate.b2.uop.flush_on_commit connect slots_10.io.brupdate.b2.uop.is_unique, issue_slots[10].brupdate.b2.uop.is_unique connect slots_10.io.brupdate.b2.uop.uses_stq, issue_slots[10].brupdate.b2.uop.uses_stq connect slots_10.io.brupdate.b2.uop.uses_ldq, issue_slots[10].brupdate.b2.uop.uses_ldq connect slots_10.io.brupdate.b2.uop.mem_signed, issue_slots[10].brupdate.b2.uop.mem_signed connect slots_10.io.brupdate.b2.uop.mem_size, issue_slots[10].brupdate.b2.uop.mem_size connect slots_10.io.brupdate.b2.uop.mem_cmd, issue_slots[10].brupdate.b2.uop.mem_cmd connect slots_10.io.brupdate.b2.uop.exc_cause, issue_slots[10].brupdate.b2.uop.exc_cause connect slots_10.io.brupdate.b2.uop.exception, issue_slots[10].brupdate.b2.uop.exception connect slots_10.io.brupdate.b2.uop.stale_pdst, issue_slots[10].brupdate.b2.uop.stale_pdst connect slots_10.io.brupdate.b2.uop.ppred_busy, issue_slots[10].brupdate.b2.uop.ppred_busy connect slots_10.io.brupdate.b2.uop.prs3_busy, issue_slots[10].brupdate.b2.uop.prs3_busy connect slots_10.io.brupdate.b2.uop.prs2_busy, issue_slots[10].brupdate.b2.uop.prs2_busy connect slots_10.io.brupdate.b2.uop.prs1_busy, issue_slots[10].brupdate.b2.uop.prs1_busy connect slots_10.io.brupdate.b2.uop.ppred, issue_slots[10].brupdate.b2.uop.ppred connect slots_10.io.brupdate.b2.uop.prs3, issue_slots[10].brupdate.b2.uop.prs3 connect slots_10.io.brupdate.b2.uop.prs2, issue_slots[10].brupdate.b2.uop.prs2 connect slots_10.io.brupdate.b2.uop.prs1, issue_slots[10].brupdate.b2.uop.prs1 connect slots_10.io.brupdate.b2.uop.pdst, issue_slots[10].brupdate.b2.uop.pdst connect slots_10.io.brupdate.b2.uop.rxq_idx, issue_slots[10].brupdate.b2.uop.rxq_idx connect slots_10.io.brupdate.b2.uop.stq_idx, issue_slots[10].brupdate.b2.uop.stq_idx connect slots_10.io.brupdate.b2.uop.ldq_idx, issue_slots[10].brupdate.b2.uop.ldq_idx connect slots_10.io.brupdate.b2.uop.rob_idx, issue_slots[10].brupdate.b2.uop.rob_idx connect slots_10.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[10].brupdate.b2.uop.fp_ctrl.vec connect slots_10.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[10].brupdate.b2.uop.fp_ctrl.wflags connect slots_10.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[10].brupdate.b2.uop.fp_ctrl.sqrt connect slots_10.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[10].brupdate.b2.uop.fp_ctrl.div connect slots_10.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[10].brupdate.b2.uop.fp_ctrl.fma connect slots_10.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[10].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_10.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[10].brupdate.b2.uop.fp_ctrl.toint connect slots_10.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[10].brupdate.b2.uop.fp_ctrl.fromint connect slots_10.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_10.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_10.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[10].brupdate.b2.uop.fp_ctrl.swap23 connect slots_10.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[10].brupdate.b2.uop.fp_ctrl.swap12 connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren3 connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren2 connect slots_10.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[10].brupdate.b2.uop.fp_ctrl.ren1 connect slots_10.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[10].brupdate.b2.uop.fp_ctrl.wen connect slots_10.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[10].brupdate.b2.uop.fp_ctrl.ldst connect slots_10.io.brupdate.b2.uop.op2_sel, issue_slots[10].brupdate.b2.uop.op2_sel connect slots_10.io.brupdate.b2.uop.op1_sel, issue_slots[10].brupdate.b2.uop.op1_sel connect slots_10.io.brupdate.b2.uop.imm_packed, issue_slots[10].brupdate.b2.uop.imm_packed connect slots_10.io.brupdate.b2.uop.pimm, issue_slots[10].brupdate.b2.uop.pimm connect slots_10.io.brupdate.b2.uop.imm_sel, issue_slots[10].brupdate.b2.uop.imm_sel connect slots_10.io.brupdate.b2.uop.imm_rename, issue_slots[10].brupdate.b2.uop.imm_rename connect slots_10.io.brupdate.b2.uop.taken, issue_slots[10].brupdate.b2.uop.taken connect slots_10.io.brupdate.b2.uop.pc_lob, issue_slots[10].brupdate.b2.uop.pc_lob connect slots_10.io.brupdate.b2.uop.edge_inst, issue_slots[10].brupdate.b2.uop.edge_inst connect slots_10.io.brupdate.b2.uop.ftq_idx, issue_slots[10].brupdate.b2.uop.ftq_idx connect slots_10.io.brupdate.b2.uop.is_mov, issue_slots[10].brupdate.b2.uop.is_mov connect slots_10.io.brupdate.b2.uop.is_rocc, issue_slots[10].brupdate.b2.uop.is_rocc connect slots_10.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[10].brupdate.b2.uop.is_sys_pc2epc connect slots_10.io.brupdate.b2.uop.is_eret, issue_slots[10].brupdate.b2.uop.is_eret connect slots_10.io.brupdate.b2.uop.is_amo, issue_slots[10].brupdate.b2.uop.is_amo connect slots_10.io.brupdate.b2.uop.is_sfence, issue_slots[10].brupdate.b2.uop.is_sfence connect slots_10.io.brupdate.b2.uop.is_fencei, issue_slots[10].brupdate.b2.uop.is_fencei connect slots_10.io.brupdate.b2.uop.is_fence, issue_slots[10].brupdate.b2.uop.is_fence connect slots_10.io.brupdate.b2.uop.is_sfb, issue_slots[10].brupdate.b2.uop.is_sfb connect slots_10.io.brupdate.b2.uop.br_type, issue_slots[10].brupdate.b2.uop.br_type connect slots_10.io.brupdate.b2.uop.br_tag, issue_slots[10].brupdate.b2.uop.br_tag connect slots_10.io.brupdate.b2.uop.br_mask, issue_slots[10].brupdate.b2.uop.br_mask connect slots_10.io.brupdate.b2.uop.dis_col_sel, issue_slots[10].brupdate.b2.uop.dis_col_sel connect slots_10.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p3_bypass_hint connect slots_10.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p2_bypass_hint connect slots_10.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[10].brupdate.b2.uop.iw_p1_bypass_hint connect slots_10.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[10].brupdate.b2.uop.iw_p2_speculative_child connect slots_10.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[10].brupdate.b2.uop.iw_p1_speculative_child connect slots_10.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[10].brupdate.b2.uop.iw_issued_partial_dgen connect slots_10.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[10].brupdate.b2.uop.iw_issued_partial_agen connect slots_10.io.brupdate.b2.uop.iw_issued, issue_slots[10].brupdate.b2.uop.iw_issued connect slots_10.io.brupdate.b2.uop.fu_code[0], issue_slots[10].brupdate.b2.uop.fu_code[0] connect slots_10.io.brupdate.b2.uop.fu_code[1], issue_slots[10].brupdate.b2.uop.fu_code[1] connect slots_10.io.brupdate.b2.uop.fu_code[2], issue_slots[10].brupdate.b2.uop.fu_code[2] connect slots_10.io.brupdate.b2.uop.fu_code[3], issue_slots[10].brupdate.b2.uop.fu_code[3] connect slots_10.io.brupdate.b2.uop.fu_code[4], issue_slots[10].brupdate.b2.uop.fu_code[4] connect slots_10.io.brupdate.b2.uop.fu_code[5], issue_slots[10].brupdate.b2.uop.fu_code[5] connect slots_10.io.brupdate.b2.uop.fu_code[6], issue_slots[10].brupdate.b2.uop.fu_code[6] connect slots_10.io.brupdate.b2.uop.fu_code[7], issue_slots[10].brupdate.b2.uop.fu_code[7] connect slots_10.io.brupdate.b2.uop.fu_code[8], issue_slots[10].brupdate.b2.uop.fu_code[8] connect slots_10.io.brupdate.b2.uop.fu_code[9], issue_slots[10].brupdate.b2.uop.fu_code[9] connect slots_10.io.brupdate.b2.uop.iq_type[0], issue_slots[10].brupdate.b2.uop.iq_type[0] connect slots_10.io.brupdate.b2.uop.iq_type[1], issue_slots[10].brupdate.b2.uop.iq_type[1] connect slots_10.io.brupdate.b2.uop.iq_type[2], issue_slots[10].brupdate.b2.uop.iq_type[2] connect slots_10.io.brupdate.b2.uop.iq_type[3], issue_slots[10].brupdate.b2.uop.iq_type[3] connect slots_10.io.brupdate.b2.uop.debug_pc, issue_slots[10].brupdate.b2.uop.debug_pc connect slots_10.io.brupdate.b2.uop.is_rvc, issue_slots[10].brupdate.b2.uop.is_rvc connect slots_10.io.brupdate.b2.uop.debug_inst, issue_slots[10].brupdate.b2.uop.debug_inst connect slots_10.io.brupdate.b2.uop.inst, issue_slots[10].brupdate.b2.uop.inst connect slots_10.io.brupdate.b1.mispredict_mask, issue_slots[10].brupdate.b1.mispredict_mask connect slots_10.io.brupdate.b1.resolve_mask, issue_slots[10].brupdate.b1.resolve_mask connect issue_slots[10].out_uop.debug_tsrc, slots_10.io.out_uop.debug_tsrc connect issue_slots[10].out_uop.debug_fsrc, slots_10.io.out_uop.debug_fsrc connect issue_slots[10].out_uop.bp_xcpt_if, slots_10.io.out_uop.bp_xcpt_if connect issue_slots[10].out_uop.bp_debug_if, slots_10.io.out_uop.bp_debug_if connect issue_slots[10].out_uop.xcpt_ma_if, slots_10.io.out_uop.xcpt_ma_if connect issue_slots[10].out_uop.xcpt_ae_if, slots_10.io.out_uop.xcpt_ae_if connect issue_slots[10].out_uop.xcpt_pf_if, slots_10.io.out_uop.xcpt_pf_if connect issue_slots[10].out_uop.fp_typ, slots_10.io.out_uop.fp_typ connect issue_slots[10].out_uop.fp_rm, slots_10.io.out_uop.fp_rm connect issue_slots[10].out_uop.fp_val, slots_10.io.out_uop.fp_val connect issue_slots[10].out_uop.fcn_op, slots_10.io.out_uop.fcn_op connect issue_slots[10].out_uop.fcn_dw, slots_10.io.out_uop.fcn_dw connect issue_slots[10].out_uop.frs3_en, slots_10.io.out_uop.frs3_en connect issue_slots[10].out_uop.lrs2_rtype, slots_10.io.out_uop.lrs2_rtype connect issue_slots[10].out_uop.lrs1_rtype, slots_10.io.out_uop.lrs1_rtype connect issue_slots[10].out_uop.dst_rtype, slots_10.io.out_uop.dst_rtype connect issue_slots[10].out_uop.lrs3, slots_10.io.out_uop.lrs3 connect issue_slots[10].out_uop.lrs2, slots_10.io.out_uop.lrs2 connect issue_slots[10].out_uop.lrs1, slots_10.io.out_uop.lrs1 connect issue_slots[10].out_uop.ldst, slots_10.io.out_uop.ldst connect issue_slots[10].out_uop.ldst_is_rs1, slots_10.io.out_uop.ldst_is_rs1 connect issue_slots[10].out_uop.csr_cmd, slots_10.io.out_uop.csr_cmd connect issue_slots[10].out_uop.flush_on_commit, slots_10.io.out_uop.flush_on_commit connect issue_slots[10].out_uop.is_unique, slots_10.io.out_uop.is_unique connect issue_slots[10].out_uop.uses_stq, slots_10.io.out_uop.uses_stq connect issue_slots[10].out_uop.uses_ldq, slots_10.io.out_uop.uses_ldq connect issue_slots[10].out_uop.mem_signed, slots_10.io.out_uop.mem_signed connect issue_slots[10].out_uop.mem_size, slots_10.io.out_uop.mem_size connect issue_slots[10].out_uop.mem_cmd, slots_10.io.out_uop.mem_cmd connect issue_slots[10].out_uop.exc_cause, slots_10.io.out_uop.exc_cause connect issue_slots[10].out_uop.exception, slots_10.io.out_uop.exception connect issue_slots[10].out_uop.stale_pdst, slots_10.io.out_uop.stale_pdst connect issue_slots[10].out_uop.ppred_busy, slots_10.io.out_uop.ppred_busy connect issue_slots[10].out_uop.prs3_busy, slots_10.io.out_uop.prs3_busy connect issue_slots[10].out_uop.prs2_busy, slots_10.io.out_uop.prs2_busy connect issue_slots[10].out_uop.prs1_busy, slots_10.io.out_uop.prs1_busy connect issue_slots[10].out_uop.ppred, slots_10.io.out_uop.ppred connect issue_slots[10].out_uop.prs3, slots_10.io.out_uop.prs3 connect issue_slots[10].out_uop.prs2, slots_10.io.out_uop.prs2 connect issue_slots[10].out_uop.prs1, slots_10.io.out_uop.prs1 connect issue_slots[10].out_uop.pdst, slots_10.io.out_uop.pdst connect issue_slots[10].out_uop.rxq_idx, slots_10.io.out_uop.rxq_idx connect issue_slots[10].out_uop.stq_idx, slots_10.io.out_uop.stq_idx connect issue_slots[10].out_uop.ldq_idx, slots_10.io.out_uop.ldq_idx connect issue_slots[10].out_uop.rob_idx, slots_10.io.out_uop.rob_idx connect issue_slots[10].out_uop.fp_ctrl.vec, slots_10.io.out_uop.fp_ctrl.vec connect issue_slots[10].out_uop.fp_ctrl.wflags, slots_10.io.out_uop.fp_ctrl.wflags connect issue_slots[10].out_uop.fp_ctrl.sqrt, slots_10.io.out_uop.fp_ctrl.sqrt connect issue_slots[10].out_uop.fp_ctrl.div, slots_10.io.out_uop.fp_ctrl.div connect issue_slots[10].out_uop.fp_ctrl.fma, slots_10.io.out_uop.fp_ctrl.fma connect issue_slots[10].out_uop.fp_ctrl.fastpipe, slots_10.io.out_uop.fp_ctrl.fastpipe connect issue_slots[10].out_uop.fp_ctrl.toint, slots_10.io.out_uop.fp_ctrl.toint connect issue_slots[10].out_uop.fp_ctrl.fromint, slots_10.io.out_uop.fp_ctrl.fromint connect issue_slots[10].out_uop.fp_ctrl.typeTagOut, slots_10.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[10].out_uop.fp_ctrl.typeTagIn, slots_10.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[10].out_uop.fp_ctrl.swap23, slots_10.io.out_uop.fp_ctrl.swap23 connect issue_slots[10].out_uop.fp_ctrl.swap12, slots_10.io.out_uop.fp_ctrl.swap12 connect issue_slots[10].out_uop.fp_ctrl.ren3, slots_10.io.out_uop.fp_ctrl.ren3 connect issue_slots[10].out_uop.fp_ctrl.ren2, slots_10.io.out_uop.fp_ctrl.ren2 connect issue_slots[10].out_uop.fp_ctrl.ren1, slots_10.io.out_uop.fp_ctrl.ren1 connect issue_slots[10].out_uop.fp_ctrl.wen, slots_10.io.out_uop.fp_ctrl.wen connect issue_slots[10].out_uop.fp_ctrl.ldst, slots_10.io.out_uop.fp_ctrl.ldst connect issue_slots[10].out_uop.op2_sel, slots_10.io.out_uop.op2_sel connect issue_slots[10].out_uop.op1_sel, slots_10.io.out_uop.op1_sel connect issue_slots[10].out_uop.imm_packed, slots_10.io.out_uop.imm_packed connect issue_slots[10].out_uop.pimm, slots_10.io.out_uop.pimm connect issue_slots[10].out_uop.imm_sel, slots_10.io.out_uop.imm_sel connect issue_slots[10].out_uop.imm_rename, slots_10.io.out_uop.imm_rename connect issue_slots[10].out_uop.taken, slots_10.io.out_uop.taken connect issue_slots[10].out_uop.pc_lob, slots_10.io.out_uop.pc_lob connect issue_slots[10].out_uop.edge_inst, slots_10.io.out_uop.edge_inst connect issue_slots[10].out_uop.ftq_idx, slots_10.io.out_uop.ftq_idx connect issue_slots[10].out_uop.is_mov, slots_10.io.out_uop.is_mov connect issue_slots[10].out_uop.is_rocc, slots_10.io.out_uop.is_rocc connect issue_slots[10].out_uop.is_sys_pc2epc, slots_10.io.out_uop.is_sys_pc2epc connect issue_slots[10].out_uop.is_eret, slots_10.io.out_uop.is_eret connect issue_slots[10].out_uop.is_amo, slots_10.io.out_uop.is_amo connect issue_slots[10].out_uop.is_sfence, slots_10.io.out_uop.is_sfence connect issue_slots[10].out_uop.is_fencei, slots_10.io.out_uop.is_fencei connect issue_slots[10].out_uop.is_fence, slots_10.io.out_uop.is_fence connect issue_slots[10].out_uop.is_sfb, slots_10.io.out_uop.is_sfb connect issue_slots[10].out_uop.br_type, slots_10.io.out_uop.br_type connect issue_slots[10].out_uop.br_tag, slots_10.io.out_uop.br_tag connect issue_slots[10].out_uop.br_mask, slots_10.io.out_uop.br_mask connect issue_slots[10].out_uop.dis_col_sel, slots_10.io.out_uop.dis_col_sel connect issue_slots[10].out_uop.iw_p3_bypass_hint, slots_10.io.out_uop.iw_p3_bypass_hint connect issue_slots[10].out_uop.iw_p2_bypass_hint, slots_10.io.out_uop.iw_p2_bypass_hint connect issue_slots[10].out_uop.iw_p1_bypass_hint, slots_10.io.out_uop.iw_p1_bypass_hint connect issue_slots[10].out_uop.iw_p2_speculative_child, slots_10.io.out_uop.iw_p2_speculative_child connect issue_slots[10].out_uop.iw_p1_speculative_child, slots_10.io.out_uop.iw_p1_speculative_child connect issue_slots[10].out_uop.iw_issued_partial_dgen, slots_10.io.out_uop.iw_issued_partial_dgen connect issue_slots[10].out_uop.iw_issued_partial_agen, slots_10.io.out_uop.iw_issued_partial_agen connect issue_slots[10].out_uop.iw_issued, slots_10.io.out_uop.iw_issued connect issue_slots[10].out_uop.fu_code[0], slots_10.io.out_uop.fu_code[0] connect issue_slots[10].out_uop.fu_code[1], slots_10.io.out_uop.fu_code[1] connect issue_slots[10].out_uop.fu_code[2], slots_10.io.out_uop.fu_code[2] connect issue_slots[10].out_uop.fu_code[3], slots_10.io.out_uop.fu_code[3] connect issue_slots[10].out_uop.fu_code[4], slots_10.io.out_uop.fu_code[4] connect issue_slots[10].out_uop.fu_code[5], slots_10.io.out_uop.fu_code[5] connect issue_slots[10].out_uop.fu_code[6], slots_10.io.out_uop.fu_code[6] connect issue_slots[10].out_uop.fu_code[7], slots_10.io.out_uop.fu_code[7] connect issue_slots[10].out_uop.fu_code[8], slots_10.io.out_uop.fu_code[8] connect issue_slots[10].out_uop.fu_code[9], slots_10.io.out_uop.fu_code[9] connect issue_slots[10].out_uop.iq_type[0], slots_10.io.out_uop.iq_type[0] connect issue_slots[10].out_uop.iq_type[1], slots_10.io.out_uop.iq_type[1] connect issue_slots[10].out_uop.iq_type[2], slots_10.io.out_uop.iq_type[2] connect issue_slots[10].out_uop.iq_type[3], slots_10.io.out_uop.iq_type[3] connect issue_slots[10].out_uop.debug_pc, slots_10.io.out_uop.debug_pc connect issue_slots[10].out_uop.is_rvc, slots_10.io.out_uop.is_rvc connect issue_slots[10].out_uop.debug_inst, slots_10.io.out_uop.debug_inst connect issue_slots[10].out_uop.inst, slots_10.io.out_uop.inst connect slots_10.io.in_uop.bits.debug_tsrc, issue_slots[10].in_uop.bits.debug_tsrc connect slots_10.io.in_uop.bits.debug_fsrc, issue_slots[10].in_uop.bits.debug_fsrc connect slots_10.io.in_uop.bits.bp_xcpt_if, issue_slots[10].in_uop.bits.bp_xcpt_if connect slots_10.io.in_uop.bits.bp_debug_if, issue_slots[10].in_uop.bits.bp_debug_if connect slots_10.io.in_uop.bits.xcpt_ma_if, issue_slots[10].in_uop.bits.xcpt_ma_if connect slots_10.io.in_uop.bits.xcpt_ae_if, issue_slots[10].in_uop.bits.xcpt_ae_if connect slots_10.io.in_uop.bits.xcpt_pf_if, issue_slots[10].in_uop.bits.xcpt_pf_if connect slots_10.io.in_uop.bits.fp_typ, issue_slots[10].in_uop.bits.fp_typ connect slots_10.io.in_uop.bits.fp_rm, issue_slots[10].in_uop.bits.fp_rm connect slots_10.io.in_uop.bits.fp_val, issue_slots[10].in_uop.bits.fp_val connect slots_10.io.in_uop.bits.fcn_op, issue_slots[10].in_uop.bits.fcn_op connect slots_10.io.in_uop.bits.fcn_dw, issue_slots[10].in_uop.bits.fcn_dw connect slots_10.io.in_uop.bits.frs3_en, issue_slots[10].in_uop.bits.frs3_en connect slots_10.io.in_uop.bits.lrs2_rtype, issue_slots[10].in_uop.bits.lrs2_rtype connect slots_10.io.in_uop.bits.lrs1_rtype, issue_slots[10].in_uop.bits.lrs1_rtype connect slots_10.io.in_uop.bits.dst_rtype, issue_slots[10].in_uop.bits.dst_rtype connect slots_10.io.in_uop.bits.lrs3, issue_slots[10].in_uop.bits.lrs3 connect slots_10.io.in_uop.bits.lrs2, issue_slots[10].in_uop.bits.lrs2 connect slots_10.io.in_uop.bits.lrs1, issue_slots[10].in_uop.bits.lrs1 connect slots_10.io.in_uop.bits.ldst, issue_slots[10].in_uop.bits.ldst connect slots_10.io.in_uop.bits.ldst_is_rs1, issue_slots[10].in_uop.bits.ldst_is_rs1 connect slots_10.io.in_uop.bits.csr_cmd, issue_slots[10].in_uop.bits.csr_cmd connect slots_10.io.in_uop.bits.flush_on_commit, issue_slots[10].in_uop.bits.flush_on_commit connect slots_10.io.in_uop.bits.is_unique, issue_slots[10].in_uop.bits.is_unique connect slots_10.io.in_uop.bits.uses_stq, issue_slots[10].in_uop.bits.uses_stq connect slots_10.io.in_uop.bits.uses_ldq, issue_slots[10].in_uop.bits.uses_ldq connect slots_10.io.in_uop.bits.mem_signed, issue_slots[10].in_uop.bits.mem_signed connect slots_10.io.in_uop.bits.mem_size, issue_slots[10].in_uop.bits.mem_size connect slots_10.io.in_uop.bits.mem_cmd, issue_slots[10].in_uop.bits.mem_cmd connect slots_10.io.in_uop.bits.exc_cause, issue_slots[10].in_uop.bits.exc_cause connect slots_10.io.in_uop.bits.exception, issue_slots[10].in_uop.bits.exception connect slots_10.io.in_uop.bits.stale_pdst, issue_slots[10].in_uop.bits.stale_pdst connect slots_10.io.in_uop.bits.ppred_busy, issue_slots[10].in_uop.bits.ppred_busy connect slots_10.io.in_uop.bits.prs3_busy, issue_slots[10].in_uop.bits.prs3_busy connect slots_10.io.in_uop.bits.prs2_busy, issue_slots[10].in_uop.bits.prs2_busy connect slots_10.io.in_uop.bits.prs1_busy, issue_slots[10].in_uop.bits.prs1_busy connect slots_10.io.in_uop.bits.ppred, issue_slots[10].in_uop.bits.ppred connect slots_10.io.in_uop.bits.prs3, issue_slots[10].in_uop.bits.prs3 connect slots_10.io.in_uop.bits.prs2, issue_slots[10].in_uop.bits.prs2 connect slots_10.io.in_uop.bits.prs1, issue_slots[10].in_uop.bits.prs1 connect slots_10.io.in_uop.bits.pdst, issue_slots[10].in_uop.bits.pdst connect slots_10.io.in_uop.bits.rxq_idx, issue_slots[10].in_uop.bits.rxq_idx connect slots_10.io.in_uop.bits.stq_idx, issue_slots[10].in_uop.bits.stq_idx connect slots_10.io.in_uop.bits.ldq_idx, issue_slots[10].in_uop.bits.ldq_idx connect slots_10.io.in_uop.bits.rob_idx, issue_slots[10].in_uop.bits.rob_idx connect slots_10.io.in_uop.bits.fp_ctrl.vec, issue_slots[10].in_uop.bits.fp_ctrl.vec connect slots_10.io.in_uop.bits.fp_ctrl.wflags, issue_slots[10].in_uop.bits.fp_ctrl.wflags connect slots_10.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[10].in_uop.bits.fp_ctrl.sqrt connect slots_10.io.in_uop.bits.fp_ctrl.div, issue_slots[10].in_uop.bits.fp_ctrl.div connect slots_10.io.in_uop.bits.fp_ctrl.fma, issue_slots[10].in_uop.bits.fp_ctrl.fma connect slots_10.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].in_uop.bits.fp_ctrl.fastpipe connect slots_10.io.in_uop.bits.fp_ctrl.toint, issue_slots[10].in_uop.bits.fp_ctrl.toint connect slots_10.io.in_uop.bits.fp_ctrl.fromint, issue_slots[10].in_uop.bits.fp_ctrl.fromint connect slots_10.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut connect slots_10.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn connect slots_10.io.in_uop.bits.fp_ctrl.swap23, issue_slots[10].in_uop.bits.fp_ctrl.swap23 connect slots_10.io.in_uop.bits.fp_ctrl.swap12, issue_slots[10].in_uop.bits.fp_ctrl.swap12 connect slots_10.io.in_uop.bits.fp_ctrl.ren3, issue_slots[10].in_uop.bits.fp_ctrl.ren3 connect slots_10.io.in_uop.bits.fp_ctrl.ren2, issue_slots[10].in_uop.bits.fp_ctrl.ren2 connect slots_10.io.in_uop.bits.fp_ctrl.ren1, issue_slots[10].in_uop.bits.fp_ctrl.ren1 connect slots_10.io.in_uop.bits.fp_ctrl.wen, issue_slots[10].in_uop.bits.fp_ctrl.wen connect slots_10.io.in_uop.bits.fp_ctrl.ldst, issue_slots[10].in_uop.bits.fp_ctrl.ldst connect slots_10.io.in_uop.bits.op2_sel, issue_slots[10].in_uop.bits.op2_sel connect slots_10.io.in_uop.bits.op1_sel, issue_slots[10].in_uop.bits.op1_sel connect slots_10.io.in_uop.bits.imm_packed, issue_slots[10].in_uop.bits.imm_packed connect slots_10.io.in_uop.bits.pimm, issue_slots[10].in_uop.bits.pimm connect slots_10.io.in_uop.bits.imm_sel, issue_slots[10].in_uop.bits.imm_sel connect slots_10.io.in_uop.bits.imm_rename, issue_slots[10].in_uop.bits.imm_rename connect slots_10.io.in_uop.bits.taken, issue_slots[10].in_uop.bits.taken connect slots_10.io.in_uop.bits.pc_lob, issue_slots[10].in_uop.bits.pc_lob connect slots_10.io.in_uop.bits.edge_inst, issue_slots[10].in_uop.bits.edge_inst connect slots_10.io.in_uop.bits.ftq_idx, issue_slots[10].in_uop.bits.ftq_idx connect slots_10.io.in_uop.bits.is_mov, issue_slots[10].in_uop.bits.is_mov connect slots_10.io.in_uop.bits.is_rocc, issue_slots[10].in_uop.bits.is_rocc connect slots_10.io.in_uop.bits.is_sys_pc2epc, issue_slots[10].in_uop.bits.is_sys_pc2epc connect slots_10.io.in_uop.bits.is_eret, issue_slots[10].in_uop.bits.is_eret connect slots_10.io.in_uop.bits.is_amo, issue_slots[10].in_uop.bits.is_amo connect slots_10.io.in_uop.bits.is_sfence, issue_slots[10].in_uop.bits.is_sfence connect slots_10.io.in_uop.bits.is_fencei, issue_slots[10].in_uop.bits.is_fencei connect slots_10.io.in_uop.bits.is_fence, issue_slots[10].in_uop.bits.is_fence connect slots_10.io.in_uop.bits.is_sfb, issue_slots[10].in_uop.bits.is_sfb connect slots_10.io.in_uop.bits.br_type, issue_slots[10].in_uop.bits.br_type connect slots_10.io.in_uop.bits.br_tag, issue_slots[10].in_uop.bits.br_tag connect slots_10.io.in_uop.bits.br_mask, issue_slots[10].in_uop.bits.br_mask connect slots_10.io.in_uop.bits.dis_col_sel, issue_slots[10].in_uop.bits.dis_col_sel connect slots_10.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[10].in_uop.bits.iw_p3_bypass_hint connect slots_10.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[10].in_uop.bits.iw_p2_bypass_hint connect slots_10.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[10].in_uop.bits.iw_p1_bypass_hint connect slots_10.io.in_uop.bits.iw_p2_speculative_child, issue_slots[10].in_uop.bits.iw_p2_speculative_child connect slots_10.io.in_uop.bits.iw_p1_speculative_child, issue_slots[10].in_uop.bits.iw_p1_speculative_child connect slots_10.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[10].in_uop.bits.iw_issued_partial_dgen connect slots_10.io.in_uop.bits.iw_issued_partial_agen, issue_slots[10].in_uop.bits.iw_issued_partial_agen connect slots_10.io.in_uop.bits.iw_issued, issue_slots[10].in_uop.bits.iw_issued connect slots_10.io.in_uop.bits.fu_code[0], issue_slots[10].in_uop.bits.fu_code[0] connect slots_10.io.in_uop.bits.fu_code[1], issue_slots[10].in_uop.bits.fu_code[1] connect slots_10.io.in_uop.bits.fu_code[2], issue_slots[10].in_uop.bits.fu_code[2] connect slots_10.io.in_uop.bits.fu_code[3], issue_slots[10].in_uop.bits.fu_code[3] connect slots_10.io.in_uop.bits.fu_code[4], issue_slots[10].in_uop.bits.fu_code[4] connect slots_10.io.in_uop.bits.fu_code[5], issue_slots[10].in_uop.bits.fu_code[5] connect slots_10.io.in_uop.bits.fu_code[6], issue_slots[10].in_uop.bits.fu_code[6] connect slots_10.io.in_uop.bits.fu_code[7], issue_slots[10].in_uop.bits.fu_code[7] connect slots_10.io.in_uop.bits.fu_code[8], issue_slots[10].in_uop.bits.fu_code[8] connect slots_10.io.in_uop.bits.fu_code[9], issue_slots[10].in_uop.bits.fu_code[9] connect slots_10.io.in_uop.bits.iq_type[0], issue_slots[10].in_uop.bits.iq_type[0] connect slots_10.io.in_uop.bits.iq_type[1], issue_slots[10].in_uop.bits.iq_type[1] connect slots_10.io.in_uop.bits.iq_type[2], issue_slots[10].in_uop.bits.iq_type[2] connect slots_10.io.in_uop.bits.iq_type[3], issue_slots[10].in_uop.bits.iq_type[3] connect slots_10.io.in_uop.bits.debug_pc, issue_slots[10].in_uop.bits.debug_pc connect slots_10.io.in_uop.bits.is_rvc, issue_slots[10].in_uop.bits.is_rvc connect slots_10.io.in_uop.bits.debug_inst, issue_slots[10].in_uop.bits.debug_inst connect slots_10.io.in_uop.bits.inst, issue_slots[10].in_uop.bits.inst connect slots_10.io.in_uop.valid, issue_slots[10].in_uop.valid connect issue_slots[10].iss_uop.debug_tsrc, slots_10.io.iss_uop.debug_tsrc connect issue_slots[10].iss_uop.debug_fsrc, slots_10.io.iss_uop.debug_fsrc connect issue_slots[10].iss_uop.bp_xcpt_if, slots_10.io.iss_uop.bp_xcpt_if connect issue_slots[10].iss_uop.bp_debug_if, slots_10.io.iss_uop.bp_debug_if connect issue_slots[10].iss_uop.xcpt_ma_if, slots_10.io.iss_uop.xcpt_ma_if connect issue_slots[10].iss_uop.xcpt_ae_if, slots_10.io.iss_uop.xcpt_ae_if connect issue_slots[10].iss_uop.xcpt_pf_if, slots_10.io.iss_uop.xcpt_pf_if connect issue_slots[10].iss_uop.fp_typ, slots_10.io.iss_uop.fp_typ connect issue_slots[10].iss_uop.fp_rm, slots_10.io.iss_uop.fp_rm connect issue_slots[10].iss_uop.fp_val, slots_10.io.iss_uop.fp_val connect issue_slots[10].iss_uop.fcn_op, slots_10.io.iss_uop.fcn_op connect issue_slots[10].iss_uop.fcn_dw, slots_10.io.iss_uop.fcn_dw connect issue_slots[10].iss_uop.frs3_en, slots_10.io.iss_uop.frs3_en connect issue_slots[10].iss_uop.lrs2_rtype, slots_10.io.iss_uop.lrs2_rtype connect issue_slots[10].iss_uop.lrs1_rtype, slots_10.io.iss_uop.lrs1_rtype connect issue_slots[10].iss_uop.dst_rtype, slots_10.io.iss_uop.dst_rtype connect issue_slots[10].iss_uop.lrs3, slots_10.io.iss_uop.lrs3 connect issue_slots[10].iss_uop.lrs2, slots_10.io.iss_uop.lrs2 connect issue_slots[10].iss_uop.lrs1, slots_10.io.iss_uop.lrs1 connect issue_slots[10].iss_uop.ldst, slots_10.io.iss_uop.ldst connect issue_slots[10].iss_uop.ldst_is_rs1, slots_10.io.iss_uop.ldst_is_rs1 connect issue_slots[10].iss_uop.csr_cmd, slots_10.io.iss_uop.csr_cmd connect issue_slots[10].iss_uop.flush_on_commit, slots_10.io.iss_uop.flush_on_commit connect issue_slots[10].iss_uop.is_unique, slots_10.io.iss_uop.is_unique connect issue_slots[10].iss_uop.uses_stq, slots_10.io.iss_uop.uses_stq connect issue_slots[10].iss_uop.uses_ldq, slots_10.io.iss_uop.uses_ldq connect issue_slots[10].iss_uop.mem_signed, slots_10.io.iss_uop.mem_signed connect issue_slots[10].iss_uop.mem_size, slots_10.io.iss_uop.mem_size connect issue_slots[10].iss_uop.mem_cmd, slots_10.io.iss_uop.mem_cmd connect issue_slots[10].iss_uop.exc_cause, slots_10.io.iss_uop.exc_cause connect issue_slots[10].iss_uop.exception, slots_10.io.iss_uop.exception connect issue_slots[10].iss_uop.stale_pdst, slots_10.io.iss_uop.stale_pdst connect issue_slots[10].iss_uop.ppred_busy, slots_10.io.iss_uop.ppred_busy connect issue_slots[10].iss_uop.prs3_busy, slots_10.io.iss_uop.prs3_busy connect issue_slots[10].iss_uop.prs2_busy, slots_10.io.iss_uop.prs2_busy connect issue_slots[10].iss_uop.prs1_busy, slots_10.io.iss_uop.prs1_busy connect issue_slots[10].iss_uop.ppred, slots_10.io.iss_uop.ppred connect issue_slots[10].iss_uop.prs3, slots_10.io.iss_uop.prs3 connect issue_slots[10].iss_uop.prs2, slots_10.io.iss_uop.prs2 connect issue_slots[10].iss_uop.prs1, slots_10.io.iss_uop.prs1 connect issue_slots[10].iss_uop.pdst, slots_10.io.iss_uop.pdst connect issue_slots[10].iss_uop.rxq_idx, slots_10.io.iss_uop.rxq_idx connect issue_slots[10].iss_uop.stq_idx, slots_10.io.iss_uop.stq_idx connect issue_slots[10].iss_uop.ldq_idx, slots_10.io.iss_uop.ldq_idx connect issue_slots[10].iss_uop.rob_idx, slots_10.io.iss_uop.rob_idx connect issue_slots[10].iss_uop.fp_ctrl.vec, slots_10.io.iss_uop.fp_ctrl.vec connect issue_slots[10].iss_uop.fp_ctrl.wflags, slots_10.io.iss_uop.fp_ctrl.wflags connect issue_slots[10].iss_uop.fp_ctrl.sqrt, slots_10.io.iss_uop.fp_ctrl.sqrt connect issue_slots[10].iss_uop.fp_ctrl.div, slots_10.io.iss_uop.fp_ctrl.div connect issue_slots[10].iss_uop.fp_ctrl.fma, slots_10.io.iss_uop.fp_ctrl.fma connect issue_slots[10].iss_uop.fp_ctrl.fastpipe, slots_10.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[10].iss_uop.fp_ctrl.toint, slots_10.io.iss_uop.fp_ctrl.toint connect issue_slots[10].iss_uop.fp_ctrl.fromint, slots_10.io.iss_uop.fp_ctrl.fromint connect issue_slots[10].iss_uop.fp_ctrl.typeTagOut, slots_10.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[10].iss_uop.fp_ctrl.typeTagIn, slots_10.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[10].iss_uop.fp_ctrl.swap23, slots_10.io.iss_uop.fp_ctrl.swap23 connect issue_slots[10].iss_uop.fp_ctrl.swap12, slots_10.io.iss_uop.fp_ctrl.swap12 connect issue_slots[10].iss_uop.fp_ctrl.ren3, slots_10.io.iss_uop.fp_ctrl.ren3 connect issue_slots[10].iss_uop.fp_ctrl.ren2, slots_10.io.iss_uop.fp_ctrl.ren2 connect issue_slots[10].iss_uop.fp_ctrl.ren1, slots_10.io.iss_uop.fp_ctrl.ren1 connect issue_slots[10].iss_uop.fp_ctrl.wen, slots_10.io.iss_uop.fp_ctrl.wen connect issue_slots[10].iss_uop.fp_ctrl.ldst, slots_10.io.iss_uop.fp_ctrl.ldst connect issue_slots[10].iss_uop.op2_sel, slots_10.io.iss_uop.op2_sel connect issue_slots[10].iss_uop.op1_sel, slots_10.io.iss_uop.op1_sel connect issue_slots[10].iss_uop.imm_packed, slots_10.io.iss_uop.imm_packed connect issue_slots[10].iss_uop.pimm, slots_10.io.iss_uop.pimm connect issue_slots[10].iss_uop.imm_sel, slots_10.io.iss_uop.imm_sel connect issue_slots[10].iss_uop.imm_rename, slots_10.io.iss_uop.imm_rename connect issue_slots[10].iss_uop.taken, slots_10.io.iss_uop.taken connect issue_slots[10].iss_uop.pc_lob, slots_10.io.iss_uop.pc_lob connect issue_slots[10].iss_uop.edge_inst, slots_10.io.iss_uop.edge_inst connect issue_slots[10].iss_uop.ftq_idx, slots_10.io.iss_uop.ftq_idx connect issue_slots[10].iss_uop.is_mov, slots_10.io.iss_uop.is_mov connect issue_slots[10].iss_uop.is_rocc, slots_10.io.iss_uop.is_rocc connect issue_slots[10].iss_uop.is_sys_pc2epc, slots_10.io.iss_uop.is_sys_pc2epc connect issue_slots[10].iss_uop.is_eret, slots_10.io.iss_uop.is_eret connect issue_slots[10].iss_uop.is_amo, slots_10.io.iss_uop.is_amo connect issue_slots[10].iss_uop.is_sfence, slots_10.io.iss_uop.is_sfence connect issue_slots[10].iss_uop.is_fencei, slots_10.io.iss_uop.is_fencei connect issue_slots[10].iss_uop.is_fence, slots_10.io.iss_uop.is_fence connect issue_slots[10].iss_uop.is_sfb, slots_10.io.iss_uop.is_sfb connect issue_slots[10].iss_uop.br_type, slots_10.io.iss_uop.br_type connect issue_slots[10].iss_uop.br_tag, slots_10.io.iss_uop.br_tag connect issue_slots[10].iss_uop.br_mask, slots_10.io.iss_uop.br_mask connect issue_slots[10].iss_uop.dis_col_sel, slots_10.io.iss_uop.dis_col_sel connect issue_slots[10].iss_uop.iw_p3_bypass_hint, slots_10.io.iss_uop.iw_p3_bypass_hint connect issue_slots[10].iss_uop.iw_p2_bypass_hint, slots_10.io.iss_uop.iw_p2_bypass_hint connect issue_slots[10].iss_uop.iw_p1_bypass_hint, slots_10.io.iss_uop.iw_p1_bypass_hint connect issue_slots[10].iss_uop.iw_p2_speculative_child, slots_10.io.iss_uop.iw_p2_speculative_child connect issue_slots[10].iss_uop.iw_p1_speculative_child, slots_10.io.iss_uop.iw_p1_speculative_child connect issue_slots[10].iss_uop.iw_issued_partial_dgen, slots_10.io.iss_uop.iw_issued_partial_dgen connect issue_slots[10].iss_uop.iw_issued_partial_agen, slots_10.io.iss_uop.iw_issued_partial_agen connect issue_slots[10].iss_uop.iw_issued, slots_10.io.iss_uop.iw_issued connect issue_slots[10].iss_uop.fu_code[0], slots_10.io.iss_uop.fu_code[0] connect issue_slots[10].iss_uop.fu_code[1], slots_10.io.iss_uop.fu_code[1] connect issue_slots[10].iss_uop.fu_code[2], slots_10.io.iss_uop.fu_code[2] connect issue_slots[10].iss_uop.fu_code[3], slots_10.io.iss_uop.fu_code[3] connect issue_slots[10].iss_uop.fu_code[4], slots_10.io.iss_uop.fu_code[4] connect issue_slots[10].iss_uop.fu_code[5], slots_10.io.iss_uop.fu_code[5] connect issue_slots[10].iss_uop.fu_code[6], slots_10.io.iss_uop.fu_code[6] connect issue_slots[10].iss_uop.fu_code[7], slots_10.io.iss_uop.fu_code[7] connect issue_slots[10].iss_uop.fu_code[8], slots_10.io.iss_uop.fu_code[8] connect issue_slots[10].iss_uop.fu_code[9], slots_10.io.iss_uop.fu_code[9] connect issue_slots[10].iss_uop.iq_type[0], slots_10.io.iss_uop.iq_type[0] connect issue_slots[10].iss_uop.iq_type[1], slots_10.io.iss_uop.iq_type[1] connect issue_slots[10].iss_uop.iq_type[2], slots_10.io.iss_uop.iq_type[2] connect issue_slots[10].iss_uop.iq_type[3], slots_10.io.iss_uop.iq_type[3] connect issue_slots[10].iss_uop.debug_pc, slots_10.io.iss_uop.debug_pc connect issue_slots[10].iss_uop.is_rvc, slots_10.io.iss_uop.is_rvc connect issue_slots[10].iss_uop.debug_inst, slots_10.io.iss_uop.debug_inst connect issue_slots[10].iss_uop.inst, slots_10.io.iss_uop.inst connect slots_10.io.grant, issue_slots[10].grant connect issue_slots[10].request, slots_10.io.request connect issue_slots[10].will_be_valid, slots_10.io.will_be_valid connect issue_slots[10].valid, slots_10.io.valid connect slots_11.io.child_rebusys, issue_slots[11].child_rebusys connect slots_11.io.pred_wakeup_port.bits, issue_slots[11].pred_wakeup_port.bits connect slots_11.io.pred_wakeup_port.valid, issue_slots[11].pred_wakeup_port.valid connect slots_11.io.wakeup_ports[0].bits.rebusy, issue_slots[11].wakeup_ports[0].bits.rebusy connect slots_11.io.wakeup_ports[0].bits.speculative_mask, issue_slots[11].wakeup_ports[0].bits.speculative_mask connect slots_11.io.wakeup_ports[0].bits.bypassable, issue_slots[11].wakeup_ports[0].bits.bypassable connect slots_11.io.wakeup_ports[0].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[0].bits.uop.debug_tsrc connect slots_11.io.wakeup_ports[0].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[0].bits.uop.debug_fsrc connect slots_11.io.wakeup_ports[0].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[0].bits.uop.bp_xcpt_if connect slots_11.io.wakeup_ports[0].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[0].bits.uop.bp_debug_if connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ma_if connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ae_if connect slots_11.io.wakeup_ports[0].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[0].bits.uop.xcpt_pf_if connect slots_11.io.wakeup_ports[0].bits.uop.fp_typ, issue_slots[11].wakeup_ports[0].bits.uop.fp_typ connect slots_11.io.wakeup_ports[0].bits.uop.fp_rm, issue_slots[11].wakeup_ports[0].bits.uop.fp_rm connect slots_11.io.wakeup_ports[0].bits.uop.fp_val, issue_slots[11].wakeup_ports[0].bits.uop.fp_val connect slots_11.io.wakeup_ports[0].bits.uop.fcn_op, issue_slots[11].wakeup_ports[0].bits.uop.fcn_op connect slots_11.io.wakeup_ports[0].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[0].bits.uop.fcn_dw connect slots_11.io.wakeup_ports[0].bits.uop.frs3_en, issue_slots[11].wakeup_ports[0].bits.uop.frs3_en connect slots_11.io.wakeup_ports[0].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[0].bits.uop.lrs2_rtype connect slots_11.io.wakeup_ports[0].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[0].bits.uop.lrs1_rtype connect slots_11.io.wakeup_ports[0].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[0].bits.uop.dst_rtype connect slots_11.io.wakeup_ports[0].bits.uop.lrs3, issue_slots[11].wakeup_ports[0].bits.uop.lrs3 connect slots_11.io.wakeup_ports[0].bits.uop.lrs2, issue_slots[11].wakeup_ports[0].bits.uop.lrs2 connect slots_11.io.wakeup_ports[0].bits.uop.lrs1, issue_slots[11].wakeup_ports[0].bits.uop.lrs1 connect slots_11.io.wakeup_ports[0].bits.uop.ldst, issue_slots[11].wakeup_ports[0].bits.uop.ldst connect slots_11.io.wakeup_ports[0].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[0].bits.uop.ldst_is_rs1 connect slots_11.io.wakeup_ports[0].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[0].bits.uop.csr_cmd connect slots_11.io.wakeup_ports[0].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[0].bits.uop.flush_on_commit connect slots_11.io.wakeup_ports[0].bits.uop.is_unique, issue_slots[11].wakeup_ports[0].bits.uop.is_unique connect slots_11.io.wakeup_ports[0].bits.uop.uses_stq, issue_slots[11].wakeup_ports[0].bits.uop.uses_stq connect slots_11.io.wakeup_ports[0].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[0].bits.uop.uses_ldq connect slots_11.io.wakeup_ports[0].bits.uop.mem_signed, issue_slots[11].wakeup_ports[0].bits.uop.mem_signed connect slots_11.io.wakeup_ports[0].bits.uop.mem_size, issue_slots[11].wakeup_ports[0].bits.uop.mem_size connect slots_11.io.wakeup_ports[0].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[0].bits.uop.mem_cmd connect slots_11.io.wakeup_ports[0].bits.uop.exc_cause, issue_slots[11].wakeup_ports[0].bits.uop.exc_cause connect slots_11.io.wakeup_ports[0].bits.uop.exception, issue_slots[11].wakeup_ports[0].bits.uop.exception connect slots_11.io.wakeup_ports[0].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[0].bits.uop.stale_pdst connect slots_11.io.wakeup_ports[0].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[0].bits.uop.ppred_busy connect slots_11.io.wakeup_ports[0].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs3_busy connect slots_11.io.wakeup_ports[0].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs2_busy connect slots_11.io.wakeup_ports[0].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[0].bits.uop.prs1_busy connect slots_11.io.wakeup_ports[0].bits.uop.ppred, issue_slots[11].wakeup_ports[0].bits.uop.ppred connect slots_11.io.wakeup_ports[0].bits.uop.prs3, issue_slots[11].wakeup_ports[0].bits.uop.prs3 connect slots_11.io.wakeup_ports[0].bits.uop.prs2, issue_slots[11].wakeup_ports[0].bits.uop.prs2 connect slots_11.io.wakeup_ports[0].bits.uop.prs1, issue_slots[11].wakeup_ports[0].bits.uop.prs1 connect slots_11.io.wakeup_ports[0].bits.uop.pdst, issue_slots[11].wakeup_ports[0].bits.uop.pdst connect slots_11.io.wakeup_ports[0].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[0].bits.uop.rxq_idx connect slots_11.io.wakeup_ports[0].bits.uop.stq_idx, issue_slots[11].wakeup_ports[0].bits.uop.stq_idx connect slots_11.io.wakeup_ports[0].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[0].bits.uop.ldq_idx connect slots_11.io.wakeup_ports[0].bits.uop.rob_idx, issue_slots[11].wakeup_ports[0].bits.uop.rob_idx connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.vec connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wflags connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.div connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fma connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.toint connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fromint connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wen connect slots_11.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ldst connect slots_11.io.wakeup_ports[0].bits.uop.op2_sel, issue_slots[11].wakeup_ports[0].bits.uop.op2_sel connect slots_11.io.wakeup_ports[0].bits.uop.op1_sel, issue_slots[11].wakeup_ports[0].bits.uop.op1_sel connect slots_11.io.wakeup_ports[0].bits.uop.imm_packed, issue_slots[11].wakeup_ports[0].bits.uop.imm_packed connect slots_11.io.wakeup_ports[0].bits.uop.pimm, issue_slots[11].wakeup_ports[0].bits.uop.pimm connect slots_11.io.wakeup_ports[0].bits.uop.imm_sel, issue_slots[11].wakeup_ports[0].bits.uop.imm_sel connect slots_11.io.wakeup_ports[0].bits.uop.imm_rename, issue_slots[11].wakeup_ports[0].bits.uop.imm_rename connect slots_11.io.wakeup_ports[0].bits.uop.taken, issue_slots[11].wakeup_ports[0].bits.uop.taken connect slots_11.io.wakeup_ports[0].bits.uop.pc_lob, issue_slots[11].wakeup_ports[0].bits.uop.pc_lob connect slots_11.io.wakeup_ports[0].bits.uop.edge_inst, issue_slots[11].wakeup_ports[0].bits.uop.edge_inst connect slots_11.io.wakeup_ports[0].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[0].bits.uop.ftq_idx connect slots_11.io.wakeup_ports[0].bits.uop.is_mov, issue_slots[11].wakeup_ports[0].bits.uop.is_mov connect slots_11.io.wakeup_ports[0].bits.uop.is_rocc, issue_slots[11].wakeup_ports[0].bits.uop.is_rocc connect slots_11.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[0].bits.uop.is_sys_pc2epc connect slots_11.io.wakeup_ports[0].bits.uop.is_eret, issue_slots[11].wakeup_ports[0].bits.uop.is_eret connect slots_11.io.wakeup_ports[0].bits.uop.is_amo, issue_slots[11].wakeup_ports[0].bits.uop.is_amo connect slots_11.io.wakeup_ports[0].bits.uop.is_sfence, issue_slots[11].wakeup_ports[0].bits.uop.is_sfence connect slots_11.io.wakeup_ports[0].bits.uop.is_fencei, issue_slots[11].wakeup_ports[0].bits.uop.is_fencei connect slots_11.io.wakeup_ports[0].bits.uop.is_fence, issue_slots[11].wakeup_ports[0].bits.uop.is_fence connect slots_11.io.wakeup_ports[0].bits.uop.is_sfb, issue_slots[11].wakeup_ports[0].bits.uop.is_sfb connect slots_11.io.wakeup_ports[0].bits.uop.br_type, issue_slots[11].wakeup_ports[0].bits.uop.br_type connect slots_11.io.wakeup_ports[0].bits.uop.br_tag, issue_slots[11].wakeup_ports[0].bits.uop.br_tag connect slots_11.io.wakeup_ports[0].bits.uop.br_mask, issue_slots[11].wakeup_ports[0].bits.uop.br_mask connect slots_11.io.wakeup_ports[0].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[0].bits.uop.dis_col_sel connect slots_11.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect slots_11.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect slots_11.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect slots_11.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_speculative_child connect slots_11.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_speculative_child connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_agen connect slots_11.io.wakeup_ports[0].bits.uop.iw_issued, issue_slots[11].wakeup_ports[0].bits.uop.iw_issued connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[0] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[1] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[2] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[3] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[4] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[5] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[6] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[7] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[8] connect slots_11.io.wakeup_ports[0].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[0].bits.uop.fu_code[9] connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[0] connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[1] connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[2] connect slots_11.io.wakeup_ports[0].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[0].bits.uop.iq_type[3] connect slots_11.io.wakeup_ports[0].bits.uop.debug_pc, issue_slots[11].wakeup_ports[0].bits.uop.debug_pc connect slots_11.io.wakeup_ports[0].bits.uop.is_rvc, issue_slots[11].wakeup_ports[0].bits.uop.is_rvc connect slots_11.io.wakeup_ports[0].bits.uop.debug_inst, issue_slots[11].wakeup_ports[0].bits.uop.debug_inst connect slots_11.io.wakeup_ports[0].bits.uop.inst, issue_slots[11].wakeup_ports[0].bits.uop.inst connect slots_11.io.wakeup_ports[0].valid, issue_slots[11].wakeup_ports[0].valid connect slots_11.io.wakeup_ports[1].bits.rebusy, issue_slots[11].wakeup_ports[1].bits.rebusy connect slots_11.io.wakeup_ports[1].bits.speculative_mask, issue_slots[11].wakeup_ports[1].bits.speculative_mask connect slots_11.io.wakeup_ports[1].bits.bypassable, issue_slots[11].wakeup_ports[1].bits.bypassable connect slots_11.io.wakeup_ports[1].bits.uop.debug_tsrc, issue_slots[11].wakeup_ports[1].bits.uop.debug_tsrc connect slots_11.io.wakeup_ports[1].bits.uop.debug_fsrc, issue_slots[11].wakeup_ports[1].bits.uop.debug_fsrc connect slots_11.io.wakeup_ports[1].bits.uop.bp_xcpt_if, issue_slots[11].wakeup_ports[1].bits.uop.bp_xcpt_if connect slots_11.io.wakeup_ports[1].bits.uop.bp_debug_if, issue_slots[11].wakeup_ports[1].bits.uop.bp_debug_if connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_ma_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ma_if connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_ae_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ae_if connect slots_11.io.wakeup_ports[1].bits.uop.xcpt_pf_if, issue_slots[11].wakeup_ports[1].bits.uop.xcpt_pf_if connect slots_11.io.wakeup_ports[1].bits.uop.fp_typ, issue_slots[11].wakeup_ports[1].bits.uop.fp_typ connect slots_11.io.wakeup_ports[1].bits.uop.fp_rm, issue_slots[11].wakeup_ports[1].bits.uop.fp_rm connect slots_11.io.wakeup_ports[1].bits.uop.fp_val, issue_slots[11].wakeup_ports[1].bits.uop.fp_val connect slots_11.io.wakeup_ports[1].bits.uop.fcn_op, issue_slots[11].wakeup_ports[1].bits.uop.fcn_op connect slots_11.io.wakeup_ports[1].bits.uop.fcn_dw, issue_slots[11].wakeup_ports[1].bits.uop.fcn_dw connect slots_11.io.wakeup_ports[1].bits.uop.frs3_en, issue_slots[11].wakeup_ports[1].bits.uop.frs3_en connect slots_11.io.wakeup_ports[1].bits.uop.lrs2_rtype, issue_slots[11].wakeup_ports[1].bits.uop.lrs2_rtype connect slots_11.io.wakeup_ports[1].bits.uop.lrs1_rtype, issue_slots[11].wakeup_ports[1].bits.uop.lrs1_rtype connect slots_11.io.wakeup_ports[1].bits.uop.dst_rtype, issue_slots[11].wakeup_ports[1].bits.uop.dst_rtype connect slots_11.io.wakeup_ports[1].bits.uop.lrs3, issue_slots[11].wakeup_ports[1].bits.uop.lrs3 connect slots_11.io.wakeup_ports[1].bits.uop.lrs2, issue_slots[11].wakeup_ports[1].bits.uop.lrs2 connect slots_11.io.wakeup_ports[1].bits.uop.lrs1, issue_slots[11].wakeup_ports[1].bits.uop.lrs1 connect slots_11.io.wakeup_ports[1].bits.uop.ldst, issue_slots[11].wakeup_ports[1].bits.uop.ldst connect slots_11.io.wakeup_ports[1].bits.uop.ldst_is_rs1, issue_slots[11].wakeup_ports[1].bits.uop.ldst_is_rs1 connect slots_11.io.wakeup_ports[1].bits.uop.csr_cmd, issue_slots[11].wakeup_ports[1].bits.uop.csr_cmd connect slots_11.io.wakeup_ports[1].bits.uop.flush_on_commit, issue_slots[11].wakeup_ports[1].bits.uop.flush_on_commit connect slots_11.io.wakeup_ports[1].bits.uop.is_unique, issue_slots[11].wakeup_ports[1].bits.uop.is_unique connect slots_11.io.wakeup_ports[1].bits.uop.uses_stq, issue_slots[11].wakeup_ports[1].bits.uop.uses_stq connect slots_11.io.wakeup_ports[1].bits.uop.uses_ldq, issue_slots[11].wakeup_ports[1].bits.uop.uses_ldq connect slots_11.io.wakeup_ports[1].bits.uop.mem_signed, issue_slots[11].wakeup_ports[1].bits.uop.mem_signed connect slots_11.io.wakeup_ports[1].bits.uop.mem_size, issue_slots[11].wakeup_ports[1].bits.uop.mem_size connect slots_11.io.wakeup_ports[1].bits.uop.mem_cmd, issue_slots[11].wakeup_ports[1].bits.uop.mem_cmd connect slots_11.io.wakeup_ports[1].bits.uop.exc_cause, issue_slots[11].wakeup_ports[1].bits.uop.exc_cause connect slots_11.io.wakeup_ports[1].bits.uop.exception, issue_slots[11].wakeup_ports[1].bits.uop.exception connect slots_11.io.wakeup_ports[1].bits.uop.stale_pdst, issue_slots[11].wakeup_ports[1].bits.uop.stale_pdst connect slots_11.io.wakeup_ports[1].bits.uop.ppred_busy, issue_slots[11].wakeup_ports[1].bits.uop.ppred_busy connect slots_11.io.wakeup_ports[1].bits.uop.prs3_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs3_busy connect slots_11.io.wakeup_ports[1].bits.uop.prs2_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs2_busy connect slots_11.io.wakeup_ports[1].bits.uop.prs1_busy, issue_slots[11].wakeup_ports[1].bits.uop.prs1_busy connect slots_11.io.wakeup_ports[1].bits.uop.ppred, issue_slots[11].wakeup_ports[1].bits.uop.ppred connect slots_11.io.wakeup_ports[1].bits.uop.prs3, issue_slots[11].wakeup_ports[1].bits.uop.prs3 connect slots_11.io.wakeup_ports[1].bits.uop.prs2, issue_slots[11].wakeup_ports[1].bits.uop.prs2 connect slots_11.io.wakeup_ports[1].bits.uop.prs1, issue_slots[11].wakeup_ports[1].bits.uop.prs1 connect slots_11.io.wakeup_ports[1].bits.uop.pdst, issue_slots[11].wakeup_ports[1].bits.uop.pdst connect slots_11.io.wakeup_ports[1].bits.uop.rxq_idx, issue_slots[11].wakeup_ports[1].bits.uop.rxq_idx connect slots_11.io.wakeup_ports[1].bits.uop.stq_idx, issue_slots[11].wakeup_ports[1].bits.uop.stq_idx connect slots_11.io.wakeup_ports[1].bits.uop.ldq_idx, issue_slots[11].wakeup_ports[1].bits.uop.ldq_idx connect slots_11.io.wakeup_ports[1].bits.uop.rob_idx, issue_slots[11].wakeup_ports[1].bits.uop.rob_idx connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.vec connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wflags connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.div, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.div connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fma connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.toint connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fromint connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wen connect slots_11.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ldst connect slots_11.io.wakeup_ports[1].bits.uop.op2_sel, issue_slots[11].wakeup_ports[1].bits.uop.op2_sel connect slots_11.io.wakeup_ports[1].bits.uop.op1_sel, issue_slots[11].wakeup_ports[1].bits.uop.op1_sel connect slots_11.io.wakeup_ports[1].bits.uop.imm_packed, issue_slots[11].wakeup_ports[1].bits.uop.imm_packed connect slots_11.io.wakeup_ports[1].bits.uop.pimm, issue_slots[11].wakeup_ports[1].bits.uop.pimm connect slots_11.io.wakeup_ports[1].bits.uop.imm_sel, issue_slots[11].wakeup_ports[1].bits.uop.imm_sel connect slots_11.io.wakeup_ports[1].bits.uop.imm_rename, issue_slots[11].wakeup_ports[1].bits.uop.imm_rename connect slots_11.io.wakeup_ports[1].bits.uop.taken, issue_slots[11].wakeup_ports[1].bits.uop.taken connect slots_11.io.wakeup_ports[1].bits.uop.pc_lob, issue_slots[11].wakeup_ports[1].bits.uop.pc_lob connect slots_11.io.wakeup_ports[1].bits.uop.edge_inst, issue_slots[11].wakeup_ports[1].bits.uop.edge_inst connect slots_11.io.wakeup_ports[1].bits.uop.ftq_idx, issue_slots[11].wakeup_ports[1].bits.uop.ftq_idx connect slots_11.io.wakeup_ports[1].bits.uop.is_mov, issue_slots[11].wakeup_ports[1].bits.uop.is_mov connect slots_11.io.wakeup_ports[1].bits.uop.is_rocc, issue_slots[11].wakeup_ports[1].bits.uop.is_rocc connect slots_11.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, issue_slots[11].wakeup_ports[1].bits.uop.is_sys_pc2epc connect slots_11.io.wakeup_ports[1].bits.uop.is_eret, issue_slots[11].wakeup_ports[1].bits.uop.is_eret connect slots_11.io.wakeup_ports[1].bits.uop.is_amo, issue_slots[11].wakeup_ports[1].bits.uop.is_amo connect slots_11.io.wakeup_ports[1].bits.uop.is_sfence, issue_slots[11].wakeup_ports[1].bits.uop.is_sfence connect slots_11.io.wakeup_ports[1].bits.uop.is_fencei, issue_slots[11].wakeup_ports[1].bits.uop.is_fencei connect slots_11.io.wakeup_ports[1].bits.uop.is_fence, issue_slots[11].wakeup_ports[1].bits.uop.is_fence connect slots_11.io.wakeup_ports[1].bits.uop.is_sfb, issue_slots[11].wakeup_ports[1].bits.uop.is_sfb connect slots_11.io.wakeup_ports[1].bits.uop.br_type, issue_slots[11].wakeup_ports[1].bits.uop.br_type connect slots_11.io.wakeup_ports[1].bits.uop.br_tag, issue_slots[11].wakeup_ports[1].bits.uop.br_tag connect slots_11.io.wakeup_ports[1].bits.uop.br_mask, issue_slots[11].wakeup_ports[1].bits.uop.br_mask connect slots_11.io.wakeup_ports[1].bits.uop.dis_col_sel, issue_slots[11].wakeup_ports[1].bits.uop.dis_col_sel connect slots_11.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect slots_11.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect slots_11.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect slots_11.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_speculative_child connect slots_11.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_speculative_child connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_agen connect slots_11.io.wakeup_ports[1].bits.uop.iw_issued, issue_slots[11].wakeup_ports[1].bits.uop.iw_issued connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[0], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[0] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[1], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[1] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[2], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[2] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[3], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[3] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[4], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[4] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[5], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[5] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[6], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[6] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[7], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[7] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[8], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[8] connect slots_11.io.wakeup_ports[1].bits.uop.fu_code[9], issue_slots[11].wakeup_ports[1].bits.uop.fu_code[9] connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[0], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[0] connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[1], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[1] connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[2], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[2] connect slots_11.io.wakeup_ports[1].bits.uop.iq_type[3], issue_slots[11].wakeup_ports[1].bits.uop.iq_type[3] connect slots_11.io.wakeup_ports[1].bits.uop.debug_pc, issue_slots[11].wakeup_ports[1].bits.uop.debug_pc connect slots_11.io.wakeup_ports[1].bits.uop.is_rvc, issue_slots[11].wakeup_ports[1].bits.uop.is_rvc connect slots_11.io.wakeup_ports[1].bits.uop.debug_inst, issue_slots[11].wakeup_ports[1].bits.uop.debug_inst connect slots_11.io.wakeup_ports[1].bits.uop.inst, issue_slots[11].wakeup_ports[1].bits.uop.inst connect slots_11.io.wakeup_ports[1].valid, issue_slots[11].wakeup_ports[1].valid connect slots_11.io.squash_grant, issue_slots[11].squash_grant connect slots_11.io.clear, issue_slots[11].clear connect slots_11.io.kill, issue_slots[11].kill connect slots_11.io.brupdate.b2.target_offset, issue_slots[11].brupdate.b2.target_offset connect slots_11.io.brupdate.b2.jalr_target, issue_slots[11].brupdate.b2.jalr_target connect slots_11.io.brupdate.b2.pc_sel, issue_slots[11].brupdate.b2.pc_sel connect slots_11.io.brupdate.b2.cfi_type, issue_slots[11].brupdate.b2.cfi_type connect slots_11.io.brupdate.b2.taken, issue_slots[11].brupdate.b2.taken connect slots_11.io.brupdate.b2.mispredict, issue_slots[11].brupdate.b2.mispredict connect slots_11.io.brupdate.b2.uop.debug_tsrc, issue_slots[11].brupdate.b2.uop.debug_tsrc connect slots_11.io.brupdate.b2.uop.debug_fsrc, issue_slots[11].brupdate.b2.uop.debug_fsrc connect slots_11.io.brupdate.b2.uop.bp_xcpt_if, issue_slots[11].brupdate.b2.uop.bp_xcpt_if connect slots_11.io.brupdate.b2.uop.bp_debug_if, issue_slots[11].brupdate.b2.uop.bp_debug_if connect slots_11.io.brupdate.b2.uop.xcpt_ma_if, issue_slots[11].brupdate.b2.uop.xcpt_ma_if connect slots_11.io.brupdate.b2.uop.xcpt_ae_if, issue_slots[11].brupdate.b2.uop.xcpt_ae_if connect slots_11.io.brupdate.b2.uop.xcpt_pf_if, issue_slots[11].brupdate.b2.uop.xcpt_pf_if connect slots_11.io.brupdate.b2.uop.fp_typ, issue_slots[11].brupdate.b2.uop.fp_typ connect slots_11.io.brupdate.b2.uop.fp_rm, issue_slots[11].brupdate.b2.uop.fp_rm connect slots_11.io.brupdate.b2.uop.fp_val, issue_slots[11].brupdate.b2.uop.fp_val connect slots_11.io.brupdate.b2.uop.fcn_op, issue_slots[11].brupdate.b2.uop.fcn_op connect slots_11.io.brupdate.b2.uop.fcn_dw, issue_slots[11].brupdate.b2.uop.fcn_dw connect slots_11.io.brupdate.b2.uop.frs3_en, issue_slots[11].brupdate.b2.uop.frs3_en connect slots_11.io.brupdate.b2.uop.lrs2_rtype, issue_slots[11].brupdate.b2.uop.lrs2_rtype connect slots_11.io.brupdate.b2.uop.lrs1_rtype, issue_slots[11].brupdate.b2.uop.lrs1_rtype connect slots_11.io.brupdate.b2.uop.dst_rtype, issue_slots[11].brupdate.b2.uop.dst_rtype connect slots_11.io.brupdate.b2.uop.lrs3, issue_slots[11].brupdate.b2.uop.lrs3 connect slots_11.io.brupdate.b2.uop.lrs2, issue_slots[11].brupdate.b2.uop.lrs2 connect slots_11.io.brupdate.b2.uop.lrs1, issue_slots[11].brupdate.b2.uop.lrs1 connect slots_11.io.brupdate.b2.uop.ldst, issue_slots[11].brupdate.b2.uop.ldst connect slots_11.io.brupdate.b2.uop.ldst_is_rs1, issue_slots[11].brupdate.b2.uop.ldst_is_rs1 connect slots_11.io.brupdate.b2.uop.csr_cmd, issue_slots[11].brupdate.b2.uop.csr_cmd connect slots_11.io.brupdate.b2.uop.flush_on_commit, issue_slots[11].brupdate.b2.uop.flush_on_commit connect slots_11.io.brupdate.b2.uop.is_unique, issue_slots[11].brupdate.b2.uop.is_unique connect slots_11.io.brupdate.b2.uop.uses_stq, issue_slots[11].brupdate.b2.uop.uses_stq connect slots_11.io.brupdate.b2.uop.uses_ldq, issue_slots[11].brupdate.b2.uop.uses_ldq connect slots_11.io.brupdate.b2.uop.mem_signed, issue_slots[11].brupdate.b2.uop.mem_signed connect slots_11.io.brupdate.b2.uop.mem_size, issue_slots[11].brupdate.b2.uop.mem_size connect slots_11.io.brupdate.b2.uop.mem_cmd, issue_slots[11].brupdate.b2.uop.mem_cmd connect slots_11.io.brupdate.b2.uop.exc_cause, issue_slots[11].brupdate.b2.uop.exc_cause connect slots_11.io.brupdate.b2.uop.exception, issue_slots[11].brupdate.b2.uop.exception connect slots_11.io.brupdate.b2.uop.stale_pdst, issue_slots[11].brupdate.b2.uop.stale_pdst connect slots_11.io.brupdate.b2.uop.ppred_busy, issue_slots[11].brupdate.b2.uop.ppred_busy connect slots_11.io.brupdate.b2.uop.prs3_busy, issue_slots[11].brupdate.b2.uop.prs3_busy connect slots_11.io.brupdate.b2.uop.prs2_busy, issue_slots[11].brupdate.b2.uop.prs2_busy connect slots_11.io.brupdate.b2.uop.prs1_busy, issue_slots[11].brupdate.b2.uop.prs1_busy connect slots_11.io.brupdate.b2.uop.ppred, issue_slots[11].brupdate.b2.uop.ppred connect slots_11.io.brupdate.b2.uop.prs3, issue_slots[11].brupdate.b2.uop.prs3 connect slots_11.io.brupdate.b2.uop.prs2, issue_slots[11].brupdate.b2.uop.prs2 connect slots_11.io.brupdate.b2.uop.prs1, issue_slots[11].brupdate.b2.uop.prs1 connect slots_11.io.brupdate.b2.uop.pdst, issue_slots[11].brupdate.b2.uop.pdst connect slots_11.io.brupdate.b2.uop.rxq_idx, issue_slots[11].brupdate.b2.uop.rxq_idx connect slots_11.io.brupdate.b2.uop.stq_idx, issue_slots[11].brupdate.b2.uop.stq_idx connect slots_11.io.brupdate.b2.uop.ldq_idx, issue_slots[11].brupdate.b2.uop.ldq_idx connect slots_11.io.brupdate.b2.uop.rob_idx, issue_slots[11].brupdate.b2.uop.rob_idx connect slots_11.io.brupdate.b2.uop.fp_ctrl.vec, issue_slots[11].brupdate.b2.uop.fp_ctrl.vec connect slots_11.io.brupdate.b2.uop.fp_ctrl.wflags, issue_slots[11].brupdate.b2.uop.fp_ctrl.wflags connect slots_11.io.brupdate.b2.uop.fp_ctrl.sqrt, issue_slots[11].brupdate.b2.uop.fp_ctrl.sqrt connect slots_11.io.brupdate.b2.uop.fp_ctrl.div, issue_slots[11].brupdate.b2.uop.fp_ctrl.div connect slots_11.io.brupdate.b2.uop.fp_ctrl.fma, issue_slots[11].brupdate.b2.uop.fp_ctrl.fma connect slots_11.io.brupdate.b2.uop.fp_ctrl.fastpipe, issue_slots[11].brupdate.b2.uop.fp_ctrl.fastpipe connect slots_11.io.brupdate.b2.uop.fp_ctrl.toint, issue_slots[11].brupdate.b2.uop.fp_ctrl.toint connect slots_11.io.brupdate.b2.uop.fp_ctrl.fromint, issue_slots[11].brupdate.b2.uop.fp_ctrl.fromint connect slots_11.io.brupdate.b2.uop.fp_ctrl.typeTagOut, issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagOut connect slots_11.io.brupdate.b2.uop.fp_ctrl.typeTagIn, issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagIn connect slots_11.io.brupdate.b2.uop.fp_ctrl.swap23, issue_slots[11].brupdate.b2.uop.fp_ctrl.swap23 connect slots_11.io.brupdate.b2.uop.fp_ctrl.swap12, issue_slots[11].brupdate.b2.uop.fp_ctrl.swap12 connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren3, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren3 connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren2, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren2 connect slots_11.io.brupdate.b2.uop.fp_ctrl.ren1, issue_slots[11].brupdate.b2.uop.fp_ctrl.ren1 connect slots_11.io.brupdate.b2.uop.fp_ctrl.wen, issue_slots[11].brupdate.b2.uop.fp_ctrl.wen connect slots_11.io.brupdate.b2.uop.fp_ctrl.ldst, issue_slots[11].brupdate.b2.uop.fp_ctrl.ldst connect slots_11.io.brupdate.b2.uop.op2_sel, issue_slots[11].brupdate.b2.uop.op2_sel connect slots_11.io.brupdate.b2.uop.op1_sel, issue_slots[11].brupdate.b2.uop.op1_sel connect slots_11.io.brupdate.b2.uop.imm_packed, issue_slots[11].brupdate.b2.uop.imm_packed connect slots_11.io.brupdate.b2.uop.pimm, issue_slots[11].brupdate.b2.uop.pimm connect slots_11.io.brupdate.b2.uop.imm_sel, issue_slots[11].brupdate.b2.uop.imm_sel connect slots_11.io.brupdate.b2.uop.imm_rename, issue_slots[11].brupdate.b2.uop.imm_rename connect slots_11.io.brupdate.b2.uop.taken, issue_slots[11].brupdate.b2.uop.taken connect slots_11.io.brupdate.b2.uop.pc_lob, issue_slots[11].brupdate.b2.uop.pc_lob connect slots_11.io.brupdate.b2.uop.edge_inst, issue_slots[11].brupdate.b2.uop.edge_inst connect slots_11.io.brupdate.b2.uop.ftq_idx, issue_slots[11].brupdate.b2.uop.ftq_idx connect slots_11.io.brupdate.b2.uop.is_mov, issue_slots[11].brupdate.b2.uop.is_mov connect slots_11.io.brupdate.b2.uop.is_rocc, issue_slots[11].brupdate.b2.uop.is_rocc connect slots_11.io.brupdate.b2.uop.is_sys_pc2epc, issue_slots[11].brupdate.b2.uop.is_sys_pc2epc connect slots_11.io.brupdate.b2.uop.is_eret, issue_slots[11].brupdate.b2.uop.is_eret connect slots_11.io.brupdate.b2.uop.is_amo, issue_slots[11].brupdate.b2.uop.is_amo connect slots_11.io.brupdate.b2.uop.is_sfence, issue_slots[11].brupdate.b2.uop.is_sfence connect slots_11.io.brupdate.b2.uop.is_fencei, issue_slots[11].brupdate.b2.uop.is_fencei connect slots_11.io.brupdate.b2.uop.is_fence, issue_slots[11].brupdate.b2.uop.is_fence connect slots_11.io.brupdate.b2.uop.is_sfb, issue_slots[11].brupdate.b2.uop.is_sfb connect slots_11.io.brupdate.b2.uop.br_type, issue_slots[11].brupdate.b2.uop.br_type connect slots_11.io.brupdate.b2.uop.br_tag, issue_slots[11].brupdate.b2.uop.br_tag connect slots_11.io.brupdate.b2.uop.br_mask, issue_slots[11].brupdate.b2.uop.br_mask connect slots_11.io.brupdate.b2.uop.dis_col_sel, issue_slots[11].brupdate.b2.uop.dis_col_sel connect slots_11.io.brupdate.b2.uop.iw_p3_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p3_bypass_hint connect slots_11.io.brupdate.b2.uop.iw_p2_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p2_bypass_hint connect slots_11.io.brupdate.b2.uop.iw_p1_bypass_hint, issue_slots[11].brupdate.b2.uop.iw_p1_bypass_hint connect slots_11.io.brupdate.b2.uop.iw_p2_speculative_child, issue_slots[11].brupdate.b2.uop.iw_p2_speculative_child connect slots_11.io.brupdate.b2.uop.iw_p1_speculative_child, issue_slots[11].brupdate.b2.uop.iw_p1_speculative_child connect slots_11.io.brupdate.b2.uop.iw_issued_partial_dgen, issue_slots[11].brupdate.b2.uop.iw_issued_partial_dgen connect slots_11.io.brupdate.b2.uop.iw_issued_partial_agen, issue_slots[11].brupdate.b2.uop.iw_issued_partial_agen connect slots_11.io.brupdate.b2.uop.iw_issued, issue_slots[11].brupdate.b2.uop.iw_issued connect slots_11.io.brupdate.b2.uop.fu_code[0], issue_slots[11].brupdate.b2.uop.fu_code[0] connect slots_11.io.brupdate.b2.uop.fu_code[1], issue_slots[11].brupdate.b2.uop.fu_code[1] connect slots_11.io.brupdate.b2.uop.fu_code[2], issue_slots[11].brupdate.b2.uop.fu_code[2] connect slots_11.io.brupdate.b2.uop.fu_code[3], issue_slots[11].brupdate.b2.uop.fu_code[3] connect slots_11.io.brupdate.b2.uop.fu_code[4], issue_slots[11].brupdate.b2.uop.fu_code[4] connect slots_11.io.brupdate.b2.uop.fu_code[5], issue_slots[11].brupdate.b2.uop.fu_code[5] connect slots_11.io.brupdate.b2.uop.fu_code[6], issue_slots[11].brupdate.b2.uop.fu_code[6] connect slots_11.io.brupdate.b2.uop.fu_code[7], issue_slots[11].brupdate.b2.uop.fu_code[7] connect slots_11.io.brupdate.b2.uop.fu_code[8], issue_slots[11].brupdate.b2.uop.fu_code[8] connect slots_11.io.brupdate.b2.uop.fu_code[9], issue_slots[11].brupdate.b2.uop.fu_code[9] connect slots_11.io.brupdate.b2.uop.iq_type[0], issue_slots[11].brupdate.b2.uop.iq_type[0] connect slots_11.io.brupdate.b2.uop.iq_type[1], issue_slots[11].brupdate.b2.uop.iq_type[1] connect slots_11.io.brupdate.b2.uop.iq_type[2], issue_slots[11].brupdate.b2.uop.iq_type[2] connect slots_11.io.brupdate.b2.uop.iq_type[3], issue_slots[11].brupdate.b2.uop.iq_type[3] connect slots_11.io.brupdate.b2.uop.debug_pc, issue_slots[11].brupdate.b2.uop.debug_pc connect slots_11.io.brupdate.b2.uop.is_rvc, issue_slots[11].brupdate.b2.uop.is_rvc connect slots_11.io.brupdate.b2.uop.debug_inst, issue_slots[11].brupdate.b2.uop.debug_inst connect slots_11.io.brupdate.b2.uop.inst, issue_slots[11].brupdate.b2.uop.inst connect slots_11.io.brupdate.b1.mispredict_mask, issue_slots[11].brupdate.b1.mispredict_mask connect slots_11.io.brupdate.b1.resolve_mask, issue_slots[11].brupdate.b1.resolve_mask connect issue_slots[11].out_uop.debug_tsrc, slots_11.io.out_uop.debug_tsrc connect issue_slots[11].out_uop.debug_fsrc, slots_11.io.out_uop.debug_fsrc connect issue_slots[11].out_uop.bp_xcpt_if, slots_11.io.out_uop.bp_xcpt_if connect issue_slots[11].out_uop.bp_debug_if, slots_11.io.out_uop.bp_debug_if connect issue_slots[11].out_uop.xcpt_ma_if, slots_11.io.out_uop.xcpt_ma_if connect issue_slots[11].out_uop.xcpt_ae_if, slots_11.io.out_uop.xcpt_ae_if connect issue_slots[11].out_uop.xcpt_pf_if, slots_11.io.out_uop.xcpt_pf_if connect issue_slots[11].out_uop.fp_typ, slots_11.io.out_uop.fp_typ connect issue_slots[11].out_uop.fp_rm, slots_11.io.out_uop.fp_rm connect issue_slots[11].out_uop.fp_val, slots_11.io.out_uop.fp_val connect issue_slots[11].out_uop.fcn_op, slots_11.io.out_uop.fcn_op connect issue_slots[11].out_uop.fcn_dw, slots_11.io.out_uop.fcn_dw connect issue_slots[11].out_uop.frs3_en, slots_11.io.out_uop.frs3_en connect issue_slots[11].out_uop.lrs2_rtype, slots_11.io.out_uop.lrs2_rtype connect issue_slots[11].out_uop.lrs1_rtype, slots_11.io.out_uop.lrs1_rtype connect issue_slots[11].out_uop.dst_rtype, slots_11.io.out_uop.dst_rtype connect issue_slots[11].out_uop.lrs3, slots_11.io.out_uop.lrs3 connect issue_slots[11].out_uop.lrs2, slots_11.io.out_uop.lrs2 connect issue_slots[11].out_uop.lrs1, slots_11.io.out_uop.lrs1 connect issue_slots[11].out_uop.ldst, slots_11.io.out_uop.ldst connect issue_slots[11].out_uop.ldst_is_rs1, slots_11.io.out_uop.ldst_is_rs1 connect issue_slots[11].out_uop.csr_cmd, slots_11.io.out_uop.csr_cmd connect issue_slots[11].out_uop.flush_on_commit, slots_11.io.out_uop.flush_on_commit connect issue_slots[11].out_uop.is_unique, slots_11.io.out_uop.is_unique connect issue_slots[11].out_uop.uses_stq, slots_11.io.out_uop.uses_stq connect issue_slots[11].out_uop.uses_ldq, slots_11.io.out_uop.uses_ldq connect issue_slots[11].out_uop.mem_signed, slots_11.io.out_uop.mem_signed connect issue_slots[11].out_uop.mem_size, slots_11.io.out_uop.mem_size connect issue_slots[11].out_uop.mem_cmd, slots_11.io.out_uop.mem_cmd connect issue_slots[11].out_uop.exc_cause, slots_11.io.out_uop.exc_cause connect issue_slots[11].out_uop.exception, slots_11.io.out_uop.exception connect issue_slots[11].out_uop.stale_pdst, slots_11.io.out_uop.stale_pdst connect issue_slots[11].out_uop.ppred_busy, slots_11.io.out_uop.ppred_busy connect issue_slots[11].out_uop.prs3_busy, slots_11.io.out_uop.prs3_busy connect issue_slots[11].out_uop.prs2_busy, slots_11.io.out_uop.prs2_busy connect issue_slots[11].out_uop.prs1_busy, slots_11.io.out_uop.prs1_busy connect issue_slots[11].out_uop.ppred, slots_11.io.out_uop.ppred connect issue_slots[11].out_uop.prs3, slots_11.io.out_uop.prs3 connect issue_slots[11].out_uop.prs2, slots_11.io.out_uop.prs2 connect issue_slots[11].out_uop.prs1, slots_11.io.out_uop.prs1 connect issue_slots[11].out_uop.pdst, slots_11.io.out_uop.pdst connect issue_slots[11].out_uop.rxq_idx, slots_11.io.out_uop.rxq_idx connect issue_slots[11].out_uop.stq_idx, slots_11.io.out_uop.stq_idx connect issue_slots[11].out_uop.ldq_idx, slots_11.io.out_uop.ldq_idx connect issue_slots[11].out_uop.rob_idx, slots_11.io.out_uop.rob_idx connect issue_slots[11].out_uop.fp_ctrl.vec, slots_11.io.out_uop.fp_ctrl.vec connect issue_slots[11].out_uop.fp_ctrl.wflags, slots_11.io.out_uop.fp_ctrl.wflags connect issue_slots[11].out_uop.fp_ctrl.sqrt, slots_11.io.out_uop.fp_ctrl.sqrt connect issue_slots[11].out_uop.fp_ctrl.div, slots_11.io.out_uop.fp_ctrl.div connect issue_slots[11].out_uop.fp_ctrl.fma, slots_11.io.out_uop.fp_ctrl.fma connect issue_slots[11].out_uop.fp_ctrl.fastpipe, slots_11.io.out_uop.fp_ctrl.fastpipe connect issue_slots[11].out_uop.fp_ctrl.toint, slots_11.io.out_uop.fp_ctrl.toint connect issue_slots[11].out_uop.fp_ctrl.fromint, slots_11.io.out_uop.fp_ctrl.fromint connect issue_slots[11].out_uop.fp_ctrl.typeTagOut, slots_11.io.out_uop.fp_ctrl.typeTagOut connect issue_slots[11].out_uop.fp_ctrl.typeTagIn, slots_11.io.out_uop.fp_ctrl.typeTagIn connect issue_slots[11].out_uop.fp_ctrl.swap23, slots_11.io.out_uop.fp_ctrl.swap23 connect issue_slots[11].out_uop.fp_ctrl.swap12, slots_11.io.out_uop.fp_ctrl.swap12 connect issue_slots[11].out_uop.fp_ctrl.ren3, slots_11.io.out_uop.fp_ctrl.ren3 connect issue_slots[11].out_uop.fp_ctrl.ren2, slots_11.io.out_uop.fp_ctrl.ren2 connect issue_slots[11].out_uop.fp_ctrl.ren1, slots_11.io.out_uop.fp_ctrl.ren1 connect issue_slots[11].out_uop.fp_ctrl.wen, slots_11.io.out_uop.fp_ctrl.wen connect issue_slots[11].out_uop.fp_ctrl.ldst, slots_11.io.out_uop.fp_ctrl.ldst connect issue_slots[11].out_uop.op2_sel, slots_11.io.out_uop.op2_sel connect issue_slots[11].out_uop.op1_sel, slots_11.io.out_uop.op1_sel connect issue_slots[11].out_uop.imm_packed, slots_11.io.out_uop.imm_packed connect issue_slots[11].out_uop.pimm, slots_11.io.out_uop.pimm connect issue_slots[11].out_uop.imm_sel, slots_11.io.out_uop.imm_sel connect issue_slots[11].out_uop.imm_rename, slots_11.io.out_uop.imm_rename connect issue_slots[11].out_uop.taken, slots_11.io.out_uop.taken connect issue_slots[11].out_uop.pc_lob, slots_11.io.out_uop.pc_lob connect issue_slots[11].out_uop.edge_inst, slots_11.io.out_uop.edge_inst connect issue_slots[11].out_uop.ftq_idx, slots_11.io.out_uop.ftq_idx connect issue_slots[11].out_uop.is_mov, slots_11.io.out_uop.is_mov connect issue_slots[11].out_uop.is_rocc, slots_11.io.out_uop.is_rocc connect issue_slots[11].out_uop.is_sys_pc2epc, slots_11.io.out_uop.is_sys_pc2epc connect issue_slots[11].out_uop.is_eret, slots_11.io.out_uop.is_eret connect issue_slots[11].out_uop.is_amo, slots_11.io.out_uop.is_amo connect issue_slots[11].out_uop.is_sfence, slots_11.io.out_uop.is_sfence connect issue_slots[11].out_uop.is_fencei, slots_11.io.out_uop.is_fencei connect issue_slots[11].out_uop.is_fence, slots_11.io.out_uop.is_fence connect issue_slots[11].out_uop.is_sfb, slots_11.io.out_uop.is_sfb connect issue_slots[11].out_uop.br_type, slots_11.io.out_uop.br_type connect issue_slots[11].out_uop.br_tag, slots_11.io.out_uop.br_tag connect issue_slots[11].out_uop.br_mask, slots_11.io.out_uop.br_mask connect issue_slots[11].out_uop.dis_col_sel, slots_11.io.out_uop.dis_col_sel connect issue_slots[11].out_uop.iw_p3_bypass_hint, slots_11.io.out_uop.iw_p3_bypass_hint connect issue_slots[11].out_uop.iw_p2_bypass_hint, slots_11.io.out_uop.iw_p2_bypass_hint connect issue_slots[11].out_uop.iw_p1_bypass_hint, slots_11.io.out_uop.iw_p1_bypass_hint connect issue_slots[11].out_uop.iw_p2_speculative_child, slots_11.io.out_uop.iw_p2_speculative_child connect issue_slots[11].out_uop.iw_p1_speculative_child, slots_11.io.out_uop.iw_p1_speculative_child connect issue_slots[11].out_uop.iw_issued_partial_dgen, slots_11.io.out_uop.iw_issued_partial_dgen connect issue_slots[11].out_uop.iw_issued_partial_agen, slots_11.io.out_uop.iw_issued_partial_agen connect issue_slots[11].out_uop.iw_issued, slots_11.io.out_uop.iw_issued connect issue_slots[11].out_uop.fu_code[0], slots_11.io.out_uop.fu_code[0] connect issue_slots[11].out_uop.fu_code[1], slots_11.io.out_uop.fu_code[1] connect issue_slots[11].out_uop.fu_code[2], slots_11.io.out_uop.fu_code[2] connect issue_slots[11].out_uop.fu_code[3], slots_11.io.out_uop.fu_code[3] connect issue_slots[11].out_uop.fu_code[4], slots_11.io.out_uop.fu_code[4] connect issue_slots[11].out_uop.fu_code[5], slots_11.io.out_uop.fu_code[5] connect issue_slots[11].out_uop.fu_code[6], slots_11.io.out_uop.fu_code[6] connect issue_slots[11].out_uop.fu_code[7], slots_11.io.out_uop.fu_code[7] connect issue_slots[11].out_uop.fu_code[8], slots_11.io.out_uop.fu_code[8] connect issue_slots[11].out_uop.fu_code[9], slots_11.io.out_uop.fu_code[9] connect issue_slots[11].out_uop.iq_type[0], slots_11.io.out_uop.iq_type[0] connect issue_slots[11].out_uop.iq_type[1], slots_11.io.out_uop.iq_type[1] connect issue_slots[11].out_uop.iq_type[2], slots_11.io.out_uop.iq_type[2] connect issue_slots[11].out_uop.iq_type[3], slots_11.io.out_uop.iq_type[3] connect issue_slots[11].out_uop.debug_pc, slots_11.io.out_uop.debug_pc connect issue_slots[11].out_uop.is_rvc, slots_11.io.out_uop.is_rvc connect issue_slots[11].out_uop.debug_inst, slots_11.io.out_uop.debug_inst connect issue_slots[11].out_uop.inst, slots_11.io.out_uop.inst connect slots_11.io.in_uop.bits.debug_tsrc, issue_slots[11].in_uop.bits.debug_tsrc connect slots_11.io.in_uop.bits.debug_fsrc, issue_slots[11].in_uop.bits.debug_fsrc connect slots_11.io.in_uop.bits.bp_xcpt_if, issue_slots[11].in_uop.bits.bp_xcpt_if connect slots_11.io.in_uop.bits.bp_debug_if, issue_slots[11].in_uop.bits.bp_debug_if connect slots_11.io.in_uop.bits.xcpt_ma_if, issue_slots[11].in_uop.bits.xcpt_ma_if connect slots_11.io.in_uop.bits.xcpt_ae_if, issue_slots[11].in_uop.bits.xcpt_ae_if connect slots_11.io.in_uop.bits.xcpt_pf_if, issue_slots[11].in_uop.bits.xcpt_pf_if connect slots_11.io.in_uop.bits.fp_typ, issue_slots[11].in_uop.bits.fp_typ connect slots_11.io.in_uop.bits.fp_rm, issue_slots[11].in_uop.bits.fp_rm connect slots_11.io.in_uop.bits.fp_val, issue_slots[11].in_uop.bits.fp_val connect slots_11.io.in_uop.bits.fcn_op, issue_slots[11].in_uop.bits.fcn_op connect slots_11.io.in_uop.bits.fcn_dw, issue_slots[11].in_uop.bits.fcn_dw connect slots_11.io.in_uop.bits.frs3_en, issue_slots[11].in_uop.bits.frs3_en connect slots_11.io.in_uop.bits.lrs2_rtype, issue_slots[11].in_uop.bits.lrs2_rtype connect slots_11.io.in_uop.bits.lrs1_rtype, issue_slots[11].in_uop.bits.lrs1_rtype connect slots_11.io.in_uop.bits.dst_rtype, issue_slots[11].in_uop.bits.dst_rtype connect slots_11.io.in_uop.bits.lrs3, issue_slots[11].in_uop.bits.lrs3 connect slots_11.io.in_uop.bits.lrs2, issue_slots[11].in_uop.bits.lrs2 connect slots_11.io.in_uop.bits.lrs1, issue_slots[11].in_uop.bits.lrs1 connect slots_11.io.in_uop.bits.ldst, issue_slots[11].in_uop.bits.ldst connect slots_11.io.in_uop.bits.ldst_is_rs1, issue_slots[11].in_uop.bits.ldst_is_rs1 connect slots_11.io.in_uop.bits.csr_cmd, issue_slots[11].in_uop.bits.csr_cmd connect slots_11.io.in_uop.bits.flush_on_commit, issue_slots[11].in_uop.bits.flush_on_commit connect slots_11.io.in_uop.bits.is_unique, issue_slots[11].in_uop.bits.is_unique connect slots_11.io.in_uop.bits.uses_stq, issue_slots[11].in_uop.bits.uses_stq connect slots_11.io.in_uop.bits.uses_ldq, issue_slots[11].in_uop.bits.uses_ldq connect slots_11.io.in_uop.bits.mem_signed, issue_slots[11].in_uop.bits.mem_signed connect slots_11.io.in_uop.bits.mem_size, issue_slots[11].in_uop.bits.mem_size connect slots_11.io.in_uop.bits.mem_cmd, issue_slots[11].in_uop.bits.mem_cmd connect slots_11.io.in_uop.bits.exc_cause, issue_slots[11].in_uop.bits.exc_cause connect slots_11.io.in_uop.bits.exception, issue_slots[11].in_uop.bits.exception connect slots_11.io.in_uop.bits.stale_pdst, issue_slots[11].in_uop.bits.stale_pdst connect slots_11.io.in_uop.bits.ppred_busy, issue_slots[11].in_uop.bits.ppred_busy connect slots_11.io.in_uop.bits.prs3_busy, issue_slots[11].in_uop.bits.prs3_busy connect slots_11.io.in_uop.bits.prs2_busy, issue_slots[11].in_uop.bits.prs2_busy connect slots_11.io.in_uop.bits.prs1_busy, issue_slots[11].in_uop.bits.prs1_busy connect slots_11.io.in_uop.bits.ppred, issue_slots[11].in_uop.bits.ppred connect slots_11.io.in_uop.bits.prs3, issue_slots[11].in_uop.bits.prs3 connect slots_11.io.in_uop.bits.prs2, issue_slots[11].in_uop.bits.prs2 connect slots_11.io.in_uop.bits.prs1, issue_slots[11].in_uop.bits.prs1 connect slots_11.io.in_uop.bits.pdst, issue_slots[11].in_uop.bits.pdst connect slots_11.io.in_uop.bits.rxq_idx, issue_slots[11].in_uop.bits.rxq_idx connect slots_11.io.in_uop.bits.stq_idx, issue_slots[11].in_uop.bits.stq_idx connect slots_11.io.in_uop.bits.ldq_idx, issue_slots[11].in_uop.bits.ldq_idx connect slots_11.io.in_uop.bits.rob_idx, issue_slots[11].in_uop.bits.rob_idx connect slots_11.io.in_uop.bits.fp_ctrl.vec, issue_slots[11].in_uop.bits.fp_ctrl.vec connect slots_11.io.in_uop.bits.fp_ctrl.wflags, issue_slots[11].in_uop.bits.fp_ctrl.wflags connect slots_11.io.in_uop.bits.fp_ctrl.sqrt, issue_slots[11].in_uop.bits.fp_ctrl.sqrt connect slots_11.io.in_uop.bits.fp_ctrl.div, issue_slots[11].in_uop.bits.fp_ctrl.div connect slots_11.io.in_uop.bits.fp_ctrl.fma, issue_slots[11].in_uop.bits.fp_ctrl.fma connect slots_11.io.in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].in_uop.bits.fp_ctrl.fastpipe connect slots_11.io.in_uop.bits.fp_ctrl.toint, issue_slots[11].in_uop.bits.fp_ctrl.toint connect slots_11.io.in_uop.bits.fp_ctrl.fromint, issue_slots[11].in_uop.bits.fp_ctrl.fromint connect slots_11.io.in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut connect slots_11.io.in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn connect slots_11.io.in_uop.bits.fp_ctrl.swap23, issue_slots[11].in_uop.bits.fp_ctrl.swap23 connect slots_11.io.in_uop.bits.fp_ctrl.swap12, issue_slots[11].in_uop.bits.fp_ctrl.swap12 connect slots_11.io.in_uop.bits.fp_ctrl.ren3, issue_slots[11].in_uop.bits.fp_ctrl.ren3 connect slots_11.io.in_uop.bits.fp_ctrl.ren2, issue_slots[11].in_uop.bits.fp_ctrl.ren2 connect slots_11.io.in_uop.bits.fp_ctrl.ren1, issue_slots[11].in_uop.bits.fp_ctrl.ren1 connect slots_11.io.in_uop.bits.fp_ctrl.wen, issue_slots[11].in_uop.bits.fp_ctrl.wen connect slots_11.io.in_uop.bits.fp_ctrl.ldst, issue_slots[11].in_uop.bits.fp_ctrl.ldst connect slots_11.io.in_uop.bits.op2_sel, issue_slots[11].in_uop.bits.op2_sel connect slots_11.io.in_uop.bits.op1_sel, issue_slots[11].in_uop.bits.op1_sel connect slots_11.io.in_uop.bits.imm_packed, issue_slots[11].in_uop.bits.imm_packed connect slots_11.io.in_uop.bits.pimm, issue_slots[11].in_uop.bits.pimm connect slots_11.io.in_uop.bits.imm_sel, issue_slots[11].in_uop.bits.imm_sel connect slots_11.io.in_uop.bits.imm_rename, issue_slots[11].in_uop.bits.imm_rename connect slots_11.io.in_uop.bits.taken, issue_slots[11].in_uop.bits.taken connect slots_11.io.in_uop.bits.pc_lob, issue_slots[11].in_uop.bits.pc_lob connect slots_11.io.in_uop.bits.edge_inst, issue_slots[11].in_uop.bits.edge_inst connect slots_11.io.in_uop.bits.ftq_idx, issue_slots[11].in_uop.bits.ftq_idx connect slots_11.io.in_uop.bits.is_mov, issue_slots[11].in_uop.bits.is_mov connect slots_11.io.in_uop.bits.is_rocc, issue_slots[11].in_uop.bits.is_rocc connect slots_11.io.in_uop.bits.is_sys_pc2epc, issue_slots[11].in_uop.bits.is_sys_pc2epc connect slots_11.io.in_uop.bits.is_eret, issue_slots[11].in_uop.bits.is_eret connect slots_11.io.in_uop.bits.is_amo, issue_slots[11].in_uop.bits.is_amo connect slots_11.io.in_uop.bits.is_sfence, issue_slots[11].in_uop.bits.is_sfence connect slots_11.io.in_uop.bits.is_fencei, issue_slots[11].in_uop.bits.is_fencei connect slots_11.io.in_uop.bits.is_fence, issue_slots[11].in_uop.bits.is_fence connect slots_11.io.in_uop.bits.is_sfb, issue_slots[11].in_uop.bits.is_sfb connect slots_11.io.in_uop.bits.br_type, issue_slots[11].in_uop.bits.br_type connect slots_11.io.in_uop.bits.br_tag, issue_slots[11].in_uop.bits.br_tag connect slots_11.io.in_uop.bits.br_mask, issue_slots[11].in_uop.bits.br_mask connect slots_11.io.in_uop.bits.dis_col_sel, issue_slots[11].in_uop.bits.dis_col_sel connect slots_11.io.in_uop.bits.iw_p3_bypass_hint, issue_slots[11].in_uop.bits.iw_p3_bypass_hint connect slots_11.io.in_uop.bits.iw_p2_bypass_hint, issue_slots[11].in_uop.bits.iw_p2_bypass_hint connect slots_11.io.in_uop.bits.iw_p1_bypass_hint, issue_slots[11].in_uop.bits.iw_p1_bypass_hint connect slots_11.io.in_uop.bits.iw_p2_speculative_child, issue_slots[11].in_uop.bits.iw_p2_speculative_child connect slots_11.io.in_uop.bits.iw_p1_speculative_child, issue_slots[11].in_uop.bits.iw_p1_speculative_child connect slots_11.io.in_uop.bits.iw_issued_partial_dgen, issue_slots[11].in_uop.bits.iw_issued_partial_dgen connect slots_11.io.in_uop.bits.iw_issued_partial_agen, issue_slots[11].in_uop.bits.iw_issued_partial_agen connect slots_11.io.in_uop.bits.iw_issued, issue_slots[11].in_uop.bits.iw_issued connect slots_11.io.in_uop.bits.fu_code[0], issue_slots[11].in_uop.bits.fu_code[0] connect slots_11.io.in_uop.bits.fu_code[1], issue_slots[11].in_uop.bits.fu_code[1] connect slots_11.io.in_uop.bits.fu_code[2], issue_slots[11].in_uop.bits.fu_code[2] connect slots_11.io.in_uop.bits.fu_code[3], issue_slots[11].in_uop.bits.fu_code[3] connect slots_11.io.in_uop.bits.fu_code[4], issue_slots[11].in_uop.bits.fu_code[4] connect slots_11.io.in_uop.bits.fu_code[5], issue_slots[11].in_uop.bits.fu_code[5] connect slots_11.io.in_uop.bits.fu_code[6], issue_slots[11].in_uop.bits.fu_code[6] connect slots_11.io.in_uop.bits.fu_code[7], issue_slots[11].in_uop.bits.fu_code[7] connect slots_11.io.in_uop.bits.fu_code[8], issue_slots[11].in_uop.bits.fu_code[8] connect slots_11.io.in_uop.bits.fu_code[9], issue_slots[11].in_uop.bits.fu_code[9] connect slots_11.io.in_uop.bits.iq_type[0], issue_slots[11].in_uop.bits.iq_type[0] connect slots_11.io.in_uop.bits.iq_type[1], issue_slots[11].in_uop.bits.iq_type[1] connect slots_11.io.in_uop.bits.iq_type[2], issue_slots[11].in_uop.bits.iq_type[2] connect slots_11.io.in_uop.bits.iq_type[3], issue_slots[11].in_uop.bits.iq_type[3] connect slots_11.io.in_uop.bits.debug_pc, issue_slots[11].in_uop.bits.debug_pc connect slots_11.io.in_uop.bits.is_rvc, issue_slots[11].in_uop.bits.is_rvc connect slots_11.io.in_uop.bits.debug_inst, issue_slots[11].in_uop.bits.debug_inst connect slots_11.io.in_uop.bits.inst, issue_slots[11].in_uop.bits.inst connect slots_11.io.in_uop.valid, issue_slots[11].in_uop.valid connect issue_slots[11].iss_uop.debug_tsrc, slots_11.io.iss_uop.debug_tsrc connect issue_slots[11].iss_uop.debug_fsrc, slots_11.io.iss_uop.debug_fsrc connect issue_slots[11].iss_uop.bp_xcpt_if, slots_11.io.iss_uop.bp_xcpt_if connect issue_slots[11].iss_uop.bp_debug_if, slots_11.io.iss_uop.bp_debug_if connect issue_slots[11].iss_uop.xcpt_ma_if, slots_11.io.iss_uop.xcpt_ma_if connect issue_slots[11].iss_uop.xcpt_ae_if, slots_11.io.iss_uop.xcpt_ae_if connect issue_slots[11].iss_uop.xcpt_pf_if, slots_11.io.iss_uop.xcpt_pf_if connect issue_slots[11].iss_uop.fp_typ, slots_11.io.iss_uop.fp_typ connect issue_slots[11].iss_uop.fp_rm, slots_11.io.iss_uop.fp_rm connect issue_slots[11].iss_uop.fp_val, slots_11.io.iss_uop.fp_val connect issue_slots[11].iss_uop.fcn_op, slots_11.io.iss_uop.fcn_op connect issue_slots[11].iss_uop.fcn_dw, slots_11.io.iss_uop.fcn_dw connect issue_slots[11].iss_uop.frs3_en, slots_11.io.iss_uop.frs3_en connect issue_slots[11].iss_uop.lrs2_rtype, slots_11.io.iss_uop.lrs2_rtype connect issue_slots[11].iss_uop.lrs1_rtype, slots_11.io.iss_uop.lrs1_rtype connect issue_slots[11].iss_uop.dst_rtype, slots_11.io.iss_uop.dst_rtype connect issue_slots[11].iss_uop.lrs3, slots_11.io.iss_uop.lrs3 connect issue_slots[11].iss_uop.lrs2, slots_11.io.iss_uop.lrs2 connect issue_slots[11].iss_uop.lrs1, slots_11.io.iss_uop.lrs1 connect issue_slots[11].iss_uop.ldst, slots_11.io.iss_uop.ldst connect issue_slots[11].iss_uop.ldst_is_rs1, slots_11.io.iss_uop.ldst_is_rs1 connect issue_slots[11].iss_uop.csr_cmd, slots_11.io.iss_uop.csr_cmd connect issue_slots[11].iss_uop.flush_on_commit, slots_11.io.iss_uop.flush_on_commit connect issue_slots[11].iss_uop.is_unique, slots_11.io.iss_uop.is_unique connect issue_slots[11].iss_uop.uses_stq, slots_11.io.iss_uop.uses_stq connect issue_slots[11].iss_uop.uses_ldq, slots_11.io.iss_uop.uses_ldq connect issue_slots[11].iss_uop.mem_signed, slots_11.io.iss_uop.mem_signed connect issue_slots[11].iss_uop.mem_size, slots_11.io.iss_uop.mem_size connect issue_slots[11].iss_uop.mem_cmd, slots_11.io.iss_uop.mem_cmd connect issue_slots[11].iss_uop.exc_cause, slots_11.io.iss_uop.exc_cause connect issue_slots[11].iss_uop.exception, slots_11.io.iss_uop.exception connect issue_slots[11].iss_uop.stale_pdst, slots_11.io.iss_uop.stale_pdst connect issue_slots[11].iss_uop.ppred_busy, slots_11.io.iss_uop.ppred_busy connect issue_slots[11].iss_uop.prs3_busy, slots_11.io.iss_uop.prs3_busy connect issue_slots[11].iss_uop.prs2_busy, slots_11.io.iss_uop.prs2_busy connect issue_slots[11].iss_uop.prs1_busy, slots_11.io.iss_uop.prs1_busy connect issue_slots[11].iss_uop.ppred, slots_11.io.iss_uop.ppred connect issue_slots[11].iss_uop.prs3, slots_11.io.iss_uop.prs3 connect issue_slots[11].iss_uop.prs2, slots_11.io.iss_uop.prs2 connect issue_slots[11].iss_uop.prs1, slots_11.io.iss_uop.prs1 connect issue_slots[11].iss_uop.pdst, slots_11.io.iss_uop.pdst connect issue_slots[11].iss_uop.rxq_idx, slots_11.io.iss_uop.rxq_idx connect issue_slots[11].iss_uop.stq_idx, slots_11.io.iss_uop.stq_idx connect issue_slots[11].iss_uop.ldq_idx, slots_11.io.iss_uop.ldq_idx connect issue_slots[11].iss_uop.rob_idx, slots_11.io.iss_uop.rob_idx connect issue_slots[11].iss_uop.fp_ctrl.vec, slots_11.io.iss_uop.fp_ctrl.vec connect issue_slots[11].iss_uop.fp_ctrl.wflags, slots_11.io.iss_uop.fp_ctrl.wflags connect issue_slots[11].iss_uop.fp_ctrl.sqrt, slots_11.io.iss_uop.fp_ctrl.sqrt connect issue_slots[11].iss_uop.fp_ctrl.div, slots_11.io.iss_uop.fp_ctrl.div connect issue_slots[11].iss_uop.fp_ctrl.fma, slots_11.io.iss_uop.fp_ctrl.fma connect issue_slots[11].iss_uop.fp_ctrl.fastpipe, slots_11.io.iss_uop.fp_ctrl.fastpipe connect issue_slots[11].iss_uop.fp_ctrl.toint, slots_11.io.iss_uop.fp_ctrl.toint connect issue_slots[11].iss_uop.fp_ctrl.fromint, slots_11.io.iss_uop.fp_ctrl.fromint connect issue_slots[11].iss_uop.fp_ctrl.typeTagOut, slots_11.io.iss_uop.fp_ctrl.typeTagOut connect issue_slots[11].iss_uop.fp_ctrl.typeTagIn, slots_11.io.iss_uop.fp_ctrl.typeTagIn connect issue_slots[11].iss_uop.fp_ctrl.swap23, slots_11.io.iss_uop.fp_ctrl.swap23 connect issue_slots[11].iss_uop.fp_ctrl.swap12, slots_11.io.iss_uop.fp_ctrl.swap12 connect issue_slots[11].iss_uop.fp_ctrl.ren3, slots_11.io.iss_uop.fp_ctrl.ren3 connect issue_slots[11].iss_uop.fp_ctrl.ren2, slots_11.io.iss_uop.fp_ctrl.ren2 connect issue_slots[11].iss_uop.fp_ctrl.ren1, slots_11.io.iss_uop.fp_ctrl.ren1 connect issue_slots[11].iss_uop.fp_ctrl.wen, slots_11.io.iss_uop.fp_ctrl.wen connect issue_slots[11].iss_uop.fp_ctrl.ldst, slots_11.io.iss_uop.fp_ctrl.ldst connect issue_slots[11].iss_uop.op2_sel, slots_11.io.iss_uop.op2_sel connect issue_slots[11].iss_uop.op1_sel, slots_11.io.iss_uop.op1_sel connect issue_slots[11].iss_uop.imm_packed, slots_11.io.iss_uop.imm_packed connect issue_slots[11].iss_uop.pimm, slots_11.io.iss_uop.pimm connect issue_slots[11].iss_uop.imm_sel, slots_11.io.iss_uop.imm_sel connect issue_slots[11].iss_uop.imm_rename, slots_11.io.iss_uop.imm_rename connect issue_slots[11].iss_uop.taken, slots_11.io.iss_uop.taken connect issue_slots[11].iss_uop.pc_lob, slots_11.io.iss_uop.pc_lob connect issue_slots[11].iss_uop.edge_inst, slots_11.io.iss_uop.edge_inst connect issue_slots[11].iss_uop.ftq_idx, slots_11.io.iss_uop.ftq_idx connect issue_slots[11].iss_uop.is_mov, slots_11.io.iss_uop.is_mov connect issue_slots[11].iss_uop.is_rocc, slots_11.io.iss_uop.is_rocc connect issue_slots[11].iss_uop.is_sys_pc2epc, slots_11.io.iss_uop.is_sys_pc2epc connect issue_slots[11].iss_uop.is_eret, slots_11.io.iss_uop.is_eret connect issue_slots[11].iss_uop.is_amo, slots_11.io.iss_uop.is_amo connect issue_slots[11].iss_uop.is_sfence, slots_11.io.iss_uop.is_sfence connect issue_slots[11].iss_uop.is_fencei, slots_11.io.iss_uop.is_fencei connect issue_slots[11].iss_uop.is_fence, slots_11.io.iss_uop.is_fence connect issue_slots[11].iss_uop.is_sfb, slots_11.io.iss_uop.is_sfb connect issue_slots[11].iss_uop.br_type, slots_11.io.iss_uop.br_type connect issue_slots[11].iss_uop.br_tag, slots_11.io.iss_uop.br_tag connect issue_slots[11].iss_uop.br_mask, slots_11.io.iss_uop.br_mask connect issue_slots[11].iss_uop.dis_col_sel, slots_11.io.iss_uop.dis_col_sel connect issue_slots[11].iss_uop.iw_p3_bypass_hint, slots_11.io.iss_uop.iw_p3_bypass_hint connect issue_slots[11].iss_uop.iw_p2_bypass_hint, slots_11.io.iss_uop.iw_p2_bypass_hint connect issue_slots[11].iss_uop.iw_p1_bypass_hint, slots_11.io.iss_uop.iw_p1_bypass_hint connect issue_slots[11].iss_uop.iw_p2_speculative_child, slots_11.io.iss_uop.iw_p2_speculative_child connect issue_slots[11].iss_uop.iw_p1_speculative_child, slots_11.io.iss_uop.iw_p1_speculative_child connect issue_slots[11].iss_uop.iw_issued_partial_dgen, slots_11.io.iss_uop.iw_issued_partial_dgen connect issue_slots[11].iss_uop.iw_issued_partial_agen, slots_11.io.iss_uop.iw_issued_partial_agen connect issue_slots[11].iss_uop.iw_issued, slots_11.io.iss_uop.iw_issued connect issue_slots[11].iss_uop.fu_code[0], slots_11.io.iss_uop.fu_code[0] connect issue_slots[11].iss_uop.fu_code[1], slots_11.io.iss_uop.fu_code[1] connect issue_slots[11].iss_uop.fu_code[2], slots_11.io.iss_uop.fu_code[2] connect issue_slots[11].iss_uop.fu_code[3], slots_11.io.iss_uop.fu_code[3] connect issue_slots[11].iss_uop.fu_code[4], slots_11.io.iss_uop.fu_code[4] connect issue_slots[11].iss_uop.fu_code[5], slots_11.io.iss_uop.fu_code[5] connect issue_slots[11].iss_uop.fu_code[6], slots_11.io.iss_uop.fu_code[6] connect issue_slots[11].iss_uop.fu_code[7], slots_11.io.iss_uop.fu_code[7] connect issue_slots[11].iss_uop.fu_code[8], slots_11.io.iss_uop.fu_code[8] connect issue_slots[11].iss_uop.fu_code[9], slots_11.io.iss_uop.fu_code[9] connect issue_slots[11].iss_uop.iq_type[0], slots_11.io.iss_uop.iq_type[0] connect issue_slots[11].iss_uop.iq_type[1], slots_11.io.iss_uop.iq_type[1] connect issue_slots[11].iss_uop.iq_type[2], slots_11.io.iss_uop.iq_type[2] connect issue_slots[11].iss_uop.iq_type[3], slots_11.io.iss_uop.iq_type[3] connect issue_slots[11].iss_uop.debug_pc, slots_11.io.iss_uop.debug_pc connect issue_slots[11].iss_uop.is_rvc, slots_11.io.iss_uop.is_rvc connect issue_slots[11].iss_uop.debug_inst, slots_11.io.iss_uop.debug_inst connect issue_slots[11].iss_uop.inst, slots_11.io.iss_uop.inst connect slots_11.io.grant, issue_slots[11].grant connect issue_slots[11].request, slots_11.io.request connect issue_slots[11].will_be_valid, slots_11.io.will_be_valid connect issue_slots[11].valid, slots_11.io.valid connect issue_slots[0].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[0].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[0].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[0].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[0].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[0].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[0].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[0].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[0].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[0].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[0].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[0].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[0].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[0].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[0].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[0].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[0].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[0].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[0].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[0].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[0].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[0].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[0].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[0].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[0].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[0].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[0].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[0].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[0].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[0].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[0].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[0].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[0].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[0].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[0].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[0].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[0].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[0].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[0].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[0].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[0].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[0].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[0].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[0].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[0].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[0].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[0].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[0].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[0].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[0].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[0].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[0].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[0].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[0].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[0].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[0].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[0].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[0].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[0].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[0].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[0].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[0].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[0].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[0].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[0].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[0].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[0].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[0].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[0].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[0].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[0].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[0].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[0].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[0].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[0].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[0].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[0].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[0].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[0].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[0].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[0].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[0].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[0].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[0].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[0].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[0].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[0].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[0].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[0].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[0].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[0].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[0].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[0].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[0].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[0].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[0].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[0].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[0].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[0].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[0].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[0].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[0].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[0].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[0].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[0].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[0].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[0].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[0].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[0].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[0].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[0].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[0].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[0].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[0].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[0].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[0].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[0].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[0].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[0].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[0].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[0].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[0].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[0].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[0].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[0].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[0].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[0].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[0].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[0].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[0].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[0].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[0].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[0].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[0].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[0].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[0].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[0].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[0].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[0].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[0].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[0].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[0].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[0].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[0].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[0].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[0].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[0].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[0].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[0].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[0].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[0].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[0].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[0].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[0].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[0].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[0].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[0].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[0].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[0].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[0].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[0].child_rebusys, io.child_rebusys connect issue_slots[0].squash_grant, io.squash_grant connect issue_slots[0].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[0].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[0].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[0].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[0].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[0].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[0].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[0].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[0].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[0].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[0].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[0].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[0].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[0].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[0].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[0].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[0].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[0].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[0].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[0].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[0].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[0].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[0].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[0].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[0].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[0].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[0].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[0].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[0].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[0].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[0].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[0].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[0].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[0].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[0].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[0].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[0].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[0].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[0].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[0].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[0].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[0].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[0].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[0].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[0].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[0].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[0].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[0].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[0].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[0].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[0].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[0].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[0].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[0].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[0].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[0].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[0].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[0].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[0].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[0].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[0].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[0].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[0].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[0].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[0].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[0].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[0].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[0].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[0].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[0].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[0].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[0].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[0].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[0].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[0].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[0].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[0].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[0].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[0].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[0].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[0].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[0].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[0].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[0].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[0].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[0].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[0].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[0].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[0].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[0].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[0].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[0].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[0].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[0].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[0].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[0].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[0].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[0].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[0].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[0].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[0].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[0].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[0].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[0].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[0].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[0].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[0].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[0].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[0].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[0].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[0].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[0].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[0].kill, io.flush_pipeline connect issue_slots[1].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[1].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[1].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[1].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[1].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[1].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[1].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[1].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[1].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[1].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[1].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[1].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[1].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[1].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[1].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[1].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[1].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[1].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[1].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[1].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[1].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[1].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[1].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[1].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[1].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[1].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[1].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[1].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[1].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[1].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[1].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[1].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[1].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[1].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[1].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[1].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[1].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[1].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[1].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[1].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[1].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[1].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[1].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[1].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[1].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[1].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[1].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[1].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[1].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[1].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[1].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[1].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[1].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[1].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[1].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[1].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[1].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[1].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[1].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[1].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[1].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[1].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[1].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[1].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[1].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[1].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[1].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[1].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[1].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[1].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[1].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[1].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[1].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[1].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[1].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[1].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[1].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[1].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[1].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[1].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[1].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[1].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[1].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[1].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[1].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[1].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[1].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[1].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[1].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[1].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[1].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[1].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[1].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[1].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[1].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[1].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[1].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[1].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[1].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[1].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[1].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[1].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[1].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[1].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[1].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[1].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[1].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[1].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[1].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[1].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[1].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[1].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[1].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[1].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[1].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[1].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[1].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[1].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[1].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[1].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[1].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[1].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[1].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[1].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[1].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[1].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[1].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[1].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[1].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[1].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[1].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[1].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[1].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[1].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[1].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[1].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[1].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[1].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[1].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[1].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[1].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[1].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[1].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[1].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[1].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[1].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[1].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[1].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[1].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[1].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[1].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[1].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[1].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[1].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[1].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[1].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[1].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[1].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[1].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[1].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[1].child_rebusys, io.child_rebusys connect issue_slots[1].squash_grant, io.squash_grant connect issue_slots[1].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[1].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[1].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[1].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[1].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[1].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[1].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[1].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[1].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[1].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[1].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[1].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[1].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[1].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[1].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[1].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[1].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[1].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[1].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[1].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[1].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[1].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[1].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[1].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[1].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[1].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[1].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[1].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[1].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[1].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[1].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[1].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[1].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[1].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[1].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[1].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[1].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[1].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[1].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[1].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[1].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[1].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[1].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[1].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[1].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[1].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[1].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[1].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[1].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[1].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[1].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[1].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[1].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[1].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[1].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[1].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[1].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[1].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[1].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[1].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[1].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[1].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[1].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[1].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[1].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[1].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[1].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[1].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[1].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[1].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[1].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[1].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[1].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[1].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[1].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[1].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[1].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[1].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[1].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[1].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[1].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[1].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[1].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[1].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[1].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[1].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[1].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[1].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[1].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[1].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[1].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[1].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[1].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[1].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[1].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[1].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[1].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[1].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[1].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[1].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[1].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[1].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[1].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[1].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[1].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[1].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[1].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[1].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[1].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[1].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[1].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[1].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[1].kill, io.flush_pipeline connect issue_slots[2].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[2].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[2].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[2].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[2].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[2].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[2].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[2].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[2].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[2].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[2].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[2].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[2].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[2].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[2].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[2].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[2].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[2].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[2].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[2].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[2].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[2].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[2].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[2].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[2].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[2].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[2].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[2].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[2].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[2].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[2].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[2].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[2].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[2].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[2].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[2].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[2].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[2].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[2].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[2].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[2].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[2].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[2].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[2].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[2].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[2].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[2].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[2].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[2].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[2].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[2].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[2].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[2].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[2].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[2].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[2].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[2].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[2].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[2].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[2].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[2].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[2].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[2].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[2].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[2].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[2].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[2].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[2].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[2].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[2].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[2].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[2].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[2].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[2].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[2].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[2].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[2].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[2].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[2].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[2].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[2].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[2].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[2].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[2].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[2].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[2].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[2].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[2].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[2].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[2].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[2].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[2].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[2].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[2].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[2].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[2].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[2].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[2].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[2].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[2].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[2].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[2].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[2].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[2].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[2].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[2].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[2].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[2].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[2].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[2].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[2].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[2].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[2].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[2].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[2].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[2].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[2].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[2].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[2].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[2].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[2].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[2].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[2].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[2].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[2].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[2].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[2].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[2].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[2].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[2].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[2].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[2].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[2].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[2].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[2].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[2].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[2].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[2].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[2].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[2].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[2].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[2].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[2].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[2].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[2].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[2].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[2].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[2].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[2].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[2].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[2].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[2].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[2].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[2].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[2].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[2].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[2].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[2].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[2].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[2].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[2].child_rebusys, io.child_rebusys connect issue_slots[2].squash_grant, io.squash_grant connect issue_slots[2].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[2].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[2].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[2].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[2].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[2].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[2].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[2].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[2].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[2].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[2].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[2].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[2].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[2].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[2].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[2].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[2].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[2].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[2].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[2].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[2].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[2].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[2].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[2].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[2].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[2].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[2].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[2].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[2].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[2].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[2].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[2].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[2].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[2].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[2].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[2].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[2].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[2].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[2].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[2].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[2].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[2].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[2].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[2].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[2].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[2].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[2].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[2].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[2].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[2].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[2].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[2].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[2].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[2].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[2].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[2].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[2].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[2].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[2].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[2].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[2].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[2].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[2].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[2].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[2].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[2].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[2].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[2].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[2].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[2].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[2].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[2].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[2].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[2].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[2].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[2].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[2].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[2].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[2].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[2].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[2].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[2].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[2].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[2].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[2].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[2].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[2].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[2].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[2].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[2].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[2].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[2].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[2].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[2].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[2].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[2].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[2].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[2].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[2].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[2].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[2].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[2].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[2].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[2].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[2].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[2].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[2].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[2].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[2].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[2].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[2].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[2].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[2].kill, io.flush_pipeline connect issue_slots[3].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[3].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[3].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[3].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[3].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[3].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[3].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[3].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[3].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[3].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[3].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[3].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[3].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[3].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[3].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[3].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[3].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[3].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[3].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[3].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[3].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[3].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[3].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[3].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[3].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[3].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[3].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[3].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[3].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[3].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[3].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[3].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[3].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[3].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[3].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[3].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[3].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[3].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[3].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[3].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[3].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[3].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[3].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[3].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[3].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[3].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[3].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[3].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[3].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[3].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[3].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[3].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[3].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[3].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[3].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[3].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[3].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[3].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[3].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[3].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[3].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[3].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[3].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[3].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[3].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[3].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[3].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[3].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[3].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[3].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[3].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[3].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[3].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[3].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[3].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[3].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[3].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[3].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[3].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[3].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[3].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[3].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[3].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[3].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[3].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[3].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[3].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[3].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[3].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[3].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[3].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[3].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[3].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[3].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[3].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[3].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[3].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[3].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[3].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[3].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[3].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[3].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[3].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[3].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[3].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[3].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[3].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[3].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[3].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[3].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[3].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[3].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[3].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[3].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[3].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[3].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[3].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[3].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[3].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[3].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[3].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[3].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[3].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[3].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[3].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[3].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[3].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[3].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[3].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[3].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[3].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[3].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[3].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[3].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[3].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[3].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[3].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[3].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[3].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[3].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[3].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[3].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[3].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[3].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[3].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[3].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[3].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[3].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[3].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[3].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[3].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[3].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[3].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[3].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[3].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[3].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[3].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[3].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[3].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[3].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[3].child_rebusys, io.child_rebusys connect issue_slots[3].squash_grant, io.squash_grant connect issue_slots[3].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[3].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[3].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[3].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[3].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[3].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[3].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[3].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[3].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[3].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[3].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[3].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[3].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[3].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[3].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[3].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[3].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[3].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[3].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[3].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[3].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[3].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[3].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[3].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[3].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[3].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[3].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[3].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[3].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[3].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[3].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[3].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[3].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[3].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[3].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[3].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[3].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[3].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[3].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[3].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[3].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[3].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[3].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[3].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[3].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[3].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[3].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[3].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[3].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[3].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[3].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[3].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[3].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[3].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[3].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[3].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[3].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[3].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[3].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[3].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[3].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[3].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[3].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[3].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[3].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[3].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[3].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[3].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[3].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[3].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[3].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[3].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[3].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[3].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[3].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[3].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[3].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[3].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[3].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[3].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[3].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[3].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[3].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[3].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[3].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[3].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[3].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[3].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[3].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[3].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[3].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[3].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[3].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[3].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[3].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[3].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[3].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[3].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[3].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[3].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[3].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[3].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[3].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[3].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[3].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[3].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[3].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[3].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[3].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[3].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[3].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[3].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[3].kill, io.flush_pipeline connect issue_slots[4].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[4].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[4].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[4].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[4].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[4].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[4].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[4].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[4].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[4].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[4].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[4].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[4].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[4].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[4].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[4].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[4].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[4].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[4].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[4].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[4].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[4].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[4].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[4].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[4].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[4].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[4].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[4].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[4].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[4].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[4].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[4].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[4].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[4].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[4].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[4].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[4].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[4].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[4].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[4].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[4].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[4].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[4].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[4].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[4].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[4].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[4].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[4].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[4].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[4].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[4].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[4].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[4].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[4].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[4].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[4].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[4].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[4].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[4].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[4].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[4].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[4].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[4].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[4].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[4].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[4].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[4].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[4].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[4].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[4].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[4].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[4].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[4].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[4].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[4].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[4].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[4].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[4].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[4].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[4].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[4].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[4].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[4].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[4].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[4].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[4].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[4].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[4].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[4].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[4].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[4].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[4].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[4].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[4].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[4].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[4].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[4].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[4].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[4].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[4].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[4].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[4].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[4].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[4].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[4].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[4].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[4].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[4].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[4].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[4].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[4].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[4].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[4].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[4].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[4].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[4].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[4].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[4].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[4].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[4].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[4].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[4].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[4].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[4].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[4].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[4].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[4].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[4].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[4].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[4].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[4].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[4].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[4].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[4].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[4].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[4].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[4].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[4].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[4].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[4].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[4].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[4].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[4].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[4].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[4].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[4].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[4].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[4].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[4].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[4].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[4].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[4].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[4].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[4].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[4].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[4].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[4].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[4].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[4].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[4].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[4].child_rebusys, io.child_rebusys connect issue_slots[4].squash_grant, io.squash_grant connect issue_slots[4].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[4].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[4].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[4].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[4].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[4].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[4].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[4].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[4].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[4].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[4].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[4].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[4].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[4].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[4].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[4].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[4].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[4].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[4].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[4].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[4].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[4].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[4].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[4].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[4].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[4].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[4].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[4].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[4].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[4].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[4].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[4].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[4].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[4].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[4].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[4].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[4].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[4].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[4].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[4].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[4].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[4].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[4].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[4].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[4].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[4].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[4].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[4].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[4].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[4].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[4].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[4].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[4].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[4].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[4].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[4].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[4].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[4].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[4].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[4].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[4].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[4].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[4].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[4].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[4].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[4].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[4].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[4].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[4].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[4].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[4].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[4].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[4].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[4].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[4].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[4].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[4].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[4].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[4].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[4].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[4].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[4].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[4].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[4].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[4].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[4].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[4].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[4].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[4].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[4].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[4].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[4].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[4].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[4].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[4].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[4].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[4].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[4].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[4].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[4].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[4].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[4].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[4].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[4].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[4].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[4].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[4].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[4].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[4].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[4].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[4].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[4].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[4].kill, io.flush_pipeline connect issue_slots[5].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[5].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[5].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[5].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[5].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[5].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[5].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[5].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[5].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[5].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[5].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[5].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[5].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[5].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[5].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[5].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[5].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[5].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[5].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[5].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[5].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[5].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[5].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[5].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[5].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[5].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[5].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[5].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[5].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[5].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[5].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[5].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[5].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[5].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[5].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[5].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[5].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[5].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[5].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[5].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[5].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[5].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[5].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[5].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[5].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[5].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[5].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[5].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[5].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[5].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[5].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[5].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[5].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[5].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[5].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[5].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[5].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[5].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[5].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[5].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[5].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[5].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[5].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[5].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[5].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[5].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[5].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[5].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[5].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[5].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[5].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[5].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[5].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[5].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[5].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[5].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[5].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[5].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[5].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[5].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[5].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[5].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[5].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[5].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[5].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[5].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[5].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[5].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[5].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[5].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[5].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[5].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[5].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[5].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[5].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[5].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[5].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[5].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[5].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[5].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[5].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[5].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[5].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[5].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[5].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[5].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[5].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[5].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[5].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[5].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[5].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[5].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[5].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[5].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[5].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[5].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[5].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[5].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[5].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[5].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[5].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[5].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[5].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[5].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[5].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[5].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[5].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[5].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[5].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[5].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[5].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[5].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[5].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[5].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[5].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[5].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[5].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[5].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[5].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[5].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[5].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[5].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[5].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[5].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[5].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[5].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[5].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[5].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[5].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[5].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[5].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[5].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[5].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[5].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[5].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[5].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[5].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[5].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[5].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[5].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[5].child_rebusys, io.child_rebusys connect issue_slots[5].squash_grant, io.squash_grant connect issue_slots[5].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[5].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[5].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[5].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[5].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[5].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[5].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[5].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[5].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[5].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[5].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[5].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[5].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[5].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[5].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[5].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[5].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[5].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[5].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[5].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[5].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[5].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[5].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[5].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[5].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[5].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[5].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[5].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[5].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[5].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[5].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[5].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[5].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[5].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[5].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[5].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[5].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[5].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[5].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[5].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[5].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[5].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[5].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[5].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[5].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[5].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[5].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[5].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[5].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[5].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[5].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[5].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[5].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[5].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[5].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[5].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[5].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[5].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[5].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[5].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[5].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[5].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[5].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[5].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[5].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[5].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[5].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[5].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[5].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[5].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[5].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[5].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[5].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[5].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[5].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[5].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[5].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[5].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[5].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[5].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[5].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[5].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[5].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[5].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[5].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[5].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[5].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[5].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[5].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[5].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[5].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[5].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[5].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[5].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[5].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[5].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[5].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[5].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[5].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[5].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[5].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[5].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[5].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[5].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[5].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[5].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[5].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[5].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[5].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[5].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[5].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[5].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[5].kill, io.flush_pipeline connect issue_slots[6].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[6].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[6].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[6].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[6].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[6].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[6].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[6].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[6].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[6].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[6].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[6].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[6].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[6].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[6].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[6].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[6].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[6].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[6].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[6].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[6].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[6].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[6].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[6].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[6].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[6].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[6].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[6].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[6].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[6].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[6].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[6].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[6].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[6].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[6].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[6].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[6].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[6].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[6].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[6].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[6].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[6].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[6].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[6].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[6].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[6].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[6].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[6].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[6].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[6].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[6].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[6].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[6].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[6].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[6].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[6].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[6].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[6].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[6].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[6].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[6].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[6].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[6].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[6].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[6].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[6].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[6].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[6].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[6].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[6].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[6].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[6].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[6].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[6].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[6].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[6].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[6].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[6].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[6].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[6].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[6].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[6].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[6].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[6].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[6].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[6].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[6].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[6].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[6].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[6].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[6].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[6].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[6].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[6].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[6].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[6].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[6].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[6].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[6].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[6].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[6].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[6].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[6].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[6].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[6].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[6].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[6].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[6].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[6].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[6].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[6].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[6].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[6].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[6].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[6].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[6].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[6].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[6].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[6].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[6].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[6].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[6].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[6].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[6].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[6].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[6].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[6].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[6].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[6].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[6].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[6].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[6].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[6].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[6].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[6].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[6].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[6].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[6].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[6].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[6].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[6].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[6].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[6].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[6].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[6].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[6].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[6].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[6].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[6].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[6].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[6].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[6].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[6].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[6].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[6].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[6].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[6].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[6].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[6].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[6].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[6].child_rebusys, io.child_rebusys connect issue_slots[6].squash_grant, io.squash_grant connect issue_slots[6].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[6].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[6].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[6].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[6].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[6].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[6].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[6].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[6].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[6].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[6].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[6].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[6].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[6].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[6].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[6].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[6].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[6].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[6].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[6].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[6].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[6].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[6].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[6].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[6].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[6].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[6].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[6].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[6].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[6].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[6].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[6].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[6].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[6].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[6].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[6].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[6].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[6].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[6].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[6].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[6].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[6].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[6].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[6].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[6].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[6].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[6].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[6].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[6].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[6].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[6].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[6].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[6].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[6].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[6].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[6].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[6].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[6].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[6].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[6].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[6].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[6].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[6].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[6].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[6].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[6].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[6].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[6].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[6].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[6].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[6].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[6].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[6].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[6].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[6].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[6].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[6].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[6].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[6].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[6].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[6].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[6].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[6].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[6].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[6].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[6].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[6].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[6].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[6].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[6].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[6].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[6].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[6].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[6].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[6].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[6].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[6].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[6].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[6].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[6].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[6].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[6].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[6].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[6].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[6].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[6].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[6].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[6].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[6].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[6].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[6].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[6].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[6].kill, io.flush_pipeline connect issue_slots[7].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[7].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[7].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[7].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[7].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[7].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[7].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[7].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[7].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[7].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[7].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[7].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[7].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[7].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[7].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[7].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[7].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[7].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[7].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[7].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[7].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[7].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[7].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[7].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[7].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[7].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[7].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[7].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[7].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[7].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[7].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[7].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[7].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[7].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[7].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[7].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[7].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[7].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[7].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[7].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[7].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[7].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[7].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[7].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[7].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[7].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[7].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[7].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[7].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[7].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[7].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[7].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[7].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[7].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[7].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[7].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[7].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[7].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[7].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[7].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[7].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[7].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[7].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[7].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[7].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[7].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[7].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[7].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[7].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[7].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[7].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[7].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[7].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[7].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[7].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[7].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[7].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[7].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[7].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[7].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[7].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[7].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[7].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[7].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[7].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[7].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[7].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[7].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[7].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[7].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[7].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[7].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[7].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[7].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[7].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[7].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[7].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[7].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[7].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[7].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[7].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[7].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[7].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[7].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[7].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[7].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[7].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[7].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[7].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[7].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[7].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[7].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[7].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[7].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[7].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[7].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[7].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[7].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[7].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[7].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[7].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[7].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[7].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[7].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[7].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[7].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[7].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[7].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[7].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[7].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[7].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[7].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[7].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[7].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[7].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[7].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[7].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[7].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[7].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[7].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[7].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[7].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[7].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[7].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[7].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[7].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[7].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[7].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[7].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[7].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[7].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[7].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[7].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[7].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[7].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[7].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[7].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[7].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[7].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[7].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[7].child_rebusys, io.child_rebusys connect issue_slots[7].squash_grant, io.squash_grant connect issue_slots[7].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[7].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[7].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[7].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[7].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[7].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[7].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[7].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[7].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[7].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[7].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[7].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[7].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[7].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[7].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[7].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[7].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[7].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[7].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[7].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[7].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[7].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[7].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[7].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[7].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[7].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[7].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[7].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[7].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[7].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[7].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[7].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[7].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[7].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[7].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[7].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[7].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[7].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[7].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[7].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[7].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[7].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[7].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[7].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[7].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[7].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[7].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[7].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[7].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[7].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[7].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[7].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[7].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[7].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[7].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[7].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[7].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[7].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[7].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[7].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[7].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[7].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[7].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[7].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[7].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[7].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[7].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[7].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[7].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[7].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[7].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[7].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[7].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[7].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[7].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[7].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[7].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[7].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[7].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[7].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[7].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[7].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[7].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[7].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[7].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[7].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[7].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[7].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[7].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[7].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[7].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[7].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[7].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[7].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[7].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[7].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[7].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[7].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[7].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[7].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[7].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[7].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[7].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[7].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[7].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[7].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[7].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[7].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[7].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[7].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[7].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[7].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[7].kill, io.flush_pipeline connect issue_slots[8].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[8].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[8].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[8].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[8].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[8].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[8].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[8].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[8].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[8].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[8].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[8].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[8].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[8].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[8].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[8].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[8].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[8].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[8].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[8].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[8].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[8].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[8].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[8].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[8].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[8].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[8].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[8].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[8].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[8].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[8].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[8].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[8].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[8].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[8].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[8].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[8].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[8].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[8].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[8].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[8].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[8].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[8].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[8].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[8].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[8].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[8].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[8].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[8].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[8].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[8].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[8].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[8].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[8].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[8].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[8].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[8].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[8].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[8].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[8].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[8].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[8].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[8].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[8].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[8].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[8].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[8].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[8].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[8].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[8].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[8].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[8].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[8].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[8].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[8].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[8].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[8].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[8].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[8].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[8].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[8].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[8].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[8].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[8].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[8].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[8].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[8].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[8].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[8].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[8].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[8].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[8].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[8].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[8].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[8].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[8].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[8].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[8].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[8].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[8].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[8].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[8].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[8].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[8].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[8].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[8].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[8].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[8].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[8].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[8].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[8].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[8].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[8].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[8].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[8].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[8].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[8].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[8].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[8].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[8].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[8].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[8].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[8].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[8].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[8].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[8].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[8].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[8].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[8].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[8].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[8].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[8].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[8].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[8].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[8].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[8].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[8].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[8].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[8].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[8].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[8].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[8].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[8].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[8].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[8].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[8].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[8].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[8].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[8].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[8].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[8].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[8].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[8].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[8].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[8].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[8].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[8].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[8].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[8].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[8].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[8].child_rebusys, io.child_rebusys connect issue_slots[8].squash_grant, io.squash_grant connect issue_slots[8].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[8].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[8].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[8].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[8].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[8].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[8].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[8].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[8].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[8].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[8].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[8].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[8].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[8].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[8].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[8].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[8].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[8].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[8].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[8].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[8].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[8].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[8].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[8].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[8].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[8].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[8].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[8].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[8].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[8].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[8].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[8].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[8].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[8].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[8].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[8].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[8].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[8].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[8].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[8].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[8].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[8].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[8].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[8].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[8].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[8].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[8].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[8].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[8].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[8].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[8].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[8].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[8].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[8].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[8].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[8].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[8].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[8].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[8].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[8].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[8].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[8].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[8].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[8].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[8].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[8].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[8].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[8].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[8].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[8].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[8].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[8].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[8].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[8].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[8].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[8].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[8].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[8].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[8].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[8].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[8].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[8].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[8].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[8].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[8].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[8].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[8].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[8].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[8].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[8].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[8].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[8].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[8].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[8].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[8].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[8].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[8].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[8].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[8].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[8].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[8].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[8].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[8].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[8].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[8].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[8].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[8].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[8].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[8].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[8].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[8].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[8].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[8].kill, io.flush_pipeline connect issue_slots[9].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[9].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[9].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[9].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[9].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[9].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[9].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[9].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[9].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[9].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[9].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[9].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[9].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[9].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[9].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[9].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[9].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[9].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[9].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[9].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[9].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[9].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[9].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[9].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[9].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[9].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[9].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[9].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[9].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[9].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[9].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[9].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[9].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[9].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[9].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[9].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[9].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[9].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[9].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[9].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[9].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[9].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[9].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[9].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[9].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[9].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[9].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[9].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[9].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[9].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[9].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[9].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[9].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[9].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[9].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[9].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[9].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[9].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[9].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[9].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[9].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[9].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[9].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[9].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[9].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[9].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[9].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[9].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[9].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[9].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[9].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[9].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[9].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[9].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[9].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[9].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[9].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[9].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[9].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[9].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[9].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[9].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[9].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[9].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[9].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[9].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[9].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[9].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[9].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[9].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[9].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[9].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[9].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[9].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[9].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[9].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[9].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[9].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[9].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[9].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[9].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[9].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[9].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[9].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[9].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[9].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[9].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[9].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[9].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[9].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[9].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[9].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[9].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[9].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[9].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[9].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[9].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[9].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[9].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[9].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[9].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[9].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[9].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[9].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[9].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[9].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[9].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[9].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[9].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[9].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[9].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[9].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[9].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[9].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[9].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[9].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[9].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[9].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[9].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[9].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[9].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[9].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[9].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[9].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[9].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[9].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[9].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[9].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[9].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[9].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[9].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[9].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[9].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[9].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[9].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[9].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[9].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[9].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[9].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[9].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[9].child_rebusys, io.child_rebusys connect issue_slots[9].squash_grant, io.squash_grant connect issue_slots[9].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[9].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[9].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[9].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[9].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[9].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[9].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[9].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[9].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[9].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[9].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[9].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[9].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[9].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[9].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[9].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[9].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[9].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[9].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[9].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[9].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[9].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[9].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[9].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[9].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[9].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[9].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[9].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[9].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[9].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[9].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[9].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[9].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[9].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[9].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[9].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[9].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[9].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[9].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[9].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[9].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[9].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[9].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[9].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[9].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[9].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[9].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[9].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[9].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[9].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[9].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[9].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[9].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[9].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[9].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[9].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[9].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[9].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[9].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[9].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[9].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[9].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[9].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[9].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[9].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[9].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[9].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[9].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[9].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[9].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[9].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[9].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[9].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[9].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[9].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[9].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[9].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[9].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[9].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[9].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[9].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[9].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[9].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[9].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[9].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[9].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[9].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[9].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[9].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[9].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[9].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[9].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[9].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[9].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[9].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[9].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[9].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[9].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[9].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[9].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[9].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[9].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[9].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[9].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[9].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[9].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[9].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[9].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[9].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[9].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[9].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[9].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[9].kill, io.flush_pipeline connect issue_slots[10].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[10].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[10].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[10].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[10].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[10].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[10].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[10].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[10].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[10].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[10].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[10].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[10].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[10].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[10].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[10].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[10].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[10].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[10].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[10].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[10].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[10].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[10].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[10].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[10].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[10].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[10].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[10].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[10].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[10].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[10].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[10].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[10].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[10].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[10].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[10].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[10].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[10].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[10].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[10].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[10].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[10].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[10].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[10].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[10].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[10].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[10].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[10].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[10].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[10].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[10].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[10].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[10].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[10].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[10].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[10].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[10].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[10].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[10].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[10].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[10].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[10].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[10].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[10].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[10].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[10].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[10].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[10].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[10].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[10].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[10].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[10].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[10].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[10].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[10].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[10].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[10].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[10].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[10].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[10].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[10].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[10].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[10].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[10].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[10].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[10].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[10].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[10].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[10].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[10].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[10].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[10].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[10].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[10].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[10].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[10].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[10].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[10].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[10].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[10].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[10].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[10].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[10].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[10].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[10].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[10].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[10].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[10].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[10].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[10].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[10].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[10].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[10].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[10].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[10].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[10].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[10].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[10].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[10].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[10].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[10].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[10].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[10].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[10].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[10].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[10].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[10].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[10].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[10].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[10].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[10].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[10].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[10].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[10].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[10].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[10].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[10].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[10].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[10].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[10].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[10].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[10].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[10].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[10].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[10].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[10].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[10].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[10].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[10].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[10].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[10].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[10].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[10].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[10].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[10].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[10].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[10].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[10].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[10].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[10].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[10].child_rebusys, io.child_rebusys connect issue_slots[10].squash_grant, io.squash_grant connect issue_slots[10].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[10].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[10].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[10].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[10].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[10].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[10].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[10].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[10].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[10].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[10].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[10].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[10].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[10].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[10].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[10].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[10].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[10].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[10].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[10].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[10].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[10].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[10].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[10].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[10].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[10].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[10].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[10].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[10].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[10].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[10].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[10].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[10].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[10].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[10].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[10].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[10].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[10].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[10].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[10].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[10].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[10].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[10].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[10].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[10].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[10].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[10].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[10].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[10].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[10].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[10].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[10].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[10].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[10].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[10].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[10].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[10].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[10].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[10].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[10].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[10].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[10].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[10].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[10].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[10].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[10].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[10].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[10].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[10].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[10].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[10].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[10].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[10].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[10].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[10].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[10].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[10].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[10].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[10].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[10].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[10].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[10].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[10].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[10].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[10].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[10].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[10].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[10].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[10].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[10].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[10].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[10].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[10].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[10].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[10].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[10].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[10].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[10].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[10].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[10].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[10].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[10].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[10].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[10].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[10].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[10].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[10].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[10].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[10].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[10].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[10].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[10].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[10].kill, io.flush_pipeline connect issue_slots[11].wakeup_ports[0].bits.rebusy, io.wakeup_ports[0].bits.rebusy connect issue_slots[11].wakeup_ports[0].bits.speculative_mask, io.wakeup_ports[0].bits.speculative_mask connect issue_slots[11].wakeup_ports[0].bits.bypassable, io.wakeup_ports[0].bits.bypassable connect issue_slots[11].wakeup_ports[0].bits.uop.debug_tsrc, io.wakeup_ports[0].bits.uop.debug_tsrc connect issue_slots[11].wakeup_ports[0].bits.uop.debug_fsrc, io.wakeup_ports[0].bits.uop.debug_fsrc connect issue_slots[11].wakeup_ports[0].bits.uop.bp_xcpt_if, io.wakeup_ports[0].bits.uop.bp_xcpt_if connect issue_slots[11].wakeup_ports[0].bits.uop.bp_debug_if, io.wakeup_ports[0].bits.uop.bp_debug_if connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ma_if, io.wakeup_ports[0].bits.uop.xcpt_ma_if connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_ae_if, io.wakeup_ports[0].bits.uop.xcpt_ae_if connect issue_slots[11].wakeup_ports[0].bits.uop.xcpt_pf_if, io.wakeup_ports[0].bits.uop.xcpt_pf_if connect issue_slots[11].wakeup_ports[0].bits.uop.fp_typ, io.wakeup_ports[0].bits.uop.fp_typ connect issue_slots[11].wakeup_ports[0].bits.uop.fp_rm, io.wakeup_ports[0].bits.uop.fp_rm connect issue_slots[11].wakeup_ports[0].bits.uop.fp_val, io.wakeup_ports[0].bits.uop.fp_val connect issue_slots[11].wakeup_ports[0].bits.uop.fcn_op, io.wakeup_ports[0].bits.uop.fcn_op connect issue_slots[11].wakeup_ports[0].bits.uop.fcn_dw, io.wakeup_ports[0].bits.uop.fcn_dw connect issue_slots[11].wakeup_ports[0].bits.uop.frs3_en, io.wakeup_ports[0].bits.uop.frs3_en connect issue_slots[11].wakeup_ports[0].bits.uop.lrs2_rtype, io.wakeup_ports[0].bits.uop.lrs2_rtype connect issue_slots[11].wakeup_ports[0].bits.uop.lrs1_rtype, io.wakeup_ports[0].bits.uop.lrs1_rtype connect issue_slots[11].wakeup_ports[0].bits.uop.dst_rtype, io.wakeup_ports[0].bits.uop.dst_rtype connect issue_slots[11].wakeup_ports[0].bits.uop.lrs3, io.wakeup_ports[0].bits.uop.lrs3 connect issue_slots[11].wakeup_ports[0].bits.uop.lrs2, io.wakeup_ports[0].bits.uop.lrs2 connect issue_slots[11].wakeup_ports[0].bits.uop.lrs1, io.wakeup_ports[0].bits.uop.lrs1 connect issue_slots[11].wakeup_ports[0].bits.uop.ldst, io.wakeup_ports[0].bits.uop.ldst connect issue_slots[11].wakeup_ports[0].bits.uop.ldst_is_rs1, io.wakeup_ports[0].bits.uop.ldst_is_rs1 connect issue_slots[11].wakeup_ports[0].bits.uop.csr_cmd, io.wakeup_ports[0].bits.uop.csr_cmd connect issue_slots[11].wakeup_ports[0].bits.uop.flush_on_commit, io.wakeup_ports[0].bits.uop.flush_on_commit connect issue_slots[11].wakeup_ports[0].bits.uop.is_unique, io.wakeup_ports[0].bits.uop.is_unique connect issue_slots[11].wakeup_ports[0].bits.uop.uses_stq, io.wakeup_ports[0].bits.uop.uses_stq connect issue_slots[11].wakeup_ports[0].bits.uop.uses_ldq, io.wakeup_ports[0].bits.uop.uses_ldq connect issue_slots[11].wakeup_ports[0].bits.uop.mem_signed, io.wakeup_ports[0].bits.uop.mem_signed connect issue_slots[11].wakeup_ports[0].bits.uop.mem_size, io.wakeup_ports[0].bits.uop.mem_size connect issue_slots[11].wakeup_ports[0].bits.uop.mem_cmd, io.wakeup_ports[0].bits.uop.mem_cmd connect issue_slots[11].wakeup_ports[0].bits.uop.exc_cause, io.wakeup_ports[0].bits.uop.exc_cause connect issue_slots[11].wakeup_ports[0].bits.uop.exception, io.wakeup_ports[0].bits.uop.exception connect issue_slots[11].wakeup_ports[0].bits.uop.stale_pdst, io.wakeup_ports[0].bits.uop.stale_pdst connect issue_slots[11].wakeup_ports[0].bits.uop.ppred_busy, io.wakeup_ports[0].bits.uop.ppred_busy connect issue_slots[11].wakeup_ports[0].bits.uop.prs3_busy, io.wakeup_ports[0].bits.uop.prs3_busy connect issue_slots[11].wakeup_ports[0].bits.uop.prs2_busy, io.wakeup_ports[0].bits.uop.prs2_busy connect issue_slots[11].wakeup_ports[0].bits.uop.prs1_busy, io.wakeup_ports[0].bits.uop.prs1_busy connect issue_slots[11].wakeup_ports[0].bits.uop.ppred, io.wakeup_ports[0].bits.uop.ppred connect issue_slots[11].wakeup_ports[0].bits.uop.prs3, io.wakeup_ports[0].bits.uop.prs3 connect issue_slots[11].wakeup_ports[0].bits.uop.prs2, io.wakeup_ports[0].bits.uop.prs2 connect issue_slots[11].wakeup_ports[0].bits.uop.prs1, io.wakeup_ports[0].bits.uop.prs1 connect issue_slots[11].wakeup_ports[0].bits.uop.pdst, io.wakeup_ports[0].bits.uop.pdst connect issue_slots[11].wakeup_ports[0].bits.uop.rxq_idx, io.wakeup_ports[0].bits.uop.rxq_idx connect issue_slots[11].wakeup_ports[0].bits.uop.stq_idx, io.wakeup_ports[0].bits.uop.stq_idx connect issue_slots[11].wakeup_ports[0].bits.uop.ldq_idx, io.wakeup_ports[0].bits.uop.ldq_idx connect issue_slots[11].wakeup_ports[0].bits.uop.rob_idx, io.wakeup_ports[0].bits.uop.rob_idx connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.vec, io.wakeup_ports[0].bits.uop.fp_ctrl.vec connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wflags, io.wakeup_ports[0].bits.uop.fp_ctrl.wflags connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.div, io.wakeup_ports[0].bits.uop.fp_ctrl.div connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fma, io.wakeup_ports[0].bits.uop.fp_ctrl.fma connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.toint, io.wakeup_ports[0].bits.uop.fp_ctrl.toint connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.fromint, io.wakeup_ports[0].bits.uop.fp_ctrl.fromint connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap23, io.wakeup_ports[0].bits.uop.fp_ctrl.swap23 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.swap12, io.wakeup_ports[0].bits.uop.fp_ctrl.swap12 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren3, io.wakeup_ports[0].bits.uop.fp_ctrl.ren3 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren2, io.wakeup_ports[0].bits.uop.fp_ctrl.ren2 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ren1, io.wakeup_ports[0].bits.uop.fp_ctrl.ren1 connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.wen, io.wakeup_ports[0].bits.uop.fp_ctrl.wen connect issue_slots[11].wakeup_ports[0].bits.uop.fp_ctrl.ldst, io.wakeup_ports[0].bits.uop.fp_ctrl.ldst connect issue_slots[11].wakeup_ports[0].bits.uop.op2_sel, io.wakeup_ports[0].bits.uop.op2_sel connect issue_slots[11].wakeup_ports[0].bits.uop.op1_sel, io.wakeup_ports[0].bits.uop.op1_sel connect issue_slots[11].wakeup_ports[0].bits.uop.imm_packed, io.wakeup_ports[0].bits.uop.imm_packed connect issue_slots[11].wakeup_ports[0].bits.uop.pimm, io.wakeup_ports[0].bits.uop.pimm connect issue_slots[11].wakeup_ports[0].bits.uop.imm_sel, io.wakeup_ports[0].bits.uop.imm_sel connect issue_slots[11].wakeup_ports[0].bits.uop.imm_rename, io.wakeup_ports[0].bits.uop.imm_rename connect issue_slots[11].wakeup_ports[0].bits.uop.taken, io.wakeup_ports[0].bits.uop.taken connect issue_slots[11].wakeup_ports[0].bits.uop.pc_lob, io.wakeup_ports[0].bits.uop.pc_lob connect issue_slots[11].wakeup_ports[0].bits.uop.edge_inst, io.wakeup_ports[0].bits.uop.edge_inst connect issue_slots[11].wakeup_ports[0].bits.uop.ftq_idx, io.wakeup_ports[0].bits.uop.ftq_idx connect issue_slots[11].wakeup_ports[0].bits.uop.is_mov, io.wakeup_ports[0].bits.uop.is_mov connect issue_slots[11].wakeup_ports[0].bits.uop.is_rocc, io.wakeup_ports[0].bits.uop.is_rocc connect issue_slots[11].wakeup_ports[0].bits.uop.is_sys_pc2epc, io.wakeup_ports[0].bits.uop.is_sys_pc2epc connect issue_slots[11].wakeup_ports[0].bits.uop.is_eret, io.wakeup_ports[0].bits.uop.is_eret connect issue_slots[11].wakeup_ports[0].bits.uop.is_amo, io.wakeup_ports[0].bits.uop.is_amo connect issue_slots[11].wakeup_ports[0].bits.uop.is_sfence, io.wakeup_ports[0].bits.uop.is_sfence connect issue_slots[11].wakeup_ports[0].bits.uop.is_fencei, io.wakeup_ports[0].bits.uop.is_fencei connect issue_slots[11].wakeup_ports[0].bits.uop.is_fence, io.wakeup_ports[0].bits.uop.is_fence connect issue_slots[11].wakeup_ports[0].bits.uop.is_sfb, io.wakeup_ports[0].bits.uop.is_sfb connect issue_slots[11].wakeup_ports[0].bits.uop.br_type, io.wakeup_ports[0].bits.uop.br_type connect issue_slots[11].wakeup_ports[0].bits.uop.br_tag, io.wakeup_ports[0].bits.uop.br_tag connect issue_slots[11].wakeup_ports[0].bits.uop.br_mask, io.wakeup_ports[0].bits.uop.br_mask connect issue_slots[11].wakeup_ports[0].bits.uop.dis_col_sel, io.wakeup_ports[0].bits.uop.dis_col_sel connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p2_speculative_child, io.wakeup_ports[0].bits.uop.iw_p2_speculative_child connect issue_slots[11].wakeup_ports[0].bits.uop.iw_p1_speculative_child, io.wakeup_ports[0].bits.uop.iw_p1_speculative_child connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued_partial_agen, io.wakeup_ports[0].bits.uop.iw_issued_partial_agen connect issue_slots[11].wakeup_ports[0].bits.uop.iw_issued, io.wakeup_ports[0].bits.uop.iw_issued connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[0], io.wakeup_ports[0].bits.uop.fu_code[0] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[1], io.wakeup_ports[0].bits.uop.fu_code[1] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[2], io.wakeup_ports[0].bits.uop.fu_code[2] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[3], io.wakeup_ports[0].bits.uop.fu_code[3] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[4], io.wakeup_ports[0].bits.uop.fu_code[4] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[5], io.wakeup_ports[0].bits.uop.fu_code[5] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[6], io.wakeup_ports[0].bits.uop.fu_code[6] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[7], io.wakeup_ports[0].bits.uop.fu_code[7] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[8], io.wakeup_ports[0].bits.uop.fu_code[8] connect issue_slots[11].wakeup_ports[0].bits.uop.fu_code[9], io.wakeup_ports[0].bits.uop.fu_code[9] connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[0], io.wakeup_ports[0].bits.uop.iq_type[0] connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[1], io.wakeup_ports[0].bits.uop.iq_type[1] connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[2], io.wakeup_ports[0].bits.uop.iq_type[2] connect issue_slots[11].wakeup_ports[0].bits.uop.iq_type[3], io.wakeup_ports[0].bits.uop.iq_type[3] connect issue_slots[11].wakeup_ports[0].bits.uop.debug_pc, io.wakeup_ports[0].bits.uop.debug_pc connect issue_slots[11].wakeup_ports[0].bits.uop.is_rvc, io.wakeup_ports[0].bits.uop.is_rvc connect issue_slots[11].wakeup_ports[0].bits.uop.debug_inst, io.wakeup_ports[0].bits.uop.debug_inst connect issue_slots[11].wakeup_ports[0].bits.uop.inst, io.wakeup_ports[0].bits.uop.inst connect issue_slots[11].wakeup_ports[0].valid, io.wakeup_ports[0].valid connect issue_slots[11].wakeup_ports[1].bits.rebusy, io.wakeup_ports[1].bits.rebusy connect issue_slots[11].wakeup_ports[1].bits.speculative_mask, io.wakeup_ports[1].bits.speculative_mask connect issue_slots[11].wakeup_ports[1].bits.bypassable, io.wakeup_ports[1].bits.bypassable connect issue_slots[11].wakeup_ports[1].bits.uop.debug_tsrc, io.wakeup_ports[1].bits.uop.debug_tsrc connect issue_slots[11].wakeup_ports[1].bits.uop.debug_fsrc, io.wakeup_ports[1].bits.uop.debug_fsrc connect issue_slots[11].wakeup_ports[1].bits.uop.bp_xcpt_if, io.wakeup_ports[1].bits.uop.bp_xcpt_if connect issue_slots[11].wakeup_ports[1].bits.uop.bp_debug_if, io.wakeup_ports[1].bits.uop.bp_debug_if connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ma_if, io.wakeup_ports[1].bits.uop.xcpt_ma_if connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_ae_if, io.wakeup_ports[1].bits.uop.xcpt_ae_if connect issue_slots[11].wakeup_ports[1].bits.uop.xcpt_pf_if, io.wakeup_ports[1].bits.uop.xcpt_pf_if connect issue_slots[11].wakeup_ports[1].bits.uop.fp_typ, io.wakeup_ports[1].bits.uop.fp_typ connect issue_slots[11].wakeup_ports[1].bits.uop.fp_rm, io.wakeup_ports[1].bits.uop.fp_rm connect issue_slots[11].wakeup_ports[1].bits.uop.fp_val, io.wakeup_ports[1].bits.uop.fp_val connect issue_slots[11].wakeup_ports[1].bits.uop.fcn_op, io.wakeup_ports[1].bits.uop.fcn_op connect issue_slots[11].wakeup_ports[1].bits.uop.fcn_dw, io.wakeup_ports[1].bits.uop.fcn_dw connect issue_slots[11].wakeup_ports[1].bits.uop.frs3_en, io.wakeup_ports[1].bits.uop.frs3_en connect issue_slots[11].wakeup_ports[1].bits.uop.lrs2_rtype, io.wakeup_ports[1].bits.uop.lrs2_rtype connect issue_slots[11].wakeup_ports[1].bits.uop.lrs1_rtype, io.wakeup_ports[1].bits.uop.lrs1_rtype connect issue_slots[11].wakeup_ports[1].bits.uop.dst_rtype, io.wakeup_ports[1].bits.uop.dst_rtype connect issue_slots[11].wakeup_ports[1].bits.uop.lrs3, io.wakeup_ports[1].bits.uop.lrs3 connect issue_slots[11].wakeup_ports[1].bits.uop.lrs2, io.wakeup_ports[1].bits.uop.lrs2 connect issue_slots[11].wakeup_ports[1].bits.uop.lrs1, io.wakeup_ports[1].bits.uop.lrs1 connect issue_slots[11].wakeup_ports[1].bits.uop.ldst, io.wakeup_ports[1].bits.uop.ldst connect issue_slots[11].wakeup_ports[1].bits.uop.ldst_is_rs1, io.wakeup_ports[1].bits.uop.ldst_is_rs1 connect issue_slots[11].wakeup_ports[1].bits.uop.csr_cmd, io.wakeup_ports[1].bits.uop.csr_cmd connect issue_slots[11].wakeup_ports[1].bits.uop.flush_on_commit, io.wakeup_ports[1].bits.uop.flush_on_commit connect issue_slots[11].wakeup_ports[1].bits.uop.is_unique, io.wakeup_ports[1].bits.uop.is_unique connect issue_slots[11].wakeup_ports[1].bits.uop.uses_stq, io.wakeup_ports[1].bits.uop.uses_stq connect issue_slots[11].wakeup_ports[1].bits.uop.uses_ldq, io.wakeup_ports[1].bits.uop.uses_ldq connect issue_slots[11].wakeup_ports[1].bits.uop.mem_signed, io.wakeup_ports[1].bits.uop.mem_signed connect issue_slots[11].wakeup_ports[1].bits.uop.mem_size, io.wakeup_ports[1].bits.uop.mem_size connect issue_slots[11].wakeup_ports[1].bits.uop.mem_cmd, io.wakeup_ports[1].bits.uop.mem_cmd connect issue_slots[11].wakeup_ports[1].bits.uop.exc_cause, io.wakeup_ports[1].bits.uop.exc_cause connect issue_slots[11].wakeup_ports[1].bits.uop.exception, io.wakeup_ports[1].bits.uop.exception connect issue_slots[11].wakeup_ports[1].bits.uop.stale_pdst, io.wakeup_ports[1].bits.uop.stale_pdst connect issue_slots[11].wakeup_ports[1].bits.uop.ppred_busy, io.wakeup_ports[1].bits.uop.ppred_busy connect issue_slots[11].wakeup_ports[1].bits.uop.prs3_busy, io.wakeup_ports[1].bits.uop.prs3_busy connect issue_slots[11].wakeup_ports[1].bits.uop.prs2_busy, io.wakeup_ports[1].bits.uop.prs2_busy connect issue_slots[11].wakeup_ports[1].bits.uop.prs1_busy, io.wakeup_ports[1].bits.uop.prs1_busy connect issue_slots[11].wakeup_ports[1].bits.uop.ppred, io.wakeup_ports[1].bits.uop.ppred connect issue_slots[11].wakeup_ports[1].bits.uop.prs3, io.wakeup_ports[1].bits.uop.prs3 connect issue_slots[11].wakeup_ports[1].bits.uop.prs2, io.wakeup_ports[1].bits.uop.prs2 connect issue_slots[11].wakeup_ports[1].bits.uop.prs1, io.wakeup_ports[1].bits.uop.prs1 connect issue_slots[11].wakeup_ports[1].bits.uop.pdst, io.wakeup_ports[1].bits.uop.pdst connect issue_slots[11].wakeup_ports[1].bits.uop.rxq_idx, io.wakeup_ports[1].bits.uop.rxq_idx connect issue_slots[11].wakeup_ports[1].bits.uop.stq_idx, io.wakeup_ports[1].bits.uop.stq_idx connect issue_slots[11].wakeup_ports[1].bits.uop.ldq_idx, io.wakeup_ports[1].bits.uop.ldq_idx connect issue_slots[11].wakeup_ports[1].bits.uop.rob_idx, io.wakeup_ports[1].bits.uop.rob_idx connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.vec, io.wakeup_ports[1].bits.uop.fp_ctrl.vec connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wflags, io.wakeup_ports[1].bits.uop.fp_ctrl.wflags connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.sqrt, io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.div, io.wakeup_ports[1].bits.uop.fp_ctrl.div connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fma, io.wakeup_ports[1].bits.uop.fp_ctrl.fma connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.toint, io.wakeup_ports[1].bits.uop.fp_ctrl.toint connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.fromint, io.wakeup_ports[1].bits.uop.fp_ctrl.fromint connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap23, io.wakeup_ports[1].bits.uop.fp_ctrl.swap23 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.swap12, io.wakeup_ports[1].bits.uop.fp_ctrl.swap12 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren3, io.wakeup_ports[1].bits.uop.fp_ctrl.ren3 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren2, io.wakeup_ports[1].bits.uop.fp_ctrl.ren2 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ren1, io.wakeup_ports[1].bits.uop.fp_ctrl.ren1 connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.wen, io.wakeup_ports[1].bits.uop.fp_ctrl.wen connect issue_slots[11].wakeup_ports[1].bits.uop.fp_ctrl.ldst, io.wakeup_ports[1].bits.uop.fp_ctrl.ldst connect issue_slots[11].wakeup_ports[1].bits.uop.op2_sel, io.wakeup_ports[1].bits.uop.op2_sel connect issue_slots[11].wakeup_ports[1].bits.uop.op1_sel, io.wakeup_ports[1].bits.uop.op1_sel connect issue_slots[11].wakeup_ports[1].bits.uop.imm_packed, io.wakeup_ports[1].bits.uop.imm_packed connect issue_slots[11].wakeup_ports[1].bits.uop.pimm, io.wakeup_ports[1].bits.uop.pimm connect issue_slots[11].wakeup_ports[1].bits.uop.imm_sel, io.wakeup_ports[1].bits.uop.imm_sel connect issue_slots[11].wakeup_ports[1].bits.uop.imm_rename, io.wakeup_ports[1].bits.uop.imm_rename connect issue_slots[11].wakeup_ports[1].bits.uop.taken, io.wakeup_ports[1].bits.uop.taken connect issue_slots[11].wakeup_ports[1].bits.uop.pc_lob, io.wakeup_ports[1].bits.uop.pc_lob connect issue_slots[11].wakeup_ports[1].bits.uop.edge_inst, io.wakeup_ports[1].bits.uop.edge_inst connect issue_slots[11].wakeup_ports[1].bits.uop.ftq_idx, io.wakeup_ports[1].bits.uop.ftq_idx connect issue_slots[11].wakeup_ports[1].bits.uop.is_mov, io.wakeup_ports[1].bits.uop.is_mov connect issue_slots[11].wakeup_ports[1].bits.uop.is_rocc, io.wakeup_ports[1].bits.uop.is_rocc connect issue_slots[11].wakeup_ports[1].bits.uop.is_sys_pc2epc, io.wakeup_ports[1].bits.uop.is_sys_pc2epc connect issue_slots[11].wakeup_ports[1].bits.uop.is_eret, io.wakeup_ports[1].bits.uop.is_eret connect issue_slots[11].wakeup_ports[1].bits.uop.is_amo, io.wakeup_ports[1].bits.uop.is_amo connect issue_slots[11].wakeup_ports[1].bits.uop.is_sfence, io.wakeup_ports[1].bits.uop.is_sfence connect issue_slots[11].wakeup_ports[1].bits.uop.is_fencei, io.wakeup_ports[1].bits.uop.is_fencei connect issue_slots[11].wakeup_ports[1].bits.uop.is_fence, io.wakeup_ports[1].bits.uop.is_fence connect issue_slots[11].wakeup_ports[1].bits.uop.is_sfb, io.wakeup_ports[1].bits.uop.is_sfb connect issue_slots[11].wakeup_ports[1].bits.uop.br_type, io.wakeup_ports[1].bits.uop.br_type connect issue_slots[11].wakeup_ports[1].bits.uop.br_tag, io.wakeup_ports[1].bits.uop.br_tag connect issue_slots[11].wakeup_ports[1].bits.uop.br_mask, io.wakeup_ports[1].bits.uop.br_mask connect issue_slots[11].wakeup_ports[1].bits.uop.dis_col_sel, io.wakeup_ports[1].bits.uop.dis_col_sel connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p3_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_bypass_hint, io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p2_speculative_child, io.wakeup_ports[1].bits.uop.iw_p2_speculative_child connect issue_slots[11].wakeup_ports[1].bits.uop.iw_p1_speculative_child, io.wakeup_ports[1].bits.uop.iw_p1_speculative_child connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_dgen, io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued_partial_agen, io.wakeup_ports[1].bits.uop.iw_issued_partial_agen connect issue_slots[11].wakeup_ports[1].bits.uop.iw_issued, io.wakeup_ports[1].bits.uop.iw_issued connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[0], io.wakeup_ports[1].bits.uop.fu_code[0] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[1], io.wakeup_ports[1].bits.uop.fu_code[1] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[2], io.wakeup_ports[1].bits.uop.fu_code[2] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[3], io.wakeup_ports[1].bits.uop.fu_code[3] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[4], io.wakeup_ports[1].bits.uop.fu_code[4] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[5], io.wakeup_ports[1].bits.uop.fu_code[5] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[6], io.wakeup_ports[1].bits.uop.fu_code[6] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[7], io.wakeup_ports[1].bits.uop.fu_code[7] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[8], io.wakeup_ports[1].bits.uop.fu_code[8] connect issue_slots[11].wakeup_ports[1].bits.uop.fu_code[9], io.wakeup_ports[1].bits.uop.fu_code[9] connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[0], io.wakeup_ports[1].bits.uop.iq_type[0] connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[1], io.wakeup_ports[1].bits.uop.iq_type[1] connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[2], io.wakeup_ports[1].bits.uop.iq_type[2] connect issue_slots[11].wakeup_ports[1].bits.uop.iq_type[3], io.wakeup_ports[1].bits.uop.iq_type[3] connect issue_slots[11].wakeup_ports[1].bits.uop.debug_pc, io.wakeup_ports[1].bits.uop.debug_pc connect issue_slots[11].wakeup_ports[1].bits.uop.is_rvc, io.wakeup_ports[1].bits.uop.is_rvc connect issue_slots[11].wakeup_ports[1].bits.uop.debug_inst, io.wakeup_ports[1].bits.uop.debug_inst connect issue_slots[11].wakeup_ports[1].bits.uop.inst, io.wakeup_ports[1].bits.uop.inst connect issue_slots[11].wakeup_ports[1].valid, io.wakeup_ports[1].valid connect issue_slots[11].pred_wakeup_port.bits, io.pred_wakeup_port.bits connect issue_slots[11].pred_wakeup_port.valid, io.pred_wakeup_port.valid connect issue_slots[11].child_rebusys, io.child_rebusys connect issue_slots[11].squash_grant, io.squash_grant connect issue_slots[11].brupdate.b2.target_offset, io.brupdate.b2.target_offset connect issue_slots[11].brupdate.b2.jalr_target, io.brupdate.b2.jalr_target connect issue_slots[11].brupdate.b2.pc_sel, io.brupdate.b2.pc_sel connect issue_slots[11].brupdate.b2.cfi_type, io.brupdate.b2.cfi_type connect issue_slots[11].brupdate.b2.taken, io.brupdate.b2.taken connect issue_slots[11].brupdate.b2.mispredict, io.brupdate.b2.mispredict connect issue_slots[11].brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc connect issue_slots[11].brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc connect issue_slots[11].brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if connect issue_slots[11].brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if connect issue_slots[11].brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if connect issue_slots[11].brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if connect issue_slots[11].brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if connect issue_slots[11].brupdate.b2.uop.fp_typ, io.brupdate.b2.uop.fp_typ connect issue_slots[11].brupdate.b2.uop.fp_rm, io.brupdate.b2.uop.fp_rm connect issue_slots[11].brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val connect issue_slots[11].brupdate.b2.uop.fcn_op, io.brupdate.b2.uop.fcn_op connect issue_slots[11].brupdate.b2.uop.fcn_dw, io.brupdate.b2.uop.fcn_dw connect issue_slots[11].brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en connect issue_slots[11].brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype connect issue_slots[11].brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype connect issue_slots[11].brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype connect issue_slots[11].brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3 connect issue_slots[11].brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2 connect issue_slots[11].brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1 connect issue_slots[11].brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst connect issue_slots[11].brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1 connect issue_slots[11].brupdate.b2.uop.csr_cmd, io.brupdate.b2.uop.csr_cmd connect issue_slots[11].brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit connect issue_slots[11].brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique connect issue_slots[11].brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq connect issue_slots[11].brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq connect issue_slots[11].brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed connect issue_slots[11].brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size connect issue_slots[11].brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd connect issue_slots[11].brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause connect issue_slots[11].brupdate.b2.uop.exception, io.brupdate.b2.uop.exception connect issue_slots[11].brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst connect issue_slots[11].brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy connect issue_slots[11].brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy connect issue_slots[11].brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy connect issue_slots[11].brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy connect issue_slots[11].brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred connect issue_slots[11].brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3 connect issue_slots[11].brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2 connect issue_slots[11].brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1 connect issue_slots[11].brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst connect issue_slots[11].brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx connect issue_slots[11].brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx connect issue_slots[11].brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx connect issue_slots[11].brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx connect issue_slots[11].brupdate.b2.uop.fp_ctrl.vec, io.brupdate.b2.uop.fp_ctrl.vec connect issue_slots[11].brupdate.b2.uop.fp_ctrl.wflags, io.brupdate.b2.uop.fp_ctrl.wflags connect issue_slots[11].brupdate.b2.uop.fp_ctrl.sqrt, io.brupdate.b2.uop.fp_ctrl.sqrt connect issue_slots[11].brupdate.b2.uop.fp_ctrl.div, io.brupdate.b2.uop.fp_ctrl.div connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fma, io.brupdate.b2.uop.fp_ctrl.fma connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fastpipe, io.brupdate.b2.uop.fp_ctrl.fastpipe connect issue_slots[11].brupdate.b2.uop.fp_ctrl.toint, io.brupdate.b2.uop.fp_ctrl.toint connect issue_slots[11].brupdate.b2.uop.fp_ctrl.fromint, io.brupdate.b2.uop.fp_ctrl.fromint connect issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagOut, io.brupdate.b2.uop.fp_ctrl.typeTagOut connect issue_slots[11].brupdate.b2.uop.fp_ctrl.typeTagIn, io.brupdate.b2.uop.fp_ctrl.typeTagIn connect issue_slots[11].brupdate.b2.uop.fp_ctrl.swap23, io.brupdate.b2.uop.fp_ctrl.swap23 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.swap12, io.brupdate.b2.uop.fp_ctrl.swap12 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren3, io.brupdate.b2.uop.fp_ctrl.ren3 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren2, io.brupdate.b2.uop.fp_ctrl.ren2 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ren1, io.brupdate.b2.uop.fp_ctrl.ren1 connect issue_slots[11].brupdate.b2.uop.fp_ctrl.wen, io.brupdate.b2.uop.fp_ctrl.wen connect issue_slots[11].brupdate.b2.uop.fp_ctrl.ldst, io.brupdate.b2.uop.fp_ctrl.ldst connect issue_slots[11].brupdate.b2.uop.op2_sel, io.brupdate.b2.uop.op2_sel connect issue_slots[11].brupdate.b2.uop.op1_sel, io.brupdate.b2.uop.op1_sel connect issue_slots[11].brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed connect issue_slots[11].brupdate.b2.uop.pimm, io.brupdate.b2.uop.pimm connect issue_slots[11].brupdate.b2.uop.imm_sel, io.brupdate.b2.uop.imm_sel connect issue_slots[11].brupdate.b2.uop.imm_rename, io.brupdate.b2.uop.imm_rename connect issue_slots[11].brupdate.b2.uop.taken, io.brupdate.b2.uop.taken connect issue_slots[11].brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob connect issue_slots[11].brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst connect issue_slots[11].brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx connect issue_slots[11].brupdate.b2.uop.is_mov, io.brupdate.b2.uop.is_mov connect issue_slots[11].brupdate.b2.uop.is_rocc, io.brupdate.b2.uop.is_rocc connect issue_slots[11].brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc connect issue_slots[11].brupdate.b2.uop.is_eret, io.brupdate.b2.uop.is_eret connect issue_slots[11].brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo connect issue_slots[11].brupdate.b2.uop.is_sfence, io.brupdate.b2.uop.is_sfence connect issue_slots[11].brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei connect issue_slots[11].brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence connect issue_slots[11].brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb connect issue_slots[11].brupdate.b2.uop.br_type, io.brupdate.b2.uop.br_type connect issue_slots[11].brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag connect issue_slots[11].brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask connect issue_slots[11].brupdate.b2.uop.dis_col_sel, io.brupdate.b2.uop.dis_col_sel connect issue_slots[11].brupdate.b2.uop.iw_p3_bypass_hint, io.brupdate.b2.uop.iw_p3_bypass_hint connect issue_slots[11].brupdate.b2.uop.iw_p2_bypass_hint, io.brupdate.b2.uop.iw_p2_bypass_hint connect issue_slots[11].brupdate.b2.uop.iw_p1_bypass_hint, io.brupdate.b2.uop.iw_p1_bypass_hint connect issue_slots[11].brupdate.b2.uop.iw_p2_speculative_child, io.brupdate.b2.uop.iw_p2_speculative_child connect issue_slots[11].brupdate.b2.uop.iw_p1_speculative_child, io.brupdate.b2.uop.iw_p1_speculative_child connect issue_slots[11].brupdate.b2.uop.iw_issued_partial_dgen, io.brupdate.b2.uop.iw_issued_partial_dgen connect issue_slots[11].brupdate.b2.uop.iw_issued_partial_agen, io.brupdate.b2.uop.iw_issued_partial_agen connect issue_slots[11].brupdate.b2.uop.iw_issued, io.brupdate.b2.uop.iw_issued connect issue_slots[11].brupdate.b2.uop.fu_code[0], io.brupdate.b2.uop.fu_code[0] connect issue_slots[11].brupdate.b2.uop.fu_code[1], io.brupdate.b2.uop.fu_code[1] connect issue_slots[11].brupdate.b2.uop.fu_code[2], io.brupdate.b2.uop.fu_code[2] connect issue_slots[11].brupdate.b2.uop.fu_code[3], io.brupdate.b2.uop.fu_code[3] connect issue_slots[11].brupdate.b2.uop.fu_code[4], io.brupdate.b2.uop.fu_code[4] connect issue_slots[11].brupdate.b2.uop.fu_code[5], io.brupdate.b2.uop.fu_code[5] connect issue_slots[11].brupdate.b2.uop.fu_code[6], io.brupdate.b2.uop.fu_code[6] connect issue_slots[11].brupdate.b2.uop.fu_code[7], io.brupdate.b2.uop.fu_code[7] connect issue_slots[11].brupdate.b2.uop.fu_code[8], io.brupdate.b2.uop.fu_code[8] connect issue_slots[11].brupdate.b2.uop.fu_code[9], io.brupdate.b2.uop.fu_code[9] connect issue_slots[11].brupdate.b2.uop.iq_type[0], io.brupdate.b2.uop.iq_type[0] connect issue_slots[11].brupdate.b2.uop.iq_type[1], io.brupdate.b2.uop.iq_type[1] connect issue_slots[11].brupdate.b2.uop.iq_type[2], io.brupdate.b2.uop.iq_type[2] connect issue_slots[11].brupdate.b2.uop.iq_type[3], io.brupdate.b2.uop.iq_type[3] connect issue_slots[11].brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc connect issue_slots[11].brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc connect issue_slots[11].brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst connect issue_slots[11].brupdate.b2.uop.inst, io.brupdate.b2.uop.inst connect issue_slots[11].brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask connect issue_slots[11].brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask connect issue_slots[11].kill, io.flush_pipeline connect io.iss_uops[0].valid, UInt<1>(0h0) node _T_70 = add(issue_slots[1].grant, issue_slots[2].grant) node _T_71 = bits(_T_70, 1, 0) node _T_72 = add(issue_slots[0].grant, _T_71) node _T_73 = bits(_T_72, 1, 0) node _T_74 = add(issue_slots[4].grant, issue_slots[5].grant) node _T_75 = bits(_T_74, 1, 0) node _T_76 = add(issue_slots[3].grant, _T_75) node _T_77 = bits(_T_76, 1, 0) node _T_78 = add(_T_73, _T_77) node _T_79 = bits(_T_78, 2, 0) node _T_80 = add(issue_slots[7].grant, issue_slots[8].grant) node _T_81 = bits(_T_80, 1, 0) node _T_82 = add(issue_slots[6].grant, _T_81) node _T_83 = bits(_T_82, 1, 0) node _T_84 = add(issue_slots[10].grant, issue_slots[11].grant) node _T_85 = bits(_T_84, 1, 0) node _T_86 = add(issue_slots[9].grant, _T_85) node _T_87 = bits(_T_86, 1, 0) node _T_88 = add(_T_83, _T_87) node _T_89 = bits(_T_88, 2, 0) node _T_90 = add(_T_79, _T_89) node _T_91 = bits(_T_90, 3, 0) node _T_92 = leq(_T_91, UInt<1>(0h1)) node _T_93 = asUInt(reset) node _T_94 = eq(_T_93, UInt<1>(0h0)) when _T_94 : node _T_95 = eq(_T_92, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "Assertion failed: [issue] window giving out too many grants.\n at issue-unit-age-ordered.scala:141 assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, \"[issue] window giving out too many grants.\")\n") : printf_2 assert(clock, _T_92, UInt<1>(0h1), "") : assert_2 node vacants_0 = eq(issue_slots[0].valid, UInt<1>(0h0)) node vacants_1 = eq(issue_slots[1].valid, UInt<1>(0h0)) node vacants_2 = eq(issue_slots[2].valid, UInt<1>(0h0)) node vacants_3 = eq(issue_slots[3].valid, UInt<1>(0h0)) node vacants_4 = eq(issue_slots[4].valid, UInt<1>(0h0)) node vacants_5 = eq(issue_slots[5].valid, UInt<1>(0h0)) node vacants_6 = eq(issue_slots[6].valid, UInt<1>(0h0)) node vacants_7 = eq(issue_slots[7].valid, UInt<1>(0h0)) node vacants_8 = eq(issue_slots[8].valid, UInt<1>(0h0)) node vacants_9 = eq(issue_slots[9].valid, UInt<1>(0h0)) node vacants_10 = eq(issue_slots[10].valid, UInt<1>(0h0)) node vacants_11 = eq(issue_slots[11].valid, UInt<1>(0h0)) node vacants_12 = eq(io.dis_uops[0].valid, UInt<1>(0h0)) node vacants_13 = eq(io.dis_uops[1].valid, UInt<1>(0h0)) wire shamts_oh : UInt<2>[14] connect shamts_oh[0], UInt<1>(0h0) wire shamts_oh_1_next : UInt<2> connect shamts_oh_1_next, shamts_oh[0] node _shamts_oh_1_T = eq(shamts_oh[0], UInt<1>(0h0)) node _shamts_oh_1_T_1 = and(_shamts_oh_1_T, vacants_0) when _shamts_oh_1_T_1 : connect shamts_oh_1_next, UInt<1>(0h1) else : node _shamts_oh_1_T_2 = bits(shamts_oh[0], 1, 1) node _shamts_oh_1_T_3 = eq(_shamts_oh_1_T_2, UInt<1>(0h0)) node _shamts_oh_1_T_4 = and(_shamts_oh_1_T_3, vacants_0) when _shamts_oh_1_T_4 : node _shamts_oh_1_next_T = dshl(shamts_oh[0], UInt<1>(0h1)) connect shamts_oh_1_next, _shamts_oh_1_next_T connect shamts_oh[1], shamts_oh_1_next wire shamts_oh_2_next : UInt<2> connect shamts_oh_2_next, shamts_oh[1] node _shamts_oh_2_T = eq(shamts_oh[1], UInt<1>(0h0)) node _shamts_oh_2_T_1 = and(_shamts_oh_2_T, vacants_1) when _shamts_oh_2_T_1 : connect shamts_oh_2_next, UInt<1>(0h1) else : node _shamts_oh_2_T_2 = bits(shamts_oh[1], 1, 1) node _shamts_oh_2_T_3 = eq(_shamts_oh_2_T_2, UInt<1>(0h0)) node _shamts_oh_2_T_4 = and(_shamts_oh_2_T_3, vacants_1) when _shamts_oh_2_T_4 : node _shamts_oh_2_next_T = dshl(shamts_oh[1], UInt<1>(0h1)) connect shamts_oh_2_next, _shamts_oh_2_next_T connect shamts_oh[2], shamts_oh_2_next wire shamts_oh_3_next : UInt<2> connect shamts_oh_3_next, shamts_oh[2] node _shamts_oh_3_T = eq(shamts_oh[2], UInt<1>(0h0)) node _shamts_oh_3_T_1 = and(_shamts_oh_3_T, vacants_2) when _shamts_oh_3_T_1 : connect shamts_oh_3_next, UInt<1>(0h1) else : node _shamts_oh_3_T_2 = bits(shamts_oh[2], 1, 1) node _shamts_oh_3_T_3 = eq(_shamts_oh_3_T_2, UInt<1>(0h0)) node _shamts_oh_3_T_4 = and(_shamts_oh_3_T_3, vacants_2) when _shamts_oh_3_T_4 : node _shamts_oh_3_next_T = dshl(shamts_oh[2], UInt<1>(0h1)) connect shamts_oh_3_next, _shamts_oh_3_next_T connect shamts_oh[3], shamts_oh_3_next wire shamts_oh_4_next : UInt<2> connect shamts_oh_4_next, shamts_oh[3] node _shamts_oh_4_T = eq(shamts_oh[3], UInt<1>(0h0)) node _shamts_oh_4_T_1 = and(_shamts_oh_4_T, vacants_3) when _shamts_oh_4_T_1 : connect shamts_oh_4_next, UInt<1>(0h1) else : node _shamts_oh_4_T_2 = bits(shamts_oh[3], 1, 1) node _shamts_oh_4_T_3 = eq(_shamts_oh_4_T_2, UInt<1>(0h0)) node _shamts_oh_4_T_4 = and(_shamts_oh_4_T_3, vacants_3) when _shamts_oh_4_T_4 : node _shamts_oh_4_next_T = dshl(shamts_oh[3], UInt<1>(0h1)) connect shamts_oh_4_next, _shamts_oh_4_next_T connect shamts_oh[4], shamts_oh_4_next wire shamts_oh_5_next : UInt<2> connect shamts_oh_5_next, shamts_oh[4] node _shamts_oh_5_T = eq(shamts_oh[4], UInt<1>(0h0)) node _shamts_oh_5_T_1 = and(_shamts_oh_5_T, vacants_4) when _shamts_oh_5_T_1 : connect shamts_oh_5_next, UInt<1>(0h1) else : node _shamts_oh_5_T_2 = bits(shamts_oh[4], 1, 1) node _shamts_oh_5_T_3 = eq(_shamts_oh_5_T_2, UInt<1>(0h0)) node _shamts_oh_5_T_4 = and(_shamts_oh_5_T_3, vacants_4) when _shamts_oh_5_T_4 : node _shamts_oh_5_next_T = dshl(shamts_oh[4], UInt<1>(0h1)) connect shamts_oh_5_next, _shamts_oh_5_next_T connect shamts_oh[5], shamts_oh_5_next wire shamts_oh_6_next : UInt<2> connect shamts_oh_6_next, shamts_oh[5] node _shamts_oh_6_T = eq(shamts_oh[5], UInt<1>(0h0)) node _shamts_oh_6_T_1 = and(_shamts_oh_6_T, vacants_5) when _shamts_oh_6_T_1 : connect shamts_oh_6_next, UInt<1>(0h1) else : node _shamts_oh_6_T_2 = bits(shamts_oh[5], 1, 1) node _shamts_oh_6_T_3 = eq(_shamts_oh_6_T_2, UInt<1>(0h0)) node _shamts_oh_6_T_4 = and(_shamts_oh_6_T_3, vacants_5) when _shamts_oh_6_T_4 : node _shamts_oh_6_next_T = dshl(shamts_oh[5], UInt<1>(0h1)) connect shamts_oh_6_next, _shamts_oh_6_next_T connect shamts_oh[6], shamts_oh_6_next wire shamts_oh_7_next : UInt<2> connect shamts_oh_7_next, shamts_oh[6] node _shamts_oh_7_T = eq(shamts_oh[6], UInt<1>(0h0)) node _shamts_oh_7_T_1 = and(_shamts_oh_7_T, vacants_6) when _shamts_oh_7_T_1 : connect shamts_oh_7_next, UInt<1>(0h1) else : node _shamts_oh_7_T_2 = bits(shamts_oh[6], 1, 1) node _shamts_oh_7_T_3 = eq(_shamts_oh_7_T_2, UInt<1>(0h0)) node _shamts_oh_7_T_4 = and(_shamts_oh_7_T_3, vacants_6) when _shamts_oh_7_T_4 : node _shamts_oh_7_next_T = dshl(shamts_oh[6], UInt<1>(0h1)) connect shamts_oh_7_next, _shamts_oh_7_next_T connect shamts_oh[7], shamts_oh_7_next wire shamts_oh_8_next : UInt<2> connect shamts_oh_8_next, shamts_oh[7] node _shamts_oh_8_T = eq(shamts_oh[7], UInt<1>(0h0)) node _shamts_oh_8_T_1 = and(_shamts_oh_8_T, vacants_7) when _shamts_oh_8_T_1 : connect shamts_oh_8_next, UInt<1>(0h1) else : node _shamts_oh_8_T_2 = bits(shamts_oh[7], 1, 1) node _shamts_oh_8_T_3 = eq(_shamts_oh_8_T_2, UInt<1>(0h0)) node _shamts_oh_8_T_4 = and(_shamts_oh_8_T_3, vacants_7) when _shamts_oh_8_T_4 : node _shamts_oh_8_next_T = dshl(shamts_oh[7], UInt<1>(0h1)) connect shamts_oh_8_next, _shamts_oh_8_next_T connect shamts_oh[8], shamts_oh_8_next wire shamts_oh_9_next : UInt<2> connect shamts_oh_9_next, shamts_oh[8] node _shamts_oh_9_T = eq(shamts_oh[8], UInt<1>(0h0)) node _shamts_oh_9_T_1 = and(_shamts_oh_9_T, vacants_8) when _shamts_oh_9_T_1 : connect shamts_oh_9_next, UInt<1>(0h1) else : node _shamts_oh_9_T_2 = bits(shamts_oh[8], 1, 1) node _shamts_oh_9_T_3 = eq(_shamts_oh_9_T_2, UInt<1>(0h0)) node _shamts_oh_9_T_4 = and(_shamts_oh_9_T_3, vacants_8) when _shamts_oh_9_T_4 : node _shamts_oh_9_next_T = dshl(shamts_oh[8], UInt<1>(0h1)) connect shamts_oh_9_next, _shamts_oh_9_next_T connect shamts_oh[9], shamts_oh_9_next wire shamts_oh_10_next : UInt<2> connect shamts_oh_10_next, shamts_oh[9] node _shamts_oh_10_T = eq(shamts_oh[9], UInt<1>(0h0)) node _shamts_oh_10_T_1 = and(_shamts_oh_10_T, vacants_9) when _shamts_oh_10_T_1 : connect shamts_oh_10_next, UInt<1>(0h1) else : node _shamts_oh_10_T_2 = bits(shamts_oh[9], 1, 1) node _shamts_oh_10_T_3 = eq(_shamts_oh_10_T_2, UInt<1>(0h0)) node _shamts_oh_10_T_4 = and(_shamts_oh_10_T_3, vacants_9) when _shamts_oh_10_T_4 : node _shamts_oh_10_next_T = dshl(shamts_oh[9], UInt<1>(0h1)) connect shamts_oh_10_next, _shamts_oh_10_next_T connect shamts_oh[10], shamts_oh_10_next wire shamts_oh_11_next : UInt<2> connect shamts_oh_11_next, shamts_oh[10] node _shamts_oh_11_T = eq(shamts_oh[10], UInt<1>(0h0)) node _shamts_oh_11_T_1 = and(_shamts_oh_11_T, vacants_10) when _shamts_oh_11_T_1 : connect shamts_oh_11_next, UInt<1>(0h1) else : node _shamts_oh_11_T_2 = bits(shamts_oh[10], 1, 1) node _shamts_oh_11_T_3 = eq(_shamts_oh_11_T_2, UInt<1>(0h0)) node _shamts_oh_11_T_4 = and(_shamts_oh_11_T_3, vacants_10) when _shamts_oh_11_T_4 : node _shamts_oh_11_next_T = dshl(shamts_oh[10], UInt<1>(0h1)) connect shamts_oh_11_next, _shamts_oh_11_next_T connect shamts_oh[11], shamts_oh_11_next wire shamts_oh_12_next : UInt<2> connect shamts_oh_12_next, shamts_oh[11] node _shamts_oh_12_T = eq(shamts_oh[11], UInt<1>(0h0)) node _shamts_oh_12_T_1 = and(_shamts_oh_12_T, vacants_11) when _shamts_oh_12_T_1 : connect shamts_oh_12_next, UInt<1>(0h1) else : node _shamts_oh_12_T_2 = bits(shamts_oh[11], 1, 1) node _shamts_oh_12_T_3 = eq(_shamts_oh_12_T_2, UInt<1>(0h0)) node _shamts_oh_12_T_4 = and(_shamts_oh_12_T_3, vacants_11) when _shamts_oh_12_T_4 : node _shamts_oh_12_next_T = dshl(shamts_oh[11], UInt<1>(0h1)) connect shamts_oh_12_next, _shamts_oh_12_next_T connect shamts_oh[12], shamts_oh_12_next wire shamts_oh_13_next : UInt<2> connect shamts_oh_13_next, shamts_oh[12] node _shamts_oh_13_T = eq(shamts_oh[12], UInt<1>(0h0)) node _shamts_oh_13_T_1 = and(_shamts_oh_13_T, vacants_12) when _shamts_oh_13_T_1 : connect shamts_oh_13_next, UInt<1>(0h1) else : node _shamts_oh_13_T_2 = bits(shamts_oh[12], 1, 1) node _shamts_oh_13_T_3 = eq(_shamts_oh_13_T_2, UInt<1>(0h0)) node _shamts_oh_13_T_4 = and(_shamts_oh_13_T_3, vacants_12) when _shamts_oh_13_T_4 : node _shamts_oh_13_next_T = dshl(shamts_oh[12], UInt<1>(0h1)) connect shamts_oh_13_next, _shamts_oh_13_next_T connect shamts_oh[13], shamts_oh_13_next node _will_be_valid_T = eq(_WIRE.exception, UInt<1>(0h0)) node _will_be_valid_T_1 = and(io.dis_uops[0].valid, _will_be_valid_T) node _will_be_valid_T_2 = eq(_WIRE.is_fence, UInt<1>(0h0)) node _will_be_valid_T_3 = and(_will_be_valid_T_1, _will_be_valid_T_2) node _will_be_valid_T_4 = eq(_WIRE.is_fencei, UInt<1>(0h0)) node will_be_valid_12 = and(_will_be_valid_T_3, _will_be_valid_T_4) node _will_be_valid_T_5 = eq(_WIRE_1.exception, UInt<1>(0h0)) node _will_be_valid_T_6 = and(io.dis_uops[1].valid, _will_be_valid_T_5) node _will_be_valid_T_7 = eq(_WIRE_1.is_fence, UInt<1>(0h0)) node _will_be_valid_T_8 = and(_will_be_valid_T_6, _will_be_valid_T_7) node _will_be_valid_T_9 = eq(_WIRE_1.is_fencei, UInt<1>(0h0)) node will_be_valid_13 = and(_will_be_valid_T_8, _will_be_valid_T_9) connect issue_slots[0].in_uop.valid, UInt<1>(0h0) connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[1].out_uop.fp_typ connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[1].out_uop.fp_rm connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[1].out_uop.fcn_op connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[1].out_uop.fcn_dw connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[1].out_uop.csr_cmd connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[1].out_uop.fp_ctrl.vec connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[1].out_uop.fp_ctrl.wflags connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[1].out_uop.fp_ctrl.sqrt connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[1].out_uop.fp_ctrl.div connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[1].out_uop.fp_ctrl.fma connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].out_uop.fp_ctrl.fastpipe connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[1].out_uop.fp_ctrl.toint connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[1].out_uop.fp_ctrl.fromint connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].out_uop.fp_ctrl.typeTagOut connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].out_uop.fp_ctrl.typeTagIn connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[1].out_uop.fp_ctrl.swap23 connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[1].out_uop.fp_ctrl.swap12 connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[1].out_uop.fp_ctrl.ren3 connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[1].out_uop.fp_ctrl.ren2 connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[1].out_uop.fp_ctrl.ren1 connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[1].out_uop.fp_ctrl.wen connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[1].out_uop.fp_ctrl.ldst connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[1].out_uop.op2_sel connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[1].out_uop.op1_sel connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed connect issue_slots[0].in_uop.bits.pimm, issue_slots[1].out_uop.pimm connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[1].out_uop.imm_sel connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[1].out_uop.imm_rename connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.is_mov, issue_slots[1].out_uop.is_mov connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[1].out_uop.is_rocc connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.is_eret, issue_slots[1].out_uop.is_eret connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[1].out_uop.is_sfence connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb connect issue_slots[0].in_uop.bits.br_type, issue_slots[1].out_uop.br_type connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[1].out_uop.dis_col_sel connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[1].out_uop.iw_p3_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[1].out_uop.iw_p2_bypass_hint connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[1].out_uop.iw_p1_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[1].out_uop.iw_p2_speculative_child connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[1].out_uop.iw_p1_speculative_child connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[1].out_uop.iw_issued_partial_dgen connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[1].out_uop.iw_issued_partial_agen connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[1].out_uop.iw_issued connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[1].out_uop.fu_code[0] connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[1].out_uop.fu_code[1] connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[1].out_uop.fu_code[2] connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[1].out_uop.fu_code[3] connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[1].out_uop.fu_code[4] connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[1].out_uop.fu_code[5] connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[1].out_uop.fu_code[6] connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[1].out_uop.fu_code[7] connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[1].out_uop.fu_code[8] connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[1].out_uop.fu_code[9] connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[1].out_uop.iq_type[0] connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[1].out_uop.iq_type[1] connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[1].out_uop.iq_type[2] connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[1].out_uop.iq_type[3] connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst node _T_96 = eq(shamts_oh[1], UInt<1>(0h1)) when _T_96 : connect issue_slots[0].in_uop.valid, issue_slots[1].will_be_valid connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[1].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[1].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[1].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[1].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[1].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[1].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[1].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[1].out_uop.fp_typ connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[1].out_uop.fp_rm connect issue_slots[0].in_uop.bits.fp_val, issue_slots[1].out_uop.fp_val connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[1].out_uop.fcn_op connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[1].out_uop.fcn_dw connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[1].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[1].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[1].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[1].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.lrs3, issue_slots[1].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[1].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[1].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[1].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[1].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[1].out_uop.csr_cmd connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[1].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[1].out_uop.is_unique connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[1].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[1].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[1].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[1].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[1].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[1].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[1].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[1].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[1].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[1].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[1].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[1].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[1].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[1].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[1].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[1].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[1].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[1].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[1].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[1].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[1].out_uop.rob_idx connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[1].out_uop.fp_ctrl.vec connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[1].out_uop.fp_ctrl.wflags connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[1].out_uop.fp_ctrl.sqrt connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[1].out_uop.fp_ctrl.div connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[1].out_uop.fp_ctrl.fma connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[1].out_uop.fp_ctrl.fastpipe connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[1].out_uop.fp_ctrl.toint connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[1].out_uop.fp_ctrl.fromint connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[1].out_uop.fp_ctrl.typeTagOut connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[1].out_uop.fp_ctrl.typeTagIn connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[1].out_uop.fp_ctrl.swap23 connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[1].out_uop.fp_ctrl.swap12 connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[1].out_uop.fp_ctrl.ren3 connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[1].out_uop.fp_ctrl.ren2 connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[1].out_uop.fp_ctrl.ren1 connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[1].out_uop.fp_ctrl.wen connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[1].out_uop.fp_ctrl.ldst connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[1].out_uop.op2_sel connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[1].out_uop.op1_sel connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[1].out_uop.imm_packed connect issue_slots[0].in_uop.bits.pimm, issue_slots[1].out_uop.pimm connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[1].out_uop.imm_sel connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[1].out_uop.imm_rename connect issue_slots[0].in_uop.bits.taken, issue_slots[1].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[1].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[1].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[1].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.is_mov, issue_slots[1].out_uop.is_mov connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[1].out_uop.is_rocc connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[1].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.is_eret, issue_slots[1].out_uop.is_eret connect issue_slots[0].in_uop.bits.is_amo, issue_slots[1].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[1].out_uop.is_sfence connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[1].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[1].out_uop.is_fence connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[1].out_uop.is_sfb connect issue_slots[0].in_uop.bits.br_type, issue_slots[1].out_uop.br_type connect issue_slots[0].in_uop.bits.br_tag, issue_slots[1].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[1].out_uop.br_mask connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[1].out_uop.dis_col_sel connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[1].out_uop.iw_p3_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[1].out_uop.iw_p2_bypass_hint connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[1].out_uop.iw_p1_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[1].out_uop.iw_p2_speculative_child connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[1].out_uop.iw_p1_speculative_child connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[1].out_uop.iw_issued_partial_dgen connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[1].out_uop.iw_issued_partial_agen connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[1].out_uop.iw_issued connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[1].out_uop.fu_code[0] connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[1].out_uop.fu_code[1] connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[1].out_uop.fu_code[2] connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[1].out_uop.fu_code[3] connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[1].out_uop.fu_code[4] connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[1].out_uop.fu_code[5] connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[1].out_uop.fu_code[6] connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[1].out_uop.fu_code[7] connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[1].out_uop.fu_code[8] connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[1].out_uop.fu_code[9] connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[1].out_uop.iq_type[0] connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[1].out_uop.iq_type[1] connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[1].out_uop.iq_type[2] connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[1].out_uop.iq_type[3] connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[1].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[1].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[1].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[1].out_uop.inst node _T_97 = eq(shamts_oh[2], UInt<2>(0h2)) when _T_97 : connect issue_slots[0].in_uop.valid, issue_slots[2].will_be_valid connect issue_slots[0].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[0].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[0].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[0].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[0].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[0].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[0].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[0].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ connect issue_slots[0].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm connect issue_slots[0].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[0].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op connect issue_slots[0].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw connect issue_slots[0].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[0].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[0].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[0].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[0].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[0].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[0].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[0].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[0].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[0].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd connect issue_slots[0].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[0].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[0].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[0].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[0].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[0].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[0].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[0].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[0].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[0].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[0].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[0].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[0].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[0].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[0].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[0].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[0].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[0].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[0].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[0].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[0].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[0].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[0].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[0].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec connect issue_slots[0].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags connect issue_slots[0].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt connect issue_slots[0].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div connect issue_slots[0].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma connect issue_slots[0].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe connect issue_slots[0].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint connect issue_slots[0].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut connect issue_slots[0].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn connect issue_slots[0].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23 connect issue_slots[0].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12 connect issue_slots[0].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3 connect issue_slots[0].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2 connect issue_slots[0].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1 connect issue_slots[0].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen connect issue_slots[0].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst connect issue_slots[0].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel connect issue_slots[0].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel connect issue_slots[0].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[0].in_uop.bits.pimm, issue_slots[2].out_uop.pimm connect issue_slots[0].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel connect issue_slots[0].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename connect issue_slots[0].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[0].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[0].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[0].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[0].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov connect issue_slots[0].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc connect issue_slots[0].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[0].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret connect issue_slots[0].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[0].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence connect issue_slots[0].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[0].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[0].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[0].in_uop.bits.br_type, issue_slots[2].out_uop.br_type connect issue_slots[0].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[0].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[0].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel connect issue_slots[0].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint connect issue_slots[0].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint connect issue_slots[0].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child connect issue_slots[0].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child connect issue_slots[0].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen connect issue_slots[0].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen connect issue_slots[0].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued connect issue_slots[0].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0] connect issue_slots[0].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1] connect issue_slots[0].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2] connect issue_slots[0].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3] connect issue_slots[0].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4] connect issue_slots[0].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5] connect issue_slots[0].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6] connect issue_slots[0].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7] connect issue_slots[0].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8] connect issue_slots[0].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9] connect issue_slots[0].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0] connect issue_slots[0].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1] connect issue_slots[0].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2] connect issue_slots[0].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3] connect issue_slots[0].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[0].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[0].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[0].in_uop.bits.inst, issue_slots[2].out_uop.inst node _issue_slots_0_clear_T = neq(shamts_oh[0], UInt<1>(0h0)) connect issue_slots[0].clear, _issue_slots_0_clear_T connect issue_slots[1].in_uop.valid, UInt<1>(0h0) connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23 connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12 connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3 connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2 connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1 connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[1].in_uop.bits.pimm, issue_slots[2].out_uop.pimm connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[1].in_uop.bits.br_type, issue_slots[2].out_uop.br_type connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0] connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1] connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2] connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3] connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4] connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5] connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6] connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7] connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8] connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9] connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0] connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1] connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2] connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3] connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst node _T_98 = eq(shamts_oh[2], UInt<1>(0h1)) when _T_98 : connect issue_slots[1].in_uop.valid, issue_slots[2].will_be_valid connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[2].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[2].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[2].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[2].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[2].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[2].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[2].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[2].out_uop.fp_typ connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[2].out_uop.fp_rm connect issue_slots[1].in_uop.bits.fp_val, issue_slots[2].out_uop.fp_val connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[2].out_uop.fcn_op connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[2].out_uop.fcn_dw connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[2].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[2].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[2].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[2].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.lrs3, issue_slots[2].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[2].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[2].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[2].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[2].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[2].out_uop.csr_cmd connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[2].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[2].out_uop.is_unique connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[2].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[2].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[2].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[2].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[2].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[2].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[2].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[2].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[2].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[2].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[2].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[2].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[2].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[2].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[2].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[2].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[2].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[2].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[2].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[2].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[2].out_uop.rob_idx connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[2].out_uop.fp_ctrl.vec connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[2].out_uop.fp_ctrl.wflags connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[2].out_uop.fp_ctrl.sqrt connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[2].out_uop.fp_ctrl.div connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[2].out_uop.fp_ctrl.fma connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[2].out_uop.fp_ctrl.fastpipe connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[2].out_uop.fp_ctrl.toint connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[2].out_uop.fp_ctrl.fromint connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[2].out_uop.fp_ctrl.typeTagOut connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[2].out_uop.fp_ctrl.typeTagIn connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[2].out_uop.fp_ctrl.swap23 connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[2].out_uop.fp_ctrl.swap12 connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[2].out_uop.fp_ctrl.ren3 connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[2].out_uop.fp_ctrl.ren2 connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[2].out_uop.fp_ctrl.ren1 connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[2].out_uop.fp_ctrl.wen connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[2].out_uop.fp_ctrl.ldst connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[2].out_uop.op2_sel connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[2].out_uop.op1_sel connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[2].out_uop.imm_packed connect issue_slots[1].in_uop.bits.pimm, issue_slots[2].out_uop.pimm connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[2].out_uop.imm_sel connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[2].out_uop.imm_rename connect issue_slots[1].in_uop.bits.taken, issue_slots[2].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[2].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[2].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[2].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.is_mov, issue_slots[2].out_uop.is_mov connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[2].out_uop.is_rocc connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[2].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.is_eret, issue_slots[2].out_uop.is_eret connect issue_slots[1].in_uop.bits.is_amo, issue_slots[2].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[2].out_uop.is_sfence connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[2].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[2].out_uop.is_fence connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[2].out_uop.is_sfb connect issue_slots[1].in_uop.bits.br_type, issue_slots[2].out_uop.br_type connect issue_slots[1].in_uop.bits.br_tag, issue_slots[2].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[2].out_uop.br_mask connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[2].out_uop.dis_col_sel connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[2].out_uop.iw_p3_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[2].out_uop.iw_p2_bypass_hint connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[2].out_uop.iw_p1_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[2].out_uop.iw_p2_speculative_child connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[2].out_uop.iw_p1_speculative_child connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[2].out_uop.iw_issued_partial_dgen connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[2].out_uop.iw_issued_partial_agen connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[2].out_uop.iw_issued connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[2].out_uop.fu_code[0] connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[2].out_uop.fu_code[1] connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[2].out_uop.fu_code[2] connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[2].out_uop.fu_code[3] connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[2].out_uop.fu_code[4] connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[2].out_uop.fu_code[5] connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[2].out_uop.fu_code[6] connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[2].out_uop.fu_code[7] connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[2].out_uop.fu_code[8] connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[2].out_uop.fu_code[9] connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[2].out_uop.iq_type[0] connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[2].out_uop.iq_type[1] connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[2].out_uop.iq_type[2] connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[2].out_uop.iq_type[3] connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[2].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[2].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[2].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[2].out_uop.inst node _T_99 = eq(shamts_oh[3], UInt<2>(0h2)) when _T_99 : connect issue_slots[1].in_uop.valid, issue_slots[3].will_be_valid connect issue_slots[1].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[1].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[1].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[1].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[1].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[1].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[1].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[1].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ connect issue_slots[1].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm connect issue_slots[1].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[1].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op connect issue_slots[1].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw connect issue_slots[1].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[1].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[1].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[1].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[1].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[1].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[1].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[1].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[1].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[1].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd connect issue_slots[1].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[1].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[1].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[1].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[1].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[1].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[1].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[1].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[1].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[1].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[1].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[1].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[1].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[1].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[1].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[1].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[1].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[1].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[1].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[1].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[1].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[1].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[1].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[1].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec connect issue_slots[1].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags connect issue_slots[1].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt connect issue_slots[1].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div connect issue_slots[1].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma connect issue_slots[1].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe connect issue_slots[1].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint connect issue_slots[1].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut connect issue_slots[1].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn connect issue_slots[1].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 connect issue_slots[1].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 connect issue_slots[1].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 connect issue_slots[1].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 connect issue_slots[1].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 connect issue_slots[1].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen connect issue_slots[1].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst connect issue_slots[1].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel connect issue_slots[1].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel connect issue_slots[1].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[1].in_uop.bits.pimm, issue_slots[3].out_uop.pimm connect issue_slots[1].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel connect issue_slots[1].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename connect issue_slots[1].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[1].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[1].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[1].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[1].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov connect issue_slots[1].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc connect issue_slots[1].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[1].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret connect issue_slots[1].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[1].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence connect issue_slots[1].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[1].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[1].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[1].in_uop.bits.br_type, issue_slots[3].out_uop.br_type connect issue_slots[1].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[1].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[1].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel connect issue_slots[1].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint connect issue_slots[1].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint connect issue_slots[1].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child connect issue_slots[1].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child connect issue_slots[1].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen connect issue_slots[1].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen connect issue_slots[1].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued connect issue_slots[1].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] connect issue_slots[1].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] connect issue_slots[1].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] connect issue_slots[1].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] connect issue_slots[1].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] connect issue_slots[1].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] connect issue_slots[1].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] connect issue_slots[1].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] connect issue_slots[1].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] connect issue_slots[1].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] connect issue_slots[1].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] connect issue_slots[1].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] connect issue_slots[1].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] connect issue_slots[1].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] connect issue_slots[1].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[1].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[1].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[1].in_uop.bits.inst, issue_slots[3].out_uop.inst node _issue_slots_1_clear_T = neq(shamts_oh[1], UInt<1>(0h0)) connect issue_slots[1].clear, _issue_slots_1_clear_T connect issue_slots[2].in_uop.valid, UInt<1>(0h0) connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[2].in_uop.bits.pimm, issue_slots[3].out_uop.pimm connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[2].in_uop.bits.br_type, issue_slots[3].out_uop.br_type connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst node _T_100 = eq(shamts_oh[3], UInt<1>(0h1)) when _T_100 : connect issue_slots[2].in_uop.valid, issue_slots[3].will_be_valid connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[3].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[3].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[3].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[3].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[3].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[3].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[3].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[3].out_uop.fp_typ connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[3].out_uop.fp_rm connect issue_slots[2].in_uop.bits.fp_val, issue_slots[3].out_uop.fp_val connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[3].out_uop.fcn_op connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[3].out_uop.fcn_dw connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[3].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[3].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[3].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[3].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.lrs3, issue_slots[3].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[3].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[3].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[3].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[3].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[3].out_uop.csr_cmd connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[3].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[3].out_uop.is_unique connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[3].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[3].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[3].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[3].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[3].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[3].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[3].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[3].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[3].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[3].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[3].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[3].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[3].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[3].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[3].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[3].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[3].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[3].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[3].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[3].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[3].out_uop.rob_idx connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[3].out_uop.fp_ctrl.vec connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[3].out_uop.fp_ctrl.wflags connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[3].out_uop.fp_ctrl.sqrt connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[3].out_uop.fp_ctrl.div connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[3].out_uop.fp_ctrl.fma connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[3].out_uop.fp_ctrl.fastpipe connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[3].out_uop.fp_ctrl.toint connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[3].out_uop.fp_ctrl.fromint connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[3].out_uop.fp_ctrl.typeTagOut connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[3].out_uop.fp_ctrl.typeTagIn connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[3].out_uop.fp_ctrl.swap23 connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[3].out_uop.fp_ctrl.swap12 connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[3].out_uop.fp_ctrl.ren3 connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[3].out_uop.fp_ctrl.ren2 connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[3].out_uop.fp_ctrl.ren1 connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[3].out_uop.fp_ctrl.wen connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[3].out_uop.fp_ctrl.ldst connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[3].out_uop.op2_sel connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[3].out_uop.op1_sel connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[3].out_uop.imm_packed connect issue_slots[2].in_uop.bits.pimm, issue_slots[3].out_uop.pimm connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[3].out_uop.imm_sel connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[3].out_uop.imm_rename connect issue_slots[2].in_uop.bits.taken, issue_slots[3].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[3].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[3].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[3].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.is_mov, issue_slots[3].out_uop.is_mov connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[3].out_uop.is_rocc connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[3].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.is_eret, issue_slots[3].out_uop.is_eret connect issue_slots[2].in_uop.bits.is_amo, issue_slots[3].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[3].out_uop.is_sfence connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[3].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[3].out_uop.is_fence connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[3].out_uop.is_sfb connect issue_slots[2].in_uop.bits.br_type, issue_slots[3].out_uop.br_type connect issue_slots[2].in_uop.bits.br_tag, issue_slots[3].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[3].out_uop.br_mask connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[3].out_uop.dis_col_sel connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[3].out_uop.iw_p3_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[3].out_uop.iw_p2_bypass_hint connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[3].out_uop.iw_p1_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[3].out_uop.iw_p2_speculative_child connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[3].out_uop.iw_p1_speculative_child connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[3].out_uop.iw_issued_partial_dgen connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[3].out_uop.iw_issued_partial_agen connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[3].out_uop.iw_issued connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[3].out_uop.fu_code[0] connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[3].out_uop.fu_code[1] connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[3].out_uop.fu_code[2] connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[3].out_uop.fu_code[3] connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[3].out_uop.fu_code[4] connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[3].out_uop.fu_code[5] connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[3].out_uop.fu_code[6] connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[3].out_uop.fu_code[7] connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[3].out_uop.fu_code[8] connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[3].out_uop.fu_code[9] connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[3].out_uop.iq_type[0] connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[3].out_uop.iq_type[1] connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[3].out_uop.iq_type[2] connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[3].out_uop.iq_type[3] connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[3].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[3].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[3].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[3].out_uop.inst node _T_101 = eq(shamts_oh[4], UInt<2>(0h2)) when _T_101 : connect issue_slots[2].in_uop.valid, issue_slots[4].will_be_valid connect issue_slots[2].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[2].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[2].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[2].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[2].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[2].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[2].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[2].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ connect issue_slots[2].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm connect issue_slots[2].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[2].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op connect issue_slots[2].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw connect issue_slots[2].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[2].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[2].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[2].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[2].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[2].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[2].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[2].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[2].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[2].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd connect issue_slots[2].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[2].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[2].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[2].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[2].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[2].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[2].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[2].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[2].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[2].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[2].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[2].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[2].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[2].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[2].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[2].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[2].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[2].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[2].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[2].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[2].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[2].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[2].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[2].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec connect issue_slots[2].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags connect issue_slots[2].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt connect issue_slots[2].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div connect issue_slots[2].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma connect issue_slots[2].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe connect issue_slots[2].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint connect issue_slots[2].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut connect issue_slots[2].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn connect issue_slots[2].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 connect issue_slots[2].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 connect issue_slots[2].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 connect issue_slots[2].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 connect issue_slots[2].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 connect issue_slots[2].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen connect issue_slots[2].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst connect issue_slots[2].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel connect issue_slots[2].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel connect issue_slots[2].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[2].in_uop.bits.pimm, issue_slots[4].out_uop.pimm connect issue_slots[2].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel connect issue_slots[2].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename connect issue_slots[2].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[2].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[2].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[2].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[2].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov connect issue_slots[2].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc connect issue_slots[2].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[2].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret connect issue_slots[2].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[2].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence connect issue_slots[2].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[2].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[2].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[2].in_uop.bits.br_type, issue_slots[4].out_uop.br_type connect issue_slots[2].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[2].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[2].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel connect issue_slots[2].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint connect issue_slots[2].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint connect issue_slots[2].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child connect issue_slots[2].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child connect issue_slots[2].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen connect issue_slots[2].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen connect issue_slots[2].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued connect issue_slots[2].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] connect issue_slots[2].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] connect issue_slots[2].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] connect issue_slots[2].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] connect issue_slots[2].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] connect issue_slots[2].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] connect issue_slots[2].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] connect issue_slots[2].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] connect issue_slots[2].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] connect issue_slots[2].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] connect issue_slots[2].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] connect issue_slots[2].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] connect issue_slots[2].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] connect issue_slots[2].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] connect issue_slots[2].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[2].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[2].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[2].in_uop.bits.inst, issue_slots[4].out_uop.inst node _issue_slots_2_clear_T = neq(shamts_oh[2], UInt<1>(0h0)) connect issue_slots[2].clear, _issue_slots_2_clear_T connect issue_slots[3].in_uop.valid, UInt<1>(0h0) connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[3].in_uop.bits.pimm, issue_slots[4].out_uop.pimm connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[3].in_uop.bits.br_type, issue_slots[4].out_uop.br_type connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst node _T_102 = eq(shamts_oh[4], UInt<1>(0h1)) when _T_102 : connect issue_slots[3].in_uop.valid, issue_slots[4].will_be_valid connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[4].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[4].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[4].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[4].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[4].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[4].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[4].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[4].out_uop.fp_typ connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[4].out_uop.fp_rm connect issue_slots[3].in_uop.bits.fp_val, issue_slots[4].out_uop.fp_val connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[4].out_uop.fcn_op connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[4].out_uop.fcn_dw connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[4].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[4].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[4].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[4].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.lrs3, issue_slots[4].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[4].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[4].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[4].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[4].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[4].out_uop.csr_cmd connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[4].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[4].out_uop.is_unique connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[4].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[4].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[4].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[4].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[4].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[4].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[4].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[4].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[4].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[4].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[4].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[4].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[4].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[4].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[4].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[4].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[4].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[4].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[4].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[4].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[4].out_uop.rob_idx connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[4].out_uop.fp_ctrl.vec connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[4].out_uop.fp_ctrl.wflags connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[4].out_uop.fp_ctrl.sqrt connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[4].out_uop.fp_ctrl.div connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[4].out_uop.fp_ctrl.fma connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[4].out_uop.fp_ctrl.fastpipe connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[4].out_uop.fp_ctrl.toint connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[4].out_uop.fp_ctrl.fromint connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[4].out_uop.fp_ctrl.typeTagOut connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[4].out_uop.fp_ctrl.typeTagIn connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[4].out_uop.fp_ctrl.swap23 connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[4].out_uop.fp_ctrl.swap12 connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[4].out_uop.fp_ctrl.ren3 connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[4].out_uop.fp_ctrl.ren2 connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[4].out_uop.fp_ctrl.ren1 connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[4].out_uop.fp_ctrl.wen connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[4].out_uop.fp_ctrl.ldst connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[4].out_uop.op2_sel connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[4].out_uop.op1_sel connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[4].out_uop.imm_packed connect issue_slots[3].in_uop.bits.pimm, issue_slots[4].out_uop.pimm connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[4].out_uop.imm_sel connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[4].out_uop.imm_rename connect issue_slots[3].in_uop.bits.taken, issue_slots[4].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[4].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[4].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[4].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.is_mov, issue_slots[4].out_uop.is_mov connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[4].out_uop.is_rocc connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[4].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.is_eret, issue_slots[4].out_uop.is_eret connect issue_slots[3].in_uop.bits.is_amo, issue_slots[4].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[4].out_uop.is_sfence connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[4].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[4].out_uop.is_fence connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[4].out_uop.is_sfb connect issue_slots[3].in_uop.bits.br_type, issue_slots[4].out_uop.br_type connect issue_slots[3].in_uop.bits.br_tag, issue_slots[4].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[4].out_uop.br_mask connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[4].out_uop.dis_col_sel connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[4].out_uop.iw_p3_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[4].out_uop.iw_p2_bypass_hint connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[4].out_uop.iw_p1_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[4].out_uop.iw_p2_speculative_child connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[4].out_uop.iw_p1_speculative_child connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[4].out_uop.iw_issued_partial_dgen connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[4].out_uop.iw_issued_partial_agen connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[4].out_uop.iw_issued connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[4].out_uop.fu_code[0] connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[4].out_uop.fu_code[1] connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[4].out_uop.fu_code[2] connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[4].out_uop.fu_code[3] connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[4].out_uop.fu_code[4] connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[4].out_uop.fu_code[5] connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[4].out_uop.fu_code[6] connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[4].out_uop.fu_code[7] connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[4].out_uop.fu_code[8] connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[4].out_uop.fu_code[9] connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[4].out_uop.iq_type[0] connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[4].out_uop.iq_type[1] connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[4].out_uop.iq_type[2] connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[4].out_uop.iq_type[3] connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[4].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[4].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[4].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[4].out_uop.inst node _T_103 = eq(shamts_oh[5], UInt<2>(0h2)) when _T_103 : connect issue_slots[3].in_uop.valid, issue_slots[5].will_be_valid connect issue_slots[3].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[3].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[3].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[3].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[3].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[3].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[3].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[3].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ connect issue_slots[3].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm connect issue_slots[3].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[3].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op connect issue_slots[3].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw connect issue_slots[3].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[3].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[3].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[3].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[3].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[3].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[3].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[3].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[3].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[3].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd connect issue_slots[3].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[3].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[3].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[3].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[3].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[3].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[3].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[3].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[3].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[3].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[3].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[3].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[3].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[3].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[3].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[3].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[3].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[3].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[3].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[3].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[3].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[3].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[3].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[3].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec connect issue_slots[3].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags connect issue_slots[3].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt connect issue_slots[3].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div connect issue_slots[3].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma connect issue_slots[3].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe connect issue_slots[3].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint connect issue_slots[3].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut connect issue_slots[3].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn connect issue_slots[3].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 connect issue_slots[3].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 connect issue_slots[3].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 connect issue_slots[3].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 connect issue_slots[3].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 connect issue_slots[3].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen connect issue_slots[3].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst connect issue_slots[3].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel connect issue_slots[3].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel connect issue_slots[3].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[3].in_uop.bits.pimm, issue_slots[5].out_uop.pimm connect issue_slots[3].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel connect issue_slots[3].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename connect issue_slots[3].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[3].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[3].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[3].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[3].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov connect issue_slots[3].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc connect issue_slots[3].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[3].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret connect issue_slots[3].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[3].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence connect issue_slots[3].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[3].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[3].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[3].in_uop.bits.br_type, issue_slots[5].out_uop.br_type connect issue_slots[3].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[3].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[3].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel connect issue_slots[3].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint connect issue_slots[3].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint connect issue_slots[3].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child connect issue_slots[3].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child connect issue_slots[3].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen connect issue_slots[3].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen connect issue_slots[3].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued connect issue_slots[3].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] connect issue_slots[3].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] connect issue_slots[3].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] connect issue_slots[3].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] connect issue_slots[3].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] connect issue_slots[3].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] connect issue_slots[3].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] connect issue_slots[3].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] connect issue_slots[3].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] connect issue_slots[3].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] connect issue_slots[3].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] connect issue_slots[3].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] connect issue_slots[3].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] connect issue_slots[3].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] connect issue_slots[3].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[3].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[3].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[3].in_uop.bits.inst, issue_slots[5].out_uop.inst node _issue_slots_3_clear_T = neq(shamts_oh[3], UInt<1>(0h0)) connect issue_slots[3].clear, _issue_slots_3_clear_T connect issue_slots[4].in_uop.valid, UInt<1>(0h0) connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[4].in_uop.bits.pimm, issue_slots[5].out_uop.pimm connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[4].in_uop.bits.br_type, issue_slots[5].out_uop.br_type connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst node _T_104 = eq(shamts_oh[5], UInt<1>(0h1)) when _T_104 : connect issue_slots[4].in_uop.valid, issue_slots[5].will_be_valid connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[5].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[5].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[5].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[5].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[5].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[5].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[5].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[5].out_uop.fp_typ connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[5].out_uop.fp_rm connect issue_slots[4].in_uop.bits.fp_val, issue_slots[5].out_uop.fp_val connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[5].out_uop.fcn_op connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[5].out_uop.fcn_dw connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[5].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[5].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[5].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[5].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.lrs3, issue_slots[5].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[5].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[5].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[5].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[5].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[5].out_uop.csr_cmd connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[5].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[5].out_uop.is_unique connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[5].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[5].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[5].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[5].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[5].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[5].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[5].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[5].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[5].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[5].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[5].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[5].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[5].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[5].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[5].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[5].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[5].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[5].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[5].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[5].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[5].out_uop.rob_idx connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[5].out_uop.fp_ctrl.vec connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[5].out_uop.fp_ctrl.wflags connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[5].out_uop.fp_ctrl.sqrt connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[5].out_uop.fp_ctrl.div connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[5].out_uop.fp_ctrl.fma connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[5].out_uop.fp_ctrl.fastpipe connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[5].out_uop.fp_ctrl.toint connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[5].out_uop.fp_ctrl.fromint connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[5].out_uop.fp_ctrl.typeTagOut connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[5].out_uop.fp_ctrl.typeTagIn connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[5].out_uop.fp_ctrl.swap23 connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[5].out_uop.fp_ctrl.swap12 connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[5].out_uop.fp_ctrl.ren3 connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[5].out_uop.fp_ctrl.ren2 connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[5].out_uop.fp_ctrl.ren1 connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[5].out_uop.fp_ctrl.wen connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[5].out_uop.fp_ctrl.ldst connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[5].out_uop.op2_sel connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[5].out_uop.op1_sel connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[5].out_uop.imm_packed connect issue_slots[4].in_uop.bits.pimm, issue_slots[5].out_uop.pimm connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[5].out_uop.imm_sel connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[5].out_uop.imm_rename connect issue_slots[4].in_uop.bits.taken, issue_slots[5].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[5].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[5].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[5].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.is_mov, issue_slots[5].out_uop.is_mov connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[5].out_uop.is_rocc connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[5].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.is_eret, issue_slots[5].out_uop.is_eret connect issue_slots[4].in_uop.bits.is_amo, issue_slots[5].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[5].out_uop.is_sfence connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[5].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[5].out_uop.is_fence connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[5].out_uop.is_sfb connect issue_slots[4].in_uop.bits.br_type, issue_slots[5].out_uop.br_type connect issue_slots[4].in_uop.bits.br_tag, issue_slots[5].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[5].out_uop.br_mask connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[5].out_uop.dis_col_sel connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[5].out_uop.iw_p3_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[5].out_uop.iw_p2_bypass_hint connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[5].out_uop.iw_p1_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[5].out_uop.iw_p2_speculative_child connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[5].out_uop.iw_p1_speculative_child connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[5].out_uop.iw_issued_partial_dgen connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[5].out_uop.iw_issued_partial_agen connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[5].out_uop.iw_issued connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[5].out_uop.fu_code[0] connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[5].out_uop.fu_code[1] connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[5].out_uop.fu_code[2] connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[5].out_uop.fu_code[3] connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[5].out_uop.fu_code[4] connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[5].out_uop.fu_code[5] connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[5].out_uop.fu_code[6] connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[5].out_uop.fu_code[7] connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[5].out_uop.fu_code[8] connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[5].out_uop.fu_code[9] connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[5].out_uop.iq_type[0] connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[5].out_uop.iq_type[1] connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[5].out_uop.iq_type[2] connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[5].out_uop.iq_type[3] connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[5].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[5].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[5].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[5].out_uop.inst node _T_105 = eq(shamts_oh[6], UInt<2>(0h2)) when _T_105 : connect issue_slots[4].in_uop.valid, issue_slots[6].will_be_valid connect issue_slots[4].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[4].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[4].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[4].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[4].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[4].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[4].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[4].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ connect issue_slots[4].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm connect issue_slots[4].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[4].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op connect issue_slots[4].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw connect issue_slots[4].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[4].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[4].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[4].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[4].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[4].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[4].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[4].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[4].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[4].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd connect issue_slots[4].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[4].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[4].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[4].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[4].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[4].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[4].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[4].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[4].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[4].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[4].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[4].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[4].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[4].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[4].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[4].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[4].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[4].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[4].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[4].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[4].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[4].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[4].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[4].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec connect issue_slots[4].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags connect issue_slots[4].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt connect issue_slots[4].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div connect issue_slots[4].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma connect issue_slots[4].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe connect issue_slots[4].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint connect issue_slots[4].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut connect issue_slots[4].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn connect issue_slots[4].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 connect issue_slots[4].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 connect issue_slots[4].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 connect issue_slots[4].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 connect issue_slots[4].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 connect issue_slots[4].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen connect issue_slots[4].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst connect issue_slots[4].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel connect issue_slots[4].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel connect issue_slots[4].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[4].in_uop.bits.pimm, issue_slots[6].out_uop.pimm connect issue_slots[4].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel connect issue_slots[4].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename connect issue_slots[4].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[4].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[4].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[4].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[4].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov connect issue_slots[4].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc connect issue_slots[4].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[4].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret connect issue_slots[4].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[4].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence connect issue_slots[4].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[4].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[4].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[4].in_uop.bits.br_type, issue_slots[6].out_uop.br_type connect issue_slots[4].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[4].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[4].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel connect issue_slots[4].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint connect issue_slots[4].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint connect issue_slots[4].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child connect issue_slots[4].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child connect issue_slots[4].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen connect issue_slots[4].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen connect issue_slots[4].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued connect issue_slots[4].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] connect issue_slots[4].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] connect issue_slots[4].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] connect issue_slots[4].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] connect issue_slots[4].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] connect issue_slots[4].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] connect issue_slots[4].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] connect issue_slots[4].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] connect issue_slots[4].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] connect issue_slots[4].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] connect issue_slots[4].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] connect issue_slots[4].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] connect issue_slots[4].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] connect issue_slots[4].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] connect issue_slots[4].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[4].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[4].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[4].in_uop.bits.inst, issue_slots[6].out_uop.inst node _issue_slots_4_clear_T = neq(shamts_oh[4], UInt<1>(0h0)) connect issue_slots[4].clear, _issue_slots_4_clear_T connect issue_slots[5].in_uop.valid, UInt<1>(0h0) connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[5].in_uop.bits.pimm, issue_slots[6].out_uop.pimm connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[5].in_uop.bits.br_type, issue_slots[6].out_uop.br_type connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst node _T_106 = eq(shamts_oh[6], UInt<1>(0h1)) when _T_106 : connect issue_slots[5].in_uop.valid, issue_slots[6].will_be_valid connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[6].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[6].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[6].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[6].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[6].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[6].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[6].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[6].out_uop.fp_typ connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[6].out_uop.fp_rm connect issue_slots[5].in_uop.bits.fp_val, issue_slots[6].out_uop.fp_val connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[6].out_uop.fcn_op connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[6].out_uop.fcn_dw connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[6].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[6].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[6].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[6].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.lrs3, issue_slots[6].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[6].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[6].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[6].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[6].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[6].out_uop.csr_cmd connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[6].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[6].out_uop.is_unique connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[6].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[6].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[6].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[6].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[6].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[6].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[6].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[6].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[6].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[6].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[6].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[6].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[6].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[6].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[6].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[6].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[6].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[6].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[6].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[6].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[6].out_uop.rob_idx connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[6].out_uop.fp_ctrl.vec connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[6].out_uop.fp_ctrl.wflags connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[6].out_uop.fp_ctrl.sqrt connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[6].out_uop.fp_ctrl.div connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[6].out_uop.fp_ctrl.fma connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[6].out_uop.fp_ctrl.fastpipe connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[6].out_uop.fp_ctrl.toint connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[6].out_uop.fp_ctrl.fromint connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[6].out_uop.fp_ctrl.typeTagOut connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[6].out_uop.fp_ctrl.typeTagIn connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[6].out_uop.fp_ctrl.swap23 connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[6].out_uop.fp_ctrl.swap12 connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[6].out_uop.fp_ctrl.ren3 connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[6].out_uop.fp_ctrl.ren2 connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[6].out_uop.fp_ctrl.ren1 connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[6].out_uop.fp_ctrl.wen connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[6].out_uop.fp_ctrl.ldst connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[6].out_uop.op2_sel connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[6].out_uop.op1_sel connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[6].out_uop.imm_packed connect issue_slots[5].in_uop.bits.pimm, issue_slots[6].out_uop.pimm connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[6].out_uop.imm_sel connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[6].out_uop.imm_rename connect issue_slots[5].in_uop.bits.taken, issue_slots[6].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[6].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[6].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[6].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.is_mov, issue_slots[6].out_uop.is_mov connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[6].out_uop.is_rocc connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[6].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.is_eret, issue_slots[6].out_uop.is_eret connect issue_slots[5].in_uop.bits.is_amo, issue_slots[6].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[6].out_uop.is_sfence connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[6].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[6].out_uop.is_fence connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[6].out_uop.is_sfb connect issue_slots[5].in_uop.bits.br_type, issue_slots[6].out_uop.br_type connect issue_slots[5].in_uop.bits.br_tag, issue_slots[6].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[6].out_uop.br_mask connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[6].out_uop.dis_col_sel connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[6].out_uop.iw_p3_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[6].out_uop.iw_p2_bypass_hint connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[6].out_uop.iw_p1_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[6].out_uop.iw_p2_speculative_child connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[6].out_uop.iw_p1_speculative_child connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[6].out_uop.iw_issued_partial_dgen connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[6].out_uop.iw_issued_partial_agen connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[6].out_uop.iw_issued connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[6].out_uop.fu_code[0] connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[6].out_uop.fu_code[1] connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[6].out_uop.fu_code[2] connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[6].out_uop.fu_code[3] connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[6].out_uop.fu_code[4] connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[6].out_uop.fu_code[5] connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[6].out_uop.fu_code[6] connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[6].out_uop.fu_code[7] connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[6].out_uop.fu_code[8] connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[6].out_uop.fu_code[9] connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[6].out_uop.iq_type[0] connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[6].out_uop.iq_type[1] connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[6].out_uop.iq_type[2] connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[6].out_uop.iq_type[3] connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[6].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[6].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[6].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[6].out_uop.inst node _T_107 = eq(shamts_oh[7], UInt<2>(0h2)) when _T_107 : connect issue_slots[5].in_uop.valid, issue_slots[7].will_be_valid connect issue_slots[5].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[5].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[5].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[5].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[5].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[5].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[5].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[5].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ connect issue_slots[5].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm connect issue_slots[5].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[5].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op connect issue_slots[5].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw connect issue_slots[5].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[5].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[5].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[5].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[5].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[5].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[5].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[5].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[5].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[5].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd connect issue_slots[5].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[5].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[5].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[5].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[5].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[5].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[5].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[5].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[5].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[5].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[5].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[5].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[5].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[5].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[5].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[5].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[5].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[5].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[5].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[5].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[5].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[5].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[5].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[5].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec connect issue_slots[5].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags connect issue_slots[5].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt connect issue_slots[5].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div connect issue_slots[5].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma connect issue_slots[5].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe connect issue_slots[5].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint connect issue_slots[5].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut connect issue_slots[5].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn connect issue_slots[5].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 connect issue_slots[5].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 connect issue_slots[5].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 connect issue_slots[5].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 connect issue_slots[5].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 connect issue_slots[5].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen connect issue_slots[5].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst connect issue_slots[5].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel connect issue_slots[5].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel connect issue_slots[5].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[5].in_uop.bits.pimm, issue_slots[7].out_uop.pimm connect issue_slots[5].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel connect issue_slots[5].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename connect issue_slots[5].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[5].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[5].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[5].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[5].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov connect issue_slots[5].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc connect issue_slots[5].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[5].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret connect issue_slots[5].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[5].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence connect issue_slots[5].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[5].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[5].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[5].in_uop.bits.br_type, issue_slots[7].out_uop.br_type connect issue_slots[5].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[5].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[5].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel connect issue_slots[5].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint connect issue_slots[5].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint connect issue_slots[5].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child connect issue_slots[5].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child connect issue_slots[5].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen connect issue_slots[5].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen connect issue_slots[5].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued connect issue_slots[5].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] connect issue_slots[5].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] connect issue_slots[5].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] connect issue_slots[5].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] connect issue_slots[5].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] connect issue_slots[5].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] connect issue_slots[5].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] connect issue_slots[5].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] connect issue_slots[5].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] connect issue_slots[5].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] connect issue_slots[5].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] connect issue_slots[5].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] connect issue_slots[5].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] connect issue_slots[5].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] connect issue_slots[5].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[5].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[5].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[5].in_uop.bits.inst, issue_slots[7].out_uop.inst node _issue_slots_5_clear_T = neq(shamts_oh[5], UInt<1>(0h0)) connect issue_slots[5].clear, _issue_slots_5_clear_T connect issue_slots[6].in_uop.valid, UInt<1>(0h0) connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[6].in_uop.bits.pimm, issue_slots[7].out_uop.pimm connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[6].in_uop.bits.br_type, issue_slots[7].out_uop.br_type connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst node _T_108 = eq(shamts_oh[7], UInt<1>(0h1)) when _T_108 : connect issue_slots[6].in_uop.valid, issue_slots[7].will_be_valid connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[7].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[7].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[7].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[7].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[7].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[7].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[7].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[7].out_uop.fp_typ connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[7].out_uop.fp_rm connect issue_slots[6].in_uop.bits.fp_val, issue_slots[7].out_uop.fp_val connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[7].out_uop.fcn_op connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[7].out_uop.fcn_dw connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[7].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[7].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[7].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[7].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.lrs3, issue_slots[7].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[7].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[7].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[7].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[7].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[7].out_uop.csr_cmd connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[7].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[7].out_uop.is_unique connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[7].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[7].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[7].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[7].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[7].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[7].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[7].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[7].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[7].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[7].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[7].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[7].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[7].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[7].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[7].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[7].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[7].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[7].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[7].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[7].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[7].out_uop.rob_idx connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[7].out_uop.fp_ctrl.vec connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[7].out_uop.fp_ctrl.wflags connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[7].out_uop.fp_ctrl.sqrt connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[7].out_uop.fp_ctrl.div connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[7].out_uop.fp_ctrl.fma connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[7].out_uop.fp_ctrl.fastpipe connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[7].out_uop.fp_ctrl.toint connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[7].out_uop.fp_ctrl.fromint connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[7].out_uop.fp_ctrl.typeTagOut connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[7].out_uop.fp_ctrl.typeTagIn connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[7].out_uop.fp_ctrl.swap23 connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[7].out_uop.fp_ctrl.swap12 connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[7].out_uop.fp_ctrl.ren3 connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[7].out_uop.fp_ctrl.ren2 connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[7].out_uop.fp_ctrl.ren1 connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[7].out_uop.fp_ctrl.wen connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[7].out_uop.fp_ctrl.ldst connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[7].out_uop.op2_sel connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[7].out_uop.op1_sel connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[7].out_uop.imm_packed connect issue_slots[6].in_uop.bits.pimm, issue_slots[7].out_uop.pimm connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[7].out_uop.imm_sel connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[7].out_uop.imm_rename connect issue_slots[6].in_uop.bits.taken, issue_slots[7].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[7].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[7].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[7].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.is_mov, issue_slots[7].out_uop.is_mov connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[7].out_uop.is_rocc connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[7].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.is_eret, issue_slots[7].out_uop.is_eret connect issue_slots[6].in_uop.bits.is_amo, issue_slots[7].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[7].out_uop.is_sfence connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[7].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[7].out_uop.is_fence connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[7].out_uop.is_sfb connect issue_slots[6].in_uop.bits.br_type, issue_slots[7].out_uop.br_type connect issue_slots[6].in_uop.bits.br_tag, issue_slots[7].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[7].out_uop.br_mask connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[7].out_uop.dis_col_sel connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[7].out_uop.iw_p3_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[7].out_uop.iw_p2_bypass_hint connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[7].out_uop.iw_p1_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[7].out_uop.iw_p2_speculative_child connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[7].out_uop.iw_p1_speculative_child connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[7].out_uop.iw_issued_partial_dgen connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[7].out_uop.iw_issued_partial_agen connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[7].out_uop.iw_issued connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[7].out_uop.fu_code[0] connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[7].out_uop.fu_code[1] connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[7].out_uop.fu_code[2] connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[7].out_uop.fu_code[3] connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[7].out_uop.fu_code[4] connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[7].out_uop.fu_code[5] connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[7].out_uop.fu_code[6] connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[7].out_uop.fu_code[7] connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[7].out_uop.fu_code[8] connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[7].out_uop.fu_code[9] connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[7].out_uop.iq_type[0] connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[7].out_uop.iq_type[1] connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[7].out_uop.iq_type[2] connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[7].out_uop.iq_type[3] connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[7].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[7].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[7].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[7].out_uop.inst node _T_109 = eq(shamts_oh[8], UInt<2>(0h2)) when _T_109 : connect issue_slots[6].in_uop.valid, issue_slots[8].will_be_valid connect issue_slots[6].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[6].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[6].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[6].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[6].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[6].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[6].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[6].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ connect issue_slots[6].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm connect issue_slots[6].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[6].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op connect issue_slots[6].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw connect issue_slots[6].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[6].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[6].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[6].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[6].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[6].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[6].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[6].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[6].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[6].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd connect issue_slots[6].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[6].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[6].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[6].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[6].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[6].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[6].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[6].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[6].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[6].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[6].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[6].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[6].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[6].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[6].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[6].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[6].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[6].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[6].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[6].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[6].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[6].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[6].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[6].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec connect issue_slots[6].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags connect issue_slots[6].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt connect issue_slots[6].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div connect issue_slots[6].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma connect issue_slots[6].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe connect issue_slots[6].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint connect issue_slots[6].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut connect issue_slots[6].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn connect issue_slots[6].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 connect issue_slots[6].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 connect issue_slots[6].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 connect issue_slots[6].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 connect issue_slots[6].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 connect issue_slots[6].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen connect issue_slots[6].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst connect issue_slots[6].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel connect issue_slots[6].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel connect issue_slots[6].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[6].in_uop.bits.pimm, issue_slots[8].out_uop.pimm connect issue_slots[6].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel connect issue_slots[6].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename connect issue_slots[6].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[6].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[6].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[6].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[6].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov connect issue_slots[6].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc connect issue_slots[6].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[6].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret connect issue_slots[6].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[6].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence connect issue_slots[6].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[6].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[6].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[6].in_uop.bits.br_type, issue_slots[8].out_uop.br_type connect issue_slots[6].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[6].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[6].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel connect issue_slots[6].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint connect issue_slots[6].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint connect issue_slots[6].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child connect issue_slots[6].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child connect issue_slots[6].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen connect issue_slots[6].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen connect issue_slots[6].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued connect issue_slots[6].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] connect issue_slots[6].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] connect issue_slots[6].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] connect issue_slots[6].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] connect issue_slots[6].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] connect issue_slots[6].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] connect issue_slots[6].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] connect issue_slots[6].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] connect issue_slots[6].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] connect issue_slots[6].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] connect issue_slots[6].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] connect issue_slots[6].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] connect issue_slots[6].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] connect issue_slots[6].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] connect issue_slots[6].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[6].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[6].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[6].in_uop.bits.inst, issue_slots[8].out_uop.inst node _issue_slots_6_clear_T = neq(shamts_oh[6], UInt<1>(0h0)) connect issue_slots[6].clear, _issue_slots_6_clear_T connect issue_slots[7].in_uop.valid, UInt<1>(0h0) connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[7].in_uop.bits.pimm, issue_slots[8].out_uop.pimm connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[7].in_uop.bits.br_type, issue_slots[8].out_uop.br_type connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst node _T_110 = eq(shamts_oh[8], UInt<1>(0h1)) when _T_110 : connect issue_slots[7].in_uop.valid, issue_slots[8].will_be_valid connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[8].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[8].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[8].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[8].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[8].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[8].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[8].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[8].out_uop.fp_typ connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[8].out_uop.fp_rm connect issue_slots[7].in_uop.bits.fp_val, issue_slots[8].out_uop.fp_val connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[8].out_uop.fcn_op connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[8].out_uop.fcn_dw connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[8].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[8].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[8].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[8].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.lrs3, issue_slots[8].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[8].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[8].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[8].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[8].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[8].out_uop.csr_cmd connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[8].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[8].out_uop.is_unique connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[8].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[8].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[8].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[8].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[8].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[8].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[8].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[8].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[8].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[8].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[8].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[8].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[8].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[8].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[8].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[8].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[8].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[8].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[8].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[8].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[8].out_uop.rob_idx connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[8].out_uop.fp_ctrl.vec connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[8].out_uop.fp_ctrl.wflags connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[8].out_uop.fp_ctrl.sqrt connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[8].out_uop.fp_ctrl.div connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[8].out_uop.fp_ctrl.fma connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[8].out_uop.fp_ctrl.fastpipe connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[8].out_uop.fp_ctrl.toint connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[8].out_uop.fp_ctrl.fromint connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[8].out_uop.fp_ctrl.typeTagOut connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[8].out_uop.fp_ctrl.typeTagIn connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[8].out_uop.fp_ctrl.swap23 connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[8].out_uop.fp_ctrl.swap12 connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[8].out_uop.fp_ctrl.ren3 connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[8].out_uop.fp_ctrl.ren2 connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[8].out_uop.fp_ctrl.ren1 connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[8].out_uop.fp_ctrl.wen connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[8].out_uop.fp_ctrl.ldst connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[8].out_uop.op2_sel connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[8].out_uop.op1_sel connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[8].out_uop.imm_packed connect issue_slots[7].in_uop.bits.pimm, issue_slots[8].out_uop.pimm connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[8].out_uop.imm_sel connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[8].out_uop.imm_rename connect issue_slots[7].in_uop.bits.taken, issue_slots[8].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[8].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[8].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[8].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.is_mov, issue_slots[8].out_uop.is_mov connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[8].out_uop.is_rocc connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[8].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.is_eret, issue_slots[8].out_uop.is_eret connect issue_slots[7].in_uop.bits.is_amo, issue_slots[8].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[8].out_uop.is_sfence connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[8].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[8].out_uop.is_fence connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[8].out_uop.is_sfb connect issue_slots[7].in_uop.bits.br_type, issue_slots[8].out_uop.br_type connect issue_slots[7].in_uop.bits.br_tag, issue_slots[8].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[8].out_uop.br_mask connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[8].out_uop.dis_col_sel connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[8].out_uop.iw_p3_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[8].out_uop.iw_p2_bypass_hint connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[8].out_uop.iw_p1_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[8].out_uop.iw_p2_speculative_child connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[8].out_uop.iw_p1_speculative_child connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[8].out_uop.iw_issued_partial_dgen connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[8].out_uop.iw_issued_partial_agen connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[8].out_uop.iw_issued connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[8].out_uop.fu_code[0] connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[8].out_uop.fu_code[1] connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[8].out_uop.fu_code[2] connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[8].out_uop.fu_code[3] connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[8].out_uop.fu_code[4] connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[8].out_uop.fu_code[5] connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[8].out_uop.fu_code[6] connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[8].out_uop.fu_code[7] connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[8].out_uop.fu_code[8] connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[8].out_uop.fu_code[9] connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[8].out_uop.iq_type[0] connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[8].out_uop.iq_type[1] connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[8].out_uop.iq_type[2] connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[8].out_uop.iq_type[3] connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[8].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[8].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[8].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[8].out_uop.inst node _T_111 = eq(shamts_oh[9], UInt<2>(0h2)) when _T_111 : connect issue_slots[7].in_uop.valid, issue_slots[9].will_be_valid connect issue_slots[7].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[7].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[7].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[7].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[7].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[7].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[7].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[7].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ connect issue_slots[7].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm connect issue_slots[7].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[7].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op connect issue_slots[7].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw connect issue_slots[7].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[7].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[7].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[7].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[7].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[7].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[7].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[7].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[7].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[7].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd connect issue_slots[7].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[7].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[7].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[7].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[7].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[7].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[7].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[7].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[7].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[7].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[7].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[7].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[7].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[7].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[7].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[7].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[7].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[7].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[7].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[7].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[7].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[7].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[7].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[7].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec connect issue_slots[7].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags connect issue_slots[7].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt connect issue_slots[7].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div connect issue_slots[7].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma connect issue_slots[7].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe connect issue_slots[7].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint connect issue_slots[7].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut connect issue_slots[7].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn connect issue_slots[7].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 connect issue_slots[7].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 connect issue_slots[7].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 connect issue_slots[7].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 connect issue_slots[7].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 connect issue_slots[7].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen connect issue_slots[7].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst connect issue_slots[7].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel connect issue_slots[7].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel connect issue_slots[7].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[7].in_uop.bits.pimm, issue_slots[9].out_uop.pimm connect issue_slots[7].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel connect issue_slots[7].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename connect issue_slots[7].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[7].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[7].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[7].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[7].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov connect issue_slots[7].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc connect issue_slots[7].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[7].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret connect issue_slots[7].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[7].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence connect issue_slots[7].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[7].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[7].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[7].in_uop.bits.br_type, issue_slots[9].out_uop.br_type connect issue_slots[7].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[7].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[7].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel connect issue_slots[7].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint connect issue_slots[7].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint connect issue_slots[7].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child connect issue_slots[7].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child connect issue_slots[7].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen connect issue_slots[7].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen connect issue_slots[7].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued connect issue_slots[7].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] connect issue_slots[7].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] connect issue_slots[7].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] connect issue_slots[7].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] connect issue_slots[7].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] connect issue_slots[7].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] connect issue_slots[7].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] connect issue_slots[7].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] connect issue_slots[7].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] connect issue_slots[7].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] connect issue_slots[7].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] connect issue_slots[7].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] connect issue_slots[7].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] connect issue_slots[7].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] connect issue_slots[7].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[7].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[7].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[7].in_uop.bits.inst, issue_slots[9].out_uop.inst node _issue_slots_7_clear_T = neq(shamts_oh[7], UInt<1>(0h0)) connect issue_slots[7].clear, _issue_slots_7_clear_T connect issue_slots[8].in_uop.valid, UInt<1>(0h0) connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[8].in_uop.bits.pimm, issue_slots[9].out_uop.pimm connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[8].in_uop.bits.br_type, issue_slots[9].out_uop.br_type connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst node _T_112 = eq(shamts_oh[9], UInt<1>(0h1)) when _T_112 : connect issue_slots[8].in_uop.valid, issue_slots[9].will_be_valid connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[9].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[9].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[9].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[9].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[9].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[9].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[9].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[9].out_uop.fp_typ connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[9].out_uop.fp_rm connect issue_slots[8].in_uop.bits.fp_val, issue_slots[9].out_uop.fp_val connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[9].out_uop.fcn_op connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[9].out_uop.fcn_dw connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[9].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[9].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[9].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[9].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.lrs3, issue_slots[9].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[9].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[9].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[9].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[9].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[9].out_uop.csr_cmd connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[9].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[9].out_uop.is_unique connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[9].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[9].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[9].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[9].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[9].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[9].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[9].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[9].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[9].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[9].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[9].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[9].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[9].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[9].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[9].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[9].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[9].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[9].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[9].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[9].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[9].out_uop.rob_idx connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[9].out_uop.fp_ctrl.vec connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[9].out_uop.fp_ctrl.wflags connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[9].out_uop.fp_ctrl.sqrt connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[9].out_uop.fp_ctrl.div connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[9].out_uop.fp_ctrl.fma connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[9].out_uop.fp_ctrl.fastpipe connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[9].out_uop.fp_ctrl.toint connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[9].out_uop.fp_ctrl.fromint connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[9].out_uop.fp_ctrl.typeTagOut connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[9].out_uop.fp_ctrl.typeTagIn connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[9].out_uop.fp_ctrl.swap23 connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[9].out_uop.fp_ctrl.swap12 connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[9].out_uop.fp_ctrl.ren3 connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[9].out_uop.fp_ctrl.ren2 connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[9].out_uop.fp_ctrl.ren1 connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[9].out_uop.fp_ctrl.wen connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[9].out_uop.fp_ctrl.ldst connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[9].out_uop.op2_sel connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[9].out_uop.op1_sel connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[9].out_uop.imm_packed connect issue_slots[8].in_uop.bits.pimm, issue_slots[9].out_uop.pimm connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[9].out_uop.imm_sel connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[9].out_uop.imm_rename connect issue_slots[8].in_uop.bits.taken, issue_slots[9].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[9].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[9].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[9].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.is_mov, issue_slots[9].out_uop.is_mov connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[9].out_uop.is_rocc connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[9].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.is_eret, issue_slots[9].out_uop.is_eret connect issue_slots[8].in_uop.bits.is_amo, issue_slots[9].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[9].out_uop.is_sfence connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[9].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[9].out_uop.is_fence connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[9].out_uop.is_sfb connect issue_slots[8].in_uop.bits.br_type, issue_slots[9].out_uop.br_type connect issue_slots[8].in_uop.bits.br_tag, issue_slots[9].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[9].out_uop.br_mask connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[9].out_uop.dis_col_sel connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[9].out_uop.iw_p3_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[9].out_uop.iw_p2_bypass_hint connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[9].out_uop.iw_p1_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[9].out_uop.iw_p2_speculative_child connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[9].out_uop.iw_p1_speculative_child connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[9].out_uop.iw_issued_partial_dgen connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[9].out_uop.iw_issued_partial_agen connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[9].out_uop.iw_issued connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[9].out_uop.fu_code[0] connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[9].out_uop.fu_code[1] connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[9].out_uop.fu_code[2] connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[9].out_uop.fu_code[3] connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[9].out_uop.fu_code[4] connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[9].out_uop.fu_code[5] connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[9].out_uop.fu_code[6] connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[9].out_uop.fu_code[7] connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[9].out_uop.fu_code[8] connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[9].out_uop.fu_code[9] connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[9].out_uop.iq_type[0] connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[9].out_uop.iq_type[1] connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[9].out_uop.iq_type[2] connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[9].out_uop.iq_type[3] connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[9].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[9].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[9].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[9].out_uop.inst node _T_113 = eq(shamts_oh[10], UInt<2>(0h2)) when _T_113 : connect issue_slots[8].in_uop.valid, issue_slots[10].will_be_valid connect issue_slots[8].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[8].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[8].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[8].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[8].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[8].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[8].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[8].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ connect issue_slots[8].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm connect issue_slots[8].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[8].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op connect issue_slots[8].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw connect issue_slots[8].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[8].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[8].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[8].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[8].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[8].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[8].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[8].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[8].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[8].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd connect issue_slots[8].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[8].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[8].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[8].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[8].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[8].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[8].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[8].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[8].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[8].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[8].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[8].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[8].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[8].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[8].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[8].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[8].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[8].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[8].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[8].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[8].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[8].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[8].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[8].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec connect issue_slots[8].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags connect issue_slots[8].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt connect issue_slots[8].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div connect issue_slots[8].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma connect issue_slots[8].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe connect issue_slots[8].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint connect issue_slots[8].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut connect issue_slots[8].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn connect issue_slots[8].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 connect issue_slots[8].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 connect issue_slots[8].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 connect issue_slots[8].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 connect issue_slots[8].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 connect issue_slots[8].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen connect issue_slots[8].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst connect issue_slots[8].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel connect issue_slots[8].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel connect issue_slots[8].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[8].in_uop.bits.pimm, issue_slots[10].out_uop.pimm connect issue_slots[8].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel connect issue_slots[8].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename connect issue_slots[8].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[8].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[8].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[8].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[8].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov connect issue_slots[8].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc connect issue_slots[8].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[8].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret connect issue_slots[8].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[8].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence connect issue_slots[8].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[8].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[8].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[8].in_uop.bits.br_type, issue_slots[10].out_uop.br_type connect issue_slots[8].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[8].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[8].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel connect issue_slots[8].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint connect issue_slots[8].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint connect issue_slots[8].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child connect issue_slots[8].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child connect issue_slots[8].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen connect issue_slots[8].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen connect issue_slots[8].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued connect issue_slots[8].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] connect issue_slots[8].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] connect issue_slots[8].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] connect issue_slots[8].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] connect issue_slots[8].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] connect issue_slots[8].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] connect issue_slots[8].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] connect issue_slots[8].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] connect issue_slots[8].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] connect issue_slots[8].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] connect issue_slots[8].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] connect issue_slots[8].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] connect issue_slots[8].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] connect issue_slots[8].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] connect issue_slots[8].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[8].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[8].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[8].in_uop.bits.inst, issue_slots[10].out_uop.inst node _issue_slots_8_clear_T = neq(shamts_oh[8], UInt<1>(0h0)) connect issue_slots[8].clear, _issue_slots_8_clear_T connect issue_slots[9].in_uop.valid, UInt<1>(0h0) connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[9].in_uop.bits.pimm, issue_slots[10].out_uop.pimm connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[9].in_uop.bits.br_type, issue_slots[10].out_uop.br_type connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst node _T_114 = eq(shamts_oh[10], UInt<1>(0h1)) when _T_114 : connect issue_slots[9].in_uop.valid, issue_slots[10].will_be_valid connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[10].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[10].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[10].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[10].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[10].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[10].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[10].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[10].out_uop.fp_typ connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[10].out_uop.fp_rm connect issue_slots[9].in_uop.bits.fp_val, issue_slots[10].out_uop.fp_val connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[10].out_uop.fcn_op connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[10].out_uop.fcn_dw connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[10].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[10].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[10].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[10].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.lrs3, issue_slots[10].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[10].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[10].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[10].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[10].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[10].out_uop.csr_cmd connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[10].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[10].out_uop.is_unique connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[10].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[10].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[10].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[10].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[10].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[10].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[10].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[10].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[10].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[10].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[10].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[10].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[10].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[10].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[10].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[10].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[10].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[10].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[10].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[10].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[10].out_uop.rob_idx connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[10].out_uop.fp_ctrl.vec connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[10].out_uop.fp_ctrl.wflags connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[10].out_uop.fp_ctrl.sqrt connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[10].out_uop.fp_ctrl.div connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[10].out_uop.fp_ctrl.fma connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[10].out_uop.fp_ctrl.fastpipe connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[10].out_uop.fp_ctrl.toint connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[10].out_uop.fp_ctrl.fromint connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[10].out_uop.fp_ctrl.typeTagOut connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[10].out_uop.fp_ctrl.typeTagIn connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[10].out_uop.fp_ctrl.swap23 connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[10].out_uop.fp_ctrl.swap12 connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[10].out_uop.fp_ctrl.ren3 connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[10].out_uop.fp_ctrl.ren2 connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[10].out_uop.fp_ctrl.ren1 connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[10].out_uop.fp_ctrl.wen connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[10].out_uop.fp_ctrl.ldst connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[10].out_uop.op2_sel connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[10].out_uop.op1_sel connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[10].out_uop.imm_packed connect issue_slots[9].in_uop.bits.pimm, issue_slots[10].out_uop.pimm connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[10].out_uop.imm_sel connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[10].out_uop.imm_rename connect issue_slots[9].in_uop.bits.taken, issue_slots[10].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[10].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[10].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[10].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.is_mov, issue_slots[10].out_uop.is_mov connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[10].out_uop.is_rocc connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[10].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.is_eret, issue_slots[10].out_uop.is_eret connect issue_slots[9].in_uop.bits.is_amo, issue_slots[10].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[10].out_uop.is_sfence connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[10].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[10].out_uop.is_fence connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[10].out_uop.is_sfb connect issue_slots[9].in_uop.bits.br_type, issue_slots[10].out_uop.br_type connect issue_slots[9].in_uop.bits.br_tag, issue_slots[10].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[10].out_uop.br_mask connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[10].out_uop.dis_col_sel connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[10].out_uop.iw_p3_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[10].out_uop.iw_p2_bypass_hint connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[10].out_uop.iw_p1_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[10].out_uop.iw_p2_speculative_child connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[10].out_uop.iw_p1_speculative_child connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[10].out_uop.iw_issued_partial_dgen connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[10].out_uop.iw_issued_partial_agen connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[10].out_uop.iw_issued connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[10].out_uop.fu_code[0] connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[10].out_uop.fu_code[1] connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[10].out_uop.fu_code[2] connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[10].out_uop.fu_code[3] connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[10].out_uop.fu_code[4] connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[10].out_uop.fu_code[5] connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[10].out_uop.fu_code[6] connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[10].out_uop.fu_code[7] connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[10].out_uop.fu_code[8] connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[10].out_uop.fu_code[9] connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[10].out_uop.iq_type[0] connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[10].out_uop.iq_type[1] connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[10].out_uop.iq_type[2] connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[10].out_uop.iq_type[3] connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[10].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[10].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[10].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[10].out_uop.inst node _T_115 = eq(shamts_oh[11], UInt<2>(0h2)) when _T_115 : connect issue_slots[9].in_uop.valid, issue_slots[11].will_be_valid connect issue_slots[9].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[9].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[9].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[9].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[9].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[9].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[9].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[9].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ connect issue_slots[9].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm connect issue_slots[9].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[9].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op connect issue_slots[9].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw connect issue_slots[9].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[9].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[9].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[9].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[9].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[9].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[9].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[9].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[9].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[9].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd connect issue_slots[9].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[9].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[9].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[9].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[9].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[9].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[9].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[9].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[9].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[9].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[9].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[9].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[9].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[9].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[9].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[9].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[9].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[9].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[9].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[9].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[9].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[9].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[9].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[9].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec connect issue_slots[9].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags connect issue_slots[9].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt connect issue_slots[9].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div connect issue_slots[9].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma connect issue_slots[9].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe connect issue_slots[9].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint connect issue_slots[9].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut connect issue_slots[9].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn connect issue_slots[9].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 connect issue_slots[9].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 connect issue_slots[9].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 connect issue_slots[9].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 connect issue_slots[9].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 connect issue_slots[9].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen connect issue_slots[9].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst connect issue_slots[9].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel connect issue_slots[9].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel connect issue_slots[9].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[9].in_uop.bits.pimm, issue_slots[11].out_uop.pimm connect issue_slots[9].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel connect issue_slots[9].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename connect issue_slots[9].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[9].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[9].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[9].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[9].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov connect issue_slots[9].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc connect issue_slots[9].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[9].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret connect issue_slots[9].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[9].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence connect issue_slots[9].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[9].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[9].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[9].in_uop.bits.br_type, issue_slots[11].out_uop.br_type connect issue_slots[9].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[9].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[9].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel connect issue_slots[9].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint connect issue_slots[9].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint connect issue_slots[9].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child connect issue_slots[9].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child connect issue_slots[9].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen connect issue_slots[9].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen connect issue_slots[9].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued connect issue_slots[9].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] connect issue_slots[9].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] connect issue_slots[9].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] connect issue_slots[9].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] connect issue_slots[9].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] connect issue_slots[9].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] connect issue_slots[9].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] connect issue_slots[9].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] connect issue_slots[9].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] connect issue_slots[9].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] connect issue_slots[9].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] connect issue_slots[9].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] connect issue_slots[9].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] connect issue_slots[9].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] connect issue_slots[9].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[9].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[9].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[9].in_uop.bits.inst, issue_slots[11].out_uop.inst node _issue_slots_9_clear_T = neq(shamts_oh[9], UInt<1>(0h0)) connect issue_slots[9].clear, _issue_slots_9_clear_T connect issue_slots[10].in_uop.valid, UInt<1>(0h0) connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[10].in_uop.bits.pimm, issue_slots[11].out_uop.pimm connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[10].in_uop.bits.br_type, issue_slots[11].out_uop.br_type connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst node _T_116 = eq(shamts_oh[11], UInt<1>(0h1)) when _T_116 : connect issue_slots[10].in_uop.valid, issue_slots[11].will_be_valid connect issue_slots[10].in_uop.bits.debug_tsrc, issue_slots[11].out_uop.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, issue_slots[11].out_uop.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, issue_slots[11].out_uop.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, issue_slots[11].out_uop.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, issue_slots[11].out_uop.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, issue_slots[11].out_uop.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, issue_slots[11].out_uop.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_typ, issue_slots[11].out_uop.fp_typ connect issue_slots[10].in_uop.bits.fp_rm, issue_slots[11].out_uop.fp_rm connect issue_slots[10].in_uop.bits.fp_val, issue_slots[11].out_uop.fp_val connect issue_slots[10].in_uop.bits.fcn_op, issue_slots[11].out_uop.fcn_op connect issue_slots[10].in_uop.bits.fcn_dw, issue_slots[11].out_uop.fcn_dw connect issue_slots[10].in_uop.bits.frs3_en, issue_slots[11].out_uop.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, issue_slots[11].out_uop.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, issue_slots[11].out_uop.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, issue_slots[11].out_uop.dst_rtype connect issue_slots[10].in_uop.bits.lrs3, issue_slots[11].out_uop.lrs3 connect issue_slots[10].in_uop.bits.lrs2, issue_slots[11].out_uop.lrs2 connect issue_slots[10].in_uop.bits.lrs1, issue_slots[11].out_uop.lrs1 connect issue_slots[10].in_uop.bits.ldst, issue_slots[11].out_uop.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, issue_slots[11].out_uop.ldst_is_rs1 connect issue_slots[10].in_uop.bits.csr_cmd, issue_slots[11].out_uop.csr_cmd connect issue_slots[10].in_uop.bits.flush_on_commit, issue_slots[11].out_uop.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, issue_slots[11].out_uop.is_unique connect issue_slots[10].in_uop.bits.uses_stq, issue_slots[11].out_uop.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, issue_slots[11].out_uop.uses_ldq connect issue_slots[10].in_uop.bits.mem_signed, issue_slots[11].out_uop.mem_signed connect issue_slots[10].in_uop.bits.mem_size, issue_slots[11].out_uop.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, issue_slots[11].out_uop.mem_cmd connect issue_slots[10].in_uop.bits.exc_cause, issue_slots[11].out_uop.exc_cause connect issue_slots[10].in_uop.bits.exception, issue_slots[11].out_uop.exception connect issue_slots[10].in_uop.bits.stale_pdst, issue_slots[11].out_uop.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, issue_slots[11].out_uop.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, issue_slots[11].out_uop.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, issue_slots[11].out_uop.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, issue_slots[11].out_uop.prs1_busy connect issue_slots[10].in_uop.bits.ppred, issue_slots[11].out_uop.ppred connect issue_slots[10].in_uop.bits.prs3, issue_slots[11].out_uop.prs3 connect issue_slots[10].in_uop.bits.prs2, issue_slots[11].out_uop.prs2 connect issue_slots[10].in_uop.bits.prs1, issue_slots[11].out_uop.prs1 connect issue_slots[10].in_uop.bits.pdst, issue_slots[11].out_uop.pdst connect issue_slots[10].in_uop.bits.rxq_idx, issue_slots[11].out_uop.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, issue_slots[11].out_uop.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, issue_slots[11].out_uop.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, issue_slots[11].out_uop.rob_idx connect issue_slots[10].in_uop.bits.fp_ctrl.vec, issue_slots[11].out_uop.fp_ctrl.vec connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, issue_slots[11].out_uop.fp_ctrl.wflags connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, issue_slots[11].out_uop.fp_ctrl.sqrt connect issue_slots[10].in_uop.bits.fp_ctrl.div, issue_slots[11].out_uop.fp_ctrl.div connect issue_slots[10].in_uop.bits.fp_ctrl.fma, issue_slots[11].out_uop.fp_ctrl.fma connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, issue_slots[11].out_uop.fp_ctrl.fastpipe connect issue_slots[10].in_uop.bits.fp_ctrl.toint, issue_slots[11].out_uop.fp_ctrl.toint connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, issue_slots[11].out_uop.fp_ctrl.fromint connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, issue_slots[11].out_uop.fp_ctrl.typeTagOut connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, issue_slots[11].out_uop.fp_ctrl.typeTagIn connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, issue_slots[11].out_uop.fp_ctrl.swap23 connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, issue_slots[11].out_uop.fp_ctrl.swap12 connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, issue_slots[11].out_uop.fp_ctrl.ren3 connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, issue_slots[11].out_uop.fp_ctrl.ren2 connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, issue_slots[11].out_uop.fp_ctrl.ren1 connect issue_slots[10].in_uop.bits.fp_ctrl.wen, issue_slots[11].out_uop.fp_ctrl.wen connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, issue_slots[11].out_uop.fp_ctrl.ldst connect issue_slots[10].in_uop.bits.op2_sel, issue_slots[11].out_uop.op2_sel connect issue_slots[10].in_uop.bits.op1_sel, issue_slots[11].out_uop.op1_sel connect issue_slots[10].in_uop.bits.imm_packed, issue_slots[11].out_uop.imm_packed connect issue_slots[10].in_uop.bits.pimm, issue_slots[11].out_uop.pimm connect issue_slots[10].in_uop.bits.imm_sel, issue_slots[11].out_uop.imm_sel connect issue_slots[10].in_uop.bits.imm_rename, issue_slots[11].out_uop.imm_rename connect issue_slots[10].in_uop.bits.taken, issue_slots[11].out_uop.taken connect issue_slots[10].in_uop.bits.pc_lob, issue_slots[11].out_uop.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, issue_slots[11].out_uop.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, issue_slots[11].out_uop.ftq_idx connect issue_slots[10].in_uop.bits.is_mov, issue_slots[11].out_uop.is_mov connect issue_slots[10].in_uop.bits.is_rocc, issue_slots[11].out_uop.is_rocc connect issue_slots[10].in_uop.bits.is_sys_pc2epc, issue_slots[11].out_uop.is_sys_pc2epc connect issue_slots[10].in_uop.bits.is_eret, issue_slots[11].out_uop.is_eret connect issue_slots[10].in_uop.bits.is_amo, issue_slots[11].out_uop.is_amo connect issue_slots[10].in_uop.bits.is_sfence, issue_slots[11].out_uop.is_sfence connect issue_slots[10].in_uop.bits.is_fencei, issue_slots[11].out_uop.is_fencei connect issue_slots[10].in_uop.bits.is_fence, issue_slots[11].out_uop.is_fence connect issue_slots[10].in_uop.bits.is_sfb, issue_slots[11].out_uop.is_sfb connect issue_slots[10].in_uop.bits.br_type, issue_slots[11].out_uop.br_type connect issue_slots[10].in_uop.bits.br_tag, issue_slots[11].out_uop.br_tag connect issue_slots[10].in_uop.bits.br_mask, issue_slots[11].out_uop.br_mask connect issue_slots[10].in_uop.bits.dis_col_sel, issue_slots[11].out_uop.dis_col_sel connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, issue_slots[11].out_uop.iw_p3_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, issue_slots[11].out_uop.iw_p2_bypass_hint connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, issue_slots[11].out_uop.iw_p1_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, issue_slots[11].out_uop.iw_p2_speculative_child connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, issue_slots[11].out_uop.iw_p1_speculative_child connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, issue_slots[11].out_uop.iw_issued_partial_dgen connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, issue_slots[11].out_uop.iw_issued_partial_agen connect issue_slots[10].in_uop.bits.iw_issued, issue_slots[11].out_uop.iw_issued connect issue_slots[10].in_uop.bits.fu_code[0], issue_slots[11].out_uop.fu_code[0] connect issue_slots[10].in_uop.bits.fu_code[1], issue_slots[11].out_uop.fu_code[1] connect issue_slots[10].in_uop.bits.fu_code[2], issue_slots[11].out_uop.fu_code[2] connect issue_slots[10].in_uop.bits.fu_code[3], issue_slots[11].out_uop.fu_code[3] connect issue_slots[10].in_uop.bits.fu_code[4], issue_slots[11].out_uop.fu_code[4] connect issue_slots[10].in_uop.bits.fu_code[5], issue_slots[11].out_uop.fu_code[5] connect issue_slots[10].in_uop.bits.fu_code[6], issue_slots[11].out_uop.fu_code[6] connect issue_slots[10].in_uop.bits.fu_code[7], issue_slots[11].out_uop.fu_code[7] connect issue_slots[10].in_uop.bits.fu_code[8], issue_slots[11].out_uop.fu_code[8] connect issue_slots[10].in_uop.bits.fu_code[9], issue_slots[11].out_uop.fu_code[9] connect issue_slots[10].in_uop.bits.iq_type[0], issue_slots[11].out_uop.iq_type[0] connect issue_slots[10].in_uop.bits.iq_type[1], issue_slots[11].out_uop.iq_type[1] connect issue_slots[10].in_uop.bits.iq_type[2], issue_slots[11].out_uop.iq_type[2] connect issue_slots[10].in_uop.bits.iq_type[3], issue_slots[11].out_uop.iq_type[3] connect issue_slots[10].in_uop.bits.debug_pc, issue_slots[11].out_uop.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, issue_slots[11].out_uop.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, issue_slots[11].out_uop.debug_inst connect issue_slots[10].in_uop.bits.inst, issue_slots[11].out_uop.inst node _T_117 = eq(shamts_oh[12], UInt<2>(0h2)) when _T_117 : connect issue_slots[10].in_uop.valid, will_be_valid_12 connect issue_slots[10].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[10].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[10].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[10].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[10].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[10].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[10].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[10].in_uop.bits.fp_typ, _WIRE.fp_typ connect issue_slots[10].in_uop.bits.fp_rm, _WIRE.fp_rm connect issue_slots[10].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[10].in_uop.bits.fcn_op, _WIRE.fcn_op connect issue_slots[10].in_uop.bits.fcn_dw, _WIRE.fcn_dw connect issue_slots[10].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[10].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[10].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[10].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[10].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[10].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[10].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[10].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[10].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[10].in_uop.bits.csr_cmd, _WIRE.csr_cmd connect issue_slots[10].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[10].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[10].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[10].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[10].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[10].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[10].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[10].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[10].in_uop.bits.exception, _WIRE.exception connect issue_slots[10].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[10].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[10].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[10].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[10].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[10].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[10].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[10].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[10].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[10].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[10].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[10].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[10].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[10].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[10].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec connect issue_slots[10].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags connect issue_slots[10].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt connect issue_slots[10].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div connect issue_slots[10].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma connect issue_slots[10].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe connect issue_slots[10].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint connect issue_slots[10].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut connect issue_slots[10].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn connect issue_slots[10].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 connect issue_slots[10].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 connect issue_slots[10].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 connect issue_slots[10].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 connect issue_slots[10].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 connect issue_slots[10].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen connect issue_slots[10].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst connect issue_slots[10].in_uop.bits.op2_sel, _WIRE.op2_sel connect issue_slots[10].in_uop.bits.op1_sel, _WIRE.op1_sel connect issue_slots[10].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[10].in_uop.bits.pimm, _WIRE.pimm connect issue_slots[10].in_uop.bits.imm_sel, _WIRE.imm_sel connect issue_slots[10].in_uop.bits.imm_rename, _WIRE.imm_rename connect issue_slots[10].in_uop.bits.taken, _WIRE.taken connect issue_slots[10].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[10].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[10].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[10].in_uop.bits.is_mov, _WIRE.is_mov connect issue_slots[10].in_uop.bits.is_rocc, _WIRE.is_rocc connect issue_slots[10].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[10].in_uop.bits.is_eret, _WIRE.is_eret connect issue_slots[10].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[10].in_uop.bits.is_sfence, _WIRE.is_sfence connect issue_slots[10].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[10].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[10].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[10].in_uop.bits.br_type, _WIRE.br_type connect issue_slots[10].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[10].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[10].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel connect issue_slots[10].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint connect issue_slots[10].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint connect issue_slots[10].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child connect issue_slots[10].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child connect issue_slots[10].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen connect issue_slots[10].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen connect issue_slots[10].in_uop.bits.iw_issued, _WIRE.iw_issued connect issue_slots[10].in_uop.bits.fu_code[0], _WIRE.fu_code[0] connect issue_slots[10].in_uop.bits.fu_code[1], _WIRE.fu_code[1] connect issue_slots[10].in_uop.bits.fu_code[2], _WIRE.fu_code[2] connect issue_slots[10].in_uop.bits.fu_code[3], _WIRE.fu_code[3] connect issue_slots[10].in_uop.bits.fu_code[4], _WIRE.fu_code[4] connect issue_slots[10].in_uop.bits.fu_code[5], _WIRE.fu_code[5] connect issue_slots[10].in_uop.bits.fu_code[6], _WIRE.fu_code[6] connect issue_slots[10].in_uop.bits.fu_code[7], _WIRE.fu_code[7] connect issue_slots[10].in_uop.bits.fu_code[8], _WIRE.fu_code[8] connect issue_slots[10].in_uop.bits.fu_code[9], _WIRE.fu_code[9] connect issue_slots[10].in_uop.bits.iq_type[0], _WIRE.iq_type[0] connect issue_slots[10].in_uop.bits.iq_type[1], _WIRE.iq_type[1] connect issue_slots[10].in_uop.bits.iq_type[2], _WIRE.iq_type[2] connect issue_slots[10].in_uop.bits.iq_type[3], _WIRE.iq_type[3] connect issue_slots[10].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[10].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[10].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[10].in_uop.bits.inst, _WIRE.inst node _issue_slots_10_clear_T = neq(shamts_oh[10], UInt<1>(0h0)) connect issue_slots[10].clear, _issue_slots_10_clear_T connect issue_slots[11].in_uop.valid, UInt<1>(0h0) connect issue_slots[11].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_typ, _WIRE.fp_typ connect issue_slots[11].in_uop.bits.fp_rm, _WIRE.fp_rm connect issue_slots[11].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[11].in_uop.bits.fcn_op, _WIRE.fcn_op connect issue_slots[11].in_uop.bits.fcn_dw, _WIRE.fcn_dw connect issue_slots[11].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[11].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[11].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[11].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[11].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[11].in_uop.bits.csr_cmd, _WIRE.csr_cmd connect issue_slots[11].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[11].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[11].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[11].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[11].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[11].in_uop.bits.exception, _WIRE.exception connect issue_slots[11].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[11].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[11].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[11].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[11].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[11].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[11].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[11].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt connect issue_slots[11].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div connect issue_slots[11].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe connect issue_slots[11].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 connect issue_slots[11].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst connect issue_slots[11].in_uop.bits.op2_sel, _WIRE.op2_sel connect issue_slots[11].in_uop.bits.op1_sel, _WIRE.op1_sel connect issue_slots[11].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[11].in_uop.bits.pimm, _WIRE.pimm connect issue_slots[11].in_uop.bits.imm_sel, _WIRE.imm_sel connect issue_slots[11].in_uop.bits.imm_rename, _WIRE.imm_rename connect issue_slots[11].in_uop.bits.taken, _WIRE.taken connect issue_slots[11].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[11].in_uop.bits.is_mov, _WIRE.is_mov connect issue_slots[11].in_uop.bits.is_rocc, _WIRE.is_rocc connect issue_slots[11].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[11].in_uop.bits.is_eret, _WIRE.is_eret connect issue_slots[11].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[11].in_uop.bits.is_sfence, _WIRE.is_sfence connect issue_slots[11].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[11].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[11].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[11].in_uop.bits.br_type, _WIRE.br_type connect issue_slots[11].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[11].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[11].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen connect issue_slots[11].in_uop.bits.iw_issued, _WIRE.iw_issued connect issue_slots[11].in_uop.bits.fu_code[0], _WIRE.fu_code[0] connect issue_slots[11].in_uop.bits.fu_code[1], _WIRE.fu_code[1] connect issue_slots[11].in_uop.bits.fu_code[2], _WIRE.fu_code[2] connect issue_slots[11].in_uop.bits.fu_code[3], _WIRE.fu_code[3] connect issue_slots[11].in_uop.bits.fu_code[4], _WIRE.fu_code[4] connect issue_slots[11].in_uop.bits.fu_code[5], _WIRE.fu_code[5] connect issue_slots[11].in_uop.bits.fu_code[6], _WIRE.fu_code[6] connect issue_slots[11].in_uop.bits.fu_code[7], _WIRE.fu_code[7] connect issue_slots[11].in_uop.bits.fu_code[8], _WIRE.fu_code[8] connect issue_slots[11].in_uop.bits.fu_code[9], _WIRE.fu_code[9] connect issue_slots[11].in_uop.bits.iq_type[0], _WIRE.iq_type[0] connect issue_slots[11].in_uop.bits.iq_type[1], _WIRE.iq_type[1] connect issue_slots[11].in_uop.bits.iq_type[2], _WIRE.iq_type[2] connect issue_slots[11].in_uop.bits.iq_type[3], _WIRE.iq_type[3] connect issue_slots[11].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[11].in_uop.bits.inst, _WIRE.inst node _T_118 = eq(shamts_oh[12], UInt<1>(0h1)) when _T_118 : connect issue_slots[11].in_uop.valid, will_be_valid_12 connect issue_slots[11].in_uop.bits.debug_tsrc, _WIRE.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, _WIRE.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, _WIRE.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, _WIRE.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, _WIRE.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, _WIRE.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, _WIRE.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_typ, _WIRE.fp_typ connect issue_slots[11].in_uop.bits.fp_rm, _WIRE.fp_rm connect issue_slots[11].in_uop.bits.fp_val, _WIRE.fp_val connect issue_slots[11].in_uop.bits.fcn_op, _WIRE.fcn_op connect issue_slots[11].in_uop.bits.fcn_dw, _WIRE.fcn_dw connect issue_slots[11].in_uop.bits.frs3_en, _WIRE.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, _WIRE.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, _WIRE.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, _WIRE.dst_rtype connect issue_slots[11].in_uop.bits.lrs3, _WIRE.lrs3 connect issue_slots[11].in_uop.bits.lrs2, _WIRE.lrs2 connect issue_slots[11].in_uop.bits.lrs1, _WIRE.lrs1 connect issue_slots[11].in_uop.bits.ldst, _WIRE.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, _WIRE.ldst_is_rs1 connect issue_slots[11].in_uop.bits.csr_cmd, _WIRE.csr_cmd connect issue_slots[11].in_uop.bits.flush_on_commit, _WIRE.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, _WIRE.is_unique connect issue_slots[11].in_uop.bits.uses_stq, _WIRE.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, _WIRE.uses_ldq connect issue_slots[11].in_uop.bits.mem_signed, _WIRE.mem_signed connect issue_slots[11].in_uop.bits.mem_size, _WIRE.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, _WIRE.mem_cmd connect issue_slots[11].in_uop.bits.exc_cause, _WIRE.exc_cause connect issue_slots[11].in_uop.bits.exception, _WIRE.exception connect issue_slots[11].in_uop.bits.stale_pdst, _WIRE.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, _WIRE.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, _WIRE.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, _WIRE.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, _WIRE.prs1_busy connect issue_slots[11].in_uop.bits.ppred, _WIRE.ppred connect issue_slots[11].in_uop.bits.prs3, _WIRE.prs3 connect issue_slots[11].in_uop.bits.prs2, _WIRE.prs2 connect issue_slots[11].in_uop.bits.prs1, _WIRE.prs1 connect issue_slots[11].in_uop.bits.pdst, _WIRE.pdst connect issue_slots[11].in_uop.bits.rxq_idx, _WIRE.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, _WIRE.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, _WIRE.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, _WIRE.rob_idx connect issue_slots[11].in_uop.bits.fp_ctrl.vec, _WIRE.fp_ctrl.vec connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, _WIRE.fp_ctrl.wflags connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, _WIRE.fp_ctrl.sqrt connect issue_slots[11].in_uop.bits.fp_ctrl.div, _WIRE.fp_ctrl.div connect issue_slots[11].in_uop.bits.fp_ctrl.fma, _WIRE.fp_ctrl.fma connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, _WIRE.fp_ctrl.fastpipe connect issue_slots[11].in_uop.bits.fp_ctrl.toint, _WIRE.fp_ctrl.toint connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, _WIRE.fp_ctrl.fromint connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, _WIRE.fp_ctrl.typeTagOut connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, _WIRE.fp_ctrl.typeTagIn connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, _WIRE.fp_ctrl.swap23 connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, _WIRE.fp_ctrl.swap12 connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, _WIRE.fp_ctrl.ren3 connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, _WIRE.fp_ctrl.ren2 connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, _WIRE.fp_ctrl.ren1 connect issue_slots[11].in_uop.bits.fp_ctrl.wen, _WIRE.fp_ctrl.wen connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, _WIRE.fp_ctrl.ldst connect issue_slots[11].in_uop.bits.op2_sel, _WIRE.op2_sel connect issue_slots[11].in_uop.bits.op1_sel, _WIRE.op1_sel connect issue_slots[11].in_uop.bits.imm_packed, _WIRE.imm_packed connect issue_slots[11].in_uop.bits.pimm, _WIRE.pimm connect issue_slots[11].in_uop.bits.imm_sel, _WIRE.imm_sel connect issue_slots[11].in_uop.bits.imm_rename, _WIRE.imm_rename connect issue_slots[11].in_uop.bits.taken, _WIRE.taken connect issue_slots[11].in_uop.bits.pc_lob, _WIRE.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, _WIRE.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, _WIRE.ftq_idx connect issue_slots[11].in_uop.bits.is_mov, _WIRE.is_mov connect issue_slots[11].in_uop.bits.is_rocc, _WIRE.is_rocc connect issue_slots[11].in_uop.bits.is_sys_pc2epc, _WIRE.is_sys_pc2epc connect issue_slots[11].in_uop.bits.is_eret, _WIRE.is_eret connect issue_slots[11].in_uop.bits.is_amo, _WIRE.is_amo connect issue_slots[11].in_uop.bits.is_sfence, _WIRE.is_sfence connect issue_slots[11].in_uop.bits.is_fencei, _WIRE.is_fencei connect issue_slots[11].in_uop.bits.is_fence, _WIRE.is_fence connect issue_slots[11].in_uop.bits.is_sfb, _WIRE.is_sfb connect issue_slots[11].in_uop.bits.br_type, _WIRE.br_type connect issue_slots[11].in_uop.bits.br_tag, _WIRE.br_tag connect issue_slots[11].in_uop.bits.br_mask, _WIRE.br_mask connect issue_slots[11].in_uop.bits.dis_col_sel, _WIRE.dis_col_sel connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, _WIRE.iw_p3_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, _WIRE.iw_p2_bypass_hint connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, _WIRE.iw_p1_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, _WIRE.iw_p2_speculative_child connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, _WIRE.iw_p1_speculative_child connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, _WIRE.iw_issued_partial_dgen connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, _WIRE.iw_issued_partial_agen connect issue_slots[11].in_uop.bits.iw_issued, _WIRE.iw_issued connect issue_slots[11].in_uop.bits.fu_code[0], _WIRE.fu_code[0] connect issue_slots[11].in_uop.bits.fu_code[1], _WIRE.fu_code[1] connect issue_slots[11].in_uop.bits.fu_code[2], _WIRE.fu_code[2] connect issue_slots[11].in_uop.bits.fu_code[3], _WIRE.fu_code[3] connect issue_slots[11].in_uop.bits.fu_code[4], _WIRE.fu_code[4] connect issue_slots[11].in_uop.bits.fu_code[5], _WIRE.fu_code[5] connect issue_slots[11].in_uop.bits.fu_code[6], _WIRE.fu_code[6] connect issue_slots[11].in_uop.bits.fu_code[7], _WIRE.fu_code[7] connect issue_slots[11].in_uop.bits.fu_code[8], _WIRE.fu_code[8] connect issue_slots[11].in_uop.bits.fu_code[9], _WIRE.fu_code[9] connect issue_slots[11].in_uop.bits.iq_type[0], _WIRE.iq_type[0] connect issue_slots[11].in_uop.bits.iq_type[1], _WIRE.iq_type[1] connect issue_slots[11].in_uop.bits.iq_type[2], _WIRE.iq_type[2] connect issue_slots[11].in_uop.bits.iq_type[3], _WIRE.iq_type[3] connect issue_slots[11].in_uop.bits.debug_pc, _WIRE.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, _WIRE.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, _WIRE.debug_inst connect issue_slots[11].in_uop.bits.inst, _WIRE.inst node _T_119 = eq(shamts_oh[13], UInt<2>(0h2)) when _T_119 : connect issue_slots[11].in_uop.valid, will_be_valid_13 connect issue_slots[11].in_uop.bits.debug_tsrc, _WIRE_1.debug_tsrc connect issue_slots[11].in_uop.bits.debug_fsrc, _WIRE_1.debug_fsrc connect issue_slots[11].in_uop.bits.bp_xcpt_if, _WIRE_1.bp_xcpt_if connect issue_slots[11].in_uop.bits.bp_debug_if, _WIRE_1.bp_debug_if connect issue_slots[11].in_uop.bits.xcpt_ma_if, _WIRE_1.xcpt_ma_if connect issue_slots[11].in_uop.bits.xcpt_ae_if, _WIRE_1.xcpt_ae_if connect issue_slots[11].in_uop.bits.xcpt_pf_if, _WIRE_1.xcpt_pf_if connect issue_slots[11].in_uop.bits.fp_typ, _WIRE_1.fp_typ connect issue_slots[11].in_uop.bits.fp_rm, _WIRE_1.fp_rm connect issue_slots[11].in_uop.bits.fp_val, _WIRE_1.fp_val connect issue_slots[11].in_uop.bits.fcn_op, _WIRE_1.fcn_op connect issue_slots[11].in_uop.bits.fcn_dw, _WIRE_1.fcn_dw connect issue_slots[11].in_uop.bits.frs3_en, _WIRE_1.frs3_en connect issue_slots[11].in_uop.bits.lrs2_rtype, _WIRE_1.lrs2_rtype connect issue_slots[11].in_uop.bits.lrs1_rtype, _WIRE_1.lrs1_rtype connect issue_slots[11].in_uop.bits.dst_rtype, _WIRE_1.dst_rtype connect issue_slots[11].in_uop.bits.lrs3, _WIRE_1.lrs3 connect issue_slots[11].in_uop.bits.lrs2, _WIRE_1.lrs2 connect issue_slots[11].in_uop.bits.lrs1, _WIRE_1.lrs1 connect issue_slots[11].in_uop.bits.ldst, _WIRE_1.ldst connect issue_slots[11].in_uop.bits.ldst_is_rs1, _WIRE_1.ldst_is_rs1 connect issue_slots[11].in_uop.bits.csr_cmd, _WIRE_1.csr_cmd connect issue_slots[11].in_uop.bits.flush_on_commit, _WIRE_1.flush_on_commit connect issue_slots[11].in_uop.bits.is_unique, _WIRE_1.is_unique connect issue_slots[11].in_uop.bits.uses_stq, _WIRE_1.uses_stq connect issue_slots[11].in_uop.bits.uses_ldq, _WIRE_1.uses_ldq connect issue_slots[11].in_uop.bits.mem_signed, _WIRE_1.mem_signed connect issue_slots[11].in_uop.bits.mem_size, _WIRE_1.mem_size connect issue_slots[11].in_uop.bits.mem_cmd, _WIRE_1.mem_cmd connect issue_slots[11].in_uop.bits.exc_cause, _WIRE_1.exc_cause connect issue_slots[11].in_uop.bits.exception, _WIRE_1.exception connect issue_slots[11].in_uop.bits.stale_pdst, _WIRE_1.stale_pdst connect issue_slots[11].in_uop.bits.ppred_busy, _WIRE_1.ppred_busy connect issue_slots[11].in_uop.bits.prs3_busy, _WIRE_1.prs3_busy connect issue_slots[11].in_uop.bits.prs2_busy, _WIRE_1.prs2_busy connect issue_slots[11].in_uop.bits.prs1_busy, _WIRE_1.prs1_busy connect issue_slots[11].in_uop.bits.ppred, _WIRE_1.ppred connect issue_slots[11].in_uop.bits.prs3, _WIRE_1.prs3 connect issue_slots[11].in_uop.bits.prs2, _WIRE_1.prs2 connect issue_slots[11].in_uop.bits.prs1, _WIRE_1.prs1 connect issue_slots[11].in_uop.bits.pdst, _WIRE_1.pdst connect issue_slots[11].in_uop.bits.rxq_idx, _WIRE_1.rxq_idx connect issue_slots[11].in_uop.bits.stq_idx, _WIRE_1.stq_idx connect issue_slots[11].in_uop.bits.ldq_idx, _WIRE_1.ldq_idx connect issue_slots[11].in_uop.bits.rob_idx, _WIRE_1.rob_idx connect issue_slots[11].in_uop.bits.fp_ctrl.vec, _WIRE_1.fp_ctrl.vec connect issue_slots[11].in_uop.bits.fp_ctrl.wflags, _WIRE_1.fp_ctrl.wflags connect issue_slots[11].in_uop.bits.fp_ctrl.sqrt, _WIRE_1.fp_ctrl.sqrt connect issue_slots[11].in_uop.bits.fp_ctrl.div, _WIRE_1.fp_ctrl.div connect issue_slots[11].in_uop.bits.fp_ctrl.fma, _WIRE_1.fp_ctrl.fma connect issue_slots[11].in_uop.bits.fp_ctrl.fastpipe, _WIRE_1.fp_ctrl.fastpipe connect issue_slots[11].in_uop.bits.fp_ctrl.toint, _WIRE_1.fp_ctrl.toint connect issue_slots[11].in_uop.bits.fp_ctrl.fromint, _WIRE_1.fp_ctrl.fromint connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagOut, _WIRE_1.fp_ctrl.typeTagOut connect issue_slots[11].in_uop.bits.fp_ctrl.typeTagIn, _WIRE_1.fp_ctrl.typeTagIn connect issue_slots[11].in_uop.bits.fp_ctrl.swap23, _WIRE_1.fp_ctrl.swap23 connect issue_slots[11].in_uop.bits.fp_ctrl.swap12, _WIRE_1.fp_ctrl.swap12 connect issue_slots[11].in_uop.bits.fp_ctrl.ren3, _WIRE_1.fp_ctrl.ren3 connect issue_slots[11].in_uop.bits.fp_ctrl.ren2, _WIRE_1.fp_ctrl.ren2 connect issue_slots[11].in_uop.bits.fp_ctrl.ren1, _WIRE_1.fp_ctrl.ren1 connect issue_slots[11].in_uop.bits.fp_ctrl.wen, _WIRE_1.fp_ctrl.wen connect issue_slots[11].in_uop.bits.fp_ctrl.ldst, _WIRE_1.fp_ctrl.ldst connect issue_slots[11].in_uop.bits.op2_sel, _WIRE_1.op2_sel connect issue_slots[11].in_uop.bits.op1_sel, _WIRE_1.op1_sel connect issue_slots[11].in_uop.bits.imm_packed, _WIRE_1.imm_packed connect issue_slots[11].in_uop.bits.pimm, _WIRE_1.pimm connect issue_slots[11].in_uop.bits.imm_sel, _WIRE_1.imm_sel connect issue_slots[11].in_uop.bits.imm_rename, _WIRE_1.imm_rename connect issue_slots[11].in_uop.bits.taken, _WIRE_1.taken connect issue_slots[11].in_uop.bits.pc_lob, _WIRE_1.pc_lob connect issue_slots[11].in_uop.bits.edge_inst, _WIRE_1.edge_inst connect issue_slots[11].in_uop.bits.ftq_idx, _WIRE_1.ftq_idx connect issue_slots[11].in_uop.bits.is_mov, _WIRE_1.is_mov connect issue_slots[11].in_uop.bits.is_rocc, _WIRE_1.is_rocc connect issue_slots[11].in_uop.bits.is_sys_pc2epc, _WIRE_1.is_sys_pc2epc connect issue_slots[11].in_uop.bits.is_eret, _WIRE_1.is_eret connect issue_slots[11].in_uop.bits.is_amo, _WIRE_1.is_amo connect issue_slots[11].in_uop.bits.is_sfence, _WIRE_1.is_sfence connect issue_slots[11].in_uop.bits.is_fencei, _WIRE_1.is_fencei connect issue_slots[11].in_uop.bits.is_fence, _WIRE_1.is_fence connect issue_slots[11].in_uop.bits.is_sfb, _WIRE_1.is_sfb connect issue_slots[11].in_uop.bits.br_type, _WIRE_1.br_type connect issue_slots[11].in_uop.bits.br_tag, _WIRE_1.br_tag connect issue_slots[11].in_uop.bits.br_mask, _WIRE_1.br_mask connect issue_slots[11].in_uop.bits.dis_col_sel, _WIRE_1.dis_col_sel connect issue_slots[11].in_uop.bits.iw_p3_bypass_hint, _WIRE_1.iw_p3_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_bypass_hint, _WIRE_1.iw_p2_bypass_hint connect issue_slots[11].in_uop.bits.iw_p1_bypass_hint, _WIRE_1.iw_p1_bypass_hint connect issue_slots[11].in_uop.bits.iw_p2_speculative_child, _WIRE_1.iw_p2_speculative_child connect issue_slots[11].in_uop.bits.iw_p1_speculative_child, _WIRE_1.iw_p1_speculative_child connect issue_slots[11].in_uop.bits.iw_issued_partial_dgen, _WIRE_1.iw_issued_partial_dgen connect issue_slots[11].in_uop.bits.iw_issued_partial_agen, _WIRE_1.iw_issued_partial_agen connect issue_slots[11].in_uop.bits.iw_issued, _WIRE_1.iw_issued connect issue_slots[11].in_uop.bits.fu_code[0], _WIRE_1.fu_code[0] connect issue_slots[11].in_uop.bits.fu_code[1], _WIRE_1.fu_code[1] connect issue_slots[11].in_uop.bits.fu_code[2], _WIRE_1.fu_code[2] connect issue_slots[11].in_uop.bits.fu_code[3], _WIRE_1.fu_code[3] connect issue_slots[11].in_uop.bits.fu_code[4], _WIRE_1.fu_code[4] connect issue_slots[11].in_uop.bits.fu_code[5], _WIRE_1.fu_code[5] connect issue_slots[11].in_uop.bits.fu_code[6], _WIRE_1.fu_code[6] connect issue_slots[11].in_uop.bits.fu_code[7], _WIRE_1.fu_code[7] connect issue_slots[11].in_uop.bits.fu_code[8], _WIRE_1.fu_code[8] connect issue_slots[11].in_uop.bits.fu_code[9], _WIRE_1.fu_code[9] connect issue_slots[11].in_uop.bits.iq_type[0], _WIRE_1.iq_type[0] connect issue_slots[11].in_uop.bits.iq_type[1], _WIRE_1.iq_type[1] connect issue_slots[11].in_uop.bits.iq_type[2], _WIRE_1.iq_type[2] connect issue_slots[11].in_uop.bits.iq_type[3], _WIRE_1.iq_type[3] connect issue_slots[11].in_uop.bits.debug_pc, _WIRE_1.debug_pc connect issue_slots[11].in_uop.bits.is_rvc, _WIRE_1.is_rvc connect issue_slots[11].in_uop.bits.debug_inst, _WIRE_1.debug_inst connect issue_slots[11].in_uop.bits.inst, _WIRE_1.inst node _issue_slots_11_clear_T = neq(shamts_oh[11], UInt<1>(0h0)) connect issue_slots[11].clear, _issue_slots_11_clear_T reg is_available : UInt<1>[12], clock node _T_120 = eq(issue_slots[0].will_be_valid, UInt<1>(0h0)) node _T_121 = or(_T_120, issue_slots[0].clear) node _T_122 = eq(issue_slots[0].in_uop.valid, UInt<1>(0h0)) node _T_123 = and(_T_121, _T_122) node _T_124 = eq(issue_slots[1].will_be_valid, UInt<1>(0h0)) node _T_125 = or(_T_124, issue_slots[1].clear) node _T_126 = eq(issue_slots[1].in_uop.valid, UInt<1>(0h0)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(issue_slots[2].will_be_valid, UInt<1>(0h0)) node _T_129 = or(_T_128, issue_slots[2].clear) node _T_130 = eq(issue_slots[2].in_uop.valid, UInt<1>(0h0)) node _T_131 = and(_T_129, _T_130) node _T_132 = eq(issue_slots[3].will_be_valid, UInt<1>(0h0)) node _T_133 = or(_T_132, issue_slots[3].clear) node _T_134 = eq(issue_slots[3].in_uop.valid, UInt<1>(0h0)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(issue_slots[4].will_be_valid, UInt<1>(0h0)) node _T_137 = or(_T_136, issue_slots[4].clear) node _T_138 = eq(issue_slots[4].in_uop.valid, UInt<1>(0h0)) node _T_139 = and(_T_137, _T_138) node _T_140 = eq(issue_slots[5].will_be_valid, UInt<1>(0h0)) node _T_141 = or(_T_140, issue_slots[5].clear) node _T_142 = eq(issue_slots[5].in_uop.valid, UInt<1>(0h0)) node _T_143 = and(_T_141, _T_142) node _T_144 = eq(issue_slots[6].will_be_valid, UInt<1>(0h0)) node _T_145 = or(_T_144, issue_slots[6].clear) node _T_146 = eq(issue_slots[6].in_uop.valid, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(issue_slots[7].will_be_valid, UInt<1>(0h0)) node _T_149 = or(_T_148, issue_slots[7].clear) node _T_150 = eq(issue_slots[7].in_uop.valid, UInt<1>(0h0)) node _T_151 = and(_T_149, _T_150) node _T_152 = eq(issue_slots[8].will_be_valid, UInt<1>(0h0)) node _T_153 = or(_T_152, issue_slots[8].clear) node _T_154 = eq(issue_slots[8].in_uop.valid, UInt<1>(0h0)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(issue_slots[9].will_be_valid, UInt<1>(0h0)) node _T_157 = or(_T_156, issue_slots[9].clear) node _T_158 = eq(issue_slots[9].in_uop.valid, UInt<1>(0h0)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(issue_slots[10].will_be_valid, UInt<1>(0h0)) node _T_161 = or(_T_160, issue_slots[10].clear) node _T_162 = eq(issue_slots[10].in_uop.valid, UInt<1>(0h0)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(issue_slots[11].will_be_valid, UInt<1>(0h0)) node _T_165 = or(_T_164, issue_slots[11].clear) node _T_166 = eq(issue_slots[11].in_uop.valid, UInt<1>(0h0)) node _T_167 = and(_T_165, _T_166) wire _WIRE_12 : UInt<1>[12] connect _WIRE_12[0], _T_123 connect _WIRE_12[1], _T_127 connect _WIRE_12[2], _T_131 connect _WIRE_12[3], _T_135 connect _WIRE_12[4], _T_139 connect _WIRE_12[5], _T_143 connect _WIRE_12[6], _T_147 connect _WIRE_12[7], _T_151 connect _WIRE_12[8], _T_155 connect _WIRE_12[9], _T_159 connect _WIRE_12[10], _T_163 connect _WIRE_12[11], _T_167 connect is_available, _WIRE_12 node _io_dis_uops_0_ready_T = add(is_available[1], is_available[2]) node _io_dis_uops_0_ready_T_1 = bits(_io_dis_uops_0_ready_T, 1, 0) node _io_dis_uops_0_ready_T_2 = add(is_available[0], _io_dis_uops_0_ready_T_1) node _io_dis_uops_0_ready_T_3 = bits(_io_dis_uops_0_ready_T_2, 1, 0) node _io_dis_uops_0_ready_T_4 = add(is_available[4], is_available[5]) node _io_dis_uops_0_ready_T_5 = bits(_io_dis_uops_0_ready_T_4, 1, 0) node _io_dis_uops_0_ready_T_6 = add(is_available[3], _io_dis_uops_0_ready_T_5) node _io_dis_uops_0_ready_T_7 = bits(_io_dis_uops_0_ready_T_6, 1, 0) node _io_dis_uops_0_ready_T_8 = add(_io_dis_uops_0_ready_T_3, _io_dis_uops_0_ready_T_7) node _io_dis_uops_0_ready_T_9 = bits(_io_dis_uops_0_ready_T_8, 2, 0) node _io_dis_uops_0_ready_T_10 = add(is_available[7], is_available[8]) node _io_dis_uops_0_ready_T_11 = bits(_io_dis_uops_0_ready_T_10, 1, 0) node _io_dis_uops_0_ready_T_12 = add(is_available[6], _io_dis_uops_0_ready_T_11) node _io_dis_uops_0_ready_T_13 = bits(_io_dis_uops_0_ready_T_12, 1, 0) node _io_dis_uops_0_ready_T_14 = add(is_available[10], is_available[11]) node _io_dis_uops_0_ready_T_15 = bits(_io_dis_uops_0_ready_T_14, 1, 0) node _io_dis_uops_0_ready_T_16 = add(is_available[9], _io_dis_uops_0_ready_T_15) node _io_dis_uops_0_ready_T_17 = bits(_io_dis_uops_0_ready_T_16, 1, 0) node _io_dis_uops_0_ready_T_18 = add(_io_dis_uops_0_ready_T_13, _io_dis_uops_0_ready_T_17) node _io_dis_uops_0_ready_T_19 = bits(_io_dis_uops_0_ready_T_18, 2, 0) node _io_dis_uops_0_ready_T_20 = add(_io_dis_uops_0_ready_T_9, _io_dis_uops_0_ready_T_19) node _io_dis_uops_0_ready_T_21 = bits(_io_dis_uops_0_ready_T_20, 3, 0) node _io_dis_uops_0_ready_T_22 = and(io.dis_uops[0].ready, io.dis_uops[0].valid) node _io_dis_uops_0_ready_T_23 = and(io.dis_uops[1].ready, io.dis_uops[1].valid) node _io_dis_uops_0_ready_T_24 = add(_io_dis_uops_0_ready_T_22, _io_dis_uops_0_ready_T_23) node _io_dis_uops_0_ready_T_25 = bits(_io_dis_uops_0_ready_T_24, 1, 0) node _io_dis_uops_0_ready_T_26 = add(UInt<4>(0h0), _io_dis_uops_0_ready_T_25) node _io_dis_uops_0_ready_T_27 = tail(_io_dis_uops_0_ready_T_26, 1) node _io_dis_uops_0_ready_T_28 = gt(_io_dis_uops_0_ready_T_21, _io_dis_uops_0_ready_T_27) reg io_dis_uops_0_ready_REG : UInt<1>, clock connect io_dis_uops_0_ready_REG, _io_dis_uops_0_ready_T_28 connect io.dis_uops[0].ready, io_dis_uops_0_ready_REG node _T_168 = eq(io.dis_uops[0].ready, UInt<1>(0h0)) node _T_169 = shr(shamts_oh[12], 0) node _T_170 = neq(_T_169, UInt<1>(0h0)) node _T_171 = or(_T_168, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:214 assert (!io.dis_uops(w).ready \|\| (shamts_oh(w+numIssueSlots) >> w) =/= 0.U)\n") : printf_3 assert(clock, _T_171, UInt<1>(0h1), "") : assert_3 node _io_dis_uops_1_ready_T = add(is_available[1], is_available[2]) node _io_dis_uops_1_ready_T_1 = bits(_io_dis_uops_1_ready_T, 1, 0) node _io_dis_uops_1_ready_T_2 = add(is_available[0], _io_dis_uops_1_ready_T_1) node _io_dis_uops_1_ready_T_3 = bits(_io_dis_uops_1_ready_T_2, 1, 0) node _io_dis_uops_1_ready_T_4 = add(is_available[4], is_available[5]) node _io_dis_uops_1_ready_T_5 = bits(_io_dis_uops_1_ready_T_4, 1, 0) node _io_dis_uops_1_ready_T_6 = add(is_available[3], _io_dis_uops_1_ready_T_5) node _io_dis_uops_1_ready_T_7 = bits(_io_dis_uops_1_ready_T_6, 1, 0) node _io_dis_uops_1_ready_T_8 = add(_io_dis_uops_1_ready_T_3, _io_dis_uops_1_ready_T_7) node _io_dis_uops_1_ready_T_9 = bits(_io_dis_uops_1_ready_T_8, 2, 0) node _io_dis_uops_1_ready_T_10 = add(is_available[7], is_available[8]) node _io_dis_uops_1_ready_T_11 = bits(_io_dis_uops_1_ready_T_10, 1, 0) node _io_dis_uops_1_ready_T_12 = add(is_available[6], _io_dis_uops_1_ready_T_11) node _io_dis_uops_1_ready_T_13 = bits(_io_dis_uops_1_ready_T_12, 1, 0) node _io_dis_uops_1_ready_T_14 = add(is_available[10], is_available[11]) node _io_dis_uops_1_ready_T_15 = bits(_io_dis_uops_1_ready_T_14, 1, 0) node _io_dis_uops_1_ready_T_16 = add(is_available[9], _io_dis_uops_1_ready_T_15) node _io_dis_uops_1_ready_T_17 = bits(_io_dis_uops_1_ready_T_16, 1, 0) node _io_dis_uops_1_ready_T_18 = add(_io_dis_uops_1_ready_T_13, _io_dis_uops_1_ready_T_17) node _io_dis_uops_1_ready_T_19 = bits(_io_dis_uops_1_ready_T_18, 2, 0) node _io_dis_uops_1_ready_T_20 = add(_io_dis_uops_1_ready_T_9, _io_dis_uops_1_ready_T_19) node _io_dis_uops_1_ready_T_21 = bits(_io_dis_uops_1_ready_T_20, 3, 0) node _io_dis_uops_1_ready_T_22 = and(io.dis_uops[0].ready, io.dis_uops[0].valid) node _io_dis_uops_1_ready_T_23 = and(io.dis_uops[1].ready, io.dis_uops[1].valid) node _io_dis_uops_1_ready_T_24 = add(_io_dis_uops_1_ready_T_22, _io_dis_uops_1_ready_T_23) node _io_dis_uops_1_ready_T_25 = bits(_io_dis_uops_1_ready_T_24, 1, 0) node _io_dis_uops_1_ready_T_26 = add(UInt<4>(0h1), _io_dis_uops_1_ready_T_25) node _io_dis_uops_1_ready_T_27 = tail(_io_dis_uops_1_ready_T_26, 1) node _io_dis_uops_1_ready_T_28 = gt(_io_dis_uops_1_ready_T_21, _io_dis_uops_1_ready_T_27) reg io_dis_uops_1_ready_REG : UInt<1>, clock connect io_dis_uops_1_ready_REG, _io_dis_uops_1_ready_T_28 connect io.dis_uops[1].ready, io_dis_uops_1_ready_REG node _T_175 = eq(io.dis_uops[1].ready, UInt<1>(0h0)) node _T_176 = shr(shamts_oh[13], 1) node _T_177 = neq(_T_176, UInt<1>(0h0)) node _T_178 = or(_T_175, _T_177) node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(_T_178, UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-unit-age-ordered.scala:214 assert (!io.dis_uops(w).ready \|\| (shamts_oh(w+numIssueSlots) >> w) =/= 0.U)\n") : printf_4 assert(clock, _T_178, UInt<1>(0h1), "") : assert_4 wire iss_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[1] connect iss_uops[0].valid, UInt<1>(0h0) invalidate iss_uops[0].bits.debug_tsrc invalidate iss_uops[0].bits.debug_fsrc invalidate iss_uops[0].bits.bp_xcpt_if invalidate iss_uops[0].bits.bp_debug_if invalidate iss_uops[0].bits.xcpt_ma_if invalidate iss_uops[0].bits.xcpt_ae_if invalidate iss_uops[0].bits.xcpt_pf_if invalidate iss_uops[0].bits.fp_typ invalidate iss_uops[0].bits.fp_rm invalidate iss_uops[0].bits.fp_val invalidate iss_uops[0].bits.fcn_op invalidate iss_uops[0].bits.fcn_dw invalidate iss_uops[0].bits.frs3_en invalidate iss_uops[0].bits.lrs2_rtype invalidate iss_uops[0].bits.lrs1_rtype invalidate iss_uops[0].bits.dst_rtype invalidate iss_uops[0].bits.lrs3 invalidate iss_uops[0].bits.lrs2 invalidate iss_uops[0].bits.lrs1 invalidate iss_uops[0].bits.ldst invalidate iss_uops[0].bits.ldst_is_rs1 invalidate iss_uops[0].bits.csr_cmd invalidate iss_uops[0].bits.flush_on_commit invalidate iss_uops[0].bits.is_unique invalidate iss_uops[0].bits.uses_stq invalidate iss_uops[0].bits.uses_ldq invalidate iss_uops[0].bits.mem_signed invalidate iss_uops[0].bits.mem_size invalidate iss_uops[0].bits.mem_cmd invalidate iss_uops[0].bits.exc_cause invalidate iss_uops[0].bits.exception invalidate iss_uops[0].bits.stale_pdst invalidate iss_uops[0].bits.ppred_busy invalidate iss_uops[0].bits.prs3_busy invalidate iss_uops[0].bits.prs2_busy invalidate iss_uops[0].bits.prs1_busy invalidate iss_uops[0].bits.ppred invalidate iss_uops[0].bits.prs3 invalidate iss_uops[0].bits.prs2 invalidate iss_uops[0].bits.prs1 invalidate iss_uops[0].bits.pdst invalidate iss_uops[0].bits.rxq_idx invalidate iss_uops[0].bits.stq_idx invalidate iss_uops[0].bits.ldq_idx invalidate iss_uops[0].bits.rob_idx invalidate iss_uops[0].bits.fp_ctrl.vec invalidate iss_uops[0].bits.fp_ctrl.wflags invalidate iss_uops[0].bits.fp_ctrl.sqrt invalidate iss_uops[0].bits.fp_ctrl.div invalidate iss_uops[0].bits.fp_ctrl.fma invalidate iss_uops[0].bits.fp_ctrl.fastpipe invalidate iss_uops[0].bits.fp_ctrl.toint invalidate iss_uops[0].bits.fp_ctrl.fromint invalidate iss_uops[0].bits.fp_ctrl.typeTagOut invalidate iss_uops[0].bits.fp_ctrl.typeTagIn invalidate iss_uops[0].bits.fp_ctrl.swap23 invalidate iss_uops[0].bits.fp_ctrl.swap12 invalidate iss_uops[0].bits.fp_ctrl.ren3 invalidate iss_uops[0].bits.fp_ctrl.ren2 invalidate iss_uops[0].bits.fp_ctrl.ren1 invalidate iss_uops[0].bits.fp_ctrl.wen invalidate iss_uops[0].bits.fp_ctrl.ldst invalidate iss_uops[0].bits.op2_sel invalidate iss_uops[0].bits.op1_sel invalidate iss_uops[0].bits.imm_packed invalidate iss_uops[0].bits.pimm invalidate iss_uops[0].bits.imm_sel invalidate iss_uops[0].bits.imm_rename invalidate iss_uops[0].bits.taken invalidate iss_uops[0].bits.pc_lob invalidate iss_uops[0].bits.edge_inst invalidate iss_uops[0].bits.ftq_idx invalidate iss_uops[0].bits.is_mov invalidate iss_uops[0].bits.is_rocc invalidate iss_uops[0].bits.is_sys_pc2epc invalidate iss_uops[0].bits.is_eret invalidate iss_uops[0].bits.is_amo invalidate iss_uops[0].bits.is_sfence invalidate iss_uops[0].bits.is_fencei invalidate iss_uops[0].bits.is_fence invalidate iss_uops[0].bits.is_sfb invalidate iss_uops[0].bits.br_type invalidate iss_uops[0].bits.br_tag invalidate iss_uops[0].bits.br_mask invalidate iss_uops[0].bits.dis_col_sel invalidate iss_uops[0].bits.iw_p3_bypass_hint invalidate iss_uops[0].bits.iw_p2_bypass_hint invalidate iss_uops[0].bits.iw_p1_bypass_hint invalidate iss_uops[0].bits.iw_p2_speculative_child invalidate iss_uops[0].bits.iw_p1_speculative_child invalidate iss_uops[0].bits.iw_issued_partial_dgen invalidate iss_uops[0].bits.iw_issued_partial_agen invalidate iss_uops[0].bits.iw_issued invalidate iss_uops[0].bits.fu_code[0] invalidate iss_uops[0].bits.fu_code[1] invalidate iss_uops[0].bits.fu_code[2] invalidate iss_uops[0].bits.fu_code[3] invalidate iss_uops[0].bits.fu_code[4] invalidate iss_uops[0].bits.fu_code[5] invalidate iss_uops[0].bits.fu_code[6] invalidate iss_uops[0].bits.fu_code[7] invalidate iss_uops[0].bits.fu_code[8] invalidate iss_uops[0].bits.fu_code[9] invalidate iss_uops[0].bits.iq_type[0] invalidate iss_uops[0].bits.iq_type[1] invalidate iss_uops[0].bits.iq_type[2] invalidate iss_uops[0].bits.iq_type[3] invalidate iss_uops[0].bits.debug_pc invalidate iss_uops[0].bits.is_rvc invalidate iss_uops[0].bits.debug_inst invalidate iss_uops[0].bits.inst connect issue_slots[0].grant, UInt<1>(0h0) node _fu_code_match_T = and(issue_slots[0].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_1 = and(issue_slots[0].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_2 = and(issue_slots[0].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_3 = and(issue_slots[0].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_4 = and(issue_slots[0].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_5 = and(issue_slots[0].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_6 = and(issue_slots[0].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_7 = and(issue_slots[0].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_8 = and(issue_slots[0].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_9 = and(issue_slots[0].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_10 = or(_fu_code_match_T, _fu_code_match_T_1) node _fu_code_match_T_11 = or(_fu_code_match_T_10, _fu_code_match_T_2) node _fu_code_match_T_12 = or(_fu_code_match_T_11, _fu_code_match_T_3) node _fu_code_match_T_13 = or(_fu_code_match_T_12, _fu_code_match_T_4) node _fu_code_match_T_14 = or(_fu_code_match_T_13, _fu_code_match_T_5) node _fu_code_match_T_15 = or(_fu_code_match_T_14, _fu_code_match_T_6) node _fu_code_match_T_16 = or(_fu_code_match_T_15, _fu_code_match_T_7) node _fu_code_match_T_17 = or(_fu_code_match_T_16, _fu_code_match_T_8) node fu_code_match = or(_fu_code_match_T_17, _fu_code_match_T_9) node can_allocate = and(fu_code_match, UInt<1>(0h1)) node _T_182 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_183 = and(issue_slots[0].request, _T_182) node _T_184 = and(_T_183, can_allocate) node _T_185 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_186 = and(_T_184, _T_185) when _T_186 : connect issue_slots[0].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[0].iss_uop node _T_187 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_188 = and(issue_slots[0].request, _T_187) node _T_189 = and(_T_188, can_allocate) node _T_190 = or(_T_189, UInt<1>(0h0)) node _T_191 = and(issue_slots[0].request, can_allocate) node _T_192 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = and(_T_191, _T_192) node _T_194 = or(_T_193, UInt<1>(0h0)) connect issue_slots[1].grant, UInt<1>(0h0) node _fu_code_match_T_18 = and(issue_slots[1].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_19 = and(issue_slots[1].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_20 = and(issue_slots[1].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_21 = and(issue_slots[1].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_22 = and(issue_slots[1].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_23 = and(issue_slots[1].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_24 = and(issue_slots[1].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_25 = and(issue_slots[1].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_26 = and(issue_slots[1].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_27 = and(issue_slots[1].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_28 = or(_fu_code_match_T_18, _fu_code_match_T_19) node _fu_code_match_T_29 = or(_fu_code_match_T_28, _fu_code_match_T_20) node _fu_code_match_T_30 = or(_fu_code_match_T_29, _fu_code_match_T_21) node _fu_code_match_T_31 = or(_fu_code_match_T_30, _fu_code_match_T_22) node _fu_code_match_T_32 = or(_fu_code_match_T_31, _fu_code_match_T_23) node _fu_code_match_T_33 = or(_fu_code_match_T_32, _fu_code_match_T_24) node _fu_code_match_T_34 = or(_fu_code_match_T_33, _fu_code_match_T_25) node _fu_code_match_T_35 = or(_fu_code_match_T_34, _fu_code_match_T_26) node fu_code_match_1 = or(_fu_code_match_T_35, _fu_code_match_T_27) node can_allocate_1 = and(fu_code_match_1, UInt<1>(0h1)) node _T_195 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_196 = and(issue_slots[1].request, _T_195) node _T_197 = and(_T_196, can_allocate_1) node _T_198 = eq(_T_190, UInt<1>(0h0)) node _T_199 = and(_T_197, _T_198) when _T_199 : connect issue_slots[1].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[1].iss_uop node _T_200 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_201 = and(issue_slots[1].request, _T_200) node _T_202 = and(_T_201, can_allocate_1) node _T_203 = or(_T_202, _T_190) node _T_204 = and(issue_slots[1].request, can_allocate_1) node _T_205 = eq(_T_190, UInt<1>(0h0)) node _T_206 = and(_T_204, _T_205) node _T_207 = or(_T_206, UInt<1>(0h0)) connect issue_slots[2].grant, UInt<1>(0h0) node _fu_code_match_T_36 = and(issue_slots[2].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_37 = and(issue_slots[2].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_38 = and(issue_slots[2].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_39 = and(issue_slots[2].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_40 = and(issue_slots[2].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_41 = and(issue_slots[2].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_42 = and(issue_slots[2].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_43 = and(issue_slots[2].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_44 = and(issue_slots[2].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_45 = and(issue_slots[2].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_46 = or(_fu_code_match_T_36, _fu_code_match_T_37) node _fu_code_match_T_47 = or(_fu_code_match_T_46, _fu_code_match_T_38) node _fu_code_match_T_48 = or(_fu_code_match_T_47, _fu_code_match_T_39) node _fu_code_match_T_49 = or(_fu_code_match_T_48, _fu_code_match_T_40) node _fu_code_match_T_50 = or(_fu_code_match_T_49, _fu_code_match_T_41) node _fu_code_match_T_51 = or(_fu_code_match_T_50, _fu_code_match_T_42) node _fu_code_match_T_52 = or(_fu_code_match_T_51, _fu_code_match_T_43) node _fu_code_match_T_53 = or(_fu_code_match_T_52, _fu_code_match_T_44) node fu_code_match_2 = or(_fu_code_match_T_53, _fu_code_match_T_45) node can_allocate_2 = and(fu_code_match_2, UInt<1>(0h1)) node _T_208 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = and(issue_slots[2].request, _T_208) node _T_210 = and(_T_209, can_allocate_2) node _T_211 = eq(_T_203, UInt<1>(0h0)) node _T_212 = and(_T_210, _T_211) when _T_212 : connect issue_slots[2].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[2].iss_uop node _T_213 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = and(issue_slots[2].request, _T_213) node _T_215 = and(_T_214, can_allocate_2) node _T_216 = or(_T_215, _T_203) node _T_217 = and(issue_slots[2].request, can_allocate_2) node _T_218 = eq(_T_203, UInt<1>(0h0)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(_T_219, UInt<1>(0h0)) connect issue_slots[3].grant, UInt<1>(0h0) node _fu_code_match_T_54 = and(issue_slots[3].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_55 = and(issue_slots[3].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_56 = and(issue_slots[3].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_57 = and(issue_slots[3].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_58 = and(issue_slots[3].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_59 = and(issue_slots[3].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_60 = and(issue_slots[3].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_61 = and(issue_slots[3].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_62 = and(issue_slots[3].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_63 = and(issue_slots[3].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_64 = or(_fu_code_match_T_54, _fu_code_match_T_55) node _fu_code_match_T_65 = or(_fu_code_match_T_64, _fu_code_match_T_56) node _fu_code_match_T_66 = or(_fu_code_match_T_65, _fu_code_match_T_57) node _fu_code_match_T_67 = or(_fu_code_match_T_66, _fu_code_match_T_58) node _fu_code_match_T_68 = or(_fu_code_match_T_67, _fu_code_match_T_59) node _fu_code_match_T_69 = or(_fu_code_match_T_68, _fu_code_match_T_60) node _fu_code_match_T_70 = or(_fu_code_match_T_69, _fu_code_match_T_61) node _fu_code_match_T_71 = or(_fu_code_match_T_70, _fu_code_match_T_62) node fu_code_match_3 = or(_fu_code_match_T_71, _fu_code_match_T_63) node can_allocate_3 = and(fu_code_match_3, UInt<1>(0h1)) node _T_221 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_222 = and(issue_slots[3].request, _T_221) node _T_223 = and(_T_222, can_allocate_3) node _T_224 = eq(_T_216, UInt<1>(0h0)) node _T_225 = and(_T_223, _T_224) when _T_225 : connect issue_slots[3].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[3].iss_uop node _T_226 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_227 = and(issue_slots[3].request, _T_226) node _T_228 = and(_T_227, can_allocate_3) node _T_229 = or(_T_228, _T_216) node _T_230 = and(issue_slots[3].request, can_allocate_3) node _T_231 = eq(_T_216, UInt<1>(0h0)) node _T_232 = and(_T_230, _T_231) node _T_233 = or(_T_232, UInt<1>(0h0)) connect issue_slots[4].grant, UInt<1>(0h0) node _fu_code_match_T_72 = and(issue_slots[4].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_73 = and(issue_slots[4].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_74 = and(issue_slots[4].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_75 = and(issue_slots[4].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_76 = and(issue_slots[4].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_77 = and(issue_slots[4].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_78 = and(issue_slots[4].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_79 = and(issue_slots[4].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_80 = and(issue_slots[4].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_81 = and(issue_slots[4].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_82 = or(_fu_code_match_T_72, _fu_code_match_T_73) node _fu_code_match_T_83 = or(_fu_code_match_T_82, _fu_code_match_T_74) node _fu_code_match_T_84 = or(_fu_code_match_T_83, _fu_code_match_T_75) node _fu_code_match_T_85 = or(_fu_code_match_T_84, _fu_code_match_T_76) node _fu_code_match_T_86 = or(_fu_code_match_T_85, _fu_code_match_T_77) node _fu_code_match_T_87 = or(_fu_code_match_T_86, _fu_code_match_T_78) node _fu_code_match_T_88 = or(_fu_code_match_T_87, _fu_code_match_T_79) node _fu_code_match_T_89 = or(_fu_code_match_T_88, _fu_code_match_T_80) node fu_code_match_4 = or(_fu_code_match_T_89, _fu_code_match_T_81) node can_allocate_4 = and(fu_code_match_4, UInt<1>(0h1)) node _T_234 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_235 = and(issue_slots[4].request, _T_234) node _T_236 = and(_T_235, can_allocate_4) node _T_237 = eq(_T_229, UInt<1>(0h0)) node _T_238 = and(_T_236, _T_237) when _T_238 : connect issue_slots[4].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[4].iss_uop node _T_239 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_240 = and(issue_slots[4].request, _T_239) node _T_241 = and(_T_240, can_allocate_4) node _T_242 = or(_T_241, _T_229) node _T_243 = and(issue_slots[4].request, can_allocate_4) node _T_244 = eq(_T_229, UInt<1>(0h0)) node _T_245 = and(_T_243, _T_244) node _T_246 = or(_T_245, UInt<1>(0h0)) connect issue_slots[5].grant, UInt<1>(0h0) node _fu_code_match_T_90 = and(issue_slots[5].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_91 = and(issue_slots[5].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_92 = and(issue_slots[5].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_93 = and(issue_slots[5].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_94 = and(issue_slots[5].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_95 = and(issue_slots[5].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_96 = and(issue_slots[5].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_97 = and(issue_slots[5].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_98 = and(issue_slots[5].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_99 = and(issue_slots[5].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_100 = or(_fu_code_match_T_90, _fu_code_match_T_91) node _fu_code_match_T_101 = or(_fu_code_match_T_100, _fu_code_match_T_92) node _fu_code_match_T_102 = or(_fu_code_match_T_101, _fu_code_match_T_93) node _fu_code_match_T_103 = or(_fu_code_match_T_102, _fu_code_match_T_94) node _fu_code_match_T_104 = or(_fu_code_match_T_103, _fu_code_match_T_95) node _fu_code_match_T_105 = or(_fu_code_match_T_104, _fu_code_match_T_96) node _fu_code_match_T_106 = or(_fu_code_match_T_105, _fu_code_match_T_97) node _fu_code_match_T_107 = or(_fu_code_match_T_106, _fu_code_match_T_98) node fu_code_match_5 = or(_fu_code_match_T_107, _fu_code_match_T_99) node can_allocate_5 = and(fu_code_match_5, UInt<1>(0h1)) node _T_247 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_248 = and(issue_slots[5].request, _T_247) node _T_249 = and(_T_248, can_allocate_5) node _T_250 = eq(_T_242, UInt<1>(0h0)) node _T_251 = and(_T_249, _T_250) when _T_251 : connect issue_slots[5].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[5].iss_uop node _T_252 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_253 = and(issue_slots[5].request, _T_252) node _T_254 = and(_T_253, can_allocate_5) node _T_255 = or(_T_254, _T_242) node _T_256 = and(issue_slots[5].request, can_allocate_5) node _T_257 = eq(_T_242, UInt<1>(0h0)) node _T_258 = and(_T_256, _T_257) node _T_259 = or(_T_258, UInt<1>(0h0)) connect issue_slots[6].grant, UInt<1>(0h0) node _fu_code_match_T_108 = and(issue_slots[6].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_109 = and(issue_slots[6].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_110 = and(issue_slots[6].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_111 = and(issue_slots[6].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_112 = and(issue_slots[6].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_113 = and(issue_slots[6].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_114 = and(issue_slots[6].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_115 = and(issue_slots[6].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_116 = and(issue_slots[6].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_117 = and(issue_slots[6].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_118 = or(_fu_code_match_T_108, _fu_code_match_T_109) node _fu_code_match_T_119 = or(_fu_code_match_T_118, _fu_code_match_T_110) node _fu_code_match_T_120 = or(_fu_code_match_T_119, _fu_code_match_T_111) node _fu_code_match_T_121 = or(_fu_code_match_T_120, _fu_code_match_T_112) node _fu_code_match_T_122 = or(_fu_code_match_T_121, _fu_code_match_T_113) node _fu_code_match_T_123 = or(_fu_code_match_T_122, _fu_code_match_T_114) node _fu_code_match_T_124 = or(_fu_code_match_T_123, _fu_code_match_T_115) node _fu_code_match_T_125 = or(_fu_code_match_T_124, _fu_code_match_T_116) node fu_code_match_6 = or(_fu_code_match_T_125, _fu_code_match_T_117) node can_allocate_6 = and(fu_code_match_6, UInt<1>(0h1)) node _T_260 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_261 = and(issue_slots[6].request, _T_260) node _T_262 = and(_T_261, can_allocate_6) node _T_263 = eq(_T_255, UInt<1>(0h0)) node _T_264 = and(_T_262, _T_263) when _T_264 : connect issue_slots[6].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[6].iss_uop node _T_265 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_266 = and(issue_slots[6].request, _T_265) node _T_267 = and(_T_266, can_allocate_6) node _T_268 = or(_T_267, _T_255) node _T_269 = and(issue_slots[6].request, can_allocate_6) node _T_270 = eq(_T_255, UInt<1>(0h0)) node _T_271 = and(_T_269, _T_270) node _T_272 = or(_T_271, UInt<1>(0h0)) connect issue_slots[7].grant, UInt<1>(0h0) node _fu_code_match_T_126 = and(issue_slots[7].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_127 = and(issue_slots[7].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_128 = and(issue_slots[7].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_129 = and(issue_slots[7].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_130 = and(issue_slots[7].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_131 = and(issue_slots[7].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_132 = and(issue_slots[7].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_133 = and(issue_slots[7].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_134 = and(issue_slots[7].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_135 = and(issue_slots[7].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_136 = or(_fu_code_match_T_126, _fu_code_match_T_127) node _fu_code_match_T_137 = or(_fu_code_match_T_136, _fu_code_match_T_128) node _fu_code_match_T_138 = or(_fu_code_match_T_137, _fu_code_match_T_129) node _fu_code_match_T_139 = or(_fu_code_match_T_138, _fu_code_match_T_130) node _fu_code_match_T_140 = or(_fu_code_match_T_139, _fu_code_match_T_131) node _fu_code_match_T_141 = or(_fu_code_match_T_140, _fu_code_match_T_132) node _fu_code_match_T_142 = or(_fu_code_match_T_141, _fu_code_match_T_133) node _fu_code_match_T_143 = or(_fu_code_match_T_142, _fu_code_match_T_134) node fu_code_match_7 = or(_fu_code_match_T_143, _fu_code_match_T_135) node can_allocate_7 = and(fu_code_match_7, UInt<1>(0h1)) node _T_273 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_274 = and(issue_slots[7].request, _T_273) node _T_275 = and(_T_274, can_allocate_7) node _T_276 = eq(_T_268, UInt<1>(0h0)) node _T_277 = and(_T_275, _T_276) when _T_277 : connect issue_slots[7].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[7].iss_uop node _T_278 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_279 = and(issue_slots[7].request, _T_278) node _T_280 = and(_T_279, can_allocate_7) node _T_281 = or(_T_280, _T_268) node _T_282 = and(issue_slots[7].request, can_allocate_7) node _T_283 = eq(_T_268, UInt<1>(0h0)) node _T_284 = and(_T_282, _T_283) node _T_285 = or(_T_284, UInt<1>(0h0)) connect issue_slots[8].grant, UInt<1>(0h0) node _fu_code_match_T_144 = and(issue_slots[8].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_145 = and(issue_slots[8].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_146 = and(issue_slots[8].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_147 = and(issue_slots[8].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_148 = and(issue_slots[8].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_149 = and(issue_slots[8].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_150 = and(issue_slots[8].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_151 = and(issue_slots[8].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_152 = and(issue_slots[8].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_153 = and(issue_slots[8].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_154 = or(_fu_code_match_T_144, _fu_code_match_T_145) node _fu_code_match_T_155 = or(_fu_code_match_T_154, _fu_code_match_T_146) node _fu_code_match_T_156 = or(_fu_code_match_T_155, _fu_code_match_T_147) node _fu_code_match_T_157 = or(_fu_code_match_T_156, _fu_code_match_T_148) node _fu_code_match_T_158 = or(_fu_code_match_T_157, _fu_code_match_T_149) node _fu_code_match_T_159 = or(_fu_code_match_T_158, _fu_code_match_T_150) node _fu_code_match_T_160 = or(_fu_code_match_T_159, _fu_code_match_T_151) node _fu_code_match_T_161 = or(_fu_code_match_T_160, _fu_code_match_T_152) node fu_code_match_8 = or(_fu_code_match_T_161, _fu_code_match_T_153) node can_allocate_8 = and(fu_code_match_8, UInt<1>(0h1)) node _T_286 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_287 = and(issue_slots[8].request, _T_286) node _T_288 = and(_T_287, can_allocate_8) node _T_289 = eq(_T_281, UInt<1>(0h0)) node _T_290 = and(_T_288, _T_289) when _T_290 : connect issue_slots[8].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[8].iss_uop node _T_291 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = and(issue_slots[8].request, _T_291) node _T_293 = and(_T_292, can_allocate_8) node _T_294 = or(_T_293, _T_281) node _T_295 = and(issue_slots[8].request, can_allocate_8) node _T_296 = eq(_T_281, UInt<1>(0h0)) node _T_297 = and(_T_295, _T_296) node _T_298 = or(_T_297, UInt<1>(0h0)) connect issue_slots[9].grant, UInt<1>(0h0) node _fu_code_match_T_162 = and(issue_slots[9].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_163 = and(issue_slots[9].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_164 = and(issue_slots[9].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_165 = and(issue_slots[9].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_166 = and(issue_slots[9].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_167 = and(issue_slots[9].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_168 = and(issue_slots[9].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_169 = and(issue_slots[9].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_170 = and(issue_slots[9].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_171 = and(issue_slots[9].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_172 = or(_fu_code_match_T_162, _fu_code_match_T_163) node _fu_code_match_T_173 = or(_fu_code_match_T_172, _fu_code_match_T_164) node _fu_code_match_T_174 = or(_fu_code_match_T_173, _fu_code_match_T_165) node _fu_code_match_T_175 = or(_fu_code_match_T_174, _fu_code_match_T_166) node _fu_code_match_T_176 = or(_fu_code_match_T_175, _fu_code_match_T_167) node _fu_code_match_T_177 = or(_fu_code_match_T_176, _fu_code_match_T_168) node _fu_code_match_T_178 = or(_fu_code_match_T_177, _fu_code_match_T_169) node _fu_code_match_T_179 = or(_fu_code_match_T_178, _fu_code_match_T_170) node fu_code_match_9 = or(_fu_code_match_T_179, _fu_code_match_T_171) node can_allocate_9 = and(fu_code_match_9, UInt<1>(0h1)) node _T_299 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_300 = and(issue_slots[9].request, _T_299) node _T_301 = and(_T_300, can_allocate_9) node _T_302 = eq(_T_294, UInt<1>(0h0)) node _T_303 = and(_T_301, _T_302) when _T_303 : connect issue_slots[9].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[9].iss_uop node _T_304 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_305 = and(issue_slots[9].request, _T_304) node _T_306 = and(_T_305, can_allocate_9) node _T_307 = or(_T_306, _T_294) node _T_308 = and(issue_slots[9].request, can_allocate_9) node _T_309 = eq(_T_294, UInt<1>(0h0)) node _T_310 = and(_T_308, _T_309) node _T_311 = or(_T_310, UInt<1>(0h0)) connect issue_slots[10].grant, UInt<1>(0h0) node _fu_code_match_T_180 = and(issue_slots[10].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_181 = and(issue_slots[10].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_182 = and(issue_slots[10].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_183 = and(issue_slots[10].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_184 = and(issue_slots[10].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_185 = and(issue_slots[10].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_186 = and(issue_slots[10].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_187 = and(issue_slots[10].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_188 = and(issue_slots[10].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_189 = and(issue_slots[10].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_190 = or(_fu_code_match_T_180, _fu_code_match_T_181) node _fu_code_match_T_191 = or(_fu_code_match_T_190, _fu_code_match_T_182) node _fu_code_match_T_192 = or(_fu_code_match_T_191, _fu_code_match_T_183) node _fu_code_match_T_193 = or(_fu_code_match_T_192, _fu_code_match_T_184) node _fu_code_match_T_194 = or(_fu_code_match_T_193, _fu_code_match_T_185) node _fu_code_match_T_195 = or(_fu_code_match_T_194, _fu_code_match_T_186) node _fu_code_match_T_196 = or(_fu_code_match_T_195, _fu_code_match_T_187) node _fu_code_match_T_197 = or(_fu_code_match_T_196, _fu_code_match_T_188) node fu_code_match_10 = or(_fu_code_match_T_197, _fu_code_match_T_189) node can_allocate_10 = and(fu_code_match_10, UInt<1>(0h1)) node _T_312 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_313 = and(issue_slots[10].request, _T_312) node _T_314 = and(_T_313, can_allocate_10) node _T_315 = eq(_T_307, UInt<1>(0h0)) node _T_316 = and(_T_314, _T_315) when _T_316 : connect issue_slots[10].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[10].iss_uop node _T_317 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_318 = and(issue_slots[10].request, _T_317) node _T_319 = and(_T_318, can_allocate_10) node _T_320 = or(_T_319, _T_307) node _T_321 = and(issue_slots[10].request, can_allocate_10) node _T_322 = eq(_T_307, UInt<1>(0h0)) node _T_323 = and(_T_321, _T_322) node _T_324 = or(_T_323, UInt<1>(0h0)) connect issue_slots[11].grant, UInt<1>(0h0) node _fu_code_match_T_198 = and(issue_slots[11].iss_uop.fu_code[0], io.fu_types[0][0]) node _fu_code_match_T_199 = and(issue_slots[11].iss_uop.fu_code[1], io.fu_types[0][1]) node _fu_code_match_T_200 = and(issue_slots[11].iss_uop.fu_code[2], io.fu_types[0][2]) node _fu_code_match_T_201 = and(issue_slots[11].iss_uop.fu_code[3], io.fu_types[0][3]) node _fu_code_match_T_202 = and(issue_slots[11].iss_uop.fu_code[4], io.fu_types[0][4]) node _fu_code_match_T_203 = and(issue_slots[11].iss_uop.fu_code[5], io.fu_types[0][5]) node _fu_code_match_T_204 = and(issue_slots[11].iss_uop.fu_code[6], io.fu_types[0][6]) node _fu_code_match_T_205 = and(issue_slots[11].iss_uop.fu_code[7], io.fu_types[0][7]) node _fu_code_match_T_206 = and(issue_slots[11].iss_uop.fu_code[8], io.fu_types[0][8]) node _fu_code_match_T_207 = and(issue_slots[11].iss_uop.fu_code[9], io.fu_types[0][9]) node _fu_code_match_T_208 = or(_fu_code_match_T_198, _fu_code_match_T_199) node _fu_code_match_T_209 = or(_fu_code_match_T_208, _fu_code_match_T_200) node _fu_code_match_T_210 = or(_fu_code_match_T_209, _fu_code_match_T_201) node _fu_code_match_T_211 = or(_fu_code_match_T_210, _fu_code_match_T_202) node _fu_code_match_T_212 = or(_fu_code_match_T_211, _fu_code_match_T_203) node _fu_code_match_T_213 = or(_fu_code_match_T_212, _fu_code_match_T_204) node _fu_code_match_T_214 = or(_fu_code_match_T_213, _fu_code_match_T_205) node _fu_code_match_T_215 = or(_fu_code_match_T_214, _fu_code_match_T_206) node fu_code_match_11 = or(_fu_code_match_T_215, _fu_code_match_T_207) node can_allocate_11 = and(fu_code_match_11, UInt<1>(0h1)) node _T_325 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_326 = and(issue_slots[11].request, _T_325) node _T_327 = and(_T_326, can_allocate_11) node _T_328 = eq(_T_320, UInt<1>(0h0)) node _T_329 = and(_T_327, _T_328) when _T_329 : connect issue_slots[11].grant, UInt<1>(0h1) connect iss_uops[0].valid, UInt<1>(0h1) connect iss_uops[0].bits, issue_slots[11].iss_uop node _T_330 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_331 = and(issue_slots[11].request, _T_330) node _T_332 = and(_T_331, can_allocate_11) node _T_333 = or(_T_332, _T_320) node _T_334 = and(issue_slots[11].request, can_allocate_11) node _T_335 = eq(_T_320, UInt<1>(0h0)) node _T_336 = and(_T_334, _T_335) node _T_337 = or(_T_336, UInt<1>(0h0)) connect io.iss_uops, iss_uops when io.squash_grant : connect io.iss_uops[0].valid, UInt<1>(0h0)	module IssueUnitCollapsing( // @[issue-unit-age-ordered.scala:22:7] input clock, // @[issue-unit-age-ordered.scala:22:7] input reset, // @[issue-unit-age-ordered.scala:22:7] output io_dis_uops_0_ready, // @[issue-unit.scala:44:14] input io_dis_uops_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [11:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_dis_uops_1_ready, // @[issue-unit.scala:44:14] input io_dis_uops_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_1_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [11:0] io_dis_uops_1_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_1_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_rob_idx, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_ldq_idx, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_1_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_iss_uops_0_valid, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_inst, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] output [39:0] io_iss_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] output [11:0] io_iss_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_type, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_taken, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_pimm, // @[issue-unit.scala:44:14] output [19:0] io_iss_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_pdst, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs1, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs2, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs3, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ppred, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_exception, // @[issue-unit.scala:44:14] output [63:0] io_iss_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_ldst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_fu_types_0_7, // @[issue-unit.scala:44:14] input io_fu_types_0_9, // @[issue-unit.scala:44:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:44:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_eret, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rocc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_taken, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_brupdate_b2_mispredict, // @[issue-unit.scala:44:14] input io_brupdate_b2_taken, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:44:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:44:14] input io_flush_pipeline, // @[issue-unit.scala:44:14] input io_squash_grant, // @[issue-unit.scala:44:14] input [63:0] io_tsc_reg // @[issue-unit.scala:44:14] ); wire issue_slots_11_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_0_0 = io_dis_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_1_0 = io_dis_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_2_0 = io_dis_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_3_0 = io_dis_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_0_0 = io_dis_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_1_0 = io_dis_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_2_0 = io_dis_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_3_0 = io_dis_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_4_0 = io_dis_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_5_0 = io_dis_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_6_0 = io_dis_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_7_0 = io_dis_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_8_0 = io_dis_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_9_0 = io_dis_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_0 = io_dis_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_agen_0 = io_dis_uops_0_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_dis_uops_0_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_iw_p1_speculative_child_0 = io_dis_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_iw_p2_speculative_child_0 = io_dis_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_dis_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_dis_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_dis_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_dis_col_sel_0 = io_dis_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_type_0 = io_dis_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfence_0 = io_dis_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_eret_0 = io_dis_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rocc_0 = io_dis_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_mov_0 = io_dis_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_imm_rename_0 = io_dis_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_imm_sel_0 = io_dis_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_pimm_0 = io_dis_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_op1_sel_0 = io_dis_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_op2_sel_0 = io_dis_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ldst_0 = io_dis_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wen_0 = io_dis_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren1_0 = io_dis_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren2_0 = io_dis_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren3_0 = io_dis_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap12_0 = io_dis_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap23_0 = io_dis_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fromint_0 = io_dis_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_toint_0 = io_dis_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_dis_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fma_0 = io_dis_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_div_0 = io_dis_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_dis_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wflags_0 = io_dis_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_vec_0 = io_dis_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ppred_0 = io_dis_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ppred_busy_0 = io_dis_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_csr_cmd_0 = io_dis_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fcn_dw_0 = io_dis_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_fcn_op_0 = io_dis_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_fp_rm_0 = io_dis_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_typ_0 = io_dis_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_0_0 = io_dis_uops_1_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_1_0 = io_dis_uops_1_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_2_0 = io_dis_uops_1_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_3_0 = io_dis_uops_1_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_0_0 = io_dis_uops_1_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_1_0 = io_dis_uops_1_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_2_0 = io_dis_uops_1_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_3_0 = io_dis_uops_1_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_4_0 = io_dis_uops_1_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_5_0 = io_dis_uops_1_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_6_0 = io_dis_uops_1_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_7_0 = io_dis_uops_1_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_8_0 = io_dis_uops_1_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_9_0 = io_dis_uops_1_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_0 = io_dis_uops_1_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_agen_0 = io_dis_uops_1_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_dis_uops_1_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_iw_p1_speculative_child_0 = io_dis_uops_1_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_iw_p2_speculative_child_0 = io_dis_uops_1_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_dis_uops_1_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_dis_uops_1_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_dis_uops_1_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_dis_col_sel_0 = io_dis_uops_1_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_type_0 = io_dis_uops_1_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfence_0 = io_dis_uops_1_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_eret_0 = io_dis_uops_1_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rocc_0 = io_dis_uops_1_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_mov_0 = io_dis_uops_1_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_imm_rename_0 = io_dis_uops_1_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_imm_sel_0 = io_dis_uops_1_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_pimm_0 = io_dis_uops_1_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_op1_sel_0 = io_dis_uops_1_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_op2_sel_0 = io_dis_uops_1_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ldst_0 = io_dis_uops_1_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wen_0 = io_dis_uops_1_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren1_0 = io_dis_uops_1_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren2_0 = io_dis_uops_1_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren3_0 = io_dis_uops_1_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap12_0 = io_dis_uops_1_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap23_0 = io_dis_uops_1_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fromint_0 = io_dis_uops_1_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_toint_0 = io_dis_uops_1_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_dis_uops_1_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fma_0 = io_dis_uops_1_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_div_0 = io_dis_uops_1_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_dis_uops_1_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wflags_0 = io_dis_uops_1_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_vec_0 = io_dis_uops_1_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ppred_0 = io_dis_uops_1_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ppred_busy_0 = io_dis_uops_1_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_csr_cmd_0 = io_dis_uops_1_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fcn_dw_0 = io_dis_uops_1_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_fcn_op_0 = io_dis_uops_1_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_fp_rm_0 = io_dis_uops_1_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_typ_0 = io_dis_uops_1_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_7_0 = io_fu_types_0_7; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_9_0 = io_fu_types_0_9; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:22:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:22:7] wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:22:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_0 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_2 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_3 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_4 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_5 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_8 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_rebusys_0 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_0 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs1_rebusys_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire issue_slots_0_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_clear = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire _shamts_oh_1_T_2 = 1'h0; // @[issue-unit-age-ordered.scala:165:28] wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:199:49] wire iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:241:22] wire _fu_code_match_T = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_1 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_2 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_3 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_4 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_5 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_8 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_10 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_11 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_12 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_13 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_14 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_18 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_19 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_20 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_21 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_22 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_23 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_26 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_28 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_29 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_30 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_31 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_32 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_36 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_37 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_38 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_39 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_40 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_41 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_44 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_46 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_47 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_48 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_49 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_50 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_54 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_55 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_56 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_57 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_58 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_59 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_62 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_64 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_65 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_66 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_67 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_68 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_72 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_73 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_74 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_75 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_76 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_77 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_80 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_82 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_83 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_84 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_85 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_86 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_90 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_91 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_92 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_93 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_94 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_95 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_98 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_100 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_101 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_102 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_103 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_104 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_108 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_109 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_110 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_111 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_112 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_113 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_116 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_118 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_119 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_120 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_121 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_122 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_126 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_127 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_128 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_129 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_130 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_131 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_134 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_136 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_137 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_138 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_139 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_140 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_144 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_145 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_146 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_147 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_148 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_149 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_152 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_154 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_155 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_156 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_157 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_158 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_162 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_163 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_164 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_165 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_166 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_167 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_170 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_172 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_173 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_174 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_175 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_176 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_180 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_181 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_182 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_183 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_184 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_185 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_188 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_190 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_191 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_192 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_193 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_194 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_198 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_199 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_200 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_201 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_202 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_203 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_206 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_208 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_209 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_210 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_211 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_212 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_6 = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire issue_slots_0_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire _shamts_oh_1_T = 1'h1; // @[issue-unit-age-ordered.scala:163:21] wire _shamts_oh_1_T_3 = 1'h1; // @[issue-unit-age-ordered.scala:165:19] wire [1:0] io_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] issue_slots_0_in_uop_bits_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_child_rebusys = 2'h0; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] shamts_oh_0 = 2'h0; // @[issue-unit-age-ordered.scala:158:23] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] issue_slots_0_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] _shamts_oh_1_next_T = 3'h0; // @[issue-unit-age-ordered.scala:166:26] wire [31:0] iss_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:241:22] wire [31:0] iss_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:241:22] wire [39:0] iss_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:241:22] wire [11:0] iss_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:241:22] wire [19:0] iss_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:241:22] wire [63:0] iss_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:241:22] wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_0_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_1_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_2_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_3_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_4_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_5_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_6_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_7_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_8_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_9_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_10_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_11_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_0_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_1_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_2_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_3_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_4_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_5_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_6_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_7_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_8_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_9_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_10_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_11_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_8_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_9_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_10_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_11_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_8_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_9_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_10_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_11_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_8_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_9_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_10_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [11:0] issue_slots_11_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_8_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_9_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_10_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_11_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_iss_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [11:0] io_iss_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_iss_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_iss_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0 = io_wakeup_ports_0_valid_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0 = io_wakeup_ports_0_valid_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0 = io_wakeup_ports_0_valid_0 & prs3_matches_0; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire _T = prs1_wakeups_0 \| prs1_wakeups_1; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire _WIRE_iw_p1_bypass_hint = _T & prs1_wakeups_0; // @[issue-unit-age-ordered.scala:39:35, :47:89, :57:{32,38}, :60:37] wire _T_12 = prs2_wakeups_0 \| prs2_wakeups_1; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire _WIRE_prs2_busy = ~_T_12 & io_dis_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :66:29] wire _WIRE_iw_p2_bypass_hint = _T_12 & prs2_wakeups_0; // @[issue-unit-age-ordered.scala:40:35, :48:89, :65:{32,38}, :68:37] wire _T_24 = prs3_wakeups_0 \| prs3_wakeups_1; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _WIRE_prs3_busy = ~_T_24 & io_dis_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29] wire _WIRE_iw_p3_bypass_hint = _T_24 & prs3_wakeups_0; // @[issue-unit-age-ordered.scala:41:35, :49:89, :76:{32,38}, :78:37] wire [1:0] _WIRE_lrs1_rtype = io_dis_uops_0_bits_uses_stq_0 ? 2'h2 : io_dis_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :103:43, :104:32] wire _WIRE_prs1_busy = ~io_dis_uops_0_bits_uses_stq_0 & ~_T & io_dis_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :58:29, :62:116, :103:43, :105:32] wire prs1_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs3_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire _T_35 = prs1_wakeups_0_1 \| prs1_wakeups_1_1; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire _T_47 = prs2_wakeups_0_1 \| prs2_wakeups_1_1; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire _T_59 = prs3_wakeups_0_1 \| prs3_wakeups_1_1; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _fu_code_match_T_6 = issue_slots_0_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_24 = issue_slots_1_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_42 = issue_slots_2_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_60 = issue_slots_3_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_78 = issue_slots_4_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_96 = issue_slots_5_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_114 = issue_slots_6_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_132 = issue_slots_7_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_150 = issue_slots_8_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_168 = issue_slots_9_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_186 = issue_slots_10_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_204 = issue_slots_11_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire issue_slots_0_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_0_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_0_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_0_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_1_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_1_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_2_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_2_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_3_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_3_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_4_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_4_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_5_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_5_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_6_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_6_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_7_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_7_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_8_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_8_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_9_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_9_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_10_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_10_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_11_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_11_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [11:0] issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_clear; // @[issue-unit-age-ordered.scala:122:28] wire vacants_0 = ~issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire _shamts_oh_1_T_1 = vacants_0; // @[issue-unit-age-ordered.scala:157:38, :163:29] wire _shamts_oh_1_T_4 = vacants_0; // @[issue-unit-age-ordered.scala:157:38, :165:36] wire vacants_1 = ~issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_2 = ~issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_3 = ~issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_4 = ~issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_5 = ~issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_6 = ~issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_7 = ~issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_8 = ~issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_9 = ~issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_10 = ~issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_11 = ~issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_12 = ~io_dis_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire vacants_13 = ~io_dis_uops_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire [1:0] shamts_oh_1_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_2_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_3_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_4_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_5_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_6_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_7_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_8_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_9_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_10_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_11_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_12_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_13_next; // @[issue-unit-age-ordered.scala:161:21] wire [1:0] shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23] wire [1:0] shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23] assign shamts_oh_1 = shamts_oh_1_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] assign shamts_oh_1_next = {1'h0, _shamts_oh_1_T_1}; // @[issue-unit-age-ordered.scala:161:21, :163:{29,37}, :164:13, :165:44] assign shamts_oh_2 = shamts_oh_2_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_2_T = ~(\|shamts_oh_1); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_2_T_1 = _shamts_oh_2_T & vacants_1; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_2_T_2 = shamts_oh_1[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_2_T_3 = ~_shamts_oh_2_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_2_T_4 = _shamts_oh_2_T_3 & vacants_1; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_2_next_T = {shamts_oh_1, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_2_next = _shamts_oh_2_T_1 ? 2'h1 : _shamts_oh_2_T_4 ? _shamts_oh_2_next_T[1:0] : shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_3 = shamts_oh_3_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_3_T = ~(\|shamts_oh_2); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_3_T_1 = _shamts_oh_3_T & vacants_2; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_3_T_2 = shamts_oh_2[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_3_T_3 = ~_shamts_oh_3_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_3_T_4 = _shamts_oh_3_T_3 & vacants_2; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_3_next_T = {shamts_oh_2, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_3_next = _shamts_oh_3_T_1 ? 2'h1 : _shamts_oh_3_T_4 ? _shamts_oh_3_next_T[1:0] : shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_4 = shamts_oh_4_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_4_T = ~(\|shamts_oh_3); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_4_T_1 = _shamts_oh_4_T & vacants_3; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_4_T_2 = shamts_oh_3[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_4_T_3 = ~_shamts_oh_4_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_4_T_4 = _shamts_oh_4_T_3 & vacants_3; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_4_next_T = {shamts_oh_3, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_4_next = _shamts_oh_4_T_1 ? 2'h1 : _shamts_oh_4_T_4 ? _shamts_oh_4_next_T[1:0] : shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_5 = shamts_oh_5_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_5_T = ~(\|shamts_oh_4); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_5_T_1 = _shamts_oh_5_T & vacants_4; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_5_T_2 = shamts_oh_4[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_5_T_3 = ~_shamts_oh_5_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_5_T_4 = _shamts_oh_5_T_3 & vacants_4; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_5_next_T = {shamts_oh_4, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_5_next = _shamts_oh_5_T_1 ? 2'h1 : _shamts_oh_5_T_4 ? _shamts_oh_5_next_T[1:0] : shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_6 = shamts_oh_6_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_6_T = ~(\|shamts_oh_5); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_6_T_1 = _shamts_oh_6_T & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_6_T_2 = shamts_oh_5[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_6_T_3 = ~_shamts_oh_6_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_6_T_4 = _shamts_oh_6_T_3 & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_6_next_T = {shamts_oh_5, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_6_next = _shamts_oh_6_T_1 ? 2'h1 : _shamts_oh_6_T_4 ? _shamts_oh_6_next_T[1:0] : shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_7 = shamts_oh_7_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_7_T = ~(\|shamts_oh_6); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_7_T_1 = _shamts_oh_7_T & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_7_T_2 = shamts_oh_6[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_7_T_3 = ~_shamts_oh_7_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_7_T_4 = _shamts_oh_7_T_3 & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_7_next_T = {shamts_oh_6, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_7_next = _shamts_oh_7_T_1 ? 2'h1 : _shamts_oh_7_T_4 ? _shamts_oh_7_next_T[1:0] : shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_8 = shamts_oh_8_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_8_T = ~(\|shamts_oh_7); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_8_T_1 = _shamts_oh_8_T & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_8_T_2 = shamts_oh_7[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_8_T_3 = ~_shamts_oh_8_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_8_T_4 = _shamts_oh_8_T_3 & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_8_next_T = {shamts_oh_7, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_8_next = _shamts_oh_8_T_1 ? 2'h1 : _shamts_oh_8_T_4 ? _shamts_oh_8_next_T[1:0] : shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_9 = shamts_oh_9_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_9_T = ~(\|shamts_oh_8); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_9_T_1 = _shamts_oh_9_T & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_9_T_2 = shamts_oh_8[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_9_T_3 = ~_shamts_oh_9_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_9_T_4 = _shamts_oh_9_T_3 & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_9_next_T = {shamts_oh_8, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_9_next = _shamts_oh_9_T_1 ? 2'h1 : _shamts_oh_9_T_4 ? _shamts_oh_9_next_T[1:0] : shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_10 = shamts_oh_10_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_10_T = ~(\|shamts_oh_9); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_10_T_1 = _shamts_oh_10_T & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_10_T_2 = shamts_oh_9[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_10_T_3 = ~_shamts_oh_10_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_10_T_4 = _shamts_oh_10_T_3 & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_10_next_T = {shamts_oh_9, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_10_next = _shamts_oh_10_T_1 ? 2'h1 : _shamts_oh_10_T_4 ? _shamts_oh_10_next_T[1:0] : shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_11 = shamts_oh_11_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_11_T = ~(\|shamts_oh_10); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_11_T_1 = _shamts_oh_11_T & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_11_T_2 = shamts_oh_10[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_11_T_3 = ~_shamts_oh_11_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_11_T_4 = _shamts_oh_11_T_3 & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_11_next_T = {shamts_oh_10, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_11_next = _shamts_oh_11_T_1 ? 2'h1 : _shamts_oh_11_T_4 ? _shamts_oh_11_next_T[1:0] : shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_12 = shamts_oh_12_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_12_T = ~(\|shamts_oh_11); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_12_T_1 = _shamts_oh_12_T & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_12_T_2 = shamts_oh_11[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_12_T_3 = ~_shamts_oh_12_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_12_T_4 = _shamts_oh_12_T_3 & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [2:0] _shamts_oh_12_next_T = {shamts_oh_11, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_12_next = _shamts_oh_12_T_1 ? 2'h1 : _shamts_oh_12_T_4 ? _shamts_oh_12_next_T[1:0] : shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_13 = shamts_oh_13_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_13_T = shamts_oh_12 == 2'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_13_T_1 = _shamts_oh_13_T & vacants_12; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}] wire _shamts_oh_13_T_2 = shamts_oh_12[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_13_T_3 = ~_shamts_oh_13_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_13_T_4 = _shamts_oh_13_T_3 & vacants_12; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}] wire [2:0] _shamts_oh_13_next_T = {shamts_oh_12, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_13_next = _shamts_oh_13_T_1 ? 2'h1 : _shamts_oh_13_T_4 ? _shamts_oh_13_next_T[1:0] : shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] wire _will_be_valid_T = ~io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_1 = io_dis_uops_0_valid_0 & _will_be_valid_T; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_2 = ~io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_3 = _will_be_valid_T_1 & _will_be_valid_T_2; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_4 = ~io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_12 = _will_be_valid_T_3 & _will_be_valid_T_4; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _will_be_valid_T_5 = ~io_dis_uops_1_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_6 = io_dis_uops_1_valid_0 & _will_be_valid_T_5; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_7 = ~io_dis_uops_1_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_8 = _will_be_valid_T_6 & _will_be_valid_T_7; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_9 = ~io_dis_uops_1_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_13 = _will_be_valid_T_8 & _will_be_valid_T_9; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _T_97 = shamts_oh_2 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_0_in_uop_valid = _T_97 ? issue_slots_2_will_be_valid : shamts_oh_1 == 2'h1 & issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_0_in_uop_bits_debug_tsrc = _T_97 ? issue_slots_2_out_uop_debug_tsrc : issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_fsrc = _T_97 ? issue_slots_2_out_uop_debug_fsrc : issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_xcpt_if = _T_97 ? issue_slots_2_out_uop_bp_xcpt_if : issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_debug_if = _T_97 ? issue_slots_2_out_uop_bp_debug_if : issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ma_if = _T_97 ? issue_slots_2_out_uop_xcpt_ma_if : issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ae_if = _T_97 ? issue_slots_2_out_uop_xcpt_ae_if : issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_pf_if = _T_97 ? issue_slots_2_out_uop_xcpt_pf_if : issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_typ = _T_97 ? issue_slots_2_out_uop_fp_typ : issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_rm = _T_97 ? issue_slots_2_out_uop_fp_rm : issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_val = _T_97 ? issue_slots_2_out_uop_fp_val : issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_op = _T_97 ? issue_slots_2_out_uop_fcn_op : issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_dw = _T_97 ? issue_slots_2_out_uop_fcn_dw : issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_frs3_en = _T_97 ? issue_slots_2_out_uop_frs3_en : issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2_rtype = _T_97 ? issue_slots_2_out_uop_lrs2_rtype : issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1_rtype = _T_97 ? issue_slots_2_out_uop_lrs1_rtype : issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dst_rtype = _T_97 ? issue_slots_2_out_uop_dst_rtype : issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs3 = _T_97 ? issue_slots_2_out_uop_lrs3 : issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2 = _T_97 ? issue_slots_2_out_uop_lrs2 : issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1 = _T_97 ? issue_slots_2_out_uop_lrs1 : issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst = _T_97 ? issue_slots_2_out_uop_ldst : issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst_is_rs1 = _T_97 ? issue_slots_2_out_uop_ldst_is_rs1 : issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_csr_cmd = _T_97 ? issue_slots_2_out_uop_csr_cmd : issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_flush_on_commit = _T_97 ? issue_slots_2_out_uop_flush_on_commit : issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_unique = _T_97 ? issue_slots_2_out_uop_is_unique : issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_stq = _T_97 ? issue_slots_2_out_uop_uses_stq : issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_ldq = _T_97 ? issue_slots_2_out_uop_uses_ldq : issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_signed = _T_97 ? issue_slots_2_out_uop_mem_signed : issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_size = _T_97 ? issue_slots_2_out_uop_mem_size : issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_cmd = _T_97 ? issue_slots_2_out_uop_mem_cmd : issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exc_cause = _T_97 ? issue_slots_2_out_uop_exc_cause : issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exception = _T_97 ? issue_slots_2_out_uop_exception : issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stale_pdst = _T_97 ? issue_slots_2_out_uop_stale_pdst : issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred_busy = _T_97 ? issue_slots_2_out_uop_ppred_busy : issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3_busy = _T_97 ? issue_slots_2_out_uop_prs3_busy : issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2_busy = _T_97 ? issue_slots_2_out_uop_prs2_busy : issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1_busy = _T_97 ? issue_slots_2_out_uop_prs1_busy : issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred = _T_97 ? issue_slots_2_out_uop_ppred : issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3 = _T_97 ? issue_slots_2_out_uop_prs3 : issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2 = _T_97 ? issue_slots_2_out_uop_prs2 : issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1 = _T_97 ? issue_slots_2_out_uop_prs1 : issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pdst = _T_97 ? issue_slots_2_out_uop_pdst : issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rxq_idx = _T_97 ? issue_slots_2_out_uop_rxq_idx : issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stq_idx = _T_97 ? issue_slots_2_out_uop_stq_idx : issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldq_idx = _T_97 ? issue_slots_2_out_uop_ldq_idx : issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rob_idx = _T_97 ? issue_slots_2_out_uop_rob_idx : issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_vec = _T_97 ? issue_slots_2_out_uop_fp_ctrl_vec : issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wflags = _T_97 ? issue_slots_2_out_uop_fp_ctrl_wflags : issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_sqrt = _T_97 ? issue_slots_2_out_uop_fp_ctrl_sqrt : issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_div = _T_97 ? issue_slots_2_out_uop_fp_ctrl_div : issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fma = _T_97 ? issue_slots_2_out_uop_fp_ctrl_fma : issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fastpipe = _T_97 ? issue_slots_2_out_uop_fp_ctrl_fastpipe : issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_toint = _T_97 ? issue_slots_2_out_uop_fp_ctrl_toint : issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fromint = _T_97 ? issue_slots_2_out_uop_fp_ctrl_fromint : issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut = _T_97 ? issue_slots_2_out_uop_fp_ctrl_typeTagOut : issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn = _T_97 ? issue_slots_2_out_uop_fp_ctrl_typeTagIn : issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap23 = _T_97 ? issue_slots_2_out_uop_fp_ctrl_swap23 : issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap12 = _T_97 ? issue_slots_2_out_uop_fp_ctrl_swap12 : issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren3 = _T_97 ? issue_slots_2_out_uop_fp_ctrl_ren3 : issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren2 = _T_97 ? issue_slots_2_out_uop_fp_ctrl_ren2 : issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren1 = _T_97 ? issue_slots_2_out_uop_fp_ctrl_ren1 : issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wen = _T_97 ? issue_slots_2_out_uop_fp_ctrl_wen : issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ldst = _T_97 ? issue_slots_2_out_uop_fp_ctrl_ldst : issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op2_sel = _T_97 ? issue_slots_2_out_uop_op2_sel : issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op1_sel = _T_97 ? issue_slots_2_out_uop_op1_sel : issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_packed = _T_97 ? issue_slots_2_out_uop_imm_packed : issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pimm = _T_97 ? issue_slots_2_out_uop_pimm : issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_sel = _T_97 ? issue_slots_2_out_uop_imm_sel : issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_rename = _T_97 ? issue_slots_2_out_uop_imm_rename : issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_taken = _T_97 ? issue_slots_2_out_uop_taken : issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pc_lob = _T_97 ? issue_slots_2_out_uop_pc_lob : issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_edge_inst = _T_97 ? issue_slots_2_out_uop_edge_inst : issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ftq_idx = _T_97 ? issue_slots_2_out_uop_ftq_idx : issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_mov = _T_97 ? issue_slots_2_out_uop_is_mov : issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rocc = _T_97 ? issue_slots_2_out_uop_is_rocc : issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sys_pc2epc = _T_97 ? issue_slots_2_out_uop_is_sys_pc2epc : issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_eret = _T_97 ? issue_slots_2_out_uop_is_eret : issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_amo = _T_97 ? issue_slots_2_out_uop_is_amo : issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfence = _T_97 ? issue_slots_2_out_uop_is_sfence : issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fencei = _T_97 ? issue_slots_2_out_uop_is_fencei : issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fence = _T_97 ? issue_slots_2_out_uop_is_fence : issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfb = _T_97 ? issue_slots_2_out_uop_is_sfb : issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_type = _T_97 ? issue_slots_2_out_uop_br_type : issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_tag = _T_97 ? issue_slots_2_out_uop_br_tag : issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_mask = _T_97 ? issue_slots_2_out_uop_br_mask : issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dis_col_sel = _T_97 ? issue_slots_2_out_uop_dis_col_sel : issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p3_bypass_hint = _T_97 ? issue_slots_2_out_uop_iw_p3_bypass_hint : issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p2_bypass_hint = _T_97 ? issue_slots_2_out_uop_iw_p2_bypass_hint : issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p1_bypass_hint = _T_97 ? issue_slots_2_out_uop_iw_p1_bypass_hint : issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_issued = _T_97 ? issue_slots_2_out_uop_iw_issued : issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_0 = _T_97 ? issue_slots_2_out_uop_fu_code_0 : issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_1 = _T_97 ? issue_slots_2_out_uop_fu_code_1 : issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_2 = _T_97 ? issue_slots_2_out_uop_fu_code_2 : issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_3 = _T_97 ? issue_slots_2_out_uop_fu_code_3 : issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_4 = _T_97 ? issue_slots_2_out_uop_fu_code_4 : issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_5 = _T_97 ? issue_slots_2_out_uop_fu_code_5 : issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_6 = _T_97 ? issue_slots_2_out_uop_fu_code_6 : issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_7 = _T_97 ? issue_slots_2_out_uop_fu_code_7 : issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_8 = _T_97 ? issue_slots_2_out_uop_fu_code_8 : issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_9 = _T_97 ? issue_slots_2_out_uop_fu_code_9 : issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_0 = _T_97 ? issue_slots_2_out_uop_iq_type_0 : issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_1 = _T_97 ? issue_slots_2_out_uop_iq_type_1 : issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_2 = _T_97 ? issue_slots_2_out_uop_iq_type_2 : issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_3 = _T_97 ? issue_slots_2_out_uop_iq_type_3 : issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_pc = _T_97 ? issue_slots_2_out_uop_debug_pc : issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rvc = _T_97 ? issue_slots_2_out_uop_is_rvc : issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_inst = _T_97 ? issue_slots_2_out_uop_debug_inst : issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_inst = _T_97 ? issue_slots_2_out_uop_inst : issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] wire _T_99 = shamts_oh_3 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_1_in_uop_valid = _T_99 ? issue_slots_3_will_be_valid : shamts_oh_2 == 2'h1 & issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_1_in_uop_bits_debug_tsrc = _T_99 ? issue_slots_3_out_uop_debug_tsrc : issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_fsrc = _T_99 ? issue_slots_3_out_uop_debug_fsrc : issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_xcpt_if = _T_99 ? issue_slots_3_out_uop_bp_xcpt_if : issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_debug_if = _T_99 ? issue_slots_3_out_uop_bp_debug_if : issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ma_if = _T_99 ? issue_slots_3_out_uop_xcpt_ma_if : issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ae_if = _T_99 ? issue_slots_3_out_uop_xcpt_ae_if : issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_pf_if = _T_99 ? issue_slots_3_out_uop_xcpt_pf_if : issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_typ = _T_99 ? issue_slots_3_out_uop_fp_typ : issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_rm = _T_99 ? issue_slots_3_out_uop_fp_rm : issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_val = _T_99 ? issue_slots_3_out_uop_fp_val : issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_op = _T_99 ? issue_slots_3_out_uop_fcn_op : issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_dw = _T_99 ? issue_slots_3_out_uop_fcn_dw : issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_frs3_en = _T_99 ? issue_slots_3_out_uop_frs3_en : issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2_rtype = _T_99 ? issue_slots_3_out_uop_lrs2_rtype : issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1_rtype = _T_99 ? issue_slots_3_out_uop_lrs1_rtype : issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dst_rtype = _T_99 ? issue_slots_3_out_uop_dst_rtype : issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs3 = _T_99 ? issue_slots_3_out_uop_lrs3 : issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2 = _T_99 ? issue_slots_3_out_uop_lrs2 : issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1 = _T_99 ? issue_slots_3_out_uop_lrs1 : issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst = _T_99 ? issue_slots_3_out_uop_ldst : issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst_is_rs1 = _T_99 ? issue_slots_3_out_uop_ldst_is_rs1 : issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_csr_cmd = _T_99 ? issue_slots_3_out_uop_csr_cmd : issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_flush_on_commit = _T_99 ? issue_slots_3_out_uop_flush_on_commit : issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_unique = _T_99 ? issue_slots_3_out_uop_is_unique : issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_stq = _T_99 ? issue_slots_3_out_uop_uses_stq : issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_ldq = _T_99 ? issue_slots_3_out_uop_uses_ldq : issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_signed = _T_99 ? issue_slots_3_out_uop_mem_signed : issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_size = _T_99 ? issue_slots_3_out_uop_mem_size : issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_cmd = _T_99 ? issue_slots_3_out_uop_mem_cmd : issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exc_cause = _T_99 ? issue_slots_3_out_uop_exc_cause : issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exception = _T_99 ? issue_slots_3_out_uop_exception : issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stale_pdst = _T_99 ? issue_slots_3_out_uop_stale_pdst : issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred_busy = _T_99 ? issue_slots_3_out_uop_ppred_busy : issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3_busy = _T_99 ? issue_slots_3_out_uop_prs3_busy : issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2_busy = _T_99 ? issue_slots_3_out_uop_prs2_busy : issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1_busy = _T_99 ? issue_slots_3_out_uop_prs1_busy : issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred = _T_99 ? issue_slots_3_out_uop_ppred : issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3 = _T_99 ? issue_slots_3_out_uop_prs3 : issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2 = _T_99 ? issue_slots_3_out_uop_prs2 : issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1 = _T_99 ? issue_slots_3_out_uop_prs1 : issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pdst = _T_99 ? issue_slots_3_out_uop_pdst : issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rxq_idx = _T_99 ? issue_slots_3_out_uop_rxq_idx : issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stq_idx = _T_99 ? issue_slots_3_out_uop_stq_idx : issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldq_idx = _T_99 ? issue_slots_3_out_uop_ldq_idx : issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rob_idx = _T_99 ? issue_slots_3_out_uop_rob_idx : issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_vec = _T_99 ? issue_slots_3_out_uop_fp_ctrl_vec : issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wflags = _T_99 ? issue_slots_3_out_uop_fp_ctrl_wflags : issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_sqrt = _T_99 ? issue_slots_3_out_uop_fp_ctrl_sqrt : issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_div = _T_99 ? issue_slots_3_out_uop_fp_ctrl_div : issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fma = _T_99 ? issue_slots_3_out_uop_fp_ctrl_fma : issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fastpipe = _T_99 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_toint = _T_99 ? issue_slots_3_out_uop_fp_ctrl_toint : issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fromint = _T_99 ? issue_slots_3_out_uop_fp_ctrl_fromint : issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut = _T_99 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn = _T_99 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap23 = _T_99 ? issue_slots_3_out_uop_fp_ctrl_swap23 : issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap12 = _T_99 ? issue_slots_3_out_uop_fp_ctrl_swap12 : issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren3 = _T_99 ? issue_slots_3_out_uop_fp_ctrl_ren3 : issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren2 = _T_99 ? issue_slots_3_out_uop_fp_ctrl_ren2 : issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren1 = _T_99 ? issue_slots_3_out_uop_fp_ctrl_ren1 : issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wen = _T_99 ? issue_slots_3_out_uop_fp_ctrl_wen : issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ldst = _T_99 ? issue_slots_3_out_uop_fp_ctrl_ldst : issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op2_sel = _T_99 ? issue_slots_3_out_uop_op2_sel : issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op1_sel = _T_99 ? issue_slots_3_out_uop_op1_sel : issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_packed = _T_99 ? issue_slots_3_out_uop_imm_packed : issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pimm = _T_99 ? issue_slots_3_out_uop_pimm : issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_sel = _T_99 ? issue_slots_3_out_uop_imm_sel : issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_rename = _T_99 ? issue_slots_3_out_uop_imm_rename : issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_taken = _T_99 ? issue_slots_3_out_uop_taken : issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pc_lob = _T_99 ? issue_slots_3_out_uop_pc_lob : issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_edge_inst = _T_99 ? issue_slots_3_out_uop_edge_inst : issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ftq_idx = _T_99 ? issue_slots_3_out_uop_ftq_idx : issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_mov = _T_99 ? issue_slots_3_out_uop_is_mov : issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rocc = _T_99 ? issue_slots_3_out_uop_is_rocc : issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sys_pc2epc = _T_99 ? issue_slots_3_out_uop_is_sys_pc2epc : issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_eret = _T_99 ? issue_slots_3_out_uop_is_eret : issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_amo = _T_99 ? issue_slots_3_out_uop_is_amo : issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfence = _T_99 ? issue_slots_3_out_uop_is_sfence : issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fencei = _T_99 ? issue_slots_3_out_uop_is_fencei : issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fence = _T_99 ? issue_slots_3_out_uop_is_fence : issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfb = _T_99 ? issue_slots_3_out_uop_is_sfb : issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_type = _T_99 ? issue_slots_3_out_uop_br_type : issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_tag = _T_99 ? issue_slots_3_out_uop_br_tag : issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_mask = _T_99 ? issue_slots_3_out_uop_br_mask : issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dis_col_sel = _T_99 ? issue_slots_3_out_uop_dis_col_sel : issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p3_bypass_hint = _T_99 ? issue_slots_3_out_uop_iw_p3_bypass_hint : issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p2_bypass_hint = _T_99 ? issue_slots_3_out_uop_iw_p2_bypass_hint : issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p1_bypass_hint = _T_99 ? issue_slots_3_out_uop_iw_p1_bypass_hint : issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_issued = _T_99 ? issue_slots_3_out_uop_iw_issued : issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_0 = _T_99 ? issue_slots_3_out_uop_fu_code_0 : issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_1 = _T_99 ? issue_slots_3_out_uop_fu_code_1 : issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_2 = _T_99 ? issue_slots_3_out_uop_fu_code_2 : issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_3 = _T_99 ? issue_slots_3_out_uop_fu_code_3 : issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_4 = _T_99 ? issue_slots_3_out_uop_fu_code_4 : issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_5 = _T_99 ? issue_slots_3_out_uop_fu_code_5 : issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_6 = _T_99 ? issue_slots_3_out_uop_fu_code_6 : issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_7 = _T_99 ? issue_slots_3_out_uop_fu_code_7 : issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_8 = _T_99 ? issue_slots_3_out_uop_fu_code_8 : issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_9 = _T_99 ? issue_slots_3_out_uop_fu_code_9 : issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_0 = _T_99 ? issue_slots_3_out_uop_iq_type_0 : issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_1 = _T_99 ? issue_slots_3_out_uop_iq_type_1 : issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_2 = _T_99 ? issue_slots_3_out_uop_iq_type_2 : issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_3 = _T_99 ? issue_slots_3_out_uop_iq_type_3 : issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_pc = _T_99 ? issue_slots_3_out_uop_debug_pc : issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rvc = _T_99 ? issue_slots_3_out_uop_is_rvc : issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_inst = _T_99 ? issue_slots_3_out_uop_debug_inst : issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_inst = _T_99 ? issue_slots_3_out_uop_inst : issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_1_clear_T = \|shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_1_clear = _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_101 = shamts_oh_4 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_2_in_uop_valid = _T_101 ? issue_slots_4_will_be_valid : shamts_oh_3 == 2'h1 & issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_2_in_uop_bits_debug_tsrc = _T_101 ? issue_slots_4_out_uop_debug_tsrc : issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_fsrc = _T_101 ? issue_slots_4_out_uop_debug_fsrc : issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_xcpt_if = _T_101 ? issue_slots_4_out_uop_bp_xcpt_if : issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_debug_if = _T_101 ? issue_slots_4_out_uop_bp_debug_if : issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ma_if = _T_101 ? issue_slots_4_out_uop_xcpt_ma_if : issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ae_if = _T_101 ? issue_slots_4_out_uop_xcpt_ae_if : issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_pf_if = _T_101 ? issue_slots_4_out_uop_xcpt_pf_if : issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_typ = _T_101 ? issue_slots_4_out_uop_fp_typ : issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_rm = _T_101 ? issue_slots_4_out_uop_fp_rm : issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_val = _T_101 ? issue_slots_4_out_uop_fp_val : issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_op = _T_101 ? issue_slots_4_out_uop_fcn_op : issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_dw = _T_101 ? issue_slots_4_out_uop_fcn_dw : issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_frs3_en = _T_101 ? issue_slots_4_out_uop_frs3_en : issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2_rtype = _T_101 ? issue_slots_4_out_uop_lrs2_rtype : issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1_rtype = _T_101 ? issue_slots_4_out_uop_lrs1_rtype : issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dst_rtype = _T_101 ? issue_slots_4_out_uop_dst_rtype : issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs3 = _T_101 ? issue_slots_4_out_uop_lrs3 : issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2 = _T_101 ? issue_slots_4_out_uop_lrs2 : issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1 = _T_101 ? issue_slots_4_out_uop_lrs1 : issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst = _T_101 ? issue_slots_4_out_uop_ldst : issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst_is_rs1 = _T_101 ? issue_slots_4_out_uop_ldst_is_rs1 : issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_csr_cmd = _T_101 ? issue_slots_4_out_uop_csr_cmd : issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_flush_on_commit = _T_101 ? issue_slots_4_out_uop_flush_on_commit : issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_unique = _T_101 ? issue_slots_4_out_uop_is_unique : issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_stq = _T_101 ? issue_slots_4_out_uop_uses_stq : issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_ldq = _T_101 ? issue_slots_4_out_uop_uses_ldq : issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_signed = _T_101 ? issue_slots_4_out_uop_mem_signed : issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_size = _T_101 ? issue_slots_4_out_uop_mem_size : issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_cmd = _T_101 ? issue_slots_4_out_uop_mem_cmd : issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exc_cause = _T_101 ? issue_slots_4_out_uop_exc_cause : issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exception = _T_101 ? issue_slots_4_out_uop_exception : issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stale_pdst = _T_101 ? issue_slots_4_out_uop_stale_pdst : issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred_busy = _T_101 ? issue_slots_4_out_uop_ppred_busy : issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3_busy = _T_101 ? issue_slots_4_out_uop_prs3_busy : issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2_busy = _T_101 ? issue_slots_4_out_uop_prs2_busy : issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1_busy = _T_101 ? issue_slots_4_out_uop_prs1_busy : issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred = _T_101 ? issue_slots_4_out_uop_ppred : issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3 = _T_101 ? issue_slots_4_out_uop_prs3 : issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2 = _T_101 ? issue_slots_4_out_uop_prs2 : issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1 = _T_101 ? issue_slots_4_out_uop_prs1 : issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pdst = _T_101 ? issue_slots_4_out_uop_pdst : issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rxq_idx = _T_101 ? issue_slots_4_out_uop_rxq_idx : issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stq_idx = _T_101 ? issue_slots_4_out_uop_stq_idx : issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldq_idx = _T_101 ? issue_slots_4_out_uop_ldq_idx : issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rob_idx = _T_101 ? issue_slots_4_out_uop_rob_idx : issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_vec = _T_101 ? issue_slots_4_out_uop_fp_ctrl_vec : issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wflags = _T_101 ? issue_slots_4_out_uop_fp_ctrl_wflags : issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_sqrt = _T_101 ? issue_slots_4_out_uop_fp_ctrl_sqrt : issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_div = _T_101 ? issue_slots_4_out_uop_fp_ctrl_div : issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fma = _T_101 ? issue_slots_4_out_uop_fp_ctrl_fma : issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fastpipe = _T_101 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_toint = _T_101 ? issue_slots_4_out_uop_fp_ctrl_toint : issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fromint = _T_101 ? issue_slots_4_out_uop_fp_ctrl_fromint : issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut = _T_101 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn = _T_101 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap23 = _T_101 ? issue_slots_4_out_uop_fp_ctrl_swap23 : issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap12 = _T_101 ? issue_slots_4_out_uop_fp_ctrl_swap12 : issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren3 = _T_101 ? issue_slots_4_out_uop_fp_ctrl_ren3 : issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren2 = _T_101 ? issue_slots_4_out_uop_fp_ctrl_ren2 : issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren1 = _T_101 ? issue_slots_4_out_uop_fp_ctrl_ren1 : issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wen = _T_101 ? issue_slots_4_out_uop_fp_ctrl_wen : issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ldst = _T_101 ? issue_slots_4_out_uop_fp_ctrl_ldst : issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op2_sel = _T_101 ? issue_slots_4_out_uop_op2_sel : issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op1_sel = _T_101 ? issue_slots_4_out_uop_op1_sel : issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_packed = _T_101 ? issue_slots_4_out_uop_imm_packed : issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pimm = _T_101 ? issue_slots_4_out_uop_pimm : issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_sel = _T_101 ? issue_slots_4_out_uop_imm_sel : issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_rename = _T_101 ? issue_slots_4_out_uop_imm_rename : issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_taken = _T_101 ? issue_slots_4_out_uop_taken : issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pc_lob = _T_101 ? issue_slots_4_out_uop_pc_lob : issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_edge_inst = _T_101 ? issue_slots_4_out_uop_edge_inst : issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ftq_idx = _T_101 ? issue_slots_4_out_uop_ftq_idx : issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_mov = _T_101 ? issue_slots_4_out_uop_is_mov : issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rocc = _T_101 ? issue_slots_4_out_uop_is_rocc : issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sys_pc2epc = _T_101 ? issue_slots_4_out_uop_is_sys_pc2epc : issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_eret = _T_101 ? issue_slots_4_out_uop_is_eret : issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_amo = _T_101 ? issue_slots_4_out_uop_is_amo : issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfence = _T_101 ? issue_slots_4_out_uop_is_sfence : issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fencei = _T_101 ? issue_slots_4_out_uop_is_fencei : issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fence = _T_101 ? issue_slots_4_out_uop_is_fence : issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfb = _T_101 ? issue_slots_4_out_uop_is_sfb : issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_type = _T_101 ? issue_slots_4_out_uop_br_type : issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_tag = _T_101 ? issue_slots_4_out_uop_br_tag : issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_mask = _T_101 ? issue_slots_4_out_uop_br_mask : issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dis_col_sel = _T_101 ? issue_slots_4_out_uop_dis_col_sel : issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p3_bypass_hint = _T_101 ? issue_slots_4_out_uop_iw_p3_bypass_hint : issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p2_bypass_hint = _T_101 ? issue_slots_4_out_uop_iw_p2_bypass_hint : issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p1_bypass_hint = _T_101 ? issue_slots_4_out_uop_iw_p1_bypass_hint : issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_issued = _T_101 ? issue_slots_4_out_uop_iw_issued : issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_0 = _T_101 ? issue_slots_4_out_uop_fu_code_0 : issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_1 = _T_101 ? issue_slots_4_out_uop_fu_code_1 : issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_2 = _T_101 ? issue_slots_4_out_uop_fu_code_2 : issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_3 = _T_101 ? issue_slots_4_out_uop_fu_code_3 : issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_4 = _T_101 ? issue_slots_4_out_uop_fu_code_4 : issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_5 = _T_101 ? issue_slots_4_out_uop_fu_code_5 : issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_6 = _T_101 ? issue_slots_4_out_uop_fu_code_6 : issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_7 = _T_101 ? issue_slots_4_out_uop_fu_code_7 : issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_8 = _T_101 ? issue_slots_4_out_uop_fu_code_8 : issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_9 = _T_101 ? issue_slots_4_out_uop_fu_code_9 : issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_0 = _T_101 ? issue_slots_4_out_uop_iq_type_0 : issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_1 = _T_101 ? issue_slots_4_out_uop_iq_type_1 : issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_2 = _T_101 ? issue_slots_4_out_uop_iq_type_2 : issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_3 = _T_101 ? issue_slots_4_out_uop_iq_type_3 : issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_pc = _T_101 ? issue_slots_4_out_uop_debug_pc : issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rvc = _T_101 ? issue_slots_4_out_uop_is_rvc : issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_inst = _T_101 ? issue_slots_4_out_uop_debug_inst : issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_inst = _T_101 ? issue_slots_4_out_uop_inst : issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_2_clear_T = \|shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_2_clear = _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_103 = shamts_oh_5 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_3_in_uop_valid = _T_103 ? issue_slots_5_will_be_valid : shamts_oh_4 == 2'h1 & issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_3_in_uop_bits_debug_tsrc = _T_103 ? issue_slots_5_out_uop_debug_tsrc : issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_fsrc = _T_103 ? issue_slots_5_out_uop_debug_fsrc : issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_xcpt_if = _T_103 ? issue_slots_5_out_uop_bp_xcpt_if : issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_debug_if = _T_103 ? issue_slots_5_out_uop_bp_debug_if : issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ma_if = _T_103 ? issue_slots_5_out_uop_xcpt_ma_if : issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ae_if = _T_103 ? issue_slots_5_out_uop_xcpt_ae_if : issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_pf_if = _T_103 ? issue_slots_5_out_uop_xcpt_pf_if : issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_typ = _T_103 ? issue_slots_5_out_uop_fp_typ : issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_rm = _T_103 ? issue_slots_5_out_uop_fp_rm : issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_val = _T_103 ? issue_slots_5_out_uop_fp_val : issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_op = _T_103 ? issue_slots_5_out_uop_fcn_op : issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_dw = _T_103 ? issue_slots_5_out_uop_fcn_dw : issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_frs3_en = _T_103 ? issue_slots_5_out_uop_frs3_en : issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2_rtype = _T_103 ? issue_slots_5_out_uop_lrs2_rtype : issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1_rtype = _T_103 ? issue_slots_5_out_uop_lrs1_rtype : issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dst_rtype = _T_103 ? issue_slots_5_out_uop_dst_rtype : issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs3 = _T_103 ? issue_slots_5_out_uop_lrs3 : issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2 = _T_103 ? issue_slots_5_out_uop_lrs2 : issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1 = _T_103 ? issue_slots_5_out_uop_lrs1 : issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst = _T_103 ? issue_slots_5_out_uop_ldst : issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst_is_rs1 = _T_103 ? issue_slots_5_out_uop_ldst_is_rs1 : issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_csr_cmd = _T_103 ? issue_slots_5_out_uop_csr_cmd : issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_flush_on_commit = _T_103 ? issue_slots_5_out_uop_flush_on_commit : issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_unique = _T_103 ? issue_slots_5_out_uop_is_unique : issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_stq = _T_103 ? issue_slots_5_out_uop_uses_stq : issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_ldq = _T_103 ? issue_slots_5_out_uop_uses_ldq : issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_signed = _T_103 ? issue_slots_5_out_uop_mem_signed : issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_size = _T_103 ? issue_slots_5_out_uop_mem_size : issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_cmd = _T_103 ? issue_slots_5_out_uop_mem_cmd : issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exc_cause = _T_103 ? issue_slots_5_out_uop_exc_cause : issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exception = _T_103 ? issue_slots_5_out_uop_exception : issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stale_pdst = _T_103 ? issue_slots_5_out_uop_stale_pdst : issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred_busy = _T_103 ? issue_slots_5_out_uop_ppred_busy : issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3_busy = _T_103 ? issue_slots_5_out_uop_prs3_busy : issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2_busy = _T_103 ? issue_slots_5_out_uop_prs2_busy : issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1_busy = _T_103 ? issue_slots_5_out_uop_prs1_busy : issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred = _T_103 ? issue_slots_5_out_uop_ppred : issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3 = _T_103 ? issue_slots_5_out_uop_prs3 : issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2 = _T_103 ? issue_slots_5_out_uop_prs2 : issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1 = _T_103 ? issue_slots_5_out_uop_prs1 : issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pdst = _T_103 ? issue_slots_5_out_uop_pdst : issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rxq_idx = _T_103 ? issue_slots_5_out_uop_rxq_idx : issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stq_idx = _T_103 ? issue_slots_5_out_uop_stq_idx : issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldq_idx = _T_103 ? issue_slots_5_out_uop_ldq_idx : issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rob_idx = _T_103 ? issue_slots_5_out_uop_rob_idx : issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_vec = _T_103 ? issue_slots_5_out_uop_fp_ctrl_vec : issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wflags = _T_103 ? issue_slots_5_out_uop_fp_ctrl_wflags : issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_sqrt = _T_103 ? issue_slots_5_out_uop_fp_ctrl_sqrt : issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_div = _T_103 ? issue_slots_5_out_uop_fp_ctrl_div : issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fma = _T_103 ? issue_slots_5_out_uop_fp_ctrl_fma : issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fastpipe = _T_103 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_toint = _T_103 ? issue_slots_5_out_uop_fp_ctrl_toint : issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fromint = _T_103 ? issue_slots_5_out_uop_fp_ctrl_fromint : issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut = _T_103 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn = _T_103 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap23 = _T_103 ? issue_slots_5_out_uop_fp_ctrl_swap23 : issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap12 = _T_103 ? issue_slots_5_out_uop_fp_ctrl_swap12 : issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren3 = _T_103 ? issue_slots_5_out_uop_fp_ctrl_ren3 : issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren2 = _T_103 ? issue_slots_5_out_uop_fp_ctrl_ren2 : issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren1 = _T_103 ? issue_slots_5_out_uop_fp_ctrl_ren1 : issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wen = _T_103 ? issue_slots_5_out_uop_fp_ctrl_wen : issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ldst = _T_103 ? issue_slots_5_out_uop_fp_ctrl_ldst : issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op2_sel = _T_103 ? issue_slots_5_out_uop_op2_sel : issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op1_sel = _T_103 ? issue_slots_5_out_uop_op1_sel : issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_packed = _T_103 ? issue_slots_5_out_uop_imm_packed : issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pimm = _T_103 ? issue_slots_5_out_uop_pimm : issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_sel = _T_103 ? issue_slots_5_out_uop_imm_sel : issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_rename = _T_103 ? issue_slots_5_out_uop_imm_rename : issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_taken = _T_103 ? issue_slots_5_out_uop_taken : issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pc_lob = _T_103 ? issue_slots_5_out_uop_pc_lob : issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_edge_inst = _T_103 ? issue_slots_5_out_uop_edge_inst : issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ftq_idx = _T_103 ? issue_slots_5_out_uop_ftq_idx : issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_mov = _T_103 ? issue_slots_5_out_uop_is_mov : issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rocc = _T_103 ? issue_slots_5_out_uop_is_rocc : issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sys_pc2epc = _T_103 ? issue_slots_5_out_uop_is_sys_pc2epc : issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_eret = _T_103 ? issue_slots_5_out_uop_is_eret : issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_amo = _T_103 ? issue_slots_5_out_uop_is_amo : issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfence = _T_103 ? issue_slots_5_out_uop_is_sfence : issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fencei = _T_103 ? issue_slots_5_out_uop_is_fencei : issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fence = _T_103 ? issue_slots_5_out_uop_is_fence : issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfb = _T_103 ? issue_slots_5_out_uop_is_sfb : issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_type = _T_103 ? issue_slots_5_out_uop_br_type : issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_tag = _T_103 ? issue_slots_5_out_uop_br_tag : issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_mask = _T_103 ? issue_slots_5_out_uop_br_mask : issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dis_col_sel = _T_103 ? issue_slots_5_out_uop_dis_col_sel : issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p3_bypass_hint = _T_103 ? issue_slots_5_out_uop_iw_p3_bypass_hint : issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p2_bypass_hint = _T_103 ? issue_slots_5_out_uop_iw_p2_bypass_hint : issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p1_bypass_hint = _T_103 ? issue_slots_5_out_uop_iw_p1_bypass_hint : issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_issued = _T_103 ? issue_slots_5_out_uop_iw_issued : issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_0 = _T_103 ? issue_slots_5_out_uop_fu_code_0 : issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_1 = _T_103 ? issue_slots_5_out_uop_fu_code_1 : issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_2 = _T_103 ? issue_slots_5_out_uop_fu_code_2 : issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_3 = _T_103 ? issue_slots_5_out_uop_fu_code_3 : issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_4 = _T_103 ? issue_slots_5_out_uop_fu_code_4 : issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_5 = _T_103 ? issue_slots_5_out_uop_fu_code_5 : issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_6 = _T_103 ? issue_slots_5_out_uop_fu_code_6 : issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_7 = _T_103 ? issue_slots_5_out_uop_fu_code_7 : issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_8 = _T_103 ? issue_slots_5_out_uop_fu_code_8 : issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_9 = _T_103 ? issue_slots_5_out_uop_fu_code_9 : issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_0 = _T_103 ? issue_slots_5_out_uop_iq_type_0 : issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_1 = _T_103 ? issue_slots_5_out_uop_iq_type_1 : issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_2 = _T_103 ? issue_slots_5_out_uop_iq_type_2 : issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_3 = _T_103 ? issue_slots_5_out_uop_iq_type_3 : issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_pc = _T_103 ? issue_slots_5_out_uop_debug_pc : issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rvc = _T_103 ? issue_slots_5_out_uop_is_rvc : issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_inst = _T_103 ? issue_slots_5_out_uop_debug_inst : issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_inst = _T_103 ? issue_slots_5_out_uop_inst : issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_3_clear_T = \|shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_3_clear = _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_105 = shamts_oh_6 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_4_in_uop_valid = _T_105 ? issue_slots_6_will_be_valid : shamts_oh_5 == 2'h1 & issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_4_in_uop_bits_debug_tsrc = _T_105 ? issue_slots_6_out_uop_debug_tsrc : issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_fsrc = _T_105 ? issue_slots_6_out_uop_debug_fsrc : issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_xcpt_if = _T_105 ? issue_slots_6_out_uop_bp_xcpt_if : issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_debug_if = _T_105 ? issue_slots_6_out_uop_bp_debug_if : issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ma_if = _T_105 ? issue_slots_6_out_uop_xcpt_ma_if : issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ae_if = _T_105 ? issue_slots_6_out_uop_xcpt_ae_if : issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_pf_if = _T_105 ? issue_slots_6_out_uop_xcpt_pf_if : issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_typ = _T_105 ? issue_slots_6_out_uop_fp_typ : issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_rm = _T_105 ? issue_slots_6_out_uop_fp_rm : issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_val = _T_105 ? issue_slots_6_out_uop_fp_val : issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_op = _T_105 ? issue_slots_6_out_uop_fcn_op : issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_dw = _T_105 ? issue_slots_6_out_uop_fcn_dw : issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_frs3_en = _T_105 ? issue_slots_6_out_uop_frs3_en : issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2_rtype = _T_105 ? issue_slots_6_out_uop_lrs2_rtype : issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1_rtype = _T_105 ? issue_slots_6_out_uop_lrs1_rtype : issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dst_rtype = _T_105 ? issue_slots_6_out_uop_dst_rtype : issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs3 = _T_105 ? issue_slots_6_out_uop_lrs3 : issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2 = _T_105 ? issue_slots_6_out_uop_lrs2 : issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1 = _T_105 ? issue_slots_6_out_uop_lrs1 : issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst = _T_105 ? issue_slots_6_out_uop_ldst : issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst_is_rs1 = _T_105 ? issue_slots_6_out_uop_ldst_is_rs1 : issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_csr_cmd = _T_105 ? issue_slots_6_out_uop_csr_cmd : issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_flush_on_commit = _T_105 ? issue_slots_6_out_uop_flush_on_commit : issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_unique = _T_105 ? issue_slots_6_out_uop_is_unique : issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_stq = _T_105 ? issue_slots_6_out_uop_uses_stq : issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_ldq = _T_105 ? issue_slots_6_out_uop_uses_ldq : issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_signed = _T_105 ? issue_slots_6_out_uop_mem_signed : issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_size = _T_105 ? issue_slots_6_out_uop_mem_size : issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_cmd = _T_105 ? issue_slots_6_out_uop_mem_cmd : issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exc_cause = _T_105 ? issue_slots_6_out_uop_exc_cause : issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exception = _T_105 ? issue_slots_6_out_uop_exception : issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stale_pdst = _T_105 ? issue_slots_6_out_uop_stale_pdst : issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred_busy = _T_105 ? issue_slots_6_out_uop_ppred_busy : issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3_busy = _T_105 ? issue_slots_6_out_uop_prs3_busy : issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2_busy = _T_105 ? issue_slots_6_out_uop_prs2_busy : issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1_busy = _T_105 ? issue_slots_6_out_uop_prs1_busy : issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred = _T_105 ? issue_slots_6_out_uop_ppred : issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3 = _T_105 ? issue_slots_6_out_uop_prs3 : issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2 = _T_105 ? issue_slots_6_out_uop_prs2 : issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1 = _T_105 ? issue_slots_6_out_uop_prs1 : issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pdst = _T_105 ? issue_slots_6_out_uop_pdst : issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rxq_idx = _T_105 ? issue_slots_6_out_uop_rxq_idx : issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stq_idx = _T_105 ? issue_slots_6_out_uop_stq_idx : issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldq_idx = _T_105 ? issue_slots_6_out_uop_ldq_idx : issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rob_idx = _T_105 ? issue_slots_6_out_uop_rob_idx : issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_vec = _T_105 ? issue_slots_6_out_uop_fp_ctrl_vec : issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wflags = _T_105 ? issue_slots_6_out_uop_fp_ctrl_wflags : issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_sqrt = _T_105 ? issue_slots_6_out_uop_fp_ctrl_sqrt : issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_div = _T_105 ? issue_slots_6_out_uop_fp_ctrl_div : issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fma = _T_105 ? issue_slots_6_out_uop_fp_ctrl_fma : issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fastpipe = _T_105 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_toint = _T_105 ? issue_slots_6_out_uop_fp_ctrl_toint : issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fromint = _T_105 ? issue_slots_6_out_uop_fp_ctrl_fromint : issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut = _T_105 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn = _T_105 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap23 = _T_105 ? issue_slots_6_out_uop_fp_ctrl_swap23 : issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap12 = _T_105 ? issue_slots_6_out_uop_fp_ctrl_swap12 : issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren3 = _T_105 ? issue_slots_6_out_uop_fp_ctrl_ren3 : issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren2 = _T_105 ? issue_slots_6_out_uop_fp_ctrl_ren2 : issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren1 = _T_105 ? issue_slots_6_out_uop_fp_ctrl_ren1 : issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wen = _T_105 ? issue_slots_6_out_uop_fp_ctrl_wen : issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ldst = _T_105 ? issue_slots_6_out_uop_fp_ctrl_ldst : issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op2_sel = _T_105 ? issue_slots_6_out_uop_op2_sel : issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op1_sel = _T_105 ? issue_slots_6_out_uop_op1_sel : issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_packed = _T_105 ? issue_slots_6_out_uop_imm_packed : issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pimm = _T_105 ? issue_slots_6_out_uop_pimm : issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_sel = _T_105 ? issue_slots_6_out_uop_imm_sel : issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_rename = _T_105 ? issue_slots_6_out_uop_imm_rename : issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_taken = _T_105 ? issue_slots_6_out_uop_taken : issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pc_lob = _T_105 ? issue_slots_6_out_uop_pc_lob : issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_edge_inst = _T_105 ? issue_slots_6_out_uop_edge_inst : issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ftq_idx = _T_105 ? issue_slots_6_out_uop_ftq_idx : issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_mov = _T_105 ? issue_slots_6_out_uop_is_mov : issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rocc = _T_105 ? issue_slots_6_out_uop_is_rocc : issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sys_pc2epc = _T_105 ? issue_slots_6_out_uop_is_sys_pc2epc : issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_eret = _T_105 ? issue_slots_6_out_uop_is_eret : issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_amo = _T_105 ? issue_slots_6_out_uop_is_amo : issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfence = _T_105 ? issue_slots_6_out_uop_is_sfence : issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fencei = _T_105 ? issue_slots_6_out_uop_is_fencei : issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fence = _T_105 ? issue_slots_6_out_uop_is_fence : issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfb = _T_105 ? issue_slots_6_out_uop_is_sfb : issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_type = _T_105 ? issue_slots_6_out_uop_br_type : issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_tag = _T_105 ? issue_slots_6_out_uop_br_tag : issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_mask = _T_105 ? issue_slots_6_out_uop_br_mask : issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dis_col_sel = _T_105 ? issue_slots_6_out_uop_dis_col_sel : issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p3_bypass_hint = _T_105 ? issue_slots_6_out_uop_iw_p3_bypass_hint : issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p2_bypass_hint = _T_105 ? issue_slots_6_out_uop_iw_p2_bypass_hint : issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p1_bypass_hint = _T_105 ? issue_slots_6_out_uop_iw_p1_bypass_hint : issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_issued = _T_105 ? issue_slots_6_out_uop_iw_issued : issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_0 = _T_105 ? issue_slots_6_out_uop_fu_code_0 : issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_1 = _T_105 ? issue_slots_6_out_uop_fu_code_1 : issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_2 = _T_105 ? issue_slots_6_out_uop_fu_code_2 : issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_3 = _T_105 ? issue_slots_6_out_uop_fu_code_3 : issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_4 = _T_105 ? issue_slots_6_out_uop_fu_code_4 : issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_5 = _T_105 ? issue_slots_6_out_uop_fu_code_5 : issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_6 = _T_105 ? issue_slots_6_out_uop_fu_code_6 : issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_7 = _T_105 ? issue_slots_6_out_uop_fu_code_7 : issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_8 = _T_105 ? issue_slots_6_out_uop_fu_code_8 : issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_9 = _T_105 ? issue_slots_6_out_uop_fu_code_9 : issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_0 = _T_105 ? issue_slots_6_out_uop_iq_type_0 : issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_1 = _T_105 ? issue_slots_6_out_uop_iq_type_1 : issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_2 = _T_105 ? issue_slots_6_out_uop_iq_type_2 : issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_3 = _T_105 ? issue_slots_6_out_uop_iq_type_3 : issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_pc = _T_105 ? issue_slots_6_out_uop_debug_pc : issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rvc = _T_105 ? issue_slots_6_out_uop_is_rvc : issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_inst = _T_105 ? issue_slots_6_out_uop_debug_inst : issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_inst = _T_105 ? issue_slots_6_out_uop_inst : issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_4_clear_T = \|shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_4_clear = _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_107 = shamts_oh_7 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_5_in_uop_valid = _T_107 ? issue_slots_7_will_be_valid : shamts_oh_6 == 2'h1 & issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_5_in_uop_bits_debug_tsrc = _T_107 ? issue_slots_7_out_uop_debug_tsrc : issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_fsrc = _T_107 ? issue_slots_7_out_uop_debug_fsrc : issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_xcpt_if = _T_107 ? issue_slots_7_out_uop_bp_xcpt_if : issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_debug_if = _T_107 ? issue_slots_7_out_uop_bp_debug_if : issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ma_if = _T_107 ? issue_slots_7_out_uop_xcpt_ma_if : issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ae_if = _T_107 ? issue_slots_7_out_uop_xcpt_ae_if : issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_pf_if = _T_107 ? issue_slots_7_out_uop_xcpt_pf_if : issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_typ = _T_107 ? issue_slots_7_out_uop_fp_typ : issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_rm = _T_107 ? issue_slots_7_out_uop_fp_rm : issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_val = _T_107 ? issue_slots_7_out_uop_fp_val : issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_op = _T_107 ? issue_slots_7_out_uop_fcn_op : issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_dw = _T_107 ? issue_slots_7_out_uop_fcn_dw : issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_frs3_en = _T_107 ? issue_slots_7_out_uop_frs3_en : issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2_rtype = _T_107 ? issue_slots_7_out_uop_lrs2_rtype : issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1_rtype = _T_107 ? issue_slots_7_out_uop_lrs1_rtype : issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dst_rtype = _T_107 ? issue_slots_7_out_uop_dst_rtype : issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs3 = _T_107 ? issue_slots_7_out_uop_lrs3 : issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2 = _T_107 ? issue_slots_7_out_uop_lrs2 : issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1 = _T_107 ? issue_slots_7_out_uop_lrs1 : issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst = _T_107 ? issue_slots_7_out_uop_ldst : issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst_is_rs1 = _T_107 ? issue_slots_7_out_uop_ldst_is_rs1 : issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_csr_cmd = _T_107 ? issue_slots_7_out_uop_csr_cmd : issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_flush_on_commit = _T_107 ? issue_slots_7_out_uop_flush_on_commit : issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_unique = _T_107 ? issue_slots_7_out_uop_is_unique : issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_stq = _T_107 ? issue_slots_7_out_uop_uses_stq : issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_ldq = _T_107 ? issue_slots_7_out_uop_uses_ldq : issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_signed = _T_107 ? issue_slots_7_out_uop_mem_signed : issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_size = _T_107 ? issue_slots_7_out_uop_mem_size : issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_cmd = _T_107 ? issue_slots_7_out_uop_mem_cmd : issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exc_cause = _T_107 ? issue_slots_7_out_uop_exc_cause : issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exception = _T_107 ? issue_slots_7_out_uop_exception : issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stale_pdst = _T_107 ? issue_slots_7_out_uop_stale_pdst : issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred_busy = _T_107 ? issue_slots_7_out_uop_ppred_busy : issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3_busy = _T_107 ? issue_slots_7_out_uop_prs3_busy : issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2_busy = _T_107 ? issue_slots_7_out_uop_prs2_busy : issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1_busy = _T_107 ? issue_slots_7_out_uop_prs1_busy : issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred = _T_107 ? issue_slots_7_out_uop_ppred : issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3 = _T_107 ? issue_slots_7_out_uop_prs3 : issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2 = _T_107 ? issue_slots_7_out_uop_prs2 : issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1 = _T_107 ? issue_slots_7_out_uop_prs1 : issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pdst = _T_107 ? issue_slots_7_out_uop_pdst : issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rxq_idx = _T_107 ? issue_slots_7_out_uop_rxq_idx : issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stq_idx = _T_107 ? issue_slots_7_out_uop_stq_idx : issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldq_idx = _T_107 ? issue_slots_7_out_uop_ldq_idx : issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rob_idx = _T_107 ? issue_slots_7_out_uop_rob_idx : issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_vec = _T_107 ? issue_slots_7_out_uop_fp_ctrl_vec : issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wflags = _T_107 ? issue_slots_7_out_uop_fp_ctrl_wflags : issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_sqrt = _T_107 ? issue_slots_7_out_uop_fp_ctrl_sqrt : issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_div = _T_107 ? issue_slots_7_out_uop_fp_ctrl_div : issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fma = _T_107 ? issue_slots_7_out_uop_fp_ctrl_fma : issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fastpipe = _T_107 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_toint = _T_107 ? issue_slots_7_out_uop_fp_ctrl_toint : issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fromint = _T_107 ? issue_slots_7_out_uop_fp_ctrl_fromint : issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut = _T_107 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn = _T_107 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap23 = _T_107 ? issue_slots_7_out_uop_fp_ctrl_swap23 : issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap12 = _T_107 ? issue_slots_7_out_uop_fp_ctrl_swap12 : issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren3 = _T_107 ? issue_slots_7_out_uop_fp_ctrl_ren3 : issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren2 = _T_107 ? issue_slots_7_out_uop_fp_ctrl_ren2 : issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren1 = _T_107 ? issue_slots_7_out_uop_fp_ctrl_ren1 : issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wen = _T_107 ? issue_slots_7_out_uop_fp_ctrl_wen : issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ldst = _T_107 ? issue_slots_7_out_uop_fp_ctrl_ldst : issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op2_sel = _T_107 ? issue_slots_7_out_uop_op2_sel : issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op1_sel = _T_107 ? issue_slots_7_out_uop_op1_sel : issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_packed = _T_107 ? issue_slots_7_out_uop_imm_packed : issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pimm = _T_107 ? issue_slots_7_out_uop_pimm : issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_sel = _T_107 ? issue_slots_7_out_uop_imm_sel : issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_rename = _T_107 ? issue_slots_7_out_uop_imm_rename : issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_taken = _T_107 ? issue_slots_7_out_uop_taken : issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pc_lob = _T_107 ? issue_slots_7_out_uop_pc_lob : issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_edge_inst = _T_107 ? issue_slots_7_out_uop_edge_inst : issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ftq_idx = _T_107 ? issue_slots_7_out_uop_ftq_idx : issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_mov = _T_107 ? issue_slots_7_out_uop_is_mov : issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rocc = _T_107 ? issue_slots_7_out_uop_is_rocc : issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sys_pc2epc = _T_107 ? issue_slots_7_out_uop_is_sys_pc2epc : issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_eret = _T_107 ? issue_slots_7_out_uop_is_eret : issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_amo = _T_107 ? issue_slots_7_out_uop_is_amo : issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfence = _T_107 ? issue_slots_7_out_uop_is_sfence : issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fencei = _T_107 ? issue_slots_7_out_uop_is_fencei : issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fence = _T_107 ? issue_slots_7_out_uop_is_fence : issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfb = _T_107 ? issue_slots_7_out_uop_is_sfb : issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_type = _T_107 ? issue_slots_7_out_uop_br_type : issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_tag = _T_107 ? issue_slots_7_out_uop_br_tag : issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_mask = _T_107 ? issue_slots_7_out_uop_br_mask : issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dis_col_sel = _T_107 ? issue_slots_7_out_uop_dis_col_sel : issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p3_bypass_hint = _T_107 ? issue_slots_7_out_uop_iw_p3_bypass_hint : issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p2_bypass_hint = _T_107 ? issue_slots_7_out_uop_iw_p2_bypass_hint : issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p1_bypass_hint = _T_107 ? issue_slots_7_out_uop_iw_p1_bypass_hint : issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_issued = _T_107 ? issue_slots_7_out_uop_iw_issued : issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_0 = _T_107 ? issue_slots_7_out_uop_fu_code_0 : issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_1 = _T_107 ? issue_slots_7_out_uop_fu_code_1 : issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_2 = _T_107 ? issue_slots_7_out_uop_fu_code_2 : issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_3 = _T_107 ? issue_slots_7_out_uop_fu_code_3 : issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_4 = _T_107 ? issue_slots_7_out_uop_fu_code_4 : issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_5 = _T_107 ? issue_slots_7_out_uop_fu_code_5 : issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_6 = _T_107 ? issue_slots_7_out_uop_fu_code_6 : issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_7 = _T_107 ? issue_slots_7_out_uop_fu_code_7 : issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_8 = _T_107 ? issue_slots_7_out_uop_fu_code_8 : issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_9 = _T_107 ? issue_slots_7_out_uop_fu_code_9 : issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_0 = _T_107 ? issue_slots_7_out_uop_iq_type_0 : issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_1 = _T_107 ? issue_slots_7_out_uop_iq_type_1 : issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_2 = _T_107 ? issue_slots_7_out_uop_iq_type_2 : issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_3 = _T_107 ? issue_slots_7_out_uop_iq_type_3 : issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_pc = _T_107 ? issue_slots_7_out_uop_debug_pc : issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rvc = _T_107 ? issue_slots_7_out_uop_is_rvc : issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_inst = _T_107 ? issue_slots_7_out_uop_debug_inst : issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_inst = _T_107 ? issue_slots_7_out_uop_inst : issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_5_clear_T = \|shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_5_clear = _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_109 = shamts_oh_8 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_6_in_uop_valid = _T_109 ? issue_slots_8_will_be_valid : shamts_oh_7 == 2'h1 & issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_6_in_uop_bits_debug_tsrc = _T_109 ? issue_slots_8_out_uop_debug_tsrc : issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_fsrc = _T_109 ? issue_slots_8_out_uop_debug_fsrc : issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_xcpt_if = _T_109 ? issue_slots_8_out_uop_bp_xcpt_if : issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_debug_if = _T_109 ? issue_slots_8_out_uop_bp_debug_if : issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ma_if = _T_109 ? issue_slots_8_out_uop_xcpt_ma_if : issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ae_if = _T_109 ? issue_slots_8_out_uop_xcpt_ae_if : issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_pf_if = _T_109 ? issue_slots_8_out_uop_xcpt_pf_if : issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_typ = _T_109 ? issue_slots_8_out_uop_fp_typ : issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_rm = _T_109 ? issue_slots_8_out_uop_fp_rm : issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_val = _T_109 ? issue_slots_8_out_uop_fp_val : issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_op = _T_109 ? issue_slots_8_out_uop_fcn_op : issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_dw = _T_109 ? issue_slots_8_out_uop_fcn_dw : issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_frs3_en = _T_109 ? issue_slots_8_out_uop_frs3_en : issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2_rtype = _T_109 ? issue_slots_8_out_uop_lrs2_rtype : issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1_rtype = _T_109 ? issue_slots_8_out_uop_lrs1_rtype : issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dst_rtype = _T_109 ? issue_slots_8_out_uop_dst_rtype : issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs3 = _T_109 ? issue_slots_8_out_uop_lrs3 : issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2 = _T_109 ? issue_slots_8_out_uop_lrs2 : issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1 = _T_109 ? issue_slots_8_out_uop_lrs1 : issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst = _T_109 ? issue_slots_8_out_uop_ldst : issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst_is_rs1 = _T_109 ? issue_slots_8_out_uop_ldst_is_rs1 : issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_csr_cmd = _T_109 ? issue_slots_8_out_uop_csr_cmd : issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_flush_on_commit = _T_109 ? issue_slots_8_out_uop_flush_on_commit : issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_unique = _T_109 ? issue_slots_8_out_uop_is_unique : issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_stq = _T_109 ? issue_slots_8_out_uop_uses_stq : issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_ldq = _T_109 ? issue_slots_8_out_uop_uses_ldq : issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_signed = _T_109 ? issue_slots_8_out_uop_mem_signed : issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_size = _T_109 ? issue_slots_8_out_uop_mem_size : issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_cmd = _T_109 ? issue_slots_8_out_uop_mem_cmd : issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exc_cause = _T_109 ? issue_slots_8_out_uop_exc_cause : issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exception = _T_109 ? issue_slots_8_out_uop_exception : issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stale_pdst = _T_109 ? issue_slots_8_out_uop_stale_pdst : issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred_busy = _T_109 ? issue_slots_8_out_uop_ppred_busy : issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3_busy = _T_109 ? issue_slots_8_out_uop_prs3_busy : issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2_busy = _T_109 ? issue_slots_8_out_uop_prs2_busy : issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1_busy = _T_109 ? issue_slots_8_out_uop_prs1_busy : issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred = _T_109 ? issue_slots_8_out_uop_ppred : issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3 = _T_109 ? issue_slots_8_out_uop_prs3 : issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2 = _T_109 ? issue_slots_8_out_uop_prs2 : issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1 = _T_109 ? issue_slots_8_out_uop_prs1 : issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pdst = _T_109 ? issue_slots_8_out_uop_pdst : issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rxq_idx = _T_109 ? issue_slots_8_out_uop_rxq_idx : issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stq_idx = _T_109 ? issue_slots_8_out_uop_stq_idx : issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldq_idx = _T_109 ? issue_slots_8_out_uop_ldq_idx : issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rob_idx = _T_109 ? issue_slots_8_out_uop_rob_idx : issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_vec = _T_109 ? issue_slots_8_out_uop_fp_ctrl_vec : issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wflags = _T_109 ? issue_slots_8_out_uop_fp_ctrl_wflags : issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_sqrt = _T_109 ? issue_slots_8_out_uop_fp_ctrl_sqrt : issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_div = _T_109 ? issue_slots_8_out_uop_fp_ctrl_div : issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fma = _T_109 ? issue_slots_8_out_uop_fp_ctrl_fma : issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fastpipe = _T_109 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_toint = _T_109 ? issue_slots_8_out_uop_fp_ctrl_toint : issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fromint = _T_109 ? issue_slots_8_out_uop_fp_ctrl_fromint : issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut = _T_109 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn = _T_109 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap23 = _T_109 ? issue_slots_8_out_uop_fp_ctrl_swap23 : issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap12 = _T_109 ? issue_slots_8_out_uop_fp_ctrl_swap12 : issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren3 = _T_109 ? issue_slots_8_out_uop_fp_ctrl_ren3 : issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren2 = _T_109 ? issue_slots_8_out_uop_fp_ctrl_ren2 : issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren1 = _T_109 ? issue_slots_8_out_uop_fp_ctrl_ren1 : issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wen = _T_109 ? issue_slots_8_out_uop_fp_ctrl_wen : issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ldst = _T_109 ? issue_slots_8_out_uop_fp_ctrl_ldst : issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op2_sel = _T_109 ? issue_slots_8_out_uop_op2_sel : issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op1_sel = _T_109 ? issue_slots_8_out_uop_op1_sel : issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_packed = _T_109 ? issue_slots_8_out_uop_imm_packed : issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pimm = _T_109 ? issue_slots_8_out_uop_pimm : issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_sel = _T_109 ? issue_slots_8_out_uop_imm_sel : issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_rename = _T_109 ? issue_slots_8_out_uop_imm_rename : issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_taken = _T_109 ? issue_slots_8_out_uop_taken : issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pc_lob = _T_109 ? issue_slots_8_out_uop_pc_lob : issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_edge_inst = _T_109 ? issue_slots_8_out_uop_edge_inst : issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ftq_idx = _T_109 ? issue_slots_8_out_uop_ftq_idx : issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_mov = _T_109 ? issue_slots_8_out_uop_is_mov : issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rocc = _T_109 ? issue_slots_8_out_uop_is_rocc : issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sys_pc2epc = _T_109 ? issue_slots_8_out_uop_is_sys_pc2epc : issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_eret = _T_109 ? issue_slots_8_out_uop_is_eret : issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_amo = _T_109 ? issue_slots_8_out_uop_is_amo : issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfence = _T_109 ? issue_slots_8_out_uop_is_sfence : issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fencei = _T_109 ? issue_slots_8_out_uop_is_fencei : issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fence = _T_109 ? issue_slots_8_out_uop_is_fence : issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfb = _T_109 ? issue_slots_8_out_uop_is_sfb : issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_type = _T_109 ? issue_slots_8_out_uop_br_type : issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_tag = _T_109 ? issue_slots_8_out_uop_br_tag : issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_mask = _T_109 ? issue_slots_8_out_uop_br_mask : issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dis_col_sel = _T_109 ? issue_slots_8_out_uop_dis_col_sel : issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p3_bypass_hint = _T_109 ? issue_slots_8_out_uop_iw_p3_bypass_hint : issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p2_bypass_hint = _T_109 ? issue_slots_8_out_uop_iw_p2_bypass_hint : issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p1_bypass_hint = _T_109 ? issue_slots_8_out_uop_iw_p1_bypass_hint : issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_issued = _T_109 ? issue_slots_8_out_uop_iw_issued : issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_0 = _T_109 ? issue_slots_8_out_uop_fu_code_0 : issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_1 = _T_109 ? issue_slots_8_out_uop_fu_code_1 : issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_2 = _T_109 ? issue_slots_8_out_uop_fu_code_2 : issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_3 = _T_109 ? issue_slots_8_out_uop_fu_code_3 : issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_4 = _T_109 ? issue_slots_8_out_uop_fu_code_4 : issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_5 = _T_109 ? issue_slots_8_out_uop_fu_code_5 : issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_6 = _T_109 ? issue_slots_8_out_uop_fu_code_6 : issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_7 = _T_109 ? issue_slots_8_out_uop_fu_code_7 : issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_8 = _T_109 ? issue_slots_8_out_uop_fu_code_8 : issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_9 = _T_109 ? issue_slots_8_out_uop_fu_code_9 : issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_0 = _T_109 ? issue_slots_8_out_uop_iq_type_0 : issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_1 = _T_109 ? issue_slots_8_out_uop_iq_type_1 : issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_2 = _T_109 ? issue_slots_8_out_uop_iq_type_2 : issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_3 = _T_109 ? issue_slots_8_out_uop_iq_type_3 : issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_pc = _T_109 ? issue_slots_8_out_uop_debug_pc : issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rvc = _T_109 ? issue_slots_8_out_uop_is_rvc : issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_inst = _T_109 ? issue_slots_8_out_uop_debug_inst : issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_inst = _T_109 ? issue_slots_8_out_uop_inst : issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_6_clear_T = \|shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_6_clear = _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_111 = shamts_oh_9 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_7_in_uop_valid = _T_111 ? issue_slots_9_will_be_valid : shamts_oh_8 == 2'h1 & issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_7_in_uop_bits_debug_tsrc = _T_111 ? issue_slots_9_out_uop_debug_tsrc : issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_fsrc = _T_111 ? issue_slots_9_out_uop_debug_fsrc : issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_xcpt_if = _T_111 ? issue_slots_9_out_uop_bp_xcpt_if : issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_debug_if = _T_111 ? issue_slots_9_out_uop_bp_debug_if : issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ma_if = _T_111 ? issue_slots_9_out_uop_xcpt_ma_if : issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ae_if = _T_111 ? issue_slots_9_out_uop_xcpt_ae_if : issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_pf_if = _T_111 ? issue_slots_9_out_uop_xcpt_pf_if : issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_typ = _T_111 ? issue_slots_9_out_uop_fp_typ : issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_rm = _T_111 ? issue_slots_9_out_uop_fp_rm : issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_val = _T_111 ? issue_slots_9_out_uop_fp_val : issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_op = _T_111 ? issue_slots_9_out_uop_fcn_op : issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_dw = _T_111 ? issue_slots_9_out_uop_fcn_dw : issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_frs3_en = _T_111 ? issue_slots_9_out_uop_frs3_en : issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2_rtype = _T_111 ? issue_slots_9_out_uop_lrs2_rtype : issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1_rtype = _T_111 ? issue_slots_9_out_uop_lrs1_rtype : issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dst_rtype = _T_111 ? issue_slots_9_out_uop_dst_rtype : issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs3 = _T_111 ? issue_slots_9_out_uop_lrs3 : issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2 = _T_111 ? issue_slots_9_out_uop_lrs2 : issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1 = _T_111 ? issue_slots_9_out_uop_lrs1 : issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst = _T_111 ? issue_slots_9_out_uop_ldst : issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst_is_rs1 = _T_111 ? issue_slots_9_out_uop_ldst_is_rs1 : issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_csr_cmd = _T_111 ? issue_slots_9_out_uop_csr_cmd : issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_flush_on_commit = _T_111 ? issue_slots_9_out_uop_flush_on_commit : issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_unique = _T_111 ? issue_slots_9_out_uop_is_unique : issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_stq = _T_111 ? issue_slots_9_out_uop_uses_stq : issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_ldq = _T_111 ? issue_slots_9_out_uop_uses_ldq : issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_signed = _T_111 ? issue_slots_9_out_uop_mem_signed : issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_size = _T_111 ? issue_slots_9_out_uop_mem_size : issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_cmd = _T_111 ? issue_slots_9_out_uop_mem_cmd : issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exc_cause = _T_111 ? issue_slots_9_out_uop_exc_cause : issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exception = _T_111 ? issue_slots_9_out_uop_exception : issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stale_pdst = _T_111 ? issue_slots_9_out_uop_stale_pdst : issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred_busy = _T_111 ? issue_slots_9_out_uop_ppred_busy : issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3_busy = _T_111 ? issue_slots_9_out_uop_prs3_busy : issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2_busy = _T_111 ? issue_slots_9_out_uop_prs2_busy : issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1_busy = _T_111 ? issue_slots_9_out_uop_prs1_busy : issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred = _T_111 ? issue_slots_9_out_uop_ppred : issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3 = _T_111 ? issue_slots_9_out_uop_prs3 : issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2 = _T_111 ? issue_slots_9_out_uop_prs2 : issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1 = _T_111 ? issue_slots_9_out_uop_prs1 : issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pdst = _T_111 ? issue_slots_9_out_uop_pdst : issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rxq_idx = _T_111 ? issue_slots_9_out_uop_rxq_idx : issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stq_idx = _T_111 ? issue_slots_9_out_uop_stq_idx : issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldq_idx = _T_111 ? issue_slots_9_out_uop_ldq_idx : issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rob_idx = _T_111 ? issue_slots_9_out_uop_rob_idx : issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_vec = _T_111 ? issue_slots_9_out_uop_fp_ctrl_vec : issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wflags = _T_111 ? issue_slots_9_out_uop_fp_ctrl_wflags : issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_sqrt = _T_111 ? issue_slots_9_out_uop_fp_ctrl_sqrt : issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_div = _T_111 ? issue_slots_9_out_uop_fp_ctrl_div : issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fma = _T_111 ? issue_slots_9_out_uop_fp_ctrl_fma : issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fastpipe = _T_111 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_toint = _T_111 ? issue_slots_9_out_uop_fp_ctrl_toint : issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fromint = _T_111 ? issue_slots_9_out_uop_fp_ctrl_fromint : issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut = _T_111 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn = _T_111 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap23 = _T_111 ? issue_slots_9_out_uop_fp_ctrl_swap23 : issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap12 = _T_111 ? issue_slots_9_out_uop_fp_ctrl_swap12 : issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren3 = _T_111 ? issue_slots_9_out_uop_fp_ctrl_ren3 : issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren2 = _T_111 ? issue_slots_9_out_uop_fp_ctrl_ren2 : issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren1 = _T_111 ? issue_slots_9_out_uop_fp_ctrl_ren1 : issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wen = _T_111 ? issue_slots_9_out_uop_fp_ctrl_wen : issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ldst = _T_111 ? issue_slots_9_out_uop_fp_ctrl_ldst : issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op2_sel = _T_111 ? issue_slots_9_out_uop_op2_sel : issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op1_sel = _T_111 ? issue_slots_9_out_uop_op1_sel : issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_packed = _T_111 ? issue_slots_9_out_uop_imm_packed : issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pimm = _T_111 ? issue_slots_9_out_uop_pimm : issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_sel = _T_111 ? issue_slots_9_out_uop_imm_sel : issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_rename = _T_111 ? issue_slots_9_out_uop_imm_rename : issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_taken = _T_111 ? issue_slots_9_out_uop_taken : issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pc_lob = _T_111 ? issue_slots_9_out_uop_pc_lob : issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_edge_inst = _T_111 ? issue_slots_9_out_uop_edge_inst : issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ftq_idx = _T_111 ? issue_slots_9_out_uop_ftq_idx : issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_mov = _T_111 ? issue_slots_9_out_uop_is_mov : issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rocc = _T_111 ? issue_slots_9_out_uop_is_rocc : issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sys_pc2epc = _T_111 ? issue_slots_9_out_uop_is_sys_pc2epc : issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_eret = _T_111 ? issue_slots_9_out_uop_is_eret : issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_amo = _T_111 ? issue_slots_9_out_uop_is_amo : issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfence = _T_111 ? issue_slots_9_out_uop_is_sfence : issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fencei = _T_111 ? issue_slots_9_out_uop_is_fencei : issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fence = _T_111 ? issue_slots_9_out_uop_is_fence : issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfb = _T_111 ? issue_slots_9_out_uop_is_sfb : issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_type = _T_111 ? issue_slots_9_out_uop_br_type : issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_tag = _T_111 ? issue_slots_9_out_uop_br_tag : issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_mask = _T_111 ? issue_slots_9_out_uop_br_mask : issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dis_col_sel = _T_111 ? issue_slots_9_out_uop_dis_col_sel : issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p3_bypass_hint = _T_111 ? issue_slots_9_out_uop_iw_p3_bypass_hint : issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p2_bypass_hint = _T_111 ? issue_slots_9_out_uop_iw_p2_bypass_hint : issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p1_bypass_hint = _T_111 ? issue_slots_9_out_uop_iw_p1_bypass_hint : issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_issued = _T_111 ? issue_slots_9_out_uop_iw_issued : issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_0 = _T_111 ? issue_slots_9_out_uop_fu_code_0 : issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_1 = _T_111 ? issue_slots_9_out_uop_fu_code_1 : issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_2 = _T_111 ? issue_slots_9_out_uop_fu_code_2 : issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_3 = _T_111 ? issue_slots_9_out_uop_fu_code_3 : issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_4 = _T_111 ? issue_slots_9_out_uop_fu_code_4 : issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_5 = _T_111 ? issue_slots_9_out_uop_fu_code_5 : issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_6 = _T_111 ? issue_slots_9_out_uop_fu_code_6 : issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_7 = _T_111 ? issue_slots_9_out_uop_fu_code_7 : issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_8 = _T_111 ? issue_slots_9_out_uop_fu_code_8 : issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_9 = _T_111 ? issue_slots_9_out_uop_fu_code_9 : issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_0 = _T_111 ? issue_slots_9_out_uop_iq_type_0 : issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_1 = _T_111 ? issue_slots_9_out_uop_iq_type_1 : issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_2 = _T_111 ? issue_slots_9_out_uop_iq_type_2 : issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_3 = _T_111 ? issue_slots_9_out_uop_iq_type_3 : issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_pc = _T_111 ? issue_slots_9_out_uop_debug_pc : issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rvc = _T_111 ? issue_slots_9_out_uop_is_rvc : issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_inst = _T_111 ? issue_slots_9_out_uop_debug_inst : issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_inst = _T_111 ? issue_slots_9_out_uop_inst : issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_7_clear_T = \|shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_7_clear = _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_113 = shamts_oh_10 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_8_in_uop_valid = _T_113 ? issue_slots_10_will_be_valid : shamts_oh_9 == 2'h1 & issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_8_in_uop_bits_debug_tsrc = _T_113 ? issue_slots_10_out_uop_debug_tsrc : issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_fsrc = _T_113 ? issue_slots_10_out_uop_debug_fsrc : issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_xcpt_if = _T_113 ? issue_slots_10_out_uop_bp_xcpt_if : issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_debug_if = _T_113 ? issue_slots_10_out_uop_bp_debug_if : issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ma_if = _T_113 ? issue_slots_10_out_uop_xcpt_ma_if : issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ae_if = _T_113 ? issue_slots_10_out_uop_xcpt_ae_if : issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_pf_if = _T_113 ? issue_slots_10_out_uop_xcpt_pf_if : issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_typ = _T_113 ? issue_slots_10_out_uop_fp_typ : issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_rm = _T_113 ? issue_slots_10_out_uop_fp_rm : issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_val = _T_113 ? issue_slots_10_out_uop_fp_val : issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_op = _T_113 ? issue_slots_10_out_uop_fcn_op : issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_dw = _T_113 ? issue_slots_10_out_uop_fcn_dw : issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_frs3_en = _T_113 ? issue_slots_10_out_uop_frs3_en : issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2_rtype = _T_113 ? issue_slots_10_out_uop_lrs2_rtype : issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1_rtype = _T_113 ? issue_slots_10_out_uop_lrs1_rtype : issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dst_rtype = _T_113 ? issue_slots_10_out_uop_dst_rtype : issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs3 = _T_113 ? issue_slots_10_out_uop_lrs3 : issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2 = _T_113 ? issue_slots_10_out_uop_lrs2 : issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1 = _T_113 ? issue_slots_10_out_uop_lrs1 : issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst = _T_113 ? issue_slots_10_out_uop_ldst : issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst_is_rs1 = _T_113 ? issue_slots_10_out_uop_ldst_is_rs1 : issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_csr_cmd = _T_113 ? issue_slots_10_out_uop_csr_cmd : issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_flush_on_commit = _T_113 ? issue_slots_10_out_uop_flush_on_commit : issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_unique = _T_113 ? issue_slots_10_out_uop_is_unique : issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_stq = _T_113 ? issue_slots_10_out_uop_uses_stq : issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_ldq = _T_113 ? issue_slots_10_out_uop_uses_ldq : issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_signed = _T_113 ? issue_slots_10_out_uop_mem_signed : issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_size = _T_113 ? issue_slots_10_out_uop_mem_size : issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_cmd = _T_113 ? issue_slots_10_out_uop_mem_cmd : issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exc_cause = _T_113 ? issue_slots_10_out_uop_exc_cause : issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exception = _T_113 ? issue_slots_10_out_uop_exception : issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stale_pdst = _T_113 ? issue_slots_10_out_uop_stale_pdst : issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred_busy = _T_113 ? issue_slots_10_out_uop_ppred_busy : issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3_busy = _T_113 ? issue_slots_10_out_uop_prs3_busy : issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2_busy = _T_113 ? issue_slots_10_out_uop_prs2_busy : issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1_busy = _T_113 ? issue_slots_10_out_uop_prs1_busy : issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred = _T_113 ? issue_slots_10_out_uop_ppred : issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3 = _T_113 ? issue_slots_10_out_uop_prs3 : issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2 = _T_113 ? issue_slots_10_out_uop_prs2 : issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1 = _T_113 ? issue_slots_10_out_uop_prs1 : issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pdst = _T_113 ? issue_slots_10_out_uop_pdst : issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rxq_idx = _T_113 ? issue_slots_10_out_uop_rxq_idx : issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stq_idx = _T_113 ? issue_slots_10_out_uop_stq_idx : issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldq_idx = _T_113 ? issue_slots_10_out_uop_ldq_idx : issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rob_idx = _T_113 ? issue_slots_10_out_uop_rob_idx : issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_vec = _T_113 ? issue_slots_10_out_uop_fp_ctrl_vec : issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wflags = _T_113 ? issue_slots_10_out_uop_fp_ctrl_wflags : issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_sqrt = _T_113 ? issue_slots_10_out_uop_fp_ctrl_sqrt : issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_div = _T_113 ? issue_slots_10_out_uop_fp_ctrl_div : issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fma = _T_113 ? issue_slots_10_out_uop_fp_ctrl_fma : issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fastpipe = _T_113 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_toint = _T_113 ? issue_slots_10_out_uop_fp_ctrl_toint : issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fromint = _T_113 ? issue_slots_10_out_uop_fp_ctrl_fromint : issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut = _T_113 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn = _T_113 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap23 = _T_113 ? issue_slots_10_out_uop_fp_ctrl_swap23 : issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap12 = _T_113 ? issue_slots_10_out_uop_fp_ctrl_swap12 : issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren3 = _T_113 ? issue_slots_10_out_uop_fp_ctrl_ren3 : issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren2 = _T_113 ? issue_slots_10_out_uop_fp_ctrl_ren2 : issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren1 = _T_113 ? issue_slots_10_out_uop_fp_ctrl_ren1 : issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wen = _T_113 ? issue_slots_10_out_uop_fp_ctrl_wen : issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ldst = _T_113 ? issue_slots_10_out_uop_fp_ctrl_ldst : issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op2_sel = _T_113 ? issue_slots_10_out_uop_op2_sel : issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op1_sel = _T_113 ? issue_slots_10_out_uop_op1_sel : issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_packed = _T_113 ? issue_slots_10_out_uop_imm_packed : issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pimm = _T_113 ? issue_slots_10_out_uop_pimm : issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_sel = _T_113 ? issue_slots_10_out_uop_imm_sel : issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_rename = _T_113 ? issue_slots_10_out_uop_imm_rename : issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_taken = _T_113 ? issue_slots_10_out_uop_taken : issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pc_lob = _T_113 ? issue_slots_10_out_uop_pc_lob : issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_edge_inst = _T_113 ? issue_slots_10_out_uop_edge_inst : issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ftq_idx = _T_113 ? issue_slots_10_out_uop_ftq_idx : issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_mov = _T_113 ? issue_slots_10_out_uop_is_mov : issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rocc = _T_113 ? issue_slots_10_out_uop_is_rocc : issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sys_pc2epc = _T_113 ? issue_slots_10_out_uop_is_sys_pc2epc : issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_eret = _T_113 ? issue_slots_10_out_uop_is_eret : issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_amo = _T_113 ? issue_slots_10_out_uop_is_amo : issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfence = _T_113 ? issue_slots_10_out_uop_is_sfence : issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fencei = _T_113 ? issue_slots_10_out_uop_is_fencei : issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fence = _T_113 ? issue_slots_10_out_uop_is_fence : issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfb = _T_113 ? issue_slots_10_out_uop_is_sfb : issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_type = _T_113 ? issue_slots_10_out_uop_br_type : issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_tag = _T_113 ? issue_slots_10_out_uop_br_tag : issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_mask = _T_113 ? issue_slots_10_out_uop_br_mask : issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dis_col_sel = _T_113 ? issue_slots_10_out_uop_dis_col_sel : issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p3_bypass_hint = _T_113 ? issue_slots_10_out_uop_iw_p3_bypass_hint : issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p2_bypass_hint = _T_113 ? issue_slots_10_out_uop_iw_p2_bypass_hint : issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p1_bypass_hint = _T_113 ? issue_slots_10_out_uop_iw_p1_bypass_hint : issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_issued = _T_113 ? issue_slots_10_out_uop_iw_issued : issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_0 = _T_113 ? issue_slots_10_out_uop_fu_code_0 : issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_1 = _T_113 ? issue_slots_10_out_uop_fu_code_1 : issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_2 = _T_113 ? issue_slots_10_out_uop_fu_code_2 : issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_3 = _T_113 ? issue_slots_10_out_uop_fu_code_3 : issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_4 = _T_113 ? issue_slots_10_out_uop_fu_code_4 : issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_5 = _T_113 ? issue_slots_10_out_uop_fu_code_5 : issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_6 = _T_113 ? issue_slots_10_out_uop_fu_code_6 : issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_7 = _T_113 ? issue_slots_10_out_uop_fu_code_7 : issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_8 = _T_113 ? issue_slots_10_out_uop_fu_code_8 : issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_9 = _T_113 ? issue_slots_10_out_uop_fu_code_9 : issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_0 = _T_113 ? issue_slots_10_out_uop_iq_type_0 : issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_1 = _T_113 ? issue_slots_10_out_uop_iq_type_1 : issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_2 = _T_113 ? issue_slots_10_out_uop_iq_type_2 : issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_3 = _T_113 ? issue_slots_10_out_uop_iq_type_3 : issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_pc = _T_113 ? issue_slots_10_out_uop_debug_pc : issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rvc = _T_113 ? issue_slots_10_out_uop_is_rvc : issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_inst = _T_113 ? issue_slots_10_out_uop_debug_inst : issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_inst = _T_113 ? issue_slots_10_out_uop_inst : issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_8_clear_T = \|shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_8_clear = _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_115 = shamts_oh_11 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_9_in_uop_valid = _T_115 ? issue_slots_11_will_be_valid : shamts_oh_10 == 2'h1 & issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_9_in_uop_bits_debug_tsrc = _T_115 ? issue_slots_11_out_uop_debug_tsrc : issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_fsrc = _T_115 ? issue_slots_11_out_uop_debug_fsrc : issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_xcpt_if = _T_115 ? issue_slots_11_out_uop_bp_xcpt_if : issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_debug_if = _T_115 ? issue_slots_11_out_uop_bp_debug_if : issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ma_if = _T_115 ? issue_slots_11_out_uop_xcpt_ma_if : issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ae_if = _T_115 ? issue_slots_11_out_uop_xcpt_ae_if : issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_pf_if = _T_115 ? issue_slots_11_out_uop_xcpt_pf_if : issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_typ = _T_115 ? issue_slots_11_out_uop_fp_typ : issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_rm = _T_115 ? issue_slots_11_out_uop_fp_rm : issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_val = _T_115 ? issue_slots_11_out_uop_fp_val : issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_op = _T_115 ? issue_slots_11_out_uop_fcn_op : issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_dw = _T_115 ? issue_slots_11_out_uop_fcn_dw : issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_frs3_en = _T_115 ? issue_slots_11_out_uop_frs3_en : issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2_rtype = _T_115 ? issue_slots_11_out_uop_lrs2_rtype : issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1_rtype = _T_115 ? issue_slots_11_out_uop_lrs1_rtype : issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dst_rtype = _T_115 ? issue_slots_11_out_uop_dst_rtype : issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs3 = _T_115 ? issue_slots_11_out_uop_lrs3 : issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2 = _T_115 ? issue_slots_11_out_uop_lrs2 : issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1 = _T_115 ? issue_slots_11_out_uop_lrs1 : issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst = _T_115 ? issue_slots_11_out_uop_ldst : issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst_is_rs1 = _T_115 ? issue_slots_11_out_uop_ldst_is_rs1 : issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_csr_cmd = _T_115 ? issue_slots_11_out_uop_csr_cmd : issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_flush_on_commit = _T_115 ? issue_slots_11_out_uop_flush_on_commit : issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_unique = _T_115 ? issue_slots_11_out_uop_is_unique : issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_stq = _T_115 ? issue_slots_11_out_uop_uses_stq : issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_ldq = _T_115 ? issue_slots_11_out_uop_uses_ldq : issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_signed = _T_115 ? issue_slots_11_out_uop_mem_signed : issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_size = _T_115 ? issue_slots_11_out_uop_mem_size : issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_cmd = _T_115 ? issue_slots_11_out_uop_mem_cmd : issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exc_cause = _T_115 ? issue_slots_11_out_uop_exc_cause : issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exception = _T_115 ? issue_slots_11_out_uop_exception : issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stale_pdst = _T_115 ? issue_slots_11_out_uop_stale_pdst : issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred_busy = _T_115 ? issue_slots_11_out_uop_ppred_busy : issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3_busy = _T_115 ? issue_slots_11_out_uop_prs3_busy : issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2_busy = _T_115 ? issue_slots_11_out_uop_prs2_busy : issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1_busy = _T_115 ? issue_slots_11_out_uop_prs1_busy : issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred = _T_115 ? issue_slots_11_out_uop_ppred : issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3 = _T_115 ? issue_slots_11_out_uop_prs3 : issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2 = _T_115 ? issue_slots_11_out_uop_prs2 : issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1 = _T_115 ? issue_slots_11_out_uop_prs1 : issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pdst = _T_115 ? issue_slots_11_out_uop_pdst : issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rxq_idx = _T_115 ? issue_slots_11_out_uop_rxq_idx : issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stq_idx = _T_115 ? issue_slots_11_out_uop_stq_idx : issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldq_idx = _T_115 ? issue_slots_11_out_uop_ldq_idx : issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rob_idx = _T_115 ? issue_slots_11_out_uop_rob_idx : issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_vec = _T_115 ? issue_slots_11_out_uop_fp_ctrl_vec : issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wflags = _T_115 ? issue_slots_11_out_uop_fp_ctrl_wflags : issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_sqrt = _T_115 ? issue_slots_11_out_uop_fp_ctrl_sqrt : issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_div = _T_115 ? issue_slots_11_out_uop_fp_ctrl_div : issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fma = _T_115 ? issue_slots_11_out_uop_fp_ctrl_fma : issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fastpipe = _T_115 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_toint = _T_115 ? issue_slots_11_out_uop_fp_ctrl_toint : issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fromint = _T_115 ? issue_slots_11_out_uop_fp_ctrl_fromint : issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut = _T_115 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn = _T_115 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap23 = _T_115 ? issue_slots_11_out_uop_fp_ctrl_swap23 : issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap12 = _T_115 ? issue_slots_11_out_uop_fp_ctrl_swap12 : issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren3 = _T_115 ? issue_slots_11_out_uop_fp_ctrl_ren3 : issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren2 = _T_115 ? issue_slots_11_out_uop_fp_ctrl_ren2 : issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren1 = _T_115 ? issue_slots_11_out_uop_fp_ctrl_ren1 : issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wen = _T_115 ? issue_slots_11_out_uop_fp_ctrl_wen : issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ldst = _T_115 ? issue_slots_11_out_uop_fp_ctrl_ldst : issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op2_sel = _T_115 ? issue_slots_11_out_uop_op2_sel : issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op1_sel = _T_115 ? issue_slots_11_out_uop_op1_sel : issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_packed = _T_115 ? issue_slots_11_out_uop_imm_packed : issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pimm = _T_115 ? issue_slots_11_out_uop_pimm : issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_sel = _T_115 ? issue_slots_11_out_uop_imm_sel : issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_rename = _T_115 ? issue_slots_11_out_uop_imm_rename : issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_taken = _T_115 ? issue_slots_11_out_uop_taken : issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pc_lob = _T_115 ? issue_slots_11_out_uop_pc_lob : issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_edge_inst = _T_115 ? issue_slots_11_out_uop_edge_inst : issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ftq_idx = _T_115 ? issue_slots_11_out_uop_ftq_idx : issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_mov = _T_115 ? issue_slots_11_out_uop_is_mov : issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rocc = _T_115 ? issue_slots_11_out_uop_is_rocc : issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sys_pc2epc = _T_115 ? issue_slots_11_out_uop_is_sys_pc2epc : issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_eret = _T_115 ? issue_slots_11_out_uop_is_eret : issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_amo = _T_115 ? issue_slots_11_out_uop_is_amo : issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfence = _T_115 ? issue_slots_11_out_uop_is_sfence : issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fencei = _T_115 ? issue_slots_11_out_uop_is_fencei : issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fence = _T_115 ? issue_slots_11_out_uop_is_fence : issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfb = _T_115 ? issue_slots_11_out_uop_is_sfb : issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_type = _T_115 ? issue_slots_11_out_uop_br_type : issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_tag = _T_115 ? issue_slots_11_out_uop_br_tag : issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_mask = _T_115 ? issue_slots_11_out_uop_br_mask : issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dis_col_sel = _T_115 ? issue_slots_11_out_uop_dis_col_sel : issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p3_bypass_hint = _T_115 ? issue_slots_11_out_uop_iw_p3_bypass_hint : issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p2_bypass_hint = _T_115 ? issue_slots_11_out_uop_iw_p2_bypass_hint : issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p1_bypass_hint = _T_115 ? issue_slots_11_out_uop_iw_p1_bypass_hint : issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_issued = _T_115 ? issue_slots_11_out_uop_iw_issued : issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_0 = _T_115 ? issue_slots_11_out_uop_fu_code_0 : issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_1 = _T_115 ? issue_slots_11_out_uop_fu_code_1 : issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_2 = _T_115 ? issue_slots_11_out_uop_fu_code_2 : issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_3 = _T_115 ? issue_slots_11_out_uop_fu_code_3 : issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_4 = _T_115 ? issue_slots_11_out_uop_fu_code_4 : issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_5 = _T_115 ? issue_slots_11_out_uop_fu_code_5 : issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_6 = _T_115 ? issue_slots_11_out_uop_fu_code_6 : issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_7 = _T_115 ? issue_slots_11_out_uop_fu_code_7 : issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_8 = _T_115 ? issue_slots_11_out_uop_fu_code_8 : issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_9 = _T_115 ? issue_slots_11_out_uop_fu_code_9 : issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_0 = _T_115 ? issue_slots_11_out_uop_iq_type_0 : issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_1 = _T_115 ? issue_slots_11_out_uop_iq_type_1 : issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_2 = _T_115 ? issue_slots_11_out_uop_iq_type_2 : issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_3 = _T_115 ? issue_slots_11_out_uop_iq_type_3 : issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_pc = _T_115 ? issue_slots_11_out_uop_debug_pc : issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rvc = _T_115 ? issue_slots_11_out_uop_is_rvc : issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_inst = _T_115 ? issue_slots_11_out_uop_debug_inst : issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_inst = _T_115 ? issue_slots_11_out_uop_inst : issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_9_clear_T = \|shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_9_clear = _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_117 = shamts_oh_12 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_10_in_uop_valid = _T_117 ? will_be_valid_12 : shamts_oh_11 == 2'h1 & issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_10_in_uop_bits_debug_tsrc = _T_117 ? io_dis_uops_0_bits_debug_tsrc_0 : issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_fsrc = _T_117 ? io_dis_uops_0_bits_debug_fsrc_0 : issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_xcpt_if = _T_117 ? io_dis_uops_0_bits_bp_xcpt_if_0 : issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_debug_if = _T_117 ? io_dis_uops_0_bits_bp_debug_if_0 : issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ma_if = _T_117 ? io_dis_uops_0_bits_xcpt_ma_if_0 : issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ae_if = _T_117 ? io_dis_uops_0_bits_xcpt_ae_if_0 : issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_pf_if = _T_117 ? io_dis_uops_0_bits_xcpt_pf_if_0 : issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_typ = _T_117 ? io_dis_uops_0_bits_fp_typ_0 : issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_rm = _T_117 ? io_dis_uops_0_bits_fp_rm_0 : issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_val = _T_117 ? io_dis_uops_0_bits_fp_val_0 : issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_op = _T_117 ? io_dis_uops_0_bits_fcn_op_0 : issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_dw = _T_117 ? io_dis_uops_0_bits_fcn_dw_0 : issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_frs3_en = _T_117 ? io_dis_uops_0_bits_frs3_en_0 : issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2_rtype = _T_117 ? io_dis_uops_0_bits_lrs2_rtype_0 : issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1_rtype = _T_117 ? _WIRE_lrs1_rtype : issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:35:17, :103:43, :104:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dst_rtype = _T_117 ? io_dis_uops_0_bits_dst_rtype_0 : issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs3 = _T_117 ? io_dis_uops_0_bits_lrs3_0 : issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2 = _T_117 ? io_dis_uops_0_bits_lrs2_0 : issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1 = _T_117 ? io_dis_uops_0_bits_lrs1_0 : issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst = _T_117 ? io_dis_uops_0_bits_ldst_0 : issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst_is_rs1 = _T_117 ? io_dis_uops_0_bits_ldst_is_rs1_0 : issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_csr_cmd = _T_117 ? io_dis_uops_0_bits_csr_cmd_0 : issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_flush_on_commit = _T_117 ? io_dis_uops_0_bits_flush_on_commit_0 : issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_unique = _T_117 ? io_dis_uops_0_bits_is_unique_0 : issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_stq = _T_117 ? io_dis_uops_0_bits_uses_stq_0 : issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_ldq = _T_117 ? io_dis_uops_0_bits_uses_ldq_0 : issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_signed = _T_117 ? io_dis_uops_0_bits_mem_signed_0 : issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_size = _T_117 ? io_dis_uops_0_bits_mem_size_0 : issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_cmd = _T_117 ? io_dis_uops_0_bits_mem_cmd_0 : issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exc_cause = _T_117 ? io_dis_uops_0_bits_exc_cause_0 : issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exception = _T_117 ? io_dis_uops_0_bits_exception_0 : issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stale_pdst = _T_117 ? io_dis_uops_0_bits_stale_pdst_0 : issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred_busy = ~_T_117 & issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3_busy = _T_117 ? _WIRE_prs3_busy : issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:35:17, :76:38, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2_busy = _T_117 ? _WIRE_prs2_busy : issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:35:17, :65:38, :66:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1_busy = _T_117 ? _WIRE_prs1_busy : issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:35:17, :57:38, :58:29, :62:116, :103:43, :105:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred = _T_117 ? io_dis_uops_0_bits_ppred_0 : issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3 = _T_117 ? io_dis_uops_0_bits_prs3_0 : issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2 = _T_117 ? io_dis_uops_0_bits_prs2_0 : issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1 = _T_117 ? io_dis_uops_0_bits_prs1_0 : issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pdst = _T_117 ? io_dis_uops_0_bits_pdst_0 : issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rxq_idx = _T_117 ? io_dis_uops_0_bits_rxq_idx_0 : issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stq_idx = _T_117 ? io_dis_uops_0_bits_stq_idx_0 : issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldq_idx = _T_117 ? io_dis_uops_0_bits_ldq_idx_0 : issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rob_idx = _T_117 ? io_dis_uops_0_bits_rob_idx_0 : issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_vec = _T_117 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wflags = _T_117 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_sqrt = _T_117 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_div = _T_117 ? io_dis_uops_0_bits_fp_ctrl_div_0 : issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fma = _T_117 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fastpipe = _T_117 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_toint = _T_117 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fromint = _T_117 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut = _T_117 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn = _T_117 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap23 = _T_117 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap12 = _T_117 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren3 = _T_117 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren2 = _T_117 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren1 = _T_117 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wen = _T_117 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ldst = _T_117 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op2_sel = _T_117 ? io_dis_uops_0_bits_op2_sel_0 : issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op1_sel = _T_117 ? io_dis_uops_0_bits_op1_sel_0 : issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_packed = _T_117 ? io_dis_uops_0_bits_imm_packed_0 : issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pimm = _T_117 ? io_dis_uops_0_bits_pimm_0 : issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_sel = _T_117 ? io_dis_uops_0_bits_imm_sel_0 : issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_rename = _T_117 ? io_dis_uops_0_bits_imm_rename_0 : issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_taken = _T_117 ? io_dis_uops_0_bits_taken_0 : issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pc_lob = _T_117 ? io_dis_uops_0_bits_pc_lob_0 : issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_edge_inst = _T_117 ? io_dis_uops_0_bits_edge_inst_0 : issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ftq_idx = _T_117 ? io_dis_uops_0_bits_ftq_idx_0 : issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_mov = _T_117 ? io_dis_uops_0_bits_is_mov_0 : issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rocc = _T_117 ? io_dis_uops_0_bits_is_rocc_0 : issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sys_pc2epc = _T_117 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_eret = _T_117 ? io_dis_uops_0_bits_is_eret_0 : issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_amo = _T_117 ? io_dis_uops_0_bits_is_amo_0 : issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfence = _T_117 ? io_dis_uops_0_bits_is_sfence_0 : issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fencei = _T_117 ? io_dis_uops_0_bits_is_fencei_0 : issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fence = _T_117 ? io_dis_uops_0_bits_is_fence_0 : issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfb = _T_117 ? io_dis_uops_0_bits_is_sfb_0 : issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_type = _T_117 ? io_dis_uops_0_bits_br_type_0 : issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_tag = _T_117 ? io_dis_uops_0_bits_br_tag_0 : issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_mask = _T_117 ? io_dis_uops_0_bits_br_mask_0 : issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dis_col_sel = _T_117 ? io_dis_uops_0_bits_dis_col_sel_0 : issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p3_bypass_hint = _T_117 ? _WIRE_iw_p3_bypass_hint : issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p2_bypass_hint = _T_117 ? _WIRE_iw_p2_bypass_hint : issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p1_bypass_hint = _T_117 ? _WIRE_iw_p1_bypass_hint : issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p2_speculative_child = ~_T_117 \| _T_12 ? 2'h0 : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :65:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p1_speculative_child = ~_T_117 \| _T ? 2'h0 : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :57:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_issued = ~_T_117 & issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_0 = _T_117 ? io_dis_uops_0_bits_fu_code_0_0 : issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_1 = _T_117 ? io_dis_uops_0_bits_fu_code_1_0 : issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_2 = _T_117 ? io_dis_uops_0_bits_fu_code_2_0 : issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_3 = _T_117 ? io_dis_uops_0_bits_fu_code_3_0 : issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_4 = _T_117 ? io_dis_uops_0_bits_fu_code_4_0 : issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_5 = _T_117 ? io_dis_uops_0_bits_fu_code_5_0 : issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_6 = _T_117 ? io_dis_uops_0_bits_fu_code_6_0 : issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_7 = _T_117 ? io_dis_uops_0_bits_fu_code_7_0 : issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_8 = _T_117 ? io_dis_uops_0_bits_fu_code_8_0 : issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_9 = _T_117 ? io_dis_uops_0_bits_fu_code_9_0 : issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_0 = _T_117 ? io_dis_uops_0_bits_iq_type_0_0 : issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_1 = _T_117 ? io_dis_uops_0_bits_iq_type_1_0 : issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_2 = _T_117 ? io_dis_uops_0_bits_iq_type_2_0 : issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_3 = _T_117 ? io_dis_uops_0_bits_iq_type_3_0 : issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_pc = _T_117 ? io_dis_uops_0_bits_debug_pc_0 : issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rvc = _T_117 ? io_dis_uops_0_bits_is_rvc_0 : issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_inst = _T_117 ? io_dis_uops_0_bits_debug_inst_0 : issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_inst = _T_117 ? io_dis_uops_0_bits_inst_0 : issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_10_clear_T = \|shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_10_clear = _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_119 = shamts_oh_13 == 2'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_11_in_uop_valid = _T_119 ? will_be_valid_13 : shamts_oh_12 == 2'h1 & will_be_valid_12; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_11_in_uop_bits_debug_tsrc = _T_119 ? io_dis_uops_1_bits_debug_tsrc_0 : io_dis_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_fsrc = _T_119 ? io_dis_uops_1_bits_debug_fsrc_0 : io_dis_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_xcpt_if = _T_119 ? io_dis_uops_1_bits_bp_xcpt_if_0 : io_dis_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_debug_if = _T_119 ? io_dis_uops_1_bits_bp_debug_if_0 : io_dis_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ma_if = _T_119 ? io_dis_uops_1_bits_xcpt_ma_if_0 : io_dis_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ae_if = _T_119 ? io_dis_uops_1_bits_xcpt_ae_if_0 : io_dis_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_pf_if = _T_119 ? io_dis_uops_1_bits_xcpt_pf_if_0 : io_dis_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_typ = _T_119 ? io_dis_uops_1_bits_fp_typ_0 : io_dis_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_rm = _T_119 ? io_dis_uops_1_bits_fp_rm_0 : io_dis_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_val = _T_119 ? io_dis_uops_1_bits_fp_val_0 : io_dis_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_op = _T_119 ? io_dis_uops_1_bits_fcn_op_0 : io_dis_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_dw = _T_119 ? io_dis_uops_1_bits_fcn_dw_0 : io_dis_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_frs3_en = _T_119 ? io_dis_uops_1_bits_frs3_en_0 : io_dis_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2_rtype = _T_119 ? io_dis_uops_1_bits_lrs2_rtype_0 : io_dis_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1_rtype = _T_119 ? (io_dis_uops_1_bits_uses_stq_0 ? 2'h2 : io_dis_uops_1_bits_lrs1_rtype_0) : _WIRE_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7, :35:17, :103:43, :104:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dst_rtype = _T_119 ? io_dis_uops_1_bits_dst_rtype_0 : io_dis_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs3 = _T_119 ? io_dis_uops_1_bits_lrs3_0 : io_dis_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2 = _T_119 ? io_dis_uops_1_bits_lrs2_0 : io_dis_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1 = _T_119 ? io_dis_uops_1_bits_lrs1_0 : io_dis_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst = _T_119 ? io_dis_uops_1_bits_ldst_0 : io_dis_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst_is_rs1 = _T_119 ? io_dis_uops_1_bits_ldst_is_rs1_0 : io_dis_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_csr_cmd = _T_119 ? io_dis_uops_1_bits_csr_cmd_0 : io_dis_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_flush_on_commit = _T_119 ? io_dis_uops_1_bits_flush_on_commit_0 : io_dis_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_unique = _T_119 ? io_dis_uops_1_bits_is_unique_0 : io_dis_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_stq = _T_119 ? io_dis_uops_1_bits_uses_stq_0 : io_dis_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_ldq = _T_119 ? io_dis_uops_1_bits_uses_ldq_0 : io_dis_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_signed = _T_119 ? io_dis_uops_1_bits_mem_signed_0 : io_dis_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_size = _T_119 ? io_dis_uops_1_bits_mem_size_0 : io_dis_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_cmd = _T_119 ? io_dis_uops_1_bits_mem_cmd_0 : io_dis_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exc_cause = _T_119 ? io_dis_uops_1_bits_exc_cause_0 : io_dis_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exception = _T_119 ? io_dis_uops_1_bits_exception_0 : io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stale_pdst = _T_119 ? io_dis_uops_1_bits_stale_pdst_0 : io_dis_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3_busy = _T_119 ? ~_T_59 & io_dis_uops_1_bits_prs3_busy_0 : _WIRE_prs3_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2_busy = _T_119 ? ~_T_47 & io_dis_uops_1_bits_prs2_busy_0 : _WIRE_prs2_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :66:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1_busy = _T_119 ? ~io_dis_uops_1_bits_uses_stq_0 & ~_T_35 & io_dis_uops_1_bits_prs1_busy_0 : _WIRE_prs1_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :58:29, :62:116, :103:43, :105:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ppred = _T_119 ? io_dis_uops_1_bits_ppred_0 : io_dis_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3 = _T_119 ? io_dis_uops_1_bits_prs3_0 : io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2 = _T_119 ? io_dis_uops_1_bits_prs2_0 : io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1 = _T_119 ? io_dis_uops_1_bits_prs1_0 : io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pdst = _T_119 ? io_dis_uops_1_bits_pdst_0 : io_dis_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rxq_idx = _T_119 ? io_dis_uops_1_bits_rxq_idx_0 : io_dis_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stq_idx = _T_119 ? io_dis_uops_1_bits_stq_idx_0 : io_dis_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldq_idx = _T_119 ? io_dis_uops_1_bits_ldq_idx_0 : io_dis_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rob_idx = _T_119 ? io_dis_uops_1_bits_rob_idx_0 : io_dis_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_vec = _T_119 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : io_dis_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wflags = _T_119 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : io_dis_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_sqrt = _T_119 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : io_dis_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_div = _T_119 ? io_dis_uops_1_bits_fp_ctrl_div_0 : io_dis_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fma = _T_119 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : io_dis_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fastpipe = _T_119 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : io_dis_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_toint = _T_119 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : io_dis_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fromint = _T_119 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : io_dis_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut = _T_119 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : io_dis_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn = _T_119 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : io_dis_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap23 = _T_119 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : io_dis_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap12 = _T_119 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : io_dis_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren3 = _T_119 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : io_dis_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren2 = _T_119 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : io_dis_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren1 = _T_119 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : io_dis_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wen = _T_119 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : io_dis_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ldst = _T_119 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : io_dis_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op2_sel = _T_119 ? io_dis_uops_1_bits_op2_sel_0 : io_dis_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op1_sel = _T_119 ? io_dis_uops_1_bits_op1_sel_0 : io_dis_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_packed = _T_119 ? io_dis_uops_1_bits_imm_packed_0 : io_dis_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pimm = _T_119 ? io_dis_uops_1_bits_pimm_0 : io_dis_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_sel = _T_119 ? io_dis_uops_1_bits_imm_sel_0 : io_dis_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_rename = _T_119 ? io_dis_uops_1_bits_imm_rename_0 : io_dis_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_taken = _T_119 ? io_dis_uops_1_bits_taken_0 : io_dis_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pc_lob = _T_119 ? io_dis_uops_1_bits_pc_lob_0 : io_dis_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_edge_inst = _T_119 ? io_dis_uops_1_bits_edge_inst_0 : io_dis_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ftq_idx = _T_119 ? io_dis_uops_1_bits_ftq_idx_0 : io_dis_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_mov = _T_119 ? io_dis_uops_1_bits_is_mov_0 : io_dis_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rocc = _T_119 ? io_dis_uops_1_bits_is_rocc_0 : io_dis_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sys_pc2epc = _T_119 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : io_dis_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_eret = _T_119 ? io_dis_uops_1_bits_is_eret_0 : io_dis_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_amo = _T_119 ? io_dis_uops_1_bits_is_amo_0 : io_dis_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfence = _T_119 ? io_dis_uops_1_bits_is_sfence_0 : io_dis_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fencei = _T_119 ? io_dis_uops_1_bits_is_fencei_0 : io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fence = _T_119 ? io_dis_uops_1_bits_is_fence_0 : io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfb = _T_119 ? io_dis_uops_1_bits_is_sfb_0 : io_dis_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_type = _T_119 ? io_dis_uops_1_bits_br_type_0 : io_dis_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_tag = _T_119 ? io_dis_uops_1_bits_br_tag_0 : io_dis_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_mask = _T_119 ? io_dis_uops_1_bits_br_mask_0 : io_dis_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dis_col_sel = _T_119 ? io_dis_uops_1_bits_dis_col_sel_0 : io_dis_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p3_bypass_hint = _T_119 ? _T_59 & prs3_wakeups_0_1 : _WIRE_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :49:89, :76:{32,38}, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p2_bypass_hint = _T_119 ? _T_47 & prs2_wakeups_0_1 : _WIRE_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :48:89, :65:{32,38}, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p1_bypass_hint = _T_119 ? _T_35 & prs1_wakeups_0_1 : _WIRE_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :47:89, :57:{32,38}, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p2_speculative_child = _T_119 ? (_T_47 ? 2'h0 : io_dis_uops_1_bits_iw_p2_speculative_child_0) : _T_12 ? 2'h0 : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :67:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p1_speculative_child = _T_119 ? (_T_35 ? 2'h0 : io_dis_uops_1_bits_iw_p1_speculative_child_0) : _T ? 2'h0 : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :59:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_0 = _T_119 ? io_dis_uops_1_bits_fu_code_0_0 : io_dis_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_1 = _T_119 ? io_dis_uops_1_bits_fu_code_1_0 : io_dis_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_2 = _T_119 ? io_dis_uops_1_bits_fu_code_2_0 : io_dis_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_3 = _T_119 ? io_dis_uops_1_bits_fu_code_3_0 : io_dis_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_4 = _T_119 ? io_dis_uops_1_bits_fu_code_4_0 : io_dis_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_5 = _T_119 ? io_dis_uops_1_bits_fu_code_5_0 : io_dis_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_6 = _T_119 ? io_dis_uops_1_bits_fu_code_6_0 : io_dis_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_7 = _T_119 ? io_dis_uops_1_bits_fu_code_7_0 : io_dis_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_8 = _T_119 ? io_dis_uops_1_bits_fu_code_8_0 : io_dis_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_9 = _T_119 ? io_dis_uops_1_bits_fu_code_9_0 : io_dis_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_0 = _T_119 ? io_dis_uops_1_bits_iq_type_0_0 : io_dis_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_1 = _T_119 ? io_dis_uops_1_bits_iq_type_1_0 : io_dis_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_2 = _T_119 ? io_dis_uops_1_bits_iq_type_2_0 : io_dis_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_3 = _T_119 ? io_dis_uops_1_bits_iq_type_3_0 : io_dis_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_pc = _T_119 ? io_dis_uops_1_bits_debug_pc_0 : io_dis_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rvc = _T_119 ? io_dis_uops_1_bits_is_rvc_0 : io_dis_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_inst = _T_119 ? io_dis_uops_1_bits_debug_inst_0 : io_dis_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_inst = _T_119 ? io_dis_uops_1_bits_inst_0 : io_dis_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_11_clear_T = \|shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_11_clear = _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] reg is_available_0; // @[issue-unit-age-ordered.scala:208:25] reg is_available_1; // @[issue-unit-age-ordered.scala:208:25] reg is_available_2; // @[issue-unit-age-ordered.scala:208:25] reg is_available_3; // @[issue-unit-age-ordered.scala:208:25] reg is_available_4; // @[issue-unit-age-ordered.scala:208:25] reg is_available_5; // @[issue-unit-age-ordered.scala:208:25] reg is_available_6; // @[issue-unit-age-ordered.scala:208:25] reg is_available_7; // @[issue-unit-age-ordered.scala:208:25] reg is_available_8; // @[issue-unit-age-ordered.scala:208:25] reg is_available_9; // @[issue-unit-age-ordered.scala:208:25] reg is_available_10; // @[issue-unit-age-ordered.scala:208:25] reg is_available_11; // @[issue-unit-age-ordered.scala:208:25] wire [1:0] _GEN = {1'h0, is_available_1} + {1'h0, is_available_2}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T = _GEN; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T = _GEN; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_1 = _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_0 = {2'h0, is_available_0}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_2 = _GEN_0 + {1'h0, _io_dis_uops_0_ready_T_1}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_3 = _io_dis_uops_0_ready_T_2[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_1 = {1'h0, is_available_4} + {1'h0, is_available_5}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_4 = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_4 = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_5 = _io_dis_uops_0_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_2 = {2'h0, is_available_3}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_6 = _GEN_2 + {1'h0, _io_dis_uops_0_ready_T_5}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_7 = _io_dis_uops_0_ready_T_6[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_8 = {1'h0, _io_dis_uops_0_ready_T_3} + {1'h0, _io_dis_uops_0_ready_T_7}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_9 = _io_dis_uops_0_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_3 = {1'h0, is_available_7} + {1'h0, is_available_8}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_10 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_10 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_11 = _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_4 = {2'h0, is_available_6}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_12 = _GEN_4 + {1'h0, _io_dis_uops_0_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_13 = _io_dis_uops_0_ready_T_12[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_5 = {1'h0, is_available_10} + {1'h0, is_available_11}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_14 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_14 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_15 = _io_dis_uops_0_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_6 = {2'h0, is_available_9}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_16 = _GEN_6 + {1'h0, _io_dis_uops_0_ready_T_15}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_17 = _io_dis_uops_0_ready_T_16[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_18 = {1'h0, _io_dis_uops_0_ready_T_13} + {1'h0, _io_dis_uops_0_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_19 = _io_dis_uops_0_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_20 = {1'h0, _io_dis_uops_0_ready_T_9} + {1'h0, _io_dis_uops_0_ready_T_19}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_21 = _io_dis_uops_0_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire _GEN_7 = io_dis_uops_0_ready_0 & io_dis_uops_0_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_22; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_22 = _GEN_7; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_22; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_22 = _GEN_7; // @[Decoupled.scala:51:35] wire _GEN_8 = io_dis_uops_1_ready_0 & io_dis_uops_1_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_23; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_23 = _GEN_8; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_23; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_23 = _GEN_8; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_24 = {1'h0, _io_dis_uops_0_ready_T_22} + {1'h0, _io_dis_uops_0_ready_T_23}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_25 = _io_dis_uops_0_ready_T_24; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_0_ready_T_26 = {3'h0, _io_dis_uops_0_ready_T_25}; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_0_ready_T_27 = _io_dis_uops_0_ready_T_26[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_0_ready_T_28 = _io_dis_uops_0_ready_T_21 > _io_dis_uops_0_ready_T_27; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_0_ready_0 = io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] wire [1:0] _io_dis_uops_1_ready_T_1 = _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_2 = _GEN_0 + {1'h0, _io_dis_uops_1_ready_T_1}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_3 = _io_dis_uops_1_ready_T_2[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_5 = _io_dis_uops_1_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_6 = _GEN_2 + {1'h0, _io_dis_uops_1_ready_T_5}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_7 = _io_dis_uops_1_ready_T_6[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_8 = {1'h0, _io_dis_uops_1_ready_T_3} + {1'h0, _io_dis_uops_1_ready_T_7}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_9 = _io_dis_uops_1_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_11 = _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_12 = _GEN_4 + {1'h0, _io_dis_uops_1_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_13 = _io_dis_uops_1_ready_T_12[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_15 = _io_dis_uops_1_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_16 = _GEN_6 + {1'h0, _io_dis_uops_1_ready_T_15}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_17 = _io_dis_uops_1_ready_T_16[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_18 = {1'h0, _io_dis_uops_1_ready_T_13} + {1'h0, _io_dis_uops_1_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_19 = _io_dis_uops_1_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_20 = {1'h0, _io_dis_uops_1_ready_T_9} + {1'h0, _io_dis_uops_1_ready_T_19}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_21 = _io_dis_uops_1_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_24 = {1'h0, _io_dis_uops_1_ready_T_22} + {1'h0, _io_dis_uops_1_ready_T_23}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_1_ready_T_25 = _io_dis_uops_1_ready_T_24; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_1_ready_T_26 = {3'h0, _io_dis_uops_1_ready_T_25} + 5'h1; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_1_ready_T_27 = _io_dis_uops_1_ready_T_26[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_1_ready_T_28 = _io_dis_uops_1_ready_T_21 > _io_dis_uops_1_ready_T_27; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_1_ready_0 = io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_113 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_113( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_sbus_i3_o2_a32d64s9k3z4c : input clock : Clock input reset : Reset output auto : { flip anon_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.user.amba_prot.fetch invalidate anonIn.a.bits.user.amba_prot.secure invalidate anonIn.a.bits.user.amba_prot.privileged invalidate anonIn.a.bits.user.amba_prot.writealloc invalidate anonIn.a.bits.user.amba_prot.readalloc invalidate anonIn.a.bits.user.amba_prot.modifiable invalidate anonIn.a.bits.user.amba_prot.bufferable invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate anonIn_1.e.bits.sink invalidate anonIn_1.e.valid invalidate anonIn_1.e.ready invalidate anonIn_1.d.bits.corrupt invalidate anonIn_1.d.bits.data invalidate anonIn_1.d.bits.denied invalidate anonIn_1.d.bits.sink invalidate anonIn_1.d.bits.source invalidate anonIn_1.d.bits.size invalidate anonIn_1.d.bits.param invalidate anonIn_1.d.bits.opcode invalidate anonIn_1.d.valid invalidate anonIn_1.d.ready invalidate anonIn_1.c.bits.corrupt invalidate anonIn_1.c.bits.data invalidate anonIn_1.c.bits.address invalidate anonIn_1.c.bits.source invalidate anonIn_1.c.bits.size invalidate anonIn_1.c.bits.param invalidate anonIn_1.c.bits.opcode invalidate anonIn_1.c.valid invalidate anonIn_1.c.ready invalidate anonIn_1.b.bits.corrupt invalidate anonIn_1.b.bits.data invalidate anonIn_1.b.bits.mask invalidate anonIn_1.b.bits.address invalidate anonIn_1.b.bits.source invalidate anonIn_1.b.bits.size invalidate anonIn_1.b.bits.param invalidate anonIn_1.b.bits.opcode invalidate anonIn_1.b.valid invalidate anonIn_1.b.ready invalidate anonIn_1.a.bits.corrupt invalidate anonIn_1.a.bits.data invalidate anonIn_1.a.bits.mask invalidate anonIn_1.a.bits.address invalidate anonIn_1.a.bits.source invalidate anonIn_1.a.bits.size invalidate anonIn_1.a.bits.param invalidate anonIn_1.a.bits.opcode invalidate anonIn_1.a.valid invalidate anonIn_1.a.ready wire anonIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn_2.d.bits.corrupt invalidate anonIn_2.d.bits.data invalidate anonIn_2.d.bits.denied invalidate anonIn_2.d.bits.sink invalidate anonIn_2.d.bits.source invalidate anonIn_2.d.bits.size invalidate anonIn_2.d.bits.param invalidate anonIn_2.d.bits.opcode invalidate anonIn_2.d.valid invalidate anonIn_2.d.ready invalidate anonIn_2.a.bits.corrupt invalidate anonIn_2.a.bits.data invalidate anonIn_2.a.bits.mask invalidate anonIn_2.a.bits.user.amba_prot.fetch invalidate anonIn_2.a.bits.user.amba_prot.secure invalidate anonIn_2.a.bits.user.amba_prot.privileged invalidate anonIn_2.a.bits.user.amba_prot.writealloc invalidate anonIn_2.a.bits.user.amba_prot.readalloc invalidate anonIn_2.a.bits.user.amba_prot.modifiable invalidate anonIn_2.a.bits.user.amba_prot.bufferable invalidate anonIn_2.a.bits.address invalidate anonIn_2.a.bits.source invalidate anonIn_2.a.bits.size invalidate anonIn_2.a.bits.param invalidate anonIn_2.a.bits.opcode invalidate anonIn_2.a.valid invalidate anonIn_2.a.ready inst monitor of TLMonitor connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch connect monitor.io.in.a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure connect monitor.io.in.a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged connect monitor.io.in.a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc connect monitor.io.in.a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc connect monitor.io.in.a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable connect monitor.io.in.a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready inst monitor_1 of TLMonitor_1 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.e.bits.sink, anonIn_1.e.bits.sink connect monitor_1.io.in.e.valid, anonIn_1.e.valid connect monitor_1.io.in.e.ready, anonIn_1.e.ready connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, anonIn_1.d.valid connect monitor_1.io.in.d.ready, anonIn_1.d.ready connect monitor_1.io.in.c.bits.corrupt, anonIn_1.c.bits.corrupt connect monitor_1.io.in.c.bits.data, anonIn_1.c.bits.data connect monitor_1.io.in.c.bits.address, anonIn_1.c.bits.address connect monitor_1.io.in.c.bits.source, anonIn_1.c.bits.source connect monitor_1.io.in.c.bits.size, anonIn_1.c.bits.size connect monitor_1.io.in.c.bits.param, anonIn_1.c.bits.param connect monitor_1.io.in.c.bits.opcode, anonIn_1.c.bits.opcode connect monitor_1.io.in.c.valid, anonIn_1.c.valid connect monitor_1.io.in.c.ready, anonIn_1.c.ready connect monitor_1.io.in.b.bits.corrupt, anonIn_1.b.bits.corrupt connect monitor_1.io.in.b.bits.data, anonIn_1.b.bits.data connect monitor_1.io.in.b.bits.mask, anonIn_1.b.bits.mask connect monitor_1.io.in.b.bits.address, anonIn_1.b.bits.address connect monitor_1.io.in.b.bits.source, anonIn_1.b.bits.source connect monitor_1.io.in.b.bits.size, anonIn_1.b.bits.size connect monitor_1.io.in.b.bits.param, anonIn_1.b.bits.param connect monitor_1.io.in.b.bits.opcode, anonIn_1.b.bits.opcode connect monitor_1.io.in.b.valid, anonIn_1.b.valid connect monitor_1.io.in.b.ready, anonIn_1.b.ready connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, anonIn_1.a.valid connect monitor_1.io.in.a.ready, anonIn_1.a.ready inst monitor_2 of TLMonitor_2 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.d.bits.corrupt, anonIn_2.d.bits.corrupt connect monitor_2.io.in.d.bits.data, anonIn_2.d.bits.data connect monitor_2.io.in.d.bits.denied, anonIn_2.d.bits.denied connect monitor_2.io.in.d.bits.sink, anonIn_2.d.bits.sink connect monitor_2.io.in.d.bits.source, anonIn_2.d.bits.source connect monitor_2.io.in.d.bits.size, anonIn_2.d.bits.size connect monitor_2.io.in.d.bits.param, anonIn_2.d.bits.param connect monitor_2.io.in.d.bits.opcode, anonIn_2.d.bits.opcode connect monitor_2.io.in.d.valid, anonIn_2.d.valid connect monitor_2.io.in.d.ready, anonIn_2.d.ready connect monitor_2.io.in.a.bits.corrupt, anonIn_2.a.bits.corrupt connect monitor_2.io.in.a.bits.data, anonIn_2.a.bits.data connect monitor_2.io.in.a.bits.mask, anonIn_2.a.bits.mask connect monitor_2.io.in.a.bits.user.amba_prot.fetch, anonIn_2.a.bits.user.amba_prot.fetch connect monitor_2.io.in.a.bits.user.amba_prot.secure, anonIn_2.a.bits.user.amba_prot.secure connect monitor_2.io.in.a.bits.user.amba_prot.privileged, anonIn_2.a.bits.user.amba_prot.privileged connect monitor_2.io.in.a.bits.user.amba_prot.writealloc, anonIn_2.a.bits.user.amba_prot.writealloc connect monitor_2.io.in.a.bits.user.amba_prot.readalloc, anonIn_2.a.bits.user.amba_prot.readalloc connect monitor_2.io.in.a.bits.user.amba_prot.modifiable, anonIn_2.a.bits.user.amba_prot.modifiable connect monitor_2.io.in.a.bits.user.amba_prot.bufferable, anonIn_2.a.bits.user.amba_prot.bufferable connect monitor_2.io.in.a.bits.address, anonIn_2.a.bits.address connect monitor_2.io.in.a.bits.source, anonIn_2.a.bits.source connect monitor_2.io.in.a.bits.size, anonIn_2.a.bits.size connect monitor_2.io.in.a.bits.param, anonIn_2.a.bits.param connect monitor_2.io.in.a.bits.opcode, anonIn_2.a.bits.opcode connect monitor_2.io.in.a.valid, anonIn_2.a.valid connect monitor_2.io.in.a.ready, anonIn_2.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.user.amba_prot.fetch invalidate anonOut.a.bits.user.amba_prot.secure invalidate anonOut.a.bits.user.amba_prot.privileged invalidate anonOut.a.bits.user.amba_prot.writealloc invalidate anonOut.a.bits.user.amba_prot.readalloc invalidate anonOut.a.bits.user.amba_prot.modifiable invalidate anonOut.a.bits.user.amba_prot.bufferable invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate x1_anonOut.e.bits.sink invalidate x1_anonOut.e.valid invalidate x1_anonOut.e.ready invalidate x1_anonOut.d.bits.corrupt invalidate x1_anonOut.d.bits.data invalidate x1_anonOut.d.bits.denied invalidate x1_anonOut.d.bits.sink invalidate x1_anonOut.d.bits.source invalidate x1_anonOut.d.bits.size invalidate x1_anonOut.d.bits.param invalidate x1_anonOut.d.bits.opcode invalidate x1_anonOut.d.valid invalidate x1_anonOut.d.ready invalidate x1_anonOut.c.bits.corrupt invalidate x1_anonOut.c.bits.data invalidate x1_anonOut.c.bits.address invalidate x1_anonOut.c.bits.source invalidate x1_anonOut.c.bits.size invalidate x1_anonOut.c.bits.param invalidate x1_anonOut.c.bits.opcode invalidate x1_anonOut.c.valid invalidate x1_anonOut.c.ready invalidate x1_anonOut.b.bits.corrupt invalidate x1_anonOut.b.bits.data invalidate x1_anonOut.b.bits.mask invalidate x1_anonOut.b.bits.address invalidate x1_anonOut.b.bits.source invalidate x1_anonOut.b.bits.size invalidate x1_anonOut.b.bits.param invalidate x1_anonOut.b.bits.opcode invalidate x1_anonOut.b.valid invalidate x1_anonOut.b.ready invalidate x1_anonOut.a.bits.corrupt invalidate x1_anonOut.a.bits.data invalidate x1_anonOut.a.bits.mask invalidate x1_anonOut.a.bits.address invalidate x1_anonOut.a.bits.source invalidate x1_anonOut.a.bits.size invalidate x1_anonOut.a.bits.param invalidate x1_anonOut.a.bits.opcode invalidate x1_anonOut.a.valid invalidate x1_anonOut.a.ready connect auto.anon_out_0, anonOut connect auto.anon_out_1, x1_anonOut connect anonIn, auto.anon_in_0 connect anonIn_1, auto.anon_in_1 connect anonIn_2, auto.anon_in_2 wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[3] invalidate in[0].a.bits.user.amba_prot.fetch invalidate in[0].a.bits.user.amba_prot.secure invalidate in[0].a.bits.user.amba_prot.privileged invalidate in[0].a.bits.user.amba_prot.writealloc invalidate in[0].a.bits.user.amba_prot.readalloc invalidate in[0].a.bits.user.amba_prot.modifiable invalidate in[0].a.bits.user.amba_prot.bufferable connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt connect in[0].a.bits.data, anonIn.a.bits.data connect in[0].a.bits.mask, anonIn.a.bits.mask connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable connect in[0].a.bits.address, anonIn.a.bits.address connect in[0].a.bits.source, anonIn.a.bits.source connect in[0].a.bits.size, anonIn.a.bits.size connect in[0].a.bits.param, anonIn.a.bits.param connect in[0].a.bits.opcode, anonIn.a.bits.opcode connect in[0].a.valid, anonIn.a.valid connect anonIn.a.ready, in[0].a.ready node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<9>(0h100)) connect in[0].a.bits.source, _in_0_a_bits_source_T invalidate in[0].b.bits.corrupt invalidate in[0].b.bits.data invalidate in[0].b.bits.mask invalidate in[0].b.bits.address invalidate in[0].b.bits.source invalidate in[0].b.bits.size invalidate in[0].b.bits.param invalidate in[0].b.bits.opcode invalidate in[0].b.valid invalidate in[0].b.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready invalidate _WIRE_1.bits.corrupt invalidate _WIRE_1.bits.data invalidate _WIRE_1.bits.mask invalidate _WIRE_1.bits.address invalidate _WIRE_1.bits.source invalidate _WIRE_1.bits.size invalidate _WIRE_1.bits.param invalidate _WIRE_1.bits.opcode invalidate _WIRE_1.valid invalidate _WIRE_1.ready connect in[0].b.ready, UInt<1>(0h1) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.mask, UInt<8>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<2>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) invalidate in[0].c.bits.corrupt invalidate in[0].c.bits.data invalidate in[0].c.bits.user.amba_prot.fetch invalidate in[0].c.bits.user.amba_prot.secure invalidate in[0].c.bits.user.amba_prot.privileged invalidate in[0].c.bits.user.amba_prot.writealloc invalidate in[0].c.bits.user.amba_prot.readalloc invalidate in[0].c.bits.user.amba_prot.modifiable invalidate in[0].c.bits.user.amba_prot.bufferable invalidate in[0].c.bits.address invalidate in[0].c.bits.source invalidate in[0].c.bits.size invalidate in[0].c.bits.param invalidate in[0].c.bits.opcode invalidate in[0].c.valid invalidate in[0].c.ready wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_4.bits.address, UInt<32>(0h0) connect _WIRE_4.bits.source, UInt<5>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<3>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready invalidate _WIRE_5.bits.corrupt invalidate _WIRE_5.bits.data invalidate _WIRE_5.bits.user.amba_prot.fetch invalidate _WIRE_5.bits.user.amba_prot.secure invalidate _WIRE_5.bits.user.amba_prot.privileged invalidate _WIRE_5.bits.user.amba_prot.writealloc invalidate _WIRE_5.bits.user.amba_prot.readalloc invalidate _WIRE_5.bits.user.amba_prot.modifiable invalidate _WIRE_5.bits.user.amba_prot.bufferable invalidate _WIRE_5.bits.address invalidate _WIRE_5.bits.source invalidate _WIRE_5.bits.size invalidate _WIRE_5.bits.param invalidate _WIRE_5.bits.opcode invalidate _WIRE_5.valid invalidate _WIRE_5.ready connect in[0].c.valid, UInt<1>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt connect anonIn.d.bits.data, in[0].d.bits.data connect anonIn.d.bits.denied, in[0].d.bits.denied connect anonIn.d.bits.sink, in[0].d.bits.sink connect anonIn.d.bits.source, in[0].d.bits.source connect anonIn.d.bits.size, in[0].d.bits.size connect anonIn.d.bits.param, in[0].d.bits.param connect anonIn.d.bits.opcode, in[0].d.bits.opcode connect anonIn.d.valid, in[0].d.valid connect in[0].d.ready, anonIn.d.ready node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0) connect anonIn.d.bits.source, _anonIn_d_bits_source_T invalidate in[0].e.bits.sink invalidate in[0].e.valid invalidate in[0].e.ready wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_8.bits.sink, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready invalidate _WIRE_9.bits.sink invalidate _WIRE_9.valid invalidate _WIRE_9.ready connect in[0].e.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.ready, UInt<1>(0h1) invalidate in[1].a.bits.user.amba_prot.fetch invalidate in[1].a.bits.user.amba_prot.secure invalidate in[1].a.bits.user.amba_prot.privileged invalidate in[1].a.bits.user.amba_prot.writealloc invalidate in[1].a.bits.user.amba_prot.readalloc invalidate in[1].a.bits.user.amba_prot.modifiable invalidate in[1].a.bits.user.amba_prot.bufferable connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt connect in[1].a.bits.data, anonIn_1.a.bits.data connect in[1].a.bits.mask, anonIn_1.a.bits.mask connect in[1].a.bits.address, anonIn_1.a.bits.address connect in[1].a.bits.source, anonIn_1.a.bits.source connect in[1].a.bits.size, anonIn_1.a.bits.size connect in[1].a.bits.param, anonIn_1.a.bits.param connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode connect in[1].a.valid, anonIn_1.a.valid connect anonIn_1.a.ready, in[1].a.ready node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<9>(0h120)) connect in[1].a.bits.source, _in_1_a_bits_source_T connect anonIn_1.b.bits.corrupt, in[1].b.bits.corrupt connect anonIn_1.b.bits.data, in[1].b.bits.data connect anonIn_1.b.bits.mask, in[1].b.bits.mask connect anonIn_1.b.bits.address, in[1].b.bits.address connect anonIn_1.b.bits.source, in[1].b.bits.source connect anonIn_1.b.bits.size, in[1].b.bits.size connect anonIn_1.b.bits.param, in[1].b.bits.param connect anonIn_1.b.bits.opcode, in[1].b.bits.opcode connect anonIn_1.b.valid, in[1].b.valid connect in[1].b.ready, anonIn_1.b.ready node _anonIn_b_bits_source_T = bits(in[1].b.bits.source, 1, 0) connect anonIn_1.b.bits.source, _anonIn_b_bits_source_T invalidate in[1].c.bits.user.amba_prot.fetch invalidate in[1].c.bits.user.amba_prot.secure invalidate in[1].c.bits.user.amba_prot.privileged invalidate in[1].c.bits.user.amba_prot.writealloc invalidate in[1].c.bits.user.amba_prot.readalloc invalidate in[1].c.bits.user.amba_prot.modifiable invalidate in[1].c.bits.user.amba_prot.bufferable connect in[1].c.bits.corrupt, anonIn_1.c.bits.corrupt connect in[1].c.bits.data, anonIn_1.c.bits.data connect in[1].c.bits.address, anonIn_1.c.bits.address connect in[1].c.bits.source, anonIn_1.c.bits.source connect in[1].c.bits.size, anonIn_1.c.bits.size connect in[1].c.bits.param, anonIn_1.c.bits.param connect in[1].c.bits.opcode, anonIn_1.c.bits.opcode connect in[1].c.valid, anonIn_1.c.valid connect anonIn_1.c.ready, in[1].c.ready node _in_1_c_bits_source_T = or(anonIn_1.c.bits.source, UInt<9>(0h120)) connect in[1].c.bits.source, _in_1_c_bits_source_T connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt connect anonIn_1.d.bits.data, in[1].d.bits.data connect anonIn_1.d.bits.denied, in[1].d.bits.denied connect anonIn_1.d.bits.sink, in[1].d.bits.sink connect anonIn_1.d.bits.source, in[1].d.bits.source connect anonIn_1.d.bits.size, in[1].d.bits.size connect anonIn_1.d.bits.param, in[1].d.bits.param connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode connect anonIn_1.d.valid, in[1].d.valid connect in[1].d.ready, anonIn_1.d.ready node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 1, 0) connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1 connect in[1].e.bits.sink, anonIn_1.e.bits.sink connect in[1].e.valid, anonIn_1.e.valid connect anonIn_1.e.ready, in[1].e.ready invalidate in[2].a.bits.user.amba_prot.fetch invalidate in[2].a.bits.user.amba_prot.secure invalidate in[2].a.bits.user.amba_prot.privileged invalidate in[2].a.bits.user.amba_prot.writealloc invalidate in[2].a.bits.user.amba_prot.readalloc invalidate in[2].a.bits.user.amba_prot.modifiable invalidate in[2].a.bits.user.amba_prot.bufferable connect in[2].a.bits.corrupt, anonIn_2.a.bits.corrupt connect in[2].a.bits.data, anonIn_2.a.bits.data connect in[2].a.bits.mask, anonIn_2.a.bits.mask connect in[2].a.bits.user.amba_prot.fetch, anonIn_2.a.bits.user.amba_prot.fetch connect in[2].a.bits.user.amba_prot.secure, anonIn_2.a.bits.user.amba_prot.secure connect in[2].a.bits.user.amba_prot.privileged, anonIn_2.a.bits.user.amba_prot.privileged connect in[2].a.bits.user.amba_prot.writealloc, anonIn_2.a.bits.user.amba_prot.writealloc connect in[2].a.bits.user.amba_prot.readalloc, anonIn_2.a.bits.user.amba_prot.readalloc connect in[2].a.bits.user.amba_prot.modifiable, anonIn_2.a.bits.user.amba_prot.modifiable connect in[2].a.bits.user.amba_prot.bufferable, anonIn_2.a.bits.user.amba_prot.bufferable connect in[2].a.bits.address, anonIn_2.a.bits.address connect in[2].a.bits.source, anonIn_2.a.bits.source connect in[2].a.bits.size, anonIn_2.a.bits.size connect in[2].a.bits.param, anonIn_2.a.bits.param connect in[2].a.bits.opcode, anonIn_2.a.bits.opcode connect in[2].a.valid, anonIn_2.a.valid connect anonIn_2.a.ready, in[2].a.ready node _in_2_a_bits_source_T = or(anonIn_2.a.bits.source, UInt<1>(0h0)) connect in[2].a.bits.source, _in_2_a_bits_source_T invalidate in[2].b.bits.corrupt invalidate in[2].b.bits.data invalidate in[2].b.bits.mask invalidate in[2].b.bits.address invalidate in[2].b.bits.source invalidate in[2].b.bits.size invalidate in[2].b.bits.param invalidate in[2].b.bits.opcode invalidate in[2].b.valid invalidate in[2].b.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.mask, UInt<8>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<2>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready invalidate _WIRE_13.bits.corrupt invalidate _WIRE_13.bits.data invalidate _WIRE_13.bits.mask invalidate _WIRE_13.bits.address invalidate _WIRE_13.bits.source invalidate _WIRE_13.bits.size invalidate _WIRE_13.bits.param invalidate _WIRE_13.bits.opcode invalidate _WIRE_13.valid invalidate _WIRE_13.ready connect in[2].b.ready, UInt<1>(0h1) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.mask, UInt<8>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<2>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.valid, UInt<1>(0h0) invalidate in[2].c.bits.corrupt invalidate in[2].c.bits.data invalidate in[2].c.bits.user.amba_prot.fetch invalidate in[2].c.bits.user.amba_prot.secure invalidate in[2].c.bits.user.amba_prot.privileged invalidate in[2].c.bits.user.amba_prot.writealloc invalidate in[2].c.bits.user.amba_prot.readalloc invalidate in[2].c.bits.user.amba_prot.modifiable invalidate in[2].c.bits.user.amba_prot.bufferable invalidate in[2].c.bits.address invalidate in[2].c.bits.source invalidate in[2].c.bits.size invalidate in[2].c.bits.param invalidate in[2].c.bits.opcode invalidate in[2].c.valid invalidate in[2].c.ready wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready invalidate _WIRE_17.bits.corrupt invalidate _WIRE_17.bits.data invalidate _WIRE_17.bits.user.amba_prot.fetch invalidate _WIRE_17.bits.user.amba_prot.secure invalidate _WIRE_17.bits.user.amba_prot.privileged invalidate _WIRE_17.bits.user.amba_prot.writealloc invalidate _WIRE_17.bits.user.amba_prot.readalloc invalidate _WIRE_17.bits.user.amba_prot.modifiable invalidate _WIRE_17.bits.user.amba_prot.bufferable invalidate _WIRE_17.bits.address invalidate _WIRE_17.bits.source invalidate _WIRE_17.bits.size invalidate _WIRE_17.bits.param invalidate _WIRE_17.bits.opcode invalidate _WIRE_17.valid invalidate _WIRE_17.ready connect in[2].c.valid, UInt<1>(0h0) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.ready, UInt<1>(0h1) connect anonIn_2.d.bits.corrupt, in[2].d.bits.corrupt connect anonIn_2.d.bits.data, in[2].d.bits.data connect anonIn_2.d.bits.denied, in[2].d.bits.denied connect anonIn_2.d.bits.sink, in[2].d.bits.sink connect anonIn_2.d.bits.source, in[2].d.bits.source connect anonIn_2.d.bits.size, in[2].d.bits.size connect anonIn_2.d.bits.param, in[2].d.bits.param connect anonIn_2.d.bits.opcode, in[2].d.bits.opcode connect anonIn_2.d.valid, in[2].d.valid connect in[2].d.ready, anonIn_2.d.ready node _anonIn_d_bits_source_T_2 = bits(in[2].d.bits.source, 7, 0) connect anonIn_2.d.bits.source, _anonIn_d_bits_source_T_2 invalidate in[2].e.bits.sink invalidate in[2].e.valid invalidate in[2].e.ready wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_20.bits.sink, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready invalidate _WIRE_21.bits.sink invalidate _WIRE_21.valid invalidate _WIRE_21.ready connect in[2].e.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_22.bits.sink, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.ready, UInt<1>(0h1) wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}[2] invalidate out[0].a.bits.user.amba_prot.fetch invalidate out[0].a.bits.user.amba_prot.secure invalidate out[0].a.bits.user.amba_prot.privileged invalidate out[0].a.bits.user.amba_prot.writealloc invalidate out[0].a.bits.user.amba_prot.readalloc invalidate out[0].a.bits.user.amba_prot.modifiable invalidate out[0].a.bits.user.amba_prot.bufferable connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt connect anonOut.a.bits.data, out[0].a.bits.data connect anonOut.a.bits.mask, out[0].a.bits.mask connect anonOut.a.bits.user.amba_prot.fetch, out[0].a.bits.user.amba_prot.fetch connect anonOut.a.bits.user.amba_prot.secure, out[0].a.bits.user.amba_prot.secure connect anonOut.a.bits.user.amba_prot.privileged, out[0].a.bits.user.amba_prot.privileged connect anonOut.a.bits.user.amba_prot.writealloc, out[0].a.bits.user.amba_prot.writealloc connect anonOut.a.bits.user.amba_prot.readalloc, out[0].a.bits.user.amba_prot.readalloc connect anonOut.a.bits.user.amba_prot.modifiable, out[0].a.bits.user.amba_prot.modifiable connect anonOut.a.bits.user.amba_prot.bufferable, out[0].a.bits.user.amba_prot.bufferable connect anonOut.a.bits.address, out[0].a.bits.address connect anonOut.a.bits.source, out[0].a.bits.source connect anonOut.a.bits.size, out[0].a.bits.size connect anonOut.a.bits.param, out[0].a.bits.param connect anonOut.a.bits.opcode, out[0].a.bits.opcode connect anonOut.a.valid, out[0].a.valid connect out[0].a.ready, anonOut.a.ready invalidate out[0].b.bits.corrupt invalidate out[0].b.bits.data invalidate out[0].b.bits.mask invalidate out[0].b.bits.address invalidate out[0].b.bits.source invalidate out[0].b.bits.size invalidate out[0].b.bits.param invalidate out[0].b.bits.opcode invalidate out[0].b.valid invalidate out[0].b.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<9>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready invalidate _WIRE_25.bits.corrupt invalidate _WIRE_25.bits.data invalidate _WIRE_25.bits.mask invalidate _WIRE_25.bits.address invalidate _WIRE_25.bits.source invalidate _WIRE_25.bits.size invalidate _WIRE_25.bits.param invalidate _WIRE_25.bits.opcode invalidate _WIRE_25.valid invalidate _WIRE_25.ready connect out[0].b.valid, UInt<1>(0h0) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.mask, UInt<8>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<9>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<2>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready connect _WIRE_27.ready, UInt<1>(0h1) invalidate out[0].c.bits.corrupt invalidate out[0].c.bits.data invalidate out[0].c.bits.user.amba_prot.fetch invalidate out[0].c.bits.user.amba_prot.secure invalidate out[0].c.bits.user.amba_prot.privileged invalidate out[0].c.bits.user.amba_prot.writealloc invalidate out[0].c.bits.user.amba_prot.readalloc invalidate out[0].c.bits.user.amba_prot.modifiable invalidate out[0].c.bits.user.amba_prot.bufferable invalidate out[0].c.bits.address invalidate out[0].c.bits.source invalidate out[0].c.bits.size invalidate out[0].c.bits.param invalidate out[0].c.bits.opcode invalidate out[0].c.valid invalidate out[0].c.ready wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_28.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<9>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready invalidate _WIRE_29.bits.corrupt invalidate _WIRE_29.bits.data invalidate _WIRE_29.bits.user.amba_prot.fetch invalidate _WIRE_29.bits.user.amba_prot.secure invalidate _WIRE_29.bits.user.amba_prot.privileged invalidate _WIRE_29.bits.user.amba_prot.writealloc invalidate _WIRE_29.bits.user.amba_prot.readalloc invalidate _WIRE_29.bits.user.amba_prot.modifiable invalidate _WIRE_29.bits.user.amba_prot.bufferable invalidate _WIRE_29.bits.address invalidate _WIRE_29.bits.source invalidate _WIRE_29.bits.size invalidate _WIRE_29.bits.param invalidate _WIRE_29.bits.opcode invalidate _WIRE_29.valid invalidate _WIRE_29.ready connect out[0].c.ready, UInt<1>(0h1) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_30.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_30.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_30.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_30.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_30.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_30.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_30.bits.address, UInt<29>(0h0) connect _WIRE_30.bits.source, UInt<9>(0h0) connect _WIRE_30.bits.size, UInt<4>(0h0) connect _WIRE_30.bits.param, UInt<3>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.valid, UInt<1>(0h0) connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt connect out[0].d.bits.data, anonOut.d.bits.data connect out[0].d.bits.denied, anonOut.d.bits.denied connect out[0].d.bits.sink, anonOut.d.bits.sink connect out[0].d.bits.source, anonOut.d.bits.source connect out[0].d.bits.size, anonOut.d.bits.size connect out[0].d.bits.param, anonOut.d.bits.param connect out[0].d.bits.opcode, anonOut.d.bits.opcode connect out[0].d.valid, anonOut.d.valid connect anonOut.d.ready, out[0].d.ready node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) connect out[0].d.bits.sink, _out_0_d_bits_sink_T invalidate out[0].e.bits.sink invalidate out[0].e.valid invalidate out[0].e.ready wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_32.bits.sink, UInt<1>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready invalidate _WIRE_33.bits.sink invalidate _WIRE_33.valid invalidate _WIRE_33.ready connect out[0].e.ready, UInt<1>(0h1) wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_34.bits.sink, UInt<1>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready connect _WIRE_35.valid, UInt<1>(0h0) invalidate out[1].a.bits.user.amba_prot.fetch invalidate out[1].a.bits.user.amba_prot.secure invalidate out[1].a.bits.user.amba_prot.privileged invalidate out[1].a.bits.user.amba_prot.writealloc invalidate out[1].a.bits.user.amba_prot.readalloc invalidate out[1].a.bits.user.amba_prot.modifiable invalidate out[1].a.bits.user.amba_prot.bufferable connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt connect x1_anonOut.a.bits.data, out[1].a.bits.data connect x1_anonOut.a.bits.mask, out[1].a.bits.mask connect x1_anonOut.a.bits.address, out[1].a.bits.address connect x1_anonOut.a.bits.source, out[1].a.bits.source connect x1_anonOut.a.bits.size, out[1].a.bits.size connect x1_anonOut.a.bits.param, out[1].a.bits.param connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode connect x1_anonOut.a.valid, out[1].a.valid connect out[1].a.ready, x1_anonOut.a.ready connect out[1].b.bits.corrupt, x1_anonOut.b.bits.corrupt connect out[1].b.bits.data, x1_anonOut.b.bits.data connect out[1].b.bits.mask, x1_anonOut.b.bits.mask connect out[1].b.bits.address, x1_anonOut.b.bits.address connect out[1].b.bits.source, x1_anonOut.b.bits.source connect out[1].b.bits.size, x1_anonOut.b.bits.size connect out[1].b.bits.param, x1_anonOut.b.bits.param connect out[1].b.bits.opcode, x1_anonOut.b.bits.opcode connect out[1].b.valid, x1_anonOut.b.valid connect x1_anonOut.b.ready, out[1].b.ready invalidate out[1].c.bits.user.amba_prot.fetch invalidate out[1].c.bits.user.amba_prot.secure invalidate out[1].c.bits.user.amba_prot.privileged invalidate out[1].c.bits.user.amba_prot.writealloc invalidate out[1].c.bits.user.amba_prot.readalloc invalidate out[1].c.bits.user.amba_prot.modifiable invalidate out[1].c.bits.user.amba_prot.bufferable connect x1_anonOut.c.bits.corrupt, out[1].c.bits.corrupt connect x1_anonOut.c.bits.data, out[1].c.bits.data connect x1_anonOut.c.bits.address, out[1].c.bits.address connect x1_anonOut.c.bits.source, out[1].c.bits.source connect x1_anonOut.c.bits.size, out[1].c.bits.size connect x1_anonOut.c.bits.param, out[1].c.bits.param connect x1_anonOut.c.bits.opcode, out[1].c.bits.opcode connect x1_anonOut.c.valid, out[1].c.valid connect out[1].c.ready, x1_anonOut.c.ready connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt connect out[1].d.bits.data, x1_anonOut.d.bits.data connect out[1].d.bits.denied, x1_anonOut.d.bits.denied connect out[1].d.bits.sink, x1_anonOut.d.bits.sink connect out[1].d.bits.source, x1_anonOut.d.bits.source connect out[1].d.bits.size, x1_anonOut.d.bits.size connect out[1].d.bits.param, x1_anonOut.d.bits.param connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode connect out[1].d.valid, x1_anonOut.d.valid connect x1_anonOut.d.ready, out[1].d.ready node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0)) connect out[1].d.bits.sink, _out_1_d_bits_sink_T connect x1_anonOut.e.bits.sink, out[1].e.bits.sink connect x1_anonOut.e.valid, out[1].e.valid connect out[1].e.ready, x1_anonOut.e.ready node _anonOut_e_bits_sink_T = bits(out[1].e.bits.sink, 2, 0) connect x1_anonOut.e.bits.sink, _anonOut_e_bits_sink_T node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_1 = cvt(_requestAIO_T) node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_3 = asSInt(_requestAIO_T_2) node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_6 = cvt(_requestAIO_T_5) node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h9c011000))) node _requestAIO_T_8 = asSInt(_requestAIO_T_7) node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_11 = cvt(_requestAIO_T_10) node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<33>(0h9c000000))) node _requestAIO_T_13 = asSInt(_requestAIO_T_12) node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0))) node _requestAIO_T_15 = xor(in[0].a.bits.address, UInt<29>(0h10000000)) node _requestAIO_T_16 = cvt(_requestAIO_T_15) node _requestAIO_T_17 = and(_requestAIO_T_16, asSInt(UInt<33>(0h9c011000))) node _requestAIO_T_18 = asSInt(_requestAIO_T_17) node _requestAIO_T_19 = eq(_requestAIO_T_18, asSInt(UInt<1>(0h0))) node _requestAIO_T_20 = or(_requestAIO_T_4, _requestAIO_T_9) node _requestAIO_T_21 = or(_requestAIO_T_20, _requestAIO_T_14) node _requestAIO_T_22 = or(_requestAIO_T_21, _requestAIO_T_19) node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_22) node _requestAIO_T_23 = xor(in[0].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_24 = cvt(_requestAIO_T_23) node _requestAIO_T_25 = and(_requestAIO_T_24, asSInt(UInt<33>(0h9c010000))) node _requestAIO_T_26 = asSInt(_requestAIO_T_25) node _requestAIO_T_27 = eq(_requestAIO_T_26, asSInt(UInt<1>(0h0))) node _requestAIO_T_28 = xor(in[0].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_29 = cvt(_requestAIO_T_28) node _requestAIO_T_30 = and(_requestAIO_T_29, asSInt(UInt<33>(0h90000000))) node _requestAIO_T_31 = asSInt(_requestAIO_T_30) node _requestAIO_T_32 = eq(_requestAIO_T_31, asSInt(UInt<1>(0h0))) node _requestAIO_T_33 = or(_requestAIO_T_27, _requestAIO_T_32) node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_33) node _requestAIO_T_34 = xor(in[1].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_35 = cvt(_requestAIO_T_34) node _requestAIO_T_36 = and(_requestAIO_T_35, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_37 = asSInt(_requestAIO_T_36) node _requestAIO_T_38 = eq(_requestAIO_T_37, asSInt(UInt<1>(0h0))) node _requestAIO_T_39 = xor(in[1].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_40 = cvt(_requestAIO_T_39) node _requestAIO_T_41 = and(_requestAIO_T_40, asSInt(UInt<33>(0h9c011000))) node _requestAIO_T_42 = asSInt(_requestAIO_T_41) node _requestAIO_T_43 = eq(_requestAIO_T_42, asSInt(UInt<1>(0h0))) node _requestAIO_T_44 = xor(in[1].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_45 = cvt(_requestAIO_T_44) node _requestAIO_T_46 = and(_requestAIO_T_45, asSInt(UInt<33>(0h9c000000))) node _requestAIO_T_47 = asSInt(_requestAIO_T_46) node _requestAIO_T_48 = eq(_requestAIO_T_47, asSInt(UInt<1>(0h0))) node _requestAIO_T_49 = xor(in[1].a.bits.address, UInt<29>(0h10000000)) node _requestAIO_T_50 = cvt(_requestAIO_T_49) node _requestAIO_T_51 = and(_requestAIO_T_50, asSInt(UInt<33>(0h9c011000))) node _requestAIO_T_52 = asSInt(_requestAIO_T_51) node _requestAIO_T_53 = eq(_requestAIO_T_52, asSInt(UInt<1>(0h0))) node _requestAIO_T_54 = or(_requestAIO_T_38, _requestAIO_T_43) node _requestAIO_T_55 = or(_requestAIO_T_54, _requestAIO_T_48) node _requestAIO_T_56 = or(_requestAIO_T_55, _requestAIO_T_53) node requestAIO_1_0 = or(UInt<1>(0h0), _requestAIO_T_56) node _requestAIO_T_57 = xor(in[1].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_58 = cvt(_requestAIO_T_57) node _requestAIO_T_59 = and(_requestAIO_T_58, asSInt(UInt<33>(0h9c010000))) node _requestAIO_T_60 = asSInt(_requestAIO_T_59) node _requestAIO_T_61 = eq(_requestAIO_T_60, asSInt(UInt<1>(0h0))) node _requestAIO_T_62 = xor(in[1].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_63 = cvt(_requestAIO_T_62) node _requestAIO_T_64 = and(_requestAIO_T_63, asSInt(UInt<33>(0h90000000))) node _requestAIO_T_65 = asSInt(_requestAIO_T_64) node _requestAIO_T_66 = eq(_requestAIO_T_65, asSInt(UInt<1>(0h0))) node _requestAIO_T_67 = or(_requestAIO_T_61, _requestAIO_T_66) node requestAIO_1_1 = or(UInt<1>(0h0), _requestAIO_T_67) node _requestAIO_T_68 = xor(in[2].a.bits.address, UInt<1>(0h0)) node _requestAIO_T_69 = cvt(_requestAIO_T_68) node _requestAIO_T_70 = and(_requestAIO_T_69, asSInt(UInt<33>(0h8c000000))) node _requestAIO_T_71 = asSInt(_requestAIO_T_70) node _requestAIO_T_72 = eq(_requestAIO_T_71, asSInt(UInt<1>(0h0))) node _requestAIO_T_73 = xor(in[2].a.bits.address, UInt<17>(0h10000)) node _requestAIO_T_74 = cvt(_requestAIO_T_73) node _requestAIO_T_75 = and(_requestAIO_T_74, asSInt(UInt<33>(0h9c011000))) node _requestAIO_T_76 = asSInt(_requestAIO_T_75) node _requestAIO_T_77 = eq(_requestAIO_T_76, asSInt(UInt<1>(0h0))) node _requestAIO_T_78 = xor(in[2].a.bits.address, UInt<28>(0hc000000)) node _requestAIO_T_79 = cvt(_requestAIO_T_78) node _requestAIO_T_80 = and(_requestAIO_T_79, asSInt(UInt<33>(0h9c000000))) node _requestAIO_T_81 = asSInt(_requestAIO_T_80) node _requestAIO_T_82 = eq(_requestAIO_T_81, asSInt(UInt<1>(0h0))) node _requestAIO_T_83 = xor(in[2].a.bits.address, UInt<29>(0h10000000)) node _requestAIO_T_84 = cvt(_requestAIO_T_83) node _requestAIO_T_85 = and(_requestAIO_T_84, asSInt(UInt<33>(0h9c011000))) node _requestAIO_T_86 = asSInt(_requestAIO_T_85) node _requestAIO_T_87 = eq(_requestAIO_T_86, asSInt(UInt<1>(0h0))) node _requestAIO_T_88 = or(_requestAIO_T_72, _requestAIO_T_77) node _requestAIO_T_89 = or(_requestAIO_T_88, _requestAIO_T_82) node _requestAIO_T_90 = or(_requestAIO_T_89, _requestAIO_T_87) node requestAIO_2_0 = or(UInt<1>(0h0), _requestAIO_T_90) node _requestAIO_T_91 = xor(in[2].a.bits.address, UInt<28>(0h8000000)) node _requestAIO_T_92 = cvt(_requestAIO_T_91) node _requestAIO_T_93 = and(_requestAIO_T_92, asSInt(UInt<33>(0h9c010000))) node _requestAIO_T_94 = asSInt(_requestAIO_T_93) node _requestAIO_T_95 = eq(_requestAIO_T_94, asSInt(UInt<1>(0h0))) node _requestAIO_T_96 = xor(in[2].a.bits.address, UInt<32>(0h80000000)) node _requestAIO_T_97 = cvt(_requestAIO_T_96) node _requestAIO_T_98 = and(_requestAIO_T_97, asSInt(UInt<33>(0h90000000))) node _requestAIO_T_99 = asSInt(_requestAIO_T_98) node _requestAIO_T_100 = eq(_requestAIO_T_99, asSInt(UInt<1>(0h0))) node _requestAIO_T_101 = or(_requestAIO_T_95, _requestAIO_T_100) node requestAIO_2_1 = or(UInt<1>(0h0), _requestAIO_T_101) node _requestCIO_T = xor(in[0].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_1 = cvt(_requestCIO_T) node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) node _requestCIO_T_3 = asSInt(_requestCIO_T_2) node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) node _requestCIO_T_5 = xor(in[0].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_6 = cvt(_requestCIO_T_5) node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) node _requestCIO_T_8 = asSInt(_requestCIO_T_7) node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9) node _requestCIO_T_10 = xor(in[1].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_11 = cvt(_requestCIO_T_10) node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0))) node _requestCIO_T_13 = asSInt(_requestCIO_T_12) node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0))) node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_14) node _requestCIO_T_15 = xor(in[1].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_16 = cvt(_requestCIO_T_15) node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0))) node _requestCIO_T_18 = asSInt(_requestCIO_T_17) node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0))) node requestCIO_1_1 = or(UInt<1>(0h1), _requestCIO_T_19) node _requestCIO_T_20 = xor(in[2].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_21 = cvt(_requestCIO_T_20) node _requestCIO_T_22 = and(_requestCIO_T_21, asSInt(UInt<1>(0h0))) node _requestCIO_T_23 = asSInt(_requestCIO_T_22) node _requestCIO_T_24 = eq(_requestCIO_T_23, asSInt(UInt<1>(0h0))) node requestCIO_2_0 = or(UInt<1>(0h1), _requestCIO_T_24) node _requestCIO_T_25 = xor(in[2].c.bits.address, UInt<1>(0h0)) node _requestCIO_T_26 = cvt(_requestCIO_T_25) node _requestCIO_T_27 = and(_requestCIO_T_26, asSInt(UInt<1>(0h0))) node _requestCIO_T_28 = asSInt(_requestCIO_T_27) node _requestCIO_T_29 = eq(_requestCIO_T_28, asSInt(UInt<1>(0h0))) node requestCIO_2_1 = or(UInt<1>(0h1), _requestCIO_T_29) node _requestBOI_uncommonBits_T = or(out[0].b.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0) node _requestBOI_T = shr(out[0].b.bits.source, 5) node _requestBOI_T_1 = eq(_requestBOI_T, UInt<4>(0h8)) node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f)) node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) node _requestBOI_uncommonBits_T_1 = or(out[0].b.bits.source, UInt<2>(0h0)) node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 1, 0) node _requestBOI_T_5 = shr(out[0].b.bits.source, 2) node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<7>(0h48)) node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<2>(0h3)) node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9) node _requestBOI_uncommonBits_T_2 = or(out[0].b.bits.source, UInt<8>(0h0)) node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 7, 0) node _requestBOI_T_10 = shr(out[0].b.bits.source, 8) node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h0)) node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2) node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12) node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<8>(0hff)) node requestBOI_0_2 = and(_requestBOI_T_13, _requestBOI_T_14) node _requestBOI_uncommonBits_T_3 = or(out[1].b.bits.source, UInt<5>(0h0)) node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 4, 0) node _requestBOI_T_15 = shr(out[1].b.bits.source, 5) node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<4>(0h8)) node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3) node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17) node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<5>(0h1f)) node requestBOI_1_0 = and(_requestBOI_T_18, _requestBOI_T_19) node _requestBOI_uncommonBits_T_4 = or(out[1].b.bits.source, UInt<2>(0h0)) node requestBOI_uncommonBits_4 = bits(_requestBOI_uncommonBits_T_4, 1, 0) node _requestBOI_T_20 = shr(out[1].b.bits.source, 2) node _requestBOI_T_21 = eq(_requestBOI_T_20, UInt<7>(0h48)) node _requestBOI_T_22 = leq(UInt<1>(0h0), requestBOI_uncommonBits_4) node _requestBOI_T_23 = and(_requestBOI_T_21, _requestBOI_T_22) node _requestBOI_T_24 = leq(requestBOI_uncommonBits_4, UInt<2>(0h3)) node requestBOI_1_1 = and(_requestBOI_T_23, _requestBOI_T_24) node _requestBOI_uncommonBits_T_5 = or(out[1].b.bits.source, UInt<8>(0h0)) node requestBOI_uncommonBits_5 = bits(_requestBOI_uncommonBits_T_5, 7, 0) node _requestBOI_T_25 = shr(out[1].b.bits.source, 8) node _requestBOI_T_26 = eq(_requestBOI_T_25, UInt<1>(0h0)) node _requestBOI_T_27 = leq(UInt<1>(0h0), requestBOI_uncommonBits_5) node _requestBOI_T_28 = and(_requestBOI_T_26, _requestBOI_T_27) node _requestBOI_T_29 = leq(requestBOI_uncommonBits_5, UInt<8>(0hff)) node requestBOI_1_2 = and(_requestBOI_T_28, _requestBOI_T_29) node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0) node _requestDOI_T = shr(out[0].d.bits.source, 5) node _requestDOI_T_1 = eq(_requestDOI_T, UInt<4>(0h8)) node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f)) node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<2>(0h0)) node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 1, 0) node _requestDOI_T_5 = shr(out[0].d.bits.source, 2) node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<7>(0h48)) node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<2>(0h3)) node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9) node _requestDOI_uncommonBits_T_2 = or(out[0].d.bits.source, UInt<8>(0h0)) node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 7, 0) node _requestDOI_T_10 = shr(out[0].d.bits.source, 8) node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h0)) node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2) node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12) node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<8>(0hff)) node requestDOI_0_2 = and(_requestDOI_T_13, _requestDOI_T_14) node _requestDOI_uncommonBits_T_3 = or(out[1].d.bits.source, UInt<5>(0h0)) node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 4, 0) node _requestDOI_T_15 = shr(out[1].d.bits.source, 5) node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<4>(0h8)) node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3) node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17) node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<5>(0h1f)) node requestDOI_1_0 = and(_requestDOI_T_18, _requestDOI_T_19) node _requestDOI_uncommonBits_T_4 = or(out[1].d.bits.source, UInt<2>(0h0)) node requestDOI_uncommonBits_4 = bits(_requestDOI_uncommonBits_T_4, 1, 0) node _requestDOI_T_20 = shr(out[1].d.bits.source, 2) node _requestDOI_T_21 = eq(_requestDOI_T_20, UInt<7>(0h48)) node _requestDOI_T_22 = leq(UInt<1>(0h0), requestDOI_uncommonBits_4) node _requestDOI_T_23 = and(_requestDOI_T_21, _requestDOI_T_22) node _requestDOI_T_24 = leq(requestDOI_uncommonBits_4, UInt<2>(0h3)) node requestDOI_1_1 = and(_requestDOI_T_23, _requestDOI_T_24) node _requestDOI_uncommonBits_T_5 = or(out[1].d.bits.source, UInt<8>(0h0)) node requestDOI_uncommonBits_5 = bits(_requestDOI_uncommonBits_T_5, 7, 0) node _requestDOI_T_25 = shr(out[1].d.bits.source, 8) node _requestDOI_T_26 = eq(_requestDOI_T_25, UInt<1>(0h0)) node _requestDOI_T_27 = leq(UInt<1>(0h0), requestDOI_uncommonBits_5) node _requestDOI_T_28 = and(_requestDOI_T_26, _requestDOI_T_27) node _requestDOI_T_29 = leq(requestDOI_uncommonBits_5, UInt<8>(0hff)) node requestDOI_1_2 = and(_requestDOI_T_28, _requestDOI_T_29) node _requestEIO_uncommonBits_T = or(in[0].e.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 2, 0) node _requestEIO_T = shr(in[0].e.bits.sink, 3) node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0)) node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits) node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2) node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<3>(0h7)) node requestEIO_0_1 = and(_requestEIO_T_3, _requestEIO_T_4) node _requestEIO_uncommonBits_T_1 = or(in[1].e.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 2, 0) node _requestEIO_T_5 = shr(in[1].e.bits.sink, 3) node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0)) node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1) node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7) node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<3>(0h7)) node requestEIO_1_1 = and(_requestEIO_T_8, _requestEIO_T_9) node _requestEIO_uncommonBits_T_2 = or(in[2].e.bits.sink, UInt<3>(0h0)) node requestEIO_uncommonBits_2 = bits(_requestEIO_uncommonBits_T_2, 2, 0) node _requestEIO_T_10 = shr(in[2].e.bits.sink, 3) node _requestEIO_T_11 = eq(_requestEIO_T_10, UInt<1>(0h0)) node _requestEIO_T_12 = leq(UInt<1>(0h0), requestEIO_uncommonBits_2) node _requestEIO_T_13 = and(_requestEIO_T_11, _requestEIO_T_12) node _requestEIO_T_14 = leq(requestEIO_uncommonBits_2, UInt<3>(0h7)) node requestEIO_2_1 = and(_requestEIO_T_13, _requestEIO_T_14) node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) node beatsAI_decode = shr(_beatsAI_decode_T_2, 3) node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3) node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) node _beatsAI_decode_T_6 = dshl(UInt<12>(0hfff), in[2].a.bits.size) node _beatsAI_decode_T_7 = bits(_beatsAI_decode_T_6, 11, 0) node _beatsAI_decode_T_8 = not(_beatsAI_decode_T_7) node beatsAI_decode_2 = shr(_beatsAI_decode_T_8, 3) node _beatsAI_opdata_T_2 = bits(in[2].a.bits.opcode, 2, 2) node beatsAI_opdata_2 = eq(_beatsAI_opdata_T_2, UInt<1>(0h0)) node beatsAI_2 = mux(beatsAI_opdata_2, beatsAI_decode_2, UInt<1>(0h0)) node _beatsBO_decode_T = dshl(UInt<12>(0hfff), out[0].b.bits.size) node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) node beatsBO_decode = shr(_beatsBO_decode_T_2, 3) node _beatsBO_opdata_T = bits(out[0].b.bits.opcode, 2, 2) node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].b.bits.size) node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0) node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4) node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3) node _beatsBO_opdata_T_1 = bits(out[1].b.bits.opcode, 2, 2) node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0)) node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0)) node _beatsCI_decode_T = dshl(UInt<12>(0hfff), in[0].c.bits.size) node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) node beatsCI_decode = shr(_beatsCI_decode_T_2, 3) node beatsCI_opdata = bits(in[0].c.bits.opcode, 0, 0) node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].c.bits.size) node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3) node beatsCI_opdata_1 = bits(in[1].c.bits.opcode, 0, 0) node beatsCI_1 = mux(beatsCI_opdata_1, beatsCI_decode_1, UInt<1>(0h0)) node _beatsCI_decode_T_6 = dshl(UInt<12>(0hfff), in[2].c.bits.size) node _beatsCI_decode_T_7 = bits(_beatsCI_decode_T_6, 11, 0) node _beatsCI_decode_T_8 = not(_beatsCI_decode_T_7) node beatsCI_decode_2 = shr(_beatsCI_decode_T_8, 3) node beatsCI_opdata_2 = bits(in[2].c.bits.opcode, 0, 0) node beatsCI_2 = mux(UInt<1>(0h0), beatsCI_decode_2, UInt<1>(0h0)) node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) node beatsDO_decode = shr(_beatsDO_decode_T_2, 3) node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size) node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0) node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4) node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3) node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0) node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0)) wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered[0].bits, in[0].a.bits node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 connect portsAOI_filtered[1].bits, in[0].a.bits node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T) connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1 node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0)) node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1) wire _portsAOI_in_0_a_ready_WIRE : UInt<1> connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2 connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered_1[0].bits, in[1].a.bits node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 connect portsAOI_filtered_1[1].bits, in[1].a.bits node _portsAOI_filtered_1_valid_T_2 = or(requestAIO_1_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_1_valid_T_2) connect portsAOI_filtered_1[1].valid, _portsAOI_filtered_1_valid_T_3 node _portsAOI_in_1_a_ready_T = mux(requestAIO_1_0, portsAOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsAOI_in_1_a_ready_T_1 = mux(requestAIO_1_1, portsAOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsAOI_in_1_a_ready_T_2 = or(_portsAOI_in_1_a_ready_T, _portsAOI_in_1_a_ready_T_1) wire _portsAOI_in_1_a_ready_WIRE : UInt<1> connect _portsAOI_in_1_a_ready_WIRE, _portsAOI_in_1_a_ready_T_2 connect in[1].a.ready, _portsAOI_in_1_a_ready_WIRE wire portsAOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsAOI_filtered_2[0].bits, in[2].a.bits node _portsAOI_filtered_0_valid_T_4 = or(requestAIO_2_0, UInt<1>(0h0)) node _portsAOI_filtered_0_valid_T_5 = and(in[2].a.valid, _portsAOI_filtered_0_valid_T_4) connect portsAOI_filtered_2[0].valid, _portsAOI_filtered_0_valid_T_5 connect portsAOI_filtered_2[1].bits, in[2].a.bits node _portsAOI_filtered_1_valid_T_4 = or(requestAIO_2_1, UInt<1>(0h0)) node _portsAOI_filtered_1_valid_T_5 = and(in[2].a.valid, _portsAOI_filtered_1_valid_T_4) connect portsAOI_filtered_2[1].valid, _portsAOI_filtered_1_valid_T_5 node _portsAOI_in_2_a_ready_T = mux(requestAIO_2_0, portsAOI_filtered_2[0].ready, UInt<1>(0h0)) node _portsAOI_in_2_a_ready_T_1 = mux(requestAIO_2_1, portsAOI_filtered_2[1].ready, UInt<1>(0h0)) node _portsAOI_in_2_a_ready_T_2 = or(_portsAOI_in_2_a_ready_T, _portsAOI_in_2_a_ready_T_1) wire _portsAOI_in_2_a_ready_WIRE : UInt<1> connect _portsAOI_in_2_a_ready_WIRE, _portsAOI_in_2_a_ready_T_2 connect in[2].a.ready, _portsAOI_in_2_a_ready_WIRE wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[3] connect portsBIO_filtered[0].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[0].bits.data, out[0].b.bits.data connect portsBIO_filtered[0].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[0].bits.address, out[0].b.bits.address connect portsBIO_filtered[0].bits.source, out[0].b.bits.source connect portsBIO_filtered[0].bits.size, out[0].b.bits.size connect portsBIO_filtered[0].bits.param, out[0].b.bits.param connect portsBIO_filtered[0].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_0_valid_T) connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 connect portsBIO_filtered[1].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[1].bits.data, out[0].b.bits.data connect portsBIO_filtered[1].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[1].bits.address, out[0].b.bits.address connect portsBIO_filtered[1].bits.source, out[0].b.bits.source connect portsBIO_filtered[1].bits.size, out[0].b.bits.size connect portsBIO_filtered[1].bits.param, out[0].b.bits.param connect portsBIO_filtered[1].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_1_valid_T) connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 connect portsBIO_filtered[2].bits.corrupt, out[0].b.bits.corrupt connect portsBIO_filtered[2].bits.data, out[0].b.bits.data connect portsBIO_filtered[2].bits.mask, out[0].b.bits.mask connect portsBIO_filtered[2].bits.address, out[0].b.bits.address connect portsBIO_filtered[2].bits.source, out[0].b.bits.source connect portsBIO_filtered[2].bits.size, out[0].b.bits.size connect portsBIO_filtered[2].bits.param, out[0].b.bits.param connect portsBIO_filtered[2].bits.opcode, out[0].b.bits.opcode node _portsBIO_filtered_2_valid_T = or(requestBOI_0_2, UInt<1>(0h0)) node _portsBIO_filtered_2_valid_T_1 = and(out[0].b.valid, _portsBIO_filtered_2_valid_T) connect portsBIO_filtered[2].valid, _portsBIO_filtered_2_valid_T_1 node _portsBIO_out_0_b_ready_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_2 = mux(requestBOI_0_2, portsBIO_filtered[2].ready, UInt<1>(0h0)) node _portsBIO_out_0_b_ready_T_3 = or(_portsBIO_out_0_b_ready_T, _portsBIO_out_0_b_ready_T_1) node _portsBIO_out_0_b_ready_T_4 = or(_portsBIO_out_0_b_ready_T_3, _portsBIO_out_0_b_ready_T_2) wire _portsBIO_out_0_b_ready_WIRE : UInt<1> connect _portsBIO_out_0_b_ready_WIRE, _portsBIO_out_0_b_ready_T_4 connect out[0].b.ready, _portsBIO_out_0_b_ready_WIRE wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[3] connect portsBIO_filtered_1[0].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[0].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[0].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[0].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[0].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[0].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[0].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[0].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h0)) node _portsBIO_filtered_0_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_0_valid_T_2) connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3 connect portsBIO_filtered_1[1].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[1].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[1].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[1].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[1].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[1].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[1].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[1].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_1_valid_T_2 = or(requestBOI_1_1, UInt<1>(0h0)) node _portsBIO_filtered_1_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_1_valid_T_2) connect portsBIO_filtered_1[1].valid, _portsBIO_filtered_1_valid_T_3 connect portsBIO_filtered_1[2].bits.corrupt, out[1].b.bits.corrupt connect portsBIO_filtered_1[2].bits.data, out[1].b.bits.data connect portsBIO_filtered_1[2].bits.mask, out[1].b.bits.mask connect portsBIO_filtered_1[2].bits.address, out[1].b.bits.address connect portsBIO_filtered_1[2].bits.source, out[1].b.bits.source connect portsBIO_filtered_1[2].bits.size, out[1].b.bits.size connect portsBIO_filtered_1[2].bits.param, out[1].b.bits.param connect portsBIO_filtered_1[2].bits.opcode, out[1].b.bits.opcode node _portsBIO_filtered_2_valid_T_2 = or(requestBOI_1_2, UInt<1>(0h0)) node _portsBIO_filtered_2_valid_T_3 = and(out[1].b.valid, _portsBIO_filtered_2_valid_T_2) connect portsBIO_filtered_1[2].valid, _portsBIO_filtered_2_valid_T_3 node _portsBIO_out_1_b_ready_T = mux(requestBOI_1_0, portsBIO_filtered_1[0].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_1 = mux(requestBOI_1_1, portsBIO_filtered_1[1].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_2 = mux(requestBOI_1_2, portsBIO_filtered_1[2].ready, UInt<1>(0h0)) node _portsBIO_out_1_b_ready_T_3 = or(_portsBIO_out_1_b_ready_T, _portsBIO_out_1_b_ready_T_1) node _portsBIO_out_1_b_ready_T_4 = or(_portsBIO_out_1_b_ready_T_3, _portsBIO_out_1_b_ready_T_2) wire _portsBIO_out_1_b_ready_WIRE : UInt<1> connect _portsBIO_out_1_b_ready_WIRE, _portsBIO_out_1_b_ready_T_4 connect out[1].b.ready, _portsBIO_out_1_b_ready_WIRE wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered[0].bits, in[0].c.bits node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_0_valid_T) connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 connect portsCOI_filtered[1].bits, in[0].c.bits node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_1 = and(in[0].c.valid, _portsCOI_filtered_1_valid_T) connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1 node _portsCOI_in_0_c_ready_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0)) node _portsCOI_in_0_c_ready_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0)) node _portsCOI_in_0_c_ready_T_2 = or(_portsCOI_in_0_c_ready_T, _portsCOI_in_0_c_ready_T_1) wire _portsCOI_in_0_c_ready_WIRE : UInt<1> connect _portsCOI_in_0_c_ready_WIRE, _portsCOI_in_0_c_ready_T_2 connect in[0].c.ready, _portsCOI_in_0_c_ready_WIRE wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered_1[0].bits, in[1].c.bits node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_0_valid_T_2) connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 connect portsCOI_filtered_1[1].bits, in[1].c.bits node _portsCOI_filtered_1_valid_T_2 = or(requestCIO_1_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_3 = and(in[1].c.valid, _portsCOI_filtered_1_valid_T_2) connect portsCOI_filtered_1[1].valid, _portsCOI_filtered_1_valid_T_3 node _portsCOI_in_1_c_ready_T = mux(requestCIO_1_0, portsCOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsCOI_in_1_c_ready_T_1 = mux(requestCIO_1_1, portsCOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsCOI_in_1_c_ready_T_2 = or(_portsCOI_in_1_c_ready_T, _portsCOI_in_1_c_ready_T_1) wire _portsCOI_in_1_c_ready_WIRE : UInt<1> connect _portsCOI_in_1_c_ready_WIRE, _portsCOI_in_1_c_ready_T_2 connect in[1].c.ready, _portsCOI_in_1_c_ready_WIRE wire portsCOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2] connect portsCOI_filtered_2[0].bits, in[2].c.bits node _portsCOI_filtered_0_valid_T_4 = or(requestCIO_2_0, UInt<1>(0h0)) node _portsCOI_filtered_0_valid_T_5 = and(in[2].c.valid, _portsCOI_filtered_0_valid_T_4) connect portsCOI_filtered_2[0].valid, _portsCOI_filtered_0_valid_T_5 connect portsCOI_filtered_2[1].bits, in[2].c.bits node _portsCOI_filtered_1_valid_T_4 = or(requestCIO_2_1, UInt<1>(0h0)) node _portsCOI_filtered_1_valid_T_5 = and(in[2].c.valid, _portsCOI_filtered_1_valid_T_4) connect portsCOI_filtered_2[1].valid, _portsCOI_filtered_1_valid_T_5 node _portsCOI_in_2_c_ready_T = mux(requestCIO_2_0, portsCOI_filtered_2[0].ready, UInt<1>(0h0)) node _portsCOI_in_2_c_ready_T_1 = mux(requestCIO_2_1, portsCOI_filtered_2[1].ready, UInt<1>(0h0)) node _portsCOI_in_2_c_ready_T_2 = or(_portsCOI_in_2_c_ready_T, _portsCOI_in_2_c_ready_T_1) wire _portsCOI_in_2_c_ready_WIRE : UInt<1> connect _portsCOI_in_2_c_ready_WIRE, _portsCOI_in_2_c_ready_T_2 connect in[2].c.ready, _portsCOI_in_2_c_ready_WIRE wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[3] connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[0].bits.data, out[0].d.bits.data connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[0].bits.source, out[0].d.bits.source connect portsDIO_filtered[0].bits.size, out[0].d.bits.size connect portsDIO_filtered[0].bits.param, out[0].d.bits.param connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[1].bits.data, out[0].d.bits.data connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[1].bits.source, out[0].d.bits.source connect portsDIO_filtered[1].bits.size, out[0].d.bits.size connect portsDIO_filtered[1].bits.param, out[0].d.bits.param connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 connect portsDIO_filtered[2].bits.corrupt, out[0].d.bits.corrupt connect portsDIO_filtered[2].bits.data, out[0].d.bits.data connect portsDIO_filtered[2].bits.denied, out[0].d.bits.denied connect portsDIO_filtered[2].bits.sink, out[0].d.bits.sink connect portsDIO_filtered[2].bits.source, out[0].d.bits.source connect portsDIO_filtered[2].bits.size, out[0].d.bits.size connect portsDIO_filtered[2].bits.param, out[0].d.bits.param connect portsDIO_filtered[2].bits.opcode, out[0].d.bits.opcode node _portsDIO_filtered_2_valid_T = or(requestDOI_0_2, UInt<1>(0h0)) node _portsDIO_filtered_2_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_2_valid_T) connect portsDIO_filtered[2].valid, _portsDIO_filtered_2_valid_T_1 node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_2 = mux(requestDOI_0_2, portsDIO_filtered[2].ready, UInt<1>(0h0)) node _portsDIO_out_0_d_ready_T_3 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) node _portsDIO_out_0_d_ready_T_4 = or(_portsDIO_out_0_d_ready_T_3, _portsDIO_out_0_d_ready_T_2) wire _portsDIO_out_0_d_ready_WIRE : UInt<1> connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_4 connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[3] connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h0)) node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2) connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3 connect portsDIO_filtered_1[1].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[1].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[1].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[1].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[1].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[1].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[1].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[1].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_1_valid_T_2 = or(requestDOI_1_1, UInt<1>(0h0)) node _portsDIO_filtered_1_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_1_valid_T_2) connect portsDIO_filtered_1[1].valid, _portsDIO_filtered_1_valid_T_3 connect portsDIO_filtered_1[2].bits.corrupt, out[1].d.bits.corrupt connect portsDIO_filtered_1[2].bits.data, out[1].d.bits.data connect portsDIO_filtered_1[2].bits.denied, out[1].d.bits.denied connect portsDIO_filtered_1[2].bits.sink, out[1].d.bits.sink connect portsDIO_filtered_1[2].bits.source, out[1].d.bits.source connect portsDIO_filtered_1[2].bits.size, out[1].d.bits.size connect portsDIO_filtered_1[2].bits.param, out[1].d.bits.param connect portsDIO_filtered_1[2].bits.opcode, out[1].d.bits.opcode node _portsDIO_filtered_2_valid_T_2 = or(requestDOI_1_2, UInt<1>(0h0)) node _portsDIO_filtered_2_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_2_valid_T_2) connect portsDIO_filtered_1[2].valid, _portsDIO_filtered_2_valid_T_3 node _portsDIO_out_1_d_ready_T = mux(requestDOI_1_0, portsDIO_filtered_1[0].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_1 = mux(requestDOI_1_1, portsDIO_filtered_1[1].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_2 = mux(requestDOI_1_2, portsDIO_filtered_1[2].ready, UInt<1>(0h0)) node _portsDIO_out_1_d_ready_T_3 = or(_portsDIO_out_1_d_ready_T, _portsDIO_out_1_d_ready_T_1) node _portsDIO_out_1_d_ready_T_4 = or(_portsDIO_out_1_d_ready_T_3, _portsDIO_out_1_d_ready_T_2) wire _portsDIO_out_1_d_ready_WIRE : UInt<1> connect _portsDIO_out_1_d_ready_WIRE, _portsDIO_out_1_d_ready_T_4 connect out[1].d.ready, _portsDIO_out_1_d_ready_WIRE wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2] connect portsEOI_filtered[0].bits, in[0].e.bits node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_0_valid_T) connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 connect portsEOI_filtered[1].bits, in[0].e.bits node _portsEOI_filtered_1_valid_T = or(requestEIO_0_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_1 = and(in[0].e.valid, _portsEOI_filtered_1_valid_T) connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1 node _portsEOI_in_0_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0)) node _portsEOI_in_0_e_ready_T_1 = mux(requestEIO_0_1, portsEOI_filtered[1].ready, UInt<1>(0h0)) node _portsEOI_in_0_e_ready_T_2 = or(_portsEOI_in_0_e_ready_T, _portsEOI_in_0_e_ready_T_1) wire _portsEOI_in_0_e_ready_WIRE : UInt<1> connect _portsEOI_in_0_e_ready_WIRE, _portsEOI_in_0_e_ready_T_2 connect in[0].e.ready, _portsEOI_in_0_e_ready_WIRE wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2] connect portsEOI_filtered_1[0].bits, in[1].e.bits node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_0_valid_T_2) connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 connect portsEOI_filtered_1[1].bits, in[1].e.bits node _portsEOI_filtered_1_valid_T_2 = or(requestEIO_1_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_3 = and(in[1].e.valid, _portsEOI_filtered_1_valid_T_2) connect portsEOI_filtered_1[1].valid, _portsEOI_filtered_1_valid_T_3 node _portsEOI_in_1_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_1[0].ready, UInt<1>(0h0)) node _portsEOI_in_1_e_ready_T_1 = mux(requestEIO_1_1, portsEOI_filtered_1[1].ready, UInt<1>(0h0)) node _portsEOI_in_1_e_ready_T_2 = or(_portsEOI_in_1_e_ready_T, _portsEOI_in_1_e_ready_T_1) wire _portsEOI_in_1_e_ready_WIRE : UInt<1> connect _portsEOI_in_1_e_ready_WIRE, _portsEOI_in_1_e_ready_T_2 connect in[1].e.ready, _portsEOI_in_1_e_ready_WIRE wire portsEOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}[2] connect portsEOI_filtered_2[0].bits, in[2].e.bits node _portsEOI_filtered_0_valid_T_4 = or(UInt<1>(0h0), UInt<1>(0h0)) node _portsEOI_filtered_0_valid_T_5 = and(in[2].e.valid, _portsEOI_filtered_0_valid_T_4) connect portsEOI_filtered_2[0].valid, _portsEOI_filtered_0_valid_T_5 connect portsEOI_filtered_2[1].bits, in[2].e.bits node _portsEOI_filtered_1_valid_T_4 = or(requestEIO_2_1, UInt<1>(0h0)) node _portsEOI_filtered_1_valid_T_5 = and(in[2].e.valid, _portsEOI_filtered_1_valid_T_4) connect portsEOI_filtered_2[1].valid, _portsEOI_filtered_1_valid_T_5 node _portsEOI_in_2_e_ready_T = mux(UInt<1>(0h0), portsEOI_filtered_2[0].ready, UInt<1>(0h0)) node _portsEOI_in_2_e_ready_T_1 = mux(requestEIO_2_1, portsEOI_filtered_2[1].ready, UInt<1>(0h0)) node _portsEOI_in_2_e_ready_T_2 = or(_portsEOI_in_2_e_ready_T, _portsEOI_in_2_e_ready_T_1) wire _portsEOI_in_2_e_ready_WIRE : UInt<1> connect _portsEOI_in_2_e_ready_WIRE, _portsEOI_in_2_e_ready_T_2 connect in[2].e.ready, _portsEOI_in_2_e_ready_WIRE regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, out[0].a.ready) node readys_hi = cat(portsAOI_filtered_2[0].valid, portsAOI_filtered_1[0].valid) node _readys_T = cat(readys_hi, portsAOI_filtered[0].valid) node readys_valid = bits(_readys_T, 2, 0) node _readys_T_1 = eq(readys_valid, _readys_T) node _readys_T_2 = asUInt(reset) node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) when _readys_T_3 : node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) when _readys_T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert regreset readys_mask : UInt<3>, clock, reset, UInt<3>(0h7) node _readys_filter_T = not(readys_mask) node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) node readys_filter = cat(_readys_filter_T_1, readys_valid) node _readys_unready_T = shr(readys_filter, 1) node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) node _readys_unready_T_2 = shr(_readys_unready_T_1, 2) node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2) node _readys_unready_T_4 = bits(_readys_unready_T_3, 5, 0) node _readys_unready_T_5 = shr(_readys_unready_T_4, 1) node _readys_unready_T_6 = shl(readys_mask, 3) node readys_unready = or(_readys_unready_T_5, _readys_unready_T_6) node _readys_readys_T = shr(readys_unready, 3) node _readys_readys_T_1 = bits(readys_unready, 2, 0) node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) node readys_readys = not(_readys_readys_T_2) node _readys_T_5 = orr(readys_valid) node _readys_T_6 = and(latch, _readys_T_5) when _readys_T_6 : node _readys_mask_T = and(readys_readys, readys_valid) node _readys_mask_T_1 = shl(_readys_mask_T, 1) node _readys_mask_T_2 = bits(_readys_mask_T_1, 2, 0) node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) node _readys_mask_T_4 = shl(_readys_mask_T_3, 2) node _readys_mask_T_5 = bits(_readys_mask_T_4, 2, 0) node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5) node _readys_mask_T_7 = bits(_readys_mask_T_6, 2, 0) connect readys_mask, _readys_mask_T_7 node _readys_T_7 = bits(readys_readys, 2, 0) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) node _readys_T_10 = bits(_readys_T_7, 2, 2) wire readys : UInt<1>[3] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 connect readys[2], _readys_T_10 node _winner_T = and(readys[0], portsAOI_filtered[0].valid) node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) node _winner_T_2 = and(readys[2], portsAOI_filtered_2[0].valid) wire winner : UInt<1>[3] connect winner[0], _winner_T connect winner[1], _winner_T_1 connect winner[2], _winner_T_2 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node prefixOR_2 = or(prefixOR_1, winner[1]) node _prefixOR_T = or(prefixOR_2, winner[2]) node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = eq(winner[0], UInt<1>(0h0)) node _T_2 = or(_T, _T_1) node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) node _T_4 = eq(winner[1], UInt<1>(0h0)) node _T_5 = or(_T_3, _T_4) node _T_6 = eq(prefixOR_2, UInt<1>(0h0)) node _T_7 = eq(winner[2], UInt<1>(0h0)) node _T_8 = or(_T_6, _T_7) node _T_9 = and(_T_2, _T_5) node _T_10 = and(_T_9, _T_8) node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : node _T_13 = eq(_T_10, UInt<1>(0h0)) when _T_13 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_10, UInt<1>(0h1), "") : assert node _T_14 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _T_15 = or(_T_14, portsAOI_filtered_2[0].valid) node _T_16 = eq(_T_15, UInt<1>(0h0)) node _T_17 = or(winner[0], winner[1]) node _T_18 = or(_T_17, winner[2]) node _T_19 = or(_T_16, _T_18) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_19, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) node maskedBeats_2 = mux(winner[2], beatsAI_2, UInt<1>(0h0)) node _initBeats_T = or(maskedBeats_0, maskedBeats_1) node initBeats = or(_initBeats_T, maskedBeats_2) node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[3] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) connect _state_WIRE[2], UInt<1>(0h0) regreset state : UInt<1>[3], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) connect portsAOI_filtered[0].ready, _filtered_0_ready_T node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 node _filtered_0_ready_T_2 = and(out[0].a.ready, allowed[2]) connect portsAOI_filtered_2[0].ready, _filtered_0_ready_T_2 node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) node _out_0_a_valid_T_1 = or(_out_0_a_valid_T, portsAOI_filtered_2[0].valid) node _out_0_a_valid_T_2 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_3 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_4 = mux(state[2], portsAOI_filtered_2[0].valid, UInt<1>(0h0)) node _out_0_a_valid_T_5 = or(_out_0_a_valid_T_2, _out_0_a_valid_T_3) node _out_0_a_valid_T_6 = or(_out_0_a_valid_T_5, _out_0_a_valid_T_4) wire _out_0_a_valid_WIRE : UInt<1> connect _out_0_a_valid_WIRE, _out_0_a_valid_T_6 node _out_0_a_valid_T_7 = mux(idle, _out_0_a_valid_T_1, _out_0_a_valid_WIRE) connect out[0].a.valid, _out_0_a_valid_T_7 wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_2 = mux(muxState[2], portsAOI_filtered_2[0].bits.corrupt, UInt<1>(0h0)) node _out_0_a_bits_T_3 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) node _out_0_a_bits_T_4 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_2) wire _out_0_a_bits_WIRE_1 : UInt<1> connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_4 connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 node _out_0_a_bits_T_5 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_6 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_7 = mux(muxState[2], portsAOI_filtered_2[0].bits.data, UInt<1>(0h0)) node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_5, _out_0_a_bits_T_6) node _out_0_a_bits_T_9 = or(_out_0_a_bits_T_8, _out_0_a_bits_T_7) wire _out_0_a_bits_WIRE_2 : UInt<64> connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_9 connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 node _out_0_a_bits_T_10 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_11 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_12 = mux(muxState[2], portsAOI_filtered_2[0].bits.mask, UInt<1>(0h0)) node _out_0_a_bits_T_13 = or(_out_0_a_bits_T_10, _out_0_a_bits_T_11) node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_13, _out_0_a_bits_T_12) wire _out_0_a_bits_WIRE_3 : UInt<8> connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_14 connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 wire _out_0_a_bits_WIRE_4 : { } connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 wire _out_0_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}} wire _out_0_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>} node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.fetch, UInt<1>(0h0)) node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.fetch, UInt<1>(0h0)) node _out_0_a_bits_T_17 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.fetch, UInt<1>(0h0)) node _out_0_a_bits_T_18 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) node _out_0_a_bits_T_19 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_17) wire _out_0_a_bits_WIRE_7 : UInt<1> connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_19 connect _out_0_a_bits_WIRE_6.fetch, _out_0_a_bits_WIRE_7 node _out_0_a_bits_T_20 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.secure, UInt<1>(0h0)) node _out_0_a_bits_T_21 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.secure, UInt<1>(0h0)) node _out_0_a_bits_T_22 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.secure, UInt<1>(0h0)) node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_20, _out_0_a_bits_T_21) node _out_0_a_bits_T_24 = or(_out_0_a_bits_T_23, _out_0_a_bits_T_22) wire _out_0_a_bits_WIRE_8 : UInt<1> connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_24 connect _out_0_a_bits_WIRE_6.secure, _out_0_a_bits_WIRE_8 node _out_0_a_bits_T_25 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.privileged, UInt<1>(0h0)) node _out_0_a_bits_T_26 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.privileged, UInt<1>(0h0)) node _out_0_a_bits_T_27 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.privileged, UInt<1>(0h0)) node _out_0_a_bits_T_28 = or(_out_0_a_bits_T_25, _out_0_a_bits_T_26) node _out_0_a_bits_T_29 = or(_out_0_a_bits_T_28, _out_0_a_bits_T_27) wire _out_0_a_bits_WIRE_9 : UInt<1> connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_29 connect _out_0_a_bits_WIRE_6.privileged, _out_0_a_bits_WIRE_9 node _out_0_a_bits_T_30 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.writealloc, UInt<1>(0h0)) node _out_0_a_bits_T_31 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.writealloc, UInt<1>(0h0)) node _out_0_a_bits_T_32 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.writealloc, UInt<1>(0h0)) node _out_0_a_bits_T_33 = or(_out_0_a_bits_T_30, _out_0_a_bits_T_31) node _out_0_a_bits_T_34 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_32) wire _out_0_a_bits_WIRE_10 : UInt<1> connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_34 connect _out_0_a_bits_WIRE_6.writealloc, _out_0_a_bits_WIRE_10 node _out_0_a_bits_T_35 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.readalloc, UInt<1>(0h0)) node _out_0_a_bits_T_36 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.readalloc, UInt<1>(0h0)) node _out_0_a_bits_T_37 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.readalloc, UInt<1>(0h0)) node _out_0_a_bits_T_38 = or(_out_0_a_bits_T_35, _out_0_a_bits_T_36) node _out_0_a_bits_T_39 = or(_out_0_a_bits_T_38, _out_0_a_bits_T_37) wire _out_0_a_bits_WIRE_11 : UInt<1> connect _out_0_a_bits_WIRE_11, _out_0_a_bits_T_39 connect _out_0_a_bits_WIRE_6.readalloc, _out_0_a_bits_WIRE_11 node _out_0_a_bits_T_40 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.modifiable, UInt<1>(0h0)) node _out_0_a_bits_T_41 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.modifiable, UInt<1>(0h0)) node _out_0_a_bits_T_42 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.modifiable, UInt<1>(0h0)) node _out_0_a_bits_T_43 = or(_out_0_a_bits_T_40, _out_0_a_bits_T_41) node _out_0_a_bits_T_44 = or(_out_0_a_bits_T_43, _out_0_a_bits_T_42) wire _out_0_a_bits_WIRE_12 : UInt<1> connect _out_0_a_bits_WIRE_12, _out_0_a_bits_T_44 connect _out_0_a_bits_WIRE_6.modifiable, _out_0_a_bits_WIRE_12 node _out_0_a_bits_T_45 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.bufferable, UInt<1>(0h0)) node _out_0_a_bits_T_46 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.bufferable, UInt<1>(0h0)) node _out_0_a_bits_T_47 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.bufferable, UInt<1>(0h0)) node _out_0_a_bits_T_48 = or(_out_0_a_bits_T_45, _out_0_a_bits_T_46) node _out_0_a_bits_T_49 = or(_out_0_a_bits_T_48, _out_0_a_bits_T_47) wire _out_0_a_bits_WIRE_13 : UInt<1> connect _out_0_a_bits_WIRE_13, _out_0_a_bits_T_49 connect _out_0_a_bits_WIRE_6.bufferable, _out_0_a_bits_WIRE_13 connect _out_0_a_bits_WIRE_5.amba_prot, _out_0_a_bits_WIRE_6 connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 node _out_0_a_bits_T_50 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_51 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_52 = mux(muxState[2], portsAOI_filtered_2[0].bits.address, UInt<1>(0h0)) node _out_0_a_bits_T_53 = or(_out_0_a_bits_T_50, _out_0_a_bits_T_51) node _out_0_a_bits_T_54 = or(_out_0_a_bits_T_53, _out_0_a_bits_T_52) wire _out_0_a_bits_WIRE_14 : UInt<32> connect _out_0_a_bits_WIRE_14, _out_0_a_bits_T_54 connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_14 node _out_0_a_bits_T_55 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_56 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_57 = mux(muxState[2], portsAOI_filtered_2[0].bits.source, UInt<1>(0h0)) node _out_0_a_bits_T_58 = or(_out_0_a_bits_T_55, _out_0_a_bits_T_56) node _out_0_a_bits_T_59 = or(_out_0_a_bits_T_58, _out_0_a_bits_T_57) wire _out_0_a_bits_WIRE_15 : UInt<9> connect _out_0_a_bits_WIRE_15, _out_0_a_bits_T_59 connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_15 node _out_0_a_bits_T_60 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_61 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_62 = mux(muxState[2], portsAOI_filtered_2[0].bits.size, UInt<1>(0h0)) node _out_0_a_bits_T_63 = or(_out_0_a_bits_T_60, _out_0_a_bits_T_61) node _out_0_a_bits_T_64 = or(_out_0_a_bits_T_63, _out_0_a_bits_T_62) wire _out_0_a_bits_WIRE_16 : UInt<4> connect _out_0_a_bits_WIRE_16, _out_0_a_bits_T_64 connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_16 node _out_0_a_bits_T_65 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_66 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_67 = mux(muxState[2], portsAOI_filtered_2[0].bits.param, UInt<1>(0h0)) node _out_0_a_bits_T_68 = or(_out_0_a_bits_T_65, _out_0_a_bits_T_66) node _out_0_a_bits_T_69 = or(_out_0_a_bits_T_68, _out_0_a_bits_T_67) wire _out_0_a_bits_WIRE_17 : UInt<3> connect _out_0_a_bits_WIRE_17, _out_0_a_bits_T_69 connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_17 node _out_0_a_bits_T_70 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_71 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_72 = mux(muxState[2], portsAOI_filtered_2[0].bits.opcode, UInt<1>(0h0)) node _out_0_a_bits_T_73 = or(_out_0_a_bits_T_70, _out_0_a_bits_T_71) node _out_0_a_bits_T_74 = or(_out_0_a_bits_T_73, _out_0_a_bits_T_72) wire _out_0_a_bits_WIRE_18 : UInt<3> connect _out_0_a_bits_WIRE_18, _out_0_a_bits_T_74 connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_18 connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt connect out[0].a.bits.data, _out_0_a_bits_WIRE.data connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask connect out[0].a.bits.user.amba_prot.fetch, _out_0_a_bits_WIRE.user.amba_prot.fetch connect out[0].a.bits.user.amba_prot.secure, _out_0_a_bits_WIRE.user.amba_prot.secure connect out[0].a.bits.user.amba_prot.privileged, _out_0_a_bits_WIRE.user.amba_prot.privileged connect out[0].a.bits.user.amba_prot.writealloc, _out_0_a_bits_WIRE.user.amba_prot.writealloc connect out[0].a.bits.user.amba_prot.readalloc, _out_0_a_bits_WIRE.user.amba_prot.readalloc connect out[0].a.bits.user.amba_prot.modifiable, _out_0_a_bits_WIRE.user.amba_prot.modifiable connect out[0].a.bits.user.amba_prot.bufferable, _out_0_a_bits_WIRE.user.amba_prot.bufferable connect out[0].a.bits.address, _out_0_a_bits_WIRE.address connect out[0].a.bits.source, _out_0_a_bits_WIRE.source connect out[0].a.bits.size, _out_0_a_bits_WIRE.size connect out[0].a.bits.param, _out_0_a_bits_WIRE.param connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode invalidate out[0].c.bits.corrupt invalidate out[0].c.bits.data invalidate out[0].c.bits.user.amba_prot.fetch invalidate out[0].c.bits.user.amba_prot.secure invalidate out[0].c.bits.user.amba_prot.privileged invalidate out[0].c.bits.user.amba_prot.writealloc invalidate out[0].c.bits.user.amba_prot.readalloc invalidate out[0].c.bits.user.amba_prot.modifiable invalidate out[0].c.bits.user.amba_prot.bufferable invalidate out[0].c.bits.address invalidate out[0].c.bits.source invalidate out[0].c.bits.size invalidate out[0].c.bits.param invalidate out[0].c.bits.opcode invalidate out[0].e.bits.sink connect portsCOI_filtered[0].ready, UInt<1>(0h0) connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) connect portsCOI_filtered_2[0].ready, UInt<1>(0h0) connect portsEOI_filtered[0].ready, UInt<1>(0h0) connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) connect portsEOI_filtered_2[0].ready, UInt<1>(0h0) regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0) node idle_1 = eq(beatsLeft_1, UInt<1>(0h0)) node latch_1 = and(idle_1, out[1].a.ready) node readys_hi_1 = cat(portsAOI_filtered_2[1].valid, portsAOI_filtered_1[1].valid) node _readys_T_11 = cat(readys_hi_1, portsAOI_filtered[1].valid) node readys_valid_1 = bits(_readys_T_11, 2, 0) node _readys_T_12 = eq(readys_valid_1, _readys_T_11) node _readys_T_13 = asUInt(reset) node _readys_T_14 = eq(_readys_T_13, UInt<1>(0h0)) when _readys_T_14 : node _readys_T_15 = eq(_readys_T_12, UInt<1>(0h0)) when _readys_T_15 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_1 assert(clock, _readys_T_12, UInt<1>(0h1), "") : readys_assert_1 regreset readys_mask_1 : UInt<3>, clock, reset, UInt<3>(0h7) node _readys_filter_T_2 = not(readys_mask_1) node _readys_filter_T_3 = and(readys_valid_1, _readys_filter_T_2) node readys_filter_1 = cat(_readys_filter_T_3, readys_valid_1) node _readys_unready_T_7 = shr(readys_filter_1, 1) node _readys_unready_T_8 = or(readys_filter_1, _readys_unready_T_7) node _readys_unready_T_9 = shr(_readys_unready_T_8, 2) node _readys_unready_T_10 = or(_readys_unready_T_8, _readys_unready_T_9) node _readys_unready_T_11 = bits(_readys_unready_T_10, 5, 0) node _readys_unready_T_12 = shr(_readys_unready_T_11, 1) node _readys_unready_T_13 = shl(readys_mask_1, 3) node readys_unready_1 = or(_readys_unready_T_12, _readys_unready_T_13) node _readys_readys_T_3 = shr(readys_unready_1, 3) node _readys_readys_T_4 = bits(readys_unready_1, 2, 0) node _readys_readys_T_5 = and(_readys_readys_T_3, _readys_readys_T_4) node readys_readys_1 = not(_readys_readys_T_5) node _readys_T_16 = orr(readys_valid_1) node _readys_T_17 = and(latch_1, _readys_T_16) when _readys_T_17 : node _readys_mask_T_8 = and(readys_readys_1, readys_valid_1) node _readys_mask_T_9 = shl(_readys_mask_T_8, 1) node _readys_mask_T_10 = bits(_readys_mask_T_9, 2, 0) node _readys_mask_T_11 = or(_readys_mask_T_8, _readys_mask_T_10) node _readys_mask_T_12 = shl(_readys_mask_T_11, 2) node _readys_mask_T_13 = bits(_readys_mask_T_12, 2, 0) node _readys_mask_T_14 = or(_readys_mask_T_11, _readys_mask_T_13) node _readys_mask_T_15 = bits(_readys_mask_T_14, 2, 0) connect readys_mask_1, _readys_mask_T_15 node _readys_T_18 = bits(readys_readys_1, 2, 0) node _readys_T_19 = bits(_readys_T_18, 0, 0) node _readys_T_20 = bits(_readys_T_18, 1, 1) node _readys_T_21 = bits(_readys_T_18, 2, 2) wire readys_1 : UInt<1>[3] connect readys_1[0], _readys_T_19 connect readys_1[1], _readys_T_20 connect readys_1[2], _readys_T_21 node _winner_T_3 = and(readys_1[0], portsAOI_filtered[1].valid) node _winner_T_4 = and(readys_1[1], portsAOI_filtered_1[1].valid) node _winner_T_5 = and(readys_1[2], portsAOI_filtered_2[1].valid) wire winner_1 : UInt<1>[3] connect winner_1[0], _winner_T_3 connect winner_1[1], _winner_T_4 connect winner_1[2], _winner_T_5 node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0]) node prefixOR_2_1 = or(prefixOR_1_1, winner_1[1]) node _prefixOR_T_1 = or(prefixOR_2_1, winner_1[2]) node _T_23 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_24 = eq(winner_1[0], UInt<1>(0h0)) node _T_25 = or(_T_23, _T_24) node _T_26 = eq(prefixOR_1_1, UInt<1>(0h0)) node _T_27 = eq(winner_1[1], UInt<1>(0h0)) node _T_28 = or(_T_26, _T_27) node _T_29 = eq(prefixOR_2_1, UInt<1>(0h0)) node _T_30 = eq(winner_1[2], UInt<1>(0h0)) node _T_31 = or(_T_29, _T_30) node _T_32 = and(_T_25, _T_28) node _T_33 = and(_T_32, _T_31) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid) node _T_38 = or(_T_37, portsAOI_filtered_2[1].valid) node _T_39 = eq(_T_38, UInt<1>(0h0)) node _T_40 = or(winner_1[0], winner_1[1]) node _T_41 = or(_T_40, winner_1[2]) node _T_42 = or(_T_39, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_3 assert(clock, _T_42, UInt<1>(0h1), "") : assert_3 node maskedBeats_0_1 = mux(winner_1[0], beatsAI_0, UInt<1>(0h0)) node maskedBeats_1_1 = mux(winner_1[1], beatsAI_1, UInt<1>(0h0)) node maskedBeats_2_1 = mux(winner_1[2], beatsAI_2, UInt<1>(0h0)) node _initBeats_T_1 = or(maskedBeats_0_1, maskedBeats_1_1) node initBeats_1 = or(_initBeats_T_1, maskedBeats_2_1) node _beatsLeft_T_4 = and(out[1].a.ready, out[1].a.valid) node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4) node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1) node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6) connect beatsLeft_1, _beatsLeft_T_7 wire _state_WIRE_1 : UInt<1>[3] connect _state_WIRE_1[0], UInt<1>(0h0) connect _state_WIRE_1[1], UInt<1>(0h0) connect _state_WIRE_1[2], UInt<1>(0h0) regreset state_1 : UInt<1>[3], clock, reset, _state_WIRE_1 node muxState_1 = mux(idle_1, winner_1, state_1) connect state_1, muxState_1 node allowed_1 = mux(idle_1, readys_1, state_1) node _filtered_1_ready_T = and(out[1].a.ready, allowed_1[0]) connect portsAOI_filtered[1].ready, _filtered_1_ready_T node _filtered_1_ready_T_1 = and(out[1].a.ready, allowed_1[1]) connect portsAOI_filtered_1[1].ready, _filtered_1_ready_T_1 node _filtered_1_ready_T_2 = and(out[1].a.ready, allowed_1[2]) connect portsAOI_filtered_2[1].ready, _filtered_1_ready_T_2 node _out_1_a_valid_T = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid) node _out_1_a_valid_T_1 = or(_out_1_a_valid_T, portsAOI_filtered_2[1].valid) node _out_1_a_valid_T_2 = mux(state_1[0], portsAOI_filtered[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_3 = mux(state_1[1], portsAOI_filtered_1[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_4 = mux(state_1[2], portsAOI_filtered_2[1].valid, UInt<1>(0h0)) node _out_1_a_valid_T_5 = or(_out_1_a_valid_T_2, _out_1_a_valid_T_3) node _out_1_a_valid_T_6 = or(_out_1_a_valid_T_5, _out_1_a_valid_T_4) wire _out_1_a_valid_WIRE : UInt<1> connect _out_1_a_valid_WIRE, _out_1_a_valid_T_6 node _out_1_a_valid_T_7 = mux(idle_1, _out_1_a_valid_T_1, _out_1_a_valid_WIRE) connect out[1].a.valid, _out_1_a_valid_T_7 wire _out_1_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<9>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _out_1_a_bits_T = mux(muxState_1[0], portsAOI_filtered[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_1 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_2 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.corrupt, UInt<1>(0h0)) node _out_1_a_bits_T_3 = or(_out_1_a_bits_T, _out_1_a_bits_T_1) node _out_1_a_bits_T_4 = or(_out_1_a_bits_T_3, _out_1_a_bits_T_2) wire _out_1_a_bits_WIRE_1 : UInt<1> connect _out_1_a_bits_WIRE_1, _out_1_a_bits_T_4 connect _out_1_a_bits_WIRE.corrupt, _out_1_a_bits_WIRE_1 node _out_1_a_bits_T_5 = mux(muxState_1[0], portsAOI_filtered[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_6 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_7 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.data, UInt<1>(0h0)) node _out_1_a_bits_T_8 = or(_out_1_a_bits_T_5, _out_1_a_bits_T_6) node _out_1_a_bits_T_9 = or(_out_1_a_bits_T_8, _out_1_a_bits_T_7) wire _out_1_a_bits_WIRE_2 : UInt<64> connect _out_1_a_bits_WIRE_2, _out_1_a_bits_T_9 connect _out_1_a_bits_WIRE.data, _out_1_a_bits_WIRE_2 node _out_1_a_bits_T_10 = mux(muxState_1[0], portsAOI_filtered[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_11 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_12 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.mask, UInt<1>(0h0)) node _out_1_a_bits_T_13 = or(_out_1_a_bits_T_10, _out_1_a_bits_T_11) node _out_1_a_bits_T_14 = or(_out_1_a_bits_T_13, _out_1_a_bits_T_12) wire _out_1_a_bits_WIRE_3 : UInt<8> connect _out_1_a_bits_WIRE_3, _out_1_a_bits_T_14 connect _out_1_a_bits_WIRE.mask, _out_1_a_bits_WIRE_3 wire _out_1_a_bits_WIRE_4 : { } connect _out_1_a_bits_WIRE.echo, _out_1_a_bits_WIRE_4 wire _out_1_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}} wire _out_1_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>} node _out_1_a_bits_T_15 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.fetch, UInt<1>(0h0)) node _out_1_a_bits_T_16 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.fetch, UInt<1>(0h0)) node _out_1_a_bits_T_17 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.user.amba_prot.fetch, UInt<1>(0h0)) node _out_1_a_bits_T_18 = or(_out_1_a_bits_T_15, _out_1_a_bits_T_16) node _out_1_a_bits_T_19 = or(_out_1_a_bits_T_18, _out_1_a_bits_T_17) wire _out_1_a_bits_WIRE_7 : UInt<1> connect _out_1_a_bits_WIRE_7, _out_1_a_bits_T_19 connect _out_1_a_bits_WIRE_6.fetch, _out_1_a_bits_WIRE_7 node _out_1_a_bits_T_20 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.secure, UInt<1>(0h0)) node _out_1_a_bits_T_21 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.secure, UInt<1>(0h0)) node _out_1_a_bits_T_22 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.user.amba_prot.secure, UInt<1>(0h0)) node _out_1_a_bits_T_23 = or(_out_1_a_bits_T_20, _out_1_a_bits_T_21) node _out_1_a_bits_T_24 = or(_out_1_a_bits_T_23, _out_1_a_bits_T_22) wire _out_1_a_bits_WIRE_8 : UInt<1> connect _out_1_a_bits_WIRE_8, _out_1_a_bits_T_24 connect _out_1_a_bits_WIRE_6.secure, _out_1_a_bits_WIRE_8 node _out_1_a_bits_T_25 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.privileged, UInt<1>(0h0)) node _out_1_a_bits_T_26 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.privileged, UInt<1>(0h0)) node _out_1_a_bits_T_27 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.user.amba_prot.privileged, UInt<1>(0h0)) node _out_1_a_bits_T_28 = or(_out_1_a_bits_T_25, _out_1_a_bits_T_26) node _out_1_a_bits_T_29 = or(_out_1_a_bits_T_28, _out_1_a_bits_T_27) wire _out_1_a_bits_WIRE_9 : UInt<1> connect _out_1_a_bits_WIRE_9, _out_1_a_bits_T_29 connect _out_1_a_bits_WIRE_6.privileged, _out_1_a_bits_WIRE_9 node _out_1_a_bits_T_30 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.writealloc, UInt<1>(0h0)) node _out_1_a_bits_T_31 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.writealloc, UInt<1>(0h0)) node _out_1_a_bits_T_32 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.user.amba_prot.writealloc, UInt<1>(0h0)) node _out_1_a_bits_T_33 = or(_out_1_a_bits_T_30, _out_1_a_bits_T_31) node _out_1_a_bits_T_34 = or(_out_1_a_bits_T_33, _out_1_a_bits_T_32) wire _out_1_a_bits_WIRE_10 : UInt<1> connect _out_1_a_bits_WIRE_10, _out_1_a_bits_T_34 connect _out_1_a_bits_WIRE_6.writealloc, _out_1_a_bits_WIRE_10 node _out_1_a_bits_T_35 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.readalloc, UInt<1>(0h0)) node _out_1_a_bits_T_36 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.readalloc, UInt<1>(0h0)) node _out_1_a_bits_T_37 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.user.amba_prot.readalloc, UInt<1>(0h0)) node _out_1_a_bits_T_38 = or(_out_1_a_bits_T_35, _out_1_a_bits_T_36) node _out_1_a_bits_T_39 = or(_out_1_a_bits_T_38, _out_1_a_bits_T_37) wire _out_1_a_bits_WIRE_11 : UInt<1> connect _out_1_a_bits_WIRE_11, _out_1_a_bits_T_39 connect _out_1_a_bits_WIRE_6.readalloc, _out_1_a_bits_WIRE_11 node _out_1_a_bits_T_40 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.modifiable, UInt<1>(0h0)) node _out_1_a_bits_T_41 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.modifiable, UInt<1>(0h0)) node _out_1_a_bits_T_42 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.user.amba_prot.modifiable, UInt<1>(0h0)) node _out_1_a_bits_T_43 = or(_out_1_a_bits_T_40, _out_1_a_bits_T_41) node _out_1_a_bits_T_44 = or(_out_1_a_bits_T_43, _out_1_a_bits_T_42) wire _out_1_a_bits_WIRE_12 : UInt<1> connect _out_1_a_bits_WIRE_12, _out_1_a_bits_T_44 connect _out_1_a_bits_WIRE_6.modifiable, _out_1_a_bits_WIRE_12 node _out_1_a_bits_T_45 = mux(muxState_1[0], portsAOI_filtered[1].bits.user.amba_prot.bufferable, UInt<1>(0h0)) node _out_1_a_bits_T_46 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.user.amba_prot.bufferable, UInt<1>(0h0)) node _out_1_a_bits_T_47 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.user.amba_prot.bufferable, UInt<1>(0h0)) node _out_1_a_bits_T_48 = or(_out_1_a_bits_T_45, _out_1_a_bits_T_46) node _out_1_a_bits_T_49 = or(_out_1_a_bits_T_48, _out_1_a_bits_T_47) wire _out_1_a_bits_WIRE_13 : UInt<1> connect _out_1_a_bits_WIRE_13, _out_1_a_bits_T_49 connect _out_1_a_bits_WIRE_6.bufferable, _out_1_a_bits_WIRE_13 connect _out_1_a_bits_WIRE_5.amba_prot, _out_1_a_bits_WIRE_6 connect _out_1_a_bits_WIRE.user, _out_1_a_bits_WIRE_5 node _out_1_a_bits_T_50 = mux(muxState_1[0], portsAOI_filtered[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_51 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_52 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.address, UInt<1>(0h0)) node _out_1_a_bits_T_53 = or(_out_1_a_bits_T_50, _out_1_a_bits_T_51) node _out_1_a_bits_T_54 = or(_out_1_a_bits_T_53, _out_1_a_bits_T_52) wire _out_1_a_bits_WIRE_14 : UInt<32> connect _out_1_a_bits_WIRE_14, _out_1_a_bits_T_54 connect _out_1_a_bits_WIRE.address, _out_1_a_bits_WIRE_14 node _out_1_a_bits_T_55 = mux(muxState_1[0], portsAOI_filtered[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_56 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_57 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.source, UInt<1>(0h0)) node _out_1_a_bits_T_58 = or(_out_1_a_bits_T_55, _out_1_a_bits_T_56) node _out_1_a_bits_T_59 = or(_out_1_a_bits_T_58, _out_1_a_bits_T_57) wire _out_1_a_bits_WIRE_15 : UInt<9> connect _out_1_a_bits_WIRE_15, _out_1_a_bits_T_59 connect _out_1_a_bits_WIRE.source, _out_1_a_bits_WIRE_15 node _out_1_a_bits_T_60 = mux(muxState_1[0], portsAOI_filtered[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_61 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_62 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.size, UInt<1>(0h0)) node _out_1_a_bits_T_63 = or(_out_1_a_bits_T_60, _out_1_a_bits_T_61) node _out_1_a_bits_T_64 = or(_out_1_a_bits_T_63, _out_1_a_bits_T_62) wire _out_1_a_bits_WIRE_16 : UInt<4> connect _out_1_a_bits_WIRE_16, _out_1_a_bits_T_64 connect _out_1_a_bits_WIRE.size, _out_1_a_bits_WIRE_16 node _out_1_a_bits_T_65 = mux(muxState_1[0], portsAOI_filtered[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_66 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_67 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.param, UInt<1>(0h0)) node _out_1_a_bits_T_68 = or(_out_1_a_bits_T_65, _out_1_a_bits_T_66) node _out_1_a_bits_T_69 = or(_out_1_a_bits_T_68, _out_1_a_bits_T_67) wire _out_1_a_bits_WIRE_17 : UInt<3> connect _out_1_a_bits_WIRE_17, _out_1_a_bits_T_69 connect _out_1_a_bits_WIRE.param, _out_1_a_bits_WIRE_17 node _out_1_a_bits_T_70 = mux(muxState_1[0], portsAOI_filtered[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_71 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_72 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.opcode, UInt<1>(0h0)) node _out_1_a_bits_T_73 = or(_out_1_a_bits_T_70, _out_1_a_bits_T_71) node _out_1_a_bits_T_74 = or(_out_1_a_bits_T_73, _out_1_a_bits_T_72) wire _out_1_a_bits_WIRE_18 : UInt<3> connect _out_1_a_bits_WIRE_18, _out_1_a_bits_T_74 connect _out_1_a_bits_WIRE.opcode, _out_1_a_bits_WIRE_18 connect out[1].a.bits.corrupt, _out_1_a_bits_WIRE.corrupt connect out[1].a.bits.data, _out_1_a_bits_WIRE.data connect out[1].a.bits.mask, _out_1_a_bits_WIRE.mask connect out[1].a.bits.user.amba_prot.fetch, _out_1_a_bits_WIRE.user.amba_prot.fetch connect out[1].a.bits.user.amba_prot.secure, _out_1_a_bits_WIRE.user.amba_prot.secure connect out[1].a.bits.user.amba_prot.privileged, _out_1_a_bits_WIRE.user.amba_prot.privileged connect out[1].a.bits.user.amba_prot.writealloc, _out_1_a_bits_WIRE.user.amba_prot.writealloc connect out[1].a.bits.user.amba_prot.readalloc, _out_1_a_bits_WIRE.user.amba_prot.readalloc connect out[1].a.bits.user.amba_prot.modifiable, _out_1_a_bits_WIRE.user.amba_prot.modifiable connect out[1].a.bits.user.amba_prot.bufferable, _out_1_a_bits_WIRE.user.amba_prot.bufferable connect out[1].a.bits.address, _out_1_a_bits_WIRE.address connect out[1].a.bits.source, _out_1_a_bits_WIRE.source connect out[1].a.bits.size, _out_1_a_bits_WIRE.size connect out[1].a.bits.param, _out_1_a_bits_WIRE.param connect out[1].a.bits.opcode, _out_1_a_bits_WIRE.opcode connect out[1].c, portsCOI_filtered_1[1] connect out[1].e, portsEOI_filtered_1[1] connect portsCOI_filtered[1].ready, UInt<1>(0h0) connect portsCOI_filtered_2[1].ready, UInt<1>(0h0) connect portsEOI_filtered[1].ready, UInt<1>(0h0) connect portsEOI_filtered_2[1].ready, UInt<1>(0h0) invalidate in[0].b.bits.corrupt invalidate in[0].b.bits.data invalidate in[0].b.bits.mask invalidate in[0].b.bits.address invalidate in[0].b.bits.source invalidate in[0].b.bits.size invalidate in[0].b.bits.param invalidate in[0].b.bits.opcode regreset beatsLeft_2 : UInt, clock, reset, UInt<1>(0h0) node idle_2 = eq(beatsLeft_2, UInt<1>(0h0)) node latch_2 = and(idle_2, in[0].d.ready) node _readys_T_22 = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid) node readys_valid_2 = bits(_readys_T_22, 1, 0) node _readys_T_23 = eq(readys_valid_2, _readys_T_22) node _readys_T_24 = asUInt(reset) node _readys_T_25 = eq(_readys_T_24, UInt<1>(0h0)) when _readys_T_25 : node _readys_T_26 = eq(_readys_T_23, UInt<1>(0h0)) when _readys_T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_2 assert(clock, _readys_T_23, UInt<1>(0h1), "") : readys_assert_2 regreset readys_mask_2 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_4 = not(readys_mask_2) node _readys_filter_T_5 = and(readys_valid_2, _readys_filter_T_4) node readys_filter_2 = cat(_readys_filter_T_5, readys_valid_2) node _readys_unready_T_14 = shr(readys_filter_2, 1) node _readys_unready_T_15 = or(readys_filter_2, _readys_unready_T_14) node _readys_unready_T_16 = bits(_readys_unready_T_15, 3, 0) node _readys_unready_T_17 = shr(_readys_unready_T_16, 1) node _readys_unready_T_18 = shl(readys_mask_2, 2) node readys_unready_2 = or(_readys_unready_T_17, _readys_unready_T_18) node _readys_readys_T_6 = shr(readys_unready_2, 2) node _readys_readys_T_7 = bits(readys_unready_2, 1, 0) node _readys_readys_T_8 = and(_readys_readys_T_6, _readys_readys_T_7) node readys_readys_2 = not(_readys_readys_T_8) node _readys_T_27 = orr(readys_valid_2) node _readys_T_28 = and(latch_2, _readys_T_27) when _readys_T_28 : node _readys_mask_T_16 = and(readys_readys_2, readys_valid_2) node _readys_mask_T_17 = shl(_readys_mask_T_16, 1) node _readys_mask_T_18 = bits(_readys_mask_T_17, 1, 0) node _readys_mask_T_19 = or(_readys_mask_T_16, _readys_mask_T_18) node _readys_mask_T_20 = bits(_readys_mask_T_19, 1, 0) connect readys_mask_2, _readys_mask_T_20 node _readys_T_29 = bits(readys_readys_2, 1, 0) node _readys_T_30 = bits(_readys_T_29, 0, 0) node _readys_T_31 = bits(_readys_T_29, 1, 1) wire readys_2 : UInt<1>[2] connect readys_2[0], _readys_T_30 connect readys_2[1], _readys_T_31 node _winner_T_6 = and(readys_2[0], portsDIO_filtered[0].valid) node _winner_T_7 = and(readys_2[1], portsDIO_filtered_1[0].valid) wire winner_2 : UInt<1>[2] connect winner_2[0], _winner_T_6 connect winner_2[1], _winner_T_7 node prefixOR_1_2 = or(UInt<1>(0h0), winner_2[0]) node _prefixOR_T_2 = or(prefixOR_1_2, winner_2[1]) node _T_46 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_47 = eq(winner_2[0], UInt<1>(0h0)) node _T_48 = or(_T_46, _T_47) node _T_49 = eq(prefixOR_1_2, UInt<1>(0h0)) node _T_50 = eq(winner_2[1], UInt<1>(0h0)) node _T_51 = or(_T_49, _T_50) node _T_52 = and(_T_48, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_4 assert(clock, _T_52, UInt<1>(0h1), "") : assert_4 node _T_56 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = or(winner_2[0], winner_2[1]) node _T_59 = or(_T_57, _T_58) node _T_60 = asUInt(reset) node _T_61 = eq(_T_60, UInt<1>(0h0)) when _T_61 : node _T_62 = eq(_T_59, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_5 assert(clock, _T_59, UInt<1>(0h1), "") : assert_5 node maskedBeats_0_2 = mux(winner_2[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_2 = mux(winner_2[1], beatsDO_1, UInt<1>(0h0)) node initBeats_2 = or(maskedBeats_0_2, maskedBeats_1_2) node _beatsLeft_T_8 = and(in[0].d.ready, in[0].d.valid) node _beatsLeft_T_9 = sub(beatsLeft_2, _beatsLeft_T_8) node _beatsLeft_T_10 = tail(_beatsLeft_T_9, 1) node _beatsLeft_T_11 = mux(latch_2, initBeats_2, _beatsLeft_T_10) connect beatsLeft_2, _beatsLeft_T_11 wire _state_WIRE_2 : UInt<1>[2] connect _state_WIRE_2[0], UInt<1>(0h0) connect _state_WIRE_2[1], UInt<1>(0h0) regreset state_2 : UInt<1>[2], clock, reset, _state_WIRE_2 node muxState_2 = mux(idle_2, winner_2, state_2) connect state_2, muxState_2 node allowed_2 = mux(idle_2, readys_2, state_2) node _filtered_0_ready_T_3 = and(in[0].d.ready, allowed_2[0]) connect portsDIO_filtered[0].ready, _filtered_0_ready_T_3 node _filtered_0_ready_T_4 = and(in[0].d.ready, allowed_2[1]) connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_4 node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid) node _in_0_d_valid_T_1 = mux(state_2[0], portsDIO_filtered[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_2 = mux(state_2[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0)) node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2) wire _in_0_d_valid_WIRE : UInt<1> connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3 node _in_0_d_valid_T_4 = mux(idle_2, _in_0_d_valid_T, _in_0_d_valid_WIRE) connect in[0].d.valid, _in_0_d_valid_T_4 wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_0_d_bits_T = mux(muxState_2[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_1 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0)) node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1) wire _in_0_d_bits_WIRE_1 : UInt<1> connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2 connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1 node _in_0_d_bits_T_3 = mux(muxState_2[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_4 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0)) node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4) wire _in_0_d_bits_WIRE_2 : UInt<64> connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5 connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2 wire _in_0_d_bits_WIRE_3 : { } connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3 wire _in_0_d_bits_WIRE_4 : { } connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4 node _in_0_d_bits_T_6 = mux(muxState_2[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_7 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0)) node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7) wire _in_0_d_bits_WIRE_5 : UInt<1> connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8 connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5 node _in_0_d_bits_T_9 = mux(muxState_2[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_10 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0)) node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10) wire _in_0_d_bits_WIRE_6 : UInt<3> connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11 connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6 node _in_0_d_bits_T_12 = mux(muxState_2[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_13 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0)) node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13) wire _in_0_d_bits_WIRE_7 : UInt<9> connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14 connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7 node _in_0_d_bits_T_15 = mux(muxState_2[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_16 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0)) node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16) wire _in_0_d_bits_WIRE_8 : UInt<4> connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17 connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8 node _in_0_d_bits_T_18 = mux(muxState_2[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_19 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0)) node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19) wire _in_0_d_bits_WIRE_9 : UInt<2> connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20 connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9 node _in_0_d_bits_T_21 = mux(muxState_2[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_22 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0)) node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22) wire _in_0_d_bits_WIRE_10 : UInt<3> connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23 connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10 connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt connect in[0].d.bits.data, _in_0_d_bits_WIRE.data connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink connect in[0].d.bits.source, _in_0_d_bits_WIRE.source connect in[0].d.bits.size, _in_0_d_bits_WIRE.size connect in[0].d.bits.param, _in_0_d_bits_WIRE.param connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode connect portsBIO_filtered[0].ready, UInt<1>(0h0) connect portsBIO_filtered_1[0].ready, UInt<1>(0h0) connect in[1].b, portsBIO_filtered_1[1] regreset beatsLeft_3 : UInt, clock, reset, UInt<1>(0h0) node idle_3 = eq(beatsLeft_3, UInt<1>(0h0)) node latch_3 = and(idle_3, in[1].d.ready) node _readys_T_32 = cat(portsDIO_filtered_1[1].valid, portsDIO_filtered[1].valid) node readys_valid_3 = bits(_readys_T_32, 1, 0) node _readys_T_33 = eq(readys_valid_3, _readys_T_32) node _readys_T_34 = asUInt(reset) node _readys_T_35 = eq(_readys_T_34, UInt<1>(0h0)) when _readys_T_35 : node _readys_T_36 = eq(_readys_T_33, UInt<1>(0h0)) when _readys_T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_3 assert(clock, _readys_T_33, UInt<1>(0h1), "") : readys_assert_3 regreset readys_mask_3 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_6 = not(readys_mask_3) node _readys_filter_T_7 = and(readys_valid_3, _readys_filter_T_6) node readys_filter_3 = cat(_readys_filter_T_7, readys_valid_3) node _readys_unready_T_19 = shr(readys_filter_3, 1) node _readys_unready_T_20 = or(readys_filter_3, _readys_unready_T_19) node _readys_unready_T_21 = bits(_readys_unready_T_20, 3, 0) node _readys_unready_T_22 = shr(_readys_unready_T_21, 1) node _readys_unready_T_23 = shl(readys_mask_3, 2) node readys_unready_3 = or(_readys_unready_T_22, _readys_unready_T_23) node _readys_readys_T_9 = shr(readys_unready_3, 2) node _readys_readys_T_10 = bits(readys_unready_3, 1, 0) node _readys_readys_T_11 = and(_readys_readys_T_9, _readys_readys_T_10) node readys_readys_3 = not(_readys_readys_T_11) node _readys_T_37 = orr(readys_valid_3) node _readys_T_38 = and(latch_3, _readys_T_37) when _readys_T_38 : node _readys_mask_T_21 = and(readys_readys_3, readys_valid_3) node _readys_mask_T_22 = shl(_readys_mask_T_21, 1) node _readys_mask_T_23 = bits(_readys_mask_T_22, 1, 0) node _readys_mask_T_24 = or(_readys_mask_T_21, _readys_mask_T_23) node _readys_mask_T_25 = bits(_readys_mask_T_24, 1, 0) connect readys_mask_3, _readys_mask_T_25 node _readys_T_39 = bits(readys_readys_3, 1, 0) node _readys_T_40 = bits(_readys_T_39, 0, 0) node _readys_T_41 = bits(_readys_T_39, 1, 1) wire readys_3 : UInt<1>[2] connect readys_3[0], _readys_T_40 connect readys_3[1], _readys_T_41 node _winner_T_8 = and(readys_3[0], portsDIO_filtered[1].valid) node _winner_T_9 = and(readys_3[1], portsDIO_filtered_1[1].valid) wire winner_3 : UInt<1>[2] connect winner_3[0], _winner_T_8 connect winner_3[1], _winner_T_9 node prefixOR_1_3 = or(UInt<1>(0h0), winner_3[0]) node _prefixOR_T_3 = or(prefixOR_1_3, winner_3[1]) node _T_63 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_64 = eq(winner_3[0], UInt<1>(0h0)) node _T_65 = or(_T_63, _T_64) node _T_66 = eq(prefixOR_1_3, UInt<1>(0h0)) node _T_67 = eq(winner_3[1], UInt<1>(0h0)) node _T_68 = or(_T_66, _T_67) node _T_69 = and(_T_65, _T_68) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_6 assert(clock, _T_69, UInt<1>(0h1), "") : assert_6 node _T_73 = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = or(winner_3[0], winner_3[1]) node _T_76 = or(_T_74, _T_75) node _T_77 = asUInt(reset) node _T_78 = eq(_T_77, UInt<1>(0h0)) when _T_78 : node _T_79 = eq(_T_76, UInt<1>(0h0)) when _T_79 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_7 assert(clock, _T_76, UInt<1>(0h1), "") : assert_7 node maskedBeats_0_3 = mux(winner_3[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_3 = mux(winner_3[1], beatsDO_1, UInt<1>(0h0)) node initBeats_3 = or(maskedBeats_0_3, maskedBeats_1_3) node _beatsLeft_T_12 = and(in[1].d.ready, in[1].d.valid) node _beatsLeft_T_13 = sub(beatsLeft_3, _beatsLeft_T_12) node _beatsLeft_T_14 = tail(_beatsLeft_T_13, 1) node _beatsLeft_T_15 = mux(latch_3, initBeats_3, _beatsLeft_T_14) connect beatsLeft_3, _beatsLeft_T_15 wire _state_WIRE_3 : UInt<1>[2] connect _state_WIRE_3[0], UInt<1>(0h0) connect _state_WIRE_3[1], UInt<1>(0h0) regreset state_3 : UInt<1>[2], clock, reset, _state_WIRE_3 node muxState_3 = mux(idle_3, winner_3, state_3) connect state_3, muxState_3 node allowed_3 = mux(idle_3, readys_3, state_3) node _filtered_1_ready_T_3 = and(in[1].d.ready, allowed_3[0]) connect portsDIO_filtered[1].ready, _filtered_1_ready_T_3 node _filtered_1_ready_T_4 = and(in[1].d.ready, allowed_3[1]) connect portsDIO_filtered_1[1].ready, _filtered_1_ready_T_4 node _in_1_d_valid_T = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid) node _in_1_d_valid_T_1 = mux(state_3[0], portsDIO_filtered[1].valid, UInt<1>(0h0)) node _in_1_d_valid_T_2 = mux(state_3[1], portsDIO_filtered_1[1].valid, UInt<1>(0h0)) node _in_1_d_valid_T_3 = or(_in_1_d_valid_T_1, _in_1_d_valid_T_2) wire _in_1_d_valid_WIRE : UInt<1> connect _in_1_d_valid_WIRE, _in_1_d_valid_T_3 node _in_1_d_valid_T_4 = mux(idle_3, _in_1_d_valid_T, _in_1_d_valid_WIRE) connect in[1].d.valid, _in_1_d_valid_T_4 wire _in_1_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_1_d_bits_T = mux(muxState_3[0], portsDIO_filtered[1].bits.corrupt, UInt<1>(0h0)) node _in_1_d_bits_T_1 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.corrupt, UInt<1>(0h0)) node _in_1_d_bits_T_2 = or(_in_1_d_bits_T, _in_1_d_bits_T_1) wire _in_1_d_bits_WIRE_1 : UInt<1> connect _in_1_d_bits_WIRE_1, _in_1_d_bits_T_2 connect _in_1_d_bits_WIRE.corrupt, _in_1_d_bits_WIRE_1 node _in_1_d_bits_T_3 = mux(muxState_3[0], portsDIO_filtered[1].bits.data, UInt<1>(0h0)) node _in_1_d_bits_T_4 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.data, UInt<1>(0h0)) node _in_1_d_bits_T_5 = or(_in_1_d_bits_T_3, _in_1_d_bits_T_4) wire _in_1_d_bits_WIRE_2 : UInt<64> connect _in_1_d_bits_WIRE_2, _in_1_d_bits_T_5 connect _in_1_d_bits_WIRE.data, _in_1_d_bits_WIRE_2 wire _in_1_d_bits_WIRE_3 : { } connect _in_1_d_bits_WIRE.echo, _in_1_d_bits_WIRE_3 wire _in_1_d_bits_WIRE_4 : { } connect _in_1_d_bits_WIRE.user, _in_1_d_bits_WIRE_4 node _in_1_d_bits_T_6 = mux(muxState_3[0], portsDIO_filtered[1].bits.denied, UInt<1>(0h0)) node _in_1_d_bits_T_7 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.denied, UInt<1>(0h0)) node _in_1_d_bits_T_8 = or(_in_1_d_bits_T_6, _in_1_d_bits_T_7) wire _in_1_d_bits_WIRE_5 : UInt<1> connect _in_1_d_bits_WIRE_5, _in_1_d_bits_T_8 connect _in_1_d_bits_WIRE.denied, _in_1_d_bits_WIRE_5 node _in_1_d_bits_T_9 = mux(muxState_3[0], portsDIO_filtered[1].bits.sink, UInt<1>(0h0)) node _in_1_d_bits_T_10 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.sink, UInt<1>(0h0)) node _in_1_d_bits_T_11 = or(_in_1_d_bits_T_9, _in_1_d_bits_T_10) wire _in_1_d_bits_WIRE_6 : UInt<3> connect _in_1_d_bits_WIRE_6, _in_1_d_bits_T_11 connect _in_1_d_bits_WIRE.sink, _in_1_d_bits_WIRE_6 node _in_1_d_bits_T_12 = mux(muxState_3[0], portsDIO_filtered[1].bits.source, UInt<1>(0h0)) node _in_1_d_bits_T_13 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.source, UInt<1>(0h0)) node _in_1_d_bits_T_14 = or(_in_1_d_bits_T_12, _in_1_d_bits_T_13) wire _in_1_d_bits_WIRE_7 : UInt<9> connect _in_1_d_bits_WIRE_7, _in_1_d_bits_T_14 connect _in_1_d_bits_WIRE.source, _in_1_d_bits_WIRE_7 node _in_1_d_bits_T_15 = mux(muxState_3[0], portsDIO_filtered[1].bits.size, UInt<1>(0h0)) node _in_1_d_bits_T_16 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.size, UInt<1>(0h0)) node _in_1_d_bits_T_17 = or(_in_1_d_bits_T_15, _in_1_d_bits_T_16) wire _in_1_d_bits_WIRE_8 : UInt<4> connect _in_1_d_bits_WIRE_8, _in_1_d_bits_T_17 connect _in_1_d_bits_WIRE.size, _in_1_d_bits_WIRE_8 node _in_1_d_bits_T_18 = mux(muxState_3[0], portsDIO_filtered[1].bits.param, UInt<1>(0h0)) node _in_1_d_bits_T_19 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.param, UInt<1>(0h0)) node _in_1_d_bits_T_20 = or(_in_1_d_bits_T_18, _in_1_d_bits_T_19) wire _in_1_d_bits_WIRE_9 : UInt<2> connect _in_1_d_bits_WIRE_9, _in_1_d_bits_T_20 connect _in_1_d_bits_WIRE.param, _in_1_d_bits_WIRE_9 node _in_1_d_bits_T_21 = mux(muxState_3[0], portsDIO_filtered[1].bits.opcode, UInt<1>(0h0)) node _in_1_d_bits_T_22 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.opcode, UInt<1>(0h0)) node _in_1_d_bits_T_23 = or(_in_1_d_bits_T_21, _in_1_d_bits_T_22) wire _in_1_d_bits_WIRE_10 : UInt<3> connect _in_1_d_bits_WIRE_10, _in_1_d_bits_T_23 connect _in_1_d_bits_WIRE.opcode, _in_1_d_bits_WIRE_10 connect in[1].d.bits.corrupt, _in_1_d_bits_WIRE.corrupt connect in[1].d.bits.data, _in_1_d_bits_WIRE.data connect in[1].d.bits.denied, _in_1_d_bits_WIRE.denied connect in[1].d.bits.sink, _in_1_d_bits_WIRE.sink connect in[1].d.bits.source, _in_1_d_bits_WIRE.source connect in[1].d.bits.size, _in_1_d_bits_WIRE.size connect in[1].d.bits.param, _in_1_d_bits_WIRE.param connect in[1].d.bits.opcode, _in_1_d_bits_WIRE.opcode connect portsBIO_filtered[1].ready, UInt<1>(0h0) invalidate in[2].b.bits.corrupt invalidate in[2].b.bits.data invalidate in[2].b.bits.mask invalidate in[2].b.bits.address invalidate in[2].b.bits.source invalidate in[2].b.bits.size invalidate in[2].b.bits.param invalidate in[2].b.bits.opcode regreset beatsLeft_4 : UInt, clock, reset, UInt<1>(0h0) node idle_4 = eq(beatsLeft_4, UInt<1>(0h0)) node latch_4 = and(idle_4, in[2].d.ready) node _readys_T_42 = cat(portsDIO_filtered_1[2].valid, portsDIO_filtered[2].valid) node readys_valid_4 = bits(_readys_T_42, 1, 0) node _readys_T_43 = eq(readys_valid_4, _readys_T_42) node _readys_T_44 = asUInt(reset) node _readys_T_45 = eq(_readys_T_44, UInt<1>(0h0)) when _readys_T_45 : node _readys_T_46 = eq(_readys_T_43, UInt<1>(0h0)) when _readys_T_46 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_4 assert(clock, _readys_T_43, UInt<1>(0h1), "") : readys_assert_4 regreset readys_mask_4 : UInt<2>, clock, reset, UInt<2>(0h3) node _readys_filter_T_8 = not(readys_mask_4) node _readys_filter_T_9 = and(readys_valid_4, _readys_filter_T_8) node readys_filter_4 = cat(_readys_filter_T_9, readys_valid_4) node _readys_unready_T_24 = shr(readys_filter_4, 1) node _readys_unready_T_25 = or(readys_filter_4, _readys_unready_T_24) node _readys_unready_T_26 = bits(_readys_unready_T_25, 3, 0) node _readys_unready_T_27 = shr(_readys_unready_T_26, 1) node _readys_unready_T_28 = shl(readys_mask_4, 2) node readys_unready_4 = or(_readys_unready_T_27, _readys_unready_T_28) node _readys_readys_T_12 = shr(readys_unready_4, 2) node _readys_readys_T_13 = bits(readys_unready_4, 1, 0) node _readys_readys_T_14 = and(_readys_readys_T_12, _readys_readys_T_13) node readys_readys_4 = not(_readys_readys_T_14) node _readys_T_47 = orr(readys_valid_4) node _readys_T_48 = and(latch_4, _readys_T_47) when _readys_T_48 : node _readys_mask_T_26 = and(readys_readys_4, readys_valid_4) node _readys_mask_T_27 = shl(_readys_mask_T_26, 1) node _readys_mask_T_28 = bits(_readys_mask_T_27, 1, 0) node _readys_mask_T_29 = or(_readys_mask_T_26, _readys_mask_T_28) node _readys_mask_T_30 = bits(_readys_mask_T_29, 1, 0) connect readys_mask_4, _readys_mask_T_30 node _readys_T_49 = bits(readys_readys_4, 1, 0) node _readys_T_50 = bits(_readys_T_49, 0, 0) node _readys_T_51 = bits(_readys_T_49, 1, 1) wire readys_4 : UInt<1>[2] connect readys_4[0], _readys_T_50 connect readys_4[1], _readys_T_51 node _winner_T_10 = and(readys_4[0], portsDIO_filtered[2].valid) node _winner_T_11 = and(readys_4[1], portsDIO_filtered_1[2].valid) wire winner_4 : UInt<1>[2] connect winner_4[0], _winner_T_10 connect winner_4[1], _winner_T_11 node prefixOR_1_4 = or(UInt<1>(0h0), winner_4[0]) node _prefixOR_T_4 = or(prefixOR_1_4, winner_4[1]) node _T_80 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_81 = eq(winner_4[0], UInt<1>(0h0)) node _T_82 = or(_T_80, _T_81) node _T_83 = eq(prefixOR_1_4, UInt<1>(0h0)) node _T_84 = eq(winner_4[1], UInt<1>(0h0)) node _T_85 = or(_T_83, _T_84) node _T_86 = and(_T_82, _T_85) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf_8 assert(clock, _T_86, UInt<1>(0h1), "") : assert_8 node _T_90 = or(portsDIO_filtered[2].valid, portsDIO_filtered_1[2].valid) node _T_91 = eq(_T_90, UInt<1>(0h0)) node _T_92 = or(winner_4[0], winner_4[1]) node _T_93 = or(_T_91, _T_92) node _T_94 = asUInt(reset) node _T_95 = eq(_T_94, UInt<1>(0h0)) when _T_95 : node _T_96 = eq(_T_93, UInt<1>(0h0)) when _T_96 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_9 assert(clock, _T_93, UInt<1>(0h1), "") : assert_9 node maskedBeats_0_4 = mux(winner_4[0], beatsDO_0, UInt<1>(0h0)) node maskedBeats_1_4 = mux(winner_4[1], beatsDO_1, UInt<1>(0h0)) node initBeats_4 = or(maskedBeats_0_4, maskedBeats_1_4) node _beatsLeft_T_16 = and(in[2].d.ready, in[2].d.valid) node _beatsLeft_T_17 = sub(beatsLeft_4, _beatsLeft_T_16) node _beatsLeft_T_18 = tail(_beatsLeft_T_17, 1) node _beatsLeft_T_19 = mux(latch_4, initBeats_4, _beatsLeft_T_18) connect beatsLeft_4, _beatsLeft_T_19 wire _state_WIRE_4 : UInt<1>[2] connect _state_WIRE_4[0], UInt<1>(0h0) connect _state_WIRE_4[1], UInt<1>(0h0) regreset state_4 : UInt<1>[2], clock, reset, _state_WIRE_4 node muxState_4 = mux(idle_4, winner_4, state_4) connect state_4, muxState_4 node allowed_4 = mux(idle_4, readys_4, state_4) node _filtered_2_ready_T = and(in[2].d.ready, allowed_4[0]) connect portsDIO_filtered[2].ready, _filtered_2_ready_T node _filtered_2_ready_T_1 = and(in[2].d.ready, allowed_4[1]) connect portsDIO_filtered_1[2].ready, _filtered_2_ready_T_1 node _in_2_d_valid_T = or(portsDIO_filtered[2].valid, portsDIO_filtered_1[2].valid) node _in_2_d_valid_T_1 = mux(state_4[0], portsDIO_filtered[2].valid, UInt<1>(0h0)) node _in_2_d_valid_T_2 = mux(state_4[1], portsDIO_filtered_1[2].valid, UInt<1>(0h0)) node _in_2_d_valid_T_3 = or(_in_2_d_valid_T_1, _in_2_d_valid_T_2) wire _in_2_d_valid_WIRE : UInt<1> connect _in_2_d_valid_WIRE, _in_2_d_valid_T_3 node _in_2_d_valid_T_4 = mux(idle_4, _in_2_d_valid_T, _in_2_d_valid_WIRE) connect in[2].d.valid, _in_2_d_valid_T_4 wire _in_2_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<9>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} node _in_2_d_bits_T = mux(muxState_4[0], portsDIO_filtered[2].bits.corrupt, UInt<1>(0h0)) node _in_2_d_bits_T_1 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.corrupt, UInt<1>(0h0)) node _in_2_d_bits_T_2 = or(_in_2_d_bits_T, _in_2_d_bits_T_1) wire _in_2_d_bits_WIRE_1 : UInt<1> connect _in_2_d_bits_WIRE_1, _in_2_d_bits_T_2 connect _in_2_d_bits_WIRE.corrupt, _in_2_d_bits_WIRE_1 node _in_2_d_bits_T_3 = mux(muxState_4[0], portsDIO_filtered[2].bits.data, UInt<1>(0h0)) node _in_2_d_bits_T_4 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.data, UInt<1>(0h0)) node _in_2_d_bits_T_5 = or(_in_2_d_bits_T_3, _in_2_d_bits_T_4) wire _in_2_d_bits_WIRE_2 : UInt<64> connect _in_2_d_bits_WIRE_2, _in_2_d_bits_T_5 connect _in_2_d_bits_WIRE.data, _in_2_d_bits_WIRE_2 wire _in_2_d_bits_WIRE_3 : { } connect _in_2_d_bits_WIRE.echo, _in_2_d_bits_WIRE_3 wire _in_2_d_bits_WIRE_4 : { } connect _in_2_d_bits_WIRE.user, _in_2_d_bits_WIRE_4 node _in_2_d_bits_T_6 = mux(muxState_4[0], portsDIO_filtered[2].bits.denied, UInt<1>(0h0)) node _in_2_d_bits_T_7 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.denied, UInt<1>(0h0)) node _in_2_d_bits_T_8 = or(_in_2_d_bits_T_6, _in_2_d_bits_T_7) wire _in_2_d_bits_WIRE_5 : UInt<1> connect _in_2_d_bits_WIRE_5, _in_2_d_bits_T_8 connect _in_2_d_bits_WIRE.denied, _in_2_d_bits_WIRE_5 node _in_2_d_bits_T_9 = mux(muxState_4[0], portsDIO_filtered[2].bits.sink, UInt<1>(0h0)) node _in_2_d_bits_T_10 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.sink, UInt<1>(0h0)) node _in_2_d_bits_T_11 = or(_in_2_d_bits_T_9, _in_2_d_bits_T_10) wire _in_2_d_bits_WIRE_6 : UInt<3> connect _in_2_d_bits_WIRE_6, _in_2_d_bits_T_11 connect _in_2_d_bits_WIRE.sink, _in_2_d_bits_WIRE_6 node _in_2_d_bits_T_12 = mux(muxState_4[0], portsDIO_filtered[2].bits.source, UInt<1>(0h0)) node _in_2_d_bits_T_13 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.source, UInt<1>(0h0)) node _in_2_d_bits_T_14 = or(_in_2_d_bits_T_12, _in_2_d_bits_T_13) wire _in_2_d_bits_WIRE_7 : UInt<9> connect _in_2_d_bits_WIRE_7, _in_2_d_bits_T_14 connect _in_2_d_bits_WIRE.source, _in_2_d_bits_WIRE_7 node _in_2_d_bits_T_15 = mux(muxState_4[0], portsDIO_filtered[2].bits.size, UInt<1>(0h0)) node _in_2_d_bits_T_16 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.size, UInt<1>(0h0)) node _in_2_d_bits_T_17 = or(_in_2_d_bits_T_15, _in_2_d_bits_T_16) wire _in_2_d_bits_WIRE_8 : UInt<4> connect _in_2_d_bits_WIRE_8, _in_2_d_bits_T_17 connect _in_2_d_bits_WIRE.size, _in_2_d_bits_WIRE_8 node _in_2_d_bits_T_18 = mux(muxState_4[0], portsDIO_filtered[2].bits.param, UInt<1>(0h0)) node _in_2_d_bits_T_19 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.param, UInt<1>(0h0)) node _in_2_d_bits_T_20 = or(_in_2_d_bits_T_18, _in_2_d_bits_T_19) wire _in_2_d_bits_WIRE_9 : UInt<2> connect _in_2_d_bits_WIRE_9, _in_2_d_bits_T_20 connect _in_2_d_bits_WIRE.param, _in_2_d_bits_WIRE_9 node _in_2_d_bits_T_21 = mux(muxState_4[0], portsDIO_filtered[2].bits.opcode, UInt<1>(0h0)) node _in_2_d_bits_T_22 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.opcode, UInt<1>(0h0)) node _in_2_d_bits_T_23 = or(_in_2_d_bits_T_21, _in_2_d_bits_T_22) wire _in_2_d_bits_WIRE_10 : UInt<3> connect _in_2_d_bits_WIRE_10, _in_2_d_bits_T_23 connect _in_2_d_bits_WIRE.opcode, _in_2_d_bits_WIRE_10 connect in[2].d.bits.corrupt, _in_2_d_bits_WIRE.corrupt connect in[2].d.bits.data, _in_2_d_bits_WIRE.data connect in[2].d.bits.denied, _in_2_d_bits_WIRE.denied connect in[2].d.bits.sink, _in_2_d_bits_WIRE.sink connect in[2].d.bits.source, _in_2_d_bits_WIRE.source connect in[2].d.bits.size, _in_2_d_bits_WIRE.size connect in[2].d.bits.param, _in_2_d_bits_WIRE.param connect in[2].d.bits.opcode, _in_2_d_bits_WIRE.opcode connect portsBIO_filtered[2].ready, UInt<1>(0h0) connect portsBIO_filtered_1[2].ready, UInt<1>(0h0) extmodule plusarg_reader_6 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_7 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLXbar_sbus_i3_o2_a32d64s9k3z4c( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_b_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_b_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_c_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_b_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_c_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_anon_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [8:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [8:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire allowed_4_1; // @[Arbiter.scala:92:24] wire allowed_4_0; // @[Arbiter.scala:92:24] wire allowed_3_1; // @[Arbiter.scala:92:24] wire allowed_3_0; // @[Arbiter.scala:92:24] wire allowed_2_1; // @[Arbiter.scala:92:24] wire allowed_2_0; // @[Arbiter.scala:92:24] wire allowed_1_2; // @[Arbiter.scala:92:24] wire allowed_1_1; // @[Arbiter.scala:92:24] wire allowed_1_0; // @[Arbiter.scala:92:24] wire allowed_2; // @[Arbiter.scala:92:24] wire allowed_1; // @[Arbiter.scala:92:24] wire allowed_0; // @[Arbiter.scala:92:24] wire [8:0] in_0_a_bits_source = {4'h8, auto_anon_in_0_a_bits_source}; // @[Xbar.scala:166:55] wire [8:0] in_1_a_bits_source = {7'h48, auto_anon_in_1_a_bits_source}; // @[Xbar.scala:166:55] wire [8:0] in_2_a_bits_source = {1'h0, auto_anon_in_2_a_bits_source}; // @[Xbar.scala:166:29] wire [2:0] out_0_d_bits_sink = {2'h0, auto_anon_out_0_d_bits_sink}; // @[Xbar.scala:74:9, :251:28] wire [3:0] out_1_d_bits_size = {1'h0, auto_anon_out_1_d_bits_size}; // @[Xbar.scala:250:29] wire requestAIO_0_0 = {auto_anon_in_0_a_bits_address[31], auto_anon_in_0_a_bits_address[27:26]} == 3'h0 \| {auto_anon_in_0_a_bits_address[31], auto_anon_in_0_a_bits_address[28:26], ~(auto_anon_in_0_a_bits_address[16]), auto_anon_in_0_a_bits_address[12]} == 6'h0 \| {auto_anon_in_0_a_bits_address[31], auto_anon_in_0_a_bits_address[28], ~(auto_anon_in_0_a_bits_address[27:26])} == 4'h0 \| {auto_anon_in_0_a_bits_address[31], auto_anon_in_0_a_bits_address[28:26] ^ 3'h4, auto_anon_in_0_a_bits_address[16], auto_anon_in_0_a_bits_address[12]} == 6'h0; // @[Xbar.scala:291:92] wire requestAIO_0_1 = {auto_anon_in_0_a_bits_address[31], auto_anon_in_0_a_bits_address[28], auto_anon_in_0_a_bits_address[27:26] ^ 2'h2, auto_anon_in_0_a_bits_address[16]} == 5'h0 \| {~(auto_anon_in_0_a_bits_address[31]), auto_anon_in_0_a_bits_address[28]} == 2'h0; // @[Xbar.scala:74:9, :291:92] wire requestAIO_1_0 = {auto_anon_in_1_a_bits_address[31], auto_anon_in_1_a_bits_address[27:26]} == 3'h0 \| {auto_anon_in_1_a_bits_address[31], auto_anon_in_1_a_bits_address[28:26], ~(auto_anon_in_1_a_bits_address[16]), auto_anon_in_1_a_bits_address[12]} == 6'h0 \| {auto_anon_in_1_a_bits_address[31], auto_anon_in_1_a_bits_address[28], ~(auto_anon_in_1_a_bits_address[27:26])} == 4'h0 \| {auto_anon_in_1_a_bits_address[31], auto_anon_in_1_a_bits_address[28:26] ^ 3'h4, auto_anon_in_1_a_bits_address[16], auto_anon_in_1_a_bits_address[12]} == 6'h0; // @[Xbar.scala:291:92] wire requestAIO_1_1 = {auto_anon_in_1_a_bits_address[31], auto_anon_in_1_a_bits_address[28], auto_anon_in_1_a_bits_address[27:26] ^ 2'h2, auto_anon_in_1_a_bits_address[16]} == 5'h0 \| {~(auto_anon_in_1_a_bits_address[31]), auto_anon_in_1_a_bits_address[28]} == 2'h0; // @[Xbar.scala:74:9, :291:92] wire requestAIO_2_0 = {auto_anon_in_2_a_bits_address[31], auto_anon_in_2_a_bits_address[27:26]} == 3'h0 \| {auto_anon_in_2_a_bits_address[31], auto_anon_in_2_a_bits_address[28:26], ~(auto_anon_in_2_a_bits_address[16]), auto_anon_in_2_a_bits_address[12]} == 6'h0 \| {auto_anon_in_2_a_bits_address[31], auto_anon_in_2_a_bits_address[28], ~(auto_anon_in_2_a_bits_address[27:26])} == 4'h0 \| {auto_anon_in_2_a_bits_address[31], auto_anon_in_2_a_bits_address[28:26] ^ 3'h4, auto_anon_in_2_a_bits_address[16], auto_anon_in_2_a_bits_address[12]} == 6'h0; // @[Xbar.scala:291:92] wire requestAIO_2_1 = {auto_anon_in_2_a_bits_address[31], auto_anon_in_2_a_bits_address[28], auto_anon_in_2_a_bits_address[27:26] ^ 2'h2, auto_anon_in_2_a_bits_address[16]} == 5'h0 \| {~(auto_anon_in_2_a_bits_address[31]), auto_anon_in_2_a_bits_address[28]} == 2'h0; // @[Xbar.scala:74:9, :291:92] wire requestDOI_0_0 = auto_anon_out_0_d_bits_source[8:5] == 4'h8; // @[Parameters.scala:54:{10,32}] wire requestDOI_0_1 = auto_anon_out_0_d_bits_source[8:2] == 7'h48; // @[Parameters.scala:54:{10,32}] wire requestDOI_1_0 = auto_anon_out_1_d_bits_source[8:5] == 4'h8; // @[Parameters.scala:54:{10,32}] wire requestDOI_1_1 = auto_anon_out_1_d_bits_source[8:2] == 7'h48; // @[Parameters.scala:54:{10,32}] wire portsAOI_filtered_0_valid = auto_anon_in_0_a_valid & requestAIO_0_0; // @[Xbar.scala:291:92, :355:40] wire portsAOI_filtered_1_valid = auto_anon_in_0_a_valid & requestAIO_0_1; // @[Xbar.scala:291:92, :355:40] wire _portsAOI_in_0_a_ready_T_2 = requestAIO_0_0 & auto_anon_out_0_a_ready & allowed_0 \| requestAIO_0_1 & auto_anon_out_1_a_ready & allowed_1_0; // @[Mux.scala:30:73] wire portsAOI_filtered_1_0_valid = auto_anon_in_1_a_valid & requestAIO_1_0; // @[Xbar.scala:291:92, :355:40] wire portsAOI_filtered_1_1_valid = auto_anon_in_1_a_valid & requestAIO_1_1; // @[Xbar.scala:291:92, :355:40] wire _portsAOI_in_1_a_ready_T_2 = requestAIO_1_0 & auto_anon_out_0_a_ready & allowed_1 \| requestAIO_1_1 & auto_anon_out_1_a_ready & allowed_1_1; // @[Mux.scala:30:73] wire portsAOI_filtered_2_0_valid = auto_anon_in_2_a_valid & requestAIO_2_0; // @[Xbar.scala:291:92, :355:40] wire portsAOI_filtered_2_1_valid = auto_anon_in_2_a_valid & requestAIO_2_1; // @[Xbar.scala:291:92, :355:40] wire _portsAOI_in_2_a_ready_T_2 = requestAIO_2_0 & auto_anon_out_0_a_ready & allowed_2 \| requestAIO_2_1 & auto_anon_out_1_a_ready & allowed_1_2; // @[Mux.scala:30:73] wire portsDIO_filtered_0_valid = auto_anon_out_0_d_valid & requestDOI_0_0; // @[Xbar.scala:355:40] wire portsDIO_filtered_1_valid = auto_anon_out_0_d_valid & requestDOI_0_1; // @[Xbar.scala:355:40] wire portsDIO_filtered_2_valid = auto_anon_out_0_d_valid & ~(auto_anon_out_0_d_bits_source[8]); // @[Xbar.scala:355:40] wire portsDIO_filtered_1_0_valid = auto_anon_out_1_d_valid & requestDOI_1_0; // @[Xbar.scala:355:40] wire portsDIO_filtered_1_1_valid = auto_anon_out_1_d_valid & requestDOI_1_1; // @[Xbar.scala:355:40] wire portsDIO_filtered_1_2_valid = auto_anon_out_1_d_valid & ~(auto_anon_out_1_d_bits_source[8]); // @[Xbar.scala:355:40] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire [2:0] readys_valid = {portsAOI_filtered_2_0_valid, portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:355:40] reg [2:0] readys_mask; // @[Arbiter.scala:23:23] wire [2:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [3:0] _GEN = {_readys_filter_T_1[1:0], portsAOI_filtered_2_0_valid, portsAOI_filtered_1_0_valid} \| {_readys_filter_T_1, portsAOI_filtered_2_0_valid}; // @[package.scala:262:{43,48}] wire [2:0] readys_readys = ~({readys_mask[2], _readys_filter_T_1[2] \| readys_mask[1], _GEN[3] \| readys_mask[0]} & (_GEN[2:0] \| {_readys_filter_T_1[2], _GEN[3:2]})); // @[package.scala:262:{43,48}] wire winner_0 = readys_readys[0] & portsAOI_filtered_0_valid; // @[Xbar.scala:355:40] wire winner_1 = readys_readys[1] & portsAOI_filtered_1_0_valid; // @[Xbar.scala:355:40] wire winner_2 = readys_readys[2] & portsAOI_filtered_2_0_valid; // @[Xbar.scala:355:40] wire _out_0_a_valid_T = portsAOI_filtered_0_valid \| portsAOI_filtered_1_0_valid; // @[Xbar.scala:355:40] reg state_0; // @[Arbiter.scala:88:26] reg state_1; // @[Arbiter.scala:88:26] reg state_2; // @[Arbiter.scala:88:26] wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25] wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25] wire muxState_2 = idle ? winner_2 : state_2; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25] assign allowed_0 = idle ? readys_readys[0] : state_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24] assign allowed_1 = idle ? readys_readys[1] : state_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24] assign allowed_2 = idle ? readys_readys[2] : state_2; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24] wire out_0_a_valid = idle ? _out_0_a_valid_T \| portsAOI_filtered_2_0_valid : state_0 & portsAOI_filtered_0_valid \| state_1 & portsAOI_filtered_1_0_valid \| state_2 & portsAOI_filtered_2_0_valid; // @[Mux.scala:30:73] reg [8:0] beatsLeft_1; // @[Arbiter.scala:60:30] wire idle_1 = beatsLeft_1 == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire [2:0] readys_valid_1 = {portsAOI_filtered_2_1_valid, portsAOI_filtered_1_1_valid, portsAOI_filtered_1_valid}; // @[Xbar.scala:355:40] reg [2:0] readys_mask_1; // @[Arbiter.scala:23:23] wire [2:0] _readys_filter_T_3 = readys_valid_1 & ~readys_mask_1; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [3:0] _GEN_0 = {_readys_filter_T_3[1:0], portsAOI_filtered_2_1_valid, portsAOI_filtered_1_1_valid} \| {_readys_filter_T_3, portsAOI_filtered_2_1_valid}; // @[package.scala:262:{43,48}] wire [2:0] readys_readys_1 = ~({readys_mask_1[2], _readys_filter_T_3[2] \| readys_mask_1[1], _GEN_0[3] \| readys_mask_1[0]} & (_GEN_0[2:0] \| {_readys_filter_T_3[2], _GEN_0[3:2]})); // @[package.scala:262:{43,48}] wire winner_1_0 = readys_readys_1[0] & portsAOI_filtered_1_valid; // @[Xbar.scala:355:40] wire winner_1_1 = readys_readys_1[1] & portsAOI_filtered_1_1_valid; // @[Xbar.scala:355:40] wire winner_1_2 = readys_readys_1[2] & portsAOI_filtered_2_1_valid; // @[Xbar.scala:355:40] wire _out_1_a_valid_T = portsAOI_filtered_1_valid \| portsAOI_filtered_1_1_valid; // @[Xbar.scala:355:40] reg state_1_0; // @[Arbiter.scala:88:26] reg state_1_1; // @[Arbiter.scala:88:26] reg state_1_2; // @[Arbiter.scala:88:26] wire muxState_1_0 = idle_1 ? winner_1_0 : state_1_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25] wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25] wire muxState_1_2 = idle_1 ? winner_1_2 : state_1_2; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25] assign allowed_1_0 = idle_1 ? readys_readys_1[0] : state_1_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24] assign allowed_1_1 = idle_1 ? readys_readys_1[1] : state_1_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24] assign allowed_1_2 = idle_1 ? readys_readys_1[2] : state_1_2; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24] wire out_1_a_valid = idle_1 ? _out_1_a_valid_T \| portsAOI_filtered_2_1_valid : state_1_0 & portsAOI_filtered_1_valid \| state_1_1 & portsAOI_filtered_1_1_valid \| state_1_2 & portsAOI_filtered_2_1_valid; // @[Mux.scala:30:73] reg [8:0] beatsLeft_2; // @[Arbiter.scala:60:30] wire idle_2 = beatsLeft_2 == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire [1:0] readys_valid_2 = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:355:40] reg [1:0] readys_mask_2; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_5 = readys_valid_2 & ~readys_mask_2; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [1:0] readys_readys_2 = ~({readys_mask_2[1], _readys_filter_T_5[1] \| readys_mask_2[0]} & ({_readys_filter_T_5[0], portsDIO_filtered_1_0_valid} \| _readys_filter_T_5)); // @[package.scala:262:43] wire winner_2_0 = readys_readys_2[0] & portsDIO_filtered_0_valid; // @[Xbar.scala:355:40] wire winner_2_1 = readys_readys_2[1] & portsDIO_filtered_1_0_valid; // @[Xbar.scala:355:40] wire _in_0_d_valid_T = portsDIO_filtered_0_valid \| portsDIO_filtered_1_0_valid; // @[Xbar.scala:355:40] reg state_2_0; // @[Arbiter.scala:88:26] reg state_2_1; // @[Arbiter.scala:88:26] wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25] wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25] assign allowed_2_0 = idle_2 ? readys_readys_2[0] : state_2_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24] assign allowed_2_1 = idle_2 ? readys_readys_2[1] : state_2_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24] wire in_0_d_valid = idle_2 ? _in_0_d_valid_T : state_2_0 & portsDIO_filtered_0_valid \| state_2_1 & portsDIO_filtered_1_0_valid; // @[Mux.scala:30:73] wire _in_0_d_bits_T_2 = muxState_2_0 & auto_anon_out_0_d_bits_corrupt \| muxState_2_1 & auto_anon_out_1_d_bits_corrupt; // @[Mux.scala:30:73] wire _in_0_d_bits_T_8 = muxState_2_0 & auto_anon_out_0_d_bits_denied \| muxState_2_1 & auto_anon_out_1_d_bits_denied; // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_11 = (muxState_2_0 ? out_0_d_bits_sink : 3'h0) \| (muxState_2_1 ? auto_anon_out_1_d_bits_sink : 3'h0); // @[Mux.scala:30:73] wire [4:0] _in_0_d_bits_T_14 = (muxState_2_0 ? auto_anon_out_0_d_bits_source[4:0] : 5'h0) \| (muxState_2_1 ? auto_anon_out_1_d_bits_source[4:0] : 5'h0); // @[Mux.scala:30:73] wire [3:0] _in_0_d_bits_T_17 = (muxState_2_0 ? auto_anon_out_0_d_bits_size : 4'h0) \| (muxState_2_1 ? out_1_d_bits_size : 4'h0); // @[Mux.scala:30:73] wire [1:0] _in_0_d_bits_T_20 = (muxState_2_0 ? auto_anon_out_0_d_bits_param : 2'h0) \| (muxState_2_1 ? auto_anon_out_1_d_bits_param : 2'h0); // @[Mux.scala:30:73] wire [2:0] _in_0_d_bits_T_23 = (muxState_2_0 ? auto_anon_out_0_d_bits_opcode : 3'h0) \| (muxState_2_1 ? auto_anon_out_1_d_bits_opcode : 3'h0); // @[Mux.scala:30:73] reg [8:0] beatsLeft_3; // @[Arbiter.scala:60:30] wire idle_3 = beatsLeft_3 == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire [1:0] readys_valid_3 = {portsDIO_filtered_1_1_valid, portsDIO_filtered_1_valid}; // @[Xbar.scala:355:40] reg [1:0] readys_mask_3; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_7 = readys_valid_3 & ~readys_mask_3; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [1:0] readys_readys_3 = ~({readys_mask_3[1], _readys_filter_T_7[1] \| readys_mask_3[0]} & ({_readys_filter_T_7[0], portsDIO_filtered_1_1_valid} \| _readys_filter_T_7)); // @[package.scala:262:43] wire winner_3_0 = readys_readys_3[0] & portsDIO_filtered_1_valid; // @[Xbar.scala:355:40] wire winner_3_1 = readys_readys_3[1] & portsDIO_filtered_1_1_valid; // @[Xbar.scala:355:40] wire _in_1_d_valid_T = portsDIO_filtered_1_valid \| portsDIO_filtered_1_1_valid; // @[Xbar.scala:355:40] reg state_3_0; // @[Arbiter.scala:88:26] reg state_3_1; // @[Arbiter.scala:88:26] wire muxState_3_0 = idle_3 ? winner_3_0 : state_3_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25] wire muxState_3_1 = idle_3 ? winner_3_1 : state_3_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25] assign allowed_3_0 = idle_3 ? readys_readys_3[0] : state_3_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24] assign allowed_3_1 = idle_3 ? readys_readys_3[1] : state_3_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24] wire in_1_d_valid = idle_3 ? _in_1_d_valid_T : state_3_0 & portsDIO_filtered_1_valid \| state_3_1 & portsDIO_filtered_1_1_valid; // @[Mux.scala:30:73] wire _in_1_d_bits_T_2 = muxState_3_0 & auto_anon_out_0_d_bits_corrupt \| muxState_3_1 & auto_anon_out_1_d_bits_corrupt; // @[Mux.scala:30:73] wire _in_1_d_bits_T_8 = muxState_3_0 & auto_anon_out_0_d_bits_denied \| muxState_3_1 & auto_anon_out_1_d_bits_denied; // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_11 = (muxState_3_0 ? out_0_d_bits_sink : 3'h0) \| (muxState_3_1 ? auto_anon_out_1_d_bits_sink : 3'h0); // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_T_14 = (muxState_3_0 ? auto_anon_out_0_d_bits_source[1:0] : 2'h0) \| (muxState_3_1 ? auto_anon_out_1_d_bits_source[1:0] : 2'h0); // @[Mux.scala:30:73] wire [3:0] _in_1_d_bits_T_17 = (muxState_3_0 ? auto_anon_out_0_d_bits_size : 4'h0) \| (muxState_3_1 ? out_1_d_bits_size : 4'h0); // @[Mux.scala:30:73] wire [1:0] _in_1_d_bits_T_20 = (muxState_3_0 ? auto_anon_out_0_d_bits_param : 2'h0) \| (muxState_3_1 ? auto_anon_out_1_d_bits_param : 2'h0); // @[Mux.scala:30:73] wire [2:0] _in_1_d_bits_T_23 = (muxState_3_0 ? auto_anon_out_0_d_bits_opcode : 3'h0) \| (muxState_3_1 ? auto_anon_out_1_d_bits_opcode : 3'h0); // @[Mux.scala:30:73] reg [8:0] beatsLeft_4; // @[Arbiter.scala:60:30] wire idle_4 = beatsLeft_4 == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire [1:0] readys_valid_4 = {portsDIO_filtered_1_2_valid, portsDIO_filtered_2_valid}; // @[Xbar.scala:355:40] reg [1:0] readys_mask_4; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T_9 = readys_valid_4 & ~readys_mask_4; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51] wire [1:0] readys_readys_4 = ~({readys_mask_4[1], _readys_filter_T_9[1] \| readys_mask_4[0]} & ({_readys_filter_T_9[0], portsDIO_filtered_1_2_valid} \| _readys_filter_T_9)); // @[package.scala:262:43] wire winner_4_0 = readys_readys_4[0] & portsDIO_filtered_2_valid; // @[Xbar.scala:355:40] wire winner_4_1 = readys_readys_4[1] & portsDIO_filtered_1_2_valid; // @[Xbar.scala:355:40] wire _in_2_d_valid_T = portsDIO_filtered_2_valid \| portsDIO_filtered_1_2_valid; // @[Xbar.scala:355:40]
Generate the Verilog code corresponding to this FIRRTL code module ForwardingAgeLogic_1 : input clock : Clock input reset : Reset output io : { flip matches : UInt<16>, flip youngest : UInt<4>, found : UInt<1>, found_idx : UInt<4>} wire age_mask : UInt<1>[16] connect age_mask[0], UInt<1>(0h1) node _T = geq(UInt<1>(0h0), io.youngest) when _T : connect age_mask[0], UInt<1>(0h0) connect age_mask[1], UInt<1>(0h1) node _T_1 = geq(UInt<1>(0h1), io.youngest) when _T_1 : connect age_mask[1], UInt<1>(0h0) connect age_mask[2], UInt<1>(0h1) node _T_2 = geq(UInt<2>(0h2), io.youngest) when _T_2 : connect age_mask[2], UInt<1>(0h0) connect age_mask[3], UInt<1>(0h1) node _T_3 = geq(UInt<2>(0h3), io.youngest) when _T_3 : connect age_mask[3], UInt<1>(0h0) connect age_mask[4], UInt<1>(0h1) node _T_4 = geq(UInt<3>(0h4), io.youngest) when _T_4 : connect age_mask[4], UInt<1>(0h0) connect age_mask[5], UInt<1>(0h1) node _T_5 = geq(UInt<3>(0h5), io.youngest) when _T_5 : connect age_mask[5], UInt<1>(0h0) connect age_mask[6], UInt<1>(0h1) node _T_6 = geq(UInt<3>(0h6), io.youngest) when _T_6 : connect age_mask[6], UInt<1>(0h0) connect age_mask[7], UInt<1>(0h1) node _T_7 = geq(UInt<3>(0h7), io.youngest) when _T_7 : connect age_mask[7], UInt<1>(0h0) connect age_mask[8], UInt<1>(0h1) node _T_8 = geq(UInt<4>(0h8), io.youngest) when _T_8 : connect age_mask[8], UInt<1>(0h0) connect age_mask[9], UInt<1>(0h1) node _T_9 = geq(UInt<4>(0h9), io.youngest) when _T_9 : connect age_mask[9], UInt<1>(0h0) connect age_mask[10], UInt<1>(0h1) node _T_10 = geq(UInt<4>(0ha), io.youngest) when _T_10 : connect age_mask[10], UInt<1>(0h0) connect age_mask[11], UInt<1>(0h1) node _T_11 = geq(UInt<4>(0hb), io.youngest) when _T_11 : connect age_mask[11], UInt<1>(0h0) connect age_mask[12], UInt<1>(0h1) node _T_12 = geq(UInt<4>(0hc), io.youngest) when _T_12 : connect age_mask[12], UInt<1>(0h0) connect age_mask[13], UInt<1>(0h1) node _T_13 = geq(UInt<4>(0hd), io.youngest) when _T_13 : connect age_mask[13], UInt<1>(0h0) connect age_mask[14], UInt<1>(0h1) node _T_14 = geq(UInt<4>(0he), io.youngest) when _T_14 : connect age_mask[14], UInt<1>(0h0) connect age_mask[15], UInt<1>(0h1) node _T_15 = geq(UInt<4>(0hf), io.youngest) when _T_15 : connect age_mask[15], UInt<1>(0h0) wire matches : UInt<32> node matches_lo_lo_lo = cat(age_mask[1], age_mask[0]) node matches_lo_lo_hi = cat(age_mask[3], age_mask[2]) node matches_lo_lo = cat(matches_lo_lo_hi, matches_lo_lo_lo) node matches_lo_hi_lo = cat(age_mask[5], age_mask[4]) node matches_lo_hi_hi = cat(age_mask[7], age_mask[6]) node matches_lo_hi = cat(matches_lo_hi_hi, matches_lo_hi_lo) node matches_lo = cat(matches_lo_hi, matches_lo_lo) node matches_hi_lo_lo = cat(age_mask[9], age_mask[8]) node matches_hi_lo_hi = cat(age_mask[11], age_mask[10]) node matches_hi_lo = cat(matches_hi_lo_hi, matches_hi_lo_lo) node matches_hi_hi_lo = cat(age_mask[13], age_mask[12]) node matches_hi_hi_hi = cat(age_mask[15], age_mask[14]) node matches_hi_hi = cat(matches_hi_hi_hi, matches_hi_hi_lo) node matches_hi = cat(matches_hi_hi, matches_hi_lo) node _matches_T = cat(matches_hi, matches_lo) node _matches_T_1 = and(io.matches, _matches_T) node _matches_T_2 = cat(_matches_T_1, io.matches) connect matches, _matches_T_2 reg found_match : UInt<1>, clock reg found_idx : UInt<4>, clock connect found_match, UInt<1>(0h0) connect found_idx, UInt<1>(0h0) connect io.found_idx, found_idx connect io.found, found_match node _T_16 = bits(matches, 0, 0) when _T_16 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<1>(0h0) node _T_17 = bits(matches, 1, 1) when _T_17 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<1>(0h1) node _T_18 = bits(matches, 2, 2) when _T_18 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<2>(0h2) node _T_19 = bits(matches, 3, 3) when _T_19 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<2>(0h3) node _T_20 = bits(matches, 4, 4) when _T_20 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<3>(0h4) node _T_21 = bits(matches, 5, 5) when _T_21 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<3>(0h5) node _T_22 = bits(matches, 6, 6) when _T_22 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<3>(0h6) node _T_23 = bits(matches, 7, 7) when _T_23 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<3>(0h7) node _T_24 = bits(matches, 8, 8) when _T_24 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0h8) node _T_25 = bits(matches, 9, 9) when _T_25 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0h9) node _T_26 = bits(matches, 10, 10) when _T_26 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0ha) node _T_27 = bits(matches, 11, 11) when _T_27 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0hb) node _T_28 = bits(matches, 12, 12) when _T_28 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0hc) node _T_29 = bits(matches, 13, 13) when _T_29 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0hd) node _T_30 = bits(matches, 14, 14) when _T_30 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0he) node _T_31 = bits(matches, 15, 15) when _T_31 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0hf) node _T_32 = bits(matches, 16, 16) when _T_32 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<1>(0h0) node _T_33 = bits(matches, 17, 17) when _T_33 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<1>(0h1) node _T_34 = bits(matches, 18, 18) when _T_34 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<2>(0h2) node _T_35 = bits(matches, 19, 19) when _T_35 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<2>(0h3) node _T_36 = bits(matches, 20, 20) when _T_36 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<3>(0h4) node _T_37 = bits(matches, 21, 21) when _T_37 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<3>(0h5) node _T_38 = bits(matches, 22, 22) when _T_38 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<3>(0h6) node _T_39 = bits(matches, 23, 23) when _T_39 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<3>(0h7) node _T_40 = bits(matches, 24, 24) when _T_40 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0h8) node _T_41 = bits(matches, 25, 25) when _T_41 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0h9) node _T_42 = bits(matches, 26, 26) when _T_42 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0ha) node _T_43 = bits(matches, 27, 27) when _T_43 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0hb) node _T_44 = bits(matches, 28, 28) when _T_44 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0hc) node _T_45 = bits(matches, 29, 29) when _T_45 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0hd) node _T_46 = bits(matches, 30, 30) when _T_46 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0he) node _T_47 = bits(matches, 31, 31) when _T_47 : connect found_match, UInt<1>(0h1) connect found_idx, UInt<4>(0hf)	module ForwardingAgeLogic_1( // @[lsu.scala:1972:7] input clock, // @[lsu.scala:1972:7] input reset, // @[lsu.scala:1972:7] input [15:0] io_matches, // @[lsu.scala:1974:14] input [3:0] io_youngest, // @[lsu.scala:1974:14] output io_found, // @[lsu.scala:1974:14] output [3:0] io_found_idx // @[lsu.scala:1974:14] ); wire [15:0] io_matches_0 = io_matches; // @[lsu.scala:1972:7] wire [3:0] io_youngest_0 = io_youngest; // @[lsu.scala:1972:7] wire age_mask_15 = 1'h0; // @[lsu.scala:1985:22] wire io_found_0; // @[lsu.scala:1972:7] wire [3:0] io_found_idx_0; // @[lsu.scala:1972:7] wire age_mask_0; // @[lsu.scala:1985:22] wire age_mask_1; // @[lsu.scala:1985:22] wire age_mask_2; // @[lsu.scala:1985:22] wire age_mask_3; // @[lsu.scala:1985:22] wire age_mask_4; // @[lsu.scala:1985:22] wire age_mask_5; // @[lsu.scala:1985:22] wire age_mask_6; // @[lsu.scala:1985:22] wire age_mask_7; // @[lsu.scala:1985:22] wire age_mask_8; // @[lsu.scala:1985:22] wire age_mask_9; // @[lsu.scala:1985:22] wire age_mask_10; // @[lsu.scala:1985:22] wire age_mask_11; // @[lsu.scala:1985:22] wire age_mask_12; // @[lsu.scala:1985:22] wire age_mask_13; // @[lsu.scala:1985:22] wire age_mask_14; // @[lsu.scala:1985:22] assign age_mask_0 = \|io_youngest_0; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_1 = \|(io_youngest_0[3:1]); // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_2 = io_youngest_0 > 4'h2; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_3 = \|(io_youngest_0[3:2]); // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_4 = io_youngest_0 > 4'h4; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_5 = io_youngest_0 > 4'h5; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_6 = io_youngest_0 > 4'h6; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_7 = io_youngest_0[3]; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_8 = io_youngest_0 > 4'h8; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_9 = io_youngest_0 > 4'h9; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_10 = io_youngest_0 > 4'hA; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_11 = io_youngest_0 > 4'hB; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_12 = io_youngest_0 > 4'hC; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_13 = io_youngest_0 > 4'hD; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] assign age_mask_14 = &io_youngest_0; // @[lsu.scala:1972:7, :1985:22, :1988:17, :1989:15, :1990:5, :1991:19] wire [31:0] _matches_T_2; // @[lsu.scala:1997:17] wire [31:0] matches_0; // @[lsu.scala:1996:21] wire [1:0] matches_lo_lo_lo = {age_mask_1, age_mask_0}; // @[lsu.scala:1985:22, :1997:40] wire [1:0] matches_lo_lo_hi = {age_mask_3, age_mask_2}; // @[lsu.scala:1985:22, :1997:40] wire [3:0] matches_lo_lo = {matches_lo_lo_hi, matches_lo_lo_lo}; // @[lsu.scala:1997:40] wire [1:0] matches_lo_hi_lo = {age_mask_5, age_mask_4}; // @[lsu.scala:1985:22, :1997:40] wire [1:0] matches_lo_hi_hi = {age_mask_7, age_mask_6}; // @[lsu.scala:1985:22, :1997:40] wire [3:0] matches_lo_hi = {matches_lo_hi_hi, matches_lo_hi_lo}; // @[lsu.scala:1997:40] wire [7:0] matches_lo = {matches_lo_hi, matches_lo_lo}; // @[lsu.scala:1997:40] wire [1:0] matches_hi_lo_lo = {age_mask_9, age_mask_8}; // @[lsu.scala:1985:22, :1997:40] wire [1:0] matches_hi_lo_hi = {age_mask_11, age_mask_10}; // @[lsu.scala:1985:22, :1997:40] wire [3:0] matches_hi_lo = {matches_hi_lo_hi, matches_hi_lo_lo}; // @[lsu.scala:1997:40] wire [1:0] matches_hi_hi_lo = {age_mask_13, age_mask_12}; // @[lsu.scala:1985:22, :1997:40] wire [1:0] matches_hi_hi_hi = {1'h0, age_mask_14}; // @[lsu.scala:1985:22, :1997:40] wire [3:0] matches_hi_hi = {matches_hi_hi_hi, matches_hi_hi_lo}; // @[lsu.scala:1997:40] wire [7:0] matches_hi = {matches_hi_hi, matches_hi_lo}; // @[lsu.scala:1997:40] wire [15:0] _matches_T = {matches_hi, matches_lo}; // @[lsu.scala:1997:40] wire [15:0] _matches_T_1 = io_matches_0 & _matches_T; // @[lsu.scala:1972:7, :1997:{29,40}] assign _matches_T_2 = {_matches_T_1, io_matches_0}; // @[lsu.scala:1972:7, :1997:{17,29}] assign matches_0 = _matches_T_2; // @[lsu.scala:1996:21, :1997:17] reg found_match; // @[lsu.scala:2000:24] assign io_found_0 = found_match; // @[lsu.scala:1972:7, :2000:24] reg [3:0] found_idx; // @[lsu.scala:2001:22] assign io_found_idx_0 = found_idx; // @[lsu.scala:1972:7, :2001:22] always @(posedge clock) begin // @[lsu.scala:1972:7] found_match <= \|matches_0; // @[lsu.scala:1996:21, :2000:24, :2012:7, :2013:22] found_idx <= matches_0[31] ? 4'hF : matches_0[30] ? 4'hE : matches_0[29] ? 4'hD : matches_0[28] ? 4'hC : matches_0[27] ? 4'hB : matches_0[26] ? 4'hA : matches_0[25] ? 4'h9 : matches_0[24] ? 4'h8 : matches_0[23] ? 4'h7 : matches_0[22] ? 4'h6 : matches_0[21] ? 4'h5 : matches_0[20] ? 4'h4 : matches_0[19] ? 4'h3 : matches_0[18] ? 4'h2 : matches_0[17] ? 4'h1 : matches_0[16] ? 4'h0 : matches_0[15] ? 4'hF : matches_0[14] ? 4'hE : matches_0[13] ? 4'hD : matches_0[12] ? 4'hC : matches_0[11] ? 4'hB : matches_0[10] ? 4'hA : matches_0[9] ? 4'h9 : matches_0[8] ? 4'h8 : matches_0[7] ? 4'h7 : matches_0[6] ? 4'h6 : matches_0[5] ? 4'h5 : matches_0[4] ? 4'h4 : matches_0[3] ? 4'h3 : matches_0[2] ? 4'h2 : {3'h0, matches_0[1]}; // @[lsu.scala:1988:17, :1989:15, :1990:5, :1991:19, :1996:21, :2001:22, :2011:20, :2012:7, :2014:20] always @(posedge) assign io_found = io_found_0; // @[lsu.scala:1972:7] assign io_found_idx = io_found_idx_0; // @[lsu.scala:1972:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_161 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_417 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_161( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_417 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator_48 : input clock : Clock input reset : Reset output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1]}, credit_alloc : { `2` : { alloc : UInt<1>, tail : UInt<1>}[1], `1` : { alloc : UInt<1>, tail : UInt<1>}[1], `0` : { alloc : UInt<1>, tail : UInt<1>}[10]}, switch_sel : { `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}} inst arbs_0 of SwitchArbiter_280 connect arbs_0.clock, clock connect arbs_0.reset, reset inst arbs_1 of SwitchArbiter_281 connect arbs_1.clock, clock connect arbs_1.reset, reset inst arbs_2 of SwitchArbiter_282 connect arbs_2.clock, clock connect arbs_2.reset, reset connect arbs_0.io.out[0].ready, UInt<1>(0h1) connect arbs_1.io.out[0].ready, UInt<1>(0h1) connect arbs_2.io.out[0].ready, UInt<1>(0h1) wire fires : UInt<1>[3] node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_0_valid_T_1 = or(_arbs_0_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_0_valid_T_2 = or(_arbs_0_io_in_0_valid_T_1, io.req.`0`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_0_valid_T_3 = or(_arbs_0_io_in_0_valid_T_2, io.req.`0`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_0_valid_T_4 = or(_arbs_0_io_in_0_valid_T_3, io.req.`0`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_0_valid_T_5 = or(_arbs_0_io_in_0_valid_T_4, io.req.`0`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_0_valid_T_6 = or(_arbs_0_io_in_0_valid_T_5, io.req.`0`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_0_valid_T_7 = or(_arbs_0_io_in_0_valid_T_6, io.req.`0`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_0_valid_T_8 = or(_arbs_0_io_in_0_valid_T_7, io.req.`0`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_0_valid_T_9 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T_8) connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_9 connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid) connect fires[0], _fires_0_T node _arbs_1_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid) connect fires[1], _fires_1_T node _arbs_2_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[0].valid, _arbs_2_io_in_0_valid_T connect arbs_2.io.in[0].bits.tail, io.req.`0`[0].bits.tail connect arbs_2.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0] node _fires_2_T = and(arbs_2.io.in[0].ready, arbs_2.io.in[0].valid) connect fires[2], _fires_2_T node _io_req_0_0_ready_T = or(fires[0], fires[1]) node _io_req_0_0_ready_T_1 = or(_io_req_0_0_ready_T, fires[2]) connect io.req.`0`[0].ready, _io_req_0_0_ready_T_1 wire fires_1 : UInt<1>[3] node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_1_valid_T_1 = or(_arbs_0_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_1_valid_T_2 = or(_arbs_0_io_in_1_valid_T_1, io.req.`1`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_1_valid_T_3 = or(_arbs_0_io_in_1_valid_T_2, io.req.`1`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_1_valid_T_4 = or(_arbs_0_io_in_1_valid_T_3, io.req.`1`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_1_valid_T_5 = or(_arbs_0_io_in_1_valid_T_4, io.req.`1`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_1_valid_T_6 = or(_arbs_0_io_in_1_valid_T_5, io.req.`1`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_1_valid_T_7 = or(_arbs_0_io_in_1_valid_T_6, io.req.`1`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_1_valid_T_8 = or(_arbs_0_io_in_1_valid_T_7, io.req.`1`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_1_valid_T_9 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T_8) connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_9 connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid) connect fires_1[0], _fires_0_T_1 node _arbs_1_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid) connect fires_1[1], _fires_1_T_1 node _arbs_2_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[1].valid, _arbs_2_io_in_1_valid_T connect arbs_2.io.in[1].bits.tail, io.req.`1`[0].bits.tail connect arbs_2.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0] node _fires_2_T_1 = and(arbs_2.io.in[1].ready, arbs_2.io.in[1].valid) connect fires_1[2], _fires_2_T_1 node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1]) node _io_req_1_0_ready_T_1 = or(_io_req_1_0_ready_T, fires_1[2]) connect io.req.`1`[0].ready, _io_req_1_0_ready_T_1 wire fires_2 : UInt<1>[3] node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_2_valid_T_1 = or(_arbs_0_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_2_valid_T_2 = or(_arbs_0_io_in_2_valid_T_1, io.req.`2`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_2_valid_T_3 = or(_arbs_0_io_in_2_valid_T_2, io.req.`2`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_2_valid_T_4 = or(_arbs_0_io_in_2_valid_T_3, io.req.`2`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_2_valid_T_5 = or(_arbs_0_io_in_2_valid_T_4, io.req.`2`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_2_valid_T_6 = or(_arbs_0_io_in_2_valid_T_5, io.req.`2`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_2_valid_T_7 = or(_arbs_0_io_in_2_valid_T_6, io.req.`2`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_2_valid_T_8 = or(_arbs_0_io_in_2_valid_T_7, io.req.`2`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_2_valid_T_9 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T_8) connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_9 connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid) connect fires_2[0], _fires_0_T_2 node _arbs_1_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid) connect fires_2[1], _fires_1_T_2 node _arbs_2_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[2].valid, _arbs_2_io_in_2_valid_T connect arbs_2.io.in[2].bits.tail, io.req.`2`[0].bits.tail connect arbs_2.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0] node _fires_2_T_2 = and(arbs_2.io.in[2].ready, arbs_2.io.in[2].valid) connect fires_2[2], _fires_2_T_2 node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1]) node _io_req_2_0_ready_T_1 = or(_io_req_2_0_ready_T, fires_2[2]) connect io.req.`2`[0].ready, _io_req_2_0_ready_T_1 wire fires_3 : UInt<1>[3] node _arbs_0_io_in_3_valid_T = or(io.req.`3`[0].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[1]) node _arbs_0_io_in_3_valid_T_1 = or(_arbs_0_io_in_3_valid_T, io.req.`3`[0].bits.vc_sel.`0`[2]) node _arbs_0_io_in_3_valid_T_2 = or(_arbs_0_io_in_3_valid_T_1, io.req.`3`[0].bits.vc_sel.`0`[3]) node _arbs_0_io_in_3_valid_T_3 = or(_arbs_0_io_in_3_valid_T_2, io.req.`3`[0].bits.vc_sel.`0`[4]) node _arbs_0_io_in_3_valid_T_4 = or(_arbs_0_io_in_3_valid_T_3, io.req.`3`[0].bits.vc_sel.`0`[5]) node _arbs_0_io_in_3_valid_T_5 = or(_arbs_0_io_in_3_valid_T_4, io.req.`3`[0].bits.vc_sel.`0`[6]) node _arbs_0_io_in_3_valid_T_6 = or(_arbs_0_io_in_3_valid_T_5, io.req.`3`[0].bits.vc_sel.`0`[7]) node _arbs_0_io_in_3_valid_T_7 = or(_arbs_0_io_in_3_valid_T_6, io.req.`3`[0].bits.vc_sel.`0`[8]) node _arbs_0_io_in_3_valid_T_8 = or(_arbs_0_io_in_3_valid_T_7, io.req.`3`[0].bits.vc_sel.`0`[9]) node _arbs_0_io_in_3_valid_T_9 = and(io.req.`3`[0].valid, _arbs_0_io_in_3_valid_T_8) connect arbs_0.io.in[3].valid, _arbs_0_io_in_3_valid_T_9 connect arbs_0.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_0.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_0.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_0.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_0.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_0.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_0.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_0.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_0.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_0.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_0.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_0.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_0.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] node _fires_0_T_3 = and(arbs_0.io.in[3].ready, arbs_0.io.in[3].valid) connect fires_3[0], _fires_0_T_3 node _arbs_1_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`1`[0]) connect arbs_1.io.in[3].valid, _arbs_1_io_in_3_valid_T connect arbs_1.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_1.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_1.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_1.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_1.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_1.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_1.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_1.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_1.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_1.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_1.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_1.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_1.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] node _fires_1_T_3 = and(arbs_1.io.in[3].ready, arbs_1.io.in[3].valid) connect fires_3[1], _fires_1_T_3 node _arbs_2_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`2`[0]) connect arbs_2.io.in[3].valid, _arbs_2_io_in_3_valid_T connect arbs_2.io.in[3].bits.tail, io.req.`3`[0].bits.tail connect arbs_2.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0] connect arbs_2.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1] connect arbs_2.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2] connect arbs_2.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3] connect arbs_2.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4] connect arbs_2.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5] connect arbs_2.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6] connect arbs_2.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7] connect arbs_2.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8] connect arbs_2.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9] connect arbs_2.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0] connect arbs_2.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0] node _fires_2_T_3 = and(arbs_2.io.in[3].ready, arbs_2.io.in[3].valid) connect fires_3[2], _fires_2_T_3 node _io_req_3_0_ready_T = or(fires_3[0], fires_3[1]) node _io_req_3_0_ready_T_1 = or(_io_req_3_0_ready_T, fires_3[2]) connect io.req.`3`[0].ready, _io_req_3_0_ready_T_1 node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0) node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T) node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2 node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1) node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T) node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2 node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2) node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T) node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2 node _io_switch_sel_0_0_3_0_T = bits(arbs_0.io.chosen_oh[0], 3, 3) node _io_switch_sel_0_0_3_0_T_1 = and(arbs_0.io.in[3].valid, _io_switch_sel_0_0_3_0_T) node _io_switch_sel_0_0_3_0_T_2 = and(_io_switch_sel_0_0_3_0_T_1, arbs_0.io.out[0].valid) connect io.switch_sel.`0`[0].`3`[0], _io_switch_sel_0_0_3_0_T_2 node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0) node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T) node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2 node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1) node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T) node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2 node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2) node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T) node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2 node _io_switch_sel_1_0_3_0_T = bits(arbs_1.io.chosen_oh[0], 3, 3) node _io_switch_sel_1_0_3_0_T_1 = and(arbs_1.io.in[3].valid, _io_switch_sel_1_0_3_0_T) node _io_switch_sel_1_0_3_0_T_2 = and(_io_switch_sel_1_0_3_0_T_1, arbs_1.io.out[0].valid) connect io.switch_sel.`1`[0].`3`[0], _io_switch_sel_1_0_3_0_T_2 node _io_switch_sel_2_0_0_0_T = bits(arbs_2.io.chosen_oh[0], 0, 0) node _io_switch_sel_2_0_0_0_T_1 = and(arbs_2.io.in[0].valid, _io_switch_sel_2_0_0_0_T) node _io_switch_sel_2_0_0_0_T_2 = and(_io_switch_sel_2_0_0_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`0`[0], _io_switch_sel_2_0_0_0_T_2 node _io_switch_sel_2_0_1_0_T = bits(arbs_2.io.chosen_oh[0], 1, 1) node _io_switch_sel_2_0_1_0_T_1 = and(arbs_2.io.in[1].valid, _io_switch_sel_2_0_1_0_T) node _io_switch_sel_2_0_1_0_T_2 = and(_io_switch_sel_2_0_1_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`1`[0], _io_switch_sel_2_0_1_0_T_2 node _io_switch_sel_2_0_2_0_T = bits(arbs_2.io.chosen_oh[0], 2, 2) node _io_switch_sel_2_0_2_0_T_1 = and(arbs_2.io.in[2].valid, _io_switch_sel_2_0_2_0_T) node _io_switch_sel_2_0_2_0_T_2 = and(_io_switch_sel_2_0_2_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`2`[0], _io_switch_sel_2_0_2_0_T_2 node _io_switch_sel_2_0_3_0_T = bits(arbs_2.io.chosen_oh[0], 3, 3) node _io_switch_sel_2_0_3_0_T_1 = and(arbs_2.io.in[3].valid, _io_switch_sel_2_0_3_0_T) node _io_switch_sel_2_0_3_0_T_2 = and(_io_switch_sel_2_0_3_0_T_1, arbs_2.io.out[0].valid) connect io.switch_sel.`2`[0].`3`[0], _io_switch_sel_2_0_3_0_T_2 connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[4].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[5].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[6].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[7].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[8].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[9].alloc, UInt<1>(0h0) connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h0) connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[2].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[3].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[4].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[5].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[6].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[7].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[8].tail, UInt<1>(0h0) connect io.credit_alloc.`0`[9].tail, UInt<1>(0h0) connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0) connect io.credit_alloc.`2`[0].tail, UInt<1>(0h0) node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0]) when _T : connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1]) when _T_1 : connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail node _T_2 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[2]) when _T_2 : connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[2].tail, arbs_0.io.out[0].bits.tail node _T_3 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[3]) when _T_3 : connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[3].tail, arbs_0.io.out[0].bits.tail node _T_4 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[4]) when _T_4 : connect io.credit_alloc.`0`[4].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[4].tail, arbs_0.io.out[0].bits.tail node _T_5 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[5]) when _T_5 : connect io.credit_alloc.`0`[5].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[5].tail, arbs_0.io.out[0].bits.tail node _T_6 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[6]) when _T_6 : connect io.credit_alloc.`0`[6].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[6].tail, arbs_0.io.out[0].bits.tail node _T_7 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[7]) when _T_7 : connect io.credit_alloc.`0`[7].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[7].tail, arbs_0.io.out[0].bits.tail node _T_8 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[8]) when _T_8 : connect io.credit_alloc.`0`[8].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[8].tail, arbs_0.io.out[0].bits.tail node _T_9 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[9]) when _T_9 : connect io.credit_alloc.`0`[9].alloc, UInt<1>(0h1) connect io.credit_alloc.`0`[9].tail, arbs_0.io.out[0].bits.tail node _T_10 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0]) when _T_10 : connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail node _T_11 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[0]) when _T_11 : connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h1) connect io.credit_alloc.`2`[0].tail, arbs_2.io.out[0].bits.tail	module SwitchAllocator_48( // @[SwitchAllocator.scala:64:7] input clock, // @[SwitchAllocator.scala:64:7] input reset, // @[SwitchAllocator.scala:64:7] output io_req_1_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_1_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:74:14] input io_req_1_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14] input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14] input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_2_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_1_0_tail, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_8_alloc, // @[SwitchAllocator.scala:74:14] output io_credit_alloc_0_9_alloc, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_2_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_1_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14] output io_switch_sel_0_0_1_0 // @[SwitchAllocator.scala:74:14] ); wire _arbs_2_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45] wire _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_2_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45] wire _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_in_1_ready; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_8; // @[SwitchAllocator.scala:83:45] wire _arbs_0_io_out_0_bits_vc_sel_0_9; // @[SwitchAllocator.scala:83:45] wire [3:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45] wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire arbs_0_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_0_0 \| io_req_1_0_bits_vc_sel_0_1 \| io_req_1_0_bits_vc_sel_0_2 \| io_req_1_0_bits_vc_sel_0_3 \| io_req_1_0_bits_vc_sel_0_4 \| io_req_1_0_bits_vc_sel_0_5 \| io_req_1_0_bits_vc_sel_0_6 \| io_req_1_0_bits_vc_sel_0_7 \| io_req_1_0_bits_vc_sel_0_8 \| io_req_1_0_bits_vc_sel_0_9); // @[SwitchAllocator.scala:95:{37,65}] wire arbs_1_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37] wire arbs_2_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37] wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45, :120:33] wire io_credit_alloc_2_0_alloc_0 = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45, :120:33] SwitchArbiter_280 arbs_0 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (/* unused /), .io_in_0_valid (1'h0), .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_0_io_in_1_ready), .io_in_1_valid (arbs_0_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0), .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_8 (io_req_1_0_bits_vc_sel_0_8), .io_in_1_bits_vc_sel_0_9 (io_req_1_0_bits_vc_sel_0_9), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_out_0_valid (_arbs_0_io_out_0_valid), .io_out_0_bits_vc_sel_2_0 (/ unused /), .io_out_0_bits_vc_sel_1_0 (/ unused /), .io_out_0_bits_vc_sel_0_8 (_arbs_0_io_out_0_bits_vc_sel_0_8), .io_out_0_bits_vc_sel_0_9 (_arbs_0_io_out_0_bits_vc_sel_0_9), .io_out_0_bits_tail (/ unused /), .io_chosen_oh_0 (_arbs_0_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_280 arbs_1 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_1_io_in_0_ready), .io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_1_io_in_1_ready), .io_in_1_valid (arbs_1_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0), .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_8 (io_req_1_0_bits_vc_sel_0_8), .io_in_1_bits_vc_sel_0_9 (io_req_1_0_bits_vc_sel_0_9), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_out_0_valid (_arbs_1_io_out_0_valid), .io_out_0_bits_vc_sel_2_0 (/ unused /), .io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0), .io_out_0_bits_vc_sel_0_8 (/ unused /), .io_out_0_bits_vc_sel_0_9 (/ unused /), .io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_1_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] SwitchArbiter_280 arbs_2 ( // @[SwitchAllocator.scala:83:45] .clock (clock), .reset (reset), .io_in_0_ready (_arbs_2_io_in_0_ready), .io_in_0_valid (arbs_2_io_in_0_valid), // @[SwitchAllocator.scala:95:37] .io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0), .io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0), .io_in_0_bits_tail (io_req_0_0_bits_tail), .io_in_1_ready (_arbs_2_io_in_1_ready), .io_in_1_valid (arbs_2_io_in_1_valid), // @[SwitchAllocator.scala:95:37] .io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0), .io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0), .io_in_1_bits_vc_sel_0_8 (io_req_1_0_bits_vc_sel_0_8), .io_in_1_bits_vc_sel_0_9 (io_req_1_0_bits_vc_sel_0_9), .io_in_1_bits_tail (io_req_1_0_bits_tail), .io_out_0_valid (_arbs_2_io_out_0_valid), .io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0), .io_out_0_bits_vc_sel_1_0 (/ unused /), .io_out_0_bits_vc_sel_0_8 (/ unused /), .io_out_0_bits_vc_sel_0_9 (/ unused */), .io_out_0_bits_tail (_arbs_2_io_out_0_bits_tail), .io_chosen_oh_0 (_arbs_2_io_chosen_oh_0) ); // @[SwitchAllocator.scala:83:45] assign io_req_1_0_ready = _arbs_0_io_in_1_ready & arbs_0_io_in_1_valid \| _arbs_1_io_in_1_ready & arbs_1_io_in_1_valid \| _arbs_2_io_in_1_ready & arbs_2_io_in_1_valid; // @[Decoupled.scala:51:35] assign io_req_0_0_ready = _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid \| _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid; // @[Decoupled.scala:51:35] assign io_credit_alloc_2_0_alloc = io_credit_alloc_2_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_2_0_tail = io_credit_alloc_2_0_alloc_0 & _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33] assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21] assign io_credit_alloc_0_8_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_8; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_credit_alloc_0_9_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_9; // @[SwitchAllocator.scala:64:7, :83:45, :120:33] assign io_switch_sel_2_0_1_0 = arbs_2_io_in_1_valid & _arbs_2_io_chosen_oh_0[1] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_1_0 = arbs_1_io_in_1_valid & _arbs_1_io_chosen_oh_0[1] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] assign io_switch_sel_0_0_1_0 = arbs_0_io_in_1_valid & _arbs_0_io_chosen_oh_0[1] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_30 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<29>(0h10000000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<29>(0h10000000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<29>(0h10000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<29>(0h10000000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<29>(0h10000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<29>(0h10000000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<29>(0h10000000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<29>(0h10000000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<29>(0h10000000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h1), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h1), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h1), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h1), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h1), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_60 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_61 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_62 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_63 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLMonitor_30( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_30 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_31 = shr(io.in.a.bits.source, 3) node _source_ok_T_32 = eq(_source_ok_T_31, UInt<3>(0h6)) node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_T_35 = leq(source_ok_uncommonBits_4, UInt<3>(0h4)) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0) node _source_ok_T_39 = shr(io.in.a.bits.source, 3) node _source_ok_T_40 = eq(_source_ok_T_39, UInt<3>(0h4)) node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<3>(0h4)) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[18] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_36 connect _source_ok_WIRE[12], _source_ok_T_37 connect _source_ok_WIRE[13], _source_ok_T_38 connect _source_ok_WIRE[14], _source_ok_T_44 connect _source_ok_WIRE[15], _source_ok_T_45 connect _source_ok_WIRE[16], _source_ok_T_46 connect _source_ok_WIRE[17], _source_ok_T_47 node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[7]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[8]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[9]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[10]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[11]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[12]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[13]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[14]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[15]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[16]) node source_ok = or(_source_ok_T_63, _source_ok_WIRE[17]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_112 = shr(io.in.a.bits.source, 3) node _T_113 = eq(_T_112, UInt<3>(0h6)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_4) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_120 = cvt(_T_119) node _T_121 = and(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = asSInt(_T_121) node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = or(_T_118, _T_123) node _T_125 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_126 = eq(_T_125, UInt<1>(0h0)) node _T_127 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = or(_T_126, _T_131) node _T_133 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<1>(0h0))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = or(_T_134, _T_139) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_141 = shr(io.in.a.bits.source, 3) node _T_142 = eq(_T_141, UInt<3>(0h4)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_5) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(_T_146, UInt<1>(0h0)) node _T_148 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_149 = cvt(_T_148) node _T_150 = and(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = asSInt(_T_150) node _T_152 = eq(_T_151, asSInt(UInt<1>(0h0))) node _T_153 = or(_T_147, _T_152) node _T_154 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = or(_T_155, _T_160) node _T_162 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_163 = eq(_T_162, UInt<1>(0h0)) node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = or(_T_163, _T_168) node _T_170 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_171 = eq(_T_170, UInt<1>(0h0)) node _T_172 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = or(_T_171, _T_176) node _T_178 = and(_T_11, _T_24) node _T_179 = and(_T_178, _T_37) node _T_180 = and(_T_179, _T_50) node _T_181 = and(_T_180, _T_63) node _T_182 = and(_T_181, _T_71) node _T_183 = and(_T_182, _T_79) node _T_184 = and(_T_183, _T_87) node _T_185 = and(_T_184, _T_95) node _T_186 = and(_T_185, _T_103) node _T_187 = and(_T_186, _T_111) node _T_188 = and(_T_187, _T_124) node _T_189 = and(_T_188, _T_132) node _T_190 = and(_T_189, _T_140) node _T_191 = and(_T_190, _T_153) node _T_192 = and(_T_191, _T_161) node _T_193 = and(_T_192, _T_169) node _T_194 = and(_T_193, _T_177) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_194, UInt<1>(0h1), "") : assert_1 node _T_198 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_198 : node _T_199 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_200 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_201 = and(_T_199, _T_200) node _T_202 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_203 = shr(io.in.a.bits.source, 2) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = leq(UInt<1>(0h0), uncommonBits_6) node _T_206 = and(_T_204, _T_205) node _T_207 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_208 = and(_T_206, _T_207) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_209 = shr(io.in.a.bits.source, 2) node _T_210 = eq(_T_209, UInt<1>(0h1)) node _T_211 = leq(UInt<1>(0h0), uncommonBits_7) node _T_212 = and(_T_210, _T_211) node _T_213 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_214 = and(_T_212, _T_213) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_215 = shr(io.in.a.bits.source, 2) node _T_216 = eq(_T_215, UInt<2>(0h2)) node _T_217 = leq(UInt<1>(0h0), uncommonBits_8) node _T_218 = and(_T_216, _T_217) node _T_219 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_220 = and(_T_218, _T_219) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_221 = shr(io.in.a.bits.source, 2) node _T_222 = eq(_T_221, UInt<2>(0h3)) node _T_223 = leq(UInt<1>(0h0), uncommonBits_9) node _T_224 = and(_T_222, _T_223) node _T_225 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_226 = and(_T_224, _T_225) node _T_227 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_228 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_229 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_230 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_231 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_233 = shr(io.in.a.bits.source, 3) node _T_234 = eq(_T_233, UInt<3>(0h6)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_10) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_241 = shr(io.in.a.bits.source, 3) node _T_242 = eq(_T_241, UInt<3>(0h4)) node _T_243 = leq(UInt<1>(0h0), uncommonBits_11) node _T_244 = and(_T_242, _T_243) node _T_245 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_249 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_250 = or(_T_202, _T_208) node _T_251 = or(_T_250, _T_214) node _T_252 = or(_T_251, _T_220) node _T_253 = or(_T_252, _T_226) node _T_254 = or(_T_253, _T_227) node _T_255 = or(_T_254, _T_228) node _T_256 = or(_T_255, _T_229) node _T_257 = or(_T_256, _T_230) node _T_258 = or(_T_257, _T_231) node _T_259 = or(_T_258, _T_232) node _T_260 = or(_T_259, _T_238) node _T_261 = or(_T_260, _T_239) node _T_262 = or(_T_261, _T_240) node _T_263 = or(_T_262, _T_246) node _T_264 = or(_T_263, _T_247) node _T_265 = or(_T_264, _T_248) node _T_266 = or(_T_265, _T_249) node _T_267 = and(_T_201, _T_266) node _T_268 = or(UInt<1>(0h0), _T_267) node _T_269 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_270 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_271 = cvt(_T_270) node _T_272 = and(_T_271, asSInt(UInt<13>(0h1000))) node _T_273 = asSInt(_T_272) node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0))) node _T_275 = and(_T_269, _T_274) node _T_276 = or(UInt<1>(0h0), _T_275) node _T_277 = and(_T_268, _T_276) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_277, UInt<1>(0h1), "") : assert_2 node _T_281 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_282 = shr(io.in.a.bits.source, 2) node _T_283 = eq(_T_282, UInt<1>(0h0)) node _T_284 = leq(UInt<1>(0h0), uncommonBits_12) node _T_285 = and(_T_283, _T_284) node _T_286 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_287 = and(_T_285, _T_286) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_288 = shr(io.in.a.bits.source, 2) node _T_289 = eq(_T_288, UInt<1>(0h1)) node _T_290 = leq(UInt<1>(0h0), uncommonBits_13) node _T_291 = and(_T_289, _T_290) node _T_292 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_293 = and(_T_291, _T_292) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_294 = shr(io.in.a.bits.source, 2) node _T_295 = eq(_T_294, UInt<2>(0h2)) node _T_296 = leq(UInt<1>(0h0), uncommonBits_14) node _T_297 = and(_T_295, _T_296) node _T_298 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_299 = and(_T_297, _T_298) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_300 = shr(io.in.a.bits.source, 2) node _T_301 = eq(_T_300, UInt<2>(0h3)) node _T_302 = leq(UInt<1>(0h0), uncommonBits_15) node _T_303 = and(_T_301, _T_302) node _T_304 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_305 = and(_T_303, _T_304) node _T_306 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_307 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_308 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_309 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_310 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_311 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0) node _T_312 = shr(io.in.a.bits.source, 3) node _T_313 = eq(_T_312, UInt<3>(0h6)) node _T_314 = leq(UInt<1>(0h0), uncommonBits_16) node _T_315 = and(_T_313, _T_314) node _T_316 = leq(uncommonBits_16, UInt<3>(0h4)) node _T_317 = and(_T_315, _T_316) node _T_318 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0) node _T_320 = shr(io.in.a.bits.source, 3) node _T_321 = eq(_T_320, UInt<3>(0h4)) node _T_322 = leq(UInt<1>(0h0), uncommonBits_17) node _T_323 = and(_T_321, _T_322) node _T_324 = leq(uncommonBits_17, UInt<3>(0h4)) node _T_325 = and(_T_323, _T_324) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_328 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[18] connect _WIRE[0], _T_281 connect _WIRE[1], _T_287 connect _WIRE[2], _T_293 connect _WIRE[3], _T_299 connect _WIRE[4], _T_305 connect _WIRE[5], _T_306 connect _WIRE[6], _T_307 connect _WIRE[7], _T_308 connect _WIRE[8], _T_309 connect _WIRE[9], _T_310 connect _WIRE[10], _T_311 connect _WIRE[11], _T_317 connect _WIRE[12], _T_318 connect _WIRE[13], _T_319 connect _WIRE[14], _T_325 connect _WIRE[15], _T_326 connect _WIRE[16], _T_327 connect _WIRE[17], _T_328 node _T_329 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_330 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_332 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_333 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_335 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_338 = mux(_WIRE[5], _T_329, UInt<1>(0h0)) node _T_339 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_340 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = mux(_WIRE[8], _T_330, UInt<1>(0h0)) node _T_342 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_343 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_344 = mux(_WIRE[11], _T_331, UInt<1>(0h0)) node _T_345 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_346 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_347 = mux(_WIRE[14], _T_332, UInt<1>(0h0)) node _T_348 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_349 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_350 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_351 = or(_T_333, _T_334) node _T_352 = or(_T_351, _T_335) node _T_353 = or(_T_352, _T_336) node _T_354 = or(_T_353, _T_337) node _T_355 = or(_T_354, _T_338) node _T_356 = or(_T_355, _T_339) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_341) node _T_359 = or(_T_358, _T_342) node _T_360 = or(_T_359, _T_343) node _T_361 = or(_T_360, _T_344) node _T_362 = or(_T_361, _T_345) node _T_363 = or(_T_362, _T_346) node _T_364 = or(_T_363, _T_347) node _T_365 = or(_T_364, _T_348) node _T_366 = or(_T_365, _T_349) node _T_367 = or(_T_366, _T_350) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_367 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = and(_T_371, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = and(_WIRE_1, _T_378) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_379, UInt<1>(0h1), "") : assert_3 node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(source_ok, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_386, UInt<1>(0h1), "") : assert_5 node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(is_aligned, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_393, UInt<1>(0h1), "") : assert_7 node _T_397 = not(io.in.a.bits.mask) node _T_398 = eq(_T_397, UInt<1>(0h0)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_398, UInt<1>(0h1), "") : assert_8 node _T_402 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_402, UInt<1>(0h1), "") : assert_9 node _T_406 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_406 : node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_408 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_411 = shr(io.in.a.bits.source, 2) node _T_412 = eq(_T_411, UInt<1>(0h0)) node _T_413 = leq(UInt<1>(0h0), uncommonBits_18) node _T_414 = and(_T_412, _T_413) node _T_415 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_416 = and(_T_414, _T_415) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_417 = shr(io.in.a.bits.source, 2) node _T_418 = eq(_T_417, UInt<1>(0h1)) node _T_419 = leq(UInt<1>(0h0), uncommonBits_19) node _T_420 = and(_T_418, _T_419) node _T_421 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_422 = and(_T_420, _T_421) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_423 = shr(io.in.a.bits.source, 2) node _T_424 = eq(_T_423, UInt<2>(0h2)) node _T_425 = leq(UInt<1>(0h0), uncommonBits_20) node _T_426 = and(_T_424, _T_425) node _T_427 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_428 = and(_T_426, _T_427) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_429 = shr(io.in.a.bits.source, 2) node _T_430 = eq(_T_429, UInt<2>(0h3)) node _T_431 = leq(UInt<1>(0h0), uncommonBits_21) node _T_432 = and(_T_430, _T_431) node _T_433 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 2, 0) node _T_441 = shr(io.in.a.bits.source, 3) node _T_442 = eq(_T_441, UInt<3>(0h6)) node _T_443 = leq(UInt<1>(0h0), uncommonBits_22) node _T_444 = and(_T_442, _T_443) node _T_445 = leq(uncommonBits_22, UInt<3>(0h4)) node _T_446 = and(_T_444, _T_445) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 2, 0) node _T_449 = shr(io.in.a.bits.source, 3) node _T_450 = eq(_T_449, UInt<3>(0h4)) node _T_451 = leq(UInt<1>(0h0), uncommonBits_23) node _T_452 = and(_T_450, _T_451) node _T_453 = leq(uncommonBits_23, UInt<3>(0h4)) node _T_454 = and(_T_452, _T_453) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_457 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_458 = or(_T_410, _T_416) node _T_459 = or(_T_458, _T_422) node _T_460 = or(_T_459, _T_428) node _T_461 = or(_T_460, _T_434) node _T_462 = or(_T_461, _T_435) node _T_463 = or(_T_462, _T_436) node _T_464 = or(_T_463, _T_437) node _T_465 = or(_T_464, _T_438) node _T_466 = or(_T_465, _T_439) node _T_467 = or(_T_466, _T_440) node _T_468 = or(_T_467, _T_446) node _T_469 = or(_T_468, _T_447) node _T_470 = or(_T_469, _T_448) node _T_471 = or(_T_470, _T_454) node _T_472 = or(_T_471, _T_455) node _T_473 = or(_T_472, _T_456) node _T_474 = or(_T_473, _T_457) node _T_475 = and(_T_409, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_478 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_479 = cvt(_T_478) node _T_480 = and(_T_479, asSInt(UInt<13>(0h1000))) node _T_481 = asSInt(_T_480) node _T_482 = eq(_T_481, asSInt(UInt<1>(0h0))) node _T_483 = and(_T_477, _T_482) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = and(_T_476, _T_484) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_485, UInt<1>(0h1), "") : assert_10 node _T_489 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<1>(0h0)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_24) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_496 = shr(io.in.a.bits.source, 2) node _T_497 = eq(_T_496, UInt<1>(0h1)) node _T_498 = leq(UInt<1>(0h0), uncommonBits_25) node _T_499 = and(_T_497, _T_498) node _T_500 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_501 = and(_T_499, _T_500) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_502 = shr(io.in.a.bits.source, 2) node _T_503 = eq(_T_502, UInt<2>(0h2)) node _T_504 = leq(UInt<1>(0h0), uncommonBits_26) node _T_505 = and(_T_503, _T_504) node _T_506 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_507 = and(_T_505, _T_506) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_508 = shr(io.in.a.bits.source, 2) node _T_509 = eq(_T_508, UInt<2>(0h3)) node _T_510 = leq(UInt<1>(0h0), uncommonBits_27) node _T_511 = and(_T_509, _T_510) node _T_512 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_513 = and(_T_511, _T_512) node _T_514 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_515 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_516 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_517 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_518 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_519 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 2, 0) node _T_520 = shr(io.in.a.bits.source, 3) node _T_521 = eq(_T_520, UInt<3>(0h6)) node _T_522 = leq(UInt<1>(0h0), uncommonBits_28) node _T_523 = and(_T_521, _T_522) node _T_524 = leq(uncommonBits_28, UInt<3>(0h4)) node _T_525 = and(_T_523, _T_524) node _T_526 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_527 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_528 = shr(io.in.a.bits.source, 3) node _T_529 = eq(_T_528, UInt<3>(0h4)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_29) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_29, UInt<3>(0h4)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_536 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[18] connect _WIRE_2[0], _T_489 connect _WIRE_2[1], _T_495 connect _WIRE_2[2], _T_501 connect _WIRE_2[3], _T_507 connect _WIRE_2[4], _T_513 connect _WIRE_2[5], _T_514 connect _WIRE_2[6], _T_515 connect _WIRE_2[7], _T_516 connect _WIRE_2[8], _T_517 connect _WIRE_2[9], _T_518 connect _WIRE_2[10], _T_519 connect _WIRE_2[11], _T_525 connect _WIRE_2[12], _T_526 connect _WIRE_2[13], _T_527 connect _WIRE_2[14], _T_533 connect _WIRE_2[15], _T_534 connect _WIRE_2[16], _T_535 connect _WIRE_2[17], _T_536 node _T_537 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_538 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_539 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_540 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_541 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_542 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_543 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_544 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_545 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_546 = mux(_WIRE_2[5], _T_537, UInt<1>(0h0)) node _T_547 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_548 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_549 = mux(_WIRE_2[8], _T_538, UInt<1>(0h0)) node _T_550 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_552 = mux(_WIRE_2[11], _T_539, UInt<1>(0h0)) node _T_553 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_554 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_555 = mux(_WIRE_2[14], _T_540, UInt<1>(0h0)) node _T_556 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_557 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_558 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0)) node _T_559 = or(_T_541, _T_542) node _T_560 = or(_T_559, _T_543) node _T_561 = or(_T_560, _T_544) node _T_562 = or(_T_561, _T_545) node _T_563 = or(_T_562, _T_546) node _T_564 = or(_T_563, _T_547) node _T_565 = or(_T_564, _T_548) node _T_566 = or(_T_565, _T_549) node _T_567 = or(_T_566, _T_550) node _T_568 = or(_T_567, _T_551) node _T_569 = or(_T_568, _T_552) node _T_570 = or(_T_569, _T_553) node _T_571 = or(_T_570, _T_554) node _T_572 = or(_T_571, _T_555) node _T_573 = or(_T_572, _T_556) node _T_574 = or(_T_573, _T_557) node _T_575 = or(_T_574, _T_558) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_575 node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_578 = and(_T_576, _T_577) node _T_579 = or(UInt<1>(0h0), _T_578) node _T_580 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_581 = cvt(_T_580) node _T_582 = and(_T_581, asSInt(UInt<13>(0h1000))) node _T_583 = asSInt(_T_582) node _T_584 = eq(_T_583, asSInt(UInt<1>(0h0))) node _T_585 = and(_T_579, _T_584) node _T_586 = or(UInt<1>(0h0), _T_585) node _T_587 = and(_WIRE_3, _T_586) node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(_T_587, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_587, UInt<1>(0h1), "") : assert_11 node _T_591 = asUInt(reset) node _T_592 = eq(_T_591, UInt<1>(0h0)) when _T_592 : node _T_593 = eq(source_ok, UInt<1>(0h0)) when _T_593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_594 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_594, UInt<1>(0h1), "") : assert_13 node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(is_aligned, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_601 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_601, UInt<1>(0h1), "") : assert_15 node _T_605 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_605, UInt<1>(0h1), "") : assert_16 node _T_609 = not(io.in.a.bits.mask) node _T_610 = eq(_T_609, UInt<1>(0h0)) node _T_611 = asUInt(reset) node _T_612 = eq(_T_611, UInt<1>(0h0)) when _T_612 : node _T_613 = eq(_T_610, UInt<1>(0h0)) when _T_613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_610, UInt<1>(0h1), "") : assert_17 node _T_614 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_614, UInt<1>(0h1), "") : assert_18 node _T_618 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_618 : node _T_619 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_620 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_621 = and(_T_619, _T_620) node _T_622 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_623 = shr(io.in.a.bits.source, 2) node _T_624 = eq(_T_623, UInt<1>(0h0)) node _T_625 = leq(UInt<1>(0h0), uncommonBits_30) node _T_626 = and(_T_624, _T_625) node _T_627 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_628 = and(_T_626, _T_627) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_629 = shr(io.in.a.bits.source, 2) node _T_630 = eq(_T_629, UInt<1>(0h1)) node _T_631 = leq(UInt<1>(0h0), uncommonBits_31) node _T_632 = and(_T_630, _T_631) node _T_633 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_634 = and(_T_632, _T_633) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_635 = shr(io.in.a.bits.source, 2) node _T_636 = eq(_T_635, UInt<2>(0h2)) node _T_637 = leq(UInt<1>(0h0), uncommonBits_32) node _T_638 = and(_T_636, _T_637) node _T_639 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_640 = and(_T_638, _T_639) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_641 = shr(io.in.a.bits.source, 2) node _T_642 = eq(_T_641, UInt<2>(0h3)) node _T_643 = leq(UInt<1>(0h0), uncommonBits_33) node _T_644 = and(_T_642, _T_643) node _T_645 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_646 = and(_T_644, _T_645) node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_648 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_649 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_650 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_651 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_652 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_653 = shr(io.in.a.bits.source, 3) node _T_654 = eq(_T_653, UInt<3>(0h6)) node _T_655 = leq(UInt<1>(0h0), uncommonBits_34) node _T_656 = and(_T_654, _T_655) node _T_657 = leq(uncommonBits_34, UInt<3>(0h4)) node _T_658 = and(_T_656, _T_657) node _T_659 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_660 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 2, 0) node _T_661 = shr(io.in.a.bits.source, 3) node _T_662 = eq(_T_661, UInt<3>(0h4)) node _T_663 = leq(UInt<1>(0h0), uncommonBits_35) node _T_664 = and(_T_662, _T_663) node _T_665 = leq(uncommonBits_35, UInt<3>(0h4)) node _T_666 = and(_T_664, _T_665) node _T_667 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_668 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_669 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_670 = or(_T_622, _T_628) node _T_671 = or(_T_670, _T_634) node _T_672 = or(_T_671, _T_640) node _T_673 = or(_T_672, _T_646) node _T_674 = or(_T_673, _T_647) node _T_675 = or(_T_674, _T_648) node _T_676 = or(_T_675, _T_649) node _T_677 = or(_T_676, _T_650) node _T_678 = or(_T_677, _T_651) node _T_679 = or(_T_678, _T_652) node _T_680 = or(_T_679, _T_658) node _T_681 = or(_T_680, _T_659) node _T_682 = or(_T_681, _T_660) node _T_683 = or(_T_682, _T_666) node _T_684 = or(_T_683, _T_667) node _T_685 = or(_T_684, _T_668) node _T_686 = or(_T_685, _T_669) node _T_687 = and(_T_621, _T_686) node _T_688 = or(UInt<1>(0h0), _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_688, UInt<1>(0h1), "") : assert_19 node _T_692 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_693 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_694 = and(_T_692, _T_693) node _T_695 = or(UInt<1>(0h0), _T_694) node _T_696 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<13>(0h1000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = and(_T_695, _T_700) node _T_702 = or(UInt<1>(0h0), _T_701) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_702, UInt<1>(0h1), "") : assert_20 node _T_706 = asUInt(reset) node _T_707 = eq(_T_706, UInt<1>(0h0)) when _T_707 : node _T_708 = eq(source_ok, UInt<1>(0h0)) when _T_708 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(is_aligned, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_712 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_712, UInt<1>(0h1), "") : assert_23 node _T_716 = eq(io.in.a.bits.mask, mask) node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(_T_716, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_716, UInt<1>(0h1), "") : assert_24 node _T_720 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(_T_720, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_720, UInt<1>(0h1), "") : assert_25 node _T_724 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_724 : node _T_725 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_726 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_727 = and(_T_725, _T_726) node _T_728 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_729 = shr(io.in.a.bits.source, 2) node _T_730 = eq(_T_729, UInt<1>(0h0)) node _T_731 = leq(UInt<1>(0h0), uncommonBits_36) node _T_732 = and(_T_730, _T_731) node _T_733 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_734 = and(_T_732, _T_733) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_735 = shr(io.in.a.bits.source, 2) node _T_736 = eq(_T_735, UInt<1>(0h1)) node _T_737 = leq(UInt<1>(0h0), uncommonBits_37) node _T_738 = and(_T_736, _T_737) node _T_739 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_740 = and(_T_738, _T_739) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_741 = shr(io.in.a.bits.source, 2) node _T_742 = eq(_T_741, UInt<2>(0h2)) node _T_743 = leq(UInt<1>(0h0), uncommonBits_38) node _T_744 = and(_T_742, _T_743) node _T_745 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_746 = and(_T_744, _T_745) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_747 = shr(io.in.a.bits.source, 2) node _T_748 = eq(_T_747, UInt<2>(0h3)) node _T_749 = leq(UInt<1>(0h0), uncommonBits_39) node _T_750 = and(_T_748, _T_749) node _T_751 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_754 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_755 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_756 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_757 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_758 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0) node _T_759 = shr(io.in.a.bits.source, 3) node _T_760 = eq(_T_759, UInt<3>(0h6)) node _T_761 = leq(UInt<1>(0h0), uncommonBits_40) node _T_762 = and(_T_760, _T_761) node _T_763 = leq(uncommonBits_40, UInt<3>(0h4)) node _T_764 = and(_T_762, _T_763) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0) node _T_767 = shr(io.in.a.bits.source, 3) node _T_768 = eq(_T_767, UInt<3>(0h4)) node _T_769 = leq(UInt<1>(0h0), uncommonBits_41) node _T_770 = and(_T_768, _T_769) node _T_771 = leq(uncommonBits_41, UInt<3>(0h4)) node _T_772 = and(_T_770, _T_771) node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_775 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_776 = or(_T_728, _T_734) node _T_777 = or(_T_776, _T_740) node _T_778 = or(_T_777, _T_746) node _T_779 = or(_T_778, _T_752) node _T_780 = or(_T_779, _T_753) node _T_781 = or(_T_780, _T_754) node _T_782 = or(_T_781, _T_755) node _T_783 = or(_T_782, _T_756) node _T_784 = or(_T_783, _T_757) node _T_785 = or(_T_784, _T_758) node _T_786 = or(_T_785, _T_764) node _T_787 = or(_T_786, _T_765) node _T_788 = or(_T_787, _T_766) node _T_789 = or(_T_788, _T_772) node _T_790 = or(_T_789, _T_773) node _T_791 = or(_T_790, _T_774) node _T_792 = or(_T_791, _T_775) node _T_793 = and(_T_727, _T_792) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_796 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_797 = and(_T_795, _T_796) node _T_798 = or(UInt<1>(0h0), _T_797) node _T_799 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_800 = cvt(_T_799) node _T_801 = and(_T_800, asSInt(UInt<13>(0h1000))) node _T_802 = asSInt(_T_801) node _T_803 = eq(_T_802, asSInt(UInt<1>(0h0))) node _T_804 = and(_T_798, _T_803) node _T_805 = or(UInt<1>(0h0), _T_804) node _T_806 = and(_T_794, _T_805) node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(_T_806, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_806, UInt<1>(0h1), "") : assert_26 node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(source_ok, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(is_aligned, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_816 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(_T_816, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_816, UInt<1>(0h1), "") : assert_29 node _T_820 = eq(io.in.a.bits.mask, mask) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_820, UInt<1>(0h1), "") : assert_30 node _T_824 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_824 : node _T_825 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_826 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_827 = and(_T_825, _T_826) node _T_828 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_829 = shr(io.in.a.bits.source, 2) node _T_830 = eq(_T_829, UInt<1>(0h0)) node _T_831 = leq(UInt<1>(0h0), uncommonBits_42) node _T_832 = and(_T_830, _T_831) node _T_833 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_834 = and(_T_832, _T_833) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_835 = shr(io.in.a.bits.source, 2) node _T_836 = eq(_T_835, UInt<1>(0h1)) node _T_837 = leq(UInt<1>(0h0), uncommonBits_43) node _T_838 = and(_T_836, _T_837) node _T_839 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_840 = and(_T_838, _T_839) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_841 = shr(io.in.a.bits.source, 2) node _T_842 = eq(_T_841, UInt<2>(0h2)) node _T_843 = leq(UInt<1>(0h0), uncommonBits_44) node _T_844 = and(_T_842, _T_843) node _T_845 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_846 = and(_T_844, _T_845) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_847 = shr(io.in.a.bits.source, 2) node _T_848 = eq(_T_847, UInt<2>(0h3)) node _T_849 = leq(UInt<1>(0h0), uncommonBits_45) node _T_850 = and(_T_848, _T_849) node _T_851 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_852 = and(_T_850, _T_851) node _T_853 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_854 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_855 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_856 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_857 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_858 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0) node _T_859 = shr(io.in.a.bits.source, 3) node _T_860 = eq(_T_859, UInt<3>(0h6)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_46) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_46, UInt<3>(0h4)) node _T_864 = and(_T_862, _T_863) node _T_865 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_866 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0) node _T_867 = shr(io.in.a.bits.source, 3) node _T_868 = eq(_T_867, UInt<3>(0h4)) node _T_869 = leq(UInt<1>(0h0), uncommonBits_47) node _T_870 = and(_T_868, _T_869) node _T_871 = leq(uncommonBits_47, UInt<3>(0h4)) node _T_872 = and(_T_870, _T_871) node _T_873 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_874 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_875 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_876 = or(_T_828, _T_834) node _T_877 = or(_T_876, _T_840) node _T_878 = or(_T_877, _T_846) node _T_879 = or(_T_878, _T_852) node _T_880 = or(_T_879, _T_853) node _T_881 = or(_T_880, _T_854) node _T_882 = or(_T_881, _T_855) node _T_883 = or(_T_882, _T_856) node _T_884 = or(_T_883, _T_857) node _T_885 = or(_T_884, _T_858) node _T_886 = or(_T_885, _T_864) node _T_887 = or(_T_886, _T_865) node _T_888 = or(_T_887, _T_866) node _T_889 = or(_T_888, _T_872) node _T_890 = or(_T_889, _T_873) node _T_891 = or(_T_890, _T_874) node _T_892 = or(_T_891, _T_875) node _T_893 = and(_T_827, _T_892) node _T_894 = or(UInt<1>(0h0), _T_893) node _T_895 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_896 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_897 = and(_T_895, _T_896) node _T_898 = or(UInt<1>(0h0), _T_897) node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<13>(0h1000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = and(_T_898, _T_903) node _T_905 = or(UInt<1>(0h0), _T_904) node _T_906 = and(_T_894, _T_905) node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(_T_906, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_906, UInt<1>(0h1), "") : assert_31 node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(source_ok, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(is_aligned, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_916 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(_T_916, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_916, UInt<1>(0h1), "") : assert_34 node _T_920 = not(mask) node _T_921 = and(io.in.a.bits.mask, _T_920) node _T_922 = eq(_T_921, UInt<1>(0h0)) node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_T_922, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_922, UInt<1>(0h1), "") : assert_35 node _T_926 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_926 : node _T_927 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_928 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_929 = and(_T_927, _T_928) node _T_930 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_931 = shr(io.in.a.bits.source, 2) node _T_932 = eq(_T_931, UInt<1>(0h0)) node _T_933 = leq(UInt<1>(0h0), uncommonBits_48) node _T_934 = and(_T_932, _T_933) node _T_935 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_936 = and(_T_934, _T_935) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_937 = shr(io.in.a.bits.source, 2) node _T_938 = eq(_T_937, UInt<1>(0h1)) node _T_939 = leq(UInt<1>(0h0), uncommonBits_49) node _T_940 = and(_T_938, _T_939) node _T_941 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_942 = and(_T_940, _T_941) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_943 = shr(io.in.a.bits.source, 2) node _T_944 = eq(_T_943, UInt<2>(0h2)) node _T_945 = leq(UInt<1>(0h0), uncommonBits_50) node _T_946 = and(_T_944, _T_945) node _T_947 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_948 = and(_T_946, _T_947) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_949 = shr(io.in.a.bits.source, 2) node _T_950 = eq(_T_949, UInt<2>(0h3)) node _T_951 = leq(UInt<1>(0h0), uncommonBits_51) node _T_952 = and(_T_950, _T_951) node _T_953 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_954 = and(_T_952, _T_953) node _T_955 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_956 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_957 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_958 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_959 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_960 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 2, 0) node _T_961 = shr(io.in.a.bits.source, 3) node _T_962 = eq(_T_961, UInt<3>(0h6)) node _T_963 = leq(UInt<1>(0h0), uncommonBits_52) node _T_964 = and(_T_962, _T_963) node _T_965 = leq(uncommonBits_52, UInt<3>(0h4)) node _T_966 = and(_T_964, _T_965) node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0) node _T_969 = shr(io.in.a.bits.source, 3) node _T_970 = eq(_T_969, UInt<3>(0h4)) node _T_971 = leq(UInt<1>(0h0), uncommonBits_53) node _T_972 = and(_T_970, _T_971) node _T_973 = leq(uncommonBits_53, UInt<3>(0h4)) node _T_974 = and(_T_972, _T_973) node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_977 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_978 = or(_T_930, _T_936) node _T_979 = or(_T_978, _T_942) node _T_980 = or(_T_979, _T_948) node _T_981 = or(_T_980, _T_954) node _T_982 = or(_T_981, _T_955) node _T_983 = or(_T_982, _T_956) node _T_984 = or(_T_983, _T_957) node _T_985 = or(_T_984, _T_958) node _T_986 = or(_T_985, _T_959) node _T_987 = or(_T_986, _T_960) node _T_988 = or(_T_987, _T_966) node _T_989 = or(_T_988, _T_967) node _T_990 = or(_T_989, _T_968) node _T_991 = or(_T_990, _T_974) node _T_992 = or(_T_991, _T_975) node _T_993 = or(_T_992, _T_976) node _T_994 = or(_T_993, _T_977) node _T_995 = and(_T_929, _T_994) node _T_996 = or(UInt<1>(0h0), _T_995) node _T_997 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_998 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_999 = cvt(_T_998) node _T_1000 = and(_T_999, asSInt(UInt<13>(0h1000))) node _T_1001 = asSInt(_T_1000) node _T_1002 = eq(_T_1001, asSInt(UInt<1>(0h0))) node _T_1003 = and(_T_997, _T_1002) node _T_1004 = or(UInt<1>(0h0), _T_1003) node _T_1005 = and(_T_996, _T_1004) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_36 node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(source_ok, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1012 = asUInt(reset) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(is_aligned, UInt<1>(0h0)) when _T_1014 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1015 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1016 = asUInt(reset) node _T_1017 = eq(_T_1016, UInt<1>(0h0)) when _T_1017 : node _T_1018 = eq(_T_1015, UInt<1>(0h0)) when _T_1018 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1015, UInt<1>(0h1), "") : assert_39 node _T_1019 = eq(io.in.a.bits.mask, mask) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_40 node _T_1023 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1023 : node _T_1024 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1025 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1026 = and(_T_1024, _T_1025) node _T_1027 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1028 = shr(io.in.a.bits.source, 2) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) node _T_1030 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1033 = and(_T_1031, _T_1032) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1034 = shr(io.in.a.bits.source, 2) node _T_1035 = eq(_T_1034, UInt<1>(0h1)) node _T_1036 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1037 = and(_T_1035, _T_1036) node _T_1038 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1039 = and(_T_1037, _T_1038) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1040 = shr(io.in.a.bits.source, 2) node _T_1041 = eq(_T_1040, UInt<2>(0h2)) node _T_1042 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1045 = and(_T_1043, _T_1044) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1046 = shr(io.in.a.bits.source, 2) node _T_1047 = eq(_T_1046, UInt<2>(0h3)) node _T_1048 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1051 = and(_T_1049, _T_1050) node _T_1052 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1053 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1054 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1055 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1056 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1057 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 2, 0) node _T_1058 = shr(io.in.a.bits.source, 3) node _T_1059 = eq(_T_1058, UInt<3>(0h6)) node _T_1060 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1061 = and(_T_1059, _T_1060) node _T_1062 = leq(uncommonBits_58, UInt<3>(0h4)) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1065 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0) node _T_1066 = shr(io.in.a.bits.source, 3) node _T_1067 = eq(_T_1066, UInt<3>(0h4)) node _T_1068 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1069 = and(_T_1067, _T_1068) node _T_1070 = leq(uncommonBits_59, UInt<3>(0h4)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1074 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1075 = or(_T_1027, _T_1033) node _T_1076 = or(_T_1075, _T_1039) node _T_1077 = or(_T_1076, _T_1045) node _T_1078 = or(_T_1077, _T_1051) node _T_1079 = or(_T_1078, _T_1052) node _T_1080 = or(_T_1079, _T_1053) node _T_1081 = or(_T_1080, _T_1054) node _T_1082 = or(_T_1081, _T_1055) node _T_1083 = or(_T_1082, _T_1056) node _T_1084 = or(_T_1083, _T_1057) node _T_1085 = or(_T_1084, _T_1063) node _T_1086 = or(_T_1085, _T_1064) node _T_1087 = or(_T_1086, _T_1065) node _T_1088 = or(_T_1087, _T_1071) node _T_1089 = or(_T_1088, _T_1072) node _T_1090 = or(_T_1089, _T_1073) node _T_1091 = or(_T_1090, _T_1074) node _T_1092 = and(_T_1026, _T_1091) node _T_1093 = or(UInt<1>(0h0), _T_1092) node _T_1094 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1095 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1096 = cvt(_T_1095) node _T_1097 = and(_T_1096, asSInt(UInt<13>(0h1000))) node _T_1098 = asSInt(_T_1097) node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0))) node _T_1100 = and(_T_1094, _T_1099) node _T_1101 = or(UInt<1>(0h0), _T_1100) node _T_1102 = and(_T_1093, _T_1101) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_41 node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(source_ok, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(is_aligned, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1112 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_44 node _T_1116 = eq(io.in.a.bits.mask, mask) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_45 node _T_1120 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1120 : node _T_1121 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1122 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1123 = and(_T_1121, _T_1122) node _T_1124 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1125 = shr(io.in.a.bits.source, 2) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) node _T_1127 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1128 = and(_T_1126, _T_1127) node _T_1129 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1130 = and(_T_1128, _T_1129) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1131 = shr(io.in.a.bits.source, 2) node _T_1132 = eq(_T_1131, UInt<1>(0h1)) node _T_1133 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1134 = and(_T_1132, _T_1133) node _T_1135 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1136 = and(_T_1134, _T_1135) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1137 = shr(io.in.a.bits.source, 2) node _T_1138 = eq(_T_1137, UInt<2>(0h2)) node _T_1139 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1140 = and(_T_1138, _T_1139) node _T_1141 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1142 = and(_T_1140, _T_1141) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1143 = shr(io.in.a.bits.source, 2) node _T_1144 = eq(_T_1143, UInt<2>(0h3)) node _T_1145 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1146 = and(_T_1144, _T_1145) node _T_1147 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1148 = and(_T_1146, _T_1147) node _T_1149 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1150 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1151 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1152 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1153 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1154 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0) node _T_1155 = shr(io.in.a.bits.source, 3) node _T_1156 = eq(_T_1155, UInt<3>(0h6)) node _T_1157 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1158 = and(_T_1156, _T_1157) node _T_1159 = leq(uncommonBits_64, UInt<3>(0h4)) node _T_1160 = and(_T_1158, _T_1159) node _T_1161 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1162 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 2, 0) node _T_1163 = shr(io.in.a.bits.source, 3) node _T_1164 = eq(_T_1163, UInt<3>(0h4)) node _T_1165 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1166 = and(_T_1164, _T_1165) node _T_1167 = leq(uncommonBits_65, UInt<3>(0h4)) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1170 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1171 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1172 = or(_T_1124, _T_1130) node _T_1173 = or(_T_1172, _T_1136) node _T_1174 = or(_T_1173, _T_1142) node _T_1175 = or(_T_1174, _T_1148) node _T_1176 = or(_T_1175, _T_1149) node _T_1177 = or(_T_1176, _T_1150) node _T_1178 = or(_T_1177, _T_1151) node _T_1179 = or(_T_1178, _T_1152) node _T_1180 = or(_T_1179, _T_1153) node _T_1181 = or(_T_1180, _T_1154) node _T_1182 = or(_T_1181, _T_1160) node _T_1183 = or(_T_1182, _T_1161) node _T_1184 = or(_T_1183, _T_1162) node _T_1185 = or(_T_1184, _T_1168) node _T_1186 = or(_T_1185, _T_1169) node _T_1187 = or(_T_1186, _T_1170) node _T_1188 = or(_T_1187, _T_1171) node _T_1189 = and(_T_1123, _T_1188) node _T_1190 = or(UInt<1>(0h0), _T_1189) node _T_1191 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1192 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1193 = cvt(_T_1192) node _T_1194 = and(_T_1193, asSInt(UInt<13>(0h1000))) node _T_1195 = asSInt(_T_1194) node _T_1196 = eq(_T_1195, asSInt(UInt<1>(0h0))) node _T_1197 = and(_T_1191, _T_1196) node _T_1198 = or(UInt<1>(0h0), _T_1197) node _T_1199 = and(_T_1190, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_46 node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(source_ok, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(is_aligned, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1209 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_49 node _T_1213 = eq(io.in.a.bits.mask, mask) node _T_1214 = asUInt(reset) node _T_1215 = eq(_T_1214, UInt<1>(0h0)) when _T_1215 : node _T_1216 = eq(_T_1213, UInt<1>(0h0)) when _T_1216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1213, UInt<1>(0h1), "") : assert_50 node _T_1217 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1218 = asUInt(reset) node _T_1219 = eq(_T_1218, UInt<1>(0h0)) when _T_1219 : node _T_1220 = eq(_T_1217, UInt<1>(0h0)) when _T_1220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1217, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1221 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_52 node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_65 = shr(io.in.d.bits.source, 2) node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h0)) node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_T_69 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_71 = shr(io.in.d.bits.source, 2) node _source_ok_T_72 = eq(_source_ok_T_71, UInt<1>(0h1)) node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 2) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h2)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_83 = shr(io.in.d.bits.source, 2) node _source_ok_T_84 = eq(_source_ok_T_83, UInt<2>(0h3)) node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85) node _source_ok_T_87 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 2, 0) node _source_ok_T_95 = shr(io.in.d.bits.source, 3) node _source_ok_T_96 = eq(_source_ok_T_95, UInt<3>(0h6)) node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97) node _source_ok_T_99 = leq(source_ok_uncommonBits_10, UInt<3>(0h4)) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 3) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_11, UInt<3>(0h4)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[18] connect _source_ok_WIRE_1[0], _source_ok_T_64 connect _source_ok_WIRE_1[1], _source_ok_T_70 connect _source_ok_WIRE_1[2], _source_ok_T_76 connect _source_ok_WIRE_1[3], _source_ok_T_82 connect _source_ok_WIRE_1[4], _source_ok_T_88 connect _source_ok_WIRE_1[5], _source_ok_T_89 connect _source_ok_WIRE_1[6], _source_ok_T_90 connect _source_ok_WIRE_1[7], _source_ok_T_91 connect _source_ok_WIRE_1[8], _source_ok_T_92 connect _source_ok_WIRE_1[9], _source_ok_T_93 connect _source_ok_WIRE_1[10], _source_ok_T_94 connect _source_ok_WIRE_1[11], _source_ok_T_100 connect _source_ok_WIRE_1[12], _source_ok_T_101 connect _source_ok_WIRE_1[13], _source_ok_T_102 connect _source_ok_WIRE_1[14], _source_ok_T_108 connect _source_ok_WIRE_1[15], _source_ok_T_109 connect _source_ok_WIRE_1[16], _source_ok_T_110 connect _source_ok_WIRE_1[17], _source_ok_T_111 node _source_ok_T_112 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[2]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[3]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[4]) node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_1[5]) node _source_ok_T_117 = or(_source_ok_T_116, _source_ok_WIRE_1[6]) node _source_ok_T_118 = or(_source_ok_T_117, _source_ok_WIRE_1[7]) node _source_ok_T_119 = or(_source_ok_T_118, _source_ok_WIRE_1[8]) node _source_ok_T_120 = or(_source_ok_T_119, _source_ok_WIRE_1[9]) node _source_ok_T_121 = or(_source_ok_T_120, _source_ok_WIRE_1[10]) node _source_ok_T_122 = or(_source_ok_T_121, _source_ok_WIRE_1[11]) node _source_ok_T_123 = or(_source_ok_T_122, _source_ok_WIRE_1[12]) node _source_ok_T_124 = or(_source_ok_T_123, _source_ok_WIRE_1[13]) node _source_ok_T_125 = or(_source_ok_T_124, _source_ok_WIRE_1[14]) node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_1[15]) node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_1[16]) node source_ok_1 = or(_source_ok_T_127, _source_ok_WIRE_1[17]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1225 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1225 : node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(source_ok_1, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1229 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(_T_1229, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1229, UInt<1>(0h1), "") : assert_54 node _T_1233 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_55 node _T_1237 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_56 node _T_1241 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_57 node _T_1245 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1245 : node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(source_ok_1, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(sink_ok, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1252 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_60 node _T_1256 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1257 = asUInt(reset) node _T_1258 = eq(_T_1257, UInt<1>(0h0)) when _T_1258 : node _T_1259 = eq(_T_1256, UInt<1>(0h0)) when _T_1259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1256, UInt<1>(0h1), "") : assert_61 node _T_1260 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1261 = asUInt(reset) node _T_1262 = eq(_T_1261, UInt<1>(0h0)) when _T_1262 : node _T_1263 = eq(_T_1260, UInt<1>(0h0)) when _T_1263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1260, UInt<1>(0h1), "") : assert_62 node _T_1264 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_63 node _T_1268 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1269 = or(UInt<1>(0h0), _T_1268) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_64 node _T_1273 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1273 : node _T_1274 = asUInt(reset) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) when _T_1275 : node _T_1276 = eq(source_ok_1, UInt<1>(0h0)) when _T_1276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1277 = asUInt(reset) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(sink_ok, UInt<1>(0h0)) when _T_1279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1280 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_67 node _T_1284 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_68 node _T_1288 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1289 = asUInt(reset) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(_T_1288, UInt<1>(0h0)) when _T_1291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1288, UInt<1>(0h1), "") : assert_69 node _T_1292 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1293 = or(_T_1292, io.in.d.bits.corrupt) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_70 node _T_1297 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1298 = or(UInt<1>(0h0), _T_1297) node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(_T_1298, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1298, UInt<1>(0h1), "") : assert_71 node _T_1302 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1302 : node _T_1303 = asUInt(reset) node _T_1304 = eq(_T_1303, UInt<1>(0h0)) when _T_1304 : node _T_1305 = eq(source_ok_1, UInt<1>(0h0)) when _T_1305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1306 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1307 = asUInt(reset) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) when _T_1308 : node _T_1309 = eq(_T_1306, UInt<1>(0h0)) when _T_1309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1306, UInt<1>(0h1), "") : assert_73 node _T_1310 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_74 node _T_1314 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1315 = or(UInt<1>(0h0), _T_1314) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_75 node _T_1319 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1319 : node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(source_ok_1, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1323 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1324 = asUInt(reset) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(_T_1323, UInt<1>(0h0)) when _T_1326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1323, UInt<1>(0h1), "") : assert_77 node _T_1327 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1328 = or(_T_1327, io.in.d.bits.corrupt) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_78 node _T_1332 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1333 = or(UInt<1>(0h0), _T_1332) node _T_1334 = asUInt(reset) node _T_1335 = eq(_T_1334, UInt<1>(0h0)) when _T_1335 : node _T_1336 = eq(_T_1333, UInt<1>(0h0)) when _T_1336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1333, UInt<1>(0h1), "") : assert_79 node _T_1337 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1337 : node _T_1338 = asUInt(reset) node _T_1339 = eq(_T_1338, UInt<1>(0h0)) when _T_1339 : node _T_1340 = eq(source_ok_1, UInt<1>(0h0)) when _T_1340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1341 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1342 = asUInt(reset) node _T_1343 = eq(_T_1342, UInt<1>(0h0)) when _T_1343 : node _T_1344 = eq(_T_1341, UInt<1>(0h0)) when _T_1344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1341, UInt<1>(0h1), "") : assert_81 node _T_1345 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1346 = asUInt(reset) node _T_1347 = eq(_T_1346, UInt<1>(0h0)) when _T_1347 : node _T_1348 = eq(_T_1345, UInt<1>(0h0)) when _T_1348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1345, UInt<1>(0h1), "") : assert_82 node _T_1349 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1350 = or(UInt<1>(0h0), _T_1349) node _T_1351 = asUInt(reset) node _T_1352 = eq(_T_1351, UInt<1>(0h0)) when _T_1352 : node _T_1353 = eq(_T_1350, UInt<1>(0h0)) when _T_1353 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1350, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<12>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1354 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1355 = asUInt(reset) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) when _T_1356 : node _T_1357 = eq(_T_1354, UInt<1>(0h0)) when _T_1357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1354, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<12>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1358 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1359 = asUInt(reset) node _T_1360 = eq(_T_1359, UInt<1>(0h0)) when _T_1360 : node _T_1361 = eq(_T_1358, UInt<1>(0h0)) when _T_1361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1358, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1362 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1363 = asUInt(reset) node _T_1364 = eq(_T_1363, UInt<1>(0h0)) when _T_1364 : node _T_1365 = eq(_T_1362, UInt<1>(0h0)) when _T_1365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1362, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1366 = eq(a_first, UInt<1>(0h0)) node _T_1367 = and(io.in.a.valid, _T_1366) when _T_1367 : node _T_1368 = eq(io.in.a.bits.opcode, opcode) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_87 node _T_1372 = eq(io.in.a.bits.param, param) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_88 node _T_1376 = eq(io.in.a.bits.size, size) node _T_1377 = asUInt(reset) node _T_1378 = eq(_T_1377, UInt<1>(0h0)) when _T_1378 : node _T_1379 = eq(_T_1376, UInt<1>(0h0)) when _T_1379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1376, UInt<1>(0h1), "") : assert_89 node _T_1380 = eq(io.in.a.bits.source, source) node _T_1381 = asUInt(reset) node _T_1382 = eq(_T_1381, UInt<1>(0h0)) when _T_1382 : node _T_1383 = eq(_T_1380, UInt<1>(0h0)) when _T_1383 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1380, UInt<1>(0h1), "") : assert_90 node _T_1384 = eq(io.in.a.bits.address, address) node _T_1385 = asUInt(reset) node _T_1386 = eq(_T_1385, UInt<1>(0h0)) when _T_1386 : node _T_1387 = eq(_T_1384, UInt<1>(0h0)) when _T_1387 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1384, UInt<1>(0h1), "") : assert_91 node _T_1388 = and(io.in.a.ready, io.in.a.valid) node _T_1389 = and(_T_1388, a_first) when _T_1389 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1390 = eq(d_first, UInt<1>(0h0)) node _T_1391 = and(io.in.d.valid, _T_1390) when _T_1391 : node _T_1392 = eq(io.in.d.bits.opcode, opcode_1) node _T_1393 = asUInt(reset) node _T_1394 = eq(_T_1393, UInt<1>(0h0)) when _T_1394 : node _T_1395 = eq(_T_1392, UInt<1>(0h0)) when _T_1395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1392, UInt<1>(0h1), "") : assert_92 node _T_1396 = eq(io.in.d.bits.param, param_1) node _T_1397 = asUInt(reset) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(_T_1396, UInt<1>(0h0)) when _T_1399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1396, UInt<1>(0h1), "") : assert_93 node _T_1400 = eq(io.in.d.bits.size, size_1) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_94 node _T_1404 = eq(io.in.d.bits.source, source_1) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_95 node _T_1408 = eq(io.in.d.bits.sink, sink) node _T_1409 = asUInt(reset) node _T_1410 = eq(_T_1409, UInt<1>(0h0)) when _T_1410 : node _T_1411 = eq(_T_1408, UInt<1>(0h0)) when _T_1411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1408, UInt<1>(0h1), "") : assert_96 node _T_1412 = eq(io.in.d.bits.denied, denied) node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(_T_1412, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1412, UInt<1>(0h1), "") : assert_97 node _T_1416 = and(io.in.d.ready, io.in.d.valid) node _T_1417 = and(_T_1416, d_first) when _T_1417 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1418 = and(io.in.a.valid, a_first_1) node _T_1419 = and(_T_1418, UInt<1>(0h1)) when _T_1419 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1420 = and(io.in.a.ready, io.in.a.valid) node _T_1421 = and(_T_1420, a_first_1) node _T_1422 = and(_T_1421, UInt<1>(0h1)) when _T_1422 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1423 = dshr(inflight, io.in.a.bits.source) node _T_1424 = bits(_T_1423, 0, 0) node _T_1425 = eq(_T_1424, UInt<1>(0h0)) node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(_T_1425, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1425, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1429 = and(io.in.d.valid, d_first_1) node _T_1430 = and(_T_1429, UInt<1>(0h1)) node _T_1431 = eq(d_release_ack, UInt<1>(0h0)) node _T_1432 = and(_T_1430, _T_1431) when _T_1432 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1433 = and(io.in.d.ready, io.in.d.valid) node _T_1434 = and(_T_1433, d_first_1) node _T_1435 = and(_T_1434, UInt<1>(0h1)) node _T_1436 = eq(d_release_ack, UInt<1>(0h0)) node _T_1437 = and(_T_1435, _T_1436) when _T_1437 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1438 = and(io.in.d.valid, d_first_1) node _T_1439 = and(_T_1438, UInt<1>(0h1)) node _T_1440 = eq(d_release_ack, UInt<1>(0h0)) node _T_1441 = and(_T_1439, _T_1440) when _T_1441 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1442 = dshr(inflight, io.in.d.bits.source) node _T_1443 = bits(_T_1442, 0, 0) node _T_1444 = or(_T_1443, same_cycle_resp) node _T_1445 = asUInt(reset) node _T_1446 = eq(_T_1445, UInt<1>(0h0)) when _T_1446 : node _T_1447 = eq(_T_1444, UInt<1>(0h0)) when _T_1447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1444, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1448 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1449 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1450 = or(_T_1448, _T_1449) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_100 node _T_1454 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1455 = asUInt(reset) node _T_1456 = eq(_T_1455, UInt<1>(0h0)) when _T_1456 : node _T_1457 = eq(_T_1454, UInt<1>(0h0)) when _T_1457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1454, UInt<1>(0h1), "") : assert_101 else : node _T_1458 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1459 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1460 = or(_T_1458, _T_1459) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_102 node _T_1464 = eq(io.in.d.bits.size, a_size_lookup) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_103 node _T_1468 = and(io.in.d.valid, d_first_1) node _T_1469 = and(_T_1468, a_first_1) node _T_1470 = and(_T_1469, io.in.a.valid) node _T_1471 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1472 = and(_T_1470, _T_1471) node _T_1473 = eq(d_release_ack, UInt<1>(0h0)) node _T_1474 = and(_T_1472, _T_1473) when _T_1474 : node _T_1475 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1476 = or(_T_1475, io.in.a.ready) node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(_T_1476, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1476, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_60 node _T_1480 = orr(inflight) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) node _T_1482 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1483 = or(_T_1481, _T_1482) node _T_1484 = lt(watchdog, plusarg_reader.out) node _T_1485 = or(_T_1483, _T_1484) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1489 = and(io.in.a.ready, io.in.a.valid) node _T_1490 = and(io.in.d.ready, io.in.d.valid) node _T_1491 = or(_T_1489, _T_1490) when _T_1491 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<12>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<12>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<12>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1492 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<12>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1493 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1494 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1495 = and(_T_1493, _T_1494) node _T_1496 = and(_T_1492, _T_1495) when _T_1496 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<12>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1497 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1498 = and(_T_1497, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<12>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1499 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1500 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1501 = and(_T_1499, _T_1500) node _T_1502 = and(_T_1498, _T_1501) when _T_1502 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<12>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<12>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1503 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1504 = bits(_T_1503, 0, 0) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) node _T_1506 = asUInt(reset) node _T_1507 = eq(_T_1506, UInt<1>(0h0)) when _T_1507 : node _T_1508 = eq(_T_1505, UInt<1>(0h0)) when _T_1508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1505, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1509 = and(io.in.d.valid, d_first_2) node _T_1510 = and(_T_1509, UInt<1>(0h1)) node _T_1511 = and(_T_1510, d_release_ack_1) when _T_1511 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1512 = and(io.in.d.ready, io.in.d.valid) node _T_1513 = and(_T_1512, d_first_2) node _T_1514 = and(_T_1513, UInt<1>(0h1)) node _T_1515 = and(_T_1514, d_release_ack_1) when _T_1515 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1516 = and(io.in.d.valid, d_first_2) node _T_1517 = and(_T_1516, UInt<1>(0h1)) node _T_1518 = and(_T_1517, d_release_ack_1) when _T_1518 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1519 = dshr(inflight_1, io.in.d.bits.source) node _T_1520 = bits(_T_1519, 0, 0) node _T_1521 = or(_T_1520, same_cycle_resp_1) node _T_1522 = asUInt(reset) node _T_1523 = eq(_T_1522, UInt<1>(0h0)) when _T_1523 : node _T_1524 = eq(_T_1521, UInt<1>(0h0)) when _T_1524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1521, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<12>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1525 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1526 = asUInt(reset) node _T_1527 = eq(_T_1526, UInt<1>(0h0)) when _T_1527 : node _T_1528 = eq(_T_1525, UInt<1>(0h0)) when _T_1528 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1525, UInt<1>(0h1), "") : assert_108 else : node _T_1529 = eq(io.in.d.bits.size, c_size_lookup) node _T_1530 = asUInt(reset) node _T_1531 = eq(_T_1530, UInt<1>(0h0)) when _T_1531 : node _T_1532 = eq(_T_1529, UInt<1>(0h0)) when _T_1532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1529, UInt<1>(0h1), "") : assert_109 node _T_1533 = and(io.in.d.valid, d_first_2) node _T_1534 = and(_T_1533, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<12>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1535 = and(_T_1534, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<12>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1536 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1537 = and(_T_1535, _T_1536) node _T_1538 = and(_T_1537, d_release_ack_1) node _T_1539 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1540 = and(_T_1538, _T_1539) when _T_1540 : node _T_1541 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<12>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1542 = or(_T_1541, _WIRE_27.ready) node _T_1543 = asUInt(reset) node _T_1544 = eq(_T_1543, UInt<1>(0h0)) when _T_1544 : node _T_1545 = eq(_T_1542, UInt<1>(0h0)) when _T_1545 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1542, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_61 node _T_1546 = orr(inflight_1) node _T_1547 = eq(_T_1546, UInt<1>(0h0)) node _T_1548 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1549 = or(_T_1547, _T_1548) node _T_1550 = lt(watchdog_1, plusarg_reader_1.out) node _T_1551 = or(_T_1549, _T_1550) node _T_1552 = asUInt(reset) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(_T_1551, UInt<1>(0h0)) when _T_1554 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1551, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<12>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1555 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1556 = and(io.in.d.ready, io.in.d.valid) node _T_1557 = or(_T_1555, _T_1556) when _T_1557 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_30( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h44; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 8'h46; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_39 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_32 = _source_ok_T_31 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_35 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_36 = _source_ok_T_34 & _source_ok_T_35; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_11 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_40 = _source_ok_T_39 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = source_ok_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_44 = _source_ok_T_42 & _source_ok_T_43; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_14 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 8'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 \| _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 \| _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 \| _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 \| _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 \| _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_63 \| _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = io_in_d_bits_source_0 == 8'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_71 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_77 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_83 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_66 = _source_ok_T_65 == 6'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 6'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 6'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 6'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h44; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 8'h46; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_95 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_103 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7] wire _source_ok_T_96 = _source_ok_T_95 == 5'h6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_99 = source_ok_uncommonBits_10 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_100 = _source_ok_T_98 & _source_ok_T_99; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_11 = _source_ok_T_100; // @[Parameters.scala:1138:31] wire _source_ok_T_101 = io_in_d_bits_source_0 == 8'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_101; // @[Parameters.scala:1138:31] wire _source_ok_T_102 = io_in_d_bits_source_0 == 8'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_107 = source_ok_uncommonBits_11 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_108 = _source_ok_T_106 & _source_ok_T_107; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_14 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 8'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 8'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_116 = _source_ok_T_115 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_117 = _source_ok_T_116 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_118 = _source_ok_T_117 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_119 = _source_ok_T_118 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_120 = _source_ok_T_119 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_121 = _source_ok_T_120 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_122 = _source_ok_T_121 \| _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_123 = _source_ok_T_122 \| _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_124 = _source_ok_T_123 \| _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_125 = _source_ok_T_124 \| _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_126 = _source_ok_T_125 \| _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_127 = _source_ok_T_126 \| _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_127 \| _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _T_1489 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1489; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1489; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1557 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1557; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1557; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1557; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1422 = _T_1489 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1422 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1422 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1422 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1422 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1422 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1468 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1468 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1437 = _T_1557 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1437 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1437 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1437 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1533 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1533 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1515 = _T_1557 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1515 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1515 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1515 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_44 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_88 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_44 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1 = and(io.in.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail invalidate route_buffer.io.enq.bits.flow.egress_node_id invalidate route_buffer.io.enq.bits.flow.egress_node invalidate route_buffer.io.enq.bits.flow.ingress_node_id invalidate route_buffer.io.enq.bits.flow.ingress_node invalidate route_buffer.io.enq.bits.flow.vnet_id connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h3)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_6 = and(io.in.ready, io.in.valid) node _T_7 = and(_T_6, io.in.bits.head) node _T_8 = and(_T_7, at_dest) when _T_8 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<4>(0h8), io.in.bits.egress_id) when _T_9 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<4>(0h9), io.in.bits.egress_id) when _T_10 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_11 = eq(UInt<4>(0ha), io.in.bits.egress_id) when _T_11 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_12 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_13 = and(route_q.io.enq.valid, _T_12) node _T_14 = eq(_T_13, UInt<1>(0h0)) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_14, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_89 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_44 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_18 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_19 = and(vcalloc_q.io.enq.valid, _T_18) node _T_20 = eq(_T_19, UInt<1>(0h0)) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_20, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _c_T = cat(c_hi, c_lo) node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node _c_T_1 = cat(c_hi_1, c_lo_1) node c_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_hi_2 = cat(c_hi_hi_1, io.out_credit_available.`0`[2]) node _c_T_2 = cat(c_hi_2, c_lo_2) node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _c_T_3 = cat(c_hi_3, c_lo_3) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_channel_oh_0 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 4, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_12, _out_bundle_bits_out_virt_channel_T_10) node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_11) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1 connect io.in.ready, UInt<1>(0h0) connect io.router_req.valid, UInt<1>(0h0) invalidate io.router_req.bits.flow.egress_node_id invalidate io.router_req.bits.flow.egress_node invalidate io.router_req.bits.flow.ingress_node_id invalidate io.router_req.bits.flow.ingress_node invalidate io.router_req.bits.flow.vnet_id invalidate io.router_req.bits.src_virt_id connect io.vcalloc_req.valid, UInt<1>(0h0) invalidate io.vcalloc_req.bits.vc_sel.`0`[0] invalidate io.vcalloc_req.bits.vc_sel.`0`[1] invalidate io.vcalloc_req.bits.vc_sel.`0`[2] invalidate io.vcalloc_req.bits.vc_sel.`0`[3] invalidate io.vcalloc_req.bits.vc_sel.`0`[4] invalidate io.vcalloc_req.bits.vc_sel.`1`[0] invalidate io.vcalloc_req.bits.vc_sel.`2`[0] invalidate io.vcalloc_req.bits.vc_sel.`3`[0] invalidate io.vcalloc_req.bits.in_vc invalidate io.vcalloc_req.bits.flow.egress_node_id invalidate io.vcalloc_req.bits.flow.egress_node invalidate io.vcalloc_req.bits.flow.ingress_node_id invalidate io.vcalloc_req.bits.flow.ingress_node invalidate io.vcalloc_req.bits.flow.vnet_id connect io.salloc_req[0].valid, UInt<1>(0h0) invalidate io.salloc_req[0].bits.tail invalidate io.salloc_req[0].bits.vc_sel.`0`[0] invalidate io.salloc_req[0].bits.vc_sel.`0`[1] invalidate io.salloc_req[0].bits.vc_sel.`0`[2] invalidate io.salloc_req[0].bits.vc_sel.`0`[3] invalidate io.salloc_req[0].bits.vc_sel.`0`[4] invalidate io.salloc_req[0].bits.vc_sel.`1`[0] invalidate io.salloc_req[0].bits.vc_sel.`2`[0] invalidate io.salloc_req[0].bits.vc_sel.`3`[0] connect io.out[0].valid, UInt<1>(0h0) invalidate io.out[0].bits.out_virt_channel invalidate io.out[0].bits.flit.virt_channel_id invalidate io.out[0].bits.flit.flow.egress_node_id invalidate io.out[0].bits.flit.flow.egress_node invalidate io.out[0].bits.flit.flow.ingress_node_id invalidate io.out[0].bits.flit.flow.ingress_node invalidate io.out[0].bits.flit.flow.vnet_id invalidate io.out[0].bits.flit.payload invalidate io.out[0].bits.flit.tail invalidate io.out[0].bits.flit.head	module IngressUnit_44( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset // @[IngressUnit.scala:11:7] ); endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_20 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[42] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 connect _source_ok_WIRE[41], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40]) node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_353, _T_358) node _T_360 = and(_T_11, _T_24) node _T_361 = and(_T_360, _T_37) node _T_362 = and(_T_361, _T_50) node _T_363 = and(_T_362, _T_63) node _T_364 = and(_T_363, _T_71) node _T_365 = and(_T_364, _T_79) node _T_366 = and(_T_365, _T_87) node _T_367 = and(_T_366, _T_95) node _T_368 = and(_T_367, _T_103) node _T_369 = and(_T_368, _T_111) node _T_370 = and(_T_369, _T_119) node _T_371 = and(_T_370, _T_127) node _T_372 = and(_T_371, _T_135) node _T_373 = and(_T_372, _T_143) node _T_374 = and(_T_373, _T_151) node _T_375 = and(_T_374, _T_159) node _T_376 = and(_T_375, _T_167) node _T_377 = and(_T_376, _T_175) node _T_378 = and(_T_377, _T_183) node _T_379 = and(_T_378, _T_191) node _T_380 = and(_T_379, _T_199) node _T_381 = and(_T_380, _T_207) node _T_382 = and(_T_381, _T_215) node _T_383 = and(_T_382, _T_223) node _T_384 = and(_T_383, _T_231) node _T_385 = and(_T_384, _T_239) node _T_386 = and(_T_385, _T_247) node _T_387 = and(_T_386, _T_255) node _T_388 = and(_T_387, _T_263) node _T_389 = and(_T_388, _T_271) node _T_390 = and(_T_389, _T_279) node _T_391 = and(_T_390, _T_287) node _T_392 = and(_T_391, _T_295) node _T_393 = and(_T_392, _T_303) node _T_394 = and(_T_393, _T_311) node _T_395 = and(_T_394, _T_319) node _T_396 = and(_T_395, _T_327) node _T_397 = and(_T_396, _T_335) node _T_398 = and(_T_397, _T_343) node _T_399 = and(_T_398, _T_351) node _T_400 = and(_T_399, _T_359) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_400, UInt<1>(0h1), "") : assert_1 node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_404 : node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_4) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_414 = and(_T_412, _T_413) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h1)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_5) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<2>(0h2)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_6) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h3)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_7) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_470 = or(_T_408, _T_414) node _T_471 = or(_T_470, _T_420) node _T_472 = or(_T_471, _T_426) node _T_473 = or(_T_472, _T_432) node _T_474 = or(_T_473, _T_433) node _T_475 = or(_T_474, _T_434) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_436) node _T_478 = or(_T_477, _T_437) node _T_479 = or(_T_478, _T_438) node _T_480 = or(_T_479, _T_439) node _T_481 = or(_T_480, _T_440) node _T_482 = or(_T_481, _T_441) node _T_483 = or(_T_482, _T_442) node _T_484 = or(_T_483, _T_443) node _T_485 = or(_T_484, _T_444) node _T_486 = or(_T_485, _T_445) node _T_487 = or(_T_486, _T_446) node _T_488 = or(_T_487, _T_447) node _T_489 = or(_T_488, _T_448) node _T_490 = or(_T_489, _T_449) node _T_491 = or(_T_490, _T_450) node _T_492 = or(_T_491, _T_451) node _T_493 = or(_T_492, _T_452) node _T_494 = or(_T_493, _T_453) node _T_495 = or(_T_494, _T_454) node _T_496 = or(_T_495, _T_455) node _T_497 = or(_T_496, _T_456) node _T_498 = or(_T_497, _T_457) node _T_499 = or(_T_498, _T_458) node _T_500 = or(_T_499, _T_459) node _T_501 = or(_T_500, _T_460) node _T_502 = or(_T_501, _T_461) node _T_503 = or(_T_502, _T_462) node _T_504 = or(_T_503, _T_463) node _T_505 = or(_T_504, _T_464) node _T_506 = or(_T_505, _T_465) node _T_507 = or(_T_506, _T_466) node _T_508 = or(_T_507, _T_467) node _T_509 = or(_T_508, _T_468) node _T_510 = or(_T_509, _T_469) node _T_511 = and(_T_407, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_T_512, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_521, UInt<1>(0h1), "") : assert_2 node _T_525 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<1>(0h0)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_8) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<1>(0h1)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_9) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<2>(0h2)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_10) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<2>(0h3)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_11) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_553 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_554 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_555 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_557 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_559 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_560 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_561 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_562 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_569 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_576 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_586 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[42] connect _WIRE[0], _T_525 connect _WIRE[1], _T_531 connect _WIRE[2], _T_537 connect _WIRE[3], _T_543 connect _WIRE[4], _T_549 connect _WIRE[5], _T_550 connect _WIRE[6], _T_551 connect _WIRE[7], _T_552 connect _WIRE[8], _T_553 connect _WIRE[9], _T_554 connect _WIRE[10], _T_555 connect _WIRE[11], _T_556 connect _WIRE[12], _T_557 connect _WIRE[13], _T_558 connect _WIRE[14], _T_559 connect _WIRE[15], _T_560 connect _WIRE[16], _T_561 connect _WIRE[17], _T_562 connect _WIRE[18], _T_563 connect _WIRE[19], _T_564 connect _WIRE[20], _T_565 connect _WIRE[21], _T_566 connect _WIRE[22], _T_567 connect _WIRE[23], _T_568 connect _WIRE[24], _T_569 connect _WIRE[25], _T_570 connect _WIRE[26], _T_571 connect _WIRE[27], _T_572 connect _WIRE[28], _T_573 connect _WIRE[29], _T_574 connect _WIRE[30], _T_575 connect _WIRE[31], _T_576 connect _WIRE[32], _T_577 connect _WIRE[33], _T_578 connect _WIRE[34], _T_579 connect _WIRE[35], _T_580 connect _WIRE[36], _T_581 connect _WIRE[37], _T_582 connect _WIRE[38], _T_583 connect _WIRE[39], _T_584 connect _WIRE[40], _T_585 connect _WIRE[41], _T_586 node _T_587 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_588 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_589 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_590 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_591 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_592 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_593 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_594 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_595 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_596 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_597 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_598 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_599 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_600 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_601 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_602 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_603 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_604 = mux(_WIRE[5], _T_587, UInt<1>(0h0)) node _T_605 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_606 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_607 = mux(_WIRE[8], _T_588, UInt<1>(0h0)) node _T_608 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_609 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_610 = mux(_WIRE[11], _T_589, UInt<1>(0h0)) node _T_611 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_612 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = mux(_WIRE[14], _T_590, UInt<1>(0h0)) node _T_614 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_615 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = mux(_WIRE[17], _T_591, UInt<1>(0h0)) node _T_617 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_618 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_619 = mux(_WIRE[20], _T_592, UInt<1>(0h0)) node _T_620 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_621 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = mux(_WIRE[23], _T_593, UInt<1>(0h0)) node _T_623 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_624 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_625 = mux(_WIRE[26], _T_594, UInt<1>(0h0)) node _T_626 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_627 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_628 = mux(_WIRE[29], _T_595, UInt<1>(0h0)) node _T_629 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[32], _T_596, UInt<1>(0h0)) node _T_632 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[35], _T_597, UInt<1>(0h0)) node _T_635 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[38], _T_598, UInt<1>(0h0)) node _T_638 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_641 = or(_T_599, _T_600) node _T_642 = or(_T_641, _T_601) node _T_643 = or(_T_642, _T_602) node _T_644 = or(_T_643, _T_603) node _T_645 = or(_T_644, _T_604) node _T_646 = or(_T_645, _T_605) node _T_647 = or(_T_646, _T_606) node _T_648 = or(_T_647, _T_607) node _T_649 = or(_T_648, _T_608) node _T_650 = or(_T_649, _T_609) node _T_651 = or(_T_650, _T_610) node _T_652 = or(_T_651, _T_611) node _T_653 = or(_T_652, _T_612) node _T_654 = or(_T_653, _T_613) node _T_655 = or(_T_654, _T_614) node _T_656 = or(_T_655, _T_615) node _T_657 = or(_T_656, _T_616) node _T_658 = or(_T_657, _T_617) node _T_659 = or(_T_658, _T_618) node _T_660 = or(_T_659, _T_619) node _T_661 = or(_T_660, _T_620) node _T_662 = or(_T_661, _T_621) node _T_663 = or(_T_662, _T_622) node _T_664 = or(_T_663, _T_623) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_625) node _T_667 = or(_T_666, _T_626) node _T_668 = or(_T_667, _T_627) node _T_669 = or(_T_668, _T_628) node _T_670 = or(_T_669, _T_629) node _T_671 = or(_T_670, _T_630) node _T_672 = or(_T_671, _T_631) node _T_673 = or(_T_672, _T_632) node _T_674 = or(_T_673, _T_633) node _T_675 = or(_T_674, _T_634) node _T_676 = or(_T_675, _T_635) node _T_677 = or(_T_676, _T_636) node _T_678 = or(_T_677, _T_637) node _T_679 = or(_T_678, _T_638) node _T_680 = or(_T_679, _T_639) node _T_681 = or(_T_680, _T_640) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_681 node _T_682 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_683 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_684 = and(_T_682, _T_683) node _T_685 = or(UInt<1>(0h0), _T_684) node _T_686 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = and(_T_685, _T_690) node _T_692 = or(UInt<1>(0h0), _T_691) node _T_693 = and(_WIRE_1, _T_692) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_693, UInt<1>(0h1), "") : assert_3 node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(source_ok, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_700 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_700, UInt<1>(0h1), "") : assert_5 node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(is_aligned, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_707 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_707, UInt<1>(0h1), "") : assert_7 node _T_711 = not(io.in.a.bits.mask) node _T_712 = eq(_T_711, UInt<1>(0h0)) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_712, UInt<1>(0h1), "") : assert_8 node _T_716 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(_T_716, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_716, UInt<1>(0h1), "") : assert_9 node _T_720 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_720 : node _T_721 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_722 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_725 = shr(io.in.a.bits.source, 2) node _T_726 = eq(_T_725, UInt<1>(0h0)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_12) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_731 = shr(io.in.a.bits.source, 2) node _T_732 = eq(_T_731, UInt<1>(0h1)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_13) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<2>(0h2)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_14) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<2>(0h3)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_15) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_750 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_751 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_752 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_754 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_755 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_756 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_757 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_758 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_759 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_760 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_763 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_767 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_770 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_771 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_772 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_776 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_777 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_786 = or(_T_724, _T_730) node _T_787 = or(_T_786, _T_736) node _T_788 = or(_T_787, _T_742) node _T_789 = or(_T_788, _T_748) node _T_790 = or(_T_789, _T_749) node _T_791 = or(_T_790, _T_750) node _T_792 = or(_T_791, _T_751) node _T_793 = or(_T_792, _T_752) node _T_794 = or(_T_793, _T_753) node _T_795 = or(_T_794, _T_754) node _T_796 = or(_T_795, _T_755) node _T_797 = or(_T_796, _T_756) node _T_798 = or(_T_797, _T_757) node _T_799 = or(_T_798, _T_758) node _T_800 = or(_T_799, _T_759) node _T_801 = or(_T_800, _T_760) node _T_802 = or(_T_801, _T_761) node _T_803 = or(_T_802, _T_762) node _T_804 = or(_T_803, _T_763) node _T_805 = or(_T_804, _T_764) node _T_806 = or(_T_805, _T_765) node _T_807 = or(_T_806, _T_766) node _T_808 = or(_T_807, _T_767) node _T_809 = or(_T_808, _T_768) node _T_810 = or(_T_809, _T_769) node _T_811 = or(_T_810, _T_770) node _T_812 = or(_T_811, _T_771) node _T_813 = or(_T_812, _T_772) node _T_814 = or(_T_813, _T_773) node _T_815 = or(_T_814, _T_774) node _T_816 = or(_T_815, _T_775) node _T_817 = or(_T_816, _T_776) node _T_818 = or(_T_817, _T_777) node _T_819 = or(_T_818, _T_778) node _T_820 = or(_T_819, _T_779) node _T_821 = or(_T_820, _T_780) node _T_822 = or(_T_821, _T_781) node _T_823 = or(_T_822, _T_782) node _T_824 = or(_T_823, _T_783) node _T_825 = or(_T_824, _T_784) node _T_826 = or(_T_825, _T_785) node _T_827 = and(_T_723, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = and(_T_829, _T_834) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = and(_T_828, _T_836) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_837, UInt<1>(0h1), "") : assert_10 node _T_841 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<1>(0h0)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_16) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_848 = shr(io.in.a.bits.source, 2) node _T_849 = eq(_T_848, UInt<1>(0h1)) node _T_850 = leq(UInt<1>(0h0), uncommonBits_17) node _T_851 = and(_T_849, _T_850) node _T_852 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_853 = and(_T_851, _T_852) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_854 = shr(io.in.a.bits.source, 2) node _T_855 = eq(_T_854, UInt<2>(0h2)) node _T_856 = leq(UInt<1>(0h0), uncommonBits_18) node _T_857 = and(_T_855, _T_856) node _T_858 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_859 = and(_T_857, _T_858) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<2>(0h3)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_19) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _T_866 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_867 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_868 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_869 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_871 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_872 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_873 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_874 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_875 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_876 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_878 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_879 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_888 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_889 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_890 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_894 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_895 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_896 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_897 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_902 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[42] connect _WIRE_2[0], _T_841 connect _WIRE_2[1], _T_847 connect _WIRE_2[2], _T_853 connect _WIRE_2[3], _T_859 connect _WIRE_2[4], _T_865 connect _WIRE_2[5], _T_866 connect _WIRE_2[6], _T_867 connect _WIRE_2[7], _T_868 connect _WIRE_2[8], _T_869 connect _WIRE_2[9], _T_870 connect _WIRE_2[10], _T_871 connect _WIRE_2[11], _T_872 connect _WIRE_2[12], _T_873 connect _WIRE_2[13], _T_874 connect _WIRE_2[14], _T_875 connect _WIRE_2[15], _T_876 connect _WIRE_2[16], _T_877 connect _WIRE_2[17], _T_878 connect _WIRE_2[18], _T_879 connect _WIRE_2[19], _T_880 connect _WIRE_2[20], _T_881 connect _WIRE_2[21], _T_882 connect _WIRE_2[22], _T_883 connect _WIRE_2[23], _T_884 connect _WIRE_2[24], _T_885 connect _WIRE_2[25], _T_886 connect _WIRE_2[26], _T_887 connect _WIRE_2[27], _T_888 connect _WIRE_2[28], _T_889 connect _WIRE_2[29], _T_890 connect _WIRE_2[30], _T_891 connect _WIRE_2[31], _T_892 connect _WIRE_2[32], _T_893 connect _WIRE_2[33], _T_894 connect _WIRE_2[34], _T_895 connect _WIRE_2[35], _T_896 connect _WIRE_2[36], _T_897 connect _WIRE_2[37], _T_898 connect _WIRE_2[38], _T_899 connect _WIRE_2[39], _T_900 connect _WIRE_2[40], _T_901 connect _WIRE_2[41], _T_902 node _T_903 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_904 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_905 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_906 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_907 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_908 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_909 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_910 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_911 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_912 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_913 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_914 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_915 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_916 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_919 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_920 = mux(_WIRE_2[5], _T_903, UInt<1>(0h0)) node _T_921 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_923 = mux(_WIRE_2[8], _T_904, UInt<1>(0h0)) node _T_924 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_925 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_926 = mux(_WIRE_2[11], _T_905, UInt<1>(0h0)) node _T_927 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_928 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_929 = mux(_WIRE_2[14], _T_906, UInt<1>(0h0)) node _T_930 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_931 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_932 = mux(_WIRE_2[17], _T_907, UInt<1>(0h0)) node _T_933 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_934 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_935 = mux(_WIRE_2[20], _T_908, UInt<1>(0h0)) node _T_936 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_937 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_938 = mux(_WIRE_2[23], _T_909, UInt<1>(0h0)) node _T_939 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_940 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_941 = mux(_WIRE_2[26], _T_910, UInt<1>(0h0)) node _T_942 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_943 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_944 = mux(_WIRE_2[29], _T_911, UInt<1>(0h0)) node _T_945 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_947 = mux(_WIRE_2[32], _T_912, UInt<1>(0h0)) node _T_948 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_949 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_950 = mux(_WIRE_2[35], _T_913, UInt<1>(0h0)) node _T_951 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_952 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_953 = mux(_WIRE_2[38], _T_914, UInt<1>(0h0)) node _T_954 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_955 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_956 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_957 = or(_T_915, _T_916) node _T_958 = or(_T_957, _T_917) node _T_959 = or(_T_958, _T_918) node _T_960 = or(_T_959, _T_919) node _T_961 = or(_T_960, _T_920) node _T_962 = or(_T_961, _T_921) node _T_963 = or(_T_962, _T_922) node _T_964 = or(_T_963, _T_923) node _T_965 = or(_T_964, _T_924) node _T_966 = or(_T_965, _T_925) node _T_967 = or(_T_966, _T_926) node _T_968 = or(_T_967, _T_927) node _T_969 = or(_T_968, _T_928) node _T_970 = or(_T_969, _T_929) node _T_971 = or(_T_970, _T_930) node _T_972 = or(_T_971, _T_931) node _T_973 = or(_T_972, _T_932) node _T_974 = or(_T_973, _T_933) node _T_975 = or(_T_974, _T_934) node _T_976 = or(_T_975, _T_935) node _T_977 = or(_T_976, _T_936) node _T_978 = or(_T_977, _T_937) node _T_979 = or(_T_978, _T_938) node _T_980 = or(_T_979, _T_939) node _T_981 = or(_T_980, _T_940) node _T_982 = or(_T_981, _T_941) node _T_983 = or(_T_982, _T_942) node _T_984 = or(_T_983, _T_943) node _T_985 = or(_T_984, _T_944) node _T_986 = or(_T_985, _T_945) node _T_987 = or(_T_986, _T_946) node _T_988 = or(_T_987, _T_947) node _T_989 = or(_T_988, _T_948) node _T_990 = or(_T_989, _T_949) node _T_991 = or(_T_990, _T_950) node _T_992 = or(_T_991, _T_951) node _T_993 = or(_T_992, _T_952) node _T_994 = or(_T_993, _T_953) node _T_995 = or(_T_994, _T_954) node _T_996 = or(_T_995, _T_955) node _T_997 = or(_T_996, _T_956) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_997 node _T_998 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_999 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = or(UInt<1>(0h0), _T_1000) node _T_1002 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<13>(0h1000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = and(_T_1001, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = and(_WIRE_3, _T_1008) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_11 node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(source_ok, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1016 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_13 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(is_aligned, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1023 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_15 node _T_1027 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_16 node _T_1031 = not(io.in.a.bits.mask) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_17 node _T_1036 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_18 node _T_1040 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1040 : node _T_1041 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1042 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1045 = shr(io.in.a.bits.source, 2) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) node _T_1047 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1048 = and(_T_1046, _T_1047) node _T_1049 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1050 = and(_T_1048, _T_1049) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1051 = shr(io.in.a.bits.source, 2) node _T_1052 = eq(_T_1051, UInt<1>(0h1)) node _T_1053 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1054 = and(_T_1052, _T_1053) node _T_1055 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1056 = and(_T_1054, _T_1055) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1057 = shr(io.in.a.bits.source, 2) node _T_1058 = eq(_T_1057, UInt<2>(0h2)) node _T_1059 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1062 = and(_T_1060, _T_1061) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1063 = shr(io.in.a.bits.source, 2) node _T_1064 = eq(_T_1063, UInt<2>(0h3)) node _T_1065 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1070 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1071 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1072 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1073 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1075 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1076 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1077 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1078 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1079 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1080 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1091 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1092 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1093 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1094 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1095 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1096 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1097 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1099 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1100 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1102 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1105 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1106 = or(_T_1044, _T_1050) node _T_1107 = or(_T_1106, _T_1056) node _T_1108 = or(_T_1107, _T_1062) node _T_1109 = or(_T_1108, _T_1068) node _T_1110 = or(_T_1109, _T_1069) node _T_1111 = or(_T_1110, _T_1070) node _T_1112 = or(_T_1111, _T_1071) node _T_1113 = or(_T_1112, _T_1072) node _T_1114 = or(_T_1113, _T_1073) node _T_1115 = or(_T_1114, _T_1074) node _T_1116 = or(_T_1115, _T_1075) node _T_1117 = or(_T_1116, _T_1076) node _T_1118 = or(_T_1117, _T_1077) node _T_1119 = or(_T_1118, _T_1078) node _T_1120 = or(_T_1119, _T_1079) node _T_1121 = or(_T_1120, _T_1080) node _T_1122 = or(_T_1121, _T_1081) node _T_1123 = or(_T_1122, _T_1082) node _T_1124 = or(_T_1123, _T_1083) node _T_1125 = or(_T_1124, _T_1084) node _T_1126 = or(_T_1125, _T_1085) node _T_1127 = or(_T_1126, _T_1086) node _T_1128 = or(_T_1127, _T_1087) node _T_1129 = or(_T_1128, _T_1088) node _T_1130 = or(_T_1129, _T_1089) node _T_1131 = or(_T_1130, _T_1090) node _T_1132 = or(_T_1131, _T_1091) node _T_1133 = or(_T_1132, _T_1092) node _T_1134 = or(_T_1133, _T_1093) node _T_1135 = or(_T_1134, _T_1094) node _T_1136 = or(_T_1135, _T_1095) node _T_1137 = or(_T_1136, _T_1096) node _T_1138 = or(_T_1137, _T_1097) node _T_1139 = or(_T_1138, _T_1098) node _T_1140 = or(_T_1139, _T_1099) node _T_1141 = or(_T_1140, _T_1100) node _T_1142 = or(_T_1141, _T_1101) node _T_1143 = or(_T_1142, _T_1102) node _T_1144 = or(_T_1143, _T_1103) node _T_1145 = or(_T_1144, _T_1104) node _T_1146 = or(_T_1145, _T_1105) node _T_1147 = and(_T_1043, _T_1146) node _T_1148 = or(UInt<1>(0h0), _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_19 node _T_1152 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1153 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1154 = and(_T_1152, _T_1153) node _T_1155 = or(UInt<1>(0h0), _T_1154) node _T_1156 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1157 = cvt(_T_1156) node _T_1158 = and(_T_1157, asSInt(UInt<13>(0h1000))) node _T_1159 = asSInt(_T_1158) node _T_1160 = eq(_T_1159, asSInt(UInt<1>(0h0))) node _T_1161 = and(_T_1155, _T_1160) node _T_1162 = or(UInt<1>(0h0), _T_1161) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_20 node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(is_aligned, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1172 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_23 node _T_1176 = eq(io.in.a.bits.mask, mask) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_24 node _T_1180 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_25 node _T_1184 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1184 : node _T_1185 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1186 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1189 = shr(io.in.a.bits.source, 2) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) node _T_1191 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1194 = and(_T_1192, _T_1193) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1195 = shr(io.in.a.bits.source, 2) node _T_1196 = eq(_T_1195, UInt<1>(0h1)) node _T_1197 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1200 = and(_T_1198, _T_1199) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1201 = shr(io.in.a.bits.source, 2) node _T_1202 = eq(_T_1201, UInt<2>(0h2)) node _T_1203 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1206 = and(_T_1204, _T_1205) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1207 = shr(io.in.a.bits.source, 2) node _T_1208 = eq(_T_1207, UInt<2>(0h3)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1214 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1215 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1216 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1217 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1218 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1219 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1220 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1221 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1222 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1223 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1224 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1225 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1226 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1227 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1228 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1229 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1234 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1235 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1236 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1237 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1238 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1241 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1243 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1244 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1249 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1250 = or(_T_1188, _T_1194) node _T_1251 = or(_T_1250, _T_1200) node _T_1252 = or(_T_1251, _T_1206) node _T_1253 = or(_T_1252, _T_1212) node _T_1254 = or(_T_1253, _T_1213) node _T_1255 = or(_T_1254, _T_1214) node _T_1256 = or(_T_1255, _T_1215) node _T_1257 = or(_T_1256, _T_1216) node _T_1258 = or(_T_1257, _T_1217) node _T_1259 = or(_T_1258, _T_1218) node _T_1260 = or(_T_1259, _T_1219) node _T_1261 = or(_T_1260, _T_1220) node _T_1262 = or(_T_1261, _T_1221) node _T_1263 = or(_T_1262, _T_1222) node _T_1264 = or(_T_1263, _T_1223) node _T_1265 = or(_T_1264, _T_1224) node _T_1266 = or(_T_1265, _T_1225) node _T_1267 = or(_T_1266, _T_1226) node _T_1268 = or(_T_1267, _T_1227) node _T_1269 = or(_T_1268, _T_1228) node _T_1270 = or(_T_1269, _T_1229) node _T_1271 = or(_T_1270, _T_1230) node _T_1272 = or(_T_1271, _T_1231) node _T_1273 = or(_T_1272, _T_1232) node _T_1274 = or(_T_1273, _T_1233) node _T_1275 = or(_T_1274, _T_1234) node _T_1276 = or(_T_1275, _T_1235) node _T_1277 = or(_T_1276, _T_1236) node _T_1278 = or(_T_1277, _T_1237) node _T_1279 = or(_T_1278, _T_1238) node _T_1280 = or(_T_1279, _T_1239) node _T_1281 = or(_T_1280, _T_1240) node _T_1282 = or(_T_1281, _T_1241) node _T_1283 = or(_T_1282, _T_1242) node _T_1284 = or(_T_1283, _T_1243) node _T_1285 = or(_T_1284, _T_1244) node _T_1286 = or(_T_1285, _T_1245) node _T_1287 = or(_T_1286, _T_1246) node _T_1288 = or(_T_1287, _T_1247) node _T_1289 = or(_T_1288, _T_1248) node _T_1290 = or(_T_1289, _T_1249) node _T_1291 = and(_T_1187, _T_1290) node _T_1292 = or(UInt<1>(0h0), _T_1291) node _T_1293 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1294 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = or(UInt<1>(0h0), _T_1295) node _T_1297 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = and(_T_1296, _T_1301) node _T_1303 = or(UInt<1>(0h0), _T_1302) node _T_1304 = and(_T_1292, _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_26 node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(source_ok, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(is_aligned, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1314 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_29 node _T_1318 = eq(io.in.a.bits.mask, mask) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_30 node _T_1322 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1322 : node _T_1323 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1324 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1327 = shr(io.in.a.bits.source, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1332 = and(_T_1330, _T_1331) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1333 = shr(io.in.a.bits.source, 2) node _T_1334 = eq(_T_1333, UInt<1>(0h1)) node _T_1335 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1336 = and(_T_1334, _T_1335) node _T_1337 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1338 = and(_T_1336, _T_1337) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1339 = shr(io.in.a.bits.source, 2) node _T_1340 = eq(_T_1339, UInt<2>(0h2)) node _T_1341 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1342 = and(_T_1340, _T_1341) node _T_1343 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1344 = and(_T_1342, _T_1343) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1345 = shr(io.in.a.bits.source, 2) node _T_1346 = eq(_T_1345, UInt<2>(0h3)) node _T_1347 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1348 = and(_T_1346, _T_1347) node _T_1349 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1350 = and(_T_1348, _T_1349) node _T_1351 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1352 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1353 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1354 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1356 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1357 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1358 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1359 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1360 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1361 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1362 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1363 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1364 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1365 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1366 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1367 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1368 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1369 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1370 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1371 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1372 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1373 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1374 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1375 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1376 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1377 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1378 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1379 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1380 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1381 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1382 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1383 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1384 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1385 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1386 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1387 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1388 = or(_T_1326, _T_1332) node _T_1389 = or(_T_1388, _T_1338) node _T_1390 = or(_T_1389, _T_1344) node _T_1391 = or(_T_1390, _T_1350) node _T_1392 = or(_T_1391, _T_1351) node _T_1393 = or(_T_1392, _T_1352) node _T_1394 = or(_T_1393, _T_1353) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1355) node _T_1397 = or(_T_1396, _T_1356) node _T_1398 = or(_T_1397, _T_1357) node _T_1399 = or(_T_1398, _T_1358) node _T_1400 = or(_T_1399, _T_1359) node _T_1401 = or(_T_1400, _T_1360) node _T_1402 = or(_T_1401, _T_1361) node _T_1403 = or(_T_1402, _T_1362) node _T_1404 = or(_T_1403, _T_1363) node _T_1405 = or(_T_1404, _T_1364) node _T_1406 = or(_T_1405, _T_1365) node _T_1407 = or(_T_1406, _T_1366) node _T_1408 = or(_T_1407, _T_1367) node _T_1409 = or(_T_1408, _T_1368) node _T_1410 = or(_T_1409, _T_1369) node _T_1411 = or(_T_1410, _T_1370) node _T_1412 = or(_T_1411, _T_1371) node _T_1413 = or(_T_1412, _T_1372) node _T_1414 = or(_T_1413, _T_1373) node _T_1415 = or(_T_1414, _T_1374) node _T_1416 = or(_T_1415, _T_1375) node _T_1417 = or(_T_1416, _T_1376) node _T_1418 = or(_T_1417, _T_1377) node _T_1419 = or(_T_1418, _T_1378) node _T_1420 = or(_T_1419, _T_1379) node _T_1421 = or(_T_1420, _T_1380) node _T_1422 = or(_T_1421, _T_1381) node _T_1423 = or(_T_1422, _T_1382) node _T_1424 = or(_T_1423, _T_1383) node _T_1425 = or(_T_1424, _T_1384) node _T_1426 = or(_T_1425, _T_1385) node _T_1427 = or(_T_1426, _T_1386) node _T_1428 = or(_T_1427, _T_1387) node _T_1429 = and(_T_1325, _T_1428) node _T_1430 = or(UInt<1>(0h0), _T_1429) node _T_1431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1432 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = or(UInt<1>(0h0), _T_1433) node _T_1435 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<13>(0h1000))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = and(_T_1434, _T_1439) node _T_1441 = or(UInt<1>(0h0), _T_1440) node _T_1442 = and(_T_1430, _T_1441) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_31 node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(source_ok, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(is_aligned, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1452 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_34 node _T_1456 = not(mask) node _T_1457 = and(io.in.a.bits.mask, _T_1456) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(_T_1458, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1458, UInt<1>(0h1), "") : assert_35 node _T_1462 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1462 : node _T_1463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1465 = and(_T_1463, _T_1464) node _T_1466 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1467 = shr(io.in.a.bits.source, 2) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) node _T_1469 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1472 = and(_T_1470, _T_1471) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1473 = shr(io.in.a.bits.source, 2) node _T_1474 = eq(_T_1473, UInt<1>(0h1)) node _T_1475 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1476 = and(_T_1474, _T_1475) node _T_1477 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1478 = and(_T_1476, _T_1477) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1479 = shr(io.in.a.bits.source, 2) node _T_1480 = eq(_T_1479, UInt<2>(0h2)) node _T_1481 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1482 = and(_T_1480, _T_1481) node _T_1483 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1484 = and(_T_1482, _T_1483) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1485 = shr(io.in.a.bits.source, 2) node _T_1486 = eq(_T_1485, UInt<2>(0h3)) node _T_1487 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1488 = and(_T_1486, _T_1487) node _T_1489 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1490 = and(_T_1488, _T_1489) node _T_1491 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1492 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1493 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1494 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1495 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1496 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1497 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1498 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1499 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1500 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1501 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1502 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1505 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1506 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1507 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1508 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1509 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1510 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1511 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1512 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1513 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1514 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1515 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1516 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1517 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1518 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1519 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1520 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1521 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1522 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1523 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1524 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1525 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1526 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1527 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1528 = or(_T_1466, _T_1472) node _T_1529 = or(_T_1528, _T_1478) node _T_1530 = or(_T_1529, _T_1484) node _T_1531 = or(_T_1530, _T_1490) node _T_1532 = or(_T_1531, _T_1491) node _T_1533 = or(_T_1532, _T_1492) node _T_1534 = or(_T_1533, _T_1493) node _T_1535 = or(_T_1534, _T_1494) node _T_1536 = or(_T_1535, _T_1495) node _T_1537 = or(_T_1536, _T_1496) node _T_1538 = or(_T_1537, _T_1497) node _T_1539 = or(_T_1538, _T_1498) node _T_1540 = or(_T_1539, _T_1499) node _T_1541 = or(_T_1540, _T_1500) node _T_1542 = or(_T_1541, _T_1501) node _T_1543 = or(_T_1542, _T_1502) node _T_1544 = or(_T_1543, _T_1503) node _T_1545 = or(_T_1544, _T_1504) node _T_1546 = or(_T_1545, _T_1505) node _T_1547 = or(_T_1546, _T_1506) node _T_1548 = or(_T_1547, _T_1507) node _T_1549 = or(_T_1548, _T_1508) node _T_1550 = or(_T_1549, _T_1509) node _T_1551 = or(_T_1550, _T_1510) node _T_1552 = or(_T_1551, _T_1511) node _T_1553 = or(_T_1552, _T_1512) node _T_1554 = or(_T_1553, _T_1513) node _T_1555 = or(_T_1554, _T_1514) node _T_1556 = or(_T_1555, _T_1515) node _T_1557 = or(_T_1556, _T_1516) node _T_1558 = or(_T_1557, _T_1517) node _T_1559 = or(_T_1558, _T_1518) node _T_1560 = or(_T_1559, _T_1519) node _T_1561 = or(_T_1560, _T_1520) node _T_1562 = or(_T_1561, _T_1521) node _T_1563 = or(_T_1562, _T_1522) node _T_1564 = or(_T_1563, _T_1523) node _T_1565 = or(_T_1564, _T_1524) node _T_1566 = or(_T_1565, _T_1525) node _T_1567 = or(_T_1566, _T_1526) node _T_1568 = or(_T_1567, _T_1527) node _T_1569 = and(_T_1465, _T_1568) node _T_1570 = or(UInt<1>(0h0), _T_1569) node _T_1571 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1572 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1573 = cvt(_T_1572) node _T_1574 = and(_T_1573, asSInt(UInt<13>(0h1000))) node _T_1575 = asSInt(_T_1574) node _T_1576 = eq(_T_1575, asSInt(UInt<1>(0h0))) node _T_1577 = and(_T_1571, _T_1576) node _T_1578 = or(UInt<1>(0h0), _T_1577) node _T_1579 = and(_T_1570, _T_1578) node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(_T_1579, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1579, UInt<1>(0h1), "") : assert_36 node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(source_ok, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(is_aligned, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1589 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_39 node _T_1593 = eq(io.in.a.bits.mask, mask) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_40 node _T_1597 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1597 : node _T_1598 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1599 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1600 = and(_T_1598, _T_1599) node _T_1601 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1602 = shr(io.in.a.bits.source, 2) node _T_1603 = eq(_T_1602, UInt<1>(0h0)) node _T_1604 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1605 = and(_T_1603, _T_1604) node _T_1606 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1607 = and(_T_1605, _T_1606) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1608 = shr(io.in.a.bits.source, 2) node _T_1609 = eq(_T_1608, UInt<1>(0h1)) node _T_1610 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1613 = and(_T_1611, _T_1612) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1614 = shr(io.in.a.bits.source, 2) node _T_1615 = eq(_T_1614, UInt<2>(0h2)) node _T_1616 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1617 = and(_T_1615, _T_1616) node _T_1618 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1619 = and(_T_1617, _T_1618) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1620 = shr(io.in.a.bits.source, 2) node _T_1621 = eq(_T_1620, UInt<2>(0h3)) node _T_1622 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1625 = and(_T_1623, _T_1624) node _T_1626 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1627 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1628 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1629 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1630 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1631 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1632 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1633 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1634 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1635 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1636 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1637 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1638 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1639 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1640 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1641 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1642 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1643 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1644 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1645 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1646 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1647 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1648 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1649 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1650 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1651 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1652 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1653 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1655 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1656 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1657 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1658 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1659 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1660 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1661 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1662 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1663 = or(_T_1601, _T_1607) node _T_1664 = or(_T_1663, _T_1613) node _T_1665 = or(_T_1664, _T_1619) node _T_1666 = or(_T_1665, _T_1625) node _T_1667 = or(_T_1666, _T_1626) node _T_1668 = or(_T_1667, _T_1627) node _T_1669 = or(_T_1668, _T_1628) node _T_1670 = or(_T_1669, _T_1629) node _T_1671 = or(_T_1670, _T_1630) node _T_1672 = or(_T_1671, _T_1631) node _T_1673 = or(_T_1672, _T_1632) node _T_1674 = or(_T_1673, _T_1633) node _T_1675 = or(_T_1674, _T_1634) node _T_1676 = or(_T_1675, _T_1635) node _T_1677 = or(_T_1676, _T_1636) node _T_1678 = or(_T_1677, _T_1637) node _T_1679 = or(_T_1678, _T_1638) node _T_1680 = or(_T_1679, _T_1639) node _T_1681 = or(_T_1680, _T_1640) node _T_1682 = or(_T_1681, _T_1641) node _T_1683 = or(_T_1682, _T_1642) node _T_1684 = or(_T_1683, _T_1643) node _T_1685 = or(_T_1684, _T_1644) node _T_1686 = or(_T_1685, _T_1645) node _T_1687 = or(_T_1686, _T_1646) node _T_1688 = or(_T_1687, _T_1647) node _T_1689 = or(_T_1688, _T_1648) node _T_1690 = or(_T_1689, _T_1649) node _T_1691 = or(_T_1690, _T_1650) node _T_1692 = or(_T_1691, _T_1651) node _T_1693 = or(_T_1692, _T_1652) node _T_1694 = or(_T_1693, _T_1653) node _T_1695 = or(_T_1694, _T_1654) node _T_1696 = or(_T_1695, _T_1655) node _T_1697 = or(_T_1696, _T_1656) node _T_1698 = or(_T_1697, _T_1657) node _T_1699 = or(_T_1698, _T_1658) node _T_1700 = or(_T_1699, _T_1659) node _T_1701 = or(_T_1700, _T_1660) node _T_1702 = or(_T_1701, _T_1661) node _T_1703 = or(_T_1702, _T_1662) node _T_1704 = and(_T_1600, _T_1703) node _T_1705 = or(UInt<1>(0h0), _T_1704) node _T_1706 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1707 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1708 = cvt(_T_1707) node _T_1709 = and(_T_1708, asSInt(UInt<13>(0h1000))) node _T_1710 = asSInt(_T_1709) node _T_1711 = eq(_T_1710, asSInt(UInt<1>(0h0))) node _T_1712 = and(_T_1706, _T_1711) node _T_1713 = or(UInt<1>(0h0), _T_1712) node _T_1714 = and(_T_1705, _T_1713) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_41 node _T_1718 = asUInt(reset) node _T_1719 = eq(_T_1718, UInt<1>(0h0)) when _T_1719 : node _T_1720 = eq(source_ok, UInt<1>(0h0)) when _T_1720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1721 = asUInt(reset) node _T_1722 = eq(_T_1721, UInt<1>(0h0)) when _T_1722 : node _T_1723 = eq(is_aligned, UInt<1>(0h0)) when _T_1723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1724 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1725 = asUInt(reset) node _T_1726 = eq(_T_1725, UInt<1>(0h0)) when _T_1726 : node _T_1727 = eq(_T_1724, UInt<1>(0h0)) when _T_1727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1724, UInt<1>(0h1), "") : assert_44 node _T_1728 = eq(io.in.a.bits.mask, mask) node _T_1729 = asUInt(reset) node _T_1730 = eq(_T_1729, UInt<1>(0h0)) when _T_1730 : node _T_1731 = eq(_T_1728, UInt<1>(0h0)) when _T_1731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1728, UInt<1>(0h1), "") : assert_45 node _T_1732 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1732 : node _T_1733 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1734 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1735 = and(_T_1733, _T_1734) node _T_1736 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1737 = shr(io.in.a.bits.source, 2) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) node _T_1739 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1740 = and(_T_1738, _T_1739) node _T_1741 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1742 = and(_T_1740, _T_1741) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1743 = shr(io.in.a.bits.source, 2) node _T_1744 = eq(_T_1743, UInt<1>(0h1)) node _T_1745 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1748 = and(_T_1746, _T_1747) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1749 = shr(io.in.a.bits.source, 2) node _T_1750 = eq(_T_1749, UInt<2>(0h2)) node _T_1751 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1752 = and(_T_1750, _T_1751) node _T_1753 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1754 = and(_T_1752, _T_1753) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1755 = shr(io.in.a.bits.source, 2) node _T_1756 = eq(_T_1755, UInt<2>(0h3)) node _T_1757 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1758 = and(_T_1756, _T_1757) node _T_1759 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1760 = and(_T_1758, _T_1759) node _T_1761 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1762 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1763 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1764 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1765 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1766 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1767 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1768 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1769 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1770 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1771 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1772 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1773 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1774 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1775 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1776 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1777 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1778 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1779 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1780 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1781 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1782 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1783 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1784 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1785 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1786 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1787 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1788 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1789 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1790 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1791 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1792 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1793 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1794 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1795 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1796 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1797 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1798 = or(_T_1736, _T_1742) node _T_1799 = or(_T_1798, _T_1748) node _T_1800 = or(_T_1799, _T_1754) node _T_1801 = or(_T_1800, _T_1760) node _T_1802 = or(_T_1801, _T_1761) node _T_1803 = or(_T_1802, _T_1762) node _T_1804 = or(_T_1803, _T_1763) node _T_1805 = or(_T_1804, _T_1764) node _T_1806 = or(_T_1805, _T_1765) node _T_1807 = or(_T_1806, _T_1766) node _T_1808 = or(_T_1807, _T_1767) node _T_1809 = or(_T_1808, _T_1768) node _T_1810 = or(_T_1809, _T_1769) node _T_1811 = or(_T_1810, _T_1770) node _T_1812 = or(_T_1811, _T_1771) node _T_1813 = or(_T_1812, _T_1772) node _T_1814 = or(_T_1813, _T_1773) node _T_1815 = or(_T_1814, _T_1774) node _T_1816 = or(_T_1815, _T_1775) node _T_1817 = or(_T_1816, _T_1776) node _T_1818 = or(_T_1817, _T_1777) node _T_1819 = or(_T_1818, _T_1778) node _T_1820 = or(_T_1819, _T_1779) node _T_1821 = or(_T_1820, _T_1780) node _T_1822 = or(_T_1821, _T_1781) node _T_1823 = or(_T_1822, _T_1782) node _T_1824 = or(_T_1823, _T_1783) node _T_1825 = or(_T_1824, _T_1784) node _T_1826 = or(_T_1825, _T_1785) node _T_1827 = or(_T_1826, _T_1786) node _T_1828 = or(_T_1827, _T_1787) node _T_1829 = or(_T_1828, _T_1788) node _T_1830 = or(_T_1829, _T_1789) node _T_1831 = or(_T_1830, _T_1790) node _T_1832 = or(_T_1831, _T_1791) node _T_1833 = or(_T_1832, _T_1792) node _T_1834 = or(_T_1833, _T_1793) node _T_1835 = or(_T_1834, _T_1794) node _T_1836 = or(_T_1835, _T_1795) node _T_1837 = or(_T_1836, _T_1796) node _T_1838 = or(_T_1837, _T_1797) node _T_1839 = and(_T_1735, _T_1838) node _T_1840 = or(UInt<1>(0h0), _T_1839) node _T_1841 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1842 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1843 = cvt(_T_1842) node _T_1844 = and(_T_1843, asSInt(UInt<13>(0h1000))) node _T_1845 = asSInt(_T_1844) node _T_1846 = eq(_T_1845, asSInt(UInt<1>(0h0))) node _T_1847 = and(_T_1841, _T_1846) node _T_1848 = or(UInt<1>(0h0), _T_1847) node _T_1849 = and(_T_1840, _T_1848) node _T_1850 = asUInt(reset) node _T_1851 = eq(_T_1850, UInt<1>(0h0)) when _T_1851 : node _T_1852 = eq(_T_1849, UInt<1>(0h0)) when _T_1852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1849, UInt<1>(0h1), "") : assert_46 node _T_1853 = asUInt(reset) node _T_1854 = eq(_T_1853, UInt<1>(0h0)) when _T_1854 : node _T_1855 = eq(source_ok, UInt<1>(0h0)) when _T_1855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1856 = asUInt(reset) node _T_1857 = eq(_T_1856, UInt<1>(0h0)) when _T_1857 : node _T_1858 = eq(is_aligned, UInt<1>(0h0)) when _T_1858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1859 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1860 = asUInt(reset) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) when _T_1861 : node _T_1862 = eq(_T_1859, UInt<1>(0h0)) when _T_1862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1859, UInt<1>(0h1), "") : assert_49 node _T_1863 = eq(io.in.a.bits.mask, mask) node _T_1864 = asUInt(reset) node _T_1865 = eq(_T_1864, UInt<1>(0h0)) when _T_1865 : node _T_1866 = eq(_T_1863, UInt<1>(0h0)) when _T_1866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1863, UInt<1>(0h1), "") : assert_50 node _T_1867 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1868 = asUInt(reset) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) when _T_1869 : node _T_1870 = eq(_T_1867, UInt<1>(0h0)) when _T_1870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1867, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1871 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1872 = asUInt(reset) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) when _T_1873 : node _T_1874 = eq(_T_1871, UInt<1>(0h0)) when _T_1874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1871, UInt<1>(0h1), "") : assert_52 node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 2) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_109 = shr(io.in.d.bits.source, 2) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_115 = shr(io.in.d.bits.source, 2) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_121 = shr(io.in.d.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[42] connect _source_ok_WIRE_1[0], _source_ok_T_102 connect _source_ok_WIRE_1[1], _source_ok_T_108 connect _source_ok_WIRE_1[2], _source_ok_T_114 connect _source_ok_WIRE_1[3], _source_ok_T_120 connect _source_ok_WIRE_1[4], _source_ok_T_126 connect _source_ok_WIRE_1[5], _source_ok_T_127 connect _source_ok_WIRE_1[6], _source_ok_T_128 connect _source_ok_WIRE_1[7], _source_ok_T_129 connect _source_ok_WIRE_1[8], _source_ok_T_130 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_132 connect _source_ok_WIRE_1[11], _source_ok_T_133 connect _source_ok_WIRE_1[12], _source_ok_T_134 connect _source_ok_WIRE_1[13], _source_ok_T_135 connect _source_ok_WIRE_1[14], _source_ok_T_136 connect _source_ok_WIRE_1[15], _source_ok_T_137 connect _source_ok_WIRE_1[16], _source_ok_T_138 connect _source_ok_WIRE_1[17], _source_ok_T_139 connect _source_ok_WIRE_1[18], _source_ok_T_140 connect _source_ok_WIRE_1[19], _source_ok_T_141 connect _source_ok_WIRE_1[20], _source_ok_T_142 connect _source_ok_WIRE_1[21], _source_ok_T_143 connect _source_ok_WIRE_1[22], _source_ok_T_144 connect _source_ok_WIRE_1[23], _source_ok_T_145 connect _source_ok_WIRE_1[24], _source_ok_T_146 connect _source_ok_WIRE_1[25], _source_ok_T_147 connect _source_ok_WIRE_1[26], _source_ok_T_148 connect _source_ok_WIRE_1[27], _source_ok_T_149 connect _source_ok_WIRE_1[28], _source_ok_T_150 connect _source_ok_WIRE_1[29], _source_ok_T_151 connect _source_ok_WIRE_1[30], _source_ok_T_152 connect _source_ok_WIRE_1[31], _source_ok_T_153 connect _source_ok_WIRE_1[32], _source_ok_T_154 connect _source_ok_WIRE_1[33], _source_ok_T_155 connect _source_ok_WIRE_1[34], _source_ok_T_156 connect _source_ok_WIRE_1[35], _source_ok_T_157 connect _source_ok_WIRE_1[36], _source_ok_T_158 connect _source_ok_WIRE_1[37], _source_ok_T_159 connect _source_ok_WIRE_1[38], _source_ok_T_160 connect _source_ok_WIRE_1[39], _source_ok_T_161 connect _source_ok_WIRE_1[40], _source_ok_T_162 connect _source_ok_WIRE_1[41], _source_ok_T_163 node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36]) node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37]) node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40]) node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1875 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1875 : node _T_1876 = asUInt(reset) node _T_1877 = eq(_T_1876, UInt<1>(0h0)) when _T_1877 : node _T_1878 = eq(source_ok_1, UInt<1>(0h0)) when _T_1878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1879 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_54 node _T_1883 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1884 = asUInt(reset) node _T_1885 = eq(_T_1884, UInt<1>(0h0)) when _T_1885 : node _T_1886 = eq(_T_1883, UInt<1>(0h0)) when _T_1886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1883, UInt<1>(0h1), "") : assert_55 node _T_1887 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1888 = asUInt(reset) node _T_1889 = eq(_T_1888, UInt<1>(0h0)) when _T_1889 : node _T_1890 = eq(_T_1887, UInt<1>(0h0)) when _T_1890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1887, UInt<1>(0h1), "") : assert_56 node _T_1891 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1892 = asUInt(reset) node _T_1893 = eq(_T_1892, UInt<1>(0h0)) when _T_1893 : node _T_1894 = eq(_T_1891, UInt<1>(0h0)) when _T_1894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1891, UInt<1>(0h1), "") : assert_57 node _T_1895 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1895 : node _T_1896 = asUInt(reset) node _T_1897 = eq(_T_1896, UInt<1>(0h0)) when _T_1897 : node _T_1898 = eq(source_ok_1, UInt<1>(0h0)) when _T_1898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1899 = asUInt(reset) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) when _T_1900 : node _T_1901 = eq(sink_ok, UInt<1>(0h0)) when _T_1901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1902 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1903 = asUInt(reset) node _T_1904 = eq(_T_1903, UInt<1>(0h0)) when _T_1904 : node _T_1905 = eq(_T_1902, UInt<1>(0h0)) when _T_1905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1902, UInt<1>(0h1), "") : assert_60 node _T_1906 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1907 = asUInt(reset) node _T_1908 = eq(_T_1907, UInt<1>(0h0)) when _T_1908 : node _T_1909 = eq(_T_1906, UInt<1>(0h0)) when _T_1909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1906, UInt<1>(0h1), "") : assert_61 node _T_1910 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1911 = asUInt(reset) node _T_1912 = eq(_T_1911, UInt<1>(0h0)) when _T_1912 : node _T_1913 = eq(_T_1910, UInt<1>(0h0)) when _T_1913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1910, UInt<1>(0h1), "") : assert_62 node _T_1914 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(_T_1914, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1914, UInt<1>(0h1), "") : assert_63 node _T_1918 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1919 = or(UInt<1>(0h0), _T_1918) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_64 node _T_1923 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1923 : node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(source_ok_1, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(sink_ok, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1930 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_67 node _T_1934 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(_T_1934, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1934, UInt<1>(0h1), "") : assert_68 node _T_1938 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1939 = asUInt(reset) node _T_1940 = eq(_T_1939, UInt<1>(0h0)) when _T_1940 : node _T_1941 = eq(_T_1938, UInt<1>(0h0)) when _T_1941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1938, UInt<1>(0h1), "") : assert_69 node _T_1942 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1943 = or(_T_1942, io.in.d.bits.corrupt) node _T_1944 = asUInt(reset) node _T_1945 = eq(_T_1944, UInt<1>(0h0)) when _T_1945 : node _T_1946 = eq(_T_1943, UInt<1>(0h0)) when _T_1946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1943, UInt<1>(0h1), "") : assert_70 node _T_1947 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1948 = or(UInt<1>(0h0), _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_71 node _T_1952 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1952 : node _T_1953 = asUInt(reset) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) when _T_1954 : node _T_1955 = eq(source_ok_1, UInt<1>(0h0)) when _T_1955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1956 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1957 = asUInt(reset) node _T_1958 = eq(_T_1957, UInt<1>(0h0)) when _T_1958 : node _T_1959 = eq(_T_1956, UInt<1>(0h0)) when _T_1959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1956, UInt<1>(0h1), "") : assert_73 node _T_1960 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(_T_1960, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1960, UInt<1>(0h1), "") : assert_74 node _T_1964 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1965 = or(UInt<1>(0h0), _T_1964) node _T_1966 = asUInt(reset) node _T_1967 = eq(_T_1966, UInt<1>(0h0)) when _T_1967 : node _T_1968 = eq(_T_1965, UInt<1>(0h0)) when _T_1968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1965, UInt<1>(0h1), "") : assert_75 node _T_1969 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1969 : node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_1, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1973 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1974 = asUInt(reset) node _T_1975 = eq(_T_1974, UInt<1>(0h0)) when _T_1975 : node _T_1976 = eq(_T_1973, UInt<1>(0h0)) when _T_1976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1973, UInt<1>(0h1), "") : assert_77 node _T_1977 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1978 = or(_T_1977, io.in.d.bits.corrupt) node _T_1979 = asUInt(reset) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) when _T_1980 : node _T_1981 = eq(_T_1978, UInt<1>(0h0)) when _T_1981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1978, UInt<1>(0h1), "") : assert_78 node _T_1982 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1983 = or(UInt<1>(0h0), _T_1982) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_79 node _T_1987 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1987 : node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(source_ok_1, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1991 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1992 = asUInt(reset) node _T_1993 = eq(_T_1992, UInt<1>(0h0)) when _T_1993 : node _T_1994 = eq(_T_1991, UInt<1>(0h0)) when _T_1994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1991, UInt<1>(0h1), "") : assert_81 node _T_1995 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_82 node _T_1999 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2000 = or(UInt<1>(0h0), _T_1999) node _T_2001 = asUInt(reset) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) when _T_2002 : node _T_2003 = eq(_T_2000, UInt<1>(0h0)) when _T_2003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2000, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2004 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2005 = asUInt(reset) node _T_2006 = eq(_T_2005, UInt<1>(0h0)) when _T_2006 : node _T_2007 = eq(_T_2004, UInt<1>(0h0)) when _T_2007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2004, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2008 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2009 = asUInt(reset) node _T_2010 = eq(_T_2009, UInt<1>(0h0)) when _T_2010 : node _T_2011 = eq(_T_2008, UInt<1>(0h0)) when _T_2011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2008, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2012 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(_T_2012, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2012, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2016 = eq(a_first, UInt<1>(0h0)) node _T_2017 = and(io.in.a.valid, _T_2016) when _T_2017 : node _T_2018 = eq(io.in.a.bits.opcode, opcode) node _T_2019 = asUInt(reset) node _T_2020 = eq(_T_2019, UInt<1>(0h0)) when _T_2020 : node _T_2021 = eq(_T_2018, UInt<1>(0h0)) when _T_2021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2018, UInt<1>(0h1), "") : assert_87 node _T_2022 = eq(io.in.a.bits.param, param) node _T_2023 = asUInt(reset) node _T_2024 = eq(_T_2023, UInt<1>(0h0)) when _T_2024 : node _T_2025 = eq(_T_2022, UInt<1>(0h0)) when _T_2025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2022, UInt<1>(0h1), "") : assert_88 node _T_2026 = eq(io.in.a.bits.size, size) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_89 node _T_2030 = eq(io.in.a.bits.source, source) node _T_2031 = asUInt(reset) node _T_2032 = eq(_T_2031, UInt<1>(0h0)) when _T_2032 : node _T_2033 = eq(_T_2030, UInt<1>(0h0)) when _T_2033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2030, UInt<1>(0h1), "") : assert_90 node _T_2034 = eq(io.in.a.bits.address, address) node _T_2035 = asUInt(reset) node _T_2036 = eq(_T_2035, UInt<1>(0h0)) when _T_2036 : node _T_2037 = eq(_T_2034, UInt<1>(0h0)) when _T_2037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2034, UInt<1>(0h1), "") : assert_91 node _T_2038 = and(io.in.a.ready, io.in.a.valid) node _T_2039 = and(_T_2038, a_first) when _T_2039 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2040 = eq(d_first, UInt<1>(0h0)) node _T_2041 = and(io.in.d.valid, _T_2040) when _T_2041 : node _T_2042 = eq(io.in.d.bits.opcode, opcode_1) node _T_2043 = asUInt(reset) node _T_2044 = eq(_T_2043, UInt<1>(0h0)) when _T_2044 : node _T_2045 = eq(_T_2042, UInt<1>(0h0)) when _T_2045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2042, UInt<1>(0h1), "") : assert_92 node _T_2046 = eq(io.in.d.bits.param, param_1) node _T_2047 = asUInt(reset) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) when _T_2048 : node _T_2049 = eq(_T_2046, UInt<1>(0h0)) when _T_2049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2046, UInt<1>(0h1), "") : assert_93 node _T_2050 = eq(io.in.d.bits.size, size_1) node _T_2051 = asUInt(reset) node _T_2052 = eq(_T_2051, UInt<1>(0h0)) when _T_2052 : node _T_2053 = eq(_T_2050, UInt<1>(0h0)) when _T_2053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2050, UInt<1>(0h1), "") : assert_94 node _T_2054 = eq(io.in.d.bits.source, source_1) node _T_2055 = asUInt(reset) node _T_2056 = eq(_T_2055, UInt<1>(0h0)) when _T_2056 : node _T_2057 = eq(_T_2054, UInt<1>(0h0)) when _T_2057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2054, UInt<1>(0h1), "") : assert_95 node _T_2058 = eq(io.in.d.bits.sink, sink) node _T_2059 = asUInt(reset) node _T_2060 = eq(_T_2059, UInt<1>(0h0)) when _T_2060 : node _T_2061 = eq(_T_2058, UInt<1>(0h0)) when _T_2061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2058, UInt<1>(0h1), "") : assert_96 node _T_2062 = eq(io.in.d.bits.denied, denied) node _T_2063 = asUInt(reset) node _T_2064 = eq(_T_2063, UInt<1>(0h0)) when _T_2064 : node _T_2065 = eq(_T_2062, UInt<1>(0h0)) when _T_2065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2062, UInt<1>(0h1), "") : assert_97 node _T_2066 = and(io.in.d.ready, io.in.d.valid) node _T_2067 = and(_T_2066, d_first) when _T_2067 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2068 = and(io.in.a.valid, a_first_1) node _T_2069 = and(_T_2068, UInt<1>(0h1)) when _T_2069 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2070 = and(io.in.a.ready, io.in.a.valid) node _T_2071 = and(_T_2070, a_first_1) node _T_2072 = and(_T_2071, UInt<1>(0h1)) when _T_2072 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2073 = dshr(inflight, io.in.a.bits.source) node _T_2074 = bits(_T_2073, 0, 0) node _T_2075 = eq(_T_2074, UInt<1>(0h0)) node _T_2076 = asUInt(reset) node _T_2077 = eq(_T_2076, UInt<1>(0h0)) when _T_2077 : node _T_2078 = eq(_T_2075, UInt<1>(0h0)) when _T_2078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2075, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2079 = and(io.in.d.valid, d_first_1) node _T_2080 = and(_T_2079, UInt<1>(0h1)) node _T_2081 = eq(d_release_ack, UInt<1>(0h0)) node _T_2082 = and(_T_2080, _T_2081) when _T_2082 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2083 = and(io.in.d.ready, io.in.d.valid) node _T_2084 = and(_T_2083, d_first_1) node _T_2085 = and(_T_2084, UInt<1>(0h1)) node _T_2086 = eq(d_release_ack, UInt<1>(0h0)) node _T_2087 = and(_T_2085, _T_2086) when _T_2087 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2088 = and(io.in.d.valid, d_first_1) node _T_2089 = and(_T_2088, UInt<1>(0h1)) node _T_2090 = eq(d_release_ack, UInt<1>(0h0)) node _T_2091 = and(_T_2089, _T_2090) when _T_2091 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2092 = dshr(inflight, io.in.d.bits.source) node _T_2093 = bits(_T_2092, 0, 0) node _T_2094 = or(_T_2093, same_cycle_resp) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2098 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2099 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2100 = or(_T_2098, _T_2099) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_100 node _T_2104 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(_T_2104, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2104, UInt<1>(0h1), "") : assert_101 else : node _T_2108 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2109 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2110 = or(_T_2108, _T_2109) node _T_2111 = asUInt(reset) node _T_2112 = eq(_T_2111, UInt<1>(0h0)) when _T_2112 : node _T_2113 = eq(_T_2110, UInt<1>(0h0)) when _T_2113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2110, UInt<1>(0h1), "") : assert_102 node _T_2114 = eq(io.in.d.bits.size, a_size_lookup) node _T_2115 = asUInt(reset) node _T_2116 = eq(_T_2115, UInt<1>(0h0)) when _T_2116 : node _T_2117 = eq(_T_2114, UInt<1>(0h0)) when _T_2117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2114, UInt<1>(0h1), "") : assert_103 node _T_2118 = and(io.in.d.valid, d_first_1) node _T_2119 = and(_T_2118, a_first_1) node _T_2120 = and(_T_2119, io.in.a.valid) node _T_2121 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2122 = and(_T_2120, _T_2121) node _T_2123 = eq(d_release_ack, UInt<1>(0h0)) node _T_2124 = and(_T_2122, _T_2123) when _T_2124 : node _T_2125 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2126 = or(_T_2125, io.in.a.ready) node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(_T_2126, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2126, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_72 node _T_2130 = orr(inflight) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) node _T_2132 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2133 = or(_T_2131, _T_2132) node _T_2134 = lt(watchdog, plusarg_reader.out) node _T_2135 = or(_T_2133, _T_2134) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2139 = and(io.in.a.ready, io.in.a.valid) node _T_2140 = and(io.in.d.ready, io.in.d.valid) node _T_2141 = or(_T_2139, _T_2140) when _T_2141 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2142 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2143 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2144 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = and(_T_2142, _T_2145) when _T_2146 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2147 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2148 = and(_T_2147, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2149 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2150 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2151 = and(_T_2149, _T_2150) node _T_2152 = and(_T_2148, _T_2151) when _T_2152 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2153 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2154 = bits(_T_2153, 0, 0) node _T_2155 = eq(_T_2154, UInt<1>(0h0)) node _T_2156 = asUInt(reset) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) when _T_2157 : node _T_2158 = eq(_T_2155, UInt<1>(0h0)) when _T_2158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2155, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2159 = and(io.in.d.valid, d_first_2) node _T_2160 = and(_T_2159, UInt<1>(0h1)) node _T_2161 = and(_T_2160, d_release_ack_1) when _T_2161 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2162 = and(io.in.d.ready, io.in.d.valid) node _T_2163 = and(_T_2162, d_first_2) node _T_2164 = and(_T_2163, UInt<1>(0h1)) node _T_2165 = and(_T_2164, d_release_ack_1) when _T_2165 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2166 = and(io.in.d.valid, d_first_2) node _T_2167 = and(_T_2166, UInt<1>(0h1)) node _T_2168 = and(_T_2167, d_release_ack_1) when _T_2168 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2169 = dshr(inflight_1, io.in.d.bits.source) node _T_2170 = bits(_T_2169, 0, 0) node _T_2171 = or(_T_2170, same_cycle_resp_1) node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(_T_2171, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2171, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2175 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_108 else : node _T_2179 = eq(io.in.d.bits.size, c_size_lookup) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_109 node _T_2183 = and(io.in.d.valid, d_first_2) node _T_2184 = and(_T_2183, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2185 = and(_T_2184, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2186 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2187 = and(_T_2185, _T_2186) node _T_2188 = and(_T_2187, d_release_ack_1) node _T_2189 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2190 = and(_T_2188, _T_2189) when _T_2190 : node _T_2191 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2192 = or(_T_2191, _WIRE_27.ready) node _T_2193 = asUInt(reset) node _T_2194 = eq(_T_2193, UInt<1>(0h0)) when _T_2194 : node _T_2195 = eq(_T_2192, UInt<1>(0h0)) when _T_2195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2192, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_73 node _T_2196 = orr(inflight_1) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) node _T_2198 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2199 = or(_T_2197, _T_2198) node _T_2200 = lt(watchdog_1, plusarg_reader_1.out) node _T_2201 = or(_T_2199, _T_2200) node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(_T_2201, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2201, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2205 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2206 = and(io.in.d.ready, io.in.d.valid) node _T_2207 = or(_T_2205, _T_2206) when _T_2207 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_217 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_234 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_217( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_234 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_5 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_uncommonBits_T = or(request.source, UInt<3>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 2, 0) node _req_clientBit_T = shr(request.source, 3) node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<3>(0h4)) node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2) node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<3>(0h4)) node req_clientBit = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<3>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 2, 0) node _probe_bit_T = shr(io.sinkc.bits.source, 3) node _probe_bit_T_1 = eq(_probe_bit_T, UInt<3>(0h4)) node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2) node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<3>(0h4)) node probe_bit = and(_probe_bit_T_3, _probe_bit_T_4) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<3>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 2, 0) node _new_clientBit_T = shr(new_request.source, 3) node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<3>(0h4)) node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2) node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<3>(0h4)) node new_clientBit = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_5( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [2:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _req_clientBit_T = request_source[5:3]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T == 3'h4; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire req_clientBit = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:56:48] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:56:48] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:56:48] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:56:48] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [2:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _probe_bit_T = io_sinkc_bits_source_0[5:3]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T == 3'h4; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire probe_bit = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:56:48] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:56:48] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [2:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _new_clientBit_T = new_request_source[5:3]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T == 3'h4; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire new_clientBit = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:56:48] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e5_s11_11 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_11 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e5_s11_11( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_11 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLCToNoC_4 : input clock : Clock input reset : Reset output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, egress_id : UInt}}} inst q of Queue1_TLBundleC_a32d64s6k5z4c_4 connect q.clock, clock connect q.reset, reset wire has_body : UInt<1> node _head_T = and(q.io.deq.ready, q.io.deq.valid) node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) node head_beats1_decode = shr(_head_beats1_decode_T_2, 3) node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0)) regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) node head_counter1 = tail(_head_counter1_T, 1) node head = eq(head_counter, UInt<1>(0h0)) node _head_last_T = eq(head_counter, UInt<1>(0h1)) node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) node head_last = or(_head_last_T, _head_last_T_1) node head_done = and(head_last, _head_T) node _head_count_T = not(head_counter1) node head_count = and(head_beats1, _head_count_T) when _head_T : node _head_counter_T = mux(head, head_beats1, head_counter1) connect head_counter, _head_counter_T node _tail_T = and(q.io.deq.ready, q.io.deq.valid) node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3) node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0)) regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) node tail_counter1 = tail(_tail_counter1_T, 1) node tail_first = eq(tail_counter, UInt<1>(0h0)) node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) node tail = or(_tail_last_T, _tail_last_T_1) node tail_done = and(tail, _tail_T) node _tail_count_T = not(tail_counter1) node tail_count = and(tail_beats1, _tail_count_T) when _tail_T : node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) connect tail_counter, _tail_counter_T node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address) node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) node const_hi = cat(const_hi_hi, q.io.deq.bits.size) node const = cat(const_hi, const_lo) regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) connect io.flit.valid, q.io.deq.valid node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) connect q.io.deq.ready, _q_io_deq_ready_T_2 node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) connect io.flit.bits.head, _io_flit_bits_head_T_1 node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) connect io.flit.bits.tail, _io_flit_bits_tail_T_2 node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T) node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2) node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_4) node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_5) node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<1>(0h0)) node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6) node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8) node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_10) node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_11) node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<7>(0h40)) node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12) node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14) node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16) node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17) node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<8>(0h80)) node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18) node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20) node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_22) node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_23) node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<8>(0hc0)) node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24) node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<9>(0hc0))) node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26) node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0))) node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28) node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29) node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0hb), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<4>(0he), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h11), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h14), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h17), UInt<1>(0h0)) node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) wire _io_flit_bits_egress_id_WIRE : UInt<5> connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE node _io_flit_bits_payload_T = mux(is_body, body, const) connect io.flit.bits.payload, _io_flit_bits_payload_T node _T = and(io.flit.ready, io.flit.valid) node _T_1 = and(_T, io.flit.bits.head) when _T_1 : connect is_body, UInt<1>(0h1) node _T_2 = and(io.flit.ready, io.flit.valid) node _T_3 = and(_T_2, io.flit.bits.tail) when _T_3 : connect is_body, UInt<1>(0h0) node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) connect has_body, has_body_opdata connect q.io.enq, io.protocol node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h20)) connect q.io.enq.bits.source, _q_io_enq_bits_source_T	module TLCToNoC_4( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0; // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 \| tail_beats1 == 9'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_18 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_18 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_18( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_18 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e11_s53_i64 : input clock : Clock input reset : Reset output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<64>, intExceptionFlags : UInt<3>} node rawIn_exp = bits(io.in, 63, 52) node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 64, 64) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node magGeOne = bits(rawIn.sExp, 11, 11) node posExp = bits(rawIn.sExp, 10, 0) node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0)) node _magJustBelowOne_T_1 = andr(posExp) node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1) node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _shiftedSig_T = bits(rawIn.sig, 51, 0) node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T) node _shiftedSig_T_2 = bits(rawIn.sExp, 5, 0) node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0)) node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3) node _alignedSig_T = shr(shiftedSig, 51) node _alignedSig_T_1 = bits(shiftedSig, 50, 0) node _alignedSig_T_2 = orr(_alignedSig_T_1) node alignedSig = cat(_alignedSig_T, _alignedSig_T_2) node _unroundedInt_T = shr(alignedSig, 2) node unroundedInt = or(UInt<64>(0h0), _unroundedInt_T) node _common_inexact_T = bits(alignedSig, 1, 0) node _common_inexact_T_1 = orr(_common_inexact_T) node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0)) node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2) node _roundIncr_near_even_T = bits(alignedSig, 2, 1) node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T) node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2) node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3) node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4) node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6) node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7) node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8) node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1) node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T) node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne) node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even) node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag) node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1) node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd) node _roundIncr_T_4 = and(rawIn.sign, common_inexact) node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4) node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5) node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0)) node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact) node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8) node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9) node _complUnroundedInt_T = not(unroundedInt) node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt) node _roundedInt_T = xor(roundIncr, rawIn.sign) node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1)) node _roundedInt_T_2 = tail(_roundedInt_T_1, 1) node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt) node _roundedInt_T_4 = and(roundingMode_odd, common_inexact) node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4) node magGeOne_atOverflowEdge = eq(posExp, UInt<6>(0h3f)) node _roundCarryBut2_T = bits(unroundedInt, 61, 0) node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T) node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr) node _common_overflow_T = geq(posExp, UInt<7>(0h40)) node _common_overflow_T_1 = bits(unroundedInt, 62, 0) node _common_overflow_T_2 = orr(_common_overflow_T_1) node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr) node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3) node _common_overflow_T_5 = eq(posExp, UInt<6>(0h3e)) node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2) node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6) node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7) node _common_overflow_T_9 = bits(unroundedInt, 62, 62) node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9) node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2) node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11) node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12) node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13) node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0)) node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign) node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr) node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17) node invalidExc = or(rawIn.isNaN, rawIn.isInf) node _overflow_T = eq(invalidExc, UInt<1>(0h0)) node overflow = and(_overflow_T, common_overflow) node _inexact_T = eq(invalidExc, UInt<1>(0h0)) node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0)) node _inexact_T_2 = and(_inexact_T, _inexact_T_1) node inexact = and(_inexact_T_2, common_inexact) node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0)) node excSign = and(_excSign_T, rawIn.sign) node _excOut_T = eq(io.signedOut, excSign) node _excOut_T_1 = mux(_excOut_T, UInt<64>(0h8000000000000000), UInt<1>(0h0)) node _excOut_T_2 = eq(excSign, UInt<1>(0h0)) node _excOut_T_3 = mux(_excOut_T_2, UInt<63>(0h7fffffffffffffff), UInt<1>(0h0)) node excOut = or(_excOut_T_1, _excOut_T_3) node _io_out_T = or(invalidExc, common_overflow) node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt) connect io.out, _io_out_T_1 node _io_intExceptionFlags_T = cat(invalidExc, overflow) node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact) connect io.intExceptionFlags, _io_intExceptionFlags_T_1	module RecFNToIN_e11_s53_i64( // @[RecFNToIN.scala:46:7] input [64:0] io_in, // @[RecFNToIN.scala:49:16] input [2:0] io_roundingMode, // @[RecFNToIN.scala:49:16] input io_signedOut, // @[RecFNToIN.scala:49:16] output [63:0] io_out, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire rawIn_isNaN = (&(io_in[63:62])) & io_in[61]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}] wire magJustBelowOne = ~(io_in[63]) & (&(io_in[62:52])); // @[RecFNToIN.scala:61:30, :62:28, :63:{27,37,47}] wire roundingMode_odd = io_roundingMode == 3'h6; // @[RecFNToIN.scala:72:53] wire [115:0] shiftedSig = {63'h0, io_in[63], io_in[51:0]} << (io_in[63] ? io_in[57:52] : 6'h0); // @[rawFloatFromRecFN.scala:61:49] wire [1:0] _roundIncr_near_even_T_6 = {shiftedSig[51], \|(shiftedSig[50:0])}; // @[RecFNToIN.scala:83:49, :89:{51,69}, :92:50] wire common_inexact = io_in[63] ? (\|_roundIncr_near_even_T_6) : (\|(io_in[63:61])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}] wire roundIncr = io_roundingMode == 3'h0 & (io_in[63] & ((&(shiftedSig[52:51])) \| (&_roundIncr_near_even_T_6)) \| magJustBelowOne & (\|_roundIncr_near_even_T_6)) \| io_roundingMode == 3'h4 & (io_in[63] & shiftedSig[51] \| magJustBelowOne) \| (io_roundingMode == 3'h2 \| roundingMode_odd) & io_in[64] & common_inexact \| io_roundingMode == 3'h3 & ~(io_in[64]) & common_inexact; // @[rawFloatFromRecFN.scala:52:53, :59:25] wire [63:0] complUnroundedInt = {64{io_in[64]}} ^ shiftedSig[115:52]; // @[rawFloatFromRecFN.scala:59:25] wire [63:0] _roundedInt_T_3 = roundIncr ^ io_in[64] ? complUnroundedInt + 64'h1 : complUnroundedInt; // @[rawFloatFromRecFN.scala:59:25] wire magGeOne_atOverflowEdge = io_in[62:52] == 11'h3F; // @[RecFNToIN.scala:62:28, :110:43] wire roundCarryBut2 = (&(shiftedSig[113:52])) & roundIncr; // @[RecFNToIN.scala:83:49, :90:52, :98:61, :99:61, :101:46, :113:{38,56,61}] wire common_overflow = io_in[63] ? (\|(io_in[62:58])) \| (io_signedOut ? (io_in[64] ? magGeOne_atOverflowEdge & ((\|(shiftedSig[114:52])) \| roundIncr) : magGeOne_atOverflowEdge \| io_in[62:52] == 11'h3E & roundCarryBut2) : io_in[64] \| magGeOne_atOverflowEdge & shiftedSig[114] & roundCarryBut2) : ~io_signedOut & io_in[64] & roundIncr; // @[rawFloatFromRecFN.scala:59:25] wire invalidExc = rawIn_isNaN \| (&(io_in[63:62])) & ~(io_in[61]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}, :57:{33,36}] wire excSign = ~rawIn_isNaN & io_in[64]; // @[rawFloatFromRecFN.scala:56:33, :59:25] assign io_out = invalidExc \| common_overflow ? {io_signedOut == excSign, {63{~excSign}}} : {_roundedInt_T_3[63:1], _roundedInt_T_3[0] \| roundingMode_odd & common_inexact}; // @[RecFNToIN.scala:46:7, :72:53, :92:29, :105:12, :108:{11,31}, :115:12, :133:34, :137:32, :139:27, :142:11, :143:{12,13}, :145:{18,30}] assign io_intExceptionFlags = {invalidExc, ~invalidExc & common_overflow, ~invalidExc & ~common_overflow & common_inexact}; // @[RecFNToIN.scala:46:7, :92:29, :115:12, :133:34, :134:{20,32}, :135:{32,35,52}, :146:52] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_6 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<4>, sa_stall : UInt<4>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} inst input_buffer of InputBuffer_6 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) connect input_buffer.io.deq[8].ready, UInt<1>(0h0) connect input_buffer.io.deq[9].ready, UInt<1>(0h0) inst route_arbiter of Arbiter10_RouteComputerReq_6 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, fifo_deps : UInt<10>}[10], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0ha)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id) when _T_10 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1) node _T_11 = eq(UInt<2>(0h2), io.in.flit[0].bits.flow.egress_node_id) when _T_11 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_12 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_12 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_13 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_13 : connect states[1].g, UInt<3>(0h2) connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_14 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_14 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_15 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_15 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_16 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_16 : connect states[5].g, UInt<3>(0h2) connect route_arbiter.io.in[6].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[6].bits.flow.egress_node_id invalidate route_arbiter.io.in[6].bits.flow.egress_node invalidate route_arbiter.io.in[6].bits.flow.ingress_node_id invalidate route_arbiter.io.in[6].bits.flow.ingress_node invalidate route_arbiter.io.in[6].bits.flow.vnet_id invalidate route_arbiter.io.in[6].bits.src_virt_id node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_17 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_17 : connect states[7].g, UInt<3>(0h2) node _route_arbiter_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h1)) connect route_arbiter.io.in[8].valid, _route_arbiter_io_in_8_valid_T connect route_arbiter.io.in[8].bits.flow.egress_node_id, states[8].flow.egress_node_id connect route_arbiter.io.in[8].bits.flow.egress_node, states[8].flow.egress_node connect route_arbiter.io.in[8].bits.flow.ingress_node_id, states[8].flow.ingress_node_id connect route_arbiter.io.in[8].bits.flow.ingress_node, states[8].flow.ingress_node connect route_arbiter.io.in[8].bits.flow.vnet_id, states[8].flow.vnet_id connect route_arbiter.io.in[8].bits.src_virt_id, UInt<4>(0h8) node _T_18 = and(route_arbiter.io.in[8].ready, route_arbiter.io.in[8].valid) when _T_18 : connect states[8].g, UInt<3>(0h2) node _route_arbiter_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h1)) connect route_arbiter.io.in[9].valid, _route_arbiter_io_in_9_valid_T connect route_arbiter.io.in[9].bits.flow.egress_node_id, states[9].flow.egress_node_id connect route_arbiter.io.in[9].bits.flow.egress_node, states[9].flow.egress_node connect route_arbiter.io.in[9].bits.flow.ingress_node_id, states[9].flow.ingress_node_id connect route_arbiter.io.in[9].bits.flow.ingress_node, states[9].flow.ingress_node connect route_arbiter.io.in[9].bits.flow.vnet_id, states[9].flow.vnet_id connect route_arbiter.io.in[9].bits.src_virt_id, UInt<4>(0h9) node _T_19 = and(route_arbiter.io.in[9].ready, route_arbiter.io.in[9].valid) when _T_19 : connect states[9].g, UInt<3>(0h2) node _T_20 = and(io.router_req.ready, io.router_req.valid) when _T_20 : node _T_21 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_21, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_25 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_25 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_26 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_26 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_27 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_27 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_28 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_28 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_29 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_29 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_30 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_30 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_31 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_31 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_32 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_32 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_33 = eq(UInt<4>(0h8), io.router_req.bits.src_virt_id) when _T_33 : connect states[8].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[8].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_34 = eq(UInt<4>(0h9), io.router_req.bits.src_virt_id) when _T_34 : connect states[9].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[9].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<10>, clock, reset, UInt<10>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}[10] wire vcalloc_vals : UInt<1>[10] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi = cat(vcalloc_filter_lo_hi_hi, vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi = cat(vcalloc_filter_hi_hi_hi, vcalloc_vals[7]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_filter_lo_hi_hi_1, vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi_1 = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_filter_hi_hi_hi_1, vcalloc_vals[7]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = bits(_vcalloc_filter_T_4, 16, 16) node _vcalloc_filter_T_22 = bits(_vcalloc_filter_T_4, 17, 17) node _vcalloc_filter_T_23 = bits(_vcalloc_filter_T_4, 18, 18) node _vcalloc_filter_T_24 = bits(_vcalloc_filter_T_4, 19, 19) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_24, UInt<20>(0h80000), UInt<20>(0h0)) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_23, UInt<20>(0h40000), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_22, UInt<20>(0h20000), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_21, UInt<20>(0h10000), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_20, UInt<20>(0h8000), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_19, UInt<20>(0h4000), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_18, UInt<20>(0h2000), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_17, UInt<20>(0h1000), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_16, UInt<20>(0h800), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_15, UInt<20>(0h400), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_14, UInt<20>(0h200), _vcalloc_filter_T_34) node _vcalloc_filter_T_36 = mux(_vcalloc_filter_T_13, UInt<20>(0h100), _vcalloc_filter_T_35) node _vcalloc_filter_T_37 = mux(_vcalloc_filter_T_12, UInt<20>(0h80), _vcalloc_filter_T_36) node _vcalloc_filter_T_38 = mux(_vcalloc_filter_T_11, UInt<20>(0h40), _vcalloc_filter_T_37) node _vcalloc_filter_T_39 = mux(_vcalloc_filter_T_10, UInt<20>(0h20), _vcalloc_filter_T_38) node _vcalloc_filter_T_40 = mux(_vcalloc_filter_T_9, UInt<20>(0h10), _vcalloc_filter_T_39) node _vcalloc_filter_T_41 = mux(_vcalloc_filter_T_8, UInt<20>(0h8), _vcalloc_filter_T_40) node _vcalloc_filter_T_42 = mux(_vcalloc_filter_T_7, UInt<20>(0h4), _vcalloc_filter_T_41) node _vcalloc_filter_T_43 = mux(_vcalloc_filter_T_6, UInt<20>(0h2), _vcalloc_filter_T_42) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<20>(0h1), _vcalloc_filter_T_43) node _vcalloc_sel_T = bits(vcalloc_filter, 9, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 10) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_35 = and(io.router_req.ready, io.router_req.valid) when _T_35 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_36 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_37 = or(_T_36, vcalloc_vals[2]) node _T_38 = or(_T_37, vcalloc_vals[3]) node _T_39 = or(_T_38, vcalloc_vals[4]) node _T_40 = or(_T_39, vcalloc_vals[5]) node _T_41 = or(_T_40, vcalloc_vals[6]) node _T_42 = or(_T_41, vcalloc_vals[7]) node _T_43 = or(_T_42, vcalloc_vals[8]) node _T_44 = or(_T_43, vcalloc_vals[9]) when _T_44 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = not(UInt<9>(0h0)) node _mask_T_12 = not(UInt<10>(0h0)) node _mask_T_13 = bits(vcalloc_sel, 0, 0) node _mask_T_14 = bits(vcalloc_sel, 1, 1) node _mask_T_15 = bits(vcalloc_sel, 2, 2) node _mask_T_16 = bits(vcalloc_sel, 3, 3) node _mask_T_17 = bits(vcalloc_sel, 4, 4) node _mask_T_18 = bits(vcalloc_sel, 5, 5) node _mask_T_19 = bits(vcalloc_sel, 6, 6) node _mask_T_20 = bits(vcalloc_sel, 7, 7) node _mask_T_21 = bits(vcalloc_sel, 8, 8) node _mask_T_22 = bits(vcalloc_sel, 9, 9) node _mask_T_23 = mux(_mask_T_13, _mask_T_3, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_14, _mask_T_4, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_15, _mask_T_5, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_16, _mask_T_6, UInt<1>(0h0)) node _mask_T_27 = mux(_mask_T_17, _mask_T_7, UInt<1>(0h0)) node _mask_T_28 = mux(_mask_T_18, _mask_T_8, UInt<1>(0h0)) node _mask_T_29 = mux(_mask_T_19, _mask_T_9, UInt<1>(0h0)) node _mask_T_30 = mux(_mask_T_20, _mask_T_10, UInt<1>(0h0)) node _mask_T_31 = mux(_mask_T_21, _mask_T_11, UInt<1>(0h0)) node _mask_T_32 = mux(_mask_T_22, _mask_T_12, UInt<1>(0h0)) node _mask_T_33 = or(_mask_T_23, _mask_T_24) node _mask_T_34 = or(_mask_T_33, _mask_T_25) node _mask_T_35 = or(_mask_T_34, _mask_T_26) node _mask_T_36 = or(_mask_T_35, _mask_T_27) node _mask_T_37 = or(_mask_T_36, _mask_T_28) node _mask_T_38 = or(_mask_T_37, _mask_T_29) node _mask_T_39 = or(_mask_T_38, _mask_T_30) node _mask_T_40 = or(_mask_T_39, _mask_T_31) node _mask_T_41 = or(_mask_T_40, _mask_T_32) wire _mask_WIRE : UInt<10> connect _mask_WIRE, _mask_T_41 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) node _io_vcalloc_req_valid_T_7 = or(_io_vcalloc_req_valid_T_6, vcalloc_vals[8]) node _io_vcalloc_req_valid_T_8 = or(_io_vcalloc_req_valid_T_7, vcalloc_vals[9]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_8 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) node _io_vcalloc_req_bits_T_8 = bits(vcalloc_sel, 8, 8) node _io_vcalloc_req_bits_T_9 = bits(vcalloc_sel, 9, 9) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[10] node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_27, _io_vcalloc_req_bits_T_19) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_40, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_42, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_36) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_37) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_38) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_50) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_57) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_66 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_76) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_92 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_98 = or(_io_vcalloc_req_bits_T_97, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_99 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_90) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_99, _io_vcalloc_req_bits_T_91) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_92) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_93) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_112 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_116 = or(_io_vcalloc_req_bits_T_115, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_117 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_117, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_110) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_111) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_112) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_113) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_114) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_123 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_126) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_127) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_133) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_160 = or(_io_vcalloc_req_bits_T_159, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_161 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_152) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_161 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_162, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_165) node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_166) node _io_vcalloc_req_bits_T_176 = or(_io_vcalloc_req_bits_T_175, _io_vcalloc_req_bits_T_167) node _io_vcalloc_req_bits_T_177 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_168) node _io_vcalloc_req_bits_T_178 = or(_io_vcalloc_req_bits_T_177, _io_vcalloc_req_bits_T_169) node _io_vcalloc_req_bits_T_179 = or(_io_vcalloc_req_bits_T_178, _io_vcalloc_req_bits_T_170) node _io_vcalloc_req_bits_T_180 = or(_io_vcalloc_req_bits_T_179, _io_vcalloc_req_bits_T_171) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_180 connect _io_vcalloc_req_bits_WIRE_2[8], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_181 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_182 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_183 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_184 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_182) node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_183) node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_184) node _io_vcalloc_req_bits_T_194 = or(_io_vcalloc_req_bits_T_193, _io_vcalloc_req_bits_T_185) node _io_vcalloc_req_bits_T_195 = or(_io_vcalloc_req_bits_T_194, _io_vcalloc_req_bits_T_186) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_195, _io_vcalloc_req_bits_T_187) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_188) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_190) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_199 connect _io_vcalloc_req_bits_WIRE_2[9], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[1] node _io_vcalloc_req_bits_T_200 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_201 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_202 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_201) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_210, _io_vcalloc_req_bits_T_202) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_203) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_218 = or(_io_vcalloc_req_bits_T_217, _io_vcalloc_req_bits_T_209) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_218 connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>[1] node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_227 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_228 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_219, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_233 = or(_io_vcalloc_req_bits_T_232, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_234 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_225) node _io_vcalloc_req_bits_T_235 = or(_io_vcalloc_req_bits_T_234, _io_vcalloc_req_bits_T_226) node _io_vcalloc_req_bits_T_236 = or(_io_vcalloc_req_bits_T_235, _io_vcalloc_req_bits_T_227) node _io_vcalloc_req_bits_T_237 = or(_io_vcalloc_req_bits_T_236, _io_vcalloc_req_bits_T_228) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_237 connect _io_vcalloc_req_bits_WIRE_15[0], _io_vcalloc_req_bits_WIRE_16 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_15 wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>[1] node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_242 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_243 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_244 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_245 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_246 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_247 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_248 = or(_io_vcalloc_req_bits_T_238, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_249 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_240) node _io_vcalloc_req_bits_T_250 = or(_io_vcalloc_req_bits_T_249, _io_vcalloc_req_bits_T_241) node _io_vcalloc_req_bits_T_251 = or(_io_vcalloc_req_bits_T_250, _io_vcalloc_req_bits_T_242) node _io_vcalloc_req_bits_T_252 = or(_io_vcalloc_req_bits_T_251, _io_vcalloc_req_bits_T_243) node _io_vcalloc_req_bits_T_253 = or(_io_vcalloc_req_bits_T_252, _io_vcalloc_req_bits_T_244) node _io_vcalloc_req_bits_T_254 = or(_io_vcalloc_req_bits_T_253, _io_vcalloc_req_bits_T_245) node _io_vcalloc_req_bits_T_255 = or(_io_vcalloc_req_bits_T_254, _io_vcalloc_req_bits_T_246) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_255, _io_vcalloc_req_bits_T_247) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_256 connect _io_vcalloc_req_bits_WIRE_17[0], _io_vcalloc_req_bits_WIRE_18 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_17 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_257 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_258 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_259 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_260 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_261 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_262 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_258) node _io_vcalloc_req_bits_T_268 = or(_io_vcalloc_req_bits_T_267, _io_vcalloc_req_bits_T_259) node _io_vcalloc_req_bits_T_269 = or(_io_vcalloc_req_bits_T_268, _io_vcalloc_req_bits_T_260) node _io_vcalloc_req_bits_T_270 = or(_io_vcalloc_req_bits_T_269, _io_vcalloc_req_bits_T_261) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_270, _io_vcalloc_req_bits_T_262) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_263) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_266) wire _io_vcalloc_req_bits_WIRE_19 : UInt<4> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_275 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_19 wire _io_vcalloc_req_bits_WIRE_20 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_vcalloc_req_bits_T_276 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_277 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_277) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_278) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_293 = or(_io_vcalloc_req_bits_T_292, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_294 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_21 : UInt<3> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_294 connect _io_vcalloc_req_bits_WIRE_20.egress_node_id, _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_302 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_303 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_304 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_295, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_308 = or(_io_vcalloc_req_bits_T_307, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_309 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_300) node _io_vcalloc_req_bits_T_310 = or(_io_vcalloc_req_bits_T_309, _io_vcalloc_req_bits_T_301) node _io_vcalloc_req_bits_T_311 = or(_io_vcalloc_req_bits_T_310, _io_vcalloc_req_bits_T_302) node _io_vcalloc_req_bits_T_312 = or(_io_vcalloc_req_bits_T_311, _io_vcalloc_req_bits_T_303) node _io_vcalloc_req_bits_T_313 = or(_io_vcalloc_req_bits_T_312, _io_vcalloc_req_bits_T_304) wire _io_vcalloc_req_bits_WIRE_22 : UInt<4> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_313 connect _io_vcalloc_req_bits_WIRE_20.egress_node, _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_317 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_318 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_319 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_320 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_321 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_322 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = or(_io_vcalloc_req_bits_T_314, _io_vcalloc_req_bits_T_315) node _io_vcalloc_req_bits_T_325 = or(_io_vcalloc_req_bits_T_324, _io_vcalloc_req_bits_T_316) node _io_vcalloc_req_bits_T_326 = or(_io_vcalloc_req_bits_T_325, _io_vcalloc_req_bits_T_317) node _io_vcalloc_req_bits_T_327 = or(_io_vcalloc_req_bits_T_326, _io_vcalloc_req_bits_T_318) node _io_vcalloc_req_bits_T_328 = or(_io_vcalloc_req_bits_T_327, _io_vcalloc_req_bits_T_319) node _io_vcalloc_req_bits_T_329 = or(_io_vcalloc_req_bits_T_328, _io_vcalloc_req_bits_T_320) node _io_vcalloc_req_bits_T_330 = or(_io_vcalloc_req_bits_T_329, _io_vcalloc_req_bits_T_321) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_330, _io_vcalloc_req_bits_T_322) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_323) wire _io_vcalloc_req_bits_WIRE_23 : UInt<3> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_332 connect _io_vcalloc_req_bits_WIRE_20.ingress_node_id, _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_333 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_334 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_335 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_336 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_337 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_334) node _io_vcalloc_req_bits_T_344 = or(_io_vcalloc_req_bits_T_343, _io_vcalloc_req_bits_T_335) node _io_vcalloc_req_bits_T_345 = or(_io_vcalloc_req_bits_T_344, _io_vcalloc_req_bits_T_336) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_345, _io_vcalloc_req_bits_T_337) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_338) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_342) wire _io_vcalloc_req_bits_WIRE_24 : UInt<4> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_351 connect _io_vcalloc_req_bits_WIRE_20.ingress_node, _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_352 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_352, _io_vcalloc_req_bits_T_353) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_368 = or(_io_vcalloc_req_bits_T_367, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_369 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_360) node _io_vcalloc_req_bits_T_370 = or(_io_vcalloc_req_bits_T_369, _io_vcalloc_req_bits_T_361) wire _io_vcalloc_req_bits_WIRE_25 : UInt<3> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_370 connect _io_vcalloc_req_bits_WIRE_20.vnet_id, _io_vcalloc_req_bits_WIRE_25 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_20 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].flow, states[0].flow node _T_45 = bits(vcalloc_sel, 0, 0) node _T_46 = and(vcalloc_vals[0], _T_45) node _T_47 = and(_T_46, io.vcalloc_req.ready) when _T_47 : connect states[0].g, UInt<3>(0h3) node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].flow, states[1].flow node _T_48 = bits(vcalloc_sel, 1, 1) node _T_49 = and(vcalloc_vals[1], _T_48) node _T_50 = and(_T_49, io.vcalloc_req.ready) when _T_50 : connect states[1].g, UInt<3>(0h3) connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`0`[3] invalidate vcalloc_reqs[2].vc_sel.`0`[4] invalidate vcalloc_reqs[2].vc_sel.`0`[5] invalidate vcalloc_reqs[2].vc_sel.`0`[6] invalidate vcalloc_reqs[2].vc_sel.`0`[7] invalidate vcalloc_reqs[2].vc_sel.`0`[8] invalidate vcalloc_reqs[2].vc_sel.`0`[9] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`2`[0] invalidate vcalloc_reqs[2].vc_sel.`3`[0] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].flow, states[3].flow node _T_51 = bits(vcalloc_sel, 3, 3) node _T_52 = and(vcalloc_vals[3], _T_51) node _T_53 = and(_T_52, io.vcalloc_req.ready) when _T_53 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].flow, states[4].flow node _T_54 = bits(vcalloc_sel, 4, 4) node _T_55 = and(vcalloc_vals[4], _T_54) node _T_56 = and(_T_55, io.vcalloc_req.ready) when _T_56 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].flow, states[5].flow node _T_57 = bits(vcalloc_sel, 5, 5) node _T_58 = and(vcalloc_vals[5], _T_57) node _T_59 = and(_T_58, io.vcalloc_req.ready) when _T_59 : connect states[5].g, UInt<3>(0h3) connect vcalloc_vals[6], UInt<1>(0h0) invalidate vcalloc_reqs[6].vc_sel.`0`[0] invalidate vcalloc_reqs[6].vc_sel.`0`[1] invalidate vcalloc_reqs[6].vc_sel.`0`[2] invalidate vcalloc_reqs[6].vc_sel.`0`[3] invalidate vcalloc_reqs[6].vc_sel.`0`[4] invalidate vcalloc_reqs[6].vc_sel.`0`[5] invalidate vcalloc_reqs[6].vc_sel.`0`[6] invalidate vcalloc_reqs[6].vc_sel.`0`[7] invalidate vcalloc_reqs[6].vc_sel.`0`[8] invalidate vcalloc_reqs[6].vc_sel.`0`[9] invalidate vcalloc_reqs[6].vc_sel.`1`[0] invalidate vcalloc_reqs[6].vc_sel.`2`[0] invalidate vcalloc_reqs[6].vc_sel.`3`[0] invalidate vcalloc_reqs[6].in_vc invalidate vcalloc_reqs[6].flow.egress_node_id invalidate vcalloc_reqs[6].flow.egress_node invalidate vcalloc_reqs[6].flow.ingress_node_id invalidate vcalloc_reqs[6].flow.ingress_node invalidate vcalloc_reqs[6].flow.vnet_id node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3` connect vcalloc_reqs[7].flow, states[7].flow node _T_60 = bits(vcalloc_sel, 7, 7) node _T_61 = and(vcalloc_vals[7], _T_60) node _T_62 = and(_T_61, io.vcalloc_req.ready) when _T_62 : connect states[7].g, UInt<3>(0h3) node _vcalloc_vals_8_T = eq(states[8].g, UInt<3>(0h2)) node _vcalloc_vals_8_T_1 = eq(states[8].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_8_T_2 = and(_vcalloc_vals_8_T, _vcalloc_vals_8_T_1) connect vcalloc_vals[8], _vcalloc_vals_8_T_2 connect vcalloc_reqs[8].in_vc, UInt<4>(0h8) connect vcalloc_reqs[8].vc_sel.`0`, states[8].vc_sel.`0` connect vcalloc_reqs[8].vc_sel.`1`, states[8].vc_sel.`1` connect vcalloc_reqs[8].vc_sel.`2`, states[8].vc_sel.`2` connect vcalloc_reqs[8].vc_sel.`3`, states[8].vc_sel.`3` connect vcalloc_reqs[8].flow, states[8].flow node _T_63 = bits(vcalloc_sel, 8, 8) node _T_64 = and(vcalloc_vals[8], _T_63) node _T_65 = and(_T_64, io.vcalloc_req.ready) when _T_65 : connect states[8].g, UInt<3>(0h3) node _vcalloc_vals_9_T = eq(states[9].g, UInt<3>(0h2)) node _vcalloc_vals_9_T_1 = eq(states[9].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_9_T_2 = and(_vcalloc_vals_9_T, _vcalloc_vals_9_T_1) connect vcalloc_vals[9], _vcalloc_vals_9_T_2 connect vcalloc_reqs[9].in_vc, UInt<4>(0h9) connect vcalloc_reqs[9].vc_sel.`0`, states[9].vc_sel.`0` connect vcalloc_reqs[9].vc_sel.`1`, states[9].vc_sel.`1` connect vcalloc_reqs[9].vc_sel.`2`, states[9].vc_sel.`2` connect vcalloc_reqs[9].vc_sel.`3`, states[9].vc_sel.`3` connect vcalloc_reqs[9].flow, states[9].flow node _T_66 = bits(vcalloc_sel, 9, 9) node _T_67 = and(vcalloc_vals[9], _T_66) node _T_68 = and(_T_67, io.vcalloc_req.ready) when _T_68 : connect states[9].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[5], vcalloc_vals[6]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(vcalloc_vals[8], vcalloc_vals[9]) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 1, 0) node _io_debug_va_stall_T_12 = add(vcalloc_vals[7], _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 1, 0) node _io_debug_va_stall_T_14 = add(_io_debug_va_stall_T_9, _io_debug_va_stall_T_13) node _io_debug_va_stall_T_15 = bits(_io_debug_va_stall_T_14, 2, 0) node _io_debug_va_stall_T_16 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_15) node _io_debug_va_stall_T_17 = bits(_io_debug_va_stall_T_16, 3, 0) node _io_debug_va_stall_T_18 = sub(_io_debug_va_stall_T_17, io.vcalloc_req.ready) node _io_debug_va_stall_T_19 = tail(_io_debug_va_stall_T_18, 1) connect io.debug.va_stall, _io_debug_va_stall_T_19 node _T_69 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_69 : node _T_70 = bits(vcalloc_sel, 0, 0) when _T_70 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_71 = eq(states[0].g, UInt<3>(0h2)) node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(_T_71, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_71, UInt<1>(0h1), "") : assert_3 node _T_75 = bits(vcalloc_sel, 1, 1) when _T_75 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) node _T_76 = eq(states[1].g, UInt<3>(0h2)) node _T_77 = asUInt(reset) node _T_78 = eq(_T_77, UInt<1>(0h0)) when _T_78 : node _T_79 = eq(_T_76, UInt<1>(0h0)) when _T_79 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_76, UInt<1>(0h1), "") : assert_4 node _T_80 = bits(vcalloc_sel, 2, 2) when _T_80 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].g, UInt<3>(0h3) node _T_81 = eq(states[2].g, UInt<3>(0h2)) node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(_T_81, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_81, UInt<1>(0h1), "") : assert_5 node _T_85 = bits(vcalloc_sel, 3, 3) when _T_85 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].g, UInt<3>(0h3) node _T_86 = eq(states[3].g, UInt<3>(0h2)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_86, UInt<1>(0h1), "") : assert_6 node _T_90 = bits(vcalloc_sel, 4, 4) when _T_90 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].g, UInt<3>(0h3) node _T_91 = eq(states[4].g, UInt<3>(0h2)) node _T_92 = asUInt(reset) node _T_93 = eq(_T_92, UInt<1>(0h0)) when _T_93 : node _T_94 = eq(_T_91, UInt<1>(0h0)) when _T_94 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_91, UInt<1>(0h1), "") : assert_7 node _T_95 = bits(vcalloc_sel, 5, 5) when _T_95 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].g, UInt<3>(0h3) node _T_96 = eq(states[5].g, UInt<3>(0h2)) node _T_97 = asUInt(reset) node _T_98 = eq(_T_97, UInt<1>(0h0)) when _T_98 : node _T_99 = eq(_T_96, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_96, UInt<1>(0h1), "") : assert_8 node _T_100 = bits(vcalloc_sel, 6, 6) when _T_100 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[6].g, UInt<3>(0h3) node _T_101 = eq(states[6].g, UInt<3>(0h2)) node _T_102 = asUInt(reset) node _T_103 = eq(_T_102, UInt<1>(0h0)) when _T_103 : node _T_104 = eq(_T_101, UInt<1>(0h0)) when _T_104 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_101, UInt<1>(0h1), "") : assert_9 node _T_105 = bits(vcalloc_sel, 7, 7) when _T_105 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[7].g, UInt<3>(0h3) node _T_106 = eq(states[7].g, UInt<3>(0h2)) node _T_107 = asUInt(reset) node _T_108 = eq(_T_107, UInt<1>(0h0)) when _T_108 : node _T_109 = eq(_T_106, UInt<1>(0h0)) when _T_109 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_106, UInt<1>(0h1), "") : assert_10 node _T_110 = bits(vcalloc_sel, 8, 8) when _T_110 : connect states[8].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[8].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[8].g, UInt<3>(0h3) node _T_111 = eq(states[8].g, UInt<3>(0h2)) node _T_112 = asUInt(reset) node _T_113 = eq(_T_112, UInt<1>(0h0)) when _T_113 : node _T_114 = eq(_T_111, UInt<1>(0h0)) when _T_114 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_11 assert(clock, _T_111, UInt<1>(0h1), "") : assert_11 node _T_115 = bits(vcalloc_sel, 9, 9) when _T_115 : connect states[9].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[9].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[9].g, UInt<3>(0h3) node _T_116 = eq(states[9].g, UInt<3>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_12 assert(clock, _T_116, UInt<1>(0h1), "") : assert_12 inst salloc_arb of SwitchArbiter_28 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0]) node credit_available_lo_hi_hi = cat(states[0].vc_sel.`0`[4], states[0].vc_sel.`0`[3]) node credit_available_lo_hi = cat(credit_available_lo_hi_hi, states[0].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[0].vc_sel.`0`[6], states[0].vc_sel.`0`[5]) node credit_available_hi_hi_hi = cat(states[0].vc_sel.`0`[9], states[0].vc_sel.`0`[8]) node credit_available_hi_hi = cat(credit_available_hi_hi_hi, states[0].vc_sel.`0`[7]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_1 = cat(states[0].vc_sel.`1`[0], _credit_available_T) node credit_available_hi_1 = cat(states[0].vc_sel.`3`[0], states[0].vc_sel.`2`[0]) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_1 = cat(credit_available_lo_hi_hi_1, io.out_credit_available.`0`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_1 = cat(credit_available_hi_hi_hi_1, io.out_credit_available.`0`[7]) node credit_available_hi_2 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_3 = cat(io.out_credit_available.`1`[0], _credit_available_T_2) node credit_available_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3) node credit_available = neq(_credit_available_T_4, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3] connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4] connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5] connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6] connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7] connect salloc_arb.io.in[0].bits.vc_sel.`0`[8], states[0].vc_sel.`0`[8] connect salloc_arb.io.in[0].bits.vc_sel.`0`[9], states[0].vc_sel.`0`[9] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_120 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_121 = and(_T_120, input_buffer.io.deq[0].bits.tail) when _T_121 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node credit_available_lo_lo_2 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi_hi_2 = cat(states[1].vc_sel.`0`[4], states[1].vc_sel.`0`[3]) node credit_available_lo_hi_2 = cat(credit_available_lo_hi_hi_2, states[1].vc_sel.`0`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[1].vc_sel.`0`[6], states[1].vc_sel.`0`[5]) node credit_available_hi_hi_hi_2 = cat(states[1].vc_sel.`0`[9], states[1].vc_sel.`0`[8]) node credit_available_hi_hi_2 = cat(credit_available_hi_hi_hi_2, states[1].vc_sel.`0`[7]) node credit_available_hi_4 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_5 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_5 = cat(states[1].vc_sel.`1`[0], _credit_available_T_5) node credit_available_hi_5 = cat(states[1].vc_sel.`3`[0], states[1].vc_sel.`2`[0]) node _credit_available_T_6 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_3 = cat(credit_available_lo_hi_hi_3, io.out_credit_available.`0`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_3 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_3 = cat(credit_available_hi_hi_hi_3, io.out_credit_available.`0`[7]) node credit_available_hi_6 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_7 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_7 = cat(io.out_credit_available.`1`[0], _credit_available_T_7) node credit_available_hi_7 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_8 = cat(credit_available_hi_7, credit_available_lo_7) node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8) node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`0`[8], states[1].vc_sel.`0`[8] connect salloc_arb.io.in[1].bits.vc_sel.`0`[9], states[1].vc_sel.`0`[9] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_122 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_123 = and(_T_122, input_buffer.io.deq[1].bits.tail) when _T_123 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`3`[0] node credit_available_lo_lo_4 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_hi_4 = cat(states[3].vc_sel.`0`[4], states[3].vc_sel.`0`[3]) node credit_available_lo_hi_4 = cat(credit_available_lo_hi_hi_4, states[3].vc_sel.`0`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(states[3].vc_sel.`0`[6], states[3].vc_sel.`0`[5]) node credit_available_hi_hi_hi_4 = cat(states[3].vc_sel.`0`[9], states[3].vc_sel.`0`[8]) node credit_available_hi_hi_4 = cat(credit_available_hi_hi_hi_4, states[3].vc_sel.`0`[7]) node credit_available_hi_8 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_10 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_9 = cat(states[3].vc_sel.`1`[0], _credit_available_T_10) node credit_available_hi_9 = cat(states[3].vc_sel.`3`[0], states[3].vc_sel.`2`[0]) node _credit_available_T_11 = cat(credit_available_hi_9, credit_available_lo_9) node credit_available_lo_lo_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_5 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_5 = cat(credit_available_lo_hi_hi_5, io.out_credit_available.`0`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_5 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_5 = cat(credit_available_hi_hi_hi_5, io.out_credit_available.`0`[7]) node credit_available_hi_10 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_12 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_11 = cat(io.out_credit_available.`1`[0], _credit_available_T_12) node credit_available_hi_11 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_13 = cat(credit_available_hi_11, credit_available_lo_11) node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13) node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`0`[8], states[3].vc_sel.`0`[8] connect salloc_arb.io.in[3].bits.vc_sel.`0`[9], states[3].vc_sel.`0`[9] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_124 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_125 = and(_T_124, input_buffer.io.deq[3].bits.tail) when _T_125 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_6 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_hi_6 = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3]) node credit_available_lo_hi_6 = cat(credit_available_lo_hi_hi_6, states[4].vc_sel.`0`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(states[4].vc_sel.`0`[6], states[4].vc_sel.`0`[5]) node credit_available_hi_hi_hi_6 = cat(states[4].vc_sel.`0`[9], states[4].vc_sel.`0`[8]) node credit_available_hi_hi_6 = cat(credit_available_hi_hi_hi_6, states[4].vc_sel.`0`[7]) node credit_available_hi_12 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6) node _credit_available_T_15 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_13 = cat(states[4].vc_sel.`1`[0], _credit_available_T_15) node credit_available_hi_13 = cat(states[4].vc_sel.`3`[0], states[4].vc_sel.`2`[0]) node _credit_available_T_16 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_lo_7 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_7 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_7 = cat(credit_available_lo_hi_hi_7, io.out_credit_available.`0`[2]) node credit_available_lo_14 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_7 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_7 = cat(credit_available_hi_hi_hi_7, io.out_credit_available.`0`[7]) node credit_available_hi_14 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7) node _credit_available_T_17 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_15 = cat(io.out_credit_available.`1`[0], _credit_available_T_17) node credit_available_hi_15 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_18 = cat(credit_available_hi_15, credit_available_lo_15) node _credit_available_T_19 = and(_credit_available_T_16, _credit_available_T_18) node credit_available_3 = neq(_credit_available_T_19, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`0`[8], states[4].vc_sel.`0`[8] connect salloc_arb.io.in[4].bits.vc_sel.`0`[9], states[4].vc_sel.`0`[9] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_126 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_127 = and(_T_126, input_buffer.io.deq[4].bits.tail) when _T_127 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_8 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_hi_8 = cat(states[5].vc_sel.`0`[4], states[5].vc_sel.`0`[3]) node credit_available_lo_hi_8 = cat(credit_available_lo_hi_hi_8, states[5].vc_sel.`0`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[5].vc_sel.`0`[6], states[5].vc_sel.`0`[5]) node credit_available_hi_hi_hi_8 = cat(states[5].vc_sel.`0`[9], states[5].vc_sel.`0`[8]) node credit_available_hi_hi_8 = cat(credit_available_hi_hi_hi_8, states[5].vc_sel.`0`[7]) node credit_available_hi_16 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8) node _credit_available_T_20 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_17 = cat(states[5].vc_sel.`1`[0], _credit_available_T_20) node credit_available_hi_17 = cat(states[5].vc_sel.`3`[0], states[5].vc_sel.`2`[0]) node _credit_available_T_21 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_lo_9 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_9 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_9 = cat(credit_available_lo_hi_hi_9, io.out_credit_available.`0`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_9 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_9 = cat(credit_available_hi_hi_hi_9, io.out_credit_available.`0`[7]) node credit_available_hi_18 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9) node _credit_available_T_22 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_19 = cat(io.out_credit_available.`1`[0], _credit_available_T_22) node credit_available_hi_19 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_23 = cat(credit_available_hi_19, credit_available_lo_19) node _credit_available_T_24 = and(_credit_available_T_21, _credit_available_T_23) node credit_available_4 = neq(_credit_available_T_24, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`0`[8], states[5].vc_sel.`0`[8] connect salloc_arb.io.in[5].bits.vc_sel.`0`[9], states[5].vc_sel.`0`[9] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_128 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_129 = and(_T_128, input_buffer.io.deq[5].bits.tail) when _T_129 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready connect salloc_arb.io.in[6].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[6].bits.tail invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[6].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[6].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[6].bits.vc_sel.`3`[0] node credit_available_lo_lo_10 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_hi_10 = cat(states[7].vc_sel.`0`[4], states[7].vc_sel.`0`[3]) node credit_available_lo_hi_10 = cat(credit_available_lo_hi_hi_10, states[7].vc_sel.`0`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[7].vc_sel.`0`[6], states[7].vc_sel.`0`[5]) node credit_available_hi_hi_hi_10 = cat(states[7].vc_sel.`0`[9], states[7].vc_sel.`0`[8]) node credit_available_hi_hi_10 = cat(credit_available_hi_hi_hi_10, states[7].vc_sel.`0`[7]) node credit_available_hi_20 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10) node _credit_available_T_25 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_21 = cat(states[7].vc_sel.`1`[0], _credit_available_T_25) node credit_available_hi_21 = cat(states[7].vc_sel.`3`[0], states[7].vc_sel.`2`[0]) node _credit_available_T_26 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_lo_11 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_11 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_11 = cat(credit_available_lo_hi_hi_11, io.out_credit_available.`0`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_11 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_11 = cat(credit_available_hi_hi_hi_11, io.out_credit_available.`0`[7]) node credit_available_hi_22 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11) node _credit_available_T_27 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_23 = cat(io.out_credit_available.`1`[0], _credit_available_T_27) node credit_available_hi_23 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_28 = cat(credit_available_hi_23, credit_available_lo_23) node _credit_available_T_29 = and(_credit_available_T_26, _credit_available_T_28) node credit_available_5 = neq(_credit_available_T_29, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_5) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`0`[8], states[7].vc_sel.`0`[8] connect salloc_arb.io.in[7].bits.vc_sel.`0`[9], states[7].vc_sel.`0`[9] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_130 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_131 = and(_T_130, input_buffer.io.deq[7].bits.tail) when _T_131 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node credit_available_lo_lo_12 = cat(states[8].vc_sel.`0`[1], states[8].vc_sel.`0`[0]) node credit_available_lo_hi_hi_12 = cat(states[8].vc_sel.`0`[4], states[8].vc_sel.`0`[3]) node credit_available_lo_hi_12 = cat(credit_available_lo_hi_hi_12, states[8].vc_sel.`0`[2]) node credit_available_lo_24 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(states[8].vc_sel.`0`[6], states[8].vc_sel.`0`[5]) node credit_available_hi_hi_hi_12 = cat(states[8].vc_sel.`0`[9], states[8].vc_sel.`0`[8]) node credit_available_hi_hi_12 = cat(credit_available_hi_hi_hi_12, states[8].vc_sel.`0`[7]) node credit_available_hi_24 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12) node _credit_available_T_30 = cat(credit_available_hi_24, credit_available_lo_24) node credit_available_lo_25 = cat(states[8].vc_sel.`1`[0], _credit_available_T_30) node credit_available_hi_25 = cat(states[8].vc_sel.`3`[0], states[8].vc_sel.`2`[0]) node _credit_available_T_31 = cat(credit_available_hi_25, credit_available_lo_25) node credit_available_lo_lo_13 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_13 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_13 = cat(credit_available_lo_hi_hi_13, io.out_credit_available.`0`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_13 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_13 = cat(credit_available_hi_hi_hi_13, io.out_credit_available.`0`[7]) node credit_available_hi_26 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13) node _credit_available_T_32 = cat(credit_available_hi_26, credit_available_lo_26) node credit_available_lo_27 = cat(io.out_credit_available.`1`[0], _credit_available_T_32) node credit_available_hi_27 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_33 = cat(credit_available_hi_27, credit_available_lo_27) node _credit_available_T_34 = and(_credit_available_T_31, _credit_available_T_33) node credit_available_6 = neq(_credit_available_T_34, UInt<1>(0h0)) node _salloc_arb_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h3)) node _salloc_arb_io_in_8_valid_T_1 = and(_salloc_arb_io_in_8_valid_T, credit_available_6) node _salloc_arb_io_in_8_valid_T_2 = and(_salloc_arb_io_in_8_valid_T_1, input_buffer.io.deq[8].valid) connect salloc_arb.io.in[8].valid, _salloc_arb_io_in_8_valid_T_2 connect salloc_arb.io.in[8].bits.vc_sel.`0`[0], states[8].vc_sel.`0`[0] connect salloc_arb.io.in[8].bits.vc_sel.`0`[1], states[8].vc_sel.`0`[1] connect salloc_arb.io.in[8].bits.vc_sel.`0`[2], states[8].vc_sel.`0`[2] connect salloc_arb.io.in[8].bits.vc_sel.`0`[3], states[8].vc_sel.`0`[3] connect salloc_arb.io.in[8].bits.vc_sel.`0`[4], states[8].vc_sel.`0`[4] connect salloc_arb.io.in[8].bits.vc_sel.`0`[5], states[8].vc_sel.`0`[5] connect salloc_arb.io.in[8].bits.vc_sel.`0`[6], states[8].vc_sel.`0`[6] connect salloc_arb.io.in[8].bits.vc_sel.`0`[7], states[8].vc_sel.`0`[7] connect salloc_arb.io.in[8].bits.vc_sel.`0`[8], states[8].vc_sel.`0`[8] connect salloc_arb.io.in[8].bits.vc_sel.`0`[9], states[8].vc_sel.`0`[9] connect salloc_arb.io.in[8].bits.vc_sel.`1`[0], states[8].vc_sel.`1`[0] connect salloc_arb.io.in[8].bits.vc_sel.`2`[0], states[8].vc_sel.`2`[0] connect salloc_arb.io.in[8].bits.vc_sel.`3`[0], states[8].vc_sel.`3`[0] connect salloc_arb.io.in[8].bits.tail, input_buffer.io.deq[8].bits.tail node _T_132 = and(salloc_arb.io.in[8].ready, salloc_arb.io.in[8].valid) node _T_133 = and(_T_132, input_buffer.io.deq[8].bits.tail) when _T_133 : connect states[8].g, UInt<3>(0h0) connect input_buffer.io.deq[8].ready, salloc_arb.io.in[8].ready node credit_available_lo_lo_14 = cat(states[9].vc_sel.`0`[1], states[9].vc_sel.`0`[0]) node credit_available_lo_hi_hi_14 = cat(states[9].vc_sel.`0`[4], states[9].vc_sel.`0`[3]) node credit_available_lo_hi_14 = cat(credit_available_lo_hi_hi_14, states[9].vc_sel.`0`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(states[9].vc_sel.`0`[6], states[9].vc_sel.`0`[5]) node credit_available_hi_hi_hi_14 = cat(states[9].vc_sel.`0`[9], states[9].vc_sel.`0`[8]) node credit_available_hi_hi_14 = cat(credit_available_hi_hi_hi_14, states[9].vc_sel.`0`[7]) node credit_available_hi_28 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14) node _credit_available_T_35 = cat(credit_available_hi_28, credit_available_lo_28) node credit_available_lo_29 = cat(states[9].vc_sel.`1`[0], _credit_available_T_35) node credit_available_hi_29 = cat(states[9].vc_sel.`3`[0], states[9].vc_sel.`2`[0]) node _credit_available_T_36 = cat(credit_available_hi_29, credit_available_lo_29) node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_15 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_15 = cat(credit_available_lo_hi_hi_15, io.out_credit_available.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_15 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_15 = cat(credit_available_hi_hi_hi_15, io.out_credit_available.`0`[7]) node credit_available_hi_30 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15) node _credit_available_T_37 = cat(credit_available_hi_30, credit_available_lo_30) node credit_available_lo_31 = cat(io.out_credit_available.`1`[0], _credit_available_T_37) node credit_available_hi_31 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _credit_available_T_38 = cat(credit_available_hi_31, credit_available_lo_31) node _credit_available_T_39 = and(_credit_available_T_36, _credit_available_T_38) node credit_available_7 = neq(_credit_available_T_39, UInt<1>(0h0)) node _salloc_arb_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h3)) node _salloc_arb_io_in_9_valid_T_1 = and(_salloc_arb_io_in_9_valid_T, credit_available_7) node _salloc_arb_io_in_9_valid_T_2 = and(_salloc_arb_io_in_9_valid_T_1, input_buffer.io.deq[9].valid) connect salloc_arb.io.in[9].valid, _salloc_arb_io_in_9_valid_T_2 connect salloc_arb.io.in[9].bits.vc_sel.`0`[0], states[9].vc_sel.`0`[0] connect salloc_arb.io.in[9].bits.vc_sel.`0`[1], states[9].vc_sel.`0`[1] connect salloc_arb.io.in[9].bits.vc_sel.`0`[2], states[9].vc_sel.`0`[2] connect salloc_arb.io.in[9].bits.vc_sel.`0`[3], states[9].vc_sel.`0`[3] connect salloc_arb.io.in[9].bits.vc_sel.`0`[4], states[9].vc_sel.`0`[4] connect salloc_arb.io.in[9].bits.vc_sel.`0`[5], states[9].vc_sel.`0`[5] connect salloc_arb.io.in[9].bits.vc_sel.`0`[6], states[9].vc_sel.`0`[6] connect salloc_arb.io.in[9].bits.vc_sel.`0`[7], states[9].vc_sel.`0`[7] connect salloc_arb.io.in[9].bits.vc_sel.`0`[8], states[9].vc_sel.`0`[8] connect salloc_arb.io.in[9].bits.vc_sel.`0`[9], states[9].vc_sel.`0`[9] connect salloc_arb.io.in[9].bits.vc_sel.`1`[0], states[9].vc_sel.`1`[0] connect salloc_arb.io.in[9].bits.vc_sel.`2`[0], states[9].vc_sel.`2`[0] connect salloc_arb.io.in[9].bits.vc_sel.`3`[0], states[9].vc_sel.`3`[0] connect salloc_arb.io.in[9].bits.tail, input_buffer.io.deq[9].bits.tail node _T_134 = and(salloc_arb.io.in[9].ready, salloc_arb.io.in[9].valid) node _T_135 = and(_T_134, input_buffer.io.deq[9].bits.tail) when _T_135 : connect states[9].g, UInt<3>(0h0) connect input_buffer.io.deq[9].ready, salloc_arb.io.in[9].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = eq(salloc_arb.io.in[8].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_17 = and(salloc_arb.io.in[8].valid, _io_debug_sa_stall_T_16) node _io_debug_sa_stall_T_18 = eq(salloc_arb.io.in[9].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_19 = and(salloc_arb.io.in[9].valid, _io_debug_sa_stall_T_18) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 1, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_23) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 1, 0) node _io_debug_sa_stall_T_30 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_31 = bits(_io_debug_sa_stall_T_30, 1, 0) node _io_debug_sa_stall_T_32 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_31) node _io_debug_sa_stall_T_33 = bits(_io_debug_sa_stall_T_32, 1, 0) node _io_debug_sa_stall_T_34 = add(_io_debug_sa_stall_T_29, _io_debug_sa_stall_T_33) node _io_debug_sa_stall_T_35 = bits(_io_debug_sa_stall_T_34, 2, 0) node _io_debug_sa_stall_T_36 = add(_io_debug_sa_stall_T_27, _io_debug_sa_stall_T_35) node _io_debug_sa_stall_T_37 = bits(_io_debug_sa_stall_T_36, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_37 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<4>, out_vid : UInt<4>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _io_in_vc_free_T_10 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_18 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_9, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_20 = mux(_io_in_vc_free_T_10, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_12) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_13) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_14) node _io_in_vc_free_T_24 = or(_io_in_vc_free_T_23, _io_in_vc_free_T_15) node _io_in_vc_free_T_25 = or(_io_in_vc_free_T_24, _io_in_vc_free_T_16) node _io_in_vc_free_T_26 = or(_io_in_vc_free_T_25, _io_in_vc_free_T_17) node _io_in_vc_free_T_27 = or(_io_in_vc_free_T_26, _io_in_vc_free_T_18) node _io_in_vc_free_T_28 = or(_io_in_vc_free_T_27, _io_in_vc_free_T_19) node _io_in_vc_free_T_29 = or(_io_in_vc_free_T_28, _io_in_vc_free_T_20) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_29 node _io_in_vc_free_T_30 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_31 = mux(_io_in_vc_free_T_30, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_31 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 9, 8) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 7, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 7, 4) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 3, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node salloc_outs_0_vid_hi_2 = bits(_salloc_outs_0_vid_T_3, 3, 2) node salloc_outs_0_vid_lo_2 = bits(_salloc_outs_0_vid_T_3, 1, 0) node _salloc_outs_0_vid_T_4 = orr(salloc_outs_0_vid_hi_2) node _salloc_outs_0_vid_T_5 = or(salloc_outs_0_vid_hi_2, salloc_outs_0_vid_lo_2) node _salloc_outs_0_vid_T_6 = bits(_salloc_outs_0_vid_T_5, 1, 1) node _salloc_outs_0_vid_T_7 = cat(_salloc_outs_0_vid_T_4, _salloc_outs_0_vid_T_6) node _salloc_outs_0_vid_T_8 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_7) node _salloc_outs_0_vid_T_9 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_8) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_9 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _vc_sel_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _vc_sel_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _vc_sel_WIRE : UInt<1>[10] node _vc_sel_T_10 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_20 = or(_vc_sel_T_10, _vc_sel_T_11) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_12) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_13) node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_14) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_15) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_16) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_17) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_18) node _vc_sel_T_28 = or(_vc_sel_T_27, _vc_sel_T_19) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_28 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_29 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_37 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_38 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_39 = or(_vc_sel_T_29, _vc_sel_T_30) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_31) node _vc_sel_T_41 = or(_vc_sel_T_40, _vc_sel_T_32) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_33) node _vc_sel_T_43 = or(_vc_sel_T_42, _vc_sel_T_34) node _vc_sel_T_44 = or(_vc_sel_T_43, _vc_sel_T_35) node _vc_sel_T_45 = or(_vc_sel_T_44, _vc_sel_T_36) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_37) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_38) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_47 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_58 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_50) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_51) node _vc_sel_T_61 = or(_vc_sel_T_60, _vc_sel_T_52) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_53) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_54) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_55) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_56) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_57) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_66 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_67 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_68 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_77 = or(_vc_sel_T_67, _vc_sel_T_68) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_69) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_70) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_71) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_72) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_73) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_74) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_75) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_76) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_85 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_91 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_92 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_93 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_94 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_95 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_96 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_88) node _vc_sel_T_98 = or(_vc_sel_T_97, _vc_sel_T_89) node _vc_sel_T_99 = or(_vc_sel_T_98, _vc_sel_T_90) node _vc_sel_T_100 = or(_vc_sel_T_99, _vc_sel_T_91) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_92) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_93) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_94) node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_95) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_104 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_105 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_106 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_107 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_108 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_109 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_110 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_111 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_112 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_113 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_115 = or(_vc_sel_T_105, _vc_sel_T_106) node _vc_sel_T_116 = or(_vc_sel_T_115, _vc_sel_T_107) node _vc_sel_T_117 = or(_vc_sel_T_116, _vc_sel_T_108) node _vc_sel_T_118 = or(_vc_sel_T_117, _vc_sel_T_109) node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_110) node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_111) node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_112) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_113) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_114) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_123 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_124 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_125 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_126 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_127 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_128 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_134 = or(_vc_sel_T_124, _vc_sel_T_125) node _vc_sel_T_135 = or(_vc_sel_T_134, _vc_sel_T_126) node _vc_sel_T_136 = or(_vc_sel_T_135, _vc_sel_T_127) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_128) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_129) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_130) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_131) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_132) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_133) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_142 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_151 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_152 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_153 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_145) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_146) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_147) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_148) node _vc_sel_T_158 = or(_vc_sel_T_157, _vc_sel_T_149) node _vc_sel_T_159 = or(_vc_sel_T_158, _vc_sel_T_150) node _vc_sel_T_160 = or(_vc_sel_T_159, _vc_sel_T_151) node _vc_sel_T_161 = or(_vc_sel_T_160, _vc_sel_T_152) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_161 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 node _vc_sel_T_162 = mux(_vc_sel_T, states[0].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_166 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_167 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_168 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_169 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_170 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_171 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_172 = or(_vc_sel_T_162, _vc_sel_T_163) node _vc_sel_T_173 = or(_vc_sel_T_172, _vc_sel_T_164) node _vc_sel_T_174 = or(_vc_sel_T_173, _vc_sel_T_165) node _vc_sel_T_175 = or(_vc_sel_T_174, _vc_sel_T_166) node _vc_sel_T_176 = or(_vc_sel_T_175, _vc_sel_T_167) node _vc_sel_T_177 = or(_vc_sel_T_176, _vc_sel_T_168) node _vc_sel_T_178 = or(_vc_sel_T_177, _vc_sel_T_169) node _vc_sel_T_179 = or(_vc_sel_T_178, _vc_sel_T_170) node _vc_sel_T_180 = or(_vc_sel_T_179, _vc_sel_T_171) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_180 connect _vc_sel_WIRE[8], _vc_sel_WIRE_9 node _vc_sel_T_181 = mux(_vc_sel_T, states[0].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_182 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_183 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_184 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_185 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_186 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_187 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_188 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_191 = or(_vc_sel_T_181, _vc_sel_T_182) node _vc_sel_T_192 = or(_vc_sel_T_191, _vc_sel_T_183) node _vc_sel_T_193 = or(_vc_sel_T_192, _vc_sel_T_184) node _vc_sel_T_194 = or(_vc_sel_T_193, _vc_sel_T_185) node _vc_sel_T_195 = or(_vc_sel_T_194, _vc_sel_T_186) node _vc_sel_T_196 = or(_vc_sel_T_195, _vc_sel_T_187) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_188) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_189) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_190) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_199 connect _vc_sel_WIRE[9], _vc_sel_WIRE_10 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_11 : UInt<1>[1] node _vc_sel_T_200 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_201 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_202 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_203 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_210 = or(_vc_sel_T_200, _vc_sel_T_201) node _vc_sel_T_211 = or(_vc_sel_T_210, _vc_sel_T_202) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_203) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_204) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_205) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_206) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_207) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_208) node _vc_sel_T_218 = or(_vc_sel_T_217, _vc_sel_T_209) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_218 connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12 connect vc_sel.`1`, _vc_sel_WIRE_11 wire _vc_sel_WIRE_13 : UInt<1>[1] node _vc_sel_T_219 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_226 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_227 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_228 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_229 = or(_vc_sel_T_219, _vc_sel_T_220) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_221) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_222) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_223) node _vc_sel_T_233 = or(_vc_sel_T_232, _vc_sel_T_224) node _vc_sel_T_234 = or(_vc_sel_T_233, _vc_sel_T_225) node _vc_sel_T_235 = or(_vc_sel_T_234, _vc_sel_T_226) node _vc_sel_T_236 = or(_vc_sel_T_235, _vc_sel_T_227) node _vc_sel_T_237 = or(_vc_sel_T_236, _vc_sel_T_228) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_237 connect _vc_sel_WIRE_13[0], _vc_sel_WIRE_14 connect vc_sel.`2`, _vc_sel_WIRE_13 wire _vc_sel_WIRE_15 : UInt<1>[1] node _vc_sel_T_238 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_241 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_242 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_243 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_244 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_245 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_246 = mux(_vc_sel_T_8, states[8].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_247 = mux(_vc_sel_T_9, states[9].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_248 = or(_vc_sel_T_238, _vc_sel_T_239) node _vc_sel_T_249 = or(_vc_sel_T_248, _vc_sel_T_240) node _vc_sel_T_250 = or(_vc_sel_T_249, _vc_sel_T_241) node _vc_sel_T_251 = or(_vc_sel_T_250, _vc_sel_T_242) node _vc_sel_T_252 = or(_vc_sel_T_251, _vc_sel_T_243) node _vc_sel_T_253 = or(_vc_sel_T_252, _vc_sel_T_244) node _vc_sel_T_254 = or(_vc_sel_T_253, _vc_sel_T_245) node _vc_sel_T_255 = or(_vc_sel_T_254, _vc_sel_T_246) node _vc_sel_T_256 = or(_vc_sel_T_255, _vc_sel_T_247) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_256 connect _vc_sel_WIRE_15[0], _vc_sel_WIRE_16 connect vc_sel.`3`, _vc_sel_WIRE_15 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node _channel_oh_T_6 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`0`[8]) node channel_oh_0 = or(_channel_oh_T_7, vc_sel.`0`[9]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_lo_hi = cat(virt_channel_lo_hi_hi, vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[6], vc_sel.`0`[5]) node virt_channel_hi_hi_hi = cat(vc_sel.`0`[9], vc_sel.`0`[8]) node virt_channel_hi_hi = cat(virt_channel_hi_hi_hi, vc_sel.`0`[7]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 9, 8) node virt_channel_lo_1 = bits(_virt_channel_T, 7, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 7, 4) node virt_channel_lo_2 = bits(_virt_channel_T_2, 3, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node virt_channel_hi_3 = bits(_virt_channel_T_4, 3, 2) node virt_channel_lo_3 = bits(_virt_channel_T_4, 1, 0) node _virt_channel_T_5 = orr(virt_channel_hi_3) node _virt_channel_T_6 = or(virt_channel_hi_3, virt_channel_lo_3) node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1) node _virt_channel_T_8 = cat(_virt_channel_T_5, _virt_channel_T_7) node _virt_channel_T_9 = cat(_virt_channel_T_3, _virt_channel_T_8) node _virt_channel_T_10 = cat(_virt_channel_T_1, _virt_channel_T_9) node _virt_channel_T_11 = mux(channel_oh_0, _virt_channel_T_10, UInt<1>(0h0)) node _virt_channel_T_12 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_13 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_14 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_15 = or(_virt_channel_T_11, _virt_channel_T_12) node _virt_channel_T_16 = or(_virt_channel_T_15, _virt_channel_T_13) node _virt_channel_T_17 = or(_virt_channel_T_16, _virt_channel_T_14) wire virt_channel : UInt<4> connect virt_channel, _virt_channel_T_17 node _T_136 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_136 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_payload_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_17 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_18 = mux(_salloc_outs_0_flit_payload_T_8, input_buffer.io.deq[8].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_19 = mux(_salloc_outs_0_flit_payload_T_9, input_buffer.io.deq[9].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_23 = or(_salloc_outs_0_flit_payload_T_22, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_24 = or(_salloc_outs_0_flit_payload_T_23, _salloc_outs_0_flit_payload_T_15) node _salloc_outs_0_flit_payload_T_25 = or(_salloc_outs_0_flit_payload_T_24, _salloc_outs_0_flit_payload_T_16) node _salloc_outs_0_flit_payload_T_26 = or(_salloc_outs_0_flit_payload_T_25, _salloc_outs_0_flit_payload_T_17) node _salloc_outs_0_flit_payload_T_27 = or(_salloc_outs_0_flit_payload_T_26, _salloc_outs_0_flit_payload_T_18) node _salloc_outs_0_flit_payload_T_28 = or(_salloc_outs_0_flit_payload_T_27, _salloc_outs_0_flit_payload_T_19) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_28 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_head_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_17 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_18 = mux(_salloc_outs_0_flit_head_T_8, input_buffer.io.deq[8].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_19 = mux(_salloc_outs_0_flit_head_T_9, input_buffer.io.deq[9].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_23 = or(_salloc_outs_0_flit_head_T_22, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_24 = or(_salloc_outs_0_flit_head_T_23, _salloc_outs_0_flit_head_T_15) node _salloc_outs_0_flit_head_T_25 = or(_salloc_outs_0_flit_head_T_24, _salloc_outs_0_flit_head_T_16) node _salloc_outs_0_flit_head_T_26 = or(_salloc_outs_0_flit_head_T_25, _salloc_outs_0_flit_head_T_17) node _salloc_outs_0_flit_head_T_27 = or(_salloc_outs_0_flit_head_T_26, _salloc_outs_0_flit_head_T_18) node _salloc_outs_0_flit_head_T_28 = or(_salloc_outs_0_flit_head_T_27, _salloc_outs_0_flit_head_T_19) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_28 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_tail_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_17 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_18 = mux(_salloc_outs_0_flit_tail_T_8, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_19 = mux(_salloc_outs_0_flit_tail_T_9, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_23 = or(_salloc_outs_0_flit_tail_T_22, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_24 = or(_salloc_outs_0_flit_tail_T_23, _salloc_outs_0_flit_tail_T_15) node _salloc_outs_0_flit_tail_T_25 = or(_salloc_outs_0_flit_tail_T_24, _salloc_outs_0_flit_tail_T_16) node _salloc_outs_0_flit_tail_T_26 = or(_salloc_outs_0_flit_tail_T_25, _salloc_outs_0_flit_tail_T_17) node _salloc_outs_0_flit_tail_T_27 = or(_salloc_outs_0_flit_tail_T_26, _salloc_outs_0_flit_tail_T_18) node _salloc_outs_0_flit_tail_T_28 = or(_salloc_outs_0_flit_tail_T_27, _salloc_outs_0_flit_tail_T_19) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_28 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_flow_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_flow_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_27, _salloc_outs_0_flit_flow_T_19) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_28 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_41 = or(_salloc_outs_0_flit_flow_T_40, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_42 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_43 = or(_salloc_outs_0_flit_flow_T_42, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_44 = or(_salloc_outs_0_flit_flow_T_43, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_44, _salloc_outs_0_flit_flow_T_36) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_37) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_38) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_47 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_48 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_49 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_49) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_50) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_60, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_57) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_66 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_67 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_67, _salloc_outs_0_flit_flow_T_68) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_83 = or(_salloc_outs_0_flit_flow_T_82, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_84 = or(_salloc_outs_0_flit_flow_T_83, _salloc_outs_0_flit_flow_T_75) node _salloc_outs_0_flit_flow_T_85 = or(_salloc_outs_0_flit_flow_T_84, _salloc_outs_0_flit_flow_T_76) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_85 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_86 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_87 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_88 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_89 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_90 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_91 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_92 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_93 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_94 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_95 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_96 = or(_salloc_outs_0_flit_flow_T_86, _salloc_outs_0_flit_flow_T_87) node _salloc_outs_0_flit_flow_T_97 = or(_salloc_outs_0_flit_flow_T_96, _salloc_outs_0_flit_flow_T_88) node _salloc_outs_0_flit_flow_T_98 = or(_salloc_outs_0_flit_flow_T_97, _salloc_outs_0_flit_flow_T_89) node _salloc_outs_0_flit_flow_T_99 = or(_salloc_outs_0_flit_flow_T_98, _salloc_outs_0_flit_flow_T_90) node _salloc_outs_0_flit_flow_T_100 = or(_salloc_outs_0_flit_flow_T_99, _salloc_outs_0_flit_flow_T_91) node _salloc_outs_0_flit_flow_T_101 = or(_salloc_outs_0_flit_flow_T_100, _salloc_outs_0_flit_flow_T_92) node _salloc_outs_0_flit_flow_T_102 = or(_salloc_outs_0_flit_flow_T_101, _salloc_outs_0_flit_flow_T_93) node _salloc_outs_0_flit_flow_T_103 = or(_salloc_outs_0_flit_flow_T_102, _salloc_outs_0_flit_flow_T_94) node _salloc_outs_0_flit_flow_T_104 = or(_salloc_outs_0_flit_flow_T_103, _salloc_outs_0_flit_flow_T_95) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_104 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`0`[3], UInt<1>(0h0) connect states[0].vc_sel.`0`[4], UInt<1>(0h0) connect states[0].vc_sel.`0`[5], UInt<1>(0h0) connect states[0].vc_sel.`0`[6], UInt<1>(0h0) connect states[0].vc_sel.`0`[7], UInt<1>(0h0) connect states[0].vc_sel.`0`[8], UInt<1>(0h0) connect states[0].vc_sel.`0`[9], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[3], UInt<1>(0h0) connect states[1].vc_sel.`0`[4], UInt<1>(0h0) connect states[1].vc_sel.`0`[5], UInt<1>(0h0) connect states[1].vc_sel.`0`[6], UInt<1>(0h0) connect states[1].vc_sel.`0`[7], UInt<1>(0h0) connect states[1].vc_sel.`0`[8], UInt<1>(0h0) connect states[1].vc_sel.`0`[9], UInt<1>(0h0) invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`0`[3] invalidate states[2].vc_sel.`0`[4] invalidate states[2].vc_sel.`0`[5] invalidate states[2].vc_sel.`0`[6] invalidate states[2].vc_sel.`0`[7] invalidate states[2].vc_sel.`0`[8] invalidate states[2].vc_sel.`0`[9] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`2`[0] invalidate states[2].vc_sel.`3`[0] invalidate states[2].g connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`0`[1], UInt<1>(0h0) connect states[3].vc_sel.`0`[2], UInt<1>(0h0) connect states[3].vc_sel.`0`[4], UInt<1>(0h0) connect states[3].vc_sel.`0`[5], UInt<1>(0h0) connect states[3].vc_sel.`0`[6], UInt<1>(0h0) connect states[3].vc_sel.`0`[7], UInt<1>(0h0) connect states[3].vc_sel.`0`[8], UInt<1>(0h0) connect states[3].vc_sel.`0`[9], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`0`[5], UInt<1>(0h0) connect states[4].vc_sel.`0`[6], UInt<1>(0h0) connect states[4].vc_sel.`0`[7], UInt<1>(0h0) connect states[4].vc_sel.`0`[8], UInt<1>(0h0) connect states[4].vc_sel.`0`[9], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`0`[1], UInt<1>(0h0) connect states[5].vc_sel.`0`[2], UInt<1>(0h0) connect states[5].vc_sel.`0`[3], UInt<1>(0h0) connect states[5].vc_sel.`0`[6], UInt<1>(0h0) connect states[5].vc_sel.`0`[7], UInt<1>(0h0) connect states[5].vc_sel.`0`[8], UInt<1>(0h0) connect states[5].vc_sel.`0`[9], UInt<1>(0h0) invalidate states[6].fifo_deps invalidate states[6].flow.egress_node_id invalidate states[6].flow.egress_node invalidate states[6].flow.ingress_node_id invalidate states[6].flow.ingress_node invalidate states[6].flow.vnet_id invalidate states[6].vc_sel.`0`[0] invalidate states[6].vc_sel.`0`[1] invalidate states[6].vc_sel.`0`[2] invalidate states[6].vc_sel.`0`[3] invalidate states[6].vc_sel.`0`[4] invalidate states[6].vc_sel.`0`[5] invalidate states[6].vc_sel.`0`[6] invalidate states[6].vc_sel.`0`[7] invalidate states[6].vc_sel.`0`[8] invalidate states[6].vc_sel.`0`[9] invalidate states[6].vc_sel.`1`[0] invalidate states[6].vc_sel.`2`[0] invalidate states[6].vc_sel.`3`[0] invalidate states[6].g connect states[7].vc_sel.`0`[0], UInt<1>(0h0) connect states[7].vc_sel.`0`[1], UInt<1>(0h0) connect states[7].vc_sel.`0`[2], UInt<1>(0h0) connect states[7].vc_sel.`0`[3], UInt<1>(0h0) connect states[7].vc_sel.`0`[4], UInt<1>(0h0) connect states[7].vc_sel.`0`[5], UInt<1>(0h0) connect states[7].vc_sel.`0`[6], UInt<1>(0h0) connect states[7].vc_sel.`0`[8], UInt<1>(0h0) connect states[7].vc_sel.`0`[9], UInt<1>(0h0) connect states[8].vc_sel.`0`[0], UInt<1>(0h0) connect states[8].vc_sel.`0`[1], UInt<1>(0h0) connect states[8].vc_sel.`0`[2], UInt<1>(0h0) connect states[8].vc_sel.`0`[3], UInt<1>(0h0) connect states[8].vc_sel.`0`[4], UInt<1>(0h0) connect states[8].vc_sel.`0`[5], UInt<1>(0h0) connect states[8].vc_sel.`0`[6], UInt<1>(0h0) connect states[8].vc_sel.`0`[7], UInt<1>(0h0) connect states[8].vc_sel.`0`[9], UInt<1>(0h0) connect states[9].vc_sel.`0`[0], UInt<1>(0h0) connect states[9].vc_sel.`0`[1], UInt<1>(0h0) connect states[9].vc_sel.`0`[2], UInt<1>(0h0) connect states[9].vc_sel.`0`[3], UInt<1>(0h0) connect states[9].vc_sel.`0`[4], UInt<1>(0h0) connect states[9].vc_sel.`0`[5], UInt<1>(0h0) connect states[9].vc_sel.`0`[6], UInt<1>(0h0) connect states[9].vc_sel.`0`[7], UInt<1>(0h0) node _T_137 = asUInt(reset) when _T_137 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0) connect states[8].g, UInt<3>(0h0) connect states[9].g, UInt<3>(0h0)	module InputUnit_6( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_8, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_9, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_9, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [9:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_9; // @[InputUnit.scala:266:32] wire vcalloc_vals_8; // @[InputUnit.scala:266:32] wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_8_g; // @[InputUnit.scala:192:19] reg states_8_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_0_8; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_9_g; // @[InputUnit.scala:192:19] reg states_9_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_8; // @[InputUnit.scala:192:19] reg states_9_vc_sel_0_9; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [9:0] mask; // @[InputUnit.scala:250:21] wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, vcalloc_vals_7, 1'h0, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, 1'h0, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_0 ? 20'h400 : vcalloc_vals_1 ? 20'h800 : vcalloc_vals_3 ? 20'h2000 : vcalloc_vals_4 ? 20'h4000 : vcalloc_vals_5 ? 20'h8000 : vcalloc_vals_7 ? 20'h20000 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] vcalloc_sel = vcalloc_filter[9:0] \| vcalloc_filter[19:10]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 \| vcalloc_vals_1 \| vcalloc_vals_3 \| vcalloc_vals_4 \| vcalloc_vals_5 \| vcalloc_vals_7 \| vcalloc_vals_8 \| vcalloc_vals_9; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36] wire _GEN_8 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_15 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_30 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_15 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<3>(0h7), io.in.bits.egress_id) node _T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _T_2 = eq(UInt<2>(0h3), io.in.bits.egress_id) node _T_3 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _T_5 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _T_6 = eq(UInt<3>(0h5), io.in.bits.egress_id) node _T_7 = eq(UInt<4>(0h9), io.in.bits.egress_id) node _T_8 = eq(UInt<1>(0h1), io.in.bits.egress_id) node _T_9 = or(_T, _T_1) node _T_10 = or(_T_9, _T_2) node _T_11 = or(_T_10, _T_3) node _T_12 = or(_T_11, _T_4) node _T_13 = or(_T_12, _T_5) node _T_14 = or(_T_13, _T_6) node _T_15 = or(_T_14, _T_7) node _T_16 = or(_T_15, _T_8) node _T_17 = eq(_T_16, UInt<1>(0h0)) node _T_18 = and(io.in.valid, _T_17) node _T_19 = eq(_T_18, UInt<1>(0h0)) node _T_20 = asUInt(reset) node _T_21 = eq(_T_20, UInt<1>(0h0)) when _T_21 : node _T_22 = eq(_T_19, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_19, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<3>(0h5) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<3>(0h7), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<2>(0h3), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = eq(UInt<3>(0h5), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = eq(UInt<4>(0h9), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = eq(UInt<1>(0h1), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h4), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0hd), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0h8), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<4>(0hb), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_5, UInt<4>(0he), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_6, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_16 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_7, UInt<3>(0h7), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_17 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_8, UInt<1>(0h0), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_10) node _route_buffer_io_enq_bits_flow_egress_node_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_T_18, _route_buffer_io_enq_bits_flow_egress_node_T_11) node _route_buffer_io_enq_bits_flow_egress_node_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_T_19, _route_buffer_io_enq_bits_flow_egress_node_T_12) node _route_buffer_io_enq_bits_flow_egress_node_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_T_20, _route_buffer_io_enq_bits_flow_egress_node_T_13) node _route_buffer_io_enq_bits_flow_egress_node_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_T_21, _route_buffer_io_enq_bits_flow_egress_node_T_14) node _route_buffer_io_enq_bits_flow_egress_node_T_23 = or(_route_buffer_io_enq_bits_flow_egress_node_T_22, _route_buffer_io_enq_bits_flow_egress_node_T_15) node _route_buffer_io_enq_bits_flow_egress_node_T_24 = or(_route_buffer_io_enq_bits_flow_egress_node_T_23, _route_buffer_io_enq_bits_flow_egress_node_T_16) node _route_buffer_io_enq_bits_flow_egress_node_T_25 = or(_route_buffer_io_enq_bits_flow_egress_node_T_24, _route_buffer_io_enq_bits_flow_egress_node_T_17) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_25 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<3>(0h7), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0hf), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<2>(0h3), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<4>(0hb), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<4>(0hd), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = eq(UInt<5>(0h11), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = eq(UInt<3>(0h5), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = eq(UInt<4>(0h9), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = eq(UInt<1>(0h1), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_6, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_16 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_7, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_17 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_10) node _route_buffer_io_enq_bits_flow_egress_node_id_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_18, _route_buffer_io_enq_bits_flow_egress_node_id_T_11) node _route_buffer_io_enq_bits_flow_egress_node_id_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_19, _route_buffer_io_enq_bits_flow_egress_node_id_T_12) node _route_buffer_io_enq_bits_flow_egress_node_id_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_20, _route_buffer_io_enq_bits_flow_egress_node_id_T_13) node _route_buffer_io_enq_bits_flow_egress_node_id_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_21, _route_buffer_io_enq_bits_flow_egress_node_id_T_14) node _route_buffer_io_enq_bits_flow_egress_node_id_T_23 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_22, _route_buffer_io_enq_bits_flow_egress_node_id_T_15) node _route_buffer_io_enq_bits_flow_egress_node_id_T_24 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_23, _route_buffer_io_enq_bits_flow_egress_node_id_T_16) node _route_buffer_io_enq_bits_flow_egress_node_id_T_25 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_24, _route_buffer_io_enq_bits_flow_egress_node_id_T_17) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_25 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<3>(0h5)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] node _T_23 = and(io.in.ready, io.in.valid) node _T_24 = and(_T_23, io.in.bits.head) node _T_25 = and(_T_24, at_dest) when _T_25 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) node _T_26 = eq(UInt<5>(0h15), io.in.bits.egress_id) when _T_26 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_27 = eq(UInt<5>(0h16), io.in.bits.egress_id) when _T_27 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_28 = eq(UInt<5>(0h17), io.in.bits.egress_id) when _T_28 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_29 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_30 = and(route_q.io.enq.valid, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : node _T_34 = eq(_T_31, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_31, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_31 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_15 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] node _T_35 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_36 = and(vcalloc_q.io.enq.valid, _T_35) node _T_37 = eq(_T_36, UInt<1>(0h0)) node _T_38 = asUInt(reset) node _T_39 = eq(_T_38, UInt<1>(0h0)) when _T_39 : node _T_40 = eq(_T_37, UInt<1>(0h0)) when _T_40 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_37, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T) node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0]) node _c_T_1 = cat(c_hi_1, c_lo_1) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node c_lo_2 = cat(c_lo_hi_1, c_lo_lo_1) node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_2 = cat(c_hi_2, c_lo_2) node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2) node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0]) node _c_T_3 = cat(c_hi_3, c_lo_3) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1) node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5) node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6) node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_11 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_12, _out_bundle_bits_out_virt_channel_T_10) node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_11) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_15( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _GEN; // @[Decoupled.scala:51:35] wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = io_in_bits_egress_id == 5'h7; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = io_in_bits_egress_id == 5'hF; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = io_in_bits_egress_id == 5'h3; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = io_in_bits_egress_id == 5'hB; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = io_in_bits_egress_id == 5'hD; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_14 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_15 = io_in_bits_egress_id == 5'h5; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_16 = io_in_bits_egress_id == 5'h9; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_17 = io_in_bits_egress_id == 5'h1; // @[IngressUnit.scala:30:72] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_18 = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_9, 2'h0} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_10 ? 4'hD : 4'h0); // @[Mux.scala:30:73] wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_22 = {_route_buffer_io_enq_bits_flow_egress_node_T_18[3] \| _route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_18[2:1], _route_buffer_io_enq_bits_flow_egress_node_T_18[0] \| _route_buffer_io_enq_bits_flow_egress_node_id_T_11} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_13 ? 4'hB : 4'h0) \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_14 ? 4'hE : 4'h0); // @[Mux.scala:30:73] wire [2:0] _GEN_0 = {_route_buffer_io_enq_bits_flow_egress_node_T_22[2], _route_buffer_io_enq_bits_flow_egress_node_T_22[1:0] \| {_route_buffer_io_enq_bits_flow_egress_node_id_T_15, 1'h0}} \| {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_16}}; // @[Mux.scala:30:73] wire [3:0] _GEN_1 = {_route_buffer_io_enq_bits_flow_egress_node_T_22[3], _GEN_0}; // @[Mux.scala:30:73] assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_1 == 4'h5; // @[Decoupled.scala:51:35] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_1 != 4'h5; // @[Decoupled.scala:51:35] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module ResetCatchAndSync_d3_1 : input clock : Clock input reset : Reset output io : { sync_reset : UInt<1>, flip psd : { test_mode : UInt<1>, test_mode_reset : UInt<1>}} node _post_psd_reset_T = asUInt(reset) node post_psd_reset = mux(io.psd.test_mode, io.psd.test_mode_reset, _post_psd_reset_T) inst io_sync_reset_chain of AsyncResetSynchronizerShiftReg_w1_d3_i0_115 connect io_sync_reset_chain.clock, clock connect io_sync_reset_chain.reset, post_psd_reset connect io_sync_reset_chain.io.d, UInt<1>(0h1) wire _io_sync_reset_WIRE : UInt<1> connect _io_sync_reset_WIRE, io_sync_reset_chain.io.q node _io_sync_reset_T = not(_io_sync_reset_WIRE) node _io_sync_reset_T_1 = mux(io.psd.test_mode, io.psd.test_mode_reset, _io_sync_reset_T) connect io.sync_reset, _io_sync_reset_T_1	module ResetCatchAndSync_d3_1( // @[ResetCatchAndSync.scala:13:7] input clock, // @[ResetCatchAndSync.scala:13:7] input reset, // @[ResetCatchAndSync.scala:13:7] output io_sync_reset // @[ResetCatchAndSync.scala:17:14] ); wire _post_psd_reset_T = reset; // @[ResetCatchAndSync.scala:26:76] wire io_psd_test_mode = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14] wire io_psd_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14] wire _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:28:25] wire io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7] wire post_psd_reset = _post_psd_reset_T; // @[ResetCatchAndSync.scala:26:{27,76}] wire _io_sync_reset_WIRE; // @[ShiftReg.scala:48:24] wire _io_sync_reset_T = ~_io_sync_reset_WIRE; // @[ShiftReg.scala:48:24] assign _io_sync_reset_T_1 = _io_sync_reset_T; // @[ResetCatchAndSync.scala:28:25, :29:7] assign io_sync_reset_0 = _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:13:7, :28:25] AsyncResetSynchronizerShiftReg_w1_d3_i0_115 io_sync_reset_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (post_psd_reset), // @[ResetCatchAndSync.scala:26:27] .io_q (_io_sync_reset_WIRE) ); // @[ShiftReg.scala:45:23] assign io_sync_reset = io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMasterToNoC_1 : input clock : Clock input reset : Reset output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}} inst a of TLAToNoC_1 connect a.clock, clock connect a.reset, reset inst b of TLBFromNoC_1 connect b.clock, clock connect b.reset, reset inst c of TLCToNoC_1 connect c.clock, clock connect c.reset, reset inst d of TLDFromNoC_1 connect d.clock, clock connect d.reset, reset inst e of TLEToNoC_1 connect e.clock, clock connect e.reset, reset connect a.io.protocol, io.tilelink.a connect io.tilelink.b.bits, b.io.protocol.bits connect io.tilelink.b.valid, b.io.protocol.valid connect b.io.protocol.ready, io.tilelink.b.ready connect c.io.protocol, io.tilelink.c connect io.tilelink.d.bits, d.io.protocol.bits connect io.tilelink.d.valid, d.io.protocol.valid connect d.io.protocol.ready, io.tilelink.d.ready connect e.io.protocol, io.tilelink.e connect io.flits.a.bits, a.io.flit.bits connect io.flits.a.valid, a.io.flit.valid connect a.io.flit.ready, io.flits.a.ready connect b.io.flit, io.flits.b connect io.flits.c.bits, c.io.flit.bits connect io.flits.c.valid, c.io.flit.valid connect c.io.flit.ready, io.flits.c.ready connect d.io.flit, io.flits.d connect io.flits.e.bits, e.io.flit.bits connect io.flits.e.valid, e.io.flit.valid connect e.io.flit.ready, io.flits.e.ready	module TLMasterToNoC_1( // @[Tilelink.scala:37:7] input clock, // @[Tilelink.scala:37:7] input reset, // @[Tilelink.scala:37:7] output io_tilelink_a_ready, // @[Tilelink.scala:44:14] input io_tilelink_a_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:44:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:44:14] input [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_b_ready, // @[Tilelink.scala:44:14] output io_tilelink_b_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_b_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:44:14] output [3:0] io_tilelink_b_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:44:14] output [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:44:14] output [7:0] io_tilelink_b_bits_mask, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_b_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_b_bits_corrupt, // @[Tilelink.scala:44:14] output io_tilelink_c_ready, // @[Tilelink.scala:44:14] input io_tilelink_c_valid, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:44:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:44:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:44:14] input [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:44:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:44:14] input [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:44:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:44:14] input io_tilelink_d_ready, // @[Tilelink.scala:44:14] output io_tilelink_d_valid, // @[Tilelink.scala:44:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:44:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:44:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:44:14] output [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:44:14] output [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:44:14] output [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:44:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:44:14] output io_tilelink_e_ready, // @[Tilelink.scala:44:14] input io_tilelink_e_valid, // @[Tilelink.scala:44:14] input [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:44:14] input io_flits_a_ready, // @[Tilelink.scala:44:14] output io_flits_a_valid, // @[Tilelink.scala:44:14] output io_flits_a_bits_head, // @[Tilelink.scala:44:14] output io_flits_a_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_b_ready, // @[Tilelink.scala:44:14] input io_flits_b_valid, // @[Tilelink.scala:44:14] input io_flits_b_bits_head, // @[Tilelink.scala:44:14] input io_flits_b_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:44:14] input io_flits_c_ready, // @[Tilelink.scala:44:14] output io_flits_c_valid, // @[Tilelink.scala:44:14] output io_flits_c_bits_head, // @[Tilelink.scala:44:14] output io_flits_c_bits_tail, // @[Tilelink.scala:44:14] output [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:44:14] output io_flits_d_ready, // @[Tilelink.scala:44:14] input io_flits_d_valid, // @[Tilelink.scala:44:14] input io_flits_d_bits_head, // @[Tilelink.scala:44:14] input io_flits_d_bits_tail, // @[Tilelink.scala:44:14] input [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:44:14] input io_flits_e_ready, // @[Tilelink.scala:44:14] output io_flits_e_valid, // @[Tilelink.scala:44:14] output io_flits_e_bits_head, // @[Tilelink.scala:44:14] output [72:0] io_flits_e_bits_payload, // @[Tilelink.scala:44:14] output [4:0] io_flits_e_bits_egress_id // @[Tilelink.scala:44:14] ); wire [4:0] _e_io_flit_bits_payload; // @[Tilelink.scala:58:17] wire [64:0] _c_io_flit_bits_payload; // @[Tilelink.scala:56:17] TLAToNoC_1 a ( // @[Tilelink.scala:54:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:54:17] TLBFromNoC_1 b ( // @[Tilelink.scala:55:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_b_ready), .io_protocol_valid (io_tilelink_b_valid), .io_protocol_bits_opcode (io_tilelink_b_bits_opcode), .io_protocol_bits_param (io_tilelink_b_bits_param), .io_protocol_bits_size (io_tilelink_b_bits_size), .io_protocol_bits_source (io_tilelink_b_bits_source), .io_protocol_bits_address (io_tilelink_b_bits_address), .io_protocol_bits_mask (io_tilelink_b_bits_mask), .io_protocol_bits_data (io_tilelink_b_bits_data), .io_protocol_bits_corrupt (io_tilelink_b_bits_corrupt), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail), .io_flit_bits_payload (io_flits_b_bits_payload) ); // @[Tilelink.scala:55:17] TLCToNoC_1 c ( // @[Tilelink.scala:56:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:56:17] TLDFromNoC_1 d ( // @[Tilelink.scala:57:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[64:0]) // @[Tilelink.scala:68:14] ); // @[Tilelink.scala:57:17] TLEToNoC e ( // @[Tilelink.scala:58:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_e_ready), .io_protocol_valid (io_tilelink_e_valid), .io_protocol_bits_sink (io_tilelink_e_bits_sink), .io_flit_ready (io_flits_e_ready), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_payload (_e_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_e_bits_egress_id) ); // @[Tilelink.scala:58:17] assign io_flits_c_bits_payload = {8'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :56:17, :67:14] assign io_flits_e_bits_payload = {68'h0, _e_io_flit_bits_payload}; // @[Tilelink.scala:37:7, :58:17, :69:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Rocket_4 : input clock : Clock input reset : Reset output io : { flip hartid : UInt<3>, flip reset_vector : UInt<32>, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>, lip : UInt<1>[0]}, imem : { might_request : UInt<1>, flip clock_enabled : UInt<1>, req : { valid : UInt<1>, bits : { pc : UInt<40>, speculative : UInt<1>}}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, flip gpa : { valid : UInt<1>, bits : UInt<40>}, flip gpa_is_pte : UInt<1>, btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<39>, cfiType : UInt<2>}}, bht_update : { valid : UInt<1>, bits : { prediction : { history : UInt<8>, value : UInt<1>}, pc : UInt<39>, branch : UInt<1>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : { valid : UInt<1>, bits : { cfiType : UInt<2>, returnAddr : UInt<39>}}, flush_icache : UInt<1>, flip npc : UInt<40>, flip perf : { acquire : UInt<1>, tlbMiss : UInt<1>}, progress : UInt<1>}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, flip ptw : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}, flip fpu : { flip hartid : UInt<3>, flip time : UInt<64>, flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip v_sew : UInt<3>, store_data : UInt<64>, toint_data : UInt<64>, flip ll_resp_val : UInt<1>, flip ll_resp_type : UInt<3>, flip ll_resp_tag : UInt<5>, flip ll_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip keep_clock_enabled : UInt<1>}, flip rocc : { flip cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, flip exception : UInt<1>, flip csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}, trace : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, bpwatch : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1], cease : UInt<1>, wfi : UInt<1>, flip traceStall : UInt<1>} regreset clock_en_reg : UInt<1>, clock, reset, UInt<1>(0h1) reg long_latency_stall : UInt<1>, clock reg id_reg_pause : UInt<1>, clock reg imem_might_request_reg : UInt<1>, clock wire clock_en : UInt<1> connect clock_en, UInt<1>(0h1) wire _hits_WIRE : UInt<1>[18] connect _hits_WIRE[0], UInt<1>(0h0) connect _hits_WIRE[1], UInt<1>(0h0) connect _hits_WIRE[2], UInt<1>(0h0) connect _hits_WIRE[3], UInt<1>(0h0) connect _hits_WIRE[4], UInt<1>(0h0) connect _hits_WIRE[5], UInt<1>(0h0) connect _hits_WIRE[6], UInt<1>(0h0) connect _hits_WIRE[7], UInt<1>(0h0) connect _hits_WIRE[8], UInt<1>(0h0) connect _hits_WIRE[9], UInt<1>(0h0) connect _hits_WIRE[10], UInt<1>(0h0) connect _hits_WIRE[11], UInt<1>(0h0) connect _hits_WIRE[12], UInt<1>(0h0) connect _hits_WIRE[13], UInt<1>(0h0) connect _hits_WIRE[14], UInt<1>(0h0) connect _hits_WIRE[15], UInt<1>(0h0) connect _hits_WIRE[16], UInt<1>(0h0) connect _hits_WIRE[17], UInt<1>(0h0) wire hits : UInt<1>[18] connect hits, _hits_WIRE wire _hits_WIRE_1 : UInt<1>[11] connect _hits_WIRE_1[0], UInt<1>(0h0) connect _hits_WIRE_1[1], UInt<1>(0h0) connect _hits_WIRE_1[2], UInt<1>(0h0) connect _hits_WIRE_1[3], UInt<1>(0h0) connect _hits_WIRE_1[4], UInt<1>(0h0) connect _hits_WIRE_1[5], UInt<1>(0h0) connect _hits_WIRE_1[6], UInt<1>(0h0) connect _hits_WIRE_1[7], UInt<1>(0h0) connect _hits_WIRE_1[8], UInt<1>(0h0) connect _hits_WIRE_1[9], UInt<1>(0h0) connect _hits_WIRE_1[10], UInt<1>(0h0) wire hits_1 : UInt<1>[11] connect hits_1, _hits_WIRE_1 wire _hits_WIRE_2 : UInt<1>[6] connect _hits_WIRE_2[0], UInt<1>(0h0) connect _hits_WIRE_2[1], UInt<1>(0h0) connect _hits_WIRE_2[2], UInt<1>(0h0) connect _hits_WIRE_2[3], UInt<1>(0h0) connect _hits_WIRE_2[4], UInt<1>(0h0) connect _hits_WIRE_2[5], UInt<1>(0h0) wire hits_2 : UInt<1>[6] connect hits_2, _hits_WIRE_2 reg ex_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, clock reg mem_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, clock reg wb_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>}, clock reg ex_reg_xcpt_interrupt : UInt<1>, clock reg ex_reg_valid : UInt<1>, clock reg ex_reg_rvc : UInt<1>, clock reg ex_reg_btb_resp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock reg ex_reg_xcpt : UInt<1>, clock reg ex_reg_flush_pipe : UInt<1>, clock reg ex_reg_load_use : UInt<1>, clock reg ex_reg_cause : UInt, clock reg ex_reg_replay : UInt<1>, clock reg ex_reg_pc : UInt, clock reg ex_reg_mem_size : UInt, clock reg ex_reg_hls : UInt<1>, clock reg ex_reg_inst : UInt, clock reg ex_reg_raw_inst : UInt, clock reg ex_reg_wphit : UInt<1>[1], clock reg ex_reg_set_vconfig : UInt<1>, clock reg mem_reg_xcpt_interrupt : UInt<1>, clock reg mem_reg_valid : UInt<1>, clock reg mem_reg_rvc : UInt<1>, clock reg mem_reg_btb_resp : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock reg mem_reg_xcpt : UInt<1>, clock reg mem_reg_replay : UInt<1>, clock reg mem_reg_flush_pipe : UInt<1>, clock reg mem_reg_cause : UInt, clock reg mem_reg_slow_bypass : UInt<1>, clock reg mem_reg_load : UInt<1>, clock reg mem_reg_store : UInt<1>, clock reg mem_reg_set_vconfig : UInt<1>, clock reg mem_reg_sfence : UInt<1>, clock reg mem_reg_pc : UInt, clock reg mem_reg_inst : UInt, clock reg mem_reg_mem_size : UInt, clock reg mem_reg_hls_or_dv : UInt<1>, clock reg mem_reg_raw_inst : UInt, clock reg mem_reg_wdata : UInt, clock reg mem_reg_rs2 : UInt, clock reg mem_br_taken : UInt<1>, clock wire take_pc_mem : UInt<1> reg mem_reg_wphit : UInt<1>[1], clock reg wb_reg_valid : UInt<1>, clock reg wb_reg_xcpt : UInt<1>, clock reg wb_reg_replay : UInt<1>, clock reg wb_reg_flush_pipe : UInt<1>, clock reg wb_reg_cause : UInt, clock reg wb_reg_set_vconfig : UInt<1>, clock reg wb_reg_sfence : UInt<1>, clock reg wb_reg_pc : UInt, clock reg wb_reg_mem_size : UInt, clock reg wb_reg_hls_or_dv : UInt<1>, clock reg wb_reg_hfence_v : UInt<1>, clock reg wb_reg_hfence_g : UInt<1>, clock reg wb_reg_inst : UInt, clock reg wb_reg_raw_inst : UInt, clock reg wb_reg_wdata : UInt, clock reg wb_reg_rs2 : UInt, clock wire take_pc_wb : UInt<1> reg wb_reg_wphit : UInt<1>[1], clock node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) inst ibuf of IBuf_4 connect ibuf.clock, clock connect ibuf.reset, reset connect ibuf.io.imem, io.imem.resp connect ibuf.io.kill, take_pc_mem_wb wire id_ctrl : { legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<3>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<5>, mem : UInt<1>, mem_cmd : UInt<5>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, mul : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>, dp : UInt<1>, vec : UInt<1>} wire id_ctrl_decoder_decoded_plaInput : UInt<32> node id_ctrl_decoder_decoded_invInputs = not(id_ctrl_decoder_decoded_plaInput) wire id_ctrl_decoder_decoded : UInt<42> node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1) node id_ctrl_decoder_decoded_andMatrixOutputs_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo) node _id_ctrl_decoder_decoded_andMatrixOutputs_T = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_99_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_102_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_9_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_29_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_4) node id_ctrl_decoder_decoded_andMatrixOutputs_139_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_5) node id_ctrl_decoder_decoded_andMatrixOutputs_117_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_6) node id_ctrl_decoder_decoded_andMatrixOutputs_96_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_7) node id_ctrl_decoder_decoded_andMatrixOutputs_35_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_8) node id_ctrl_decoder_decoded_andMatrixOutputs_182_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_9) node id_ctrl_decoder_decoded_andMatrixOutputs_128_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_10) node id_ctrl_decoder_decoded_andMatrixOutputs_67_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_10) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_11) node id_ctrl_decoder_decoded_andMatrixOutputs_78_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_11) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_12) node id_ctrl_decoder_decoded_andMatrixOutputs_190_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_13) node id_ctrl_decoder_decoded_andMatrixOutputs_7_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_14) node id_ctrl_decoder_decoded_andMatrixOutputs_98_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_15) node id_ctrl_decoder_decoded_andMatrixOutputs_32_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_15) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_16) node id_ctrl_decoder_decoded_andMatrixOutputs_71_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_16) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_17) node id_ctrl_decoder_decoded_andMatrixOutputs_181_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_17) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_18) node id_ctrl_decoder_decoded_andMatrixOutputs_145_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_18) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_19) node id_ctrl_decoder_decoded_andMatrixOutputs_143_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_19) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_20) node id_ctrl_decoder_decoded_andMatrixOutputs_20_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_21) node id_ctrl_decoder_decoded_andMatrixOutputs_22_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_22) node id_ctrl_decoder_decoded_andMatrixOutputs_97_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_23) node id_ctrl_decoder_decoded_andMatrixOutputs_39_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_24) node id_ctrl_decoder_decoded_andMatrixOutputs_131_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_25) node id_ctrl_decoder_decoded_andMatrixOutputs_191_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_26) node id_ctrl_decoder_decoded_andMatrixOutputs_164_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_27) node id_ctrl_decoder_decoded_andMatrixOutputs_55_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_28) node id_ctrl_decoder_decoded_andMatrixOutputs_90_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_29) node id_ctrl_decoder_decoded_andMatrixOutputs_30_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_30) node id_ctrl_decoder_decoded_andMatrixOutputs_26_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_31) node id_ctrl_decoder_decoded_andMatrixOutputs_175_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_31) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_32) node id_ctrl_decoder_decoded_andMatrixOutputs_77_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_32) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_33) node id_ctrl_decoder_decoded_andMatrixOutputs_21_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_33) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_34) node id_ctrl_decoder_decoded_andMatrixOutputs_121_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_34) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_35) node id_ctrl_decoder_decoded_andMatrixOutputs_61_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_35) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_36) node id_ctrl_decoder_decoded_andMatrixOutputs_105_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_36) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_37) node id_ctrl_decoder_decoded_andMatrixOutputs_24_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_37) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_38) node id_ctrl_decoder_decoded_andMatrixOutputs_165_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_38) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_39) node id_ctrl_decoder_decoded_andMatrixOutputs_160_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_39) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_40) node id_ctrl_decoder_decoded_andMatrixOutputs_95_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_40) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_41) node id_ctrl_decoder_decoded_andMatrixOutputs_56_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_41) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_42) node id_ctrl_decoder_decoded_andMatrixOutputs_16_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_42) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_43) node id_ctrl_decoder_decoded_andMatrixOutputs_185_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_43) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_44) node id_ctrl_decoder_decoded_andMatrixOutputs_140_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_44) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_45) node id_ctrl_decoder_decoded_andMatrixOutputs_53_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_45) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_46) node id_ctrl_decoder_decoded_andMatrixOutputs_193_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_46) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_47) node id_ctrl_decoder_decoded_andMatrixOutputs_92_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_47) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_48) node id_ctrl_decoder_decoded_andMatrixOutputs_17_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_48) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_49) node id_ctrl_decoder_decoded_andMatrixOutputs_129_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_49) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_50) node id_ctrl_decoder_decoded_andMatrixOutputs_177_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_50) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_51) node id_ctrl_decoder_decoded_andMatrixOutputs_123_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_51) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_52) node id_ctrl_decoder_decoded_andMatrixOutputs_14_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_52) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_53) node id_ctrl_decoder_decoded_andMatrixOutputs_132_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_53) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_54) node id_ctrl_decoder_decoded_andMatrixOutputs_49_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_54) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_55) node id_ctrl_decoder_decoded_andMatrixOutputs_155_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_55) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_56) node id_ctrl_decoder_decoded_andMatrixOutputs_184_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_56) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_57) node id_ctrl_decoder_decoded_andMatrixOutputs_148_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_57) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_58) node id_ctrl_decoder_decoded_andMatrixOutputs_115_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_58) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_59) node id_ctrl_decoder_decoded_andMatrixOutputs_162_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_59) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_60) node id_ctrl_decoder_decoded_andMatrixOutputs_44_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_60) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_61) node id_ctrl_decoder_decoded_andMatrixOutputs_126_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_61) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_62) node id_ctrl_decoder_decoded_andMatrixOutputs_150_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_62) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_63) node id_ctrl_decoder_decoded_andMatrixOutputs_161_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_63) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_64) node id_ctrl_decoder_decoded_andMatrixOutputs_133_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_64) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_65) node id_ctrl_decoder_decoded_andMatrixOutputs_179_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_65) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_66) node id_ctrl_decoder_decoded_andMatrixOutputs_5_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_66) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_67) node id_ctrl_decoder_decoded_andMatrixOutputs_88_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_67) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_68) node id_ctrl_decoder_decoded_andMatrixOutputs_94_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_68) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_69) node id_ctrl_decoder_decoded_andMatrixOutputs_66_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_69) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_70) node id_ctrl_decoder_decoded_andMatrixOutputs_125_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_70) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_71) node id_ctrl_decoder_decoded_andMatrixOutputs_91_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_71) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_72) node id_ctrl_decoder_decoded_andMatrixOutputs_112_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_72) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_73) node id_ctrl_decoder_decoded_andMatrixOutputs_170_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_73) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_74) node id_ctrl_decoder_decoded_andMatrixOutputs_146_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_74) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_75) node id_ctrl_decoder_decoded_andMatrixOutputs_168_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_75) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_76) node id_ctrl_decoder_decoded_andMatrixOutputs_2_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_76) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_77) node id_ctrl_decoder_decoded_andMatrixOutputs_15_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_77) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_78) node id_ctrl_decoder_decoded_andMatrixOutputs_176_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_78) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_79) node id_ctrl_decoder_decoded_andMatrixOutputs_172_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_79) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_80) node id_ctrl_decoder_decoded_andMatrixOutputs_76_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_80) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_81) node id_ctrl_decoder_decoded_andMatrixOutputs_87_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_81) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_82) node id_ctrl_decoder_decoded_andMatrixOutputs_144_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_82) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_83) node id_ctrl_decoder_decoded_andMatrixOutputs_36_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_83) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_84) node id_ctrl_decoder_decoded_andMatrixOutputs_41_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_84) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_85) node id_ctrl_decoder_decoded_andMatrixOutputs_8_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_85) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_86) node id_ctrl_decoder_decoded_andMatrixOutputs_104_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_86) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_87) node id_ctrl_decoder_decoded_andMatrixOutputs_73_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_87) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_88) node id_ctrl_decoder_decoded_andMatrixOutputs_189_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_88) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_89) node id_ctrl_decoder_decoded_andMatrixOutputs_28_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_89) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_90) node id_ctrl_decoder_decoded_andMatrixOutputs_0_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_90) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_91) node id_ctrl_decoder_decoded_andMatrixOutputs_60_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_91) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_92) node id_ctrl_decoder_decoded_andMatrixOutputs_48_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_92) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_93) node id_ctrl_decoder_decoded_andMatrixOutputs_167_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_93) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_94) node id_ctrl_decoder_decoded_andMatrixOutputs_163_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_94) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_95) node id_ctrl_decoder_decoded_andMatrixOutputs_137_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_95) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_96) node id_ctrl_decoder_decoded_andMatrixOutputs_74_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_96) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_97) node id_ctrl_decoder_decoded_andMatrixOutputs_59_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_97) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_98) node id_ctrl_decoder_decoded_andMatrixOutputs_152_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_98) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = bits(id_ctrl_decoder_decoded_plaInput, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_99) node id_ctrl_decoder_decoded_andMatrixOutputs_47_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_99) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = bits(id_ctrl_decoder_decoded_plaInput, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_100) node id_ctrl_decoder_decoded_andMatrixOutputs_103_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_100) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_101) node id_ctrl_decoder_decoded_andMatrixOutputs_83_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_101) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_102) node id_ctrl_decoder_decoded_andMatrixOutputs_31_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_102) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_103) node id_ctrl_decoder_decoded_andMatrixOutputs_13_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_103) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_104) node id_ctrl_decoder_decoded_andMatrixOutputs_111_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_104) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_105) node id_ctrl_decoder_decoded_andMatrixOutputs_65_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_105) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_106) node id_ctrl_decoder_decoded_andMatrixOutputs_124_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_106) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_107) node id_ctrl_decoder_decoded_andMatrixOutputs_50_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_107) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_108) node id_ctrl_decoder_decoded_andMatrixOutputs_6_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_108) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_109) node id_ctrl_decoder_decoded_andMatrixOutputs_134_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_109) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_110) node id_ctrl_decoder_decoded_andMatrixOutputs_153_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_110) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_111) node id_ctrl_decoder_decoded_andMatrixOutputs_109_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_111) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_112) node id_ctrl_decoder_decoded_andMatrixOutputs_187_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_112) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_113) node id_ctrl_decoder_decoded_andMatrixOutputs_45_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_113) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_114) node id_ctrl_decoder_decoded_andMatrixOutputs_79_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_114) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_115) node id_ctrl_decoder_decoded_andMatrixOutputs_159_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_115) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_116) node id_ctrl_decoder_decoded_andMatrixOutputs_34_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_116) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_117) node id_ctrl_decoder_decoded_andMatrixOutputs_86_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_117) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_118) node id_ctrl_decoder_decoded_andMatrixOutputs_10_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_118) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_119) node id_ctrl_decoder_decoded_andMatrixOutputs_93_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_119) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_120) node id_ctrl_decoder_decoded_andMatrixOutputs_180_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_120) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_121) node id_ctrl_decoder_decoded_andMatrixOutputs_43_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_121) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_122) node id_ctrl_decoder_decoded_andMatrixOutputs_135_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_122) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_123) node id_ctrl_decoder_decoded_andMatrixOutputs_3_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_123) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = bits(id_ctrl_decoder_decoded_plaInput, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_124) node id_ctrl_decoder_decoded_andMatrixOutputs_188_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_124) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_125) node id_ctrl_decoder_decoded_andMatrixOutputs_4_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_125) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_126) node id_ctrl_decoder_decoded_andMatrixOutputs_25_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_126) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_127) node id_ctrl_decoder_decoded_andMatrixOutputs_58_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_127) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_128) node id_ctrl_decoder_decoded_andMatrixOutputs_147_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_128) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_129) node id_ctrl_decoder_decoded_andMatrixOutputs_27_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_129) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_130) node id_ctrl_decoder_decoded_andMatrixOutputs_52_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_130) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_131) node id_ctrl_decoder_decoded_andMatrixOutputs_138_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_131) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_132) node id_ctrl_decoder_decoded_andMatrixOutputs_178_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_132) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_133) node id_ctrl_decoder_decoded_andMatrixOutputs_173_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_133) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_134) node id_ctrl_decoder_decoded_andMatrixOutputs_120_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_134) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_135) node id_ctrl_decoder_decoded_andMatrixOutputs_19_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_135) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_136) node id_ctrl_decoder_decoded_andMatrixOutputs_64_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_136) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_137) node id_ctrl_decoder_decoded_andMatrixOutputs_142_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_137) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_138) node id_ctrl_decoder_decoded_andMatrixOutputs_11_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_138) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_139) node id_ctrl_decoder_decoded_andMatrixOutputs_46_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_139) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_140) node id_ctrl_decoder_decoded_andMatrixOutputs_141_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_140) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(id_ctrl_decoder_decoded_plaInput, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_141) node id_ctrl_decoder_decoded_andMatrixOutputs_114_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_141) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_142) node id_ctrl_decoder_decoded_andMatrixOutputs_70_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_142) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_143) node id_ctrl_decoder_decoded_andMatrixOutputs_72_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_143) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_144) node id_ctrl_decoder_decoded_andMatrixOutputs_174_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_144) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_145) node id_ctrl_decoder_decoded_andMatrixOutputs_81_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_145) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = bits(id_ctrl_decoder_decoded_plaInput, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_146) node id_ctrl_decoder_decoded_andMatrixOutputs_130_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_146) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = bits(id_ctrl_decoder_decoded_plaInput, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_147) node id_ctrl_decoder_decoded_andMatrixOutputs_157_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_147) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_148) node id_ctrl_decoder_decoded_andMatrixOutputs_68_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_148) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_149) node id_ctrl_decoder_decoded_andMatrixOutputs_42_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_149) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_150) node id_ctrl_decoder_decoded_andMatrixOutputs_54_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_150) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_151) node id_ctrl_decoder_decoded_andMatrixOutputs_63_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_151) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_152) node id_ctrl_decoder_decoded_andMatrixOutputs_69_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_152) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_153) node id_ctrl_decoder_decoded_andMatrixOutputs_183_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_153) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_154) node id_ctrl_decoder_decoded_andMatrixOutputs_51_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_154) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_155) node id_ctrl_decoder_decoded_andMatrixOutputs_136_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_155) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_156) node id_ctrl_decoder_decoded_andMatrixOutputs_127_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_156) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_157) node id_ctrl_decoder_decoded_andMatrixOutputs_151_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_157) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_158) node id_ctrl_decoder_decoded_andMatrixOutputs_1_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_158) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_159) node id_ctrl_decoder_decoded_andMatrixOutputs_100_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_159) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_160) node id_ctrl_decoder_decoded_andMatrixOutputs_106_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_160) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_161) node id_ctrl_decoder_decoded_andMatrixOutputs_186_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_161) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_162) node id_ctrl_decoder_decoded_andMatrixOutputs_18_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_162) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_163) node id_ctrl_decoder_decoded_andMatrixOutputs_108_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_163) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_164) node id_ctrl_decoder_decoded_andMatrixOutputs_89_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_164) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_165) node id_ctrl_decoder_decoded_andMatrixOutputs_62_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_165) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_166) node id_ctrl_decoder_decoded_andMatrixOutputs_149_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_166) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_167) node id_ctrl_decoder_decoded_andMatrixOutputs_171_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_167) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_168) node id_ctrl_decoder_decoded_andMatrixOutputs_37_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_168) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = bits(id_ctrl_decoder_decoded_plaInput, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(id_ctrl_decoder_decoded_plaInput, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = bits(id_ctrl_decoder_decoded_plaInput, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = bits(id_ctrl_decoder_decoded_plaInput, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_169) node id_ctrl_decoder_decoded_andMatrixOutputs_122_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_169) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = bits(id_ctrl_decoder_decoded_plaInput, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_170) node id_ctrl_decoder_decoded_andMatrixOutputs_82_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_170) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = bits(id_ctrl_decoder_decoded_invInputs, 7, 7) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(id_ctrl_decoder_decoded_invInputs, 8, 8) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(id_ctrl_decoder_decoded_invInputs, 9, 9) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(id_ctrl_decoder_decoded_invInputs, 10, 10) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(id_ctrl_decoder_decoded_invInputs, 11, 11) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = bits(id_ctrl_decoder_decoded_invInputs, 15, 15) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = bits(id_ctrl_decoder_decoded_invInputs, 16, 16) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = bits(id_ctrl_decoder_decoded_invInputs, 17, 17) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = bits(id_ctrl_decoder_decoded_invInputs, 18, 18) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = bits(id_ctrl_decoder_decoded_invInputs, 19, 19) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = bits(id_ctrl_decoder_decoded_plaInput, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = bits(id_ctrl_decoder_decoded_plaInput, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = bits(id_ctrl_decoder_decoded_plaInput, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = bits(id_ctrl_decoder_decoded_invInputs, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_171) node id_ctrl_decoder_decoded_andMatrixOutputs_119_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_171) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = bits(id_ctrl_decoder_decoded_plaInput, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = bits(id_ctrl_decoder_decoded_plaInput, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = bits(id_ctrl_decoder_decoded_invInputs, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = bits(id_ctrl_decoder_decoded_plaInput, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = bits(id_ctrl_decoder_decoded_invInputs, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = bits(id_ctrl_decoder_decoded_plaInput, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_172) node id_ctrl_decoder_decoded_andMatrixOutputs_169_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_172) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_173) node id_ctrl_decoder_decoded_andMatrixOutputs_57_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_173) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_174) node id_ctrl_decoder_decoded_andMatrixOutputs_80_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_174) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_175) node id_ctrl_decoder_decoded_andMatrixOutputs_166_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_175) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = bits(id_ctrl_decoder_decoded_invInputs, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_176) node id_ctrl_decoder_decoded_andMatrixOutputs_154_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_176) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_177) node id_ctrl_decoder_decoded_andMatrixOutputs_192_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_177) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_178) node id_ctrl_decoder_decoded_andMatrixOutputs_38_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_178) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_179) node id_ctrl_decoder_decoded_andMatrixOutputs_158_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_179) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_180) node id_ctrl_decoder_decoded_andMatrixOutputs_110_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_180) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_181) node id_ctrl_decoder_decoded_andMatrixOutputs_23_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_181) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_182) node id_ctrl_decoder_decoded_andMatrixOutputs_101_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_182) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_183 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_183 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_183 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_183) node id_ctrl_decoder_decoded_andMatrixOutputs_118_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_183) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_184 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_184 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_184) node id_ctrl_decoder_decoded_andMatrixOutputs_116_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_184) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = bits(id_ctrl_decoder_decoded_invInputs, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_185 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_185 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_185) node id_ctrl_decoder_decoded_andMatrixOutputs_156_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_185) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_186 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_186 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_186 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_186) node id_ctrl_decoder_decoded_andMatrixOutputs_113_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_186) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_187 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_187 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_187 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_187) node id_ctrl_decoder_decoded_andMatrixOutputs_107_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_187) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_188 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_188 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_188) node id_ctrl_decoder_decoded_andMatrixOutputs_84_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_188) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_189 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_189 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_189) node id_ctrl_decoder_decoded_andMatrixOutputs_33_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_189) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_190 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_190 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_190 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_190) node id_ctrl_decoder_decoded_andMatrixOutputs_85_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_190) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = bits(id_ctrl_decoder_decoded_plaInput, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = bits(id_ctrl_decoder_decoded_invInputs, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_191 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_191 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_191 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_191) node id_ctrl_decoder_decoded_andMatrixOutputs_40_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_191) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = bits(id_ctrl_decoder_decoded_invInputs, 25, 25) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_192 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_192 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_192) node id_ctrl_decoder_decoded_andMatrixOutputs_12_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_192) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = bits(id_ctrl_decoder_decoded_plaInput, 0, 0) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = bits(id_ctrl_decoder_decoded_plaInput, 1, 1) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = bits(id_ctrl_decoder_decoded_invInputs, 2, 2) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = bits(id_ctrl_decoder_decoded_invInputs, 3, 3) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = bits(id_ctrl_decoder_decoded_plaInput, 4, 4) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = bits(id_ctrl_decoder_decoded_invInputs, 5, 5) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = bits(id_ctrl_decoder_decoded_plaInput, 6, 6) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = bits(id_ctrl_decoder_decoded_invInputs, 12, 12) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = bits(id_ctrl_decoder_decoded_invInputs, 13, 13) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = bits(id_ctrl_decoder_decoded_invInputs, 14, 14) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = bits(id_ctrl_decoder_decoded_invInputs, 20, 20) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = bits(id_ctrl_decoder_decoded_invInputs, 21, 21) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = bits(id_ctrl_decoder_decoded_invInputs, 22, 22) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = bits(id_ctrl_decoder_decoded_invInputs, 23, 23) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = bits(id_ctrl_decoder_decoded_invInputs, 24, 24) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = bits(id_ctrl_decoder_decoded_invInputs, 26, 26) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = bits(id_ctrl_decoder_decoded_invInputs, 27, 27) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = bits(id_ctrl_decoder_decoded_plaInput, 28, 28) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = bits(id_ctrl_decoder_decoded_plaInput, 29, 29) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = bits(id_ctrl_decoder_decoded_plaInput, 30, 30) node id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = bits(id_ctrl_decoder_decoded_plaInput, 31, 31) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131) node id_ctrl_decoder_decoded_andMatrixOutputs_lo_193 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133) node id_ctrl_decoder_decoded_andMatrixOutputs_hi_193 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189) node _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_193) node id_ctrl_decoder_decoded_andMatrixOutputs_75_2 = andr(_id_ctrl_decoder_decoded_andMatrixOutputs_T_193) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_118_2, id_ctrl_decoder_decoded_andMatrixOutputs_85_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_40_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_127_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_86_2, id_ctrl_decoder_decoded_andMatrixOutputs_10_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_93_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_148_2, id_ctrl_decoder_decoded_andMatrixOutputs_76_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_87_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo) node _id_ctrl_decoder_decoded_orMatrixOutputs_T = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_1 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_137_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_3 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_4 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_117_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_5 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_21_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_6 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_185_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_7 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_155_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_47_2, id_ctrl_decoder_decoded_andMatrixOutputs_83_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_82_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_55_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_1) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_9 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_8) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_154_2, id_ctrl_decoder_decoded_andMatrixOutputs_23_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_101_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_57_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_166_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_122_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_1_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_42_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_188_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_34_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_28_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_155_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_126_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_17_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_121_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_71_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_190_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_139_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_11 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_10) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_176_2, id_ctrl_decoder_decoded_andMatrixOutputs_172_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_8_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_13 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_12) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_116_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_72_2, id_ctrl_decoder_decoded_andMatrixOutputs_81_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_157_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_45_2, id_ctrl_decoder_decoded_andMatrixOutputs_114_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_187_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_77_2, id_ctrl_decoder_decoded_andMatrixOutputs_92_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_22_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_3) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_15 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_14) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_16 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_181_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_136_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_153_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_123_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_50_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_22_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_4) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_18 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_17) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_130_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_153_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_124_2, id_ctrl_decoder_decoded_andMatrixOutputs_50_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_5) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_20 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_19) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_65_2, id_ctrl_decoder_decoded_andMatrixOutputs_79_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_177_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_6) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_22 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_21) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_65_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_23 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_58_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_24 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_23) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_169_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_25 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_7) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_26 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_25) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_27 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_14_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_28 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_83_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_111_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_29_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_8) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_30 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_29) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_149_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_167_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_104_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_144_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_94_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_56_2, id_ctrl_decoder_decoded_andMatrixOutputs_179_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_31 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_9) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_32 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_31) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_142_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_43_2, id_ctrl_decoder_decoded_andMatrixOutputs_3_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_4_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_73_2, id_ctrl_decoder_decoded_andMatrixOutputs_163_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_168_2, id_ctrl_decoder_decoded_andMatrixOutputs_36_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_112_2, id_ctrl_decoder_decoded_andMatrixOutputs_170_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_39_2, id_ctrl_decoder_decoded_andMatrixOutputs_115_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_162_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_33 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_10) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_34 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_33) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_5_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_8_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_150_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_133_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_44_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_35 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_11) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_36 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_35) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_183_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_147_2, id_ctrl_decoder_decoded_andMatrixOutputs_178_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_19_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_25_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_49_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_161_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_37 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_12) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_38 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_37) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_171_2, id_ctrl_decoder_decoded_andMatrixOutputs_37_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_122_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_108_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_11_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_69_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_27_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_39 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_13) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_40 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_39) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_151_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_135_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_52_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_180_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_189_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_0_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_126_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_95_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_140_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_164_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_78_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_29_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_41 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_14) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_42 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_41) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_66_2, id_ctrl_decoder_decoded_andMatrixOutputs_146_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_18 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_43 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_15) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_44 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_43) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_45 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_46 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_45) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_180_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_91_2, id_ctrl_decoder_decoded_andMatrixOutputs_2_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_24_2, id_ctrl_decoder_decoded_andMatrixOutputs_53_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_96_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_47 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_16) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_48 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_47) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_156_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_89_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_188_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_34_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_41_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_184_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_131_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_7_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_29_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_49 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_17) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_50 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_49) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_34_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_182_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_189_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_51 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_18) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_52 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_51) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_122_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_120_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_151_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_52_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_60_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_91_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_24_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_164_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_29_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_22 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_53 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_19) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_54 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_53) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_89_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_146_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_8_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_66_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_30_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_190_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_29_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_23 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_55 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_lo_20) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_56 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_55) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_21 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_68_2, id_ctrl_decoder_decoded_andMatrixOutputs_63_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_24 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_57 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_24, id_ctrl_decoder_decoded_orMatrixOutputs_lo_21) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_58 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_57) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_151_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_137_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_22 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_184_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_140_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_29_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_25 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_25, id_ctrl_decoder_decoded_orMatrixOutputs_lo_22) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_60 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_59) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_135_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_13_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_28_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_23 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_88_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_126_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_32_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_67_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_190_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_26 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_26, id_ctrl_decoder_decoded_orMatrixOutputs_lo_23) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_62 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_61) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_63 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_191_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_64 = orr(id_ctrl_decoder_decoded_andMatrixOutputs_164_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_65 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_66 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_65) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_158_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_136_2, id_ctrl_decoder_decoded_andMatrixOutputs_192_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_38_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_141_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_174_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_24 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_50_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_134_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_175_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_124_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_22_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_27 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_27, id_ctrl_decoder_decoded_orMatrixOutputs_lo_24) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_68 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_67) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_107_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_158_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_119_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_108_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_69_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_173_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_50_2) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_25 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_103_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_155_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_95_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_131_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_145_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_143_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = cat(id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_andMatrixOutputs_117_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_29_2) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_28 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_69 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_28, id_ctrl_decoder_decoded_orMatrixOutputs_lo_25) node _id_ctrl_decoder_decoded_orMatrixOutputs_T_70 = orr(_id_ctrl_decoder_decoded_orMatrixOutputs_T_69) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_3, _id_ctrl_decoder_decoded_orMatrixOutputs_T_1) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_5) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_4) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_9, _id_ctrl_decoder_decoded_orMatrixOutputs_T_7) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = cat(UInt<1>(0h0), _id_ctrl_decoder_decoded_orMatrixOutputs_T_13) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _id_ctrl_decoder_decoded_orMatrixOutputs_T_11) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_16, _id_ctrl_decoder_decoded_orMatrixOutputs_T_15) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_22, _id_ctrl_decoder_decoded_orMatrixOutputs_T_20) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_18) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_27, _id_ctrl_decoder_decoded_orMatrixOutputs_T_26) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_24) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_32, _id_ctrl_decoder_decoded_orMatrixOutputs_T_30) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_28) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15) node id_ctrl_decoder_decoded_orMatrixOutputs_lo_26 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_36, _id_ctrl_decoder_decoded_orMatrixOutputs_T_34) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_42, _id_ctrl_decoder_decoded_orMatrixOutputs_T_40) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_38) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_46, _id_ctrl_decoder_decoded_orMatrixOutputs_T_44) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_52, _id_ctrl_decoder_decoded_orMatrixOutputs_T_50) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_48) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_56, _id_ctrl_decoder_decoded_orMatrixOutputs_T_54) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_62, _id_ctrl_decoder_decoded_orMatrixOutputs_T_60) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_58) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_66, _id_ctrl_decoder_decoded_orMatrixOutputs_T_64) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_63) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = cat(_id_ctrl_decoder_decoded_orMatrixOutputs_T_70, _id_ctrl_decoder_decoded_orMatrixOutputs_T_68) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, UInt<1>(0h0)) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16) node id_ctrl_decoder_decoded_orMatrixOutputs_hi_29 = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21) node id_ctrl_decoder_decoded_orMatrixOutputs = cat(id_ctrl_decoder_decoded_orMatrixOutputs_hi_29, id_ctrl_decoder_decoded_orMatrixOutputs_lo_26) node _id_ctrl_decoder_decoded_invMatrixOutputs_T = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 0, 0) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_1 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 1, 1) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_2 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 2, 2) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_3 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 3, 3) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_4 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 4, 4) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_5 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 5, 5) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_6 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 6, 6) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_7 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 7, 7) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_8 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 8, 8) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_9 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 9, 9) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_10 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 10, 10) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_11 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 11, 11) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_12 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 12, 12) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_13 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 13, 13) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 14, 14) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 15, 15) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 16, 16) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_17 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 17, 17) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_18 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 18, 18) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_19 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 19, 19) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_20 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 20, 20) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_21 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 21, 21) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_22 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 22, 22) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_23 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 23, 23) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_24 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 24, 24) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_25 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 25, 25) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_26 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 26, 26) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_27 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 27, 27) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_28 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 28, 28) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_29 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 29, 29) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_30 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 30, 30) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_31 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 31, 31) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_32 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 32, 32) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_33 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 33, 33) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_34 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 34, 34) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_35 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 35, 35) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_36 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 36, 36) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_37 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 37, 37) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_38 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 38, 38) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_39 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 39, 39) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_40 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 40, 40) node _id_ctrl_decoder_decoded_invMatrixOutputs_T_41 = bits(id_ctrl_decoder_decoded_orMatrixOutputs, 41, 41) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_1, _id_ctrl_decoder_decoded_invMatrixOutputs_T) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_4, _id_ctrl_decoder_decoded_invMatrixOutputs_T_3) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_2) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_6, _id_ctrl_decoder_decoded_invMatrixOutputs_T_5) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_9, _id_ctrl_decoder_decoded_invMatrixOutputs_T_8) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_7) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_11, _id_ctrl_decoder_decoded_invMatrixOutputs_T_10) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_14, _id_ctrl_decoder_decoded_invMatrixOutputs_T_13) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_12) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_17, _id_ctrl_decoder_decoded_invMatrixOutputs_T_16) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_15) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_20, _id_ctrl_decoder_decoded_invMatrixOutputs_T_19) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_18) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_22, _id_ctrl_decoder_decoded_invMatrixOutputs_T_21) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_25, _id_ctrl_decoder_decoded_invMatrixOutputs_T_24) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_23) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_27, _id_ctrl_decoder_decoded_invMatrixOutputs_T_26) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_30, _id_ctrl_decoder_decoded_invMatrixOutputs_T_29) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_28) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_32, _id_ctrl_decoder_decoded_invMatrixOutputs_T_31) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_35, _id_ctrl_decoder_decoded_invMatrixOutputs_T_34) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_33) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_38, _id_ctrl_decoder_decoded_invMatrixOutputs_T_37) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_36) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(_id_ctrl_decoder_decoded_invMatrixOutputs_T_41, _id_ctrl_decoder_decoded_invMatrixOutputs_T_40) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_39) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo) node id_ctrl_decoder_decoded_invMatrixOutputs_hi = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo) node id_ctrl_decoder_decoded_invMatrixOutputs = cat(id_ctrl_decoder_decoded_invMatrixOutputs_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo) connect id_ctrl_decoder_decoded, id_ctrl_decoder_decoded_invMatrixOutputs connect id_ctrl_decoder_decoded_plaInput, ibuf.io.inst[0].bits.inst.bits node id_ctrl_decoder_0 = bits(id_ctrl_decoder_decoded, 41, 41) node id_ctrl_decoder_1 = bits(id_ctrl_decoder_decoded, 40, 40) node id_ctrl_decoder_2 = bits(id_ctrl_decoder_decoded, 39, 39) node id_ctrl_decoder_3 = bits(id_ctrl_decoder_decoded, 38, 38) node id_ctrl_decoder_4 = bits(id_ctrl_decoder_decoded, 37, 37) node id_ctrl_decoder_5 = bits(id_ctrl_decoder_decoded, 36, 36) node id_ctrl_decoder_6 = bits(id_ctrl_decoder_decoded, 35, 35) node id_ctrl_decoder_7 = bits(id_ctrl_decoder_decoded, 34, 34) node id_ctrl_decoder_8 = bits(id_ctrl_decoder_decoded, 33, 31) node id_ctrl_decoder_9 = bits(id_ctrl_decoder_decoded, 30, 29) node id_ctrl_decoder_10 = bits(id_ctrl_decoder_decoded, 28, 26) node id_ctrl_decoder_11 = bits(id_ctrl_decoder_decoded, 25, 25) node id_ctrl_decoder_12 = bits(id_ctrl_decoder_decoded, 24, 20) node id_ctrl_decoder_13 = bits(id_ctrl_decoder_decoded, 19, 19) node id_ctrl_decoder_14 = bits(id_ctrl_decoder_decoded, 18, 14) node id_ctrl_decoder_15 = bits(id_ctrl_decoder_decoded, 13, 13) node id_ctrl_decoder_16 = bits(id_ctrl_decoder_decoded, 12, 12) node id_ctrl_decoder_17 = bits(id_ctrl_decoder_decoded, 11, 11) node id_ctrl_decoder_18 = bits(id_ctrl_decoder_decoded, 10, 10) node id_ctrl_decoder_19 = bits(id_ctrl_decoder_decoded, 9, 9) node id_ctrl_decoder_20 = bits(id_ctrl_decoder_decoded, 8, 8) node id_ctrl_decoder_21 = bits(id_ctrl_decoder_decoded, 7, 7) node id_ctrl_decoder_22 = bits(id_ctrl_decoder_decoded, 6, 4) node id_ctrl_decoder_23 = bits(id_ctrl_decoder_decoded, 3, 3) node id_ctrl_decoder_24 = bits(id_ctrl_decoder_decoded, 2, 2) node id_ctrl_decoder_25 = bits(id_ctrl_decoder_decoded, 1, 1) node id_ctrl_decoder_26 = bits(id_ctrl_decoder_decoded, 0, 0) connect id_ctrl.legal, id_ctrl_decoder_0 connect id_ctrl.fp, id_ctrl_decoder_1 connect id_ctrl.rocc, id_ctrl_decoder_2 connect id_ctrl.branch, id_ctrl_decoder_3 connect id_ctrl.jal, id_ctrl_decoder_4 connect id_ctrl.jalr, id_ctrl_decoder_5 connect id_ctrl.rxs2, id_ctrl_decoder_6 connect id_ctrl.rxs1, id_ctrl_decoder_7 connect id_ctrl.sel_alu2, id_ctrl_decoder_8 connect id_ctrl.sel_alu1, id_ctrl_decoder_9 connect id_ctrl.sel_imm, id_ctrl_decoder_10 connect id_ctrl.alu_dw, id_ctrl_decoder_11 connect id_ctrl.alu_fn, id_ctrl_decoder_12 connect id_ctrl.mem, id_ctrl_decoder_13 connect id_ctrl.mem_cmd, id_ctrl_decoder_14 connect id_ctrl.rfs1, id_ctrl_decoder_15 connect id_ctrl.rfs2, id_ctrl_decoder_16 connect id_ctrl.rfs3, id_ctrl_decoder_17 connect id_ctrl.wfd, id_ctrl_decoder_18 connect id_ctrl.mul, id_ctrl_decoder_19 connect id_ctrl.div, id_ctrl_decoder_20 connect id_ctrl.wxd, id_ctrl_decoder_21 connect id_ctrl.csr, id_ctrl_decoder_22 connect id_ctrl.fence_i, id_ctrl_decoder_23 connect id_ctrl.fence, id_ctrl_decoder_24 connect id_ctrl.amo, id_ctrl_decoder_25 connect id_ctrl.dp, id_ctrl_decoder_26 node id_raddr3 = bits(ibuf.io.inst[0].bits.inst.rs3, 4, 0) node id_raddr2 = bits(ibuf.io.inst[0].bits.inst.rs2, 4, 0) node id_raddr1 = bits(ibuf.io.inst[0].bits.inst.rs1, 4, 0) node id_waddr = bits(ibuf.io.inst[0].bits.inst.rd, 4, 0) wire id_load_use : UInt<1> regreset id_reg_fence : UInt<1>, clock, reset, UInt<1>(0h0) cmem rf : UInt<64> [31] wire id_rs_0 : UInt node _id_rs_T = eq(id_raddr1, UInt<1>(0h0)) node _id_rs_T_1 = and(UInt<1>(0h0), _id_rs_T) node _id_rs_T_2 = bits(id_raddr1, 4, 0) node _id_rs_T_3 = not(_id_rs_T_2) infer mport id_rs_MPORT = rf[_id_rs_T_3], clock node _id_rs_T_4 = mux(_id_rs_T_1, UInt<1>(0h0), id_rs_MPORT) connect id_rs_0, _id_rs_T_4 wire id_rs_1 : UInt node _id_rs_T_5 = eq(id_raddr2, UInt<1>(0h0)) node _id_rs_T_6 = and(UInt<1>(0h0), _id_rs_T_5) node _id_rs_T_7 = bits(id_raddr2, 4, 0) node _id_rs_T_8 = not(_id_rs_T_7) infer mport id_rs_MPORT_1 = rf[_id_rs_T_8], clock node _id_rs_T_9 = mux(_id_rs_T_6, UInt<1>(0h0), id_rs_MPORT_1) connect id_rs_1, _id_rs_T_9 wire ctrl_killd : UInt<1> node _id_npc_T = asSInt(ibuf.io.pc) node _id_npc_sign_T = eq(UInt<3>(0h3), UInt<3>(0h5)) node _id_npc_sign_T_1 = bits(ibuf.io.inst[0].bits.inst.bits, 31, 31) node _id_npc_sign_T_2 = asSInt(_id_npc_sign_T_1) node id_npc_sign = mux(_id_npc_sign_T, asSInt(UInt<1>(0h0)), _id_npc_sign_T_2) node _id_npc_b30_20_T = eq(UInt<3>(0h3), UInt<3>(0h2)) node _id_npc_b30_20_T_1 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 20) node _id_npc_b30_20_T_2 = asSInt(_id_npc_b30_20_T_1) node id_npc_b30_20 = mux(_id_npc_b30_20_T, _id_npc_b30_20_T_2, id_npc_sign) node _id_npc_b19_12_T = neq(UInt<3>(0h3), UInt<3>(0h2)) node _id_npc_b19_12_T_1 = neq(UInt<3>(0h3), UInt<3>(0h3)) node _id_npc_b19_12_T_2 = and(_id_npc_b19_12_T, _id_npc_b19_12_T_1) node _id_npc_b19_12_T_3 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 12) node _id_npc_b19_12_T_4 = asSInt(_id_npc_b19_12_T_3) node id_npc_b19_12 = mux(_id_npc_b19_12_T_2, id_npc_sign, _id_npc_b19_12_T_4) node _id_npc_b11_T = eq(UInt<3>(0h3), UInt<3>(0h2)) node _id_npc_b11_T_1 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _id_npc_b11_T_2 = or(_id_npc_b11_T, _id_npc_b11_T_1) node _id_npc_b11_T_3 = eq(UInt<3>(0h3), UInt<3>(0h3)) node _id_npc_b11_T_4 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) node _id_npc_b11_T_5 = asSInt(_id_npc_b11_T_4) node _id_npc_b11_T_6 = eq(UInt<3>(0h3), UInt<3>(0h1)) node _id_npc_b11_T_7 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) node _id_npc_b11_T_8 = asSInt(_id_npc_b11_T_7) node _id_npc_b11_T_9 = mux(_id_npc_b11_T_6, _id_npc_b11_T_8, id_npc_sign) node _id_npc_b11_T_10 = mux(_id_npc_b11_T_3, _id_npc_b11_T_5, _id_npc_b11_T_9) node id_npc_b11 = mux(_id_npc_b11_T_2, asSInt(UInt<1>(0h0)), _id_npc_b11_T_10) node _id_npc_b10_5_T = eq(UInt<3>(0h3), UInt<3>(0h2)) node _id_npc_b10_5_T_1 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _id_npc_b10_5_T_2 = or(_id_npc_b10_5_T, _id_npc_b10_5_T_1) node _id_npc_b10_5_T_3 = bits(ibuf.io.inst[0].bits.inst.bits, 30, 25) node id_npc_b10_5 = mux(_id_npc_b10_5_T_2, UInt<1>(0h0), _id_npc_b10_5_T_3) node _id_npc_b4_1_T = eq(UInt<3>(0h3), UInt<3>(0h2)) node _id_npc_b4_1_T_1 = eq(UInt<3>(0h3), UInt<3>(0h0)) node _id_npc_b4_1_T_2 = eq(UInt<3>(0h3), UInt<3>(0h1)) node _id_npc_b4_1_T_3 = or(_id_npc_b4_1_T_1, _id_npc_b4_1_T_2) node _id_npc_b4_1_T_4 = bits(ibuf.io.inst[0].bits.inst.bits, 11, 8) node _id_npc_b4_1_T_5 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _id_npc_b4_1_T_6 = bits(ibuf.io.inst[0].bits.inst.bits, 19, 16) node _id_npc_b4_1_T_7 = bits(ibuf.io.inst[0].bits.inst.bits, 24, 21) node _id_npc_b4_1_T_8 = mux(_id_npc_b4_1_T_5, _id_npc_b4_1_T_6, _id_npc_b4_1_T_7) node _id_npc_b4_1_T_9 = mux(_id_npc_b4_1_T_3, _id_npc_b4_1_T_4, _id_npc_b4_1_T_8) node id_npc_b4_1 = mux(_id_npc_b4_1_T, UInt<1>(0h0), _id_npc_b4_1_T_9) node _id_npc_b0_T = eq(UInt<3>(0h3), UInt<3>(0h0)) node _id_npc_b0_T_1 = bits(ibuf.io.inst[0].bits.inst.bits, 7, 7) node _id_npc_b0_T_2 = eq(UInt<3>(0h3), UInt<3>(0h4)) node _id_npc_b0_T_3 = bits(ibuf.io.inst[0].bits.inst.bits, 20, 20) node _id_npc_b0_T_4 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _id_npc_b0_T_5 = bits(ibuf.io.inst[0].bits.inst.bits, 15, 15) node _id_npc_b0_T_6 = mux(_id_npc_b0_T_4, _id_npc_b0_T_5, UInt<1>(0h0)) node _id_npc_b0_T_7 = mux(_id_npc_b0_T_2, _id_npc_b0_T_3, _id_npc_b0_T_6) node id_npc_b0 = mux(_id_npc_b0_T, _id_npc_b0_T_1, _id_npc_b0_T_7) node id_npc_lo_hi = cat(id_npc_b10_5, id_npc_b4_1) node id_npc_lo = cat(id_npc_lo_hi, id_npc_b0) node id_npc_hi_lo_lo = asUInt(id_npc_b11) node id_npc_hi_lo_hi = asUInt(id_npc_b19_12) node id_npc_hi_lo = cat(id_npc_hi_lo_hi, id_npc_hi_lo_lo) node id_npc_hi_hi_lo = asUInt(id_npc_b30_20) node id_npc_hi_hi_hi = asUInt(id_npc_sign) node id_npc_hi_hi = cat(id_npc_hi_hi_hi, id_npc_hi_hi_lo) node id_npc_hi = cat(id_npc_hi_hi, id_npc_hi_lo) node _id_npc_T_1 = cat(id_npc_hi, id_npc_lo) node _id_npc_T_2 = asSInt(_id_npc_T_1) node _id_npc_T_3 = add(_id_npc_T, _id_npc_T_2) node _id_npc_T_4 = tail(_id_npc_T_3, 1) node _id_npc_T_5 = asSInt(_id_npc_T_4) node id_npc = asUInt(_id_npc_T_5) inst csr of CSRFile_4 connect csr.clock, clock connect csr.reset, reset node _id_csr_en_T = eq(id_ctrl.csr, UInt<3>(0h6)) node _id_csr_en_T_1 = eq(id_ctrl.csr, UInt<3>(0h7)) node _id_csr_en_T_2 = eq(id_ctrl.csr, UInt<3>(0h5)) node _id_csr_en_T_3 = or(_id_csr_en_T, _id_csr_en_T_1) node id_csr_en = or(_id_csr_en_T_3, _id_csr_en_T_2) node id_system_insn = eq(id_ctrl.csr, UInt<3>(0h4)) node _id_csr_ren_T = eq(id_ctrl.csr, UInt<3>(0h6)) node _id_csr_ren_T_1 = eq(id_ctrl.csr, UInt<3>(0h7)) node _id_csr_ren_T_2 = or(_id_csr_ren_T, _id_csr_ren_T_1) node _id_csr_ren_T_3 = eq(ibuf.io.inst[0].bits.inst.rs1, UInt<1>(0h0)) node id_csr_ren = and(_id_csr_ren_T_2, _id_csr_ren_T_3) node _id_csr_T = and(id_system_insn, id_ctrl.mem) node _id_csr_T_1 = mux(id_csr_ren, UInt<3>(0h2), id_ctrl.csr) node id_csr = mux(_id_csr_T, UInt<3>(0h0), _id_csr_T_1) node _id_csr_flush_T = eq(id_csr_ren, UInt<1>(0h0)) node _id_csr_flush_T_1 = and(id_csr_en, _id_csr_flush_T) node _id_csr_flush_T_2 = and(_id_csr_flush_T_1, csr.io.decode[0].write_flush) node id_csr_flush = or(id_system_insn, _id_csr_flush_T_2) node _id_set_vconfig_T = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>(0h8000707f)) node _id_set_vconfig_T_1 = eq(UInt<15>(0h7057), _id_set_vconfig_T) node _id_set_vconfig_T_2 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>(0hc000707f)) node _id_set_vconfig_T_3 = eq(UInt<32>(0hc0007057), _id_set_vconfig_T_2) node _id_set_vconfig_T_4 = and(ibuf.io.inst[0].bits.inst.bits, UInt<32>(0hfe00707f)) node _id_set_vconfig_T_5 = eq(UInt<32>(0h80007057), _id_set_vconfig_T_4) node _id_set_vconfig_T_6 = or(_id_set_vconfig_T_1, _id_set_vconfig_T_3) node _id_set_vconfig_T_7 = or(_id_set_vconfig_T_6, _id_set_vconfig_T_5) node id_set_vconfig = and(_id_set_vconfig_T_7, UInt<1>(0h0)) connect id_ctrl.vec, UInt<1>(0h0) node _id_illegal_insn_T = eq(id_ctrl.legal, UInt<1>(0h0)) node _id_illegal_insn_T_1 = or(id_ctrl.mul, id_ctrl.div) node _id_illegal_insn_T_2 = bits(csr.io.status.isa, 12, 12) node _id_illegal_insn_T_3 = eq(_id_illegal_insn_T_2, UInt<1>(0h0)) node _id_illegal_insn_T_4 = and(_id_illegal_insn_T_1, _id_illegal_insn_T_3) node _id_illegal_insn_T_5 = or(_id_illegal_insn_T, _id_illegal_insn_T_4) node _id_illegal_insn_T_6 = bits(csr.io.status.isa, 0, 0) node _id_illegal_insn_T_7 = eq(_id_illegal_insn_T_6, UInt<1>(0h0)) node _id_illegal_insn_T_8 = and(id_ctrl.amo, _id_illegal_insn_T_7) node _id_illegal_insn_T_9 = or(_id_illegal_insn_T_5, _id_illegal_insn_T_8) node _id_illegal_insn_T_10 = eq(id_ctrl.vec, UInt<1>(0h0)) node _id_illegal_insn_T_11 = and(io.fpu.illegal_rm, _id_illegal_insn_T_10) node _id_illegal_insn_T_12 = or(csr.io.decode[0].fp_illegal, _id_illegal_insn_T_11) node _id_illegal_insn_T_13 = and(id_ctrl.fp, _id_illegal_insn_T_12) node _id_illegal_insn_T_14 = or(_id_illegal_insn_T_9, _id_illegal_insn_T_13) node _id_illegal_insn_T_15 = or(csr.io.decode[0].vector_illegal, UInt<1>(0h0)) node _id_illegal_insn_T_16 = and(id_ctrl.vec, _id_illegal_insn_T_15) node _id_illegal_insn_T_17 = or(_id_illegal_insn_T_14, _id_illegal_insn_T_16) node _id_illegal_insn_T_18 = bits(csr.io.status.isa, 3, 3) node _id_illegal_insn_T_19 = eq(_id_illegal_insn_T_18, UInt<1>(0h0)) node _id_illegal_insn_T_20 = and(id_ctrl.dp, _id_illegal_insn_T_19) node _id_illegal_insn_T_21 = or(_id_illegal_insn_T_17, _id_illegal_insn_T_20) node _id_illegal_insn_T_22 = bits(csr.io.status.isa, 2, 2) node _id_illegal_insn_T_23 = eq(_id_illegal_insn_T_22, UInt<1>(0h0)) node _id_illegal_insn_T_24 = and(ibuf.io.inst[0].bits.rvc, _id_illegal_insn_T_23) node _id_illegal_insn_T_25 = or(_id_illegal_insn_T_21, _id_illegal_insn_T_24) node _id_illegal_insn_T_26 = and(UInt<1>(0h0), id_ctrl.rxs2) node _id_illegal_insn_T_27 = or(_id_illegal_insn_T_25, _id_illegal_insn_T_26) node _id_illegal_insn_T_28 = and(UInt<1>(0h0), id_ctrl.rxs1) node _id_illegal_insn_T_29 = or(_id_illegal_insn_T_27, _id_illegal_insn_T_28) node _id_illegal_insn_T_30 = and(UInt<1>(0h0), id_ctrl.wxd) node _id_illegal_insn_T_31 = or(_id_illegal_insn_T_29, _id_illegal_insn_T_30) node _id_illegal_insn_T_32 = and(id_ctrl.rocc, csr.io.decode[0].rocc_illegal) node _id_illegal_insn_T_33 = or(_id_illegal_insn_T_31, _id_illegal_insn_T_32) node _id_illegal_insn_T_34 = eq(id_csr_ren, UInt<1>(0h0)) node _id_illegal_insn_T_35 = and(_id_illegal_insn_T_34, csr.io.decode[0].write_illegal) node _id_illegal_insn_T_36 = or(csr.io.decode[0].read_illegal, _id_illegal_insn_T_35) node _id_illegal_insn_T_37 = and(id_csr_en, _id_illegal_insn_T_36) node _id_illegal_insn_T_38 = or(_id_illegal_insn_T_33, _id_illegal_insn_T_37) node _id_illegal_insn_T_39 = eq(ibuf.io.inst[0].bits.rvc, UInt<1>(0h0)) node _id_illegal_insn_T_40 = and(id_system_insn, csr.io.decode[0].system_illegal) node _id_illegal_insn_T_41 = and(_id_illegal_insn_T_39, _id_illegal_insn_T_40) node id_illegal_insn = or(_id_illegal_insn_T_38, _id_illegal_insn_T_41) node _id_virtual_insn_T = eq(id_csr_ren, UInt<1>(0h0)) node _id_virtual_insn_T_1 = and(_id_virtual_insn_T, csr.io.decode[0].write_illegal) node _id_virtual_insn_T_2 = eq(_id_virtual_insn_T_1, UInt<1>(0h0)) node _id_virtual_insn_T_3 = and(id_csr_en, _id_virtual_insn_T_2) node _id_virtual_insn_T_4 = and(_id_virtual_insn_T_3, csr.io.decode[0].virtual_access_illegal) node _id_virtual_insn_T_5 = eq(ibuf.io.inst[0].bits.rvc, UInt<1>(0h0)) node _id_virtual_insn_T_6 = and(_id_virtual_insn_T_5, id_system_insn) node _id_virtual_insn_T_7 = and(_id_virtual_insn_T_6, csr.io.decode[0].virtual_system_illegal) node _id_virtual_insn_T_8 = or(_id_virtual_insn_T_4, _id_virtual_insn_T_7) node id_virtual_insn = and(id_ctrl.legal, _id_virtual_insn_T_8) node id_amo_aq = bits(ibuf.io.inst[0].bits.inst.bits, 26, 26) node id_amo_rl = bits(ibuf.io.inst[0].bits.inst.bits, 25, 25) node id_fence_pred = bits(ibuf.io.inst[0].bits.inst.bits, 27, 24) node id_fence_succ = bits(ibuf.io.inst[0].bits.inst.bits, 23, 20) node _id_fence_next_T = and(id_ctrl.amo, id_amo_aq) node id_fence_next = or(id_ctrl.fence, _id_fence_next_T) node _id_mem_busy_T = eq(io.dmem.ordered, UInt<1>(0h0)) node id_mem_busy = or(_id_mem_busy_T, io.dmem.req.valid) node _T = eq(id_mem_busy, UInt<1>(0h0)) when _T : connect id_reg_fence, UInt<1>(0h0) node _id_rocc_busy_T = and(ex_reg_valid, ex_ctrl.rocc) node _id_rocc_busy_T_1 = or(io.rocc.busy, _id_rocc_busy_T) node _id_rocc_busy_T_2 = and(mem_reg_valid, mem_ctrl.rocc) node _id_rocc_busy_T_3 = or(_id_rocc_busy_T_1, _id_rocc_busy_T_2) node _id_rocc_busy_T_4 = and(wb_reg_valid, wb_ctrl.rocc) node _id_rocc_busy_T_5 = or(_id_rocc_busy_T_3, _id_rocc_busy_T_4) node id_rocc_busy = and(UInt<1>(0h0), _id_rocc_busy_T_5) node _id_csr_rocc_write_T = and(UInt<1>(0h0), id_csr_en) node _id_csr_rocc_write_T_1 = eq(id_csr_ren, UInt<1>(0h0)) node id_csr_rocc_write = and(_id_csr_rocc_write_T, _id_csr_rocc_write_T_1) node _id_do_fence_T = or(id_ctrl.fence, id_csr_rocc_write) node _id_do_fence_T_1 = and(id_rocc_busy, _id_do_fence_T) node _id_do_fence_T_2 = and(UInt<1>(0h0), id_ctrl.fence) node _id_do_fence_T_3 = or(_id_do_fence_T_1, _id_do_fence_T_2) node _id_do_fence_T_4 = and(id_ctrl.amo, id_amo_rl) node _id_do_fence_T_5 = or(_id_do_fence_T_4, id_ctrl.fence_i) node _id_do_fence_T_6 = or(id_ctrl.mem, id_ctrl.rocc) node _id_do_fence_T_7 = and(id_reg_fence, _id_do_fence_T_6) node _id_do_fence_T_8 = or(_id_do_fence_T_5, _id_do_fence_T_7) node _id_do_fence_T_9 = and(id_mem_busy, _id_do_fence_T_8) node _id_do_fence_T_10 = or(_id_do_fence_T_3, _id_do_fence_T_9) wire id_do_fence : UInt<1> connect id_do_fence, _id_do_fence_T_10 inst bpu of BreakpointUnit_4 connect bpu.clock, clock connect bpu.reset, reset connect bpu.io.status.uie, csr.io.status.uie connect bpu.io.status.sie, csr.io.status.sie connect bpu.io.status.hie, csr.io.status.hie connect bpu.io.status.mie, csr.io.status.mie connect bpu.io.status.upie, csr.io.status.upie connect bpu.io.status.spie, csr.io.status.spie connect bpu.io.status.ube, csr.io.status.ube connect bpu.io.status.mpie, csr.io.status.mpie connect bpu.io.status.spp, csr.io.status.spp connect bpu.io.status.vs, csr.io.status.vs connect bpu.io.status.mpp, csr.io.status.mpp connect bpu.io.status.fs, csr.io.status.fs connect bpu.io.status.xs, csr.io.status.xs connect bpu.io.status.mprv, csr.io.status.mprv connect bpu.io.status.sum, csr.io.status.sum connect bpu.io.status.mxr, csr.io.status.mxr connect bpu.io.status.tvm, csr.io.status.tvm connect bpu.io.status.tw, csr.io.status.tw connect bpu.io.status.tsr, csr.io.status.tsr connect bpu.io.status.zero1, csr.io.status.zero1 connect bpu.io.status.sd_rv32, csr.io.status.sd_rv32 connect bpu.io.status.uxl, csr.io.status.uxl connect bpu.io.status.sxl, csr.io.status.sxl connect bpu.io.status.sbe, csr.io.status.sbe connect bpu.io.status.mbe, csr.io.status.mbe connect bpu.io.status.gva, csr.io.status.gva connect bpu.io.status.mpv, csr.io.status.mpv connect bpu.io.status.zero2, csr.io.status.zero2 connect bpu.io.status.sd, csr.io.status.sd connect bpu.io.status.v, csr.io.status.v connect bpu.io.status.prv, csr.io.status.prv connect bpu.io.status.dv, csr.io.status.dv connect bpu.io.status.dprv, csr.io.status.dprv connect bpu.io.status.isa, csr.io.status.isa connect bpu.io.status.wfi, csr.io.status.wfi connect bpu.io.status.cease, csr.io.status.cease connect bpu.io.status.debug, csr.io.status.debug connect bpu.io.bp[0].textra.sselect, csr.io.bp[0].textra.sselect connect bpu.io.bp[0].textra.pad1, csr.io.bp[0].textra.pad1 connect bpu.io.bp[0].textra.svalue, csr.io.bp[0].textra.svalue connect bpu.io.bp[0].textra.pad2, csr.io.bp[0].textra.pad2 connect bpu.io.bp[0].textra.mselect, csr.io.bp[0].textra.mselect connect bpu.io.bp[0].textra.mvalue, csr.io.bp[0].textra.mvalue connect bpu.io.bp[0].address, csr.io.bp[0].address connect bpu.io.bp[0].control.r, csr.io.bp[0].control.r connect bpu.io.bp[0].control.w, csr.io.bp[0].control.w connect bpu.io.bp[0].control.x, csr.io.bp[0].control.x connect bpu.io.bp[0].control.u, csr.io.bp[0].control.u connect bpu.io.bp[0].control.s, csr.io.bp[0].control.s connect bpu.io.bp[0].control.h, csr.io.bp[0].control.h connect bpu.io.bp[0].control.m, csr.io.bp[0].control.m connect bpu.io.bp[0].control.tmatch, csr.io.bp[0].control.tmatch connect bpu.io.bp[0].control.zero, csr.io.bp[0].control.zero connect bpu.io.bp[0].control.chain, csr.io.bp[0].control.chain connect bpu.io.bp[0].control.action, csr.io.bp[0].control.action connect bpu.io.bp[0].control.reserved, csr.io.bp[0].control.reserved connect bpu.io.bp[0].control.maskmax, csr.io.bp[0].control.maskmax connect bpu.io.bp[0].control.dmode, csr.io.bp[0].control.dmode connect bpu.io.bp[0].control.ttype, csr.io.bp[0].control.ttype connect bpu.io.pc, ibuf.io.pc connect bpu.io.ea, mem_reg_wdata connect bpu.io.mcontext, csr.io.mcontext connect bpu.io.scontext, csr.io.scontext node _T_1 = or(csr.io.interrupt, bpu.io.debug_if) node _T_2 = or(_T_1, bpu.io.xcpt_if) node _T_3 = or(_T_2, ibuf.io.inst[0].bits.xcpt0.pf.inst) node _T_4 = or(_T_3, ibuf.io.inst[0].bits.xcpt0.gf.inst) node _T_5 = or(_T_4, ibuf.io.inst[0].bits.xcpt0.ae.inst) node _T_6 = or(_T_5, ibuf.io.inst[0].bits.xcpt1.pf.inst) node _T_7 = or(_T_6, ibuf.io.inst[0].bits.xcpt1.gf.inst) node _T_8 = or(_T_7, ibuf.io.inst[0].bits.xcpt1.ae.inst) node _T_9 = or(_T_8, id_virtual_insn) node _T_10 = or(_T_9, id_illegal_insn) wire id_xcpt : UInt<1> connect id_xcpt, _T_10 node _T_11 = mux(id_virtual_insn, UInt<5>(0h16), UInt<2>(0h2)) node _T_12 = mux(ibuf.io.inst[0].bits.xcpt1.ae.inst, UInt<1>(0h1), _T_11) node _T_13 = mux(ibuf.io.inst[0].bits.xcpt1.gf.inst, UInt<5>(0h14), _T_12) node _T_14 = mux(ibuf.io.inst[0].bits.xcpt1.pf.inst, UInt<4>(0hc), _T_13) node _T_15 = mux(ibuf.io.inst[0].bits.xcpt0.ae.inst, UInt<1>(0h1), _T_14) node _T_16 = mux(ibuf.io.inst[0].bits.xcpt0.gf.inst, UInt<5>(0h14), _T_15) node _T_17 = mux(ibuf.io.inst[0].bits.xcpt0.pf.inst, UInt<4>(0hc), _T_16) node _T_18 = mux(bpu.io.xcpt_if, UInt<2>(0h3), _T_17) node _T_19 = mux(bpu.io.debug_if, UInt<4>(0he), _T_18) node _T_20 = mux(csr.io.interrupt, csr.io.interrupt_cause, _T_19) wire id_cause : UInt connect id_cause, _T_20 node _T_21 = eq(id_cause, UInt<4>(0he)) node _T_22 = and(id_xcpt, _T_21) node _T_23 = eq(id_cause, UInt<2>(0h3)) node _T_24 = and(id_xcpt, _T_23) node _T_25 = eq(id_cause, UInt<1>(0h1)) node _T_26 = and(id_xcpt, _T_25) node _T_27 = eq(id_cause, UInt<2>(0h2)) node _T_28 = and(id_xcpt, _T_27) node _T_29 = eq(id_cause, UInt<4>(0hc)) node _T_30 = and(id_xcpt, _T_29) node dcache_bypass_data = bits(io.dmem.resp.bits.data_word_bypass, 63, 0) node _ex_waddr_T = bits(ex_reg_inst, 11, 7) node ex_waddr = and(_ex_waddr_T, UInt<5>(0h1f)) node _mem_waddr_T = bits(mem_reg_inst, 11, 7) node mem_waddr = and(_mem_waddr_T, UInt<5>(0h1f)) node _wb_waddr_T = bits(wb_reg_inst, 11, 7) node wb_waddr = and(_wb_waddr_T, UInt<5>(0h1f)) node bypass_sources_1_1 = and(ex_reg_valid, ex_ctrl.wxd) node _bypass_sources_T = and(mem_reg_valid, mem_ctrl.wxd) node _bypass_sources_T_1 = eq(mem_ctrl.mem, UInt<1>(0h0)) node bypass_sources_2_1 = and(_bypass_sources_T, _bypass_sources_T_1) node bypass_sources_3_1 = and(mem_reg_valid, mem_ctrl.wxd) node _id_bypass_src_T = eq(UInt<1>(0h0), id_raddr1) node id_bypass_src_0_0 = and(UInt<1>(0h1), _id_bypass_src_T) node _id_bypass_src_T_1 = eq(ex_waddr, id_raddr1) node id_bypass_src_0_1 = and(bypass_sources_1_1, _id_bypass_src_T_1) node _id_bypass_src_T_2 = eq(mem_waddr, id_raddr1) node id_bypass_src_0_2 = and(bypass_sources_2_1, _id_bypass_src_T_2) node _id_bypass_src_T_3 = eq(mem_waddr, id_raddr1) node id_bypass_src_0_3 = and(bypass_sources_3_1, _id_bypass_src_T_3) node _id_bypass_src_T_4 = eq(UInt<1>(0h0), id_raddr2) node id_bypass_src_1_0 = and(UInt<1>(0h1), _id_bypass_src_T_4) node _id_bypass_src_T_5 = eq(ex_waddr, id_raddr2) node id_bypass_src_1_1 = and(bypass_sources_1_1, _id_bypass_src_T_5) node _id_bypass_src_T_6 = eq(mem_waddr, id_raddr2) node id_bypass_src_1_2 = and(bypass_sources_2_1, _id_bypass_src_T_6) node _id_bypass_src_T_7 = eq(mem_waddr, id_raddr2) node id_bypass_src_1_3 = and(bypass_sources_3_1, _id_bypass_src_T_7) reg ex_reg_rs_bypass : UInt<1>[2], clock reg ex_reg_rs_lsb : UInt<2>[2], clock reg ex_reg_rs_msb : UInt[2], clock node _ex_rs_T = eq(ex_reg_rs_lsb[0], UInt<1>(0h1)) node _ex_rs_T_1 = mux(_ex_rs_T, mem_reg_wdata, UInt<1>(0h0)) node _ex_rs_T_2 = eq(ex_reg_rs_lsb[0], UInt<2>(0h2)) node _ex_rs_T_3 = mux(_ex_rs_T_2, wb_reg_wdata, _ex_rs_T_1) node _ex_rs_T_4 = eq(ex_reg_rs_lsb[0], UInt<2>(0h3)) node _ex_rs_T_5 = mux(_ex_rs_T_4, dcache_bypass_data, _ex_rs_T_3) node _ex_rs_T_6 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) node ex_rs_0 = mux(ex_reg_rs_bypass[0], _ex_rs_T_5, _ex_rs_T_6) node _ex_rs_T_7 = eq(ex_reg_rs_lsb[1], UInt<1>(0h1)) node _ex_rs_T_8 = mux(_ex_rs_T_7, mem_reg_wdata, UInt<1>(0h0)) node _ex_rs_T_9 = eq(ex_reg_rs_lsb[1], UInt<2>(0h2)) node _ex_rs_T_10 = mux(_ex_rs_T_9, wb_reg_wdata, _ex_rs_T_8) node _ex_rs_T_11 = eq(ex_reg_rs_lsb[1], UInt<2>(0h3)) node _ex_rs_T_12 = mux(_ex_rs_T_11, dcache_bypass_data, _ex_rs_T_10) node _ex_rs_T_13 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) node ex_rs_1 = mux(ex_reg_rs_bypass[1], _ex_rs_T_12, _ex_rs_T_13) node _ex_imm_sign_T = eq(ex_ctrl.sel_imm, UInt<3>(0h5)) node _ex_imm_sign_T_1 = bits(ex_reg_inst, 31, 31) node _ex_imm_sign_T_2 = asSInt(_ex_imm_sign_T_1) node ex_imm_sign = mux(_ex_imm_sign_T, asSInt(UInt<1>(0h0)), _ex_imm_sign_T_2) node _ex_imm_b30_20_T = eq(ex_ctrl.sel_imm, UInt<3>(0h2)) node _ex_imm_b30_20_T_1 = bits(ex_reg_inst, 30, 20) node _ex_imm_b30_20_T_2 = asSInt(_ex_imm_b30_20_T_1) node ex_imm_b30_20 = mux(_ex_imm_b30_20_T, _ex_imm_b30_20_T_2, ex_imm_sign) node _ex_imm_b19_12_T = neq(ex_ctrl.sel_imm, UInt<3>(0h2)) node _ex_imm_b19_12_T_1 = neq(ex_ctrl.sel_imm, UInt<3>(0h3)) node _ex_imm_b19_12_T_2 = and(_ex_imm_b19_12_T, _ex_imm_b19_12_T_1) node _ex_imm_b19_12_T_3 = bits(ex_reg_inst, 19, 12) node _ex_imm_b19_12_T_4 = asSInt(_ex_imm_b19_12_T_3) node ex_imm_b19_12 = mux(_ex_imm_b19_12_T_2, ex_imm_sign, _ex_imm_b19_12_T_4) node _ex_imm_b11_T = eq(ex_ctrl.sel_imm, UInt<3>(0h2)) node _ex_imm_b11_T_1 = eq(ex_ctrl.sel_imm, UInt<3>(0h5)) node _ex_imm_b11_T_2 = or(_ex_imm_b11_T, _ex_imm_b11_T_1) node _ex_imm_b11_T_3 = eq(ex_ctrl.sel_imm, UInt<3>(0h3)) node _ex_imm_b11_T_4 = bits(ex_reg_inst, 20, 20) node _ex_imm_b11_T_5 = asSInt(_ex_imm_b11_T_4) node _ex_imm_b11_T_6 = eq(ex_ctrl.sel_imm, UInt<3>(0h1)) node _ex_imm_b11_T_7 = bits(ex_reg_inst, 7, 7) node _ex_imm_b11_T_8 = asSInt(_ex_imm_b11_T_7) node _ex_imm_b11_T_9 = mux(_ex_imm_b11_T_6, _ex_imm_b11_T_8, ex_imm_sign) node _ex_imm_b11_T_10 = mux(_ex_imm_b11_T_3, _ex_imm_b11_T_5, _ex_imm_b11_T_9) node ex_imm_b11 = mux(_ex_imm_b11_T_2, asSInt(UInt<1>(0h0)), _ex_imm_b11_T_10) node _ex_imm_b10_5_T = eq(ex_ctrl.sel_imm, UInt<3>(0h2)) node _ex_imm_b10_5_T_1 = eq(ex_ctrl.sel_imm, UInt<3>(0h5)) node _ex_imm_b10_5_T_2 = or(_ex_imm_b10_5_T, _ex_imm_b10_5_T_1) node _ex_imm_b10_5_T_3 = bits(ex_reg_inst, 30, 25) node ex_imm_b10_5 = mux(_ex_imm_b10_5_T_2, UInt<1>(0h0), _ex_imm_b10_5_T_3) node _ex_imm_b4_1_T = eq(ex_ctrl.sel_imm, UInt<3>(0h2)) node _ex_imm_b4_1_T_1 = eq(ex_ctrl.sel_imm, UInt<3>(0h0)) node _ex_imm_b4_1_T_2 = eq(ex_ctrl.sel_imm, UInt<3>(0h1)) node _ex_imm_b4_1_T_3 = or(_ex_imm_b4_1_T_1, _ex_imm_b4_1_T_2) node _ex_imm_b4_1_T_4 = bits(ex_reg_inst, 11, 8) node _ex_imm_b4_1_T_5 = eq(ex_ctrl.sel_imm, UInt<3>(0h5)) node _ex_imm_b4_1_T_6 = bits(ex_reg_inst, 19, 16) node _ex_imm_b4_1_T_7 = bits(ex_reg_inst, 24, 21) node _ex_imm_b4_1_T_8 = mux(_ex_imm_b4_1_T_5, _ex_imm_b4_1_T_6, _ex_imm_b4_1_T_7) node _ex_imm_b4_1_T_9 = mux(_ex_imm_b4_1_T_3, _ex_imm_b4_1_T_4, _ex_imm_b4_1_T_8) node ex_imm_b4_1 = mux(_ex_imm_b4_1_T, UInt<1>(0h0), _ex_imm_b4_1_T_9) node _ex_imm_b0_T = eq(ex_ctrl.sel_imm, UInt<3>(0h0)) node _ex_imm_b0_T_1 = bits(ex_reg_inst, 7, 7) node _ex_imm_b0_T_2 = eq(ex_ctrl.sel_imm, UInt<3>(0h4)) node _ex_imm_b0_T_3 = bits(ex_reg_inst, 20, 20) node _ex_imm_b0_T_4 = eq(ex_ctrl.sel_imm, UInt<3>(0h5)) node _ex_imm_b0_T_5 = bits(ex_reg_inst, 15, 15) node _ex_imm_b0_T_6 = mux(_ex_imm_b0_T_4, _ex_imm_b0_T_5, UInt<1>(0h0)) node _ex_imm_b0_T_7 = mux(_ex_imm_b0_T_2, _ex_imm_b0_T_3, _ex_imm_b0_T_6) node ex_imm_b0 = mux(_ex_imm_b0_T, _ex_imm_b0_T_1, _ex_imm_b0_T_7) node ex_imm_lo_hi = cat(ex_imm_b10_5, ex_imm_b4_1) node ex_imm_lo = cat(ex_imm_lo_hi, ex_imm_b0) node ex_imm_hi_lo_lo = asUInt(ex_imm_b11) node ex_imm_hi_lo_hi = asUInt(ex_imm_b19_12) node ex_imm_hi_lo = cat(ex_imm_hi_lo_hi, ex_imm_hi_lo_lo) node ex_imm_hi_hi_lo = asUInt(ex_imm_b30_20) node ex_imm_hi_hi_hi = asUInt(ex_imm_sign) node ex_imm_hi_hi = cat(ex_imm_hi_hi_hi, ex_imm_hi_hi_lo) node ex_imm_hi = cat(ex_imm_hi_hi, ex_imm_hi_lo) node _ex_imm_T = cat(ex_imm_hi, ex_imm_lo) node ex_imm = asSInt(_ex_imm_T) node _ex_rs1shl_T = bits(ex_reg_inst, 3, 3) node _ex_rs1shl_T_1 = bits(ex_rs_0, 31, 0) node _ex_rs1shl_T_2 = mux(_ex_rs1shl_T, _ex_rs1shl_T_1, ex_rs_0) node _ex_rs1shl_T_3 = bits(ex_reg_inst, 14, 13) node ex_rs1shl = dshl(_ex_rs1shl_T_2, _ex_rs1shl_T_3) node _ex_op1_T = asSInt(ex_rs_0) node _ex_op1_T_1 = asSInt(ex_reg_pc) node _ex_op1_T_2 = asSInt(ex_rs1shl) node _ex_op1_T_3 = eq(UInt<2>(0h1), ex_ctrl.sel_alu1) node _ex_op1_T_4 = mux(_ex_op1_T_3, _ex_op1_T, asSInt(UInt<1>(0h0))) node _ex_op1_T_5 = eq(UInt<2>(0h2), ex_ctrl.sel_alu1) node _ex_op1_T_6 = mux(_ex_op1_T_5, _ex_op1_T_1, _ex_op1_T_4) node _ex_op1_T_7 = eq(UInt<2>(0h3), ex_ctrl.sel_alu1) node ex_op1 = mux(_ex_op1_T_7, _ex_op1_T_2, _ex_op1_T_6) node _ex_op2_oh_T = bits(ex_ctrl.sel_alu2, 0, 0) node _ex_op2_oh_T_1 = shr(ex_reg_inst, 20) node _ex_op2_oh_T_2 = mux(_ex_op2_oh_T, _ex_op2_oh_T_1, ex_rs_1) node _ex_op2_oh_T_3 = bits(_ex_op2_oh_T_2, 5, 0) node _ex_op2_oh_T_4 = dshl(UInt<1>(0h1), _ex_op2_oh_T_3) node ex_op2_oh = asSInt(_ex_op2_oh_T_4) node _ex_op2_T = asSInt(ex_rs_1) node _ex_op2_T_1 = mux(ex_reg_rvc, asSInt(UInt<3>(0h2)), asSInt(UInt<4>(0h4))) node _ex_op2_T_2 = eq(UInt<3>(0h2), ex_ctrl.sel_alu2) node _ex_op2_T_3 = mux(_ex_op2_T_2, _ex_op2_T, asSInt(UInt<1>(0h0))) node _ex_op2_T_4 = eq(UInt<3>(0h3), ex_ctrl.sel_alu2) node _ex_op2_T_5 = mux(_ex_op2_T_4, ex_imm, _ex_op2_T_3) node _ex_op2_T_6 = eq(UInt<3>(0h1), ex_ctrl.sel_alu2) node _ex_op2_T_7 = mux(_ex_op2_T_6, _ex_op2_T_1, _ex_op2_T_5) node _ex_op2_T_8 = eq(UInt<3>(0h4), ex_ctrl.sel_alu2) node _ex_op2_T_9 = mux(_ex_op2_T_8, ex_op2_oh, _ex_op2_T_7) node _ex_op2_T_10 = eq(UInt<3>(0h5), ex_ctrl.sel_alu2) node ex_op2 = mux(_ex_op2_T_10, ex_op2_oh, _ex_op2_T_9) inst alu of ALU_4 connect alu.clock, clock connect alu.reset, reset connect alu.io.dw, ex_ctrl.alu_dw connect alu.io.fn, ex_ctrl.alu_fn node _alu_io_in2_T = asUInt(ex_op2) connect alu.io.in2, _alu_io_in2_T node _alu_io_in1_T = asUInt(ex_op1) connect alu.io.in1, _alu_io_in1_T inst div of MulDiv_4 connect div.clock, clock connect div.reset, reset node _div_io_req_valid_T = and(ex_reg_valid, ex_ctrl.div) connect div.io.req.valid, _div_io_req_valid_T connect div.io.req.bits.dw, ex_ctrl.alu_dw connect div.io.req.bits.fn, ex_ctrl.alu_fn connect div.io.req.bits.in1, ex_rs_0 connect div.io.req.bits.in2, ex_rs_1 connect div.io.req.bits.tag, ex_waddr node _ex_reg_valid_T = eq(ctrl_killd, UInt<1>(0h0)) connect ex_reg_valid, _ex_reg_valid_T node _ex_reg_replay_T = eq(take_pc_mem_wb, UInt<1>(0h0)) node _ex_reg_replay_T_1 = and(_ex_reg_replay_T, ibuf.io.inst[0].valid) node _ex_reg_replay_T_2 = and(_ex_reg_replay_T_1, ibuf.io.inst[0].bits.replay) connect ex_reg_replay, _ex_reg_replay_T_2 node _ex_reg_xcpt_T = eq(ctrl_killd, UInt<1>(0h0)) node _ex_reg_xcpt_T_1 = and(_ex_reg_xcpt_T, id_xcpt) connect ex_reg_xcpt, _ex_reg_xcpt_T_1 node _ex_reg_xcpt_interrupt_T = eq(take_pc_mem_wb, UInt<1>(0h0)) node _ex_reg_xcpt_interrupt_T_1 = and(_ex_reg_xcpt_interrupt_T, ibuf.io.inst[0].valid) node _ex_reg_xcpt_interrupt_T_2 = and(_ex_reg_xcpt_interrupt_T_1, csr.io.interrupt) connect ex_reg_xcpt_interrupt, _ex_reg_xcpt_interrupt_T_2 node _T_31 = eq(ctrl_killd, UInt<1>(0h0)) when _T_31 : connect ex_ctrl, id_ctrl connect ex_reg_rvc, ibuf.io.inst[0].bits.rvc connect ex_ctrl.csr, id_csr node _T_32 = eq(id_fence_succ, UInt<1>(0h0)) node _T_33 = and(id_ctrl.fence, _T_32) when _T_33 : connect id_reg_pause, UInt<1>(0h1) when id_fence_next : connect id_reg_fence, UInt<1>(0h1) when id_xcpt : connect ex_ctrl.alu_fn, UInt<1>(0h0) connect ex_ctrl.alu_dw, UInt<1>(0h1) connect ex_ctrl.sel_alu1, UInt<2>(0h1) connect ex_ctrl.sel_alu2, UInt<3>(0h0) node hi = cat(ibuf.io.inst[0].bits.xcpt1.pf.inst, ibuf.io.inst[0].bits.xcpt1.gf.inst) node _T_34 = cat(hi, ibuf.io.inst[0].bits.xcpt1.ae.inst) node _T_35 = orr(_T_34) when _T_35 : connect ex_ctrl.sel_alu1, UInt<2>(0h2) connect ex_ctrl.sel_alu2, UInt<3>(0h1) connect ex_reg_rvc, UInt<1>(0h1) node hi_1 = cat(ibuf.io.inst[0].bits.xcpt0.pf.inst, ibuf.io.inst[0].bits.xcpt0.gf.inst) node _T_36 = cat(hi_1, ibuf.io.inst[0].bits.xcpt0.ae.inst) node _T_37 = orr(_T_36) node _T_38 = or(bpu.io.xcpt_if, _T_37) when _T_38 : connect ex_ctrl.sel_alu1, UInt<2>(0h2) connect ex_ctrl.sel_alu2, UInt<3>(0h0) node _ex_reg_flush_pipe_T = or(id_ctrl.fence_i, id_csr_flush) connect ex_reg_flush_pipe, _ex_reg_flush_pipe_T connect ex_reg_load_use, id_load_use node _ex_reg_hls_T = and(UInt<1>(0h0), id_system_insn) node _ex_reg_hls_T_1 = eq(id_ctrl.mem_cmd, UInt<1>(0h0)) node _ex_reg_hls_T_2 = eq(id_ctrl.mem_cmd, UInt<1>(0h1)) node _ex_reg_hls_T_3 = eq(id_ctrl.mem_cmd, UInt<5>(0h10)) node _ex_reg_hls_T_4 = or(_ex_reg_hls_T_1, _ex_reg_hls_T_2) node _ex_reg_hls_T_5 = or(_ex_reg_hls_T_4, _ex_reg_hls_T_3) node _ex_reg_hls_T_6 = and(_ex_reg_hls_T, _ex_reg_hls_T_5) connect ex_reg_hls, _ex_reg_hls_T_6 node _ex_reg_mem_size_T = and(UInt<1>(0h0), id_system_insn) node _ex_reg_mem_size_T_1 = bits(ibuf.io.inst[0].bits.inst.bits, 27, 26) node _ex_reg_mem_size_T_2 = bits(ibuf.io.inst[0].bits.inst.bits, 13, 12) node _ex_reg_mem_size_T_3 = mux(_ex_reg_mem_size_T, _ex_reg_mem_size_T_1, _ex_reg_mem_size_T_2) connect ex_reg_mem_size, _ex_reg_mem_size_T_3 node _T_39 = eq(id_ctrl.mem_cmd, UInt<5>(0h14)) node _T_40 = eq(id_ctrl.mem_cmd, UInt<5>(0h15)) node _T_41 = eq(id_ctrl.mem_cmd, UInt<5>(0h16)) node _T_42 = eq(id_ctrl.mem_cmd, UInt<3>(0h5)) node _T_43 = or(_T_39, _T_40) node _T_44 = or(_T_43, _T_41) node _T_45 = or(_T_44, _T_42) when _T_45 : node _ex_reg_mem_size_T_4 = neq(id_raddr2, UInt<1>(0h0)) node _ex_reg_mem_size_T_5 = neq(id_raddr1, UInt<1>(0h0)) node _ex_reg_mem_size_T_6 = cat(_ex_reg_mem_size_T_4, _ex_reg_mem_size_T_5) connect ex_reg_mem_size, _ex_reg_mem_size_T_6 node _T_46 = eq(id_ctrl.mem_cmd, UInt<5>(0h14)) node _T_47 = and(_T_46, csr.io.status.v) when _T_47 : connect ex_ctrl.mem_cmd, UInt<5>(0h15) node _do_bypass_T = or(id_bypass_src_0_0, id_bypass_src_0_1) node _do_bypass_T_1 = or(_do_bypass_T, id_bypass_src_0_2) node do_bypass = or(_do_bypass_T_1, id_bypass_src_0_3) node _bypass_src_T = mux(id_bypass_src_0_2, UInt<2>(0h2), UInt<2>(0h3)) node _bypass_src_T_1 = mux(id_bypass_src_0_1, UInt<1>(0h1), _bypass_src_T) node bypass_src = mux(id_bypass_src_0_0, UInt<1>(0h0), _bypass_src_T_1) connect ex_reg_rs_bypass[0], do_bypass connect ex_reg_rs_lsb[0], bypass_src node _T_48 = eq(do_bypass, UInt<1>(0h0)) node _T_49 = and(id_ctrl.rxs1, _T_48) when _T_49 : node _ex_reg_rs_lsb_0_T = bits(id_rs_0, 1, 0) connect ex_reg_rs_lsb[0], _ex_reg_rs_lsb_0_T node _ex_reg_rs_msb_0_T = shr(id_rs_0, 2) connect ex_reg_rs_msb[0], _ex_reg_rs_msb_0_T node _do_bypass_T_2 = or(id_bypass_src_1_0, id_bypass_src_1_1) node _do_bypass_T_3 = or(_do_bypass_T_2, id_bypass_src_1_2) node do_bypass_1 = or(_do_bypass_T_3, id_bypass_src_1_3) node _bypass_src_T_2 = mux(id_bypass_src_1_2, UInt<2>(0h2), UInt<2>(0h3)) node _bypass_src_T_3 = mux(id_bypass_src_1_1, UInt<1>(0h1), _bypass_src_T_2) node bypass_src_1 = mux(id_bypass_src_1_0, UInt<1>(0h0), _bypass_src_T_3) connect ex_reg_rs_bypass[1], do_bypass_1 connect ex_reg_rs_lsb[1], bypass_src_1 node _T_50 = eq(do_bypass_1, UInt<1>(0h0)) node _T_51 = and(id_ctrl.rxs2, _T_50) when _T_51 : node _ex_reg_rs_lsb_1_T = bits(id_rs_1, 1, 0) connect ex_reg_rs_lsb[1], _ex_reg_rs_lsb_1_T node _ex_reg_rs_msb_1_T = shr(id_rs_1, 2) connect ex_reg_rs_msb[1], _ex_reg_rs_msb_1_T node _T_52 = or(id_illegal_insn, id_virtual_insn) when _T_52 : node _inst_T = bits(ibuf.io.inst[0].bits.raw, 15, 0) node inst = mux(ibuf.io.inst[0].bits.rvc, _inst_T, ibuf.io.inst[0].bits.raw) connect ex_reg_rs_bypass[0], UInt<1>(0h0) node _ex_reg_rs_lsb_0_T_1 = bits(inst, 1, 0) connect ex_reg_rs_lsb[0], _ex_reg_rs_lsb_0_T_1 node _ex_reg_rs_msb_0_T_1 = shr(inst, 2) connect ex_reg_rs_msb[0], _ex_reg_rs_msb_0_T_1 node _T_53 = eq(ctrl_killd, UInt<1>(0h0)) node _T_54 = or(_T_53, csr.io.interrupt) node _T_55 = or(_T_54, ibuf.io.inst[0].bits.replay) when _T_55 : connect ex_reg_cause, id_cause connect ex_reg_inst, ibuf.io.inst[0].bits.inst.bits connect ex_reg_raw_inst, ibuf.io.inst[0].bits.raw connect ex_reg_pc, ibuf.io.pc connect ex_reg_btb_resp, ibuf.io.btb_resp connect ex_reg_wphit[0], bpu.io.bpwatch[0].ivalid[0] node _ex_reg_set_vconfig_T = eq(id_xcpt, UInt<1>(0h0)) node _ex_reg_set_vconfig_T_1 = and(id_set_vconfig, _ex_reg_set_vconfig_T) connect ex_reg_set_vconfig, _ex_reg_set_vconfig_T_1 node _ex_pc_valid_T = or(ex_reg_valid, ex_reg_replay) node ex_pc_valid = or(_ex_pc_valid_T, ex_reg_xcpt_interrupt) node _wb_dcache_miss_T = eq(io.dmem.resp.valid, UInt<1>(0h0)) node wb_dcache_miss = and(wb_ctrl.mem, _wb_dcache_miss_T) node _replay_ex_structural_T = eq(io.dmem.req.ready, UInt<1>(0h0)) node _replay_ex_structural_T_1 = and(ex_ctrl.mem, _replay_ex_structural_T) node _replay_ex_structural_T_2 = eq(div.io.req.ready, UInt<1>(0h0)) node _replay_ex_structural_T_3 = and(ex_ctrl.div, _replay_ex_structural_T_2) node _replay_ex_structural_T_4 = or(_replay_ex_structural_T_1, _replay_ex_structural_T_3) node _replay_ex_structural_T_5 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _replay_ex_structural_T_6 = and(ex_ctrl.vec, _replay_ex_structural_T_5) node replay_ex_structural = or(_replay_ex_structural_T_4, _replay_ex_structural_T_6) node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) node _replay_ex_T = or(replay_ex_structural, replay_ex_load_use) node _replay_ex_T_1 = and(ex_reg_valid, _replay_ex_T) node replay_ex = or(ex_reg_replay, _replay_ex_T_1) node _ctrl_killx_T = or(take_pc_mem_wb, replay_ex) node _ctrl_killx_T_1 = eq(ex_reg_valid, UInt<1>(0h0)) node ctrl_killx = or(_ctrl_killx_T, _ctrl_killx_T_1) node _ex_slow_bypass_T = eq(ex_ctrl.mem_cmd, UInt<3>(0h7)) node _ex_slow_bypass_T_1 = lt(ex_reg_mem_size, UInt<2>(0h2)) node ex_slow_bypass = or(_ex_slow_bypass_T, _ex_slow_bypass_T_1) node _ex_sfence_T = and(UInt<1>(0h1), ex_ctrl.mem) node _ex_sfence_T_1 = eq(ex_ctrl.mem_cmd, UInt<5>(0h14)) node _ex_sfence_T_2 = eq(ex_ctrl.mem_cmd, UInt<5>(0h15)) node _ex_sfence_T_3 = or(_ex_sfence_T_1, _ex_sfence_T_2) node _ex_sfence_T_4 = eq(ex_ctrl.mem_cmd, UInt<5>(0h16)) node _ex_sfence_T_5 = or(_ex_sfence_T_3, _ex_sfence_T_4) node ex_sfence = and(_ex_sfence_T, _ex_sfence_T_5) node _T_56 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) wire ex_xcpt : UInt<1> connect ex_xcpt, _T_56 wire ex_cause : UInt connect ex_cause, ex_reg_cause node _T_57 = eq(ex_cause, UInt<4>(0he)) node _T_58 = and(ex_xcpt, _T_57) node _T_59 = eq(ex_cause, UInt<2>(0h3)) node _T_60 = and(ex_xcpt, _T_59) node _T_61 = eq(ex_cause, UInt<1>(0h1)) node _T_62 = and(ex_xcpt, _T_61) node _T_63 = eq(ex_cause, UInt<2>(0h2)) node _T_64 = and(ex_xcpt, _T_63) node _T_65 = eq(ex_cause, UInt<4>(0hc)) node _T_66 = and(ex_xcpt, _T_65) node _mem_pc_valid_T = or(mem_reg_valid, mem_reg_replay) node mem_pc_valid = or(_mem_pc_valid_T, mem_reg_xcpt_interrupt) node _mem_br_target_T = asSInt(mem_reg_pc) node _mem_br_target_T_1 = and(mem_ctrl.branch, mem_br_taken) node _mem_br_target_sign_T = eq(UInt<3>(0h1), UInt<3>(0h5)) node _mem_br_target_sign_T_1 = bits(mem_reg_inst, 31, 31) node _mem_br_target_sign_T_2 = asSInt(_mem_br_target_sign_T_1) node mem_br_target_sign = mux(_mem_br_target_sign_T, asSInt(UInt<1>(0h0)), _mem_br_target_sign_T_2) node _mem_br_target_b30_20_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _mem_br_target_b30_20_T_1 = bits(mem_reg_inst, 30, 20) node _mem_br_target_b30_20_T_2 = asSInt(_mem_br_target_b30_20_T_1) node mem_br_target_b30_20 = mux(_mem_br_target_b30_20_T, _mem_br_target_b30_20_T_2, mem_br_target_sign) node _mem_br_target_b19_12_T = neq(UInt<3>(0h1), UInt<3>(0h2)) node _mem_br_target_b19_12_T_1 = neq(UInt<3>(0h1), UInt<3>(0h3)) node _mem_br_target_b19_12_T_2 = and(_mem_br_target_b19_12_T, _mem_br_target_b19_12_T_1) node _mem_br_target_b19_12_T_3 = bits(mem_reg_inst, 19, 12) node _mem_br_target_b19_12_T_4 = asSInt(_mem_br_target_b19_12_T_3) node mem_br_target_b19_12 = mux(_mem_br_target_b19_12_T_2, mem_br_target_sign, _mem_br_target_b19_12_T_4) node _mem_br_target_b11_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _mem_br_target_b11_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _mem_br_target_b11_T_2 = or(_mem_br_target_b11_T, _mem_br_target_b11_T_1) node _mem_br_target_b11_T_3 = eq(UInt<3>(0h1), UInt<3>(0h3)) node _mem_br_target_b11_T_4 = bits(mem_reg_inst, 20, 20) node _mem_br_target_b11_T_5 = asSInt(_mem_br_target_b11_T_4) node _mem_br_target_b11_T_6 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _mem_br_target_b11_T_7 = bits(mem_reg_inst, 7, 7) node _mem_br_target_b11_T_8 = asSInt(_mem_br_target_b11_T_7) node _mem_br_target_b11_T_9 = mux(_mem_br_target_b11_T_6, _mem_br_target_b11_T_8, mem_br_target_sign) node _mem_br_target_b11_T_10 = mux(_mem_br_target_b11_T_3, _mem_br_target_b11_T_5, _mem_br_target_b11_T_9) node mem_br_target_b11 = mux(_mem_br_target_b11_T_2, asSInt(UInt<1>(0h0)), _mem_br_target_b11_T_10) node _mem_br_target_b10_5_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _mem_br_target_b10_5_T_1 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _mem_br_target_b10_5_T_2 = or(_mem_br_target_b10_5_T, _mem_br_target_b10_5_T_1) node _mem_br_target_b10_5_T_3 = bits(mem_reg_inst, 30, 25) node mem_br_target_b10_5 = mux(_mem_br_target_b10_5_T_2, UInt<1>(0h0), _mem_br_target_b10_5_T_3) node _mem_br_target_b4_1_T = eq(UInt<3>(0h1), UInt<3>(0h2)) node _mem_br_target_b4_1_T_1 = eq(UInt<3>(0h1), UInt<3>(0h0)) node _mem_br_target_b4_1_T_2 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _mem_br_target_b4_1_T_3 = or(_mem_br_target_b4_1_T_1, _mem_br_target_b4_1_T_2) node _mem_br_target_b4_1_T_4 = bits(mem_reg_inst, 11, 8) node _mem_br_target_b4_1_T_5 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _mem_br_target_b4_1_T_6 = bits(mem_reg_inst, 19, 16) node _mem_br_target_b4_1_T_7 = bits(mem_reg_inst, 24, 21) node _mem_br_target_b4_1_T_8 = mux(_mem_br_target_b4_1_T_5, _mem_br_target_b4_1_T_6, _mem_br_target_b4_1_T_7) node _mem_br_target_b4_1_T_9 = mux(_mem_br_target_b4_1_T_3, _mem_br_target_b4_1_T_4, _mem_br_target_b4_1_T_8) node mem_br_target_b4_1 = mux(_mem_br_target_b4_1_T, UInt<1>(0h0), _mem_br_target_b4_1_T_9) node _mem_br_target_b0_T = eq(UInt<3>(0h1), UInt<3>(0h0)) node _mem_br_target_b0_T_1 = bits(mem_reg_inst, 7, 7) node _mem_br_target_b0_T_2 = eq(UInt<3>(0h1), UInt<3>(0h4)) node _mem_br_target_b0_T_3 = bits(mem_reg_inst, 20, 20) node _mem_br_target_b0_T_4 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _mem_br_target_b0_T_5 = bits(mem_reg_inst, 15, 15) node _mem_br_target_b0_T_6 = mux(_mem_br_target_b0_T_4, _mem_br_target_b0_T_5, UInt<1>(0h0)) node _mem_br_target_b0_T_7 = mux(_mem_br_target_b0_T_2, _mem_br_target_b0_T_3, _mem_br_target_b0_T_6) node mem_br_target_b0 = mux(_mem_br_target_b0_T, _mem_br_target_b0_T_1, _mem_br_target_b0_T_7) node mem_br_target_lo_hi = cat(mem_br_target_b10_5, mem_br_target_b4_1) node mem_br_target_lo = cat(mem_br_target_lo_hi, mem_br_target_b0) node mem_br_target_hi_lo_lo = asUInt(mem_br_target_b11) node mem_br_target_hi_lo_hi = asUInt(mem_br_target_b19_12) node mem_br_target_hi_lo = cat(mem_br_target_hi_lo_hi, mem_br_target_hi_lo_lo) node mem_br_target_hi_hi_lo = asUInt(mem_br_target_b30_20) node mem_br_target_hi_hi_hi = asUInt(mem_br_target_sign) node mem_br_target_hi_hi = cat(mem_br_target_hi_hi_hi, mem_br_target_hi_hi_lo) node mem_br_target_hi = cat(mem_br_target_hi_hi, mem_br_target_hi_lo) node _mem_br_target_T_2 = cat(mem_br_target_hi, mem_br_target_lo) node _mem_br_target_T_3 = asSInt(_mem_br_target_T_2) node _mem_br_target_sign_T_3 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _mem_br_target_sign_T_4 = bits(mem_reg_inst, 31, 31) node _mem_br_target_sign_T_5 = asSInt(_mem_br_target_sign_T_4) node mem_br_target_sign_1 = mux(_mem_br_target_sign_T_3, asSInt(UInt<1>(0h0)), _mem_br_target_sign_T_5) node _mem_br_target_b30_20_T_3 = eq(UInt<3>(0h3), UInt<3>(0h2)) node _mem_br_target_b30_20_T_4 = bits(mem_reg_inst, 30, 20) node _mem_br_target_b30_20_T_5 = asSInt(_mem_br_target_b30_20_T_4) node mem_br_target_b30_20_1 = mux(_mem_br_target_b30_20_T_3, _mem_br_target_b30_20_T_5, mem_br_target_sign_1) node _mem_br_target_b19_12_T_5 = neq(UInt<3>(0h3), UInt<3>(0h2)) node _mem_br_target_b19_12_T_6 = neq(UInt<3>(0h3), UInt<3>(0h3)) node _mem_br_target_b19_12_T_7 = and(_mem_br_target_b19_12_T_5, _mem_br_target_b19_12_T_6) node _mem_br_target_b19_12_T_8 = bits(mem_reg_inst, 19, 12) node _mem_br_target_b19_12_T_9 = asSInt(_mem_br_target_b19_12_T_8) node mem_br_target_b19_12_1 = mux(_mem_br_target_b19_12_T_7, mem_br_target_sign_1, _mem_br_target_b19_12_T_9) node _mem_br_target_b11_T_11 = eq(UInt<3>(0h3), UInt<3>(0h2)) node _mem_br_target_b11_T_12 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _mem_br_target_b11_T_13 = or(_mem_br_target_b11_T_11, _mem_br_target_b11_T_12) node _mem_br_target_b11_T_14 = eq(UInt<3>(0h3), UInt<3>(0h3)) node _mem_br_target_b11_T_15 = bits(mem_reg_inst, 20, 20) node _mem_br_target_b11_T_16 = asSInt(_mem_br_target_b11_T_15) node _mem_br_target_b11_T_17 = eq(UInt<3>(0h3), UInt<3>(0h1)) node _mem_br_target_b11_T_18 = bits(mem_reg_inst, 7, 7) node _mem_br_target_b11_T_19 = asSInt(_mem_br_target_b11_T_18) node _mem_br_target_b11_T_20 = mux(_mem_br_target_b11_T_17, _mem_br_target_b11_T_19, mem_br_target_sign_1) node _mem_br_target_b11_T_21 = mux(_mem_br_target_b11_T_14, _mem_br_target_b11_T_16, _mem_br_target_b11_T_20) node mem_br_target_b11_1 = mux(_mem_br_target_b11_T_13, asSInt(UInt<1>(0h0)), _mem_br_target_b11_T_21) node _mem_br_target_b10_5_T_4 = eq(UInt<3>(0h3), UInt<3>(0h2)) node _mem_br_target_b10_5_T_5 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _mem_br_target_b10_5_T_6 = or(_mem_br_target_b10_5_T_4, _mem_br_target_b10_5_T_5) node _mem_br_target_b10_5_T_7 = bits(mem_reg_inst, 30, 25) node mem_br_target_b10_5_1 = mux(_mem_br_target_b10_5_T_6, UInt<1>(0h0), _mem_br_target_b10_5_T_7) node _mem_br_target_b4_1_T_10 = eq(UInt<3>(0h3), UInt<3>(0h2)) node _mem_br_target_b4_1_T_11 = eq(UInt<3>(0h3), UInt<3>(0h0)) node _mem_br_target_b4_1_T_12 = eq(UInt<3>(0h3), UInt<3>(0h1)) node _mem_br_target_b4_1_T_13 = or(_mem_br_target_b4_1_T_11, _mem_br_target_b4_1_T_12) node _mem_br_target_b4_1_T_14 = bits(mem_reg_inst, 11, 8) node _mem_br_target_b4_1_T_15 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _mem_br_target_b4_1_T_16 = bits(mem_reg_inst, 19, 16) node _mem_br_target_b4_1_T_17 = bits(mem_reg_inst, 24, 21) node _mem_br_target_b4_1_T_18 = mux(_mem_br_target_b4_1_T_15, _mem_br_target_b4_1_T_16, _mem_br_target_b4_1_T_17) node _mem_br_target_b4_1_T_19 = mux(_mem_br_target_b4_1_T_13, _mem_br_target_b4_1_T_14, _mem_br_target_b4_1_T_18) node mem_br_target_b4_1_1 = mux(_mem_br_target_b4_1_T_10, UInt<1>(0h0), _mem_br_target_b4_1_T_19) node _mem_br_target_b0_T_8 = eq(UInt<3>(0h3), UInt<3>(0h0)) node _mem_br_target_b0_T_9 = bits(mem_reg_inst, 7, 7) node _mem_br_target_b0_T_10 = eq(UInt<3>(0h3), UInt<3>(0h4)) node _mem_br_target_b0_T_11 = bits(mem_reg_inst, 20, 20) node _mem_br_target_b0_T_12 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _mem_br_target_b0_T_13 = bits(mem_reg_inst, 15, 15) node _mem_br_target_b0_T_14 = mux(_mem_br_target_b0_T_12, _mem_br_target_b0_T_13, UInt<1>(0h0)) node _mem_br_target_b0_T_15 = mux(_mem_br_target_b0_T_10, _mem_br_target_b0_T_11, _mem_br_target_b0_T_14) node mem_br_target_b0_1 = mux(_mem_br_target_b0_T_8, _mem_br_target_b0_T_9, _mem_br_target_b0_T_15) node mem_br_target_lo_hi_1 = cat(mem_br_target_b10_5_1, mem_br_target_b4_1_1) node mem_br_target_lo_1 = cat(mem_br_target_lo_hi_1, mem_br_target_b0_1) node mem_br_target_hi_lo_lo_1 = asUInt(mem_br_target_b11_1) node mem_br_target_hi_lo_hi_1 = asUInt(mem_br_target_b19_12_1) node mem_br_target_hi_lo_1 = cat(mem_br_target_hi_lo_hi_1, mem_br_target_hi_lo_lo_1) node mem_br_target_hi_hi_lo_1 = asUInt(mem_br_target_b30_20_1) node mem_br_target_hi_hi_hi_1 = asUInt(mem_br_target_sign_1) node mem_br_target_hi_hi_1 = cat(mem_br_target_hi_hi_hi_1, mem_br_target_hi_hi_lo_1) node mem_br_target_hi_1 = cat(mem_br_target_hi_hi_1, mem_br_target_hi_lo_1) node _mem_br_target_T_4 = cat(mem_br_target_hi_1, mem_br_target_lo_1) node _mem_br_target_T_5 = asSInt(_mem_br_target_T_4) node _mem_br_target_T_6 = mux(mem_reg_rvc, asSInt(UInt<3>(0h2)), asSInt(UInt<4>(0h4))) node _mem_br_target_T_7 = mux(mem_ctrl.jal, _mem_br_target_T_5, _mem_br_target_T_6) node _mem_br_target_T_8 = mux(_mem_br_target_T_1, _mem_br_target_T_3, _mem_br_target_T_7) node _mem_br_target_T_9 = add(_mem_br_target_T, _mem_br_target_T_8) node _mem_br_target_T_10 = tail(_mem_br_target_T_9, 1) node mem_br_target = asSInt(_mem_br_target_T_10) node _mem_npc_T = or(mem_ctrl.jalr, mem_reg_sfence) node _mem_npc_a_T = shr(mem_reg_wdata, 39) node mem_npc_a = asSInt(_mem_npc_a_T) node _mem_npc_msb_T = eq(mem_npc_a, asSInt(UInt<1>(0h0))) node _mem_npc_msb_T_1 = eq(mem_npc_a, asSInt(UInt<1>(0h1))) node _mem_npc_msb_T_2 = or(_mem_npc_msb_T, _mem_npc_msb_T_1) node _mem_npc_msb_T_3 = bits(mem_reg_wdata, 39, 39) node _mem_npc_msb_T_4 = bits(mem_reg_wdata, 38, 38) node _mem_npc_msb_T_5 = eq(_mem_npc_msb_T_4, UInt<1>(0h0)) node mem_npc_msb = mux(_mem_npc_msb_T_2, _mem_npc_msb_T_3, _mem_npc_msb_T_5) node _mem_npc_T_1 = bits(mem_reg_wdata, 38, 0) node _mem_npc_T_2 = cat(mem_npc_msb, _mem_npc_T_1) node _mem_npc_T_3 = asSInt(_mem_npc_T_2) node _mem_npc_T_4 = mux(_mem_npc_T, _mem_npc_T_3, mem_br_target) node _mem_npc_T_5 = and(_mem_npc_T_4, asSInt(UInt<2>(0h2))) node _mem_npc_T_6 = asSInt(_mem_npc_T_5) node mem_npc = asUInt(_mem_npc_T_6) node _mem_wrong_npc_T = neq(mem_npc, ex_reg_pc) node _mem_wrong_npc_T_1 = or(ibuf.io.inst[0].valid, ibuf.io.imem.valid) node _mem_wrong_npc_T_2 = neq(mem_npc, ibuf.io.pc) node _mem_wrong_npc_T_3 = mux(_mem_wrong_npc_T_1, _mem_wrong_npc_T_2, UInt<1>(0h1)) node mem_wrong_npc = mux(ex_pc_valid, _mem_wrong_npc_T, _mem_wrong_npc_T_3) node _mem_npc_misaligned_T = bits(csr.io.status.isa, 2, 2) node _mem_npc_misaligned_T_1 = eq(_mem_npc_misaligned_T, UInt<1>(0h0)) node _mem_npc_misaligned_T_2 = bits(mem_npc, 1, 1) node _mem_npc_misaligned_T_3 = and(_mem_npc_misaligned_T_1, _mem_npc_misaligned_T_2) node _mem_npc_misaligned_T_4 = eq(mem_reg_sfence, UInt<1>(0h0)) node mem_npc_misaligned = and(_mem_npc_misaligned_T_3, _mem_npc_misaligned_T_4) node _mem_int_wdata_T = eq(mem_reg_xcpt, UInt<1>(0h0)) node _mem_int_wdata_T_1 = xor(mem_ctrl.jalr, mem_npc_misaligned) node _mem_int_wdata_T_2 = and(_mem_int_wdata_T, _mem_int_wdata_T_1) node _mem_int_wdata_T_3 = asSInt(mem_reg_wdata) node _mem_int_wdata_T_4 = mux(_mem_int_wdata_T_2, mem_br_target, _mem_int_wdata_T_3) node mem_int_wdata = asUInt(_mem_int_wdata_T_4) node _mem_cfi_T = or(mem_ctrl.branch, mem_ctrl.jalr) node mem_cfi = or(_mem_cfi_T, mem_ctrl.jal) node _mem_cfi_taken_T = and(mem_ctrl.branch, mem_br_taken) node _mem_cfi_taken_T_1 = or(_mem_cfi_taken_T, mem_ctrl.jalr) node mem_cfi_taken = or(_mem_cfi_taken_T_1, mem_ctrl.jal) node _mem_direction_misprediction_T = and(UInt<1>(0h1), mem_reg_btb_resp.taken) node _mem_direction_misprediction_T_1 = neq(mem_br_taken, _mem_direction_misprediction_T) node mem_direction_misprediction = and(mem_ctrl.branch, _mem_direction_misprediction_T_1) node _take_pc_mem_T = eq(mem_reg_xcpt, UInt<1>(0h0)) node _take_pc_mem_T_1 = and(mem_reg_valid, _take_pc_mem_T) node _take_pc_mem_T_2 = or(mem_wrong_npc, mem_reg_sfence) node _take_pc_mem_T_3 = and(_take_pc_mem_T_1, _take_pc_mem_T_2) connect take_pc_mem, _take_pc_mem_T_3 node _mem_reg_valid_T = eq(ctrl_killx, UInt<1>(0h0)) connect mem_reg_valid, _mem_reg_valid_T node _mem_reg_replay_T = eq(take_pc_mem_wb, UInt<1>(0h0)) node _mem_reg_replay_T_1 = and(_mem_reg_replay_T, replay_ex) connect mem_reg_replay, _mem_reg_replay_T_1 node _mem_reg_xcpt_T = eq(ctrl_killx, UInt<1>(0h0)) node _mem_reg_xcpt_T_1 = and(_mem_reg_xcpt_T, ex_xcpt) connect mem_reg_xcpt, _mem_reg_xcpt_T_1 node _mem_reg_xcpt_interrupt_T = eq(take_pc_mem_wb, UInt<1>(0h0)) node _mem_reg_xcpt_interrupt_T_1 = and(_mem_reg_xcpt_interrupt_T, ex_reg_xcpt_interrupt) connect mem_reg_xcpt_interrupt, _mem_reg_xcpt_interrupt_T_1 node _T_67 = and(mem_reg_valid, mem_reg_flush_pipe) when _T_67 : connect mem_reg_sfence, UInt<1>(0h0) else : when ex_pc_valid : connect mem_ctrl, ex_ctrl connect mem_reg_rvc, ex_reg_rvc node _mem_reg_load_T = eq(ex_ctrl.mem_cmd, UInt<1>(0h0)) node _mem_reg_load_T_1 = eq(ex_ctrl.mem_cmd, UInt<5>(0h10)) node _mem_reg_load_T_2 = eq(ex_ctrl.mem_cmd, UInt<3>(0h6)) node _mem_reg_load_T_3 = eq(ex_ctrl.mem_cmd, UInt<3>(0h7)) node _mem_reg_load_T_4 = or(_mem_reg_load_T, _mem_reg_load_T_1) node _mem_reg_load_T_5 = or(_mem_reg_load_T_4, _mem_reg_load_T_2) node _mem_reg_load_T_6 = or(_mem_reg_load_T_5, _mem_reg_load_T_3) node _mem_reg_load_T_7 = eq(ex_ctrl.mem_cmd, UInt<3>(0h4)) node _mem_reg_load_T_8 = eq(ex_ctrl.mem_cmd, UInt<4>(0h9)) node _mem_reg_load_T_9 = eq(ex_ctrl.mem_cmd, UInt<4>(0ha)) node _mem_reg_load_T_10 = eq(ex_ctrl.mem_cmd, UInt<4>(0hb)) node _mem_reg_load_T_11 = or(_mem_reg_load_T_7, _mem_reg_load_T_8) node _mem_reg_load_T_12 = or(_mem_reg_load_T_11, _mem_reg_load_T_9) node _mem_reg_load_T_13 = or(_mem_reg_load_T_12, _mem_reg_load_T_10) node _mem_reg_load_T_14 = eq(ex_ctrl.mem_cmd, UInt<4>(0h8)) node _mem_reg_load_T_15 = eq(ex_ctrl.mem_cmd, UInt<4>(0hc)) node _mem_reg_load_T_16 = eq(ex_ctrl.mem_cmd, UInt<4>(0hd)) node _mem_reg_load_T_17 = eq(ex_ctrl.mem_cmd, UInt<4>(0he)) node _mem_reg_load_T_18 = eq(ex_ctrl.mem_cmd, UInt<4>(0hf)) node _mem_reg_load_T_19 = or(_mem_reg_load_T_14, _mem_reg_load_T_15) node _mem_reg_load_T_20 = or(_mem_reg_load_T_19, _mem_reg_load_T_16) node _mem_reg_load_T_21 = or(_mem_reg_load_T_20, _mem_reg_load_T_17) node _mem_reg_load_T_22 = or(_mem_reg_load_T_21, _mem_reg_load_T_18) node _mem_reg_load_T_23 = or(_mem_reg_load_T_13, _mem_reg_load_T_22) node _mem_reg_load_T_24 = or(_mem_reg_load_T_6, _mem_reg_load_T_23) node _mem_reg_load_T_25 = and(ex_ctrl.mem, _mem_reg_load_T_24) connect mem_reg_load, _mem_reg_load_T_25 node _mem_reg_store_T = eq(ex_ctrl.mem_cmd, UInt<1>(0h1)) node _mem_reg_store_T_1 = eq(ex_ctrl.mem_cmd, UInt<5>(0h11)) node _mem_reg_store_T_2 = or(_mem_reg_store_T, _mem_reg_store_T_1) node _mem_reg_store_T_3 = eq(ex_ctrl.mem_cmd, UInt<3>(0h7)) node _mem_reg_store_T_4 = or(_mem_reg_store_T_2, _mem_reg_store_T_3) node _mem_reg_store_T_5 = eq(ex_ctrl.mem_cmd, UInt<3>(0h4)) node _mem_reg_store_T_6 = eq(ex_ctrl.mem_cmd, UInt<4>(0h9)) node _mem_reg_store_T_7 = eq(ex_ctrl.mem_cmd, UInt<4>(0ha)) node _mem_reg_store_T_8 = eq(ex_ctrl.mem_cmd, UInt<4>(0hb)) node _mem_reg_store_T_9 = or(_mem_reg_store_T_5, _mem_reg_store_T_6) node _mem_reg_store_T_10 = or(_mem_reg_store_T_9, _mem_reg_store_T_7) node _mem_reg_store_T_11 = or(_mem_reg_store_T_10, _mem_reg_store_T_8) node _mem_reg_store_T_12 = eq(ex_ctrl.mem_cmd, UInt<4>(0h8)) node _mem_reg_store_T_13 = eq(ex_ctrl.mem_cmd, UInt<4>(0hc)) node _mem_reg_store_T_14 = eq(ex_ctrl.mem_cmd, UInt<4>(0hd)) node _mem_reg_store_T_15 = eq(ex_ctrl.mem_cmd, UInt<4>(0he)) node _mem_reg_store_T_16 = eq(ex_ctrl.mem_cmd, UInt<4>(0hf)) node _mem_reg_store_T_17 = or(_mem_reg_store_T_12, _mem_reg_store_T_13) node _mem_reg_store_T_18 = or(_mem_reg_store_T_17, _mem_reg_store_T_14) node _mem_reg_store_T_19 = or(_mem_reg_store_T_18, _mem_reg_store_T_15) node _mem_reg_store_T_20 = or(_mem_reg_store_T_19, _mem_reg_store_T_16) node _mem_reg_store_T_21 = or(_mem_reg_store_T_11, _mem_reg_store_T_20) node _mem_reg_store_T_22 = or(_mem_reg_store_T_4, _mem_reg_store_T_21) node _mem_reg_store_T_23 = and(ex_ctrl.mem, _mem_reg_store_T_22) connect mem_reg_store, _mem_reg_store_T_23 connect mem_reg_sfence, ex_sfence connect mem_reg_btb_resp, ex_reg_btb_resp connect mem_reg_flush_pipe, ex_reg_flush_pipe connect mem_reg_slow_bypass, ex_slow_bypass connect mem_reg_wphit, ex_reg_wphit connect mem_reg_set_vconfig, ex_reg_set_vconfig connect mem_reg_cause, ex_cause connect mem_reg_inst, ex_reg_inst connect mem_reg_raw_inst, ex_reg_raw_inst connect mem_reg_mem_size, ex_reg_mem_size connect mem_reg_hls_or_dv, io.dmem.req.bits.dv connect mem_reg_pc, ex_reg_pc node _mem_reg_wdata_T = mux(ex_reg_set_vconfig, alu.io.out, alu.io.out) connect mem_reg_wdata, _mem_reg_wdata_T connect mem_br_taken, alu.io.cmp_out node _T_68 = or(ex_ctrl.mem, ex_ctrl.rocc) node _T_69 = or(_T_68, ex_sfence) node _T_70 = and(ex_ctrl.rxs2, _T_69) when _T_70 : node size = mux(ex_ctrl.rocc, UInt<2>(0h3), ex_reg_mem_size) wire mem_reg_rs2_size : UInt<2> connect mem_reg_rs2_size, size node mem_reg_rs2_dat_padded = pad(ex_rs_1, 64) node _mem_reg_rs2_T = eq(mem_reg_rs2_size, UInt<1>(0h0)) node _mem_reg_rs2_T_1 = bits(mem_reg_rs2_dat_padded, 7, 0) node _mem_reg_rs2_T_2 = cat(_mem_reg_rs2_T_1, _mem_reg_rs2_T_1) node _mem_reg_rs2_T_3 = cat(_mem_reg_rs2_T_2, _mem_reg_rs2_T_2) node _mem_reg_rs2_T_4 = cat(_mem_reg_rs2_T_3, _mem_reg_rs2_T_3) node _mem_reg_rs2_T_5 = eq(mem_reg_rs2_size, UInt<1>(0h1)) node _mem_reg_rs2_T_6 = bits(mem_reg_rs2_dat_padded, 15, 0) node _mem_reg_rs2_T_7 = cat(_mem_reg_rs2_T_6, _mem_reg_rs2_T_6) node _mem_reg_rs2_T_8 = cat(_mem_reg_rs2_T_7, _mem_reg_rs2_T_7) node _mem_reg_rs2_T_9 = eq(mem_reg_rs2_size, UInt<2>(0h2)) node _mem_reg_rs2_T_10 = bits(mem_reg_rs2_dat_padded, 31, 0) node _mem_reg_rs2_T_11 = cat(_mem_reg_rs2_T_10, _mem_reg_rs2_T_10) node _mem_reg_rs2_T_12 = mux(_mem_reg_rs2_T_9, _mem_reg_rs2_T_11, mem_reg_rs2_dat_padded) node _mem_reg_rs2_T_13 = mux(_mem_reg_rs2_T_5, _mem_reg_rs2_T_8, _mem_reg_rs2_T_12) node _mem_reg_rs2_T_14 = mux(_mem_reg_rs2_T, _mem_reg_rs2_T_4, _mem_reg_rs2_T_13) connect mem_reg_rs2, _mem_reg_rs2_T_14 node _T_71 = and(ex_ctrl.jalr, csr.io.status.debug) when _T_71 : connect mem_ctrl.fence_i, UInt<1>(0h1) connect mem_reg_flush_pipe, UInt<1>(0h1) node _mem_breakpoint_T = and(mem_reg_load, bpu.io.xcpt_ld) node _mem_breakpoint_T_1 = and(mem_reg_store, bpu.io.xcpt_st) node mem_breakpoint = or(_mem_breakpoint_T, _mem_breakpoint_T_1) node _mem_debug_breakpoint_T = and(mem_reg_load, bpu.io.debug_ld) node _mem_debug_breakpoint_T_1 = and(mem_reg_store, bpu.io.debug_st) node mem_debug_breakpoint = or(_mem_debug_breakpoint_T, _mem_debug_breakpoint_T_1) node _T_72 = or(mem_debug_breakpoint, mem_breakpoint) wire mem_ldst_xcpt : UInt<1> connect mem_ldst_xcpt, _T_72 node _T_73 = mux(mem_debug_breakpoint, UInt<4>(0he), UInt<2>(0h3)) wire mem_ldst_cause : UInt connect mem_ldst_cause, _T_73 node _T_74 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) node _T_75 = and(mem_reg_valid, mem_npc_misaligned) node _T_76 = and(mem_reg_valid, mem_ldst_xcpt) node _T_77 = or(_T_74, _T_75) node _T_78 = or(_T_77, _T_76) wire mem_xcpt : UInt<1> connect mem_xcpt, _T_78 node _T_79 = mux(_T_75, UInt<1>(0h0), mem_ldst_cause) node _T_80 = mux(_T_74, mem_reg_cause, _T_79) wire mem_cause : UInt connect mem_cause, _T_80 node _T_81 = eq(mem_cause, UInt<4>(0he)) node _T_82 = and(mem_xcpt, _T_81) node _T_83 = eq(mem_cause, UInt<2>(0h3)) node _T_84 = and(mem_xcpt, _T_83) node _T_85 = eq(mem_cause, UInt<1>(0h1)) node _T_86 = and(mem_xcpt, _T_85) node _T_87 = eq(mem_cause, UInt<2>(0h2)) node _T_88 = and(mem_xcpt, _T_87) node _T_89 = eq(mem_cause, UInt<4>(0hc)) node _T_90 = and(mem_xcpt, _T_89) node _T_91 = eq(mem_cause, UInt<1>(0h0)) node _T_92 = and(mem_xcpt, _T_91) node _dcache_kill_mem_T = and(mem_reg_valid, mem_ctrl.wxd) node dcache_kill_mem = and(_dcache_kill_mem_T, io.dmem.replay_next) node _fpu_kill_mem_T = and(mem_reg_valid, mem_ctrl.fp) node fpu_kill_mem = and(_fpu_kill_mem_T, io.fpu.nack_mem) node _vec_kill_mem_T = and(mem_reg_valid, mem_ctrl.mem) node vec_kill_mem = and(_vec_kill_mem_T, UInt<1>(0h0)) node vec_kill_all = and(mem_reg_valid, UInt<1>(0h0)) node _replay_mem_T = or(dcache_kill_mem, mem_reg_replay) node _replay_mem_T_1 = or(_replay_mem_T, fpu_kill_mem) node _replay_mem_T_2 = or(_replay_mem_T_1, vec_kill_mem) node replay_mem = or(_replay_mem_T_2, vec_kill_all) node _killm_common_T = or(dcache_kill_mem, take_pc_wb) node _killm_common_T_1 = or(_killm_common_T, mem_reg_xcpt) node _killm_common_T_2 = eq(mem_reg_valid, UInt<1>(0h0)) node killm_common = or(_killm_common_T_1, _killm_common_T_2) node _div_io_kill_T = and(div.io.req.ready, div.io.req.valid) reg div_io_kill_REG : UInt<1>, clock connect div_io_kill_REG, _div_io_kill_T node _div_io_kill_T_1 = and(killm_common, div_io_kill_REG) connect div.io.kill, _div_io_kill_T_1 node _ctrl_killm_T = or(killm_common, mem_xcpt) node _ctrl_killm_T_1 = or(_ctrl_killm_T, fpu_kill_mem) node ctrl_killm = or(_ctrl_killm_T_1, vec_kill_mem) node _wb_reg_valid_T = eq(ctrl_killm, UInt<1>(0h0)) connect wb_reg_valid, _wb_reg_valid_T node _wb_reg_replay_T = eq(take_pc_wb, UInt<1>(0h0)) node _wb_reg_replay_T_1 = and(replay_mem, _wb_reg_replay_T) connect wb_reg_replay, _wb_reg_replay_T_1 node _wb_reg_xcpt_T = eq(take_pc_wb, UInt<1>(0h0)) node _wb_reg_xcpt_T_1 = and(mem_xcpt, _wb_reg_xcpt_T) node _wb_reg_xcpt_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _wb_reg_xcpt_T_3 = and(_wb_reg_xcpt_T_1, _wb_reg_xcpt_T_2) connect wb_reg_xcpt, _wb_reg_xcpt_T_3 node _wb_reg_flush_pipe_T = eq(ctrl_killm, UInt<1>(0h0)) node _wb_reg_flush_pipe_T_1 = and(_wb_reg_flush_pipe_T, mem_reg_flush_pipe) connect wb_reg_flush_pipe, _wb_reg_flush_pipe_T_1 when mem_pc_valid : connect wb_ctrl, mem_ctrl connect wb_reg_sfence, mem_reg_sfence node _wb_reg_wdata_T = eq(mem_reg_xcpt, UInt<1>(0h0)) node _wb_reg_wdata_T_1 = and(_wb_reg_wdata_T, mem_ctrl.fp) node _wb_reg_wdata_T_2 = and(_wb_reg_wdata_T_1, mem_ctrl.wxd) node _wb_reg_wdata_T_3 = mux(_wb_reg_wdata_T_2, io.fpu.toint_data, mem_int_wdata) connect wb_reg_wdata, _wb_reg_wdata_T_3 node _T_93 = or(mem_ctrl.rocc, mem_reg_sfence) node _T_94 = or(_T_93, mem_reg_set_vconfig) when _T_94 : connect wb_reg_rs2, mem_reg_rs2 connect wb_reg_cause, mem_cause connect wb_reg_inst, mem_reg_inst connect wb_reg_raw_inst, mem_reg_raw_inst connect wb_reg_mem_size, mem_reg_mem_size connect wb_reg_hls_or_dv, mem_reg_hls_or_dv node _wb_reg_hfence_v_T = eq(mem_ctrl.mem_cmd, UInt<5>(0h15)) connect wb_reg_hfence_v, _wb_reg_hfence_v_T node _wb_reg_hfence_g_T = eq(mem_ctrl.mem_cmd, UInt<5>(0h16)) connect wb_reg_hfence_g, _wb_reg_hfence_g_T connect wb_reg_pc, mem_reg_pc node _T_95 = and(bpu.io.bpwatch[0].rvalid[0], mem_reg_load) node _T_96 = and(bpu.io.bpwatch[0].wvalid[0], mem_reg_store) node _T_97 = or(_T_95, _T_96) node _T_98 = or(mem_reg_wphit[0], _T_97) connect wb_reg_wphit[0], _T_98 connect wb_reg_set_vconfig, mem_reg_set_vconfig node _T_99 = and(wb_reg_valid, wb_ctrl.mem) node _T_100 = and(_T_99, io.dmem.s2_xcpt.pf.st) node _T_101 = and(wb_reg_valid, wb_ctrl.mem) node _T_102 = and(_T_101, io.dmem.s2_xcpt.pf.ld) node _T_103 = and(wb_reg_valid, wb_ctrl.mem) node _T_104 = and(_T_103, io.dmem.s2_xcpt.gf.st) node _T_105 = and(wb_reg_valid, wb_ctrl.mem) node _T_106 = and(_T_105, io.dmem.s2_xcpt.gf.ld) node _T_107 = and(wb_reg_valid, wb_ctrl.mem) node _T_108 = and(_T_107, io.dmem.s2_xcpt.ae.st) node _T_109 = and(wb_reg_valid, wb_ctrl.mem) node _T_110 = and(_T_109, io.dmem.s2_xcpt.ae.ld) node _T_111 = and(wb_reg_valid, wb_ctrl.mem) node _T_112 = and(_T_111, io.dmem.s2_xcpt.ma.st) node _T_113 = and(wb_reg_valid, wb_ctrl.mem) node _T_114 = and(_T_113, io.dmem.s2_xcpt.ma.ld) node _T_115 = or(wb_reg_xcpt, _T_100) node _T_116 = or(_T_115, _T_102) node _T_117 = or(_T_116, _T_104) node _T_118 = or(_T_117, _T_106) node _T_119 = or(_T_118, _T_108) node _T_120 = or(_T_119, _T_110) node _T_121 = or(_T_120, _T_112) node _T_122 = or(_T_121, _T_114) wire wb_xcpt : UInt<1> connect wb_xcpt, _T_122 node _T_123 = mux(_T_112, UInt<3>(0h6), UInt<3>(0h4)) node _T_124 = mux(_T_110, UInt<3>(0h5), _T_123) node _T_125 = mux(_T_108, UInt<3>(0h7), _T_124) node _T_126 = mux(_T_106, UInt<5>(0h15), _T_125) node _T_127 = mux(_T_104, UInt<5>(0h17), _T_126) node _T_128 = mux(_T_102, UInt<4>(0hd), _T_127) node _T_129 = mux(_T_100, UInt<4>(0hf), _T_128) node _T_130 = mux(wb_reg_xcpt, wb_reg_cause, _T_129) wire wb_cause : UInt connect wb_cause, _T_130 node _T_131 = eq(wb_cause, UInt<3>(0h6)) node _T_132 = and(wb_xcpt, _T_131) node _T_133 = eq(wb_cause, UInt<3>(0h4)) node _T_134 = and(wb_xcpt, _T_133) node _T_135 = eq(wb_cause, UInt<3>(0h7)) node _T_136 = and(wb_xcpt, _T_135) node _T_137 = eq(wb_cause, UInt<3>(0h5)) node _T_138 = and(wb_xcpt, _T_137) node _T_139 = eq(wb_cause, UInt<4>(0hf)) node _T_140 = and(wb_xcpt, _T_139) node _T_141 = eq(wb_cause, UInt<4>(0hd)) node _T_142 = and(wb_xcpt, _T_141) node _wb_pc_valid_T = or(wb_reg_valid, wb_reg_replay) node wb_pc_valid = or(_wb_pc_valid_T, wb_reg_xcpt) node wb_wxd = and(wb_reg_valid, wb_ctrl.wxd) node _wb_set_sboard_T = or(wb_ctrl.div, wb_dcache_miss) node _wb_set_sboard_T_1 = or(_wb_set_sboard_T, wb_ctrl.rocc) node wb_set_sboard = or(_wb_set_sboard_T_1, wb_ctrl.vec) node replay_wb_common = or(io.dmem.s2_nack, wb_reg_replay) node _replay_wb_rocc_T = and(wb_reg_valid, wb_ctrl.rocc) node _replay_wb_rocc_T_1 = eq(io.rocc.cmd.ready, UInt<1>(0h0)) node replay_wb_rocc = and(_replay_wb_rocc_T, _replay_wb_rocc_T_1) node replay_wb_csr = and(wb_reg_valid, csr.io.rw_stall) node replay_wb_vec = and(wb_reg_valid, UInt<1>(0h0)) node _replay_wb_T = or(replay_wb_common, replay_wb_rocc) node _replay_wb_T_1 = or(_replay_wb_T, replay_wb_csr) node replay_wb = or(_replay_wb_T_1, replay_wb_vec) node _take_pc_wb_T = or(replay_wb, wb_xcpt) node _take_pc_wb_T_1 = or(_take_pc_wb_T, csr.io.eret) node _take_pc_wb_T_2 = or(_take_pc_wb_T_1, wb_reg_flush_pipe) connect take_pc_wb, _take_pc_wb_T_2 node _dmem_resp_xpu_T = bits(io.dmem.resp.bits.tag, 0, 0) node dmem_resp_xpu = eq(_dmem_resp_xpu_T, UInt<1>(0h0)) node dmem_resp_fpu = bits(io.dmem.resp.bits.tag, 0, 0) node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1) node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) node dmem_resp_replay = and(dmem_resp_valid, io.dmem.resp.bits.replay) inst ll_arb of Arbiter3_LLWB_4 connect ll_arb.clock, clock connect ll_arb.reset, reset connect ll_arb.io.in[0].valid, UInt<1>(0h0) connect ll_arb.io.in[1].valid, UInt<1>(0h0) connect ll_arb.io.in[2].valid, UInt<1>(0h0) invalidate ll_arb.io.in[0].bits.tag invalidate ll_arb.io.in[0].bits.data invalidate ll_arb.io.in[1].bits.tag invalidate ll_arb.io.in[1].bits.data invalidate ll_arb.io.in[2].bits.tag invalidate ll_arb.io.in[2].bits.data wire ll_wdata : UInt connect ll_wdata, ll_arb.io.out.bits.data wire ll_waddr : UInt connect ll_waddr, ll_arb.io.out.bits.tag node _ll_wen_T = and(ll_arb.io.out.ready, ll_arb.io.out.valid) wire ll_wen : UInt<1> connect ll_wen, _ll_wen_T node _ll_arb_io_out_ready_T = eq(wb_wxd, UInt<1>(0h0)) connect ll_arb.io.out.ready, _ll_arb_io_out_ready_T connect div.io.resp.ready, ll_arb.io.in[0].ready connect ll_arb.io.in[0].valid, div.io.resp.valid connect ll_arb.io.in[0].bits.data, div.io.resp.bits.data connect ll_arb.io.in[0].bits.tag, div.io.resp.bits.tag connect io.rocc.resp.ready, UInt<1>(0h0) connect io.rocc.mem.req.ready, UInt<1>(0h0) invalidate io.rocc.mem.clock_enabled invalidate io.rocc.mem.keep_clock_enabled invalidate io.rocc.mem.perf.storeBufferEmptyAfterStore invalidate io.rocc.mem.perf.storeBufferEmptyAfterLoad invalidate io.rocc.mem.perf.canAcceptLoadThenLoad invalidate io.rocc.mem.perf.canAcceptStoreThenRMW invalidate io.rocc.mem.perf.canAcceptStoreThenLoad invalidate io.rocc.mem.perf.blocked invalidate io.rocc.mem.perf.tlbMiss invalidate io.rocc.mem.perf.grant invalidate io.rocc.mem.perf.release invalidate io.rocc.mem.perf.acquire invalidate io.rocc.mem.store_pending invalidate io.rocc.mem.ordered invalidate io.rocc.mem.s2_gpa_is_pte invalidate io.rocc.mem.s2_gpa invalidate io.rocc.mem.s2_xcpt.ae.st invalidate io.rocc.mem.s2_xcpt.ae.ld invalidate io.rocc.mem.s2_xcpt.gf.st invalidate io.rocc.mem.s2_xcpt.gf.ld invalidate io.rocc.mem.s2_xcpt.pf.st invalidate io.rocc.mem.s2_xcpt.pf.ld invalidate io.rocc.mem.s2_xcpt.ma.st invalidate io.rocc.mem.s2_xcpt.ma.ld invalidate io.rocc.mem.replay_next invalidate io.rocc.mem.resp.bits.store_data invalidate io.rocc.mem.resp.bits.data_raw invalidate io.rocc.mem.resp.bits.data_word_bypass invalidate io.rocc.mem.resp.bits.has_data invalidate io.rocc.mem.resp.bits.replay invalidate io.rocc.mem.resp.bits.mask invalidate io.rocc.mem.resp.bits.data invalidate io.rocc.mem.resp.bits.dv invalidate io.rocc.mem.resp.bits.dprv invalidate io.rocc.mem.resp.bits.signed invalidate io.rocc.mem.resp.bits.size invalidate io.rocc.mem.resp.bits.cmd invalidate io.rocc.mem.resp.bits.tag invalidate io.rocc.mem.resp.bits.addr invalidate io.rocc.mem.resp.valid invalidate io.rocc.mem.s2_paddr invalidate io.rocc.mem.s2_uncached invalidate io.rocc.mem.s2_kill invalidate io.rocc.mem.s2_nack_cause_raw invalidate io.rocc.mem.s2_nack invalidate io.rocc.mem.s1_data.mask invalidate io.rocc.mem.s1_data.data invalidate io.rocc.mem.s1_kill invalidate io.rocc.mem.req.bits.mask invalidate io.rocc.mem.req.bits.data invalidate io.rocc.mem.req.bits.no_xcpt invalidate io.rocc.mem.req.bits.no_alloc invalidate io.rocc.mem.req.bits.no_resp invalidate io.rocc.mem.req.bits.phys invalidate io.rocc.mem.req.bits.dv invalidate io.rocc.mem.req.bits.dprv invalidate io.rocc.mem.req.bits.signed invalidate io.rocc.mem.req.bits.size invalidate io.rocc.mem.req.bits.cmd invalidate io.rocc.mem.req.bits.tag invalidate io.rocc.mem.req.bits.addr invalidate io.rocc.mem.req.valid invalidate io.rocc.mem.req.ready node _T_143 = and(dmem_resp_replay, dmem_resp_xpu) when _T_143 : connect ll_arb.io.out.ready, UInt<1>(0h0) connect ll_waddr, dmem_resp_waddr connect ll_wen, UInt<1>(0h1) node _wb_valid_T = eq(replay_wb, UInt<1>(0h0)) node _wb_valid_T_1 = and(wb_reg_valid, _wb_valid_T) node _wb_valid_T_2 = eq(wb_xcpt, UInt<1>(0h0)) node wb_valid = and(_wb_valid_T_1, _wb_valid_T_2) node wb_wen = and(wb_valid, wb_ctrl.wxd) node rf_wen = or(wb_wen, ll_wen) node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) node _rf_wdata_T = and(dmem_resp_valid, dmem_resp_xpu) node _rf_wdata_T_1 = bits(io.dmem.resp.bits.data, 63, 0) node _rf_wdata_T_2 = neq(wb_ctrl.csr, UInt<3>(0h0)) node _rf_wdata_T_3 = mux(wb_ctrl.mul, wb_reg_wdata, wb_reg_wdata) node _rf_wdata_T_4 = mux(_rf_wdata_T_2, csr.io.rw.rdata, _rf_wdata_T_3) node _rf_wdata_T_5 = mux(ll_wen, ll_wdata, _rf_wdata_T_4) node rf_wdata = mux(_rf_wdata_T, _rf_wdata_T_1, _rf_wdata_T_5) when rf_wen : node _T_144 = neq(rf_waddr, UInt<1>(0h0)) when _T_144 : node _T_145 = bits(rf_waddr, 4, 0) node _T_146 = not(_T_145) infer mport MPORT = rf[_T_146], clock connect MPORT, rf_wdata node _T_147 = eq(rf_waddr, id_raddr1) when _T_147 : connect id_rs_0, rf_wdata node _T_148 = eq(rf_waddr, id_raddr2) when _T_148 : connect id_rs_1, rf_wdata connect csr.io.ungated_clock, clock connect csr.io.decode[0].inst, ibuf.io.inst[0].bits.inst.bits connect csr.io.exception, wb_xcpt connect csr.io.cause, wb_cause connect csr.io.retire, wb_valid node _csr_io_inst_0_T = bits(wb_reg_raw_inst, 1, 0) node _csr_io_inst_0_T_1 = andr(_csr_io_inst_0_T) node _csr_io_inst_0_T_2 = shr(wb_reg_inst, 16) node _csr_io_inst_0_T_3 = mux(_csr_io_inst_0_T_1, _csr_io_inst_0_T_2, UInt<1>(0h0)) node _csr_io_inst_0_T_4 = bits(wb_reg_raw_inst, 15, 0) node _csr_io_inst_0_T_5 = cat(_csr_io_inst_0_T_3, _csr_io_inst_0_T_4) connect csr.io.inst[0], _csr_io_inst_0_T_5 connect csr.io.interrupts.seip, io.interrupts.seip connect csr.io.interrupts.meip, io.interrupts.meip connect csr.io.interrupts.msip, io.interrupts.msip connect csr.io.interrupts.mtip, io.interrupts.mtip connect csr.io.interrupts.debug, io.interrupts.debug connect csr.io.hartid, io.hartid connect io.fpu.fcsr_rm, csr.io.fcsr_rm node _csr_io_fcsr_flags_valid_T = or(io.fpu.fcsr_flags.valid, UInt<1>(0h0)) connect csr.io.fcsr_flags.valid, _csr_io_fcsr_flags_valid_T node _csr_io_fcsr_flags_bits_T = mux(io.fpu.fcsr_flags.valid, UInt<5>(0h1f), UInt<5>(0h0)) node _csr_io_fcsr_flags_bits_T_1 = and(io.fpu.fcsr_flags.bits, _csr_io_fcsr_flags_bits_T) node _csr_io_fcsr_flags_bits_T_2 = mux(UInt<1>(0h0), UInt<5>(0h1f), UInt<5>(0h0)) node _csr_io_fcsr_flags_bits_T_3 = and(UInt<5>(0h0), _csr_io_fcsr_flags_bits_T_2) node _csr_io_fcsr_flags_bits_T_4 = or(_csr_io_fcsr_flags_bits_T_1, _csr_io_fcsr_flags_bits_T_3) connect csr.io.fcsr_flags.bits, _csr_io_fcsr_flags_bits_T_4 node _io_fpu_time_T = bits(csr.io.time, 31, 0) connect io.fpu.time, _io_fpu_time_T connect io.fpu.hartid, io.hartid connect csr.io.rocc_interrupt, io.rocc.interrupt connect csr.io.pc, wb_reg_pc node tval_dmem_addr = eq(wb_reg_xcpt, UInt<1>(0h0)) node _tval_any_addr_T = eq(wb_reg_cause, UInt<2>(0h3)) node _tval_any_addr_T_1 = eq(wb_reg_cause, UInt<1>(0h1)) node _tval_any_addr_T_2 = eq(wb_reg_cause, UInt<4>(0hc)) node _tval_any_addr_T_3 = eq(wb_reg_cause, UInt<5>(0h14)) node _tval_any_addr_T_4 = or(_tval_any_addr_T, _tval_any_addr_T_1) node _tval_any_addr_T_5 = or(_tval_any_addr_T_4, _tval_any_addr_T_2) node _tval_any_addr_T_6 = or(_tval_any_addr_T_5, _tval_any_addr_T_3) node tval_any_addr = or(tval_dmem_addr, _tval_any_addr_T_6) node tval_inst = eq(wb_reg_cause, UInt<2>(0h2)) node _tval_valid_T = or(tval_any_addr, tval_inst) node tval_valid = and(wb_xcpt, _tval_valid_T) node _csr_io_gva_T = and(tval_any_addr, csr.io.status.v) node _csr_io_gva_T_1 = and(tval_dmem_addr, wb_reg_hls_or_dv) node _csr_io_gva_T_2 = or(_csr_io_gva_T, _csr_io_gva_T_1) node _csr_io_gva_T_3 = and(wb_xcpt, _csr_io_gva_T_2) connect csr.io.gva, _csr_io_gva_T_3 node _csr_io_tval_a_T = shr(wb_reg_wdata, 39) node csr_io_tval_a = asSInt(_csr_io_tval_a_T) node _csr_io_tval_msb_T = eq(csr_io_tval_a, asSInt(UInt<1>(0h0))) node _csr_io_tval_msb_T_1 = eq(csr_io_tval_a, asSInt(UInt<1>(0h1))) node _csr_io_tval_msb_T_2 = or(_csr_io_tval_msb_T, _csr_io_tval_msb_T_1) node _csr_io_tval_msb_T_3 = bits(wb_reg_wdata, 39, 39) node _csr_io_tval_msb_T_4 = bits(wb_reg_wdata, 38, 38) node _csr_io_tval_msb_T_5 = eq(_csr_io_tval_msb_T_4, UInt<1>(0h0)) node csr_io_tval_msb = mux(_csr_io_tval_msb_T_2, _csr_io_tval_msb_T_3, _csr_io_tval_msb_T_5) node _csr_io_tval_T = bits(wb_reg_wdata, 38, 0) node _csr_io_tval_T_1 = cat(csr_io_tval_msb, _csr_io_tval_T) node _csr_io_tval_T_2 = mux(tval_valid, _csr_io_tval_T_1, UInt<1>(0h0)) connect csr.io.tval, _csr_io_tval_T_2 node _htval_valid_imem_T = eq(wb_reg_cause, UInt<5>(0h14)) node htval_valid_imem = and(wb_reg_xcpt, _htval_valid_imem_T) node htval_imem = mux(htval_valid_imem, io.imem.gpa.bits, UInt<1>(0h0)) node _T_149 = eq(htval_valid_imem, UInt<1>(0h0)) node _T_150 = or(_T_149, io.imem.gpa.valid) node _T_151 = asUInt(reset) node _T_152 = eq(_T_151, UInt<1>(0h0)) when _T_152 : node _T_153 = eq(_T_150, UInt<1>(0h0)) when _T_153 : printf(clock, UInt<1>(0h1), "Assertion failed\n at RocketCore.scala:855 assert(!htval_valid_imem \|\| io.imem.gpa.valid)\n") : printf assert(clock, _T_150, UInt<1>(0h1), "") : assert node _htval_valid_dmem_T = and(wb_xcpt, tval_dmem_addr) node _htval_valid_dmem_T_1 = cat(io.dmem.s2_xcpt.gf.ld, io.dmem.s2_xcpt.gf.st) node _htval_valid_dmem_T_2 = orr(_htval_valid_dmem_T_1) node _htval_valid_dmem_T_3 = and(_htval_valid_dmem_T, _htval_valid_dmem_T_2) node _htval_valid_dmem_T_4 = cat(io.dmem.s2_xcpt.pf.ld, io.dmem.s2_xcpt.pf.st) node _htval_valid_dmem_T_5 = orr(_htval_valid_dmem_T_4) node _htval_valid_dmem_T_6 = eq(_htval_valid_dmem_T_5, UInt<1>(0h0)) node htval_valid_dmem = and(_htval_valid_dmem_T_3, _htval_valid_dmem_T_6) node htval_dmem = mux(htval_valid_dmem, io.dmem.s2_gpa, UInt<1>(0h0)) node _htval_T = or(htval_dmem, htval_imem) node htval = shr(_htval_T, 0) node _mhtinst_read_pseudo_T = and(io.imem.gpa_is_pte, htval_valid_imem) node _mhtinst_read_pseudo_T_1 = and(io.dmem.s2_gpa_is_pte, htval_valid_dmem) node mhtinst_read_pseudo = or(_mhtinst_read_pseudo_T, _mhtinst_read_pseudo_T_1) connect csr.io.htval, htval connect csr.io.mhtinst_read_pseudo, mhtinst_read_pseudo connect io.ptw.ptbr, csr.io.ptbr connect io.ptw.hgatp, csr.io.hgatp connect io.ptw.vsatp, csr.io.vsatp connect csr.io.customCSRs[0].sdata, io.ptw.customCSRs.csrs[0].sdata connect csr.io.customCSRs[0].set, io.ptw.customCSRs.csrs[0].set connect csr.io.customCSRs[0].stall, io.ptw.customCSRs.csrs[0].stall connect io.ptw.customCSRs.csrs[0].value, csr.io.customCSRs[0].value connect io.ptw.customCSRs.csrs[0].wdata, csr.io.customCSRs[0].wdata connect io.ptw.customCSRs.csrs[0].wen, csr.io.customCSRs[0].wen connect io.ptw.customCSRs.csrs[0].ren, csr.io.customCSRs[0].ren connect csr.io.customCSRs[1].sdata, io.ptw.customCSRs.csrs[1].sdata connect csr.io.customCSRs[1].set, io.ptw.customCSRs.csrs[1].set connect csr.io.customCSRs[1].stall, io.ptw.customCSRs.csrs[1].stall connect io.ptw.customCSRs.csrs[1].value, csr.io.customCSRs[1].value connect io.ptw.customCSRs.csrs[1].wdata, csr.io.customCSRs[1].wdata connect io.ptw.customCSRs.csrs[1].wen, csr.io.customCSRs[1].wen connect io.ptw.customCSRs.csrs[1].ren, csr.io.customCSRs[1].ren connect csr.io.customCSRs[2].sdata, io.ptw.customCSRs.csrs[2].sdata connect csr.io.customCSRs[2].set, io.ptw.customCSRs.csrs[2].set connect csr.io.customCSRs[2].stall, io.ptw.customCSRs.csrs[2].stall connect io.ptw.customCSRs.csrs[2].value, csr.io.customCSRs[2].value connect io.ptw.customCSRs.csrs[2].wdata, csr.io.customCSRs[2].wdata connect io.ptw.customCSRs.csrs[2].wen, csr.io.customCSRs[2].wen connect io.ptw.customCSRs.csrs[2].ren, csr.io.customCSRs[2].ren connect csr.io.customCSRs[3].sdata, io.ptw.customCSRs.csrs[3].sdata connect csr.io.customCSRs[3].set, io.ptw.customCSRs.csrs[3].set connect csr.io.customCSRs[3].stall, io.ptw.customCSRs.csrs[3].stall connect io.ptw.customCSRs.csrs[3].value, csr.io.customCSRs[3].value connect io.ptw.customCSRs.csrs[3].wdata, csr.io.customCSRs[3].wdata connect io.ptw.customCSRs.csrs[3].wen, csr.io.customCSRs[3].wen connect io.ptw.customCSRs.csrs[3].ren, csr.io.customCSRs[3].ren connect io.ptw.status, csr.io.status connect io.ptw.hstatus, csr.io.hstatus connect io.ptw.gstatus, csr.io.gstatus connect io.ptw.pmp, csr.io.pmp node _csr_io_rw_addr_T = bits(wb_reg_inst, 31, 20) connect csr.io.rw.addr, _csr_io_rw_addr_T node _csr_io_rw_cmd_T = mux(wb_reg_valid, UInt<1>(0h0), UInt<3>(0h4)) node _csr_io_rw_cmd_T_1 = not(_csr_io_rw_cmd_T) node _csr_io_rw_cmd_T_2 = and(wb_ctrl.csr, _csr_io_rw_cmd_T_1) connect csr.io.rw.cmd, _csr_io_rw_cmd_T_2 connect csr.io.rw.wdata, wb_reg_wdata connect io.trace.time, csr.io.time connect io.trace.insns, csr.io.trace connect io.trace.insns, csr.io.trace connect io.bpwatch[0].valid[0], wb_reg_wphit[0] connect io.bpwatch[0].action, csr.io.bp[0].control.action connect io.bpwatch[0].rvalid[0], UInt<1>(0h0) connect io.bpwatch[0].wvalid[0], UInt<1>(0h0) connect io.bpwatch[0].ivalid[0], UInt<1>(0h0) node _hazard_targets_T = neq(id_raddr1, UInt<1>(0h0)) node hazard_targets_0_1 = and(id_ctrl.rxs1, _hazard_targets_T) node _hazard_targets_T_1 = neq(id_raddr2, UInt<1>(0h0)) node hazard_targets_1_1 = and(id_ctrl.rxs2, _hazard_targets_T_1) node _hazard_targets_T_2 = neq(id_waddr, UInt<1>(0h0)) node hazard_targets_2_1 = and(id_ctrl.wxd, _hazard_targets_T_2) regreset _r : UInt<32>, clock, reset, UInt<32>(0h0) node _r_T = shr(_r, 1) node r = shl(_r_T, 1) node _T_154 = dshl(UInt<1>(0h1), ll_waddr) node _T_155 = mux(ll_wen, _T_154, UInt<1>(0h0)) node _T_156 = not(_T_155) node _T_157 = and(r, _T_156) node _T_158 = or(UInt<1>(0h0), ll_wen) when _T_158 : connect _r, _T_157 node _id_sboard_hazard_T = dshr(r, id_raddr1) node _id_sboard_hazard_T_1 = bits(_id_sboard_hazard_T, 0, 0) node _id_sboard_hazard_T_2 = eq(ll_waddr, id_raddr1) node _id_sboard_hazard_T_3 = and(ll_wen, _id_sboard_hazard_T_2) node _id_sboard_hazard_T_4 = eq(_id_sboard_hazard_T_3, UInt<1>(0h0)) node _id_sboard_hazard_T_5 = and(_id_sboard_hazard_T_1, _id_sboard_hazard_T_4) node _id_sboard_hazard_T_6 = and(hazard_targets_0_1, _id_sboard_hazard_T_5) node _id_sboard_hazard_T_7 = dshr(r, id_raddr2) node _id_sboard_hazard_T_8 = bits(_id_sboard_hazard_T_7, 0, 0) node _id_sboard_hazard_T_9 = eq(ll_waddr, id_raddr2) node _id_sboard_hazard_T_10 = and(ll_wen, _id_sboard_hazard_T_9) node _id_sboard_hazard_T_11 = eq(_id_sboard_hazard_T_10, UInt<1>(0h0)) node _id_sboard_hazard_T_12 = and(_id_sboard_hazard_T_8, _id_sboard_hazard_T_11) node _id_sboard_hazard_T_13 = and(hazard_targets_1_1, _id_sboard_hazard_T_12) node _id_sboard_hazard_T_14 = dshr(r, id_waddr) node _id_sboard_hazard_T_15 = bits(_id_sboard_hazard_T_14, 0, 0) node _id_sboard_hazard_T_16 = eq(ll_waddr, id_waddr) node _id_sboard_hazard_T_17 = and(ll_wen, _id_sboard_hazard_T_16) node _id_sboard_hazard_T_18 = eq(_id_sboard_hazard_T_17, UInt<1>(0h0)) node _id_sboard_hazard_T_19 = and(_id_sboard_hazard_T_15, _id_sboard_hazard_T_18) node _id_sboard_hazard_T_20 = and(hazard_targets_2_1, _id_sboard_hazard_T_19) node _id_sboard_hazard_T_21 = or(_id_sboard_hazard_T_6, _id_sboard_hazard_T_13) node id_sboard_hazard = or(_id_sboard_hazard_T_21, _id_sboard_hazard_T_20) node _T_159 = and(wb_set_sboard, wb_wen) node _T_160 = dshl(UInt<1>(0h1), wb_waddr) node _T_161 = mux(_T_159, _T_160, UInt<1>(0h0)) node _T_162 = or(_T_157, _T_161) node _T_163 = or(_T_158, _T_159) when _T_163 : connect _r, _T_162 node _ex_cannot_bypass_T = neq(ex_ctrl.csr, UInt<3>(0h0)) node _ex_cannot_bypass_T_1 = or(_ex_cannot_bypass_T, ex_ctrl.jalr) node _ex_cannot_bypass_T_2 = or(_ex_cannot_bypass_T_1, ex_ctrl.mem) node _ex_cannot_bypass_T_3 = or(_ex_cannot_bypass_T_2, ex_ctrl.mul) node _ex_cannot_bypass_T_4 = or(_ex_cannot_bypass_T_3, ex_ctrl.div) node _ex_cannot_bypass_T_5 = or(_ex_cannot_bypass_T_4, ex_ctrl.fp) node _ex_cannot_bypass_T_6 = or(_ex_cannot_bypass_T_5, ex_ctrl.rocc) node ex_cannot_bypass = or(_ex_cannot_bypass_T_6, ex_ctrl.vec) node _data_hazard_ex_T = eq(id_raddr1, ex_waddr) node _data_hazard_ex_T_1 = and(hazard_targets_0_1, _data_hazard_ex_T) node _data_hazard_ex_T_2 = eq(id_raddr2, ex_waddr) node _data_hazard_ex_T_3 = and(hazard_targets_1_1, _data_hazard_ex_T_2) node _data_hazard_ex_T_4 = eq(id_waddr, ex_waddr) node _data_hazard_ex_T_5 = and(hazard_targets_2_1, _data_hazard_ex_T_4) node _data_hazard_ex_T_6 = or(_data_hazard_ex_T_1, _data_hazard_ex_T_3) node _data_hazard_ex_T_7 = or(_data_hazard_ex_T_6, _data_hazard_ex_T_5) node data_hazard_ex = and(ex_ctrl.wxd, _data_hazard_ex_T_7) node _fp_data_hazard_ex_T = and(id_ctrl.fp, ex_ctrl.wfd) node _fp_data_hazard_ex_T_1 = eq(id_raddr1, ex_waddr) node _fp_data_hazard_ex_T_2 = and(io.fpu.dec.ren1, _fp_data_hazard_ex_T_1) node _fp_data_hazard_ex_T_3 = eq(id_raddr2, ex_waddr) node _fp_data_hazard_ex_T_4 = and(io.fpu.dec.ren2, _fp_data_hazard_ex_T_3) node _fp_data_hazard_ex_T_5 = eq(id_raddr3, ex_waddr) node _fp_data_hazard_ex_T_6 = and(io.fpu.dec.ren3, _fp_data_hazard_ex_T_5) node _fp_data_hazard_ex_T_7 = eq(id_waddr, ex_waddr) node _fp_data_hazard_ex_T_8 = and(io.fpu.dec.wen, _fp_data_hazard_ex_T_7) node _fp_data_hazard_ex_T_9 = or(_fp_data_hazard_ex_T_2, _fp_data_hazard_ex_T_4) node _fp_data_hazard_ex_T_10 = or(_fp_data_hazard_ex_T_9, _fp_data_hazard_ex_T_6) node _fp_data_hazard_ex_T_11 = or(_fp_data_hazard_ex_T_10, _fp_data_hazard_ex_T_8) node fp_data_hazard_ex = and(_fp_data_hazard_ex_T, _fp_data_hazard_ex_T_11) node _id_ex_hazard_T = and(data_hazard_ex, ex_cannot_bypass) node _id_ex_hazard_T_1 = or(_id_ex_hazard_T, fp_data_hazard_ex) node id_ex_hazard = and(ex_reg_valid, _id_ex_hazard_T_1) node mem_mem_cmd_bh = and(UInt<1>(0h1), mem_reg_slow_bypass) node _mem_cannot_bypass_T = neq(mem_ctrl.csr, UInt<3>(0h0)) node _mem_cannot_bypass_T_1 = and(mem_ctrl.mem, mem_mem_cmd_bh) node _mem_cannot_bypass_T_2 = or(_mem_cannot_bypass_T, _mem_cannot_bypass_T_1) node _mem_cannot_bypass_T_3 = or(_mem_cannot_bypass_T_2, mem_ctrl.mul) node _mem_cannot_bypass_T_4 = or(_mem_cannot_bypass_T_3, mem_ctrl.div) node _mem_cannot_bypass_T_5 = or(_mem_cannot_bypass_T_4, mem_ctrl.fp) node _mem_cannot_bypass_T_6 = or(_mem_cannot_bypass_T_5, mem_ctrl.rocc) node mem_cannot_bypass = or(_mem_cannot_bypass_T_6, mem_ctrl.vec) node _data_hazard_mem_T = eq(id_raddr1, mem_waddr) node _data_hazard_mem_T_1 = and(hazard_targets_0_1, _data_hazard_mem_T) node _data_hazard_mem_T_2 = eq(id_raddr2, mem_waddr) node _data_hazard_mem_T_3 = and(hazard_targets_1_1, _data_hazard_mem_T_2) node _data_hazard_mem_T_4 = eq(id_waddr, mem_waddr) node _data_hazard_mem_T_5 = and(hazard_targets_2_1, _data_hazard_mem_T_4) node _data_hazard_mem_T_6 = or(_data_hazard_mem_T_1, _data_hazard_mem_T_3) node _data_hazard_mem_T_7 = or(_data_hazard_mem_T_6, _data_hazard_mem_T_5) node data_hazard_mem = and(mem_ctrl.wxd, _data_hazard_mem_T_7) node _fp_data_hazard_mem_T = and(id_ctrl.fp, mem_ctrl.wfd) node _fp_data_hazard_mem_T_1 = eq(id_raddr1, mem_waddr) node _fp_data_hazard_mem_T_2 = and(io.fpu.dec.ren1, _fp_data_hazard_mem_T_1) node _fp_data_hazard_mem_T_3 = eq(id_raddr2, mem_waddr) node _fp_data_hazard_mem_T_4 = and(io.fpu.dec.ren2, _fp_data_hazard_mem_T_3) node _fp_data_hazard_mem_T_5 = eq(id_raddr3, mem_waddr) node _fp_data_hazard_mem_T_6 = and(io.fpu.dec.ren3, _fp_data_hazard_mem_T_5) node _fp_data_hazard_mem_T_7 = eq(id_waddr, mem_waddr) node _fp_data_hazard_mem_T_8 = and(io.fpu.dec.wen, _fp_data_hazard_mem_T_7) node _fp_data_hazard_mem_T_9 = or(_fp_data_hazard_mem_T_2, _fp_data_hazard_mem_T_4) node _fp_data_hazard_mem_T_10 = or(_fp_data_hazard_mem_T_9, _fp_data_hazard_mem_T_6) node _fp_data_hazard_mem_T_11 = or(_fp_data_hazard_mem_T_10, _fp_data_hazard_mem_T_8) node fp_data_hazard_mem = and(_fp_data_hazard_mem_T, _fp_data_hazard_mem_T_11) node _id_mem_hazard_T = and(data_hazard_mem, mem_cannot_bypass) node _id_mem_hazard_T_1 = or(_id_mem_hazard_T, fp_data_hazard_mem) node id_mem_hazard = and(mem_reg_valid, _id_mem_hazard_T_1) node _id_load_use_T = and(mem_reg_valid, data_hazard_mem) node _id_load_use_T_1 = and(_id_load_use_T, mem_ctrl.mem) connect id_load_use, _id_load_use_T_1 node _id_vconfig_hazard_T = and(ex_reg_valid, ex_reg_set_vconfig) node _id_vconfig_hazard_T_1 = and(mem_reg_valid, mem_reg_set_vconfig) node _id_vconfig_hazard_T_2 = or(_id_vconfig_hazard_T, _id_vconfig_hazard_T_1) node _id_vconfig_hazard_T_3 = and(wb_reg_valid, wb_reg_set_vconfig) node _id_vconfig_hazard_T_4 = or(_id_vconfig_hazard_T_2, _id_vconfig_hazard_T_3) node id_vconfig_hazard = and(id_ctrl.vec, _id_vconfig_hazard_T_4) node _data_hazard_wb_T = eq(id_raddr1, wb_waddr) node _data_hazard_wb_T_1 = and(hazard_targets_0_1, _data_hazard_wb_T) node _data_hazard_wb_T_2 = eq(id_raddr2, wb_waddr) node _data_hazard_wb_T_3 = and(hazard_targets_1_1, _data_hazard_wb_T_2) node _data_hazard_wb_T_4 = eq(id_waddr, wb_waddr) node _data_hazard_wb_T_5 = and(hazard_targets_2_1, _data_hazard_wb_T_4) node _data_hazard_wb_T_6 = or(_data_hazard_wb_T_1, _data_hazard_wb_T_3) node _data_hazard_wb_T_7 = or(_data_hazard_wb_T_6, _data_hazard_wb_T_5) node data_hazard_wb = and(wb_ctrl.wxd, _data_hazard_wb_T_7) node _fp_data_hazard_wb_T = and(id_ctrl.fp, wb_ctrl.wfd) node _fp_data_hazard_wb_T_1 = eq(id_raddr1, wb_waddr) node _fp_data_hazard_wb_T_2 = and(io.fpu.dec.ren1, _fp_data_hazard_wb_T_1) node _fp_data_hazard_wb_T_3 = eq(id_raddr2, wb_waddr) node _fp_data_hazard_wb_T_4 = and(io.fpu.dec.ren2, _fp_data_hazard_wb_T_3) node _fp_data_hazard_wb_T_5 = eq(id_raddr3, wb_waddr) node _fp_data_hazard_wb_T_6 = and(io.fpu.dec.ren3, _fp_data_hazard_wb_T_5) node _fp_data_hazard_wb_T_7 = eq(id_waddr, wb_waddr) node _fp_data_hazard_wb_T_8 = and(io.fpu.dec.wen, _fp_data_hazard_wb_T_7) node _fp_data_hazard_wb_T_9 = or(_fp_data_hazard_wb_T_2, _fp_data_hazard_wb_T_4) node _fp_data_hazard_wb_T_10 = or(_fp_data_hazard_wb_T_9, _fp_data_hazard_wb_T_6) node _fp_data_hazard_wb_T_11 = or(_fp_data_hazard_wb_T_10, _fp_data_hazard_wb_T_8) node fp_data_hazard_wb = and(_fp_data_hazard_wb_T, _fp_data_hazard_wb_T_11) node _id_wb_hazard_T = and(data_hazard_wb, wb_set_sboard) node _id_wb_hazard_T_1 = or(_id_wb_hazard_T, fp_data_hazard_wb) node id_wb_hazard = and(wb_reg_valid, _id_wb_hazard_T_1) regreset _id_stall_fpu_r : UInt<32>, clock, reset, UInt<32>(0h0) node _id_stall_fpu_T = or(wb_dcache_miss, wb_ctrl.vec) node _id_stall_fpu_T_1 = and(_id_stall_fpu_T, wb_ctrl.wfd) node _id_stall_fpu_T_2 = or(_id_stall_fpu_T_1, io.fpu.sboard_set) node _id_stall_fpu_T_3 = and(_id_stall_fpu_T_2, wb_valid) node _id_stall_fpu_T_4 = dshl(UInt<1>(0h1), wb_waddr) node _id_stall_fpu_T_5 = mux(_id_stall_fpu_T_3, _id_stall_fpu_T_4, UInt<1>(0h0)) node _id_stall_fpu_T_6 = or(_id_stall_fpu_r, _id_stall_fpu_T_5) node _id_stall_fpu_T_7 = or(UInt<1>(0h0), _id_stall_fpu_T_3) when _id_stall_fpu_T_7 : connect _id_stall_fpu_r, _id_stall_fpu_T_6 node _id_stall_fpu_T_8 = and(dmem_resp_replay, dmem_resp_fpu) node _id_stall_fpu_T_9 = or(_id_stall_fpu_T_8, UInt<1>(0h0)) node _id_stall_fpu_T_10 = dshl(UInt<1>(0h1), io.fpu.ll_resp_tag) node _id_stall_fpu_T_11 = mux(_id_stall_fpu_T_9, _id_stall_fpu_T_10, UInt<1>(0h0)) node _id_stall_fpu_T_12 = not(_id_stall_fpu_T_11) node _id_stall_fpu_T_13 = and(_id_stall_fpu_T_6, _id_stall_fpu_T_12) node _id_stall_fpu_T_14 = or(_id_stall_fpu_T_7, _id_stall_fpu_T_9) when _id_stall_fpu_T_14 : connect _id_stall_fpu_r, _id_stall_fpu_T_13 node _id_stall_fpu_T_15 = dshl(UInt<1>(0h1), io.fpu.sboard_clra) node _id_stall_fpu_T_16 = mux(io.fpu.sboard_clr, _id_stall_fpu_T_15, UInt<1>(0h0)) node _id_stall_fpu_T_17 = not(_id_stall_fpu_T_16) node _id_stall_fpu_T_18 = and(_id_stall_fpu_T_13, _id_stall_fpu_T_17) node _id_stall_fpu_T_19 = or(_id_stall_fpu_T_14, io.fpu.sboard_clr) when _id_stall_fpu_T_19 : connect _id_stall_fpu_r, _id_stall_fpu_T_18 node _id_stall_fpu_T_20 = dshr(_id_stall_fpu_r, id_raddr1) node _id_stall_fpu_T_21 = bits(_id_stall_fpu_T_20, 0, 0) node _id_stall_fpu_T_22 = and(io.fpu.dec.ren1, _id_stall_fpu_T_21) node _id_stall_fpu_T_23 = dshr(_id_stall_fpu_r, id_raddr2) node _id_stall_fpu_T_24 = bits(_id_stall_fpu_T_23, 0, 0) node _id_stall_fpu_T_25 = and(io.fpu.dec.ren2, _id_stall_fpu_T_24) node _id_stall_fpu_T_26 = dshr(_id_stall_fpu_r, id_raddr3) node _id_stall_fpu_T_27 = bits(_id_stall_fpu_T_26, 0, 0) node _id_stall_fpu_T_28 = and(io.fpu.dec.ren3, _id_stall_fpu_T_27) node _id_stall_fpu_T_29 = dshr(_id_stall_fpu_r, id_waddr) node _id_stall_fpu_T_30 = bits(_id_stall_fpu_T_29, 0, 0) node _id_stall_fpu_T_31 = and(io.fpu.dec.wen, _id_stall_fpu_T_30) node _id_stall_fpu_T_32 = or(_id_stall_fpu_T_22, _id_stall_fpu_T_25) node _id_stall_fpu_T_33 = or(_id_stall_fpu_T_32, _id_stall_fpu_T_28) node id_stall_fpu = or(_id_stall_fpu_T_33, _id_stall_fpu_T_31) reg dcache_blocked_blocked : UInt<1>, clock node _dcache_blocked_blocked_T = eq(io.dmem.req.ready, UInt<1>(0h0)) node _dcache_blocked_blocked_T_1 = and(_dcache_blocked_blocked_T, io.dmem.clock_enabled) node _dcache_blocked_blocked_T_2 = eq(io.dmem.perf.grant, UInt<1>(0h0)) node _dcache_blocked_blocked_T_3 = and(_dcache_blocked_blocked_T_1, _dcache_blocked_blocked_T_2) node _dcache_blocked_blocked_T_4 = or(dcache_blocked_blocked, io.dmem.req.valid) node _dcache_blocked_blocked_T_5 = or(_dcache_blocked_blocked_T_4, io.dmem.s2_nack) node _dcache_blocked_blocked_T_6 = and(_dcache_blocked_blocked_T_3, _dcache_blocked_blocked_T_5) connect dcache_blocked_blocked, _dcache_blocked_blocked_T_6 node _dcache_blocked_T = eq(io.dmem.perf.grant, UInt<1>(0h0)) node dcache_blocked = and(dcache_blocked_blocked, _dcache_blocked_T) reg rocc_blocked : UInt<1>, clock node _rocc_blocked_T = eq(wb_xcpt, UInt<1>(0h0)) node _rocc_blocked_T_1 = eq(io.rocc.cmd.ready, UInt<1>(0h0)) node _rocc_blocked_T_2 = and(_rocc_blocked_T, _rocc_blocked_T_1) node _rocc_blocked_T_3 = or(io.rocc.cmd.valid, rocc_blocked) node _rocc_blocked_T_4 = and(_rocc_blocked_T_2, _rocc_blocked_T_3) connect rocc_blocked, _rocc_blocked_T_4 node _ctrl_stalld_T = or(id_ex_hazard, id_mem_hazard) node _ctrl_stalld_T_1 = or(_ctrl_stalld_T, id_wb_hazard) node _ctrl_stalld_T_2 = or(_ctrl_stalld_T_1, id_sboard_hazard) node _ctrl_stalld_T_3 = or(_ctrl_stalld_T_2, id_vconfig_hazard) node _ctrl_stalld_T_4 = or(ex_reg_valid, mem_reg_valid) node _ctrl_stalld_T_5 = or(_ctrl_stalld_T_4, wb_reg_valid) node _ctrl_stalld_T_6 = and(csr.io.singleStep, _ctrl_stalld_T_5) node _ctrl_stalld_T_7 = or(_ctrl_stalld_T_3, _ctrl_stalld_T_6) node _ctrl_stalld_T_8 = and(id_csr_en, csr.io.decode[0].fp_csr) node _ctrl_stalld_T_9 = eq(io.fpu.fcsr_rdy, UInt<1>(0h0)) node _ctrl_stalld_T_10 = and(_ctrl_stalld_T_8, _ctrl_stalld_T_9) node _ctrl_stalld_T_11 = or(_ctrl_stalld_T_7, _ctrl_stalld_T_10) node _ctrl_stalld_T_12 = and(id_csr_en, csr.io.decode[0].vector_csr) node _ctrl_stalld_T_13 = and(_ctrl_stalld_T_12, UInt<1>(0h0)) node _ctrl_stalld_T_14 = or(_ctrl_stalld_T_11, _ctrl_stalld_T_13) node _ctrl_stalld_T_15 = and(id_ctrl.fp, id_stall_fpu) node _ctrl_stalld_T_16 = or(_ctrl_stalld_T_14, _ctrl_stalld_T_15) node _ctrl_stalld_T_17 = and(id_ctrl.mem, dcache_blocked) node _ctrl_stalld_T_18 = or(_ctrl_stalld_T_16, _ctrl_stalld_T_17) node _ctrl_stalld_T_19 = and(id_ctrl.rocc, rocc_blocked) node _ctrl_stalld_T_20 = or(_ctrl_stalld_T_18, _ctrl_stalld_T_19) node _ctrl_stalld_T_21 = eq(wb_wxd, UInt<1>(0h0)) node _ctrl_stalld_T_22 = and(div.io.resp.valid, _ctrl_stalld_T_21) node _ctrl_stalld_T_23 = or(div.io.req.ready, _ctrl_stalld_T_22) node _ctrl_stalld_T_24 = eq(_ctrl_stalld_T_23, UInt<1>(0h0)) node _ctrl_stalld_T_25 = or(_ctrl_stalld_T_24, div.io.req.valid) node _ctrl_stalld_T_26 = and(id_ctrl.div, _ctrl_stalld_T_25) node _ctrl_stalld_T_27 = or(_ctrl_stalld_T_20, _ctrl_stalld_T_26) node _ctrl_stalld_T_28 = eq(clock_en, UInt<1>(0h0)) node _ctrl_stalld_T_29 = or(_ctrl_stalld_T_27, _ctrl_stalld_T_28) node _ctrl_stalld_T_30 = or(_ctrl_stalld_T_29, id_do_fence) node _ctrl_stalld_T_31 = or(_ctrl_stalld_T_30, csr.io.csr_stall) node _ctrl_stalld_T_32 = or(_ctrl_stalld_T_31, id_reg_pause) node ctrl_stalld = or(_ctrl_stalld_T_32, io.traceStall) node _ctrl_killd_T = eq(ibuf.io.inst[0].valid, UInt<1>(0h0)) node _ctrl_killd_T_1 = or(_ctrl_killd_T, ibuf.io.inst[0].bits.replay) node _ctrl_killd_T_2 = or(_ctrl_killd_T_1, take_pc_mem_wb) node _ctrl_killd_T_3 = or(_ctrl_killd_T_2, ctrl_stalld) node _ctrl_killd_T_4 = or(_ctrl_killd_T_3, csr.io.interrupt) connect ctrl_killd, _ctrl_killd_T_4 connect io.imem.req.valid, take_pc_mem_wb node _io_imem_req_bits_speculative_T = eq(take_pc_wb, UInt<1>(0h0)) connect io.imem.req.bits.speculative, _io_imem_req_bits_speculative_T node _io_imem_req_bits_pc_T = or(wb_xcpt, csr.io.eret) node _io_imem_req_bits_pc_T_1 = mux(replay_wb, wb_reg_pc, mem_npc) node _io_imem_req_bits_pc_T_2 = mux(_io_imem_req_bits_pc_T, csr.io.evec, _io_imem_req_bits_pc_T_1) connect io.imem.req.bits.pc, _io_imem_req_bits_pc_T_2 node _io_imem_flush_icache_T = and(wb_reg_valid, wb_ctrl.fence_i) node _io_imem_flush_icache_T_1 = eq(io.dmem.s2_nack, UInt<1>(0h0)) node _io_imem_flush_icache_T_2 = and(_io_imem_flush_icache_T, _io_imem_flush_icache_T_1) connect io.imem.flush_icache, _io_imem_flush_icache_T_2 node _io_imem_might_request_imem_might_request_reg_T = or(ex_pc_valid, mem_pc_valid) node _io_imem_might_request_imem_might_request_reg_T_1 = bits(io.ptw.customCSRs.csrs[0].value, 1, 1) node _io_imem_might_request_imem_might_request_reg_T_2 = or(_io_imem_might_request_imem_might_request_reg_T, _io_imem_might_request_imem_might_request_reg_T_1) node _io_imem_might_request_imem_might_request_reg_T_3 = or(_io_imem_might_request_imem_might_request_reg_T_2, UInt<1>(0h0)) connect imem_might_request_reg, _io_imem_might_request_imem_might_request_reg_T_3 connect io.imem.might_request, imem_might_request_reg node _io_imem_progress_T = eq(replay_wb_common, UInt<1>(0h0)) node _io_imem_progress_T_1 = and(wb_reg_valid, _io_imem_progress_T) reg io_imem_progress_REG : UInt<1>, clock connect io_imem_progress_REG, _io_imem_progress_T_1 connect io.imem.progress, io_imem_progress_REG node _io_imem_sfence_valid_T = and(wb_reg_valid, wb_reg_sfence) connect io.imem.sfence.valid, _io_imem_sfence_valid_T node _io_imem_sfence_bits_rs1_T = bits(wb_reg_mem_size, 0, 0) connect io.imem.sfence.bits.rs1, _io_imem_sfence_bits_rs1_T node _io_imem_sfence_bits_rs2_T = bits(wb_reg_mem_size, 1, 1) connect io.imem.sfence.bits.rs2, _io_imem_sfence_bits_rs2_T connect io.imem.sfence.bits.addr, wb_reg_wdata connect io.imem.sfence.bits.asid, wb_reg_rs2 connect io.imem.sfence.bits.hv, wb_reg_hfence_v connect io.imem.sfence.bits.hg, wb_reg_hfence_g connect io.ptw.sfence.bits.hg, io.imem.sfence.bits.hg connect io.ptw.sfence.bits.hv, io.imem.sfence.bits.hv connect io.ptw.sfence.bits.asid, io.imem.sfence.bits.asid connect io.ptw.sfence.bits.addr, io.imem.sfence.bits.addr connect io.ptw.sfence.bits.rs2, io.imem.sfence.bits.rs2 connect io.ptw.sfence.bits.rs1, io.imem.sfence.bits.rs1 connect io.ptw.sfence.valid, io.imem.sfence.valid node _ibuf_io_inst_0_ready_T = eq(ctrl_stalld, UInt<1>(0h0)) connect ibuf.io.inst[0].ready, _ibuf_io_inst_0_ready_T node _io_imem_btb_update_valid_T = eq(take_pc_wb, UInt<1>(0h0)) node _io_imem_btb_update_valid_T_1 = and(mem_reg_valid, _io_imem_btb_update_valid_T) node _io_imem_btb_update_valid_T_2 = and(_io_imem_btb_update_valid_T_1, mem_wrong_npc) node _io_imem_btb_update_valid_T_3 = eq(mem_cfi, UInt<1>(0h0)) node _io_imem_btb_update_valid_T_4 = or(_io_imem_btb_update_valid_T_3, mem_cfi_taken) node _io_imem_btb_update_valid_T_5 = and(_io_imem_btb_update_valid_T_2, _io_imem_btb_update_valid_T_4) connect io.imem.btb_update.valid, _io_imem_btb_update_valid_T_5 connect io.imem.btb_update.bits.isValid, mem_cfi node _io_imem_btb_update_bits_cfiType_T = or(mem_ctrl.jal, mem_ctrl.jalr) node _io_imem_btb_update_bits_cfiType_T_1 = bits(mem_waddr, 0, 0) node _io_imem_btb_update_bits_cfiType_T_2 = and(_io_imem_btb_update_bits_cfiType_T, _io_imem_btb_update_bits_cfiType_T_1) node _io_imem_btb_update_bits_cfiType_T_3 = bits(mem_reg_inst, 19, 15) node _io_imem_btb_update_bits_cfiType_T_4 = and(_io_imem_btb_update_bits_cfiType_T_3, UInt<5>(0h1f)) node _io_imem_btb_update_bits_cfiType_T_5 = and(_io_imem_btb_update_bits_cfiType_T_4, UInt<5>(0h1b)) node _io_imem_btb_update_bits_cfiType_T_6 = eq(UInt<1>(0h1), _io_imem_btb_update_bits_cfiType_T_5) node _io_imem_btb_update_bits_cfiType_T_7 = and(mem_ctrl.jalr, _io_imem_btb_update_bits_cfiType_T_6) node _io_imem_btb_update_bits_cfiType_T_8 = or(mem_ctrl.jal, mem_ctrl.jalr) node _io_imem_btb_update_bits_cfiType_T_9 = mux(_io_imem_btb_update_bits_cfiType_T_8, UInt<1>(0h1), UInt<1>(0h0)) node _io_imem_btb_update_bits_cfiType_T_10 = mux(_io_imem_btb_update_bits_cfiType_T_7, UInt<2>(0h3), _io_imem_btb_update_bits_cfiType_T_9) node _io_imem_btb_update_bits_cfiType_T_11 = mux(_io_imem_btb_update_bits_cfiType_T_2, UInt<2>(0h2), _io_imem_btb_update_bits_cfiType_T_10) connect io.imem.btb_update.bits.cfiType, _io_imem_btb_update_bits_cfiType_T_11 connect io.imem.btb_update.bits.target, io.imem.req.bits.pc node _io_imem_btb_update_bits_br_pc_T = mux(mem_reg_rvc, UInt<1>(0h0), UInt<2>(0h2)) node _io_imem_btb_update_bits_br_pc_T_1 = add(mem_reg_pc, _io_imem_btb_update_bits_br_pc_T) node _io_imem_btb_update_bits_br_pc_T_2 = tail(_io_imem_btb_update_bits_br_pc_T_1, 1) connect io.imem.btb_update.bits.br_pc, _io_imem_btb_update_bits_br_pc_T_2 node _io_imem_btb_update_bits_pc_T = not(io.imem.btb_update.bits.br_pc) node _io_imem_btb_update_bits_pc_T_1 = or(_io_imem_btb_update_bits_pc_T, UInt<2>(0h3)) node _io_imem_btb_update_bits_pc_T_2 = not(_io_imem_btb_update_bits_pc_T_1) connect io.imem.btb_update.bits.pc, _io_imem_btb_update_bits_pc_T_2 connect io.imem.btb_update.bits.prediction, mem_reg_btb_resp invalidate io.imem.btb_update.bits.taken node _io_imem_bht_update_valid_T = eq(take_pc_wb, UInt<1>(0h0)) node _io_imem_bht_update_valid_T_1 = and(mem_reg_valid, _io_imem_bht_update_valid_T) connect io.imem.bht_update.valid, _io_imem_bht_update_valid_T_1 connect io.imem.bht_update.bits.pc, io.imem.btb_update.bits.pc connect io.imem.bht_update.bits.taken, mem_br_taken connect io.imem.bht_update.bits.mispredict, mem_wrong_npc connect io.imem.bht_update.bits.branch, mem_ctrl.branch connect io.imem.bht_update.bits.prediction, mem_reg_btb_resp.bht invalidate io.imem.ras_update.bits.returnAddr invalidate io.imem.ras_update.bits.cfiType invalidate io.imem.ras_update.valid node _io_fpu_valid_T = eq(ctrl_killd, UInt<1>(0h0)) node _io_fpu_valid_T_1 = and(_io_fpu_valid_T, id_ctrl.fp) connect io.fpu.valid, _io_fpu_valid_T_1 connect io.fpu.killx, ctrl_killx connect io.fpu.killm, killm_common connect io.fpu.inst, ibuf.io.inst[0].bits.inst.bits connect io.fpu.fromint_data, ex_rs_0 node _io_fpu_ll_resp_val_T = and(dmem_resp_valid, dmem_resp_fpu) connect io.fpu.ll_resp_val, _io_fpu_ll_resp_val_T connect io.fpu.ll_resp_data, io.dmem.resp.bits.data connect io.fpu.ll_resp_type, io.dmem.resp.bits.size connect io.fpu.ll_resp_tag, dmem_resp_waddr node _io_fpu_keep_clock_enabled_T = bits(io.ptw.customCSRs.csrs[0].value, 2, 2) connect io.fpu.keep_clock_enabled, _io_fpu_keep_clock_enabled_T connect io.fpu.v_sew, UInt<1>(0h0) node _io_dmem_req_valid_T = and(ex_reg_valid, ex_ctrl.mem) connect io.dmem.req.valid, _io_dmem_req_valid_T node ex_dcache_tag = cat(ex_waddr, ex_ctrl.fp) connect io.dmem.req.bits.tag, ex_dcache_tag connect io.dmem.req.bits.cmd, ex_ctrl.mem_cmd connect io.dmem.req.bits.size, ex_reg_mem_size node _io_dmem_req_bits_signed_T = bits(ex_reg_inst, 20, 20) node _io_dmem_req_bits_signed_T_1 = bits(ex_reg_inst, 14, 14) node _io_dmem_req_bits_signed_T_2 = mux(ex_reg_hls, _io_dmem_req_bits_signed_T, _io_dmem_req_bits_signed_T_1) node _io_dmem_req_bits_signed_T_3 = eq(_io_dmem_req_bits_signed_T_2, UInt<1>(0h0)) connect io.dmem.req.bits.signed, _io_dmem_req_bits_signed_T_3 connect io.dmem.req.bits.phys, UInt<1>(0h0) node _io_dmem_req_bits_addr_a_T = shr(ex_rs_0, 39) node io_dmem_req_bits_addr_a = asSInt(_io_dmem_req_bits_addr_a_T) node _io_dmem_req_bits_addr_msb_T = eq(io_dmem_req_bits_addr_a, asSInt(UInt<1>(0h0))) node _io_dmem_req_bits_addr_msb_T_1 = eq(io_dmem_req_bits_addr_a, asSInt(UInt<1>(0h1))) node _io_dmem_req_bits_addr_msb_T_2 = or(_io_dmem_req_bits_addr_msb_T, _io_dmem_req_bits_addr_msb_T_1) node _io_dmem_req_bits_addr_msb_T_3 = bits(alu.io.adder_out, 39, 39) node _io_dmem_req_bits_addr_msb_T_4 = bits(alu.io.adder_out, 38, 38) node _io_dmem_req_bits_addr_msb_T_5 = eq(_io_dmem_req_bits_addr_msb_T_4, UInt<1>(0h0)) node io_dmem_req_bits_addr_msb = mux(_io_dmem_req_bits_addr_msb_T_2, _io_dmem_req_bits_addr_msb_T_3, _io_dmem_req_bits_addr_msb_T_5) node _io_dmem_req_bits_addr_T = bits(alu.io.adder_out, 38, 0) node _io_dmem_req_bits_addr_T_1 = cat(io_dmem_req_bits_addr_msb, _io_dmem_req_bits_addr_T) connect io.dmem.req.bits.addr, _io_dmem_req_bits_addr_T_1 node _io_dmem_req_bits_dprv_T = mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) connect io.dmem.req.bits.dprv, _io_dmem_req_bits_dprv_T node _io_dmem_req_bits_dv_T = or(ex_reg_hls, csr.io.status.dv) connect io.dmem.req.bits.dv, _io_dmem_req_bits_dv_T node _io_dmem_req_bits_no_resp_T = eq(ex_ctrl.mem_cmd, UInt<1>(0h0)) node _io_dmem_req_bits_no_resp_T_1 = eq(ex_ctrl.mem_cmd, UInt<5>(0h10)) node _io_dmem_req_bits_no_resp_T_2 = eq(ex_ctrl.mem_cmd, UInt<3>(0h6)) node _io_dmem_req_bits_no_resp_T_3 = eq(ex_ctrl.mem_cmd, UInt<3>(0h7)) node _io_dmem_req_bits_no_resp_T_4 = or(_io_dmem_req_bits_no_resp_T, _io_dmem_req_bits_no_resp_T_1) node _io_dmem_req_bits_no_resp_T_5 = or(_io_dmem_req_bits_no_resp_T_4, _io_dmem_req_bits_no_resp_T_2) node _io_dmem_req_bits_no_resp_T_6 = or(_io_dmem_req_bits_no_resp_T_5, _io_dmem_req_bits_no_resp_T_3) node _io_dmem_req_bits_no_resp_T_7 = eq(ex_ctrl.mem_cmd, UInt<3>(0h4)) node _io_dmem_req_bits_no_resp_T_8 = eq(ex_ctrl.mem_cmd, UInt<4>(0h9)) node _io_dmem_req_bits_no_resp_T_9 = eq(ex_ctrl.mem_cmd, UInt<4>(0ha)) node _io_dmem_req_bits_no_resp_T_10 = eq(ex_ctrl.mem_cmd, UInt<4>(0hb)) node _io_dmem_req_bits_no_resp_T_11 = or(_io_dmem_req_bits_no_resp_T_7, _io_dmem_req_bits_no_resp_T_8) node _io_dmem_req_bits_no_resp_T_12 = or(_io_dmem_req_bits_no_resp_T_11, _io_dmem_req_bits_no_resp_T_9) node _io_dmem_req_bits_no_resp_T_13 = or(_io_dmem_req_bits_no_resp_T_12, _io_dmem_req_bits_no_resp_T_10) node _io_dmem_req_bits_no_resp_T_14 = eq(ex_ctrl.mem_cmd, UInt<4>(0h8)) node _io_dmem_req_bits_no_resp_T_15 = eq(ex_ctrl.mem_cmd, UInt<4>(0hc)) node _io_dmem_req_bits_no_resp_T_16 = eq(ex_ctrl.mem_cmd, UInt<4>(0hd)) node _io_dmem_req_bits_no_resp_T_17 = eq(ex_ctrl.mem_cmd, UInt<4>(0he)) node _io_dmem_req_bits_no_resp_T_18 = eq(ex_ctrl.mem_cmd, UInt<4>(0hf)) node _io_dmem_req_bits_no_resp_T_19 = or(_io_dmem_req_bits_no_resp_T_14, _io_dmem_req_bits_no_resp_T_15) node _io_dmem_req_bits_no_resp_T_20 = or(_io_dmem_req_bits_no_resp_T_19, _io_dmem_req_bits_no_resp_T_16) node _io_dmem_req_bits_no_resp_T_21 = or(_io_dmem_req_bits_no_resp_T_20, _io_dmem_req_bits_no_resp_T_17) node _io_dmem_req_bits_no_resp_T_22 = or(_io_dmem_req_bits_no_resp_T_21, _io_dmem_req_bits_no_resp_T_18) node _io_dmem_req_bits_no_resp_T_23 = or(_io_dmem_req_bits_no_resp_T_13, _io_dmem_req_bits_no_resp_T_22) node _io_dmem_req_bits_no_resp_T_24 = or(_io_dmem_req_bits_no_resp_T_6, _io_dmem_req_bits_no_resp_T_23) node _io_dmem_req_bits_no_resp_T_25 = eq(_io_dmem_req_bits_no_resp_T_24, UInt<1>(0h0)) node _io_dmem_req_bits_no_resp_T_26 = eq(ex_ctrl.fp, UInt<1>(0h0)) node _io_dmem_req_bits_no_resp_T_27 = eq(ex_waddr, UInt<1>(0h0)) node _io_dmem_req_bits_no_resp_T_28 = and(_io_dmem_req_bits_no_resp_T_26, _io_dmem_req_bits_no_resp_T_27) node _io_dmem_req_bits_no_resp_T_29 = or(_io_dmem_req_bits_no_resp_T_25, _io_dmem_req_bits_no_resp_T_28) connect io.dmem.req.bits.no_resp, _io_dmem_req_bits_no_resp_T_29 invalidate io.dmem.req.bits.no_alloc invalidate io.dmem.req.bits.no_xcpt invalidate io.dmem.req.bits.data invalidate io.dmem.req.bits.mask node _io_dmem_s1_data_data_T = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) connect io.dmem.s1_data.data, _io_dmem_s1_data_data_T invalidate io.dmem.s1_data.mask node _io_dmem_s1_kill_T = or(killm_common, mem_ldst_xcpt) node _io_dmem_s1_kill_T_1 = or(_io_dmem_s1_kill_T, fpu_kill_mem) node _io_dmem_s1_kill_T_2 = or(_io_dmem_s1_kill_T_1, vec_kill_mem) connect io.dmem.s1_kill, _io_dmem_s1_kill_T_2 connect io.dmem.s2_kill, UInt<1>(0h0) node _io_dmem_keep_clock_enabled_T = and(ibuf.io.inst[0].valid, id_ctrl.mem) node _io_dmem_keep_clock_enabled_T_1 = eq(csr.io.csr_stall, UInt<1>(0h0)) node _io_dmem_keep_clock_enabled_T_2 = and(_io_dmem_keep_clock_enabled_T, _io_dmem_keep_clock_enabled_T_1) connect io.dmem.keep_clock_enabled, _io_dmem_keep_clock_enabled_T_2 node _io_rocc_cmd_valid_T = and(wb_reg_valid, wb_ctrl.rocc) node _io_rocc_cmd_valid_T_1 = eq(replay_wb_common, UInt<1>(0h0)) node _io_rocc_cmd_valid_T_2 = and(_io_rocc_cmd_valid_T, _io_rocc_cmd_valid_T_1) connect io.rocc.cmd.valid, _io_rocc_cmd_valid_T_2 node _io_rocc_exception_T = orr(csr.io.status.xs) node _io_rocc_exception_T_1 = and(wb_xcpt, _io_rocc_exception_T) connect io.rocc.exception, _io_rocc_exception_T_1 connect io.rocc.cmd.bits.status, csr.io.status wire _io_rocc_cmd_bits_inst_WIRE : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} wire _io_rocc_cmd_bits_inst_WIRE_1 : UInt<32> connect _io_rocc_cmd_bits_inst_WIRE_1, wb_reg_inst node _io_rocc_cmd_bits_inst_T = bits(_io_rocc_cmd_bits_inst_WIRE_1, 6, 0) connect _io_rocc_cmd_bits_inst_WIRE.opcode, _io_rocc_cmd_bits_inst_T node _io_rocc_cmd_bits_inst_T_1 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 11, 7) connect _io_rocc_cmd_bits_inst_WIRE.rd, _io_rocc_cmd_bits_inst_T_1 node _io_rocc_cmd_bits_inst_T_2 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 12, 12) connect _io_rocc_cmd_bits_inst_WIRE.xs2, _io_rocc_cmd_bits_inst_T_2 node _io_rocc_cmd_bits_inst_T_3 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 13, 13) connect _io_rocc_cmd_bits_inst_WIRE.xs1, _io_rocc_cmd_bits_inst_T_3 node _io_rocc_cmd_bits_inst_T_4 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 14, 14) connect _io_rocc_cmd_bits_inst_WIRE.xd, _io_rocc_cmd_bits_inst_T_4 node _io_rocc_cmd_bits_inst_T_5 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 19, 15) connect _io_rocc_cmd_bits_inst_WIRE.rs1, _io_rocc_cmd_bits_inst_T_5 node _io_rocc_cmd_bits_inst_T_6 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 24, 20) connect _io_rocc_cmd_bits_inst_WIRE.rs2, _io_rocc_cmd_bits_inst_T_6 node _io_rocc_cmd_bits_inst_T_7 = bits(_io_rocc_cmd_bits_inst_WIRE_1, 31, 25) connect _io_rocc_cmd_bits_inst_WIRE.funct, _io_rocc_cmd_bits_inst_T_7 connect io.rocc.cmd.bits.inst, _io_rocc_cmd_bits_inst_WIRE connect io.rocc.cmd.bits.rs1, wb_reg_wdata connect io.rocc.cmd.bits.rs2, wb_reg_rs2 node _unpause_T = bits(csr.io.time, 4, 0) node _unpause_T_1 = eq(_unpause_T, UInt<1>(0h0)) node _unpause_T_2 = or(_unpause_T_1, csr.io.inhibit_cycle) node _unpause_T_3 = or(_unpause_T_2, io.dmem.perf.release) node unpause = or(_unpause_T_3, take_pc_mem_wb) when unpause : connect id_reg_pause, UInt<1>(0h0) node _io_cease_T = eq(clock_en_reg, UInt<1>(0h0)) node _io_cease_T_1 = and(csr.io.status.cease, _io_cease_T) connect io.cease, _io_cease_T_1 connect io.wfi, csr.io.status.wfi reg icache_blocked_REG : UInt<1>, clock connect icache_blocked_REG, io.imem.resp.valid node _icache_blocked_T = or(io.imem.resp.valid, icache_blocked_REG) node icache_blocked = eq(_icache_blocked_T, UInt<1>(0h0)) wire coreMonitorBundle : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>} connect coreMonitorBundle.clock, clock connect coreMonitorBundle.reset, reset connect coreMonitorBundle.hartid, io.hartid node _coreMonitorBundle_timer_T = bits(csr.io.time, 31, 0) connect coreMonitorBundle.timer, _coreMonitorBundle_timer_T node _coreMonitorBundle_valid_T = eq(csr.io.trace[0].exception, UInt<1>(0h0)) node _coreMonitorBundle_valid_T_1 = and(csr.io.trace[0].valid, _coreMonitorBundle_valid_T) connect coreMonitorBundle.valid, _coreMonitorBundle_valid_T_1 node _coreMonitorBundle_pc_T = bits(csr.io.trace[0].iaddr, 39, 0) node _coreMonitorBundle_pc_T_1 = bits(_coreMonitorBundle_pc_T, 39, 39) node _coreMonitorBundle_pc_T_2 = mux(_coreMonitorBundle_pc_T_1, UInt<24>(0hffffff), UInt<24>(0h0)) node _coreMonitorBundle_pc_T_3 = cat(_coreMonitorBundle_pc_T_2, _coreMonitorBundle_pc_T) connect coreMonitorBundle.pc, _coreMonitorBundle_pc_T_3 node _coreMonitorBundle_wrenx_T = eq(wb_set_sboard, UInt<1>(0h0)) node _coreMonitorBundle_wrenx_T_1 = and(wb_wen, _coreMonitorBundle_wrenx_T) connect coreMonitorBundle.wrenx, _coreMonitorBundle_wrenx_T_1 connect coreMonitorBundle.wrenf, UInt<1>(0h0) connect coreMonitorBundle.wrdst, wb_waddr connect coreMonitorBundle.wrdata, rf_wdata node _coreMonitorBundle_rd0src_T = bits(wb_reg_inst, 19, 15) connect coreMonitorBundle.rd0src, _coreMonitorBundle_rd0src_T reg coreMonitorBundle_rd0val_REG : UInt, clock connect coreMonitorBundle_rd0val_REG, ex_rs_0 reg coreMonitorBundle_rd0val_REG_1 : UInt, clock connect coreMonitorBundle_rd0val_REG_1, coreMonitorBundle_rd0val_REG connect coreMonitorBundle.rd0val, coreMonitorBundle_rd0val_REG_1 node _coreMonitorBundle_rd1src_T = bits(wb_reg_inst, 24, 20) connect coreMonitorBundle.rd1src, _coreMonitorBundle_rd1src_T reg coreMonitorBundle_rd1val_REG : UInt, clock connect coreMonitorBundle_rd1val_REG, ex_rs_1 reg coreMonitorBundle_rd1val_REG_1 : UInt, clock connect coreMonitorBundle_rd1val_REG_1, coreMonitorBundle_rd1val_REG connect coreMonitorBundle.rd1val, coreMonitorBundle_rd1val_REG_1 connect coreMonitorBundle.inst, csr.io.trace[0].insn connect coreMonitorBundle.excpt, csr.io.trace[0].exception connect coreMonitorBundle.priv_mode, csr.io.trace[0].priv when csr.io.trace[0].valid : node _T_164 = or(wb_ctrl.wxd, wb_ctrl.wfd) node _T_165 = mux(_T_164, coreMonitorBundle.wrdst, UInt<1>(0h0)) node _T_166 = mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, UInt<1>(0h0)) node _T_167 = or(wb_ctrl.rxs1, wb_ctrl.rfs1) node _T_168 = mux(_T_167, coreMonitorBundle.rd0src, UInt<1>(0h0)) node _T_169 = or(wb_ctrl.rxs1, wb_ctrl.rfs1) node _T_170 = mux(_T_169, coreMonitorBundle.rd0val, UInt<1>(0h0)) node _T_171 = or(wb_ctrl.rxs2, wb_ctrl.rfs2) node _T_172 = mux(_T_171, coreMonitorBundle.rd1src, UInt<1>(0h0)) node _T_173 = or(wb_ctrl.rxs2, wb_ctrl.rfs2) node _T_174 = mux(_T_173, coreMonitorBundle.rd1val, UInt<1>(0h0)) node _T_175 = asUInt(reset) node _T_176 = eq(_T_175, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, _T_165, _T_166, coreMonitorBundle.wrenx, _T_168, _T_170, _T_172, _T_174, coreMonitorBundle.inst, coreMonitorBundle.inst) : printf_1 wire xrfWriteBundle : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>} connect xrfWriteBundle.clock, clock connect xrfWriteBundle.reset, reset connect xrfWriteBundle.hartid, io.hartid node _xrfWriteBundle_timer_T = bits(csr.io.time, 31, 0) connect xrfWriteBundle.timer, _xrfWriteBundle_timer_T connect xrfWriteBundle.valid, UInt<1>(0h0) connect xrfWriteBundle.pc, UInt<1>(0h0) connect xrfWriteBundle.wrdst, rf_waddr node _xrfWriteBundle_wrenx_T = and(csr.io.trace[0].valid, wb_wen) node _xrfWriteBundle_wrenx_T_1 = eq(wb_waddr, rf_waddr) node _xrfWriteBundle_wrenx_T_2 = and(_xrfWriteBundle_wrenx_T, _xrfWriteBundle_wrenx_T_1) node _xrfWriteBundle_wrenx_T_3 = eq(_xrfWriteBundle_wrenx_T_2, UInt<1>(0h0)) node _xrfWriteBundle_wrenx_T_4 = and(rf_wen, _xrfWriteBundle_wrenx_T_3) connect xrfWriteBundle.wrenx, _xrfWriteBundle_wrenx_T_4 connect xrfWriteBundle.wrenf, UInt<1>(0h0) connect xrfWriteBundle.wrdata, rf_wdata connect xrfWriteBundle.rd0src, UInt<1>(0h0) connect xrfWriteBundle.rd0val, UInt<1>(0h0) connect xrfWriteBundle.rd1src, UInt<1>(0h0) connect xrfWriteBundle.rd1val, UInt<1>(0h0) connect xrfWriteBundle.inst, UInt<1>(0h0) connect xrfWriteBundle.excpt, UInt<1>(0h0) connect xrfWriteBundle.priv_mode, csr.io.trace[0].priv inst PlusArgTimeout of PlusArgTimeout_4 connect PlusArgTimeout.clock, clock connect PlusArgTimeout.reset, reset connect PlusArgTimeout.io.count, csr.io.time	module Rocket_4( // @[RocketCore.scala:153:7] input clock, // @[RocketCore.scala:153:7] input reset, // @[RocketCore.scala:153:7] input [2:0] io_hartid, // @[RocketCore.scala:134:14] input io_interrupts_debug, // @[RocketCore.scala:134:14] input io_interrupts_mtip, // @[RocketCore.scala:134:14] input io_interrupts_msip, // @[RocketCore.scala:134:14] input io_interrupts_meip, // @[RocketCore.scala:134:14] input io_interrupts_seip, // @[RocketCore.scala:134:14] output io_imem_might_request, // @[RocketCore.scala:134:14] output io_imem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_imem_req_bits_pc, // @[RocketCore.scala:134:14] output io_imem_req_bits_speculative, // @[RocketCore.scala:134:14] output io_imem_sfence_valid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_imem_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_imem_resp_ready, // @[RocketCore.scala:134:14] input io_imem_resp_valid, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_cfiType, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_taken, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bridx, // @[RocketCore.scala:134:14] input [38:0] io_imem_resp_bits_btb_target, // @[RocketCore.scala:134:14] input [4:0] io_imem_resp_bits_btb_entry, // @[RocketCore.scala:134:14] input [7:0] io_imem_resp_bits_btb_bht_history, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bht_value, // @[RocketCore.scala:134:14] input [39:0] io_imem_resp_bits_pc, // @[RocketCore.scala:134:14] input [31:0] io_imem_resp_bits_data, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_pf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_gf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_ae_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_imem_gpa_valid, // @[RocketCore.scala:134:14] input [39:0] io_imem_gpa_bits, // @[RocketCore.scala:134:14] input io_imem_gpa_is_pte, // @[RocketCore.scala:134:14] output io_imem_btb_update_valid, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_cfiType, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_taken, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_mask, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bridx, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_prediction_target, // @[RocketCore.scala:134:14] output [4:0] io_imem_btb_update_bits_prediction_entry, // @[RocketCore.scala:134:14] output [7:0] io_imem_btb_update_bits_prediction_bht_history, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bht_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_pc, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_target, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_isValid, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_br_pc, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_cfiType, // @[RocketCore.scala:134:14] output io_imem_bht_update_valid, // @[RocketCore.scala:134:14] output [7:0] io_imem_bht_update_bits_prediction_history, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_prediction_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_bht_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_branch, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_taken, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_mispredict, // @[RocketCore.scala:134:14] output io_imem_flush_icache, // @[RocketCore.scala:134:14] input [39:0] io_imem_npc, // @[RocketCore.scala:134:14] input io_imem_perf_acquire, // @[RocketCore.scala:134:14] input io_imem_perf_tlbMiss, // @[RocketCore.scala:134:14] output io_imem_progress, // @[RocketCore.scala:134:14] input io_dmem_req_ready, // @[RocketCore.scala:134:14] output io_dmem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_dmem_req_bits_addr, // @[RocketCore.scala:134:14] output [6:0] io_dmem_req_bits_tag, // @[RocketCore.scala:134:14] output [4:0] io_dmem_req_bits_cmd, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_size, // @[RocketCore.scala:134:14] output io_dmem_req_bits_signed, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_dprv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_dv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_no_resp, // @[RocketCore.scala:134:14] output io_dmem_s1_kill, // @[RocketCore.scala:134:14] output [63:0] io_dmem_s1_data_data, // @[RocketCore.scala:134:14] input io_dmem_s2_nack, // @[RocketCore.scala:134:14] input io_dmem_s2_nack_cause_raw, // @[RocketCore.scala:134:14] input io_dmem_s2_uncached, // @[RocketCore.scala:134:14] input [31:0] io_dmem_s2_paddr, // @[RocketCore.scala:134:14] input io_dmem_resp_valid, // @[RocketCore.scala:134:14] input [39:0] io_dmem_resp_bits_addr, // @[RocketCore.scala:134:14] input [6:0] io_dmem_resp_bits_tag, // @[RocketCore.scala:134:14] input [4:0] io_dmem_resp_bits_cmd, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_size, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_signed, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_dprv, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_dv, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data, // @[RocketCore.scala:134:14] input [7:0] io_dmem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_has_data, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_word_bypass, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_raw, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_store_data, // @[RocketCore.scala:134:14] input io_dmem_replay_next, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_st, // @[RocketCore.scala:134:14] input [39:0] io_dmem_s2_gpa, // @[RocketCore.scala:134:14] input io_dmem_ordered, // @[RocketCore.scala:134:14] input io_dmem_store_pending, // @[RocketCore.scala:134:14] input io_dmem_perf_acquire, // @[RocketCore.scala:134:14] input io_dmem_perf_release, // @[RocketCore.scala:134:14] input io_dmem_perf_grant, // @[RocketCore.scala:134:14] input io_dmem_perf_tlbMiss, // @[RocketCore.scala:134:14] input io_dmem_perf_blocked, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenRMW, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptLoadThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterStore, // @[RocketCore.scala:134:14] output io_dmem_keep_clock_enabled, // @[RocketCore.scala:134:14] output [3:0] io_ptw_ptbr_mode, // @[RocketCore.scala:134:14] output [43:0] io_ptw_ptbr_ppn, // @[RocketCore.scala:134:14] output io_ptw_sfence_valid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_ptw_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_ptw_status_debug, // @[RocketCore.scala:134:14] output io_ptw_status_cease, // @[RocketCore.scala:134:14] output io_ptw_status_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_status_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_dprv, // @[RocketCore.scala:134:14] output io_ptw_status_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_prv, // @[RocketCore.scala:134:14] output io_ptw_status_v, // @[RocketCore.scala:134:14] output io_ptw_status_sd, // @[RocketCore.scala:134:14] output io_ptw_status_mpv, // @[RocketCore.scala:134:14] output io_ptw_status_gva, // @[RocketCore.scala:134:14] output io_ptw_status_tsr, // @[RocketCore.scala:134:14] output io_ptw_status_tw, // @[RocketCore.scala:134:14] output io_ptw_status_tvm, // @[RocketCore.scala:134:14] output io_ptw_status_mxr, // @[RocketCore.scala:134:14] output io_ptw_status_sum, // @[RocketCore.scala:134:14] output io_ptw_status_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_mpp, // @[RocketCore.scala:134:14] output io_ptw_status_spp, // @[RocketCore.scala:134:14] output io_ptw_status_mpie, // @[RocketCore.scala:134:14] output io_ptw_status_spie, // @[RocketCore.scala:134:14] output io_ptw_status_mie, // @[RocketCore.scala:134:14] output io_ptw_status_sie, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spvp, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spv, // @[RocketCore.scala:134:14] output io_ptw_hstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_debug, // @[RocketCore.scala:134:14] output io_ptw_gstatus_cease, // @[RocketCore.scala:134:14] output io_ptw_gstatus_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_gstatus_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_dprv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_prv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_v, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sd, // @[RocketCore.scala:134:14] output [22:0] io_ptw_gstatus_zero2, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mbe, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sbe, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_sxl, // @[RocketCore.scala:134:14] output [7:0] io_ptw_gstatus_zero1, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tsr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tw, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tvm, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mxr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sum, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_mpp, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_vs, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spp, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_ube, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_upie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_hie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_uie, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_0_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_0_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_1_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_1_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_2_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_2_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_3_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_3_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_4_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_4_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_5_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_5_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_6_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_6_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_7_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_7_mask, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_miss, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_hit, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_value, // @[RocketCore.scala:134:14] input io_ptw_clock_enabled, // @[RocketCore.scala:134:14] output [2:0] io_fpu_hartid, // @[RocketCore.scala:134:14] output [63:0] io_fpu_time, // @[RocketCore.scala:134:14] output [31:0] io_fpu_inst, // @[RocketCore.scala:134:14] output [63:0] io_fpu_fromint_data, // @[RocketCore.scala:134:14] output [2:0] io_fpu_fcsr_rm, // @[RocketCore.scala:134:14] input io_fpu_fcsr_flags_valid, // @[RocketCore.scala:134:14] input [4:0] io_fpu_fcsr_flags_bits, // @[RocketCore.scala:134:14] input [63:0] io_fpu_store_data, // @[RocketCore.scala:134:14] input [63:0] io_fpu_toint_data, // @[RocketCore.scala:134:14] output io_fpu_ll_resp_val, // @[RocketCore.scala:134:14] output [2:0] io_fpu_ll_resp_type, // @[RocketCore.scala:134:14] output [4:0] io_fpu_ll_resp_tag, // @[RocketCore.scala:134:14] output [63:0] io_fpu_ll_resp_data, // @[RocketCore.scala:134:14] output io_fpu_valid, // @[RocketCore.scala:134:14] input io_fpu_fcsr_rdy, // @[RocketCore.scala:134:14] input io_fpu_nack_mem, // @[RocketCore.scala:134:14] input io_fpu_illegal_rm, // @[RocketCore.scala:134:14] output io_fpu_killx, // @[RocketCore.scala:134:14] output io_fpu_killm, // @[RocketCore.scala:134:14] input io_fpu_dec_ldst, // @[RocketCore.scala:134:14] input io_fpu_dec_wen, // @[RocketCore.scala:134:14] input io_fpu_dec_ren1, // @[RocketCore.scala:134:14] input io_fpu_dec_ren2, // @[RocketCore.scala:134:14] input io_fpu_dec_ren3, // @[RocketCore.scala:134:14] input io_fpu_dec_swap12, // @[RocketCore.scala:134:14] input io_fpu_dec_swap23, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagIn, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagOut, // @[RocketCore.scala:134:14] input io_fpu_dec_fromint, // @[RocketCore.scala:134:14] input io_fpu_dec_toint, // @[RocketCore.scala:134:14] input io_fpu_dec_fastpipe, // @[RocketCore.scala:134:14] input io_fpu_dec_fma, // @[RocketCore.scala:134:14] input io_fpu_dec_div, // @[RocketCore.scala:134:14] input io_fpu_dec_sqrt, // @[RocketCore.scala:134:14] input io_fpu_dec_wflags, // @[RocketCore.scala:134:14] input io_fpu_dec_vec, // @[RocketCore.scala:134:14] input io_fpu_sboard_set, // @[RocketCore.scala:134:14] input io_fpu_sboard_clr, // @[RocketCore.scala:134:14] input [4:0] io_fpu_sboard_clra, // @[RocketCore.scala:134:14] output io_fpu_keep_clock_enabled, // @[RocketCore.scala:134:14] output io_trace_insns_0_valid, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_iaddr, // @[RocketCore.scala:134:14] output [31:0] io_trace_insns_0_insn, // @[RocketCore.scala:134:14] output [2:0] io_trace_insns_0_priv, // @[RocketCore.scala:134:14] output io_trace_insns_0_exception, // @[RocketCore.scala:134:14] output io_trace_insns_0_interrupt, // @[RocketCore.scala:134:14] output [63:0] io_trace_insns_0_cause, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_tval, // @[RocketCore.scala:134:14] output [63:0] io_trace_time, // @[RocketCore.scala:134:14] output io_bpwatch_0_valid_0, // @[RocketCore.scala:134:14] output [2:0] io_bpwatch_0_action, // @[RocketCore.scala:134:14] output io_wfi // @[RocketCore.scala:134:14] ); wire ll_arb_io_out_ready; // @[RocketCore.scala:782:23, :809:44, :810:25] wire id_ctrl_fence; // @[RocketCore.scala:321:21] wire id_ctrl_rocc; // @[RocketCore.scala:321:21] wire io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire _ll_arb_io_in_0_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_out_valid; // @[RocketCore.scala:776:22] wire [4:0] _ll_arb_io_out_bits_tag; // @[RocketCore.scala:776:22] wire _div_io_req_ready; // @[RocketCore.scala:511:19] wire _div_io_resp_valid; // @[RocketCore.scala:511:19] wire [63:0] _div_io_resp_bits_data; // @[RocketCore.scala:511:19] wire [4:0] _div_io_resp_bits_tag; // @[RocketCore.scala:511:19] wire [63:0] _alu_io_adder_out; // @[RocketCore.scala:504:19] wire _alu_io_cmp_out; // @[RocketCore.scala:504:19] wire _bpu_io_xcpt_if; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_ld; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_st; // @[RocketCore.scala:414:19] wire _bpu_io_debug_if; // @[RocketCore.scala:414:19] wire _bpu_io_debug_ld; // @[RocketCore.scala:414:19] wire _bpu_io_debug_st; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_rvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_wvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_ivalid_0; // @[RocketCore.scala:414:19] wire [63:0] _csr_io_rw_rdata; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_read_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_csr_stall; // @[RocketCore.scala:341:19] wire _csr_io_eret; // @[RocketCore.scala:341:19] wire _csr_io_singleStep; // @[RocketCore.scala:341:19] wire _csr_io_status_debug; // @[RocketCore.scala:341:19] wire _csr_io_status_cease; // @[RocketCore.scala:341:19] wire _csr_io_status_wfi; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_status_isa; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_dprv; // @[RocketCore.scala:341:19] wire _csr_io_status_dv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_prv; // @[RocketCore.scala:341:19] wire _csr_io_status_v; // @[RocketCore.scala:341:19] wire _csr_io_status_sd; // @[RocketCore.scala:341:19] wire _csr_io_status_mpv; // @[RocketCore.scala:341:19] wire _csr_io_status_gva; // @[RocketCore.scala:341:19] wire _csr_io_status_tsr; // @[RocketCore.scala:341:19] wire _csr_io_status_tw; // @[RocketCore.scala:341:19] wire _csr_io_status_tvm; // @[RocketCore.scala:341:19] wire _csr_io_status_mxr; // @[RocketCore.scala:341:19] wire _csr_io_status_sum; // @[RocketCore.scala:341:19] wire _csr_io_status_mprv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_fs; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_mpp; // @[RocketCore.scala:341:19] wire _csr_io_status_spp; // @[RocketCore.scala:341:19] wire _csr_io_status_mpie; // @[RocketCore.scala:341:19] wire _csr_io_status_spie; // @[RocketCore.scala:341:19] wire _csr_io_status_mie; // @[RocketCore.scala:341:19] wire _csr_io_status_sie; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_evec; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_time; // @[RocketCore.scala:341:19] wire _csr_io_interrupt; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_interrupt_cause; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_dmode; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_action; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_bp_0_control_tmatch; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_m; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_s; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_u; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_x; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_w; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_r; // @[RocketCore.scala:341:19] wire [38:0] _csr_io_bp_0_address; // @[RocketCore.scala:341:19] wire [47:0] _csr_io_bp_0_textra_pad2; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_textra_pad1; // @[RocketCore.scala:341:19] wire _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_valid; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_trace_0_iaddr; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_trace_0_insn; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_trace_0_priv; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_exception; // @[RocketCore.scala:341:19] wire [39:0] _ibuf_io_pc; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_cfiType; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_taken; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_mask; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bridx; // @[RocketCore.scala:311:20] wire [38:0] _ibuf_io_btb_resp_target; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_btb_resp_entry; // @[RocketCore.scala:311:20] wire [7:0] _ibuf_io_btb_resp_bht_history; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bht_value; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20] wire [2:0] io_hartid_0 = io_hartid; // @[RocketCore.scala:153:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[RocketCore.scala:153:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[RocketCore.scala:153:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[RocketCore.scala:153:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[RocketCore.scala:153:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[RocketCore.scala:153:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_cfiType_0 = io_imem_resp_bits_btb_cfiType; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_taken_0 = io_imem_resp_bits_btb_taken; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_mask_0 = io_imem_resp_bits_btb_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bridx_0 = io_imem_resp_bits_btb_bridx; // @[RocketCore.scala:153:7] wire [38:0] io_imem_resp_bits_btb_target_0 = io_imem_resp_bits_btb_target; // @[RocketCore.scala:153:7] wire [4:0] io_imem_resp_bits_btb_entry_0 = io_imem_resp_bits_btb_entry; // @[RocketCore.scala:153:7] wire [7:0] io_imem_resp_bits_btb_bht_history_0 = io_imem_resp_bits_btb_bht_history; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bht_value_0 = io_imem_resp_bits_btb_bht_value; // @[RocketCore.scala:153:7] wire [39:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[RocketCore.scala:153:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_mask_0 = io_imem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_pf_inst_0 = io_imem_resp_bits_xcpt_pf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_gf_inst_0 = io_imem_resp_bits_xcpt_gf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_ae_inst_0 = io_imem_resp_bits_xcpt_ae_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_replay_0 = io_imem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_imem_gpa_valid_0 = io_imem_gpa_valid; // @[RocketCore.scala:153:7] wire [39:0] io_imem_gpa_bits_0 = io_imem_gpa_bits; // @[RocketCore.scala:153:7] wire io_imem_gpa_is_pte_0 = io_imem_gpa_is_pte; // @[RocketCore.scala:153:7] wire [39:0] io_imem_npc_0 = io_imem_npc; // @[RocketCore.scala:153:7] wire io_imem_perf_acquire_0 = io_imem_perf_acquire; // @[RocketCore.scala:153:7] wire io_imem_perf_tlbMiss_0 = io_imem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_0 = io_dmem_s2_nack; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_cause_raw_0 = io_dmem_s2_nack_cause_raw; // @[RocketCore.scala:153:7] wire io_dmem_s2_uncached_0 = io_dmem_s2_uncached; // @[RocketCore.scala:153:7] wire [31:0] io_dmem_s2_paddr_0 = io_dmem_s2_paddr; // @[RocketCore.scala:153:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_resp_bits_addr_0 = io_dmem_resp_bits_addr; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_resp_bits_tag_0 = io_dmem_resp_bits_tag; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_resp_bits_cmd_0 = io_dmem_resp_bits_cmd; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_size_0 = io_dmem_resp_bits_size; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_signed_0 = io_dmem_resp_bits_signed; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_dprv_0 = io_dmem_resp_bits_dprv; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_dv_0 = io_dmem_resp_bits_dv; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_resp_bits_mask_0 = io_dmem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_replay_0 = io_dmem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_has_data_0 = io_dmem_resp_bits_has_data; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_word_bypass_0 = io_dmem_resp_bits_data_word_bypass; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_raw_0 = io_dmem_resp_bits_data_raw; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_store_data_0 = io_dmem_resp_bits_store_data; // @[RocketCore.scala:153:7] wire io_dmem_replay_next_0 = io_dmem_replay_next; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_ld_0 = io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_st_0 = io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_ld_0 = io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_st_0 = io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_ld_0 = io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_st_0 = io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_s2_gpa_0 = io_dmem_s2_gpa; // @[RocketCore.scala:153:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[RocketCore.scala:153:7] wire io_dmem_store_pending_0 = io_dmem_store_pending; // @[RocketCore.scala:153:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[RocketCore.scala:153:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[RocketCore.scala:153:7] wire io_dmem_perf_grant_0 = io_dmem_perf_grant; // @[RocketCore.scala:153:7] wire io_dmem_perf_tlbMiss_0 = io_dmem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_perf_blocked_0 = io_dmem_perf_blocked; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenLoad_0 = io_dmem_perf_canAcceptStoreThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenRMW_0 = io_dmem_perf_canAcceptStoreThenRMW; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptLoadThenLoad_0 = io_dmem_perf_canAcceptLoadThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterLoad_0 = io_dmem_perf_storeBufferEmptyAfterLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterStore_0 = io_dmem_perf_storeBufferEmptyAfterStore; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[RocketCore.scala:153:7] wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_flags_valid_0 = io_fpu_fcsr_flags_valid; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_fcsr_flags_bits_0 = io_fpu_fcsr_flags_bits; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_store_data_0 = io_fpu_store_data; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_toint_data_0 = io_fpu_toint_data; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_rdy_0 = io_fpu_fcsr_rdy; // @[RocketCore.scala:153:7] wire io_fpu_nack_mem_0 = io_fpu_nack_mem; // @[RocketCore.scala:153:7] wire io_fpu_illegal_rm_0 = io_fpu_illegal_rm; // @[RocketCore.scala:153:7] wire io_fpu_dec_ldst_0 = io_fpu_dec_ldst; // @[RocketCore.scala:153:7] wire io_fpu_dec_wen_0 = io_fpu_dec_wen; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren1_0 = io_fpu_dec_ren1; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren2_0 = io_fpu_dec_ren2; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren3_0 = io_fpu_dec_ren3; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap12_0 = io_fpu_dec_swap12; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap23_0 = io_fpu_dec_swap23; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagIn_0 = io_fpu_dec_typeTagIn; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagOut_0 = io_fpu_dec_typeTagOut; // @[RocketCore.scala:153:7] wire io_fpu_dec_fromint_0 = io_fpu_dec_fromint; // @[RocketCore.scala:153:7] wire io_fpu_dec_toint_0 = io_fpu_dec_toint; // @[RocketCore.scala:153:7] wire io_fpu_dec_fastpipe_0 = io_fpu_dec_fastpipe; // @[RocketCore.scala:153:7] wire io_fpu_dec_fma_0 = io_fpu_dec_fma; // @[RocketCore.scala:153:7] wire io_fpu_dec_div_0 = io_fpu_dec_div; // @[RocketCore.scala:153:7] wire io_fpu_dec_sqrt_0 = io_fpu_dec_sqrt; // @[RocketCore.scala:153:7] wire io_fpu_dec_wflags_0 = io_fpu_dec_wflags; // @[RocketCore.scala:153:7] wire io_fpu_dec_vec_0 = io_fpu_dec_vec; // @[RocketCore.scala:153:7] wire io_fpu_sboard_set_0 = io_fpu_sboard_set; // @[RocketCore.scala:153:7] wire io_fpu_sboard_clr_0 = io_fpu_sboard_clr; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_sboard_clra_0 = io_fpu_sboard_clra; // @[RocketCore.scala:153:7] wire coreMonitorBundle_clock = clock; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_reset = reset; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_clock = clock; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_reset = reset; // @[RocketCore.scala:1249:28] wire io_imem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire io_dmem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire clock_en = 1'h1; // @[RocketCore.scala:153:7, :163:29] wire _id_npc_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _id_npc_b11_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _id_illegal_insn_T_10 = 1'h1; // @[RocketCore.scala:153:7, :384:73] wire _id_illegal_insn_T_15 = 1'h1; // @[RocketCore.scala:153:7, :385:55] wire _mem_br_target_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b19_12_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1343:43] wire _mem_br_target_b19_12_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1343:36] wire _mem_br_target_b11_T_6 = 1'h1; // @[RocketCore.scala:153:7, :1346:23] wire _mem_br_target_b4_1_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1349:41] wire _mem_br_target_b4_1_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1349:34] wire _mem_br_target_b19_12_T_5 = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b11_T_14 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _wb_reg_xcpt_T_2 = 1'h1; // @[RocketCore.scala:153:7, :707:45] wire _replay_wb_rocc_T_1 = 1'h1; // @[RocketCore.scala:153:7, :758:56] wire _rocc_blocked_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1029:31] wire io_imem_btb_update_bits_taken = 1'h0; // @[RocketCore.scala:153:7] wire io_imem_ras_update_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtw = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_hu = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2miss = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2hit = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s1_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_uncached = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_replay = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_replay_next = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_ordered = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_store_pending = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_acquire = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_release = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_grant = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_blocked = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_busy = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_interrupt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_exception = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_rvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_wvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_ivalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_cease = 1'h0; // @[RocketCore.scala:153:7] wire io_traceStall = 1'h0; // @[RocketCore.scala:153:7] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_10 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_11 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_12 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_13 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_14 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_15 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_16 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_17 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire hits_1 = 1'h0; // @[Events.scala:13:25] wire hits_2 = 1'h0; // @[Events.scala:13:25] wire hits_3 = 1'h0; // @[Events.scala:13:25] wire hits_4 = 1'h0; // @[Events.scala:13:25] wire hits_5 = 1'h0; // @[Events.scala:13:25] wire hits_6 = 1'h0; // @[Events.scala:13:25] wire hits_7 = 1'h0; // @[Events.scala:13:25] wire hits_8 = 1'h0; // @[Events.scala:13:25] wire hits_9 = 1'h0; // @[Events.scala:13:25] wire hits_10 = 1'h0; // @[Events.scala:13:25] wire hits_11 = 1'h0; // @[Events.scala:13:25] wire hits_12 = 1'h0; // @[Events.scala:13:25] wire hits_13 = 1'h0; // @[Events.scala:13:25] wire hits_14 = 1'h0; // @[Events.scala:13:25] wire hits_15 = 1'h0; // @[Events.scala:13:25] wire hits_16 = 1'h0; // @[Events.scala:13:25] wire hits_17 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_10 = 1'h0; // @[Events.scala:13:33] wire hits_1_0 = 1'h0; // @[Events.scala:13:25] wire hits_1_1 = 1'h0; // @[Events.scala:13:25] wire hits_1_2 = 1'h0; // @[Events.scala:13:25] wire hits_1_3 = 1'h0; // @[Events.scala:13:25] wire hits_1_4 = 1'h0; // @[Events.scala:13:25] wire hits_1_5 = 1'h0; // @[Events.scala:13:25] wire hits_1_6 = 1'h0; // @[Events.scala:13:25] wire hits_1_7 = 1'h0; // @[Events.scala:13:25] wire hits_1_8 = 1'h0; // @[Events.scala:13:25] wire hits_1_9 = 1'h0; // @[Events.scala:13:25] wire hits_1_10 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33] wire hits_2_0 = 1'h0; // @[Events.scala:13:25] wire hits_2_1 = 1'h0; // @[Events.scala:13:25] wire hits_2_2 = 1'h0; // @[Events.scala:13:25] wire hits_2_3 = 1'h0; // @[Events.scala:13:25] wire hits_2_4 = 1'h0; // @[Events.scala:13:25] wire hits_2_5 = 1'h0; // @[Events.scala:13:25] wire id_ctrl_vec = 1'h0; // @[RocketCore.scala:321:21] wire _id_rs_T_1 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_rs_T_6 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_npc_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _id_npc_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _id_npc_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43] wire _id_npc_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36] wire _id_npc_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _id_npc_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _id_npc_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _id_npc_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23] wire _id_npc_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _id_npc_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _id_npc_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _id_npc_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _id_npc_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _id_npc_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41] wire _id_npc_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34] wire _id_npc_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _id_npc_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _id_npc_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _id_npc_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _id_npc_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _id_npc_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire id_npc_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire id_set_vconfig = 1'h0; // @[RocketCore.scala:347:120] wire _id_illegal_insn_T_16 = 1'h0; // @[RocketCore.scala:385:19] wire _id_illegal_insn_T_26 = 1'h0; // @[RocketCore.scala:388:23] wire _id_illegal_insn_T_28 = 1'h0; // @[RocketCore.scala:389:23] wire _id_illegal_insn_T_30 = 1'h0; // @[RocketCore.scala:390:22] wire id_rocc_busy = 1'h0; // @[RocketCore.scala:405:34] wire _id_csr_rocc_write_T = 1'h0; // @[RocketCore.scala:408:87] wire id_csr_rocc_write = 1'h0; // @[RocketCore.scala:408:100] wire _id_do_fence_T_1 = 1'h0; // @[RocketCore.scala:410:46] wire _id_do_fence_T_2 = 1'h0; // @[RocketCore.scala:411:17] wire _id_do_fence_T_3 = 1'h0; // @[RocketCore.scala:410:86] wire _ex_reg_hls_T = 1'h0; // @[RocketCore.scala:553:37] wire _ex_reg_hls_T_6 = 1'h0; // @[RocketCore.scala:553:55] wire _ex_reg_mem_size_T = 1'h0; // @[RocketCore.scala:554:46] wire _ex_reg_set_vconfig_T_1 = 1'h0; // @[RocketCore.scala:591:42] wire _replay_ex_structural_T_5 = 1'h0; // @[RocketCore.scala:599:45] wire _replay_ex_structural_T_6 = 1'h0; // @[RocketCore.scala:599:42] wire _mem_br_target_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23] wire _mem_br_target_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _mem_br_target_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b19_12_T_6 = 1'h0; // @[RocketCore.scala:1343:43] wire _mem_br_target_b19_12_T_7 = 1'h0; // @[RocketCore.scala:1343:36] wire _mem_br_target_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_17 = 1'h0; // @[RocketCore.scala:1346:23] wire _mem_br_target_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_12 = 1'h0; // @[RocketCore.scala:1349:41] wire _mem_br_target_b4_1_T_13 = 1'h0; // @[RocketCore.scala:1349:34] wire _mem_br_target_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0_1 = 1'h0; // @[RocketCore.scala:1351:17] wire vec_kill_mem = 1'h0; // @[RocketCore.scala:697:52] wire vec_kill_all = 1'h0; // @[RocketCore.scala:698:36] wire replay_wb_csr = 1'h0; // @[RocketCore.scala:759:42] wire replay_wb_vec = 1'h0; // @[RocketCore.scala:760:36] wire _htval_valid_dmem_T_2 = 1'h0; // @[RocketCore.scala:857:83] wire _htval_valid_dmem_T_3 = 1'h0; // @[RocketCore.scala:857:54] wire htval_valid_dmem = 1'h0; // @[RocketCore.scala:857:87] wire _mhtinst_read_pseudo_T_1 = 1'h0; // @[RocketCore.scala:862:98] wire _id_vconfig_hazard_T = 1'h0; // @[RocketCore.scala:1003:19] wire id_vconfig_hazard = 1'h0; // @[RocketCore.scala:1002:39] wire _ctrl_stalld_T_12 = 1'h0; // @[RocketCore.scala:1036:15] wire _ctrl_stalld_T_13 = 1'h0; // @[RocketCore.scala:1036:46] wire _ctrl_stalld_T_28 = 1'h0; // @[RocketCore.scala:1041:5] wire _io_rocc_exception_T = 1'h0; // @[RocketCore.scala:1157:52] wire _io_rocc_exception_T_1 = 1'h0; // @[RocketCore.scala:1157:32] wire _io_cease_T = 1'h0; // @[RocketCore.scala:1166:38] wire _io_cease_T_1 = 1'h0; // @[RocketCore.scala:1166:35] wire coreMonitorBundle_wrenf = 1'h0; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_excpt = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_valid = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_wrenf = 1'h0; // @[RocketCore.scala:1249:28] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_ras_update_bits_cfiType = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] _htval_valid_dmem_T_1 = 2'h0; // @[RocketCore.scala:857:76] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[RocketCore.scala:153:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[RocketCore.scala:153:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[RocketCore.scala:153:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] _csr_io_fcsr_flags_bits_T_2 = 5'h0; // @[RocketCore.scala:839:116] wire [4:0] _csr_io_fcsr_flags_bits_T_3 = 5'h0; // @[RocketCore.scala:839:110] wire [4:0] xrfWriteBundle_rd0src = 5'h0; // @[RocketCore.scala:1249:28] wire [4:0] xrfWriteBundle_rd1src = 5'h0; // @[RocketCore.scala:1249:28] wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] htval_dmem = 40'h0; // @[RocketCore.scala:858:25] wire [31:0] io_reset_vector = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] xrfWriteBundle_inst = 32'h0; // @[RocketCore.scala:1249:28] wire [38:0] io_imem_ras_update_bits_returnAddr = 39'h0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] xrfWriteBundle_pc = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd0val = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd1val = 64'h0; // @[RocketCore.scala:1249:28] wire [1:0] io_ptw_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_v_sew = 3'h0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_hartid_0 = io_hartid_0; // @[RocketCore.scala:153:7] wire take_pc_mem_wb; // @[RocketCore.scala:307:35] wire [39:0] _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:1051:8] wire _io_imem_req_bits_speculative_T; // @[RocketCore.scala:1049:35] wire _io_imem_sfence_valid_T; // @[RocketCore.scala:1060:40] wire io_ptw_sfence_valid_0 = io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:1061:45] wire io_ptw_sfence_bits_rs1_0 = io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:1062:45] wire io_ptw_sfence_bits_rs2_0 = io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire [38:0] io_ptw_sfence_bits_addr_0 = io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_asid_0 = io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hv_0 = io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hg_0 = io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:1071:77] wire [38:0] _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:1080:33] wire [38:0] io_imem_bht_update_bits_pc_0 = io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire mem_cfi; // @[RocketCore.scala:625:50] wire [1:0] _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:1074:8] wire _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:1084:45] wire mem_wrong_npc; // @[RocketCore.scala:621:8] wire _io_imem_flush_icache_T_2; // @[RocketCore.scala:1054:59] wire _io_dmem_req_valid_T; // @[RocketCore.scala:1130:41] wire [39:0] _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:1295:8] wire _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:1136:30] wire [1:0] _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:1140:31] wire _io_dmem_req_bits_dv_T; // @[RocketCore.scala:1141:37] wire _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:1142:56] wire _io_dmem_s1_kill_T_2; // @[RocketCore.scala:1151:68] wire [63:0] _io_dmem_s1_data_data_T; // @[RocketCore.scala:1148:63] wire [63:0] io_fpu_ll_resp_data_0 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7] wire [63:0] _rf_wdata_T_1 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7, :819:78] wire [63:0] dcache_bypass_data = io_dmem_resp_bits_data_word_bypass_0; // @[RocketCore.scala:153:7, :449:62] wire _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:1154:70] wire [63:0] ex_rs_0; // @[RocketCore.scala:469:14] wire _csr_io_fcsr_flags_valid_T = io_fpu_fcsr_flags_valid_0; // @[RocketCore.scala:153:7, :838:54] wire _io_fpu_ll_resp_val_T; // @[RocketCore.scala:1099:41] wire [4:0] dmem_resp_waddr; // @[RocketCore.scala:767:46] wire _io_fpu_valid_T_1; // @[RocketCore.scala:1094:31] wire _id_illegal_insn_T_11 = io_fpu_illegal_rm_0; // @[RocketCore.scala:153:7, :384:70] wire ctrl_killx; // @[RocketCore.scala:602:48] wire killm_common; // @[RocketCore.scala:700:68] wire _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] wire _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:1156:53] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:1159:48] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:1159:48] wire [39:0] io_imem_req_bits_pc_0; // @[RocketCore.scala:153:7] wire io_imem_req_bits_speculative_0; // @[RocketCore.scala:153:7] wire io_imem_req_valid_0; // @[RocketCore.scala:153:7] wire io_imem_resp_ready_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_btb_update_bits_prediction_bht_history_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bht_value_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_taken_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_mask_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bridx_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_prediction_target_0; // @[RocketCore.scala:153:7] wire [4:0] io_imem_btb_update_bits_prediction_entry_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_target_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_isValid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_valid_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_bht_update_bits_prediction_history_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_prediction_value_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_branch_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_taken_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_mispredict_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_valid_0; // @[RocketCore.scala:153:7] wire io_imem_might_request_0; // @[RocketCore.scala:153:7] wire io_imem_flush_icache_0; // @[RocketCore.scala:153:7] wire io_imem_progress_0; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_req_bits_addr_0; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_req_bits_tag_0; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_req_bits_cmd_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_size_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_signed_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_dprv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_dv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_resp_0; // @[RocketCore.scala:153:7] wire io_dmem_req_valid_0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_s1_data_data_0; // @[RocketCore.scala:153:7] wire io_dmem_s1_kill_0; // @[RocketCore.scala:153:7] wire io_dmem_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_ptbr_mode_0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_ptbr_ppn_0; // @[RocketCore.scala:153:7] wire io_ptw_status_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_status_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_status_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_status_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_v_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_mpp_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spvp_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spv_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_gstatus_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_v_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd_0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_gstatus_zero2_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mbe_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sbe_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_sxl_0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_gstatus_zero1_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_mpp_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_vs_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_ube_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_upie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_hie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_uie_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_0_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_0_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_1_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_1_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_2_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_2_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_3_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_3_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_4_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_4_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_5_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_5_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_6_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_6_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_7_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_7_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_time_0; // @[RocketCore.scala:153:7] wire [31:0] io_fpu_inst_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_fromint_data_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_fcsr_rm_0; // @[RocketCore.scala:153:7] wire io_fpu_ll_resp_val_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_ll_resp_type_0; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7] wire io_fpu_valid_0; // @[RocketCore.scala:153:7] wire io_fpu_killx_0; // @[RocketCore.scala:153:7] wire io_fpu_killm_0; // @[RocketCore.scala:153:7] wire io_fpu_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_funct; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rd; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_opcode; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_debug; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_cease; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_wfi; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_cmd_bits_status_isa; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_dprv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_dv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_prv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_v; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_gva; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tsr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tw; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tvm; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mxr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sum; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mprv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_fs; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_mpp; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spp; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sie; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs1; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs2; // @[RocketCore.scala:153:7] wire io_rocc_cmd_valid; // @[RocketCore.scala:153:7] wire io_trace_insns_0_valid_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_iaddr_0; // @[RocketCore.scala:153:7] wire [31:0] io_trace_insns_0_insn_0; // @[RocketCore.scala:153:7] wire [2:0] io_trace_insns_0_priv_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_exception_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_interrupt_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_insns_0_cause_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_tval_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_time_0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_valid_0_0; // @[RocketCore.scala:153:7] wire [2:0] io_bpwatch_0_action_0; // @[RocketCore.scala:153:7] wire io_wfi_0; // @[RocketCore.scala:153:7] reg id_reg_pause; // @[RocketCore.scala:161:25] reg imem_might_request_reg; // @[RocketCore.scala:162:35] assign io_imem_might_request_0 = imem_might_request_reg; // @[RocketCore.scala:153:7, :162:35] reg ex_ctrl_legal; // @[RocketCore.scala:243:20] reg ex_ctrl_fp; // @[RocketCore.scala:243:20] reg ex_ctrl_rocc; // @[RocketCore.scala:243:20] reg ex_ctrl_branch; // @[RocketCore.scala:243:20] reg ex_ctrl_jal; // @[RocketCore.scala:243:20] reg ex_ctrl_jalr; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_alu2; // @[RocketCore.scala:243:20] reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala:243:20] reg ex_ctrl_alu_dw; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_alu_fn; // @[RocketCore.scala:243:20] reg ex_ctrl_mem; // @[RocketCore.scala:243:20] wire _ex_sfence_T = ex_ctrl_mem; // @[RocketCore.scala:243:20, :605:29] reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala:243:20] assign io_dmem_req_bits_cmd_0 = ex_ctrl_mem_cmd; // @[RocketCore.scala:153:7, :243:20] reg ex_ctrl_rfs1; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs3; // @[RocketCore.scala:243:20] reg ex_ctrl_wfd; // @[RocketCore.scala:243:20] reg ex_ctrl_mul; // @[RocketCore.scala:243:20] reg ex_ctrl_div; // @[RocketCore.scala:243:20] reg ex_ctrl_wxd; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_csr; // @[RocketCore.scala:243:20] reg ex_ctrl_fence_i; // @[RocketCore.scala:243:20] reg ex_ctrl_fence; // @[RocketCore.scala:243:20] reg ex_ctrl_amo; // @[RocketCore.scala:243:20] reg ex_ctrl_dp; // @[RocketCore.scala:243:20] reg mem_ctrl_legal; // @[RocketCore.scala:244:21] reg mem_ctrl_fp; // @[RocketCore.scala:244:21] reg mem_ctrl_rocc; // @[RocketCore.scala:244:21] reg mem_ctrl_branch; // @[RocketCore.scala:244:21] assign io_imem_bht_update_bits_branch_0 = mem_ctrl_branch; // @[RocketCore.scala:153:7, :244:21] reg mem_ctrl_jal; // @[RocketCore.scala:244:21] reg mem_ctrl_jalr; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_alu2; // @[RocketCore.scala:244:21] reg [1:0] mem_ctrl_sel_alu1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_imm; // @[RocketCore.scala:244:21] reg mem_ctrl_alu_dw; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_alu_fn; // @[RocketCore.scala:244:21] reg mem_ctrl_mem; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_mem_cmd; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs1; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs3; // @[RocketCore.scala:244:21] reg mem_ctrl_wfd; // @[RocketCore.scala:244:21] reg mem_ctrl_mul; // @[RocketCore.scala:244:21] reg mem_ctrl_div; // @[RocketCore.scala:244:21] reg mem_ctrl_wxd; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_csr; // @[RocketCore.scala:244:21] reg mem_ctrl_fence_i; // @[RocketCore.scala:244:21] reg mem_ctrl_fence; // @[RocketCore.scala:244:21] reg mem_ctrl_amo; // @[RocketCore.scala:244:21] reg mem_ctrl_dp; // @[RocketCore.scala:244:21] reg mem_ctrl_vec; // @[RocketCore.scala:244:21] reg wb_ctrl_legal; // @[RocketCore.scala:245:20] reg wb_ctrl_fp; // @[RocketCore.scala:245:20] reg wb_ctrl_rocc; // @[RocketCore.scala:245:20] reg wb_ctrl_branch; // @[RocketCore.scala:245:20] reg wb_ctrl_jal; // @[RocketCore.scala:245:20] reg wb_ctrl_jalr; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_alu2; // @[RocketCore.scala:245:20] reg [1:0] wb_ctrl_sel_alu1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_imm; // @[RocketCore.scala:245:20] reg wb_ctrl_alu_dw; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_alu_fn; // @[RocketCore.scala:245:20] reg wb_ctrl_mem; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_mem_cmd; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs1; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs3; // @[RocketCore.scala:245:20] reg wb_ctrl_wfd; // @[RocketCore.scala:245:20] reg wb_ctrl_mul; // @[RocketCore.scala:245:20] reg wb_ctrl_div; // @[RocketCore.scala:245:20] reg wb_ctrl_wxd; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_csr; // @[RocketCore.scala:245:20] reg wb_ctrl_fence_i; // @[RocketCore.scala:245:20] reg wb_ctrl_fence; // @[RocketCore.scala:245:20] reg wb_ctrl_amo; // @[RocketCore.scala:245:20] reg wb_ctrl_dp; // @[RocketCore.scala:245:20] reg wb_ctrl_vec; // @[RocketCore.scala:245:20] reg ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35] reg ex_reg_valid; // @[RocketCore.scala:248:35] reg ex_reg_rvc; // @[RocketCore.scala:249:35] reg [1:0] ex_reg_btb_resp_cfiType; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_taken; // @[RocketCore.scala:250:35] reg [1:0] ex_reg_btb_resp_mask; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bridx; // @[RocketCore.scala:250:35] reg [38:0] ex_reg_btb_resp_target; // @[RocketCore.scala:250:35] reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala:250:35] reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bht_value; // @[RocketCore.scala:250:35] reg ex_reg_xcpt; // @[RocketCore.scala:251:35] reg ex_reg_flush_pipe; // @[RocketCore.scala:252:35] reg ex_reg_load_use; // @[RocketCore.scala:253:35] reg [63:0] ex_reg_cause; // @[RocketCore.scala:254:35] wire [63:0] ex_cause = ex_reg_cause; // @[RocketCore.scala:254:35, :1278:50] reg ex_reg_replay; // @[RocketCore.scala:255:26] reg [39:0] ex_reg_pc; // @[RocketCore.scala:256:22] wire [39:0] _ex_op1_T_1 = ex_reg_pc; // @[RocketCore.scala:256:22, :474:24] reg [1:0] ex_reg_mem_size; // @[RocketCore.scala:257:28] assign io_dmem_req_bits_size_0 = ex_reg_mem_size; // @[RocketCore.scala:153:7, :257:28] reg [31:0] ex_reg_inst; // @[RocketCore.scala:259:24] reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala:260:28] reg ex_reg_wphit_0; // @[RocketCore.scala:261:36] reg mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36] reg mem_reg_valid; // @[RocketCore.scala:265:36] reg mem_reg_rvc; // @[RocketCore.scala:266:36] reg [1:0] mem_reg_btb_resp_cfiType; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_cfiType_0 = mem_reg_btb_resp_cfiType; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_taken_0 = mem_reg_btb_resp_taken; // @[RocketCore.scala:153:7, :267:36] wire _mem_direction_misprediction_T = mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36, :627:85] reg [1:0] mem_reg_btb_resp_mask; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_mask_0 = mem_reg_btb_resp_mask; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bridx; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bridx_0 = mem_reg_btb_resp_bridx; // @[RocketCore.scala:153:7, :267:36] reg [38:0] mem_reg_btb_resp_target; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_target_0 = mem_reg_btb_resp_target; // @[RocketCore.scala:153:7, :267:36] reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_entry_0 = mem_reg_btb_resp_entry; // @[RocketCore.scala:153:7, :267:36] reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bht_value; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_xcpt; // @[RocketCore.scala:268:36] reg mem_reg_replay; // @[RocketCore.scala:269:36] reg mem_reg_flush_pipe; // @[RocketCore.scala:270:36] reg [63:0] mem_reg_cause; // @[RocketCore.scala:271:36] reg mem_reg_slow_bypass; // @[RocketCore.scala:272:36] wire mem_mem_cmd_bh = mem_reg_slow_bypass; // @[RocketCore.scala:272:36, :995:41] reg mem_reg_load; // @[RocketCore.scala:273:36] reg mem_reg_store; // @[RocketCore.scala:274:36] reg mem_reg_set_vconfig; // @[RocketCore.scala:275:36] reg mem_reg_sfence; // @[RocketCore.scala:276:27] reg [39:0] mem_reg_pc; // @[RocketCore.scala:277:23] wire [39:0] _mem_br_target_T = mem_reg_pc; // @[RocketCore.scala:277:23, :615:34] reg [31:0] mem_reg_inst; // @[RocketCore.scala:278:25] reg [1:0] mem_reg_mem_size; // @[RocketCore.scala:279:29] reg mem_reg_hls_or_dv; // @[RocketCore.scala:280:30] reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala:281:29] reg [63:0] mem_reg_wdata; // @[RocketCore.scala:282:26] wire [63:0] _mem_int_wdata_T_3 = mem_reg_wdata; // @[RocketCore.scala:282:26, :624:111] reg [63:0] mem_reg_rs2; // @[RocketCore.scala:283:24] reg mem_br_taken; // @[RocketCore.scala:284:25] assign io_imem_bht_update_bits_taken_0 = mem_br_taken; // @[RocketCore.scala:153:7, :284:25] wire _take_pc_mem_T_3; // @[RocketCore.scala:629:49] wire take_pc_mem; // @[RocketCore.scala:285:25] reg mem_reg_wphit_0; // @[RocketCore.scala:286:35] reg wb_reg_valid; // @[RocketCore.scala:288:35] reg wb_reg_xcpt; // @[RocketCore.scala:289:35] reg wb_reg_replay; // @[RocketCore.scala:290:35] reg wb_reg_flush_pipe; // @[RocketCore.scala:291:35] reg [63:0] wb_reg_cause; // @[RocketCore.scala:292:35] reg wb_reg_set_vconfig; // @[RocketCore.scala:293:35] reg wb_reg_sfence; // @[RocketCore.scala:294:26] reg [39:0] wb_reg_pc; // @[RocketCore.scala:295:22] reg [1:0] wb_reg_mem_size; // @[RocketCore.scala:296:28] reg wb_reg_hls_or_dv; // @[RocketCore.scala:297:29] reg wb_reg_hfence_v; // @[RocketCore.scala:298:28] assign io_imem_sfence_bits_hv_0 = wb_reg_hfence_v; // @[RocketCore.scala:153:7, :298:28] reg wb_reg_hfence_g; // @[RocketCore.scala:299:28] assign io_imem_sfence_bits_hg_0 = wb_reg_hfence_g; // @[RocketCore.scala:153:7, :299:28] reg [31:0] wb_reg_inst; // @[RocketCore.scala:300:24] wire [31:0] _io_rocc_cmd_bits_inst_WIRE_1 = wb_reg_inst; // @[RocketCore.scala:300:24, :1159:48] reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala:301:28] reg [63:0] wb_reg_wdata; // @[RocketCore.scala:302:25] assign io_rocc_cmd_bits_rs1 = wb_reg_wdata; // @[RocketCore.scala:153:7, :302:25] wire [63:0] _rf_wdata_T_3 = wb_reg_wdata; // @[RocketCore.scala:302:25, :822:21] reg [63:0] wb_reg_rs2; // @[RocketCore.scala:303:23] assign io_rocc_cmd_bits_rs2 = wb_reg_rs2; // @[RocketCore.scala:153:7, :303:23] wire _take_pc_wb_T_2; // @[RocketCore.scala:762:53] wire take_pc_wb; // @[RocketCore.scala:304:24] reg wb_reg_wphit_0; // @[RocketCore.scala:305:35] assign io_bpwatch_0_valid_0_0 = wb_reg_wphit_0; // @[RocketCore.scala:153:7, :305:35] assign take_pc_mem_wb = take_pc_wb \| take_pc_mem; // @[RocketCore.scala:285:25, :304:24, :307:35] assign io_imem_req_valid_0 = take_pc_mem_wb; // @[RocketCore.scala:153:7, :307:35] wire id_ctrl_decoder_0; // @[Decode.scala:50:77] wire id_ctrl_decoder_1; // @[Decode.scala:50:77] wire id_ctrl_decoder_2; // @[Decode.scala:50:77] wire id_ctrl_decoder_3; // @[Decode.scala:50:77] wire _id_illegal_insn_T_32 = id_ctrl_rocc; // @[RocketCore.scala:321:21, :391:18] wire id_ctrl_decoder_4; // @[Decode.scala:50:77] wire id_ctrl_decoder_5; // @[Decode.scala:50:77] wire id_ctrl_decoder_6; // @[Decode.scala:50:77] wire id_ctrl_decoder_7; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_8; // @[Decode.scala:50:77] wire [1:0] id_ctrl_decoder_9; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_10; // @[Decode.scala:50:77] wire id_ctrl_decoder_11; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_12; // @[Decode.scala:50:77] wire id_ctrl_decoder_13; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_14; // @[Decode.scala:50:77] wire id_ctrl_decoder_15; // @[Decode.scala:50:77] wire id_ctrl_decoder_16; // @[Decode.scala:50:77] wire id_ctrl_decoder_17; // @[Decode.scala:50:77] wire id_ctrl_decoder_18; // @[Decode.scala:50:77] wire id_ctrl_decoder_19; // @[Decode.scala:50:77] wire id_ctrl_decoder_20; // @[Decode.scala:50:77] wire id_ctrl_decoder_21; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_22; // @[Decode.scala:50:77] wire id_ctrl_decoder_23; // @[Decode.scala:50:77] wire id_ctrl_decoder_24; // @[Decode.scala:50:77] wire id_ctrl_decoder_25; // @[Decode.scala:50:77] wire _id_do_fence_T = id_ctrl_fence; // @[RocketCore.scala:321:21, :410:64] wire id_ctrl_decoder_26; // @[Decode.scala:50:77] wire id_ctrl_legal; // @[RocketCore.scala:321:21] wire id_ctrl_fp; // @[RocketCore.scala:321:21] wire id_ctrl_branch; // @[RocketCore.scala:321:21] wire id_ctrl_jal; // @[RocketCore.scala:321:21] wire id_ctrl_jalr; // @[RocketCore.scala:321:21] wire id_ctrl_rxs2; // @[RocketCore.scala:321:21] wire id_ctrl_rxs1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_alu2; // @[RocketCore.scala:321:21] wire [1:0] id_ctrl_sel_alu1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_imm; // @[RocketCore.scala:321:21] wire id_ctrl_alu_dw; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_alu_fn; // @[RocketCore.scala:321:21] wire id_ctrl_mem; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_mem_cmd; // @[RocketCore.scala:321:21] wire id_ctrl_rfs1; // @[RocketCore.scala:321:21] wire id_ctrl_rfs2; // @[RocketCore.scala:321:21] wire id_ctrl_rfs3; // @[RocketCore.scala:321:21] wire id_ctrl_wfd; // @[RocketCore.scala:321:21] wire id_ctrl_mul; // @[RocketCore.scala:321:21] wire id_ctrl_div; // @[RocketCore.scala:321:21] wire id_ctrl_wxd; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_csr; // @[RocketCore.scala:321:21] wire id_ctrl_fence_i; // @[RocketCore.scala:321:21] wire id_ctrl_amo; // @[RocketCore.scala:321:21] wire id_ctrl_dp; // @[RocketCore.scala:321:21] wire [31:0] id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22] wire [31:0] id_ctrl_decoder_decoded_invInputs = ~id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [41:0] id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [41:0] id_ctrl_decoder_decoded; // @[pla.scala:81:23] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T = {id_ctrl_decoder_decoded_andMatrixOutputs_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_99_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_102_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_9_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_29_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_139_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_117_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_4 = id_ctrl_decoder_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_96_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_35_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_182_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_128_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_67_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_78_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_190_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_7_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_98_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_32_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_71_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_181_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_16 = id_ctrl_decoder_decoded_andMatrixOutputs_181_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_145_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_143_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_20_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_22_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_97_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_39_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_131_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_191_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_63 = id_ctrl_decoder_decoded_andMatrixOutputs_191_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_164_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_64 = id_ctrl_decoder_decoded_andMatrixOutputs_164_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_55_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_90_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_30_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_26_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_175_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_77_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_21_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_5 = id_ctrl_decoder_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_121_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_61_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_105_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_24_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_165_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_160_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_95_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_56_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_16_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_185_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_6 = id_ctrl_decoder_decoded_andMatrixOutputs_185_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_140_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_53_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_193_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_92_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_17_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_129_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_177_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_123_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_14_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_27 = id_ctrl_decoder_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_132_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_49_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_155_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_7 = id_ctrl_decoder_decoded_andMatrixOutputs_155_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_184_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_148_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_115_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_162_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_44_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_126_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_150_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_161_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_133_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_179_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_5_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_88_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_94_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_66_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_125_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_91_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_112_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_170_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_146_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_168_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_2_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_15_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_176_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_172_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_76_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_87_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_144_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_36_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_41_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_8_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_104_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_73_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_189_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_28_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_0_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_60_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_48_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_167_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_163_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_137_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_74_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_59_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_152_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_47_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_103_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_83_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_28 = id_ctrl_decoder_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_31_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_13_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_111_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_65_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_124_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_50_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_6_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_134_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_153_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_109_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_187_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_45_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_79_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_159_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_34_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_86_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_10_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_93_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_180_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_43_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_135_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_3_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_188_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_4_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_25_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_58_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_147_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_27_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_52_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_138_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_178_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_173_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_120_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_19_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_64_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_142_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_11_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_46_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_141_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_114_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_70_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_72_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_174_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_81_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_130_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_157_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_68_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_42_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_54_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_63_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_69_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_183_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_51_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_136_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_127_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_151_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_1_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_100_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_106_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_186_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_18_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_108_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_89_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_62_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_149_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_171_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_37_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = id_ctrl_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_122_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_82_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53] wire [31:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_119_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_169_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_57_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_80_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_175}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_166_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_175; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_176}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_154_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_176; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_177}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_192_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_177; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_178}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_38_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_178; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_179}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_158_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_179; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_180}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_110_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_180; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_181}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_23_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_181; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_182}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_101_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_182; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_183}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_118_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_183; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_184}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_116_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_184; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_185}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_156_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_185; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_186}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_113_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_186; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_187}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_107_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_187; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_188}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_84_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_188; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_189}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_33_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_189; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_190}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_85_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_190; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_191}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_40_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_191; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_192}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_12_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_192; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_193}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_75_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_193; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_118_2, id_ctrl_decoder_decoded_andMatrixOutputs_85_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_86_2, id_ctrl_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_148_2, id_ctrl_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [11:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T = {id_ctrl_decoder_decoded_orMatrixOutputs_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_1 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_1 = _GEN; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6 = _GEN; // @[pla.scala:114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_3 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_47_2, id_ctrl_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_55_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_9 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_0 = {id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_154_2, id_ctrl_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_57_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_1; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = _GEN_1; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = _GEN_1; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_24; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_24 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = _GEN_2; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = _GEN_3; // @[pla.scala:114:19] wire [1:0] _GEN_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = _GEN_4; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = _GEN_4; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = _GEN_4; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_5; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = _GEN_5; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = _GEN_6; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_6; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = _GEN_7; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [45:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_11 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_176_2, id_ctrl_decoder_decoded_andMatrixOutputs_172_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_13 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_116_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_72_2, id_ctrl_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_45_2, id_ctrl_decoder_decoded_andMatrixOutputs_114_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = _GEN_11; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_187_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_77_2, id_ctrl_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = _GEN_12; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_15 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = _GEN_13; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_123_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_22_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_18 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = _GEN_14; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = _GEN_14; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_124_2, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_20 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_65_2, id_ctrl_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_22 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_24 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_10; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_10 = _GEN_15; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = _GEN_15; // @[pla.scala:114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_26 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [8:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_30 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_167_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_104_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_94_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_56_2, id_ctrl_decoder_decoded_andMatrixOutputs_179_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = _GEN_16; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [14:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_32 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = _GEN_17; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_17; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_43_2, id_ctrl_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_73_2, id_ctrl_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_168_2, id_ctrl_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_112_2, id_ctrl_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_39_2, id_ctrl_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [17:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_34 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_5_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_150_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_36 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_147_2, id_ctrl_decoder_decoded_andMatrixOutputs_178_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [9:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_38 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_171_2, id_ctrl_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_108_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = _GEN_18; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = _GEN_18; // @[pla.scala:114:19] wire [1:0] _GEN_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = _GEN_19; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = _GEN_19; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_11_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [13:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_40 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_151_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_135_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_189_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_164_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [35:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_42 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_66_2, id_ctrl_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_44 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_46 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_22; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = _GEN_23; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_23; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_91_2, id_ctrl_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_24_2, id_ctrl_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_48 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = _GEN_24; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = _GEN_24; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = _GEN_25; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_26; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = _GEN_26; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] _GEN_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = _GEN_27; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_27; // @[pla.scala:114:19] wire [1:0] _GEN_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = _GEN_28; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = _GEN_29; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = _GEN_29; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] _GEN_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = _GEN_30; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = _GEN_30; // @[pla.scala:114:19] wire [1:0] _GEN_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = _GEN_31; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = _GEN_31; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = _GEN_31; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_32; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = _GEN_32; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_50 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_182_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_189_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_52 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_120_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] _GEN_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = _GEN_33; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = _GEN_33; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = _GEN_33; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_91_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_29_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19] wire [12:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [24:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_54 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_89_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] _GEN_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_34; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = _GEN_34; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = _GEN_34; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_146_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_190_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [34:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_56 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_68_2, id_ctrl_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_24, id_ctrl_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_58 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_25, id_ctrl_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_60 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_26, id_ctrl_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_62 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_66 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_65; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_158_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = _GEN_35; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = _GEN_35; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_136_2, id_ctrl_decoder_decoded_andMatrixOutputs_192_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_141_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_50_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_175_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [20:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_27, id_ctrl_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_68 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_173_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:114:19] wire [33:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_131_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_117_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:114:19] wire [34:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [68:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_28, id_ctrl_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_70 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_69; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_3, _id_ctrl_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_9, _id_ctrl_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = {1'h0, _id_ctrl_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _id_ctrl_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_16, _id_ctrl_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_22, _id_ctrl_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_27, _id_ctrl_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_32, _id_ctrl_decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_36, _id_ctrl_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_42, _id_ctrl_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_46, _id_ctrl_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_52, _id_ctrl_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_56, _id_ctrl_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_62, _id_ctrl_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_66, _id_ctrl_decoder_decoded_orMatrixOutputs_T_64}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_70, _id_ctrl_decoder_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, 1'h0}; // @[pla.scala:102:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:102:36] wire [41:0] id_ctrl_decoder_decoded_orMatrixOutputs = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_29, id_ctrl_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:102:36] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T = id_ctrl_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_1 = id_ctrl_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_2 = id_ctrl_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_3 = id_ctrl_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_4 = id_ctrl_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_5 = id_ctrl_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_6 = id_ctrl_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_7 = id_ctrl_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_8 = id_ctrl_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_9 = id_ctrl_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_10 = id_ctrl_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_11 = id_ctrl_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_12 = id_ctrl_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_13 = id_ctrl_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 = id_ctrl_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 = id_ctrl_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 = id_ctrl_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_17 = id_ctrl_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_18 = id_ctrl_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_19 = id_ctrl_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_20 = id_ctrl_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_21 = id_ctrl_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_22 = id_ctrl_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_23 = id_ctrl_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_24 = id_ctrl_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_25 = id_ctrl_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_26 = id_ctrl_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_27 = id_ctrl_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_28 = id_ctrl_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_29 = id_ctrl_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_30 = id_ctrl_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_31 = id_ctrl_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_32 = id_ctrl_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_33 = id_ctrl_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_34 = id_ctrl_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_35 = id_ctrl_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_36 = id_ctrl_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_37 = id_ctrl_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_38 = id_ctrl_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_39 = id_ctrl_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_40 = id_ctrl_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_41 = id_ctrl_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_1, _id_ctrl_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_4, _id_ctrl_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_6, _id_ctrl_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_9, _id_ctrl_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_11, _id_ctrl_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_14, _id_ctrl_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_17, _id_ctrl_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_20, _id_ctrl_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_22, _id_ctrl_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_25, _id_ctrl_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_27, _id_ctrl_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_30, _id_ctrl_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_32, _id_ctrl_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_35, _id_ctrl_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_38, _id_ctrl_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_41, _id_ctrl_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded_invMatrixOutputs = {id_ctrl_decoder_decoded_invMatrixOutputs_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded = id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign id_ctrl_decoder_0 = id_ctrl_decoder_decoded[41]; // @[pla.scala:81:23] assign id_ctrl_legal = id_ctrl_decoder_0; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_1 = id_ctrl_decoder_decoded[40]; // @[pla.scala:81:23] assign id_ctrl_fp = id_ctrl_decoder_1; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_2 = id_ctrl_decoder_decoded[39]; // @[pla.scala:81:23] assign id_ctrl_rocc = id_ctrl_decoder_2; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_3 = id_ctrl_decoder_decoded[38]; // @[pla.scala:81:23] assign id_ctrl_branch = id_ctrl_decoder_3; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_4 = id_ctrl_decoder_decoded[37]; // @[pla.scala:81:23] assign id_ctrl_jal = id_ctrl_decoder_4; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_5 = id_ctrl_decoder_decoded[36]; // @[pla.scala:81:23] assign id_ctrl_jalr = id_ctrl_decoder_5; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_6 = id_ctrl_decoder_decoded[35]; // @[pla.scala:81:23] assign id_ctrl_rxs2 = id_ctrl_decoder_6; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_7 = id_ctrl_decoder_decoded[34]; // @[pla.scala:81:23] assign id_ctrl_rxs1 = id_ctrl_decoder_7; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_8 = id_ctrl_decoder_decoded[33:31]; // @[pla.scala:81:23] assign id_ctrl_sel_alu2 = id_ctrl_decoder_8; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_9 = id_ctrl_decoder_decoded[30:29]; // @[pla.scala:81:23] assign id_ctrl_sel_alu1 = id_ctrl_decoder_9; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_10 = id_ctrl_decoder_decoded[28:26]; // @[pla.scala:81:23] assign id_ctrl_sel_imm = id_ctrl_decoder_10; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_11 = id_ctrl_decoder_decoded[25]; // @[pla.scala:81:23] assign id_ctrl_alu_dw = id_ctrl_decoder_11; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_12 = id_ctrl_decoder_decoded[24:20]; // @[pla.scala:81:23] assign id_ctrl_alu_fn = id_ctrl_decoder_12; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_13 = id_ctrl_decoder_decoded[19]; // @[pla.scala:81:23] assign id_ctrl_mem = id_ctrl_decoder_13; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_14 = id_ctrl_decoder_decoded[18:14]; // @[pla.scala:81:23] assign id_ctrl_mem_cmd = id_ctrl_decoder_14; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_15 = id_ctrl_decoder_decoded[13]; // @[pla.scala:81:23] assign id_ctrl_rfs1 = id_ctrl_decoder_15; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_16 = id_ctrl_decoder_decoded[12]; // @[pla.scala:81:23] assign id_ctrl_rfs2 = id_ctrl_decoder_16; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_17 = id_ctrl_decoder_decoded[11]; // @[pla.scala:81:23] assign id_ctrl_rfs3 = id_ctrl_decoder_17; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_18 = id_ctrl_decoder_decoded[10]; // @[pla.scala:81:23] assign id_ctrl_wfd = id_ctrl_decoder_18; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_19 = id_ctrl_decoder_decoded[9]; // @[pla.scala:81:23] assign id_ctrl_mul = id_ctrl_decoder_19; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_20 = id_ctrl_decoder_decoded[8]; // @[pla.scala:81:23] assign id_ctrl_div = id_ctrl_decoder_20; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_21 = id_ctrl_decoder_decoded[7]; // @[pla.scala:81:23] assign id_ctrl_wxd = id_ctrl_decoder_21; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_22 = id_ctrl_decoder_decoded[6:4]; // @[pla.scala:81:23] assign id_ctrl_csr = id_ctrl_decoder_22; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_23 = id_ctrl_decoder_decoded[3]; // @[pla.scala:81:23] assign id_ctrl_fence_i = id_ctrl_decoder_23; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_24 = id_ctrl_decoder_decoded[2]; // @[pla.scala:81:23] assign id_ctrl_fence = id_ctrl_decoder_24; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_25 = id_ctrl_decoder_decoded[1]; // @[pla.scala:81:23] assign id_ctrl_amo = id_ctrl_decoder_25; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_26 = id_ctrl_decoder_decoded[0]; // @[pla.scala:81:23] assign id_ctrl_dp = id_ctrl_decoder_26; // @[RocketCore.scala:321:21] wire [4:0] id_raddr3; // @[RocketCore.scala:326:72] wire [4:0] id_raddr2; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_7 = id_raddr2; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_raddr1; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_2 = id_raddr1; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_waddr; // @[RocketCore.scala:326:72] wire _id_load_use_T_1; // @[RocketCore.scala:1001:51] wire id_load_use; // @[RocketCore.scala:332:25] reg id_reg_fence; // @[RocketCore.scala:333:29] wire [63:0] id_rs_0; // @[RocketCore.scala:1325:26] wire _id_rs_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_3 = ~_id_rs_T_2; // @[RocketCore.scala:1320:{39,44}] wire [63:0] id_rs_1; // @[RocketCore.scala:1325:26] wire _id_rs_T_5 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_8 = ~_id_rs_T_7; // @[RocketCore.scala:1320:{39,44}] wire _ctrl_killd_T_4; // @[RocketCore.scala:1046:104] wire ctrl_killd; // @[RocketCore.scala:338:24] wire _id_npc_sign_T_1 = _ibuf_io_inst_0_bits_inst_bits[31]; // @[RocketCore.scala:311:20, :1341:44] wire _id_npc_sign_T_2 = _id_npc_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire id_npc_sign = _id_npc_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire _id_npc_b11_T_9 = id_npc_sign; // @[RocketCore.scala:1341:19, :1346:18] wire id_npc_hi_hi_hi = id_npc_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _id_npc_b30_20_T_1 = _ibuf_io_inst_0_bits_inst_bits[30:20]; // @[RocketCore.scala:311:20, :1342:41] wire [10:0] _id_npc_b30_20_T_2 = _id_npc_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] id_npc_b30_20 = {11{id_npc_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] id_npc_hi_hi_lo = id_npc_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _id_npc_b19_12_T_3 = _ibuf_io_inst_0_bits_inst_bits[19:12]; // @[RocketCore.scala:311:20, :1343:65] wire [7:0] _id_npc_b19_12_T_4 = _id_npc_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] id_npc_b19_12 = _id_npc_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}] wire [7:0] id_npc_hi_lo_hi = id_npc_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _id_npc_b11_T_4 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39] wire _id_npc_b0_T_3 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39, :1352:37] wire _id_npc_b11_T_5 = _id_npc_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _id_npc_b11_T_10 = _id_npc_b11_T_5; // @[RocketCore.scala:1345:{18,44}] wire _id_npc_b11_T_7 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39] wire _id_npc_b0_T_1 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39, :1351:37] wire _id_npc_b11_T_8 = _id_npc_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire id_npc_b11 = _id_npc_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire id_npc_hi_lo_lo = id_npc_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _id_npc_b10_5_T_3 = _ibuf_io_inst_0_bits_inst_bits[30:25]; // @[RocketCore.scala:311:20, :1347:62] wire [5:0] id_npc_b10_5 = _id_npc_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _id_npc_b4_1_T_4 = _ibuf_io_inst_0_bits_inst_bits[11:8]; // @[RocketCore.scala:311:20, :1349:57] wire [3:0] _id_npc_b4_1_T_6 = _ibuf_io_inst_0_bits_inst_bits[19:16]; // @[RocketCore.scala:311:20, :1350:39] wire [3:0] _id_npc_b4_1_T_7 = _ibuf_io_inst_0_bits_inst_bits[24:21]; // @[RocketCore.scala:311:20, :1350:52] wire [3:0] _id_npc_b4_1_T_8 = _id_npc_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _id_npc_b4_1_T_9 = _id_npc_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] id_npc_b4_1 = _id_npc_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _id_npc_b0_T_5 = _ibuf_io_inst_0_bits_inst_bits[15]; // @[RocketCore.scala:311:20, :1353:37] wire [9:0] id_npc_lo_hi = {id_npc_b10_5, id_npc_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] id_npc_lo = {id_npc_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] id_npc_hi_lo = {id_npc_hi_lo_hi, id_npc_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] id_npc_hi_hi = {id_npc_hi_hi_hi, id_npc_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] id_npc_hi = {id_npc_hi_hi, id_npc_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_1 = {id_npc_hi, id_npc_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_2 = _id_npc_T_1; // @[RocketCore.scala:1355:{8,53}] wire [39:0] _id_npc_T; // @[RocketCore.scala:339:28] wire [40:0] _id_npc_T_3 = {_id_npc_T[39], _id_npc_T} + {{9{_id_npc_T_2[31]}}, _id_npc_T_2}; // @[RocketCore.scala:339:{28,35}, :1355:53] wire [39:0] _id_npc_T_4 = _id_npc_T_3[39:0]; // @[RocketCore.scala:339:35] wire [39:0] _id_npc_T_5 = _id_npc_T_4; // @[RocketCore.scala:339:35] wire [39:0] id_npc = _id_npc_T_5; // @[RocketCore.scala:339:{35,65}] wire _GEN_36 = id_ctrl_csr == 3'h6; // @[package.scala:16:47] wire _id_csr_en_T; // @[package.scala:16:47] assign _id_csr_en_T = _GEN_36; // @[package.scala:16:47] wire _id_csr_ren_T; // @[package.scala:16:47] assign _id_csr_ren_T = _GEN_36; // @[package.scala:16:47] wire _id_csr_en_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_en_T_2 = id_ctrl_csr == 3'h5; // @[package.scala:16:47] wire _id_csr_en_T_3 = _id_csr_en_T \| _id_csr_en_T_1; // @[package.scala:16:47, :81:59] wire id_csr_en = _id_csr_en_T_3 \| _id_csr_en_T_2; // @[package.scala:16:47, :81:59] wire id_system_insn = id_ctrl_csr == 3'h4; // @[RocketCore.scala:321:21, :343:36] wire _id_csr_ren_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_ren_T_2 = _id_csr_ren_T \| _id_csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _id_csr_ren_T_3 = _ibuf_io_inst_0_bits_inst_rs1 == 5'h0; // @[RocketCore.scala:311:20, :344:81] wire id_csr_ren = _id_csr_ren_T_2 & _id_csr_ren_T_3; // @[package.scala:81:59] wire _id_csr_T = id_system_insn & id_ctrl_mem; // @[RocketCore.scala:321:21, :343:36, :345:35] wire [2:0] _id_csr_T_1 = id_csr_ren ? 3'h2 : id_ctrl_csr; // @[RocketCore.scala:321:21, :344:54, :345:61] wire [2:0] id_csr = _id_csr_T ? 3'h0 : _id_csr_T_1; // @[RocketCore.scala:345:{19,35,61}] wire _id_csr_flush_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54] wire _id_csr_flush_T_1 = id_csr_en & _id_csr_flush_T; // @[package.scala:81:59] wire _id_csr_flush_T_2 = _id_csr_flush_T_1 & _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19, :346:{51,66}] wire id_csr_flush = id_system_insn \| _id_csr_flush_T_2; // @[RocketCore.scala:343:36, :346:{37,66}] wire [31:0] _id_set_vconfig_T = _ibuf_io_inst_0_bits_inst_bits & 32'h8000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_1 = _id_set_vconfig_T == 32'h7057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_2 = _ibuf_io_inst_0_bits_inst_bits & 32'hC000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_3 = _id_set_vconfig_T_2 == 32'hC0007057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_4 = _ibuf_io_inst_0_bits_inst_bits & 32'hFE00707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_5 = _id_set_vconfig_T_4 == 32'h80007057; // @[RocketCore.scala:347:100] wire _id_set_vconfig_T_6 = _id_set_vconfig_T_1 \| _id_set_vconfig_T_3; // @[package.scala:81:59] wire _id_set_vconfig_T_7 = _id_set_vconfig_T_6 \| _id_set_vconfig_T_5; // @[package.scala:81:59] wire _id_illegal_insn_T = ~id_ctrl_legal; // @[RocketCore.scala:321:21, :381:25] wire _id_illegal_insn_T_1 = id_ctrl_mul \| id_ctrl_div; // @[RocketCore.scala:321:21, :382:18] wire _id_illegal_insn_T_2 = _csr_io_status_isa[12]; // @[RocketCore.scala:341:19, :382:55] wire _id_illegal_insn_T_3 = ~_id_illegal_insn_T_2; // @[RocketCore.scala:382:{37,55}] wire _id_illegal_insn_T_4 = _id_illegal_insn_T_1 & _id_illegal_insn_T_3; // @[RocketCore.scala:382:{18,34,37}] wire _id_illegal_insn_T_5 = _id_illegal_insn_T \| _id_illegal_insn_T_4; // @[RocketCore.scala:381:{25,40}, :382:34] wire _id_illegal_insn_T_6 = _csr_io_status_isa[0]; // @[RocketCore.scala:341:19, :383:38] wire _id_illegal_insn_T_7 = ~_id_illegal_insn_T_6; // @[RocketCore.scala:383:{20,38}] wire _id_illegal_insn_T_8 = id_ctrl_amo & _id_illegal_insn_T_7; // @[RocketCore.scala:321:21, :383:{17,20}] wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5 \| _id_illegal_insn_T_8; // @[RocketCore.scala:381:40, :382:65, :383:17] wire _id_illegal_insn_T_12 = _csr_io_decode_0_fp_illegal \| _id_illegal_insn_T_11; // @[RocketCore.scala:341:19, :384:{48,70}] wire _id_illegal_insn_T_13 = id_ctrl_fp & _id_illegal_insn_T_12; // @[RocketCore.scala:321:21, :384:{16,48}] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 \| _id_illegal_insn_T_13; // @[RocketCore.scala:382:65, :383:48, :384:16] wire _id_illegal_insn_T_17 = _id_illegal_insn_T_14; // @[RocketCore.scala:383:48, :384:88] wire _id_illegal_insn_T_18 = _csr_io_status_isa[3]; // @[RocketCore.scala:341:19, :386:37] wire _id_illegal_insn_T_19 = ~_id_illegal_insn_T_18; // @[RocketCore.scala:386:{19,37}] wire _id_illegal_insn_T_20 = id_ctrl_dp & _id_illegal_insn_T_19; // @[RocketCore.scala:321:21, :386:{16,19}] wire _id_illegal_insn_T_21 = _id_illegal_insn_T_17 \| _id_illegal_insn_T_20; // @[RocketCore.scala:384:88, :385:118, :386:16] wire _id_illegal_insn_T_22 = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51] wire _mem_npc_misaligned_T = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51, :623:46] wire _id_illegal_insn_T_23 = ~_id_illegal_insn_T_22; // @[RocketCore.scala:387:{33,51}] wire _id_illegal_insn_T_24 = _ibuf_io_inst_0_bits_rvc & _id_illegal_insn_T_23; // @[RocketCore.scala:311:20, :387:{30,33}] wire _id_illegal_insn_T_25 = _id_illegal_insn_T_21 \| _id_illegal_insn_T_24; // @[RocketCore.scala:385:118, :386:47, :387:30] wire _id_illegal_insn_T_27 = _id_illegal_insn_T_25; // @[RocketCore.scala:386:47, :387:61] wire _id_illegal_insn_T_29 = _id_illegal_insn_T_27; // @[RocketCore.scala:387:61, :388:39] wire _id_illegal_insn_T_31 = _id_illegal_insn_T_29; // @[RocketCore.scala:388:39, :389:39] wire _id_illegal_insn_T_33 = _id_illegal_insn_T_31 \| _id_illegal_insn_T_32; // @[RocketCore.scala:389:39, :390:37, :391:18] wire _id_illegal_insn_T_34 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :392:52] wire _id_illegal_insn_T_35 = _id_illegal_insn_T_34 & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :392:{52,64}] wire _id_illegal_insn_T_36 = _csr_io_decode_0_read_illegal \| _id_illegal_insn_T_35; // @[RocketCore.scala:341:19, :392:{49,64}] wire _id_illegal_insn_T_37 = id_csr_en & _id_illegal_insn_T_36; // @[package.scala:81:59] wire _id_illegal_insn_T_38 = _id_illegal_insn_T_33 \| _id_illegal_insn_T_37; // @[RocketCore.scala:390:37, :391:51, :392:15] wire _id_illegal_insn_T_39 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5] wire _id_illegal_insn_T_40 = id_system_insn & _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19, :343:36, :393:50] wire _id_illegal_insn_T_41 = _id_illegal_insn_T_39 & _id_illegal_insn_T_40; // @[RocketCore.scala:393:{5,31,50}] wire id_illegal_insn = _id_illegal_insn_T_38 \| _id_illegal_insn_T_41; // @[RocketCore.scala:391:51, :392:99, :393:31] wire _id_virtual_insn_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :395:22] wire _id_virtual_insn_T_1 = _id_virtual_insn_T & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :395:{22,34}] wire _id_virtual_insn_T_2 = ~_id_virtual_insn_T_1; // @[RocketCore.scala:395:{20,34}] wire _id_virtual_insn_T_3 = id_csr_en & _id_virtual_insn_T_2; // @[package.scala:81:59] wire _id_virtual_insn_T_4 = _id_virtual_insn_T_3 & _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19, :395:{17,69}] wire _id_virtual_insn_T_5 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5, :396:7] wire _id_virtual_insn_T_6 = _id_virtual_insn_T_5 & id_system_insn; // @[RocketCore.scala:343:36, :396:{7,33}] wire _id_virtual_insn_T_7 = _id_virtual_insn_T_6 & _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19, :396:{33,51}] wire _id_virtual_insn_T_8 = _id_virtual_insn_T_4 \| _id_virtual_insn_T_7; // @[RocketCore.scala:395:{69,113}, :396:51] wire id_virtual_insn = id_ctrl_legal & _id_virtual_insn_T_8; // @[RocketCore.scala:321:21, :394:39, :395:113] wire id_amo_aq = _ibuf_io_inst_0_bits_inst_bits[26]; // @[RocketCore.scala:311:20, :398:29] wire id_amo_rl = _ibuf_io_inst_0_bits_inst_bits[25]; // @[RocketCore.scala:311:20, :399:29] wire [3:0] id_fence_pred = _ibuf_io_inst_0_bits_inst_bits[27:24]; // @[RocketCore.scala:311:20, :400:33] wire [3:0] id_fence_succ = _ibuf_io_inst_0_bits_inst_bits[23:20]; // @[RocketCore.scala:311:20, :401:33] wire _id_fence_next_T = id_ctrl_amo & id_amo_aq; // @[RocketCore.scala:321:21, :398:29, :402:52] wire id_fence_next = id_ctrl_fence \| _id_fence_next_T; // @[RocketCore.scala:321:21, :402:{37,52}] wire _id_mem_busy_T = ~io_dmem_ordered_0; // @[RocketCore.scala:153:7, :403:21] wire id_mem_busy = _id_mem_busy_T \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :403:{21,38}] wire _id_rocc_busy_T = ex_reg_valid & ex_ctrl_rocc; // @[RocketCore.scala:243:20, :248:35, :406:35] wire _id_rocc_busy_T_1 = _id_rocc_busy_T; // @[RocketCore.scala:406:{19,35}] wire _id_rocc_busy_T_2 = mem_reg_valid & mem_ctrl_rocc; // @[RocketCore.scala:244:21, :265:36, :407:20] wire _id_rocc_busy_T_3 = _id_rocc_busy_T_1 \| _id_rocc_busy_T_2; // @[RocketCore.scala:406:{19,51}, :407:20] wire _GEN_37 = wb_reg_valid & wb_ctrl_rocc; // @[RocketCore.scala:245:20, :288:35, :407:53] wire _id_rocc_busy_T_4; // @[RocketCore.scala:407:53] assign _id_rocc_busy_T_4 = _GEN_37; // @[RocketCore.scala:407:53] wire _replay_wb_rocc_T; // @[RocketCore.scala:758:37] assign _replay_wb_rocc_T = _GEN_37; // @[RocketCore.scala:407:53, :758:37] wire _io_rocc_cmd_valid_T; // @[RocketCore.scala:1156:37] assign _io_rocc_cmd_valid_T = _GEN_37; // @[RocketCore.scala:407:53, :1156:37] wire _id_rocc_busy_T_5 = _id_rocc_busy_T_3 \| _id_rocc_busy_T_4; // @[RocketCore.scala:406:51, :407:{37,53}] wire _id_csr_rocc_write_T_1 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :408:103] wire _id_do_fence_T_4 = id_ctrl_amo & id_amo_rl; // @[RocketCore.scala:321:21, :399:29, :412:33] wire _id_do_fence_T_5 = _id_do_fence_T_4 \| id_ctrl_fence_i; // @[RocketCore.scala:321:21, :412:{33,46}] wire _id_do_fence_T_6 = id_ctrl_mem \| id_ctrl_rocc; // @[RocketCore.scala:321:21, :412:97] wire _id_do_fence_T_7 = id_reg_fence & _id_do_fence_T_6; // @[RocketCore.scala:333:29, :412:{81,97}] wire _id_do_fence_T_8 = _id_do_fence_T_5 \| _id_do_fence_T_7; // @[RocketCore.scala:412:{46,65,81}] wire _id_do_fence_T_9 = id_mem_busy & _id_do_fence_T_8; // @[RocketCore.scala:403:38, :412:{17,65}] wire _id_do_fence_T_10 = _id_do_fence_T_9; // @[RocketCore.scala:411:34, :412:17] wire id_do_fence = _id_do_fence_T_10; // @[RocketCore.scala:410:32, :411:34] wire [38:0] _mem_npc_T_1 = mem_reg_wdata[38:0]; // @[RocketCore.scala:282:26, :418:13, :1295:16] wire id_xcpt = _csr_io_interrupt \| _bpu_io_debug_if \| _bpu_io_xcpt_if \| _ibuf_io_inst_0_bits_xcpt0_pf_inst \| _ibuf_io_inst_0_bits_xcpt0_gf_inst \| _ibuf_io_inst_0_bits_xcpt0_ae_inst \| _ibuf_io_inst_0_bits_xcpt1_pf_inst \| _ibuf_io_inst_0_bits_xcpt1_gf_inst \| _ibuf_io_inst_0_bits_xcpt1_ae_inst \| id_virtual_insn \| id_illegal_insn; // @[RocketCore.scala:311:20, :341:19, :392:99, :394:39, :414:19, :1278:{14,35}] wire [63:0] id_cause = _csr_io_interrupt ? _csr_io_interrupt_cause : {59'h0, _bpu_io_debug_if ? 5'hE : _bpu_io_xcpt_if ? 5'h3 : _ibuf_io_inst_0_bits_xcpt0_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt0_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt0_ae_inst ? 5'h1 : _ibuf_io_inst_0_bits_xcpt1_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt1_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt1_ae_inst ? 5'h1 : id_virtual_insn ? 5'h16 : 5'h2}; // @[Mux.scala:50:70] wire [4:0] _ex_waddr_T = ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :453:29] wire [4:0] ex_waddr = _ex_waddr_T; // @[RocketCore.scala:453:{29,36}] wire [4:0] _mem_waddr_T = mem_reg_inst[11:7]; // @[RocketCore.scala:278:25, :454:31] wire [4:0] mem_waddr = _mem_waddr_T; // @[RocketCore.scala:454:{31,38}] wire [4:0] _wb_waddr_T = wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :455:29] wire [4:0] wb_waddr = _wb_waddr_T; // @[RocketCore.scala:455:{29,36}] wire [4:0] coreMonitorBundle_wrdst = wb_waddr; // @[RocketCore.scala:455:36, :1186:31] wire bypass_sources_1_1 = ex_reg_valid & ex_ctrl_wxd; // @[RocketCore.scala:243:20, :248:35, :458:19] wire _GEN_38 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :265:36, :459:20] wire _bypass_sources_T; // @[RocketCore.scala:459:20] assign _bypass_sources_T = _GEN_38; // @[RocketCore.scala:459:20] wire bypass_sources_3_1; // @[RocketCore.scala:460:20] assign bypass_sources_3_1 = _GEN_38; // @[RocketCore.scala:459:20, :460:20] wire _dcache_kill_mem_T; // @[RocketCore.scala:695:39] assign _dcache_kill_mem_T = _GEN_38; // @[RocketCore.scala:459:20, :695:39] wire _bypass_sources_T_1 = ~mem_ctrl_mem; // @[RocketCore.scala:244:21, :459:39] wire bypass_sources_2_1 = _bypass_sources_T & _bypass_sources_T_1; // @[RocketCore.scala:459:{20,36,39}] wire _id_bypass_src_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_0_0 = _id_bypass_src_T; // @[RocketCore.scala:461:{74,82}] wire _GEN_39 = ex_waddr == id_raddr1; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_1; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_1 = _GEN_39; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T = _GEN_39; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_1; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_1 = _GEN_39; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_0_1 = bypass_sources_1_1 & _id_bypass_src_T_1; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_40 = mem_waddr == id_raddr1; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_2; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_2 = _GEN_40; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_3; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_3 = _GEN_40; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T = _GEN_40; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_1; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_1 = _GEN_40; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_0_2 = bypass_sources_2_1 & _id_bypass_src_T_2; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_0_3 = bypass_sources_3_1 & _id_bypass_src_T_3; // @[RocketCore.scala:460:20, :461:{74,82}] wire _id_bypass_src_T_4 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_1_0 = _id_bypass_src_T_4; // @[RocketCore.scala:461:{74,82}] wire _GEN_41 = ex_waddr == id_raddr2; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_5; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_5 = _GEN_41; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T_2; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_2 = _GEN_41; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_3; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_3 = _GEN_41; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_1_1 = bypass_sources_1_1 & _id_bypass_src_T_5; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_42 = mem_waddr == id_raddr2; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_6; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_6 = _GEN_42; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_7; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_7 = _GEN_42; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T_2; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_2 = _GEN_42; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_3; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_3 = _GEN_42; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_1_2 = bypass_sources_2_1 & _id_bypass_src_T_6; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_1_3 = bypass_sources_3_1 & _id_bypass_src_T_7; // @[RocketCore.scala:460:20, :461:{74,82}] reg ex_reg_rs_bypass_0; // @[RocketCore.scala:465:29] reg ex_reg_rs_bypass_1; // @[RocketCore.scala:465:29] reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala:466:26] reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala:466:26] reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala:467:26] reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala:467:26] wire _ex_rs_T = ex_reg_rs_lsb_0 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_1 = _ex_rs_T ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_2 = ex_reg_rs_lsb_0 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_3 = _ex_rs_T_2 ? wb_reg_wdata : _ex_rs_T_1; // @[package.scala:39:{76,86}] wire _ex_rs_T_4 = &ex_reg_rs_lsb_0; // @[package.scala:39:86] wire [63:0] _ex_rs_T_5 = _ex_rs_T_4 ? dcache_bypass_data : _ex_rs_T_3; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_6 = {ex_reg_rs_msb_0, ex_reg_rs_lsb_0}; // @[RocketCore.scala:466:26, :467:26, :469:69] assign ex_rs_0 = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[package.scala:39:76] assign io_fpu_fromint_data_0 = ex_rs_0; // @[RocketCore.scala:153:7, :469:14] wire [63:0] _ex_op1_T = ex_rs_0; // @[RocketCore.scala:469:14, :473:24] wire _ex_rs_T_7 = ex_reg_rs_lsb_1 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_8 = _ex_rs_T_7 ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_9 = ex_reg_rs_lsb_1 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_10 = _ex_rs_T_9 ? wb_reg_wdata : _ex_rs_T_8; // @[package.scala:39:{76,86}] wire _ex_rs_T_11 = &ex_reg_rs_lsb_1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_12 = _ex_rs_T_11 ? dcache_bypass_data : _ex_rs_T_10; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_13 = {ex_reg_rs_msb_1, ex_reg_rs_lsb_1}; // @[RocketCore.scala:466:26, :467:26, :469:69] wire [63:0] ex_rs_1 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[package.scala:39:76] wire [63:0] _ex_op2_T = ex_rs_1; // @[RocketCore.scala:469:14, :479:24] wire [63:0] mem_reg_rs2_dat_padded = ex_rs_1; // @[RocketCore.scala:469:14] wire _GEN_43 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala:243:20, :1341:24] wire _ex_imm_sign_T; // @[RocketCore.scala:1341:24] assign _ex_imm_sign_T = _GEN_43; // @[RocketCore.scala:1341:24] wire _ex_imm_b11_T_1; // @[RocketCore.scala:1344:40] assign _ex_imm_b11_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1344:40] wire _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:42] assign _ex_imm_b10_5_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1347:42] wire _ex_imm_b4_1_T_5; // @[RocketCore.scala:1350:24] assign _ex_imm_b4_1_T_5 = _GEN_43; // @[RocketCore.scala:1341:24, :1350:24] wire _ex_imm_b0_T_4; // @[RocketCore.scala:1353:22] assign _ex_imm_b0_T_4 = _GEN_43; // @[RocketCore.scala:1341:24, :1353:22] wire _ex_imm_sign_T_1 = ex_reg_inst[31]; // @[RocketCore.scala:259:24, :1341:44] wire _ex_imm_sign_T_2 = _ex_imm_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire ex_imm_sign = ~_ex_imm_sign_T & _ex_imm_sign_T_2; // @[RocketCore.scala:1341:{19,24,49}] wire ex_imm_hi_hi_hi = ex_imm_sign; // @[RocketCore.scala:1341:19, :1355:8] wire _GEN_44 = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala:243:20, :1342:26] wire _ex_imm_b30_20_T; // @[RocketCore.scala:1342:26] assign _ex_imm_b30_20_T = _GEN_44; // @[RocketCore.scala:1342:26] wire _ex_imm_b11_T; // @[RocketCore.scala:1344:23] assign _ex_imm_b11_T = _GEN_44; // @[RocketCore.scala:1342:26, :1344:23] wire _ex_imm_b10_5_T; // @[RocketCore.scala:1347:25] assign _ex_imm_b10_5_T = _GEN_44; // @[RocketCore.scala:1342:26, :1347:25] wire _ex_imm_b4_1_T; // @[RocketCore.scala:1348:24] assign _ex_imm_b4_1_T = _GEN_44; // @[RocketCore.scala:1342:26, :1348:24] wire [10:0] _ex_imm_b30_20_T_1 = ex_reg_inst[30:20]; // @[RocketCore.scala:259:24, :1342:41] wire [10:0] _ex_imm_b30_20_T_2 = _ex_imm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] ex_imm_b30_20 = _ex_imm_b30_20_T ? _ex_imm_b30_20_T_2 : {11{ex_imm_sign}}; // @[RocketCore.scala:1341:19, :1342:{21,26,49}] wire [10:0] ex_imm_hi_hi_lo = ex_imm_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire _ex_imm_b19_12_T = ex_ctrl_sel_imm != 3'h2; // @[RocketCore.scala:243:20, :1343:26] wire _ex_imm_b19_12_T_1 = ex_ctrl_sel_imm != 3'h3; // @[RocketCore.scala:243:20, :1343:43] wire _ex_imm_b19_12_T_2 = _ex_imm_b19_12_T & _ex_imm_b19_12_T_1; // @[RocketCore.scala:1343:{26,36,43}] wire [7:0] _ex_imm_b19_12_T_3 = ex_reg_inst[19:12]; // @[RocketCore.scala:259:24, :1343:65] wire [7:0] _ex_imm_b19_12_T_4 = _ex_imm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] ex_imm_b19_12 = _ex_imm_b19_12_T_2 ? {8{ex_imm_sign}} : _ex_imm_b19_12_T_4; // @[RocketCore.scala:1341:19, :1343:{21,36,73}] wire [7:0] ex_imm_hi_lo_hi = ex_imm_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _ex_imm_b11_T_2 = _ex_imm_b11_T \| _ex_imm_b11_T_1; // @[RocketCore.scala:1344:{23,33,40}] wire _ex_imm_b11_T_3 = ex_ctrl_sel_imm == 3'h3; // @[RocketCore.scala:243:20, :1345:23] wire _ex_imm_b11_T_4 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39] wire _ex_imm_b0_T_3 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39, :1352:37] wire _io_dmem_req_bits_signed_T = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1136:58, :1345:39] wire _ex_imm_b11_T_5 = _ex_imm_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _GEN_45 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala:243:20, :1346:23] wire _ex_imm_b11_T_6; // @[RocketCore.scala:1346:23] assign _ex_imm_b11_T_6 = _GEN_45; // @[RocketCore.scala:1346:23] wire _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:41] assign _ex_imm_b4_1_T_2 = _GEN_45; // @[RocketCore.scala:1346:23, :1349:41] wire _ex_imm_b11_T_7 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39] wire _ex_imm_b0_T_1 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39, :1351:37] wire _ex_imm_b11_T_8 = _ex_imm_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _ex_imm_b11_T_9 = _ex_imm_b11_T_6 ? _ex_imm_b11_T_8 : ex_imm_sign; // @[RocketCore.scala:1341:19, :1346:{18,23,43}] wire _ex_imm_b11_T_10 = _ex_imm_b11_T_3 ? _ex_imm_b11_T_5 : _ex_imm_b11_T_9; // @[RocketCore.scala:1345:{18,23,44}, :1346:18] wire ex_imm_b11 = ~_ex_imm_b11_T_2 & _ex_imm_b11_T_10; // @[RocketCore.scala:1344:{18,33}, :1345:18] wire ex_imm_hi_lo_lo = ex_imm_b11; // @[RocketCore.scala:1344:18, :1355:8] wire _ex_imm_b10_5_T_2 = _ex_imm_b10_5_T \| _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:{25,35,42}] wire [5:0] _ex_imm_b10_5_T_3 = ex_reg_inst[30:25]; // @[RocketCore.scala:259:24, :1347:62] wire [5:0] ex_imm_b10_5 = _ex_imm_b10_5_T_2 ? 6'h0 : _ex_imm_b10_5_T_3; // @[RocketCore.scala:1347:{20,35,62}] wire _GEN_46 = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala:243:20, :1349:24] wire _ex_imm_b4_1_T_1; // @[RocketCore.scala:1349:24] assign _ex_imm_b4_1_T_1 = _GEN_46; // @[RocketCore.scala:1349:24] wire _ex_imm_b0_T; // @[RocketCore.scala:1351:22] assign _ex_imm_b0_T = _GEN_46; // @[RocketCore.scala:1349:24, :1351:22] wire _ex_imm_b4_1_T_3 = _ex_imm_b4_1_T_1 \| _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:{24,34,41}] wire [3:0] _ex_imm_b4_1_T_4 = ex_reg_inst[11:8]; // @[RocketCore.scala:259:24, :1349:57] wire [3:0] _ex_imm_b4_1_T_6 = ex_reg_inst[19:16]; // @[RocketCore.scala:259:24, :1350:39] wire [3:0] _ex_imm_b4_1_T_7 = ex_reg_inst[24:21]; // @[RocketCore.scala:259:24, :1350:52] wire [3:0] _ex_imm_b4_1_T_8 = _ex_imm_b4_1_T_5 ? _ex_imm_b4_1_T_6 : _ex_imm_b4_1_T_7; // @[RocketCore.scala:1350:{19,24,39,52}] wire [3:0] _ex_imm_b4_1_T_9 = _ex_imm_b4_1_T_3 ? _ex_imm_b4_1_T_4 : _ex_imm_b4_1_T_8; // @[RocketCore.scala:1349:{19,34,57}, :1350:19] wire [3:0] ex_imm_b4_1 = _ex_imm_b4_1_T ? 4'h0 : _ex_imm_b4_1_T_9; // @[RocketCore.scala:1348:{19,24}, :1349:19] wire _ex_imm_b0_T_2 = ex_ctrl_sel_imm == 3'h4; // @[RocketCore.scala:243:20, :1352:22] wire _ex_imm_b0_T_5 = ex_reg_inst[15]; // @[RocketCore.scala:259:24, :1353:37] wire _ex_imm_b0_T_6 = _ex_imm_b0_T_4 & _ex_imm_b0_T_5; // @[RocketCore.scala:1353:{17,22,37}] wire _ex_imm_b0_T_7 = _ex_imm_b0_T_2 ? _ex_imm_b0_T_3 : _ex_imm_b0_T_6; // @[RocketCore.scala:1352:{17,22,37}, :1353:17] wire ex_imm_b0 = _ex_imm_b0_T ? _ex_imm_b0_T_1 : _ex_imm_b0_T_7; // @[RocketCore.scala:1351:{17,22,37}, :1352:17] wire [9:0] ex_imm_lo_hi = {ex_imm_b10_5, ex_imm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] ex_imm_lo = {ex_imm_lo_hi, ex_imm_b0}; // @[RocketCore.scala:1351:17, :1355:8] wire [8:0] ex_imm_hi_lo = {ex_imm_hi_lo_hi, ex_imm_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] ex_imm_hi_hi = {ex_imm_hi_hi_hi, ex_imm_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] ex_imm_hi = {ex_imm_hi_hi, ex_imm_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _ex_imm_T = {ex_imm_hi, ex_imm_lo}; // @[RocketCore.scala:1355:8] wire [31:0] ex_imm = _ex_imm_T; // @[RocketCore.scala:1355:{8,53}] wire _ex_rs1shl_T = ex_reg_inst[3]; // @[RocketCore.scala:259:24, :471:34] wire [31:0] _ex_rs1shl_T_1 = ex_rs_0[31:0]; // @[RocketCore.scala:469:14, :471:47] wire [63:0] _ex_rs1shl_T_2 = _ex_rs1shl_T ? {32'h0, _ex_rs1shl_T_1} : ex_rs_0; // @[RocketCore.scala:469:14, :471:{22,34,47}] wire [1:0] _ex_rs1shl_T_3 = ex_reg_inst[14:13]; // @[RocketCore.scala:259:24, :471:79] wire [66:0] ex_rs1shl = {3'h0, _ex_rs1shl_T_2} << _ex_rs1shl_T_3; // @[RocketCore.scala:471:{22,65,79}] wire [66:0] _ex_op1_T_2 = ex_rs1shl; // @[RocketCore.scala:471:65, :475:54] wire _ex_op1_T_3 = ex_ctrl_sel_alu1 == 2'h1; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_4 = _ex_op1_T_3 ? _ex_op1_T : 64'h0; // @[RocketCore.scala:472:48, :473:24] wire _ex_op1_T_5 = ex_ctrl_sel_alu1 == 2'h2; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_6 = _ex_op1_T_5 ? {{24{_ex_op1_T_1[39]}}, _ex_op1_T_1} : _ex_op1_T_4; // @[RocketCore.scala:472:48, :474:24] wire _ex_op1_T_7 = &ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20, :472:48] wire [66:0] ex_op1 = _ex_op1_T_7 ? _ex_op1_T_2 : {{3{_ex_op1_T_6[63]}}, _ex_op1_T_6}; // @[RocketCore.scala:472:48, :475:54] wire [66:0] _alu_io_in1_T = ex_op1; // @[RocketCore.scala:472:48, :508:24] wire _ex_op2_oh_T = ex_ctrl_sel_alu2[0]; // @[RocketCore.scala:243:20, :477:48] wire [11:0] _ex_op2_oh_T_1 = ex_reg_inst[31:20]; // @[RocketCore.scala:259:24, :477:66] wire [63:0] _ex_op2_oh_T_2 = _ex_op2_oh_T ? {52'h0, _ex_op2_oh_T_1} : ex_rs_1; // @[RocketCore.scala:469:14, :477:{31,48,66}] wire [5:0] _ex_op2_oh_T_3 = _ex_op2_oh_T_2[5:0]; // @[RocketCore.scala:477:{31,90}] wire [63:0] _ex_op2_oh_T_4 = 64'h1 << _ex_op2_oh_T_3; // @[OneHot.scala:58:35] wire [63:0] ex_op2_oh = _ex_op2_oh_T_4; // @[OneHot.scala:58:35] wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:249:35, :481:19] wire _ex_op2_T_2 = ex_ctrl_sel_alu2 == 3'h2; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_3 = _ex_op2_T_2 ? _ex_op2_T : 64'h0; // @[RocketCore.scala:478:48, :479:24] wire _ex_op2_T_4 = ex_ctrl_sel_alu2 == 3'h3; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_5 = _ex_op2_T_4 ? {{32{ex_imm[31]}}, ex_imm} : _ex_op2_T_3; // @[RocketCore.scala:478:48, :1355:53] wire _ex_op2_T_6 = ex_ctrl_sel_alu2 == 3'h1; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_7 = _ex_op2_T_6 ? {{60{_ex_op2_T_1[3]}}, _ex_op2_T_1} : _ex_op2_T_5; // @[RocketCore.scala:478:48, :481:19] wire _ex_op2_T_8 = ex_ctrl_sel_alu2 == 3'h4; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_9 = _ex_op2_T_8 ? ex_op2_oh : _ex_op2_T_7; // @[RocketCore.scala:477:112, :478:48] wire _ex_op2_T_10 = ex_ctrl_sel_alu2 == 3'h5; // @[RocketCore.scala:243:20, :478:48] wire [63:0] ex_op2 = _ex_op2_T_10 ? ex_op2_oh : _ex_op2_T_9; // @[RocketCore.scala:477:112, :478:48] wire [63:0] _alu_io_in2_T = ex_op2; // @[RocketCore.scala:478:48, :507:24] wire _div_io_req_valid_T = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala:243:20, :248:35, :512:36] wire _ex_reg_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19] wire _ex_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20] wire _ex_reg_replay_T_1 = _ex_reg_replay_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :526:{20,29}] wire _ex_reg_replay_T_2 = _ex_reg_replay_T_1 & _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :526:{29,54}] wire _ex_reg_xcpt_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :527:18] wire _ex_reg_xcpt_T_1 = _ex_reg_xcpt_T & id_xcpt; // @[RocketCore.scala:527:{18,30}, :1278:14] wire _ex_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :528:28] wire _ex_reg_xcpt_interrupt_T_1 = _ex_reg_xcpt_interrupt_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :528:{28,37}] wire _ex_reg_xcpt_interrupt_T_2 = _ex_reg_xcpt_interrupt_T_1 & _csr_io_interrupt; // @[RocketCore.scala:341:19, :528:{37,62}] wire [1:0] hi = {_ibuf_io_inst_0_bits_xcpt1_pf_inst, _ibuf_io_inst_0_bits_xcpt1_gf_inst}; // @[RocketCore.scala:311:20, :541:22] wire [1:0] hi_1 = {_ibuf_io_inst_0_bits_xcpt0_pf_inst, _ibuf_io_inst_0_bits_xcpt0_gf_inst}; // @[RocketCore.scala:311:20, :546:40] wire _ex_reg_flush_pipe_T = id_ctrl_fence_i \| id_csr_flush; // @[RocketCore.scala:321:21, :346:37, :551:42] wire _ex_reg_hls_T_1 = id_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _ex_reg_hls_T_2 = id_ctrl_mem_cmd == 5'h1; // @[package.scala:16:47] wire _ex_reg_hls_T_3 = id_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _ex_reg_hls_T_4 = _ex_reg_hls_T_1 \| _ex_reg_hls_T_2; // @[package.scala:16:47, :81:59] wire _ex_reg_hls_T_5 = _ex_reg_hls_T_4 \| _ex_reg_hls_T_3; // @[package.scala:16:47, :81:59] wire [1:0] _ex_reg_mem_size_T_1 = _ibuf_io_inst_0_bits_inst_bits[27:26]; // @[RocketCore.scala:311:20, :554:75] wire [1:0] _ex_reg_mem_size_T_2 = _ibuf_io_inst_0_bits_inst_bits[13:12]; // @[RocketCore.scala:311:20, :554:95] wire [1:0] _ex_reg_mem_size_T_3 = _ex_reg_mem_size_T_2; // @[RocketCore.scala:554:{27,95}] wire _ex_reg_mem_size_T_4 = \|id_raddr2; // @[RocketCore.scala:326:72, :556:40, :1326:41] wire _ex_reg_mem_size_T_5 = \|id_raddr1; // @[RocketCore.scala:326:72, :556:59, :1326:41] wire [1:0] _ex_reg_mem_size_T_6 = {_ex_reg_mem_size_T_4, _ex_reg_mem_size_T_5}; // @[RocketCore.scala:556:{29,40,59}] wire _do_bypass_T = id_bypass_src_0_0 \| id_bypass_src_0_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_1 = _do_bypass_T \| id_bypass_src_0_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass = _do_bypass_T_1 \| id_bypass_src_0_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T = {1'h1, ~id_bypass_src_0_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_1 = id_bypass_src_0_1 ? 2'h1 : _bypass_src_T; // @[Mux.scala:50:70] wire [1:0] bypass_src = id_bypass_src_0_0 ? 2'h0 : _bypass_src_T_1; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_0_T = id_rs_0[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_0_T = id_rs_0[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire _do_bypass_T_2 = id_bypass_src_1_0 \| id_bypass_src_1_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_3 = _do_bypass_T_2 \| id_bypass_src_1_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass_1 = _do_bypass_T_3 \| id_bypass_src_1_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T_2 = {1'h1, ~id_bypass_src_1_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_3 = id_bypass_src_1_1 ? 2'h1 : _bypass_src_T_2; // @[Mux.scala:50:70] wire [1:0] bypass_src_1 = id_bypass_src_1_0 ? 2'h0 : _bypass_src_T_3; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_1_T = id_rs_1[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_1_T = id_rs_1[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire [15:0] _inst_T = _ibuf_io_inst_0_bits_raw[15:0]; // @[RocketCore.scala:311:20, :578:62] wire [31:0] inst = _ibuf_io_inst_0_bits_rvc ? {16'h0, _inst_T} : _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20, :578:{21,62}] wire [1:0] _ex_reg_rs_lsb_0_T_1 = inst[1:0]; // @[RocketCore.scala:578:21, :580:31] wire [29:0] _ex_reg_rs_msb_0_T_1 = inst[31:2]; // @[RocketCore.scala:578:21, :581:32] wire _ex_reg_set_vconfig_T = ~id_xcpt; // @[RocketCore.scala:591:45, :1278:14] wire _ex_pc_valid_T = ex_reg_valid \| ex_reg_replay; // @[RocketCore.scala:248:35, :255:26, :595:34] wire ex_pc_valid = _ex_pc_valid_T \| ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :595:{34,51}] wire _wb_dcache_miss_T = ~io_dmem_resp_valid_0; // @[RocketCore.scala:153:7, :596:39] wire wb_dcache_miss = wb_ctrl_mem & _wb_dcache_miss_T; // @[RocketCore.scala:245:20, :596:{36,39}] wire _replay_ex_structural_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45] wire _replay_ex_structural_T_1 = ex_ctrl_mem & _replay_ex_structural_T; // @[RocketCore.scala:243:20, :597:{42,45}] wire _replay_ex_structural_T_2 = ~_div_io_req_ready; // @[RocketCore.scala:511:19, :598:45] wire _replay_ex_structural_T_3 = ex_ctrl_div & _replay_ex_structural_T_2; // @[RocketCore.scala:243:20, :598:{42,45}] wire _replay_ex_structural_T_4 = _replay_ex_structural_T_1 \| _replay_ex_structural_T_3; // @[RocketCore.scala:597:{42,64}, :598:42] wire replay_ex_structural = _replay_ex_structural_T_4; // @[RocketCore.scala:597:64, :598:63] wire replay_ex_load_use = wb_dcache_miss & ex_reg_load_use; // @[RocketCore.scala:253:35, :596:36, :600:43] wire _replay_ex_T = replay_ex_structural \| replay_ex_load_use; // @[RocketCore.scala:598:63, :600:43, :601:75] wire _replay_ex_T_1 = ex_reg_valid & _replay_ex_T; // @[RocketCore.scala:248:35, :601:{50,75}] wire replay_ex = ex_reg_replay \| _replay_ex_T_1; // @[RocketCore.scala:255:26, :601:{33,50}] wire _ctrl_killx_T = take_pc_mem_wb \| replay_ex; // @[RocketCore.scala:307:35, :601:33, :602:35] wire _ctrl_killx_T_1 = ~ex_reg_valid; // @[RocketCore.scala:248:35, :602:51] assign ctrl_killx = _ctrl_killx_T \| _ctrl_killx_T_1; // @[RocketCore.scala:602:{35,48,51}] assign io_fpu_killx_0 = ctrl_killx; // @[RocketCore.scala:153:7, :602:48] wire _GEN_47 = ex_ctrl_mem_cmd == 5'h7; // @[RocketCore.scala:243:20, :604:40] wire _ex_slow_bypass_T; // @[RocketCore.scala:604:40] assign _ex_slow_bypass_T = _GEN_47; // @[RocketCore.scala:604:40] wire _mem_reg_load_T_3; // @[package.scala:16:47] assign _mem_reg_load_T_3 = _GEN_47; // @[package.scala:16:47] wire _mem_reg_store_T_3; // @[Consts.scala:90:66] assign _mem_reg_store_T_3 = _GEN_47; // @[RocketCore.scala:604:40] wire _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_3 = _GEN_47; // @[package.scala:16:47] wire _ex_slow_bypass_T_1 = ~(ex_reg_mem_size[1]); // @[RocketCore.scala:257:28, :604:69] wire ex_slow_bypass = _ex_slow_bypass_T \| _ex_slow_bypass_T_1; // @[RocketCore.scala:604:{40,50,69}] wire _ex_sfence_T_1 = ex_ctrl_mem_cmd == 5'h14; // @[RocketCore.scala:243:20, :605:64] wire _ex_sfence_T_2 = ex_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:243:20, :605:96] wire _ex_sfence_T_3 = _ex_sfence_T_1 \| _ex_sfence_T_2; // @[RocketCore.scala:605:{64,77,96}] wire _ex_sfence_T_4 = ex_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:243:20, :605:129] wire _ex_sfence_T_5 = _ex_sfence_T_3 \| _ex_sfence_T_4; // @[RocketCore.scala:605:{77,110,129}] wire ex_sfence = _ex_sfence_T & _ex_sfence_T_5; // @[RocketCore.scala:605:{29,44,110}] wire ex_xcpt = ex_reg_xcpt_interrupt \| ex_reg_xcpt; // @[RocketCore.scala:247:35, :251:35, :608:28, :1278:14] wire _mem_pc_valid_T = mem_reg_valid \| mem_reg_replay; // @[RocketCore.scala:265:36, :269:36, :614:36] wire mem_pc_valid = _mem_pc_valid_T \| mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36, :614:{36,54}] wire _GEN_48 = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala:244:21, :284:25, :616:25] wire _mem_br_target_T_1; // @[RocketCore.scala:616:25] assign _mem_br_target_T_1 = _GEN_48; // @[RocketCore.scala:616:25] wire _mem_cfi_taken_T; // @[RocketCore.scala:626:40] assign _mem_cfi_taken_T = _GEN_48; // @[RocketCore.scala:616:25, :626:40] wire _mem_br_target_sign_T_1 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_4 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_2 = _mem_br_target_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign = _mem_br_target_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire mem_br_target_hi_hi_hi = mem_br_target_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_1 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_4 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_2 = _mem_br_target_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20 = {11{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo = mem_br_target_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_3 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_8 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_4 = _mem_br_target_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12 = {8{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] mem_br_target_hi_lo_hi = mem_br_target_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_4 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_3 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_15 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_11 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_5 = _mem_br_target_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_7 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_1 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_18 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_9 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_8 = _mem_br_target_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _mem_br_target_b11_T_9 = _mem_br_target_b11_T_8; // @[RocketCore.scala:1346:{18,43}] wire _mem_br_target_b11_T_10 = _mem_br_target_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18] wire mem_br_target_b11 = _mem_br_target_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo = mem_br_target_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _mem_br_target_b10_5_T_3 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] _mem_br_target_b10_5_T_7 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] mem_br_target_b10_5 = _mem_br_target_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_4 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_14 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_9 = _mem_br_target_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _mem_br_target_b4_1_T_6 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_16 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_7 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_17 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_8 = _mem_br_target_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] mem_br_target_b4_1 = _mem_br_target_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _mem_br_target_b0_T_5 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire _mem_br_target_b0_T_13 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire [9:0] mem_br_target_lo_hi = {mem_br_target_b10_5, mem_br_target_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo = {mem_br_target_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo = {mem_br_target_hi_lo_hi, mem_br_target_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi = {mem_br_target_hi_hi_hi, mem_br_target_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi = {mem_br_target_hi_hi, mem_br_target_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_2 = {mem_br_target_hi, mem_br_target_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_3 = _mem_br_target_T_2; // @[RocketCore.scala:1355:{8,53}] wire _mem_br_target_sign_T_5 = _mem_br_target_sign_T_4; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign_1 = _mem_br_target_sign_T_5; // @[RocketCore.scala:1341:{19,49}] wire _mem_br_target_b11_T_20 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1346:18] wire mem_br_target_hi_hi_hi_1 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_5 = _mem_br_target_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20_1 = {11{mem_br_target_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo_1 = mem_br_target_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_9 = _mem_br_target_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12_1 = _mem_br_target_b19_12_T_9; // @[RocketCore.scala:1343:{21,73}] wire [7:0] mem_br_target_hi_lo_hi_1 = mem_br_target_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_16 = _mem_br_target_b11_T_15; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_21 = _mem_br_target_b11_T_16; // @[RocketCore.scala:1345:{18,44}] wire _mem_br_target_b11_T_19 = _mem_br_target_b11_T_18; // @[RocketCore.scala:1346:{39,43}] wire mem_br_target_b11_1 = _mem_br_target_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo_1 = mem_br_target_b11_1; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] mem_br_target_b10_5_1 = _mem_br_target_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_18 = _mem_br_target_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _mem_br_target_b4_1_T_19 = _mem_br_target_b4_1_T_18; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] mem_br_target_b4_1_1 = _mem_br_target_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19] wire [9:0] mem_br_target_lo_hi_1 = {mem_br_target_b10_5_1, mem_br_target_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo_1 = {mem_br_target_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo_1 = {mem_br_target_hi_lo_hi_1, mem_br_target_hi_lo_lo_1}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi_1 = {mem_br_target_hi_hi_hi_1, mem_br_target_hi_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi_1 = {mem_br_target_hi_hi_1, mem_br_target_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_4 = {mem_br_target_hi_1, mem_br_target_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_5 = _mem_br_target_T_4; // @[RocketCore.scala:1355:{8,53}] wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:266:36, :618:8] wire [31:0] _mem_br_target_T_7 = mem_ctrl_jal ? _mem_br_target_T_5 : {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6}; // @[RocketCore.scala:244:21, :617:8, :618:8, :1355:53] wire [31:0] _mem_br_target_T_8 = _mem_br_target_T_1 ? _mem_br_target_T_3 : _mem_br_target_T_7; // @[RocketCore.scala:616:{8,25}, :617:8, :1355:53] wire [40:0] _mem_br_target_T_9 = {_mem_br_target_T[39], _mem_br_target_T} + {{9{_mem_br_target_T_8[31]}}, _mem_br_target_T_8}; // @[RocketCore.scala:615:{34,41}, :616:8] wire [39:0] _mem_br_target_T_10 = _mem_br_target_T_9[39:0]; // @[RocketCore.scala:615:41] wire [39:0] mem_br_target = _mem_br_target_T_10; // @[RocketCore.scala:615:41] wire _mem_npc_T = mem_ctrl_jalr \| mem_reg_sfence; // @[RocketCore.scala:244:21, :276:27, :619:36] wire [24:0] _mem_npc_a_T = mem_reg_wdata[63:39]; // @[RocketCore.scala:282:26, :1293:17] wire [24:0] mem_npc_a = _mem_npc_a_T; // @[RocketCore.scala:1293:{17,23}] wire _mem_npc_msb_T = mem_npc_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _mem_npc_msb_T_1 = &mem_npc_a; // @[RocketCore.scala:1293:23, :1294:34] wire _mem_npc_msb_T_2 = _mem_npc_msb_T \| _mem_npc_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _mem_npc_msb_T_3 = mem_reg_wdata[39]; // @[RocketCore.scala:282:26, :1294:46] wire _mem_npc_msb_T_4 = mem_reg_wdata[38]; // @[RocketCore.scala:282:26, :1294:54] wire _mem_npc_msb_T_5 = ~_mem_npc_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire mem_npc_msb = _mem_npc_msb_T_2 ? _mem_npc_msb_T_3 : _mem_npc_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [39:0] _mem_npc_T_2 = {mem_npc_msb, _mem_npc_T_1}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _mem_npc_T_3 = _mem_npc_T_2; // @[RocketCore.scala:619:106, :1295:8] wire [39:0] _mem_npc_T_4 = _mem_npc_T ? _mem_npc_T_3 : mem_br_target; // @[RocketCore.scala:615:41, :619:{21,36,106}] wire [39:0] _mem_npc_T_5 = _mem_npc_T_4 & 40'hFFFFFFFFFE; // @[RocketCore.scala:619:{21,129}] wire [39:0] _mem_npc_T_6 = _mem_npc_T_5; // @[RocketCore.scala:619:129] wire [39:0] mem_npc = _mem_npc_T_6; // @[RocketCore.scala:619:{129,139}] wire _mem_wrong_npc_T = mem_npc != ex_reg_pc; // @[RocketCore.scala:256:22, :619:139, :621:30] wire _mem_wrong_npc_T_1 = _ibuf_io_inst_0_valid \| io_imem_resp_valid_0; // @[RocketCore.scala:153:7, :311:20, :622:31] wire _mem_wrong_npc_T_2 = mem_npc != _ibuf_io_pc; // @[RocketCore.scala:311:20, :619:139, :622:62] wire _mem_wrong_npc_T_3 = ~_mem_wrong_npc_T_1 \| _mem_wrong_npc_T_2; // @[RocketCore.scala:622:{8,31,62}] assign mem_wrong_npc = ex_pc_valid ? _mem_wrong_npc_T : _mem_wrong_npc_T_3; // @[RocketCore.scala:595:51, :621:{8,30}, :622:8] assign io_imem_bht_update_bits_mispredict_0 = mem_wrong_npc; // @[RocketCore.scala:153:7, :621:8] wire _mem_npc_misaligned_T_1 = ~_mem_npc_misaligned_T; // @[RocketCore.scala:623:{28,46}] wire _mem_npc_misaligned_T_2 = mem_npc[1]; // @[RocketCore.scala:619:139, :623:66] wire _mem_npc_misaligned_T_3 = _mem_npc_misaligned_T_1 & _mem_npc_misaligned_T_2; // @[RocketCore.scala:623:{28,56,66}] wire _mem_npc_misaligned_T_4 = ~mem_reg_sfence; // @[RocketCore.scala:276:27, :623:73] wire mem_npc_misaligned = _mem_npc_misaligned_T_3 & _mem_npc_misaligned_T_4; // @[RocketCore.scala:623:{56,70,73}] wire _mem_int_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27] wire _mem_int_wdata_T_1 = mem_ctrl_jalr ^ mem_npc_misaligned; // @[RocketCore.scala:244:21, :623:70, :624:59] wire _mem_int_wdata_T_2 = _mem_int_wdata_T & _mem_int_wdata_T_1; // @[RocketCore.scala:624:{27,41,59}] wire [63:0] _mem_int_wdata_T_4 = _mem_int_wdata_T_2 ? {{24{mem_br_target[39]}}, mem_br_target} : _mem_int_wdata_T_3; // @[RocketCore.scala:615:41, :624:{26,41,111}] wire [63:0] mem_int_wdata = _mem_int_wdata_T_4; // @[RocketCore.scala:624:{26,119}] wire _mem_cfi_T = mem_ctrl_branch \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :625:33] assign mem_cfi = _mem_cfi_T \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :625:{33,50}] assign io_imem_btb_update_bits_isValid_0 = mem_cfi; // @[RocketCore.scala:153:7, :625:50] wire _mem_cfi_taken_T_1 = _mem_cfi_taken_T \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :626:{40,57}] wire mem_cfi_taken = _mem_cfi_taken_T_1 \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :626:{57,74}] wire _mem_direction_misprediction_T_1 = mem_br_taken != _mem_direction_misprediction_T; // @[RocketCore.scala:284:25, :627:{69,85}] wire mem_direction_misprediction = mem_ctrl_branch & _mem_direction_misprediction_T_1; // @[RocketCore.scala:244:21, :627:{53,69}] wire _take_pc_mem_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :629:35] wire _take_pc_mem_T_1 = mem_reg_valid & _take_pc_mem_T; // @[RocketCore.scala:265:36, :629:{32,35}] wire _take_pc_mem_T_2 = mem_wrong_npc \| mem_reg_sfence; // @[RocketCore.scala:276:27, :621:8, :629:71] assign _take_pc_mem_T_3 = _take_pc_mem_T_1 & _take_pc_mem_T_2; // @[RocketCore.scala:629:{32,49,71}] assign take_pc_mem = _take_pc_mem_T_3; // @[RocketCore.scala:285:25, :629:49] wire _mem_reg_valid_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20] wire _mem_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :632:21] wire _mem_reg_replay_T_1 = _mem_reg_replay_T & replay_ex; // @[RocketCore.scala:601:33, :632:{21,37}] wire _mem_reg_xcpt_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20, :633:19] wire _mem_reg_xcpt_T_1 = _mem_reg_xcpt_T & ex_xcpt; // @[RocketCore.scala:633:{19,31}, :1278:14] wire _mem_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :634:29] wire _mem_reg_xcpt_interrupt_T_1 = _mem_reg_xcpt_interrupt_T & ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :634:{29,45}] wire _GEN_49 = ex_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _mem_reg_load_T; // @[package.scala:16:47] assign _mem_reg_load_T = _GEN_49; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = ex_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _mem_reg_load_T_1; // @[package.scala:16:47] assign _mem_reg_load_T_1 = _GEN_50; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_1 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = ex_ctrl_mem_cmd == 5'h6; // @[package.scala:16:47] wire _mem_reg_load_T_2; // @[package.scala:16:47] assign _mem_reg_load_T_2 = _GEN_51; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_2 = _GEN_51; // @[package.scala:16:47] wire _mem_reg_load_T_4 = _mem_reg_load_T \| _mem_reg_load_T_1; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_5 = _mem_reg_load_T_4 \| _mem_reg_load_T_2; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_6 = _mem_reg_load_T_5 \| _mem_reg_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_52 = ex_ctrl_mem_cmd == 5'h4; // @[package.scala:16:47] wire _mem_reg_load_T_7; // @[package.scala:16:47] assign _mem_reg_load_T_7 = _GEN_52; // @[package.scala:16:47] wire _mem_reg_store_T_5; // @[package.scala:16:47] assign _mem_reg_store_T_5 = _GEN_52; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_7; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_7 = _GEN_52; // @[package.scala:16:47] wire _GEN_53 = ex_ctrl_mem_cmd == 5'h9; // @[package.scala:16:47] wire _mem_reg_load_T_8; // @[package.scala:16:47] assign _mem_reg_load_T_8 = _GEN_53; // @[package.scala:16:47] wire _mem_reg_store_T_6; // @[package.scala:16:47] assign _mem_reg_store_T_6 = _GEN_53; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_8 = _GEN_53; // @[package.scala:16:47] wire _GEN_54 = ex_ctrl_mem_cmd == 5'hA; // @[package.scala:16:47] wire _mem_reg_load_T_9; // @[package.scala:16:47] assign _mem_reg_load_T_9 = _GEN_54; // @[package.scala:16:47] wire _mem_reg_store_T_7; // @[package.scala:16:47] assign _mem_reg_store_T_7 = _GEN_54; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_9 = _GEN_54; // @[package.scala:16:47] wire _GEN_55 = ex_ctrl_mem_cmd == 5'hB; // @[package.scala:16:47] wire _mem_reg_load_T_10; // @[package.scala:16:47] assign _mem_reg_load_T_10 = _GEN_55; // @[package.scala:16:47] wire _mem_reg_store_T_8; // @[package.scala:16:47] assign _mem_reg_store_T_8 = _GEN_55; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_10 = _GEN_55; // @[package.scala:16:47] wire _mem_reg_load_T_11 = _mem_reg_load_T_7 \| _mem_reg_load_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_12 = _mem_reg_load_T_11 \| _mem_reg_load_T_9; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_13 = _mem_reg_load_T_12 \| _mem_reg_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_56 = ex_ctrl_mem_cmd == 5'h8; // @[package.scala:16:47] wire _mem_reg_load_T_14; // @[package.scala:16:47] assign _mem_reg_load_T_14 = _GEN_56; // @[package.scala:16:47] wire _mem_reg_store_T_12; // @[package.scala:16:47] assign _mem_reg_store_T_12 = _GEN_56; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_14; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_14 = _GEN_56; // @[package.scala:16:47] wire _GEN_57 = ex_ctrl_mem_cmd == 5'hC; // @[package.scala:16:47] wire _mem_reg_load_T_15; // @[package.scala:16:47] assign _mem_reg_load_T_15 = _GEN_57; // @[package.scala:16:47] wire _mem_reg_store_T_13; // @[package.scala:16:47] assign _mem_reg_store_T_13 = _GEN_57; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_15 = _GEN_57; // @[package.scala:16:47] wire _GEN_58 = ex_ctrl_mem_cmd == 5'hD; // @[package.scala:16:47] wire _mem_reg_load_T_16; // @[package.scala:16:47] assign _mem_reg_load_T_16 = _GEN_58; // @[package.scala:16:47] wire _mem_reg_store_T_14; // @[package.scala:16:47] assign _mem_reg_store_T_14 = _GEN_58; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_16 = _GEN_58; // @[package.scala:16:47] wire _GEN_59 = ex_ctrl_mem_cmd == 5'hE; // @[package.scala:16:47] wire _mem_reg_load_T_17; // @[package.scala:16:47] assign _mem_reg_load_T_17 = _GEN_59; // @[package.scala:16:47] wire _mem_reg_store_T_15; // @[package.scala:16:47] assign _mem_reg_store_T_15 = _GEN_59; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_17 = _GEN_59; // @[package.scala:16:47] wire _GEN_60 = ex_ctrl_mem_cmd == 5'hF; // @[package.scala:16:47] wire _mem_reg_load_T_18; // @[package.scala:16:47] assign _mem_reg_load_T_18 = _GEN_60; // @[package.scala:16:47] wire _mem_reg_store_T_16; // @[package.scala:16:47] assign _mem_reg_store_T_16 = _GEN_60; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_18 = _GEN_60; // @[package.scala:16:47] wire _mem_reg_load_T_19 = _mem_reg_load_T_14 \| _mem_reg_load_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_20 = _mem_reg_load_T_19 \| _mem_reg_load_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_21 = _mem_reg_load_T_20 \| _mem_reg_load_T_17; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_22 = _mem_reg_load_T_21 \| _mem_reg_load_T_18; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_23 = _mem_reg_load_T_13 \| _mem_reg_load_T_22; // @[package.scala:81:59] wire _mem_reg_load_T_24 = _mem_reg_load_T_6 \| _mem_reg_load_T_23; // @[package.scala:81:59] wire _mem_reg_load_T_25 = ex_ctrl_mem & _mem_reg_load_T_24; // @[RocketCore.scala:243:20, :643:33] wire _mem_reg_store_T = ex_ctrl_mem_cmd == 5'h1; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_1 = ex_ctrl_mem_cmd == 5'h11; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_2 = _mem_reg_store_T \| _mem_reg_store_T_1; // @[Consts.scala:90:{32,42,49}] wire _mem_reg_store_T_4 = _mem_reg_store_T_2 \| _mem_reg_store_T_3; // @[Consts.scala:90:{42,59,66}] wire _mem_reg_store_T_9 = _mem_reg_store_T_5 \| _mem_reg_store_T_6; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_10 = _mem_reg_store_T_9 \| _mem_reg_store_T_7; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_11 = _mem_reg_store_T_10 \| _mem_reg_store_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_17 = _mem_reg_store_T_12 \| _mem_reg_store_T_13; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_18 = _mem_reg_store_T_17 \| _mem_reg_store_T_14; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_19 = _mem_reg_store_T_18 \| _mem_reg_store_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_20 = _mem_reg_store_T_19 \| _mem_reg_store_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_21 = _mem_reg_store_T_11 \| _mem_reg_store_T_20; // @[package.scala:81:59] wire _mem_reg_store_T_22 = _mem_reg_store_T_4 \| _mem_reg_store_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _mem_reg_store_T_23 = ex_ctrl_mem & _mem_reg_store_T_22; // @[RocketCore.scala:243:20, :644:34] wire [1:0] size = ex_ctrl_rocc ? 2'h3 : ex_reg_mem_size; // @[RocketCore.scala:243:20, :257:28, :664:21] wire [1:0] mem_reg_rs2_size = size; // @[RocketCore.scala:664:21] wire _mem_reg_rs2_T = mem_reg_rs2_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _mem_reg_rs2_T_1 = mem_reg_rs2_dat_padded[7:0]; // @[AMOALU.scala:13:27, :29:69] wire [15:0] _mem_reg_rs2_T_2 = {2{_mem_reg_rs2_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _mem_reg_rs2_T_3 = {2{_mem_reg_rs2_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _mem_reg_rs2_T_4 = {2{_mem_reg_rs2_T_3}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_5 = mem_reg_rs2_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _mem_reg_rs2_T_6 = mem_reg_rs2_dat_padded[15:0]; // @[AMOALU.scala:13:27, :29:69] wire [31:0] _mem_reg_rs2_T_7 = {2{_mem_reg_rs2_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_8 = {2{_mem_reg_rs2_T_7}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_9 = mem_reg_rs2_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _mem_reg_rs2_T_10 = mem_reg_rs2_dat_padded[31:0]; // @[AMOALU.scala:13:27, :29:69] wire [63:0] _mem_reg_rs2_T_11 = {2{_mem_reg_rs2_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_12 = _mem_reg_rs2_T_9 ? _mem_reg_rs2_T_11 : mem_reg_rs2_dat_padded; // @[AMOALU.scala:13:27, :29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_13 = _mem_reg_rs2_T_5 ? _mem_reg_rs2_T_8 : _mem_reg_rs2_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_14 = _mem_reg_rs2_T ? _mem_reg_rs2_T_4 : _mem_reg_rs2_T_13; // @[AMOALU.scala:29:{13,19,32}] wire _mem_breakpoint_T = mem_reg_load & _bpu_io_xcpt_ld; // @[RocketCore.scala:273:36, :414:19, :677:38] wire _mem_breakpoint_T_1 = mem_reg_store & _bpu_io_xcpt_st; // @[RocketCore.scala:274:36, :414:19, :677:75] wire mem_breakpoint = _mem_breakpoint_T \| _mem_breakpoint_T_1; // @[RocketCore.scala:677:{38,57,75}] wire _mem_debug_breakpoint_T = mem_reg_load & _bpu_io_debug_ld; // @[RocketCore.scala:273:36, :414:19, :678:44] wire _mem_debug_breakpoint_T_1 = mem_reg_store & _bpu_io_debug_st; // @[RocketCore.scala:274:36, :414:19, :678:82] wire mem_debug_breakpoint = _mem_debug_breakpoint_T \| _mem_debug_breakpoint_T_1; // @[RocketCore.scala:678:{44,64,82}] wire mem_ldst_xcpt = mem_debug_breakpoint \| mem_breakpoint; // @[RocketCore.scala:677:57, :678:64, :1278:{14,35}] wire [3:0] mem_ldst_cause = mem_debug_breakpoint ? 4'hE : 4'h3; // @[Mux.scala:50:70] wire _T_74 = mem_reg_xcpt_interrupt \| mem_reg_xcpt; // @[RocketCore.scala:264:36, :268:36, :684:29] wire _T_75 = mem_reg_valid & mem_npc_misaligned; // @[RocketCore.scala:265:36, :623:70, :685:20] wire mem_xcpt = _T_74 \| _T_75 \| mem_reg_valid & mem_ldst_xcpt; // @[RocketCore.scala:265:36, :684:29, :685:20, :686:20, :1278:{14,35}] wire [63:0] mem_cause = _T_74 ? mem_reg_cause : {60'h0, _T_75 ? 4'h0 : mem_ldst_cause}; // @[Mux.scala:50:70] wire dcache_kill_mem = _dcache_kill_mem_T & io_dmem_replay_next_0; // @[RocketCore.scala:153:7, :695:{39,55}] wire _fpu_kill_mem_T = mem_reg_valid & mem_ctrl_fp; // @[RocketCore.scala:244:21, :265:36, :696:36] wire fpu_kill_mem = _fpu_kill_mem_T & io_fpu_nack_mem_0; // @[RocketCore.scala:153:7, :696:{36,51}] wire _vec_kill_mem_T = mem_reg_valid & mem_ctrl_mem; // @[RocketCore.scala:244:21, :265:36, :697:36] wire _replay_mem_T = dcache_kill_mem \| mem_reg_replay; // @[RocketCore.scala:269:36, :695:55, :699:37] wire _replay_mem_T_1 = _replay_mem_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :699:{37,55}] wire _replay_mem_T_2 = _replay_mem_T_1; // @[RocketCore.scala:699:{55,71}] wire replay_mem = _replay_mem_T_2; // @[RocketCore.scala:699:{71,87}] wire _killm_common_T = dcache_kill_mem \| take_pc_wb; // @[RocketCore.scala:304:24, :695:55, :700:38] wire _killm_common_T_1 = _killm_common_T \| mem_reg_xcpt; // @[RocketCore.scala:268:36, :700:{38,52}] wire _killm_common_T_2 = ~mem_reg_valid; // @[RocketCore.scala:265:36, :700:71] assign killm_common = _killm_common_T_1 \| _killm_common_T_2; // @[RocketCore.scala:700:{52,68,71}] assign io_fpu_killm_0 = killm_common; // @[RocketCore.scala:153:7, :700:68] wire _div_io_kill_T = _div_io_req_ready & _div_io_req_valid_T; // @[Decoupled.scala:51:35] reg div_io_kill_REG; // @[RocketCore.scala:701:41] wire _div_io_kill_T_1 = killm_common & div_io_kill_REG; // @[RocketCore.scala:700:68, :701:{31,41}] wire _ctrl_killm_T = killm_common \| mem_xcpt; // @[RocketCore.scala:700:68, :702:33, :1278:14] wire _ctrl_killm_T_1 = _ctrl_killm_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :702:{33,45}] wire ctrl_killm = _ctrl_killm_T_1; // @[RocketCore.scala:702:{45,61}] wire _wb_reg_valid_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19] wire _wb_reg_replay_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34] wire _wb_reg_replay_T_1 = replay_mem & _wb_reg_replay_T; // @[RocketCore.scala:699:87, :706:{31,34}] wire _wb_reg_xcpt_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :707:30] wire _wb_reg_xcpt_T_1 = mem_xcpt & _wb_reg_xcpt_T; // @[RocketCore.scala:707:{27,30}, :1278:14] wire _wb_reg_xcpt_T_3 = _wb_reg_xcpt_T_1; // @[RocketCore.scala:707:{27,42}] wire _wb_reg_flush_pipe_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19, :708:24] wire _wb_reg_flush_pipe_T_1 = _wb_reg_flush_pipe_T & mem_reg_flush_pipe; // @[RocketCore.scala:270:36, :708:{24,36}] wire _wb_reg_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :712:25] wire _wb_reg_wdata_T_1 = _wb_reg_wdata_T & mem_ctrl_fp; // @[RocketCore.scala:244:21, :712:{25,39}] wire _wb_reg_wdata_T_2 = _wb_reg_wdata_T_1 & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :712:{39,54}] wire [63:0] _wb_reg_wdata_T_3 = _wb_reg_wdata_T_2 ? io_fpu_toint_data_0 : mem_int_wdata; // @[RocketCore.scala:153:7, :624:119, :712:{24,54}] wire _wb_reg_hfence_v_T = mem_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:244:21, :721:41] wire _wb_reg_hfence_g_T = mem_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:244:21, :722:41] wire _T_113 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala:245:20, :288:35, :730:19] wire _T_100 = _T_113 & io_dmem_s2_xcpt_pf_st_0; // @[RocketCore.scala:153:7, :730:{19,34}] wire _T_102 = _T_113 & io_dmem_s2_xcpt_pf_ld_0; // @[RocketCore.scala:153:7, :730:19, :731:34] wire _T_108 = _T_113 & io_dmem_s2_xcpt_ae_st_0; // @[RocketCore.scala:153:7, :730:19, :734:34] wire _T_110 = _T_113 & io_dmem_s2_xcpt_ae_ld_0; // @[RocketCore.scala:153:7, :730:19, :735:34] wire _T_112 = _T_113 & io_dmem_s2_xcpt_ma_st_0; // @[RocketCore.scala:153:7, :730:19, :736:34] wire wb_xcpt = wb_reg_xcpt \| _T_100 \| _T_102 \| _T_108 \| _T_110 \| _T_112 \| _T_113 & io_dmem_s2_xcpt_ma_ld_0; // @[RocketCore.scala:153:7, :289:35, :730:{19,34}, :731:34, :734:34, :735:34, :736:34, :737:34, :1278:{14,35}] wire [63:0] wb_cause = wb_reg_xcpt ? wb_reg_cause : {59'h0, _T_100 ? 5'hF : _T_102 ? 5'hD : {2'h0, _T_108 ? 3'h7 : _T_110 ? 3'h5 : {1'h1, _T_112, 1'h0}}}; // @[Mux.scala:50:70] wire _wb_pc_valid_T = wb_reg_valid \| wb_reg_replay; // @[RocketCore.scala:288:35, :290:35, :754:34] wire wb_pc_valid = _wb_pc_valid_T \| wb_reg_xcpt; // @[RocketCore.scala:289:35, :754:{34,51}] wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :288:35, :755:29] wire _wb_set_sboard_T = wb_ctrl_div \| wb_dcache_miss; // @[RocketCore.scala:245:20, :596:36, :756:35] wire _wb_set_sboard_T_1 = _wb_set_sboard_T \| wb_ctrl_rocc; // @[RocketCore.scala:245:20, :756:{35,53}] wire wb_set_sboard = _wb_set_sboard_T_1 \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :756:{53,69}] wire replay_wb_common = io_dmem_s2_nack_0 \| wb_reg_replay; // @[RocketCore.scala:153:7, :290:35, :757:42] wire replay_wb_rocc = _replay_wb_rocc_T; // @[RocketCore.scala:758:{37,53}] wire _replay_wb_T = replay_wb_common \| replay_wb_rocc; // @[RocketCore.scala:757:42, :758:53, :761:36] wire _replay_wb_T_1 = _replay_wb_T; // @[RocketCore.scala:761:{36,54}] wire replay_wb = _replay_wb_T_1; // @[RocketCore.scala:761:{54,71}] wire _take_pc_wb_T = replay_wb \| wb_xcpt; // @[RocketCore.scala:761:71, :762:27, :1278:14] wire _take_pc_wb_T_1 = _take_pc_wb_T \| _csr_io_eret; // @[RocketCore.scala:341:19, :762:{27,38}] assign _take_pc_wb_T_2 = _take_pc_wb_T_1 \| wb_reg_flush_pipe; // @[RocketCore.scala:291:35, :762:{38,53}] assign take_pc_wb = _take_pc_wb_T_2; // @[RocketCore.scala:304:24, :762:53] wire _dmem_resp_xpu_T = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45] wire dmem_resp_fpu = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45, :766:45] wire dmem_resp_xpu = ~_dmem_resp_xpu_T; // @[RocketCore.scala:765:{23,45}] assign dmem_resp_waddr = io_dmem_resp_bits_tag_0[5:1]; // @[RocketCore.scala:153:7, :767:46] assign io_fpu_ll_resp_tag_0 = dmem_resp_waddr; // @[RocketCore.scala:153:7, :767:46] wire dmem_resp_valid = io_dmem_resp_valid_0 & io_dmem_resp_bits_has_data_0; // @[RocketCore.scala:153:7, :768:44] wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay_0; // @[RocketCore.scala:153:7, :768:44, :769:42] wire [63:0] ll_wdata; // @[RocketCore.scala:779:26] wire [4:0] ll_waddr; // @[RocketCore.scala:780:26] wire _ll_wen_T = ll_arb_io_out_ready & _ll_arb_io_out_valid; // @[Decoupled.scala:51:35] wire ll_wen; // @[RocketCore.scala:781:24] wire _ll_arb_io_out_ready_T = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26] wire _T_143 = dmem_resp_replay & dmem_resp_xpu; // @[RocketCore.scala:765:23, :769:42, :809:26] assign ll_arb_io_out_ready = ~_T_143 & _ll_arb_io_out_ready_T; // @[RocketCore.scala:782:{23,26}, :809:{26,44}, :810:25] assign ll_waddr = _T_143 ? dmem_resp_waddr : _ll_arb_io_out_bits_tag; // @[RocketCore.scala:767:46, :776:22, :780:26, :809:{26,44}, :811:14] assign ll_wen = _T_143 \| _ll_wen_T; // @[Decoupled.scala:51:35] wire _wb_valid_T = ~replay_wb; // @[RocketCore.scala:761:71, :815:34] wire _wb_valid_T_1 = wb_reg_valid & _wb_valid_T; // @[RocketCore.scala:288:35, :815:{31,34}] wire _wb_valid_T_2 = ~wb_xcpt; // @[RocketCore.scala:815:48, :1278:14] wire wb_valid = _wb_valid_T_1 & _wb_valid_T_2; // @[RocketCore.scala:815:{31,45,48}] wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :815:45, :816:25] wire rf_wen = wb_wen \| ll_wen; // @[RocketCore.scala:781:24, :816:25, :817:23] wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_waddr; // @[RocketCore.scala:455:36, :780:26, :781:24, :818:21] wire [4:0] xrfWriteBundle_wrdst = rf_waddr; // @[RocketCore.scala:818:21, :1249:28] wire _rf_wdata_T = dmem_resp_valid & dmem_resp_xpu; // @[RocketCore.scala:765:23, :768:44, :819:38] wire _rf_wdata_T_2 = \|wb_ctrl_csr; // @[RocketCore.scala:245:20, :821:34] wire [63:0] _rf_wdata_T_4 = _rf_wdata_T_2 ? _csr_io_rw_rdata : _rf_wdata_T_3; // @[RocketCore.scala:341:19, :821:{21,34}, :822:21] wire [63:0] _rf_wdata_T_5 = ll_wen ? ll_wdata : _rf_wdata_T_4; // @[RocketCore.scala:779:26, :781:24, :820:21, :821:21] wire [63:0] rf_wdata = _rf_wdata_T ? _rf_wdata_T_1 : _rf_wdata_T_5; // @[RocketCore.scala:819:{21,38,78}, :820:21] wire [63:0] coreMonitorBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1186:31] wire [63:0] xrfWriteBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1249:28] wire [63:0] _id_rs_T_4; // @[RocketCore.scala:1326:25] assign id_rs_0 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr1 ? rf_wdata : _id_rs_T_4; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [63:0] _id_rs_T_9; // @[RocketCore.scala:1326:25] assign id_rs_1 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr2 ? rf_wdata : _id_rs_T_9; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [1:0] _csr_io_inst_0_T = wb_reg_raw_inst[1:0]; // @[RocketCore.scala:301:28, :832:66] wire _csr_io_inst_0_T_1 = &_csr_io_inst_0_T; // @[RocketCore.scala:832:{66,73}] wire [15:0] _csr_io_inst_0_T_2 = wb_reg_inst[31:16]; // @[RocketCore.scala:300:24, :832:91] wire [15:0] _csr_io_inst_0_T_3 = _csr_io_inst_0_T_1 ? _csr_io_inst_0_T_2 : 16'h0; // @[RocketCore.scala:832:{50,73,91}] wire [15:0] _csr_io_inst_0_T_4 = wb_reg_raw_inst[15:0]; // @[RocketCore.scala:301:28, :832:119] wire [31:0] _csr_io_inst_0_T_5 = {_csr_io_inst_0_T_3, _csr_io_inst_0_T_4}; // @[RocketCore.scala:832:{46,50,119}] wire [4:0] _csr_io_fcsr_flags_bits_T = {5{io_fpu_fcsr_flags_valid_0}}; // @[RocketCore.scala:153:7, :839:59] wire [4:0] _csr_io_fcsr_flags_bits_T_1 = io_fpu_fcsr_flags_bits_0 & _csr_io_fcsr_flags_bits_T; // @[RocketCore.scala:153:7, :839:{53,59}] wire [4:0] _csr_io_fcsr_flags_bits_T_4 = _csr_io_fcsr_flags_bits_T_1; // @[RocketCore.scala:839:{53,89}] wire [31:0] _io_fpu_time_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29] wire [31:0] _coreMonitorBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1191:41] wire [31:0] _xrfWriteBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1254:38] assign io_fpu_time_0 = {32'h0, _io_fpu_time_T}; // @[RocketCore.scala:153:7, :840:{15,29}] wire tval_dmem_addr = ~wb_reg_xcpt; // @[RocketCore.scala:289:35, :845:24] wire _tval_any_addr_T = wb_reg_cause == 64'h3; // @[package.scala:16:47] wire _tval_any_addr_T_1 = wb_reg_cause == 64'h1; // @[package.scala:16:47] wire _tval_any_addr_T_2 = wb_reg_cause == 64'hC; // @[package.scala:16:47] wire _GEN_61 = wb_reg_cause == 64'h14; // @[package.scala:16:47] wire _tval_any_addr_T_3; // @[package.scala:16:47] assign _tval_any_addr_T_3 = _GEN_61; // @[package.scala:16:47] wire _htval_valid_imem_T; // @[RocketCore.scala:853:56] assign _htval_valid_imem_T = _GEN_61; // @[package.scala:16:47] wire _tval_any_addr_T_4 = _tval_any_addr_T \| _tval_any_addr_T_1; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_5 = _tval_any_addr_T_4 \| _tval_any_addr_T_2; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_6 = _tval_any_addr_T_5 \| _tval_any_addr_T_3; // @[package.scala:16:47, :81:59] wire tval_any_addr = tval_dmem_addr \| _tval_any_addr_T_6; // @[package.scala:81:59] wire tval_inst = wb_reg_cause == 64'h2; // @[RocketCore.scala:292:35, :848:32] wire _tval_valid_T = tval_any_addr \| tval_inst; // @[RocketCore.scala:846:38, :848:32, :849:46] wire tval_valid = wb_xcpt & _tval_valid_T; // @[RocketCore.scala:849:{28,46}, :1278:14] wire _csr_io_gva_T = tval_any_addr & _csr_io_status_v; // @[RocketCore.scala:341:19, :846:38, :850:43] wire _csr_io_gva_T_1 = tval_dmem_addr & wb_reg_hls_or_dv; // @[RocketCore.scala:297:29, :845:24, :850:80] wire _csr_io_gva_T_2 = _csr_io_gva_T \| _csr_io_gva_T_1; // @[RocketCore.scala:850:{43,62,80}] wire _csr_io_gva_T_3 = wb_xcpt & _csr_io_gva_T_2; // @[RocketCore.scala:850:{25,62}, :1278:14] wire [24:0] _csr_io_tval_a_T = wb_reg_wdata[63:39]; // @[RocketCore.scala:302:25, :1293:17] wire [24:0] csr_io_tval_a = _csr_io_tval_a_T; // @[RocketCore.scala:1293:{17,23}] wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[RocketCore.scala:1293:23, :1294:34] wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T \| _csr_io_tval_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _csr_io_tval_msb_T_3 = wb_reg_wdata[39]; // @[RocketCore.scala:302:25, :1294:46] wire _csr_io_tval_msb_T_4 = wb_reg_wdata[38]; // @[RocketCore.scala:302:25, :1294:54] wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] assign io_imem_sfence_bits_addr_0 = wb_reg_wdata[38:0]; // @[RocketCore.scala:153:7, :302:25, :1295:16] wire [38:0] _csr_io_tval_T = wb_reg_wdata[38:0]; // @[RocketCore.scala:302:25, :1295:16] wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _csr_io_tval_T_2 = tval_valid ? _csr_io_tval_T_1 : 40'h0; // @[RocketCore.scala:849:28, :851:21, :1295:8] wire htval_valid_imem = wb_reg_xcpt & _htval_valid_imem_T; // @[RocketCore.scala:289:35, :853:{40,56}] wire [39:0] htval_imem = htval_valid_imem ? io_imem_gpa_bits_0 : 40'h0; // @[RocketCore.scala:153:7, :853:40, :854:25] wire [39:0] _htval_T = htval_imem; // @[RocketCore.scala:854:25, :860:29] wire _htval_valid_dmem_T = wb_xcpt & tval_dmem_addr; // @[RocketCore.scala:845:24, :857:36, :1278:14] wire [1:0] _htval_valid_dmem_T_4 = {io_dmem_s2_xcpt_pf_ld_0, io_dmem_s2_xcpt_pf_st_0}; // @[RocketCore.scala:153:7, :857:110] wire _htval_valid_dmem_T_5 = \|_htval_valid_dmem_T_4; // @[RocketCore.scala:857:{110,117}] wire _htval_valid_dmem_T_6 = ~_htval_valid_dmem_T_5; // @[RocketCore.scala:857:{90,117}] wire [39:0] htval = _htval_T; // @[RocketCore.scala:860:{29,43}] wire _mhtinst_read_pseudo_T = io_imem_gpa_is_pte_0 & htval_valid_imem; // @[RocketCore.scala:153:7, :853:40, :862:51] wire mhtinst_read_pseudo = _mhtinst_read_pseudo_T; // @[RocketCore.scala:862:{51,72}] wire [11:0] _csr_io_rw_addr_T = wb_reg_inst[31:20]; // @[RocketCore.scala:300:24, :909:32] wire [2:0] _csr_io_rw_cmd_T = {~wb_reg_valid, 2'h0}; // @[RocketCore.scala:288:35] wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}] wire [2:0] _csr_io_rw_cmd_T_2 = wb_ctrl_csr & _csr_io_rw_cmd_T_1; // @[RocketCore.scala:245:20] assign io_bpwatch_0_action_0 = {2'h0, _csr_io_bp_0_control_action}; // @[RocketCore.scala:153:7, :341:19, :962:18] wire _hazard_targets_T = \|id_raddr1; // @[RocketCore.scala:326:72, :969:55, :1326:41] wire hazard_targets_0_1 = id_ctrl_rxs1 & _hazard_targets_T; // @[RocketCore.scala:321:21, :969:{42,55}] wire _hazard_targets_T_1 = \|id_raddr2; // @[RocketCore.scala:326:72, :970:55, :1326:41] wire hazard_targets_1_1 = id_ctrl_rxs2 & _hazard_targets_T_1; // @[RocketCore.scala:321:21, :970:{42,55}] wire _hazard_targets_T_2 = \|id_waddr; // @[RocketCore.scala:326:72, :971:55] wire hazard_targets_2_1 = id_ctrl_wxd & _hazard_targets_T_2; // @[RocketCore.scala:321:21, :971:{42,55}] reg [31:0] _r; // @[RocketCore.scala:1305:29] wire [30:0] _r_T = _r[31:1]; // @[RocketCore.scala:1305:29, :1306:35] wire [31:0] r = {_r_T, 1'h0}; // @[RocketCore.scala:1306:{35,40}] wire [31:0] _GEN_62 = {27'h0, id_raddr1}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T = r >> _GEN_62; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_1 = _id_sboard_hazard_T[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_2 = ll_waddr == id_raddr1; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_3 = ll_wen & _id_sboard_hazard_T_2; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_4 = ~_id_sboard_hazard_T_3; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_5 = _id_sboard_hazard_T_1 & _id_sboard_hazard_T_4; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_6 = hazard_targets_0_1 & _id_sboard_hazard_T_5; // @[RocketCore.scala:969:42, :984:77, :1287:27] wire [31:0] _GEN_63 = {27'h0, id_raddr2}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_63; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_8 = _id_sboard_hazard_T_7[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_9 = ll_waddr == id_raddr2; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_10 = ll_wen & _id_sboard_hazard_T_9; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_11 = ~_id_sboard_hazard_T_10; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_12 = _id_sboard_hazard_T_8 & _id_sboard_hazard_T_11; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_13 = hazard_targets_1_1 & _id_sboard_hazard_T_12; // @[RocketCore.scala:970:42, :984:77, :1287:27] wire [31:0] _GEN_64 = {27'h0, id_waddr}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_64; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_15 = _id_sboard_hazard_T_14[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_16 = ll_waddr == id_waddr; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_17 = ll_wen & _id_sboard_hazard_T_16; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_18 = ~_id_sboard_hazard_T_17; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_19 = _id_sboard_hazard_T_15 & _id_sboard_hazard_T_18; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_20 = hazard_targets_2_1 & _id_sboard_hazard_T_19; // @[RocketCore.scala:971:42, :984:77, :1287:27] wire _id_sboard_hazard_T_21 = _id_sboard_hazard_T_6 \| _id_sboard_hazard_T_13; // @[RocketCore.scala:1287:{27,50}] wire id_sboard_hazard = _id_sboard_hazard_T_21 \| _id_sboard_hazard_T_20; // @[RocketCore.scala:1287:{27,50}] wire [31:0] _id_stall_fpu_T_4 = 32'h1 << wb_waddr; // @[RocketCore.scala:455:36, :1309:58] wire _ex_cannot_bypass_T = \|ex_ctrl_csr; // @[RocketCore.scala:243:20, :988:38] wire _ex_cannot_bypass_T_1 = _ex_cannot_bypass_T \| ex_ctrl_jalr; // @[RocketCore.scala:243:20, :988:{38,48}] wire _ex_cannot_bypass_T_2 = _ex_cannot_bypass_T_1 \| ex_ctrl_mem; // @[RocketCore.scala:243:20, :988:{48,64}] wire _ex_cannot_bypass_T_3 = _ex_cannot_bypass_T_2 \| ex_ctrl_mul; // @[RocketCore.scala:243:20, :988:{64,79}] wire _ex_cannot_bypass_T_4 = _ex_cannot_bypass_T_3 \| ex_ctrl_div; // @[RocketCore.scala:243:20, :988:{79,94}] wire _ex_cannot_bypass_T_5 = _ex_cannot_bypass_T_4 \| ex_ctrl_fp; // @[RocketCore.scala:243:20, :988:{94,109}] wire _ex_cannot_bypass_T_6 = _ex_cannot_bypass_T_5 \| ex_ctrl_rocc; // @[RocketCore.scala:243:20, :988:{109,123}] wire ex_cannot_bypass = _ex_cannot_bypass_T_6; // @[RocketCore.scala:988:{123,139}] wire _data_hazard_ex_T_1 = hazard_targets_0_1 & _data_hazard_ex_T; // @[RocketCore.scala:969:42, :989:70, :1287:27] wire _data_hazard_ex_T_3 = hazard_targets_1_1 & _data_hazard_ex_T_2; // @[RocketCore.scala:970:42, :989:70, :1287:27] wire _GEN_65 = id_waddr == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :989:70] wire _data_hazard_ex_T_4; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_4 = _GEN_65; // @[RocketCore.scala:989:70] wire _fp_data_hazard_ex_T_7; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_7 = _GEN_65; // @[RocketCore.scala:989:70, :990:90] wire _data_hazard_ex_T_5 = hazard_targets_2_1 & _data_hazard_ex_T_4; // @[RocketCore.scala:971:42, :989:70, :1287:27] wire _data_hazard_ex_T_6 = _data_hazard_ex_T_1 \| _data_hazard_ex_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_ex_T_7 = _data_hazard_ex_T_6 \| _data_hazard_ex_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_ex = ex_ctrl_wxd & _data_hazard_ex_T_7; // @[RocketCore.scala:243:20, :989:36, :1287:50] wire _fp_data_hazard_ex_T = id_ctrl_fp & ex_ctrl_wfd; // @[RocketCore.scala:243:20, :321:21, :990:38] wire _fp_data_hazard_ex_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_ex_T_1; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_ex_T_3; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_5 = id_raddr3 == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :990:90] wire _fp_data_hazard_ex_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_ex_T_5; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_ex_T_7; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_9 = _fp_data_hazard_ex_T_2 \| _fp_data_hazard_ex_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_10 = _fp_data_hazard_ex_T_9 \| _fp_data_hazard_ex_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_11 = _fp_data_hazard_ex_T_10 \| _fp_data_hazard_ex_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_ex = _fp_data_hazard_ex_T & _fp_data_hazard_ex_T_11; // @[RocketCore.scala:990:{38,53}, :1287:50] wire _id_ex_hazard_T = data_hazard_ex & ex_cannot_bypass; // @[RocketCore.scala:988:139, :989:36, :991:54] wire _id_ex_hazard_T_1 = _id_ex_hazard_T \| fp_data_hazard_ex; // @[RocketCore.scala:990:53, :991:{54,74}] wire id_ex_hazard = ex_reg_valid & _id_ex_hazard_T_1; // @[RocketCore.scala:248:35, :991:{35,74}] wire _mem_cannot_bypass_T = \|mem_ctrl_csr; // @[RocketCore.scala:244:21, :997:40] wire _mem_cannot_bypass_T_1 = mem_ctrl_mem & mem_mem_cmd_bh; // @[RocketCore.scala:244:21, :995:41, :997:66] wire _mem_cannot_bypass_T_2 = _mem_cannot_bypass_T \| _mem_cannot_bypass_T_1; // @[RocketCore.scala:997:{40,50,66}] wire _mem_cannot_bypass_T_3 = _mem_cannot_bypass_T_2 \| mem_ctrl_mul; // @[RocketCore.scala:244:21, :997:{50,84}] wire _mem_cannot_bypass_T_4 = _mem_cannot_bypass_T_3 \| mem_ctrl_div; // @[RocketCore.scala:244:21, :997:{84,100}] wire _mem_cannot_bypass_T_5 = _mem_cannot_bypass_T_4 \| mem_ctrl_fp; // @[RocketCore.scala:244:21, :997:{100,116}] wire _mem_cannot_bypass_T_6 = _mem_cannot_bypass_T_5 \| mem_ctrl_rocc; // @[RocketCore.scala:244:21, :997:{116,131}] wire mem_cannot_bypass = _mem_cannot_bypass_T_6 \| mem_ctrl_vec; // @[RocketCore.scala:244:21, :997:{131,148}] wire _data_hazard_mem_T_1 = hazard_targets_0_1 & _data_hazard_mem_T; // @[RocketCore.scala:969:42, :998:72, :1287:27] wire _data_hazard_mem_T_3 = hazard_targets_1_1 & _data_hazard_mem_T_2; // @[RocketCore.scala:970:42, :998:72, :1287:27] wire _GEN_66 = id_waddr == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :998:72] wire _data_hazard_mem_T_4; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_4 = _GEN_66; // @[RocketCore.scala:998:72] wire _fp_data_hazard_mem_T_7; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_7 = _GEN_66; // @[RocketCore.scala:998:72, :999:92] wire _data_hazard_mem_T_5 = hazard_targets_2_1 & _data_hazard_mem_T_4; // @[RocketCore.scala:971:42, :998:72, :1287:27] wire _data_hazard_mem_T_6 = _data_hazard_mem_T_1 \| _data_hazard_mem_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_mem_T_7 = _data_hazard_mem_T_6 \| _data_hazard_mem_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_mem = mem_ctrl_wxd & _data_hazard_mem_T_7; // @[RocketCore.scala:244:21, :998:38, :1287:50] wire _fp_data_hazard_mem_T = id_ctrl_fp & mem_ctrl_wfd; // @[RocketCore.scala:244:21, :321:21, :999:39] wire _fp_data_hazard_mem_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_mem_T_1; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_mem_T_3; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_5 = id_raddr3 == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :999:92] wire _fp_data_hazard_mem_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_mem_T_5; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_mem_T_7; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_9 = _fp_data_hazard_mem_T_2 \| _fp_data_hazard_mem_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_10 = _fp_data_hazard_mem_T_9 \| _fp_data_hazard_mem_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_11 = _fp_data_hazard_mem_T_10 \| _fp_data_hazard_mem_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_mem = _fp_data_hazard_mem_T & _fp_data_hazard_mem_T_11; // @[RocketCore.scala:999:{39,55}, :1287:50] wire _id_mem_hazard_T = data_hazard_mem & mem_cannot_bypass; // @[RocketCore.scala:997:148, :998:38, :1000:57] wire _id_mem_hazard_T_1 = _id_mem_hazard_T \| fp_data_hazard_mem; // @[RocketCore.scala:999:55, :1000:{57,78}] wire id_mem_hazard = mem_reg_valid & _id_mem_hazard_T_1; // @[RocketCore.scala:265:36, :1000:{37,78}] wire _id_load_use_T = mem_reg_valid & data_hazard_mem; // @[RocketCore.scala:265:36, :998:38, :1001:32] assign _id_load_use_T_1 = _id_load_use_T & mem_ctrl_mem; // @[RocketCore.scala:244:21, :1001:{32,51}] assign id_load_use = _id_load_use_T_1; // @[RocketCore.scala:332:25, :1001:51] wire _id_vconfig_hazard_T_1 = mem_reg_valid & mem_reg_set_vconfig; // @[RocketCore.scala:265:36, :275:36, :1004:20] wire _id_vconfig_hazard_T_2 = _id_vconfig_hazard_T_1; // @[RocketCore.scala:1003:42, :1004:20] wire _id_vconfig_hazard_T_3 = wb_reg_valid & wb_reg_set_vconfig; // @[RocketCore.scala:288:35, :293:35, :1005:19] wire _id_vconfig_hazard_T_4 = _id_vconfig_hazard_T_2 \| _id_vconfig_hazard_T_3; // @[RocketCore.scala:1003:42, :1004:44, :1005:19] wire _GEN_67 = id_raddr1 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T = _GEN_67; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_1; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_1 = _GEN_67; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_1 = hazard_targets_0_1 & _data_hazard_wb_T; // @[RocketCore.scala:969:42, :1008:70, :1287:27] wire _GEN_68 = id_raddr2 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_2; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_2 = _GEN_68; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_3; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_3 = _GEN_68; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_3 = hazard_targets_1_1 & _data_hazard_wb_T_2; // @[RocketCore.scala:970:42, :1008:70, :1287:27] wire _GEN_69 = id_waddr == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_4; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_4 = _GEN_69; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_7; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_7 = _GEN_69; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_5 = hazard_targets_2_1 & _data_hazard_wb_T_4; // @[RocketCore.scala:971:42, :1008:70, :1287:27] wire _data_hazard_wb_T_6 = _data_hazard_wb_T_1 \| _data_hazard_wb_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_wb_T_7 = _data_hazard_wb_T_6 \| _data_hazard_wb_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_wb = wb_ctrl_wxd & _data_hazard_wb_T_7; // @[RocketCore.scala:245:20, :1008:36, :1287:50] wire _fp_data_hazard_wb_T = id_ctrl_fp & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :321:21, :1009:38] wire _fp_data_hazard_wb_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_wb_T_1; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_wb_T_3; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_5 = id_raddr3 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1009:90] wire _fp_data_hazard_wb_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_wb_T_5; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_wb_T_7; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_9 = _fp_data_hazard_wb_T_2 \| _fp_data_hazard_wb_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_10 = _fp_data_hazard_wb_T_9 \| _fp_data_hazard_wb_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_11 = _fp_data_hazard_wb_T_10 \| _fp_data_hazard_wb_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_wb = _fp_data_hazard_wb_T & _fp_data_hazard_wb_T_11; // @[RocketCore.scala:1009:{38,53}, :1287:50] wire _id_wb_hazard_T = data_hazard_wb & wb_set_sboard; // @[RocketCore.scala:756:69, :1008:36, :1010:54] wire _id_wb_hazard_T_1 = _id_wb_hazard_T \| fp_data_hazard_wb; // @[RocketCore.scala:1009:53, :1010:{54,71}] wire id_wb_hazard = wb_reg_valid & _id_wb_hazard_T_1; // @[RocketCore.scala:288:35, :1010:{35,71}] reg [31:0] _id_stall_fpu_r; // @[RocketCore.scala:1305:29] wire _id_stall_fpu_T = wb_dcache_miss \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :596:36, :1014:36] wire _id_stall_fpu_T_1 = _id_stall_fpu_T & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :1014:{36,52}] wire _id_stall_fpu_T_2 = _id_stall_fpu_T_1 \| io_fpu_sboard_set_0; // @[RocketCore.scala:153:7, :1014:{52,67}] wire _id_stall_fpu_T_3 = _id_stall_fpu_T_2 & wb_valid; // @[RocketCore.scala:815:45, :1014:{67,89}] wire _id_stall_fpu_T_7 = _id_stall_fpu_T_3; // @[RocketCore.scala:1014:89, :1312:17] wire [31:0] _id_stall_fpu_T_5 = _id_stall_fpu_T_3 ? _id_stall_fpu_T_4 : 32'h0; // @[RocketCore.scala:1014:89, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_6 = _id_stall_fpu_r \| _id_stall_fpu_T_5; // @[RocketCore.scala:1300:60, :1305:29, :1309:49] wire _id_stall_fpu_T_8 = dmem_resp_replay & dmem_resp_fpu; // @[RocketCore.scala:766:45, :769:42, :1016:39] wire _id_stall_fpu_T_9 = _id_stall_fpu_T_8; // @[RocketCore.scala:1016:{39,57}] wire [31:0] _id_stall_fpu_T_10 = 32'h1 << io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_11 = _id_stall_fpu_T_9 ? _id_stall_fpu_T_10 : 32'h0; // @[RocketCore.scala:1016:57, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_12 = ~_id_stall_fpu_T_11; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_13 = _id_stall_fpu_T_6 & _id_stall_fpu_T_12; // @[RocketCore.scala:1300:60, :1301:{62,64}] wire _id_stall_fpu_T_14 = _id_stall_fpu_T_7 \| _id_stall_fpu_T_9; // @[RocketCore.scala:1016:57, :1312:17] wire [31:0] _id_stall_fpu_T_15 = 32'h1 << io_fpu_sboard_clra_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_16 = io_fpu_sboard_clr_0 ? _id_stall_fpu_T_15 : 32'h0; // @[RocketCore.scala:153:7, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_17 = ~_id_stall_fpu_T_16; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_18 = _id_stall_fpu_T_13 & _id_stall_fpu_T_17; // @[RocketCore.scala:1301:{62,64}] wire _id_stall_fpu_T_19 = _id_stall_fpu_T_14 \| io_fpu_sboard_clr_0; // @[RocketCore.scala:153:7, :1312:17] wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_62; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_21 = _id_stall_fpu_T_20[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_22 = io_fpu_dec_ren1_0 & _id_stall_fpu_T_21; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_63; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_24 = _id_stall_fpu_T_23[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_25 = io_fpu_dec_ren2_0 & _id_stall_fpu_T_24; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> id_raddr3; // @[RocketCore.scala:326:72, :1302:35, :1305:29] wire _id_stall_fpu_T_27 = _id_stall_fpu_T_26[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_28 = io_fpu_dec_ren3_0 & _id_stall_fpu_T_27; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_64; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_30 = _id_stall_fpu_T_29[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_31 = io_fpu_dec_wen_0 & _id_stall_fpu_T_30; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire _id_stall_fpu_T_32 = _id_stall_fpu_T_22 \| _id_stall_fpu_T_25; // @[RocketCore.scala:1287:{27,50}] wire _id_stall_fpu_T_33 = _id_stall_fpu_T_32 \| _id_stall_fpu_T_28; // @[RocketCore.scala:1287:{27,50}] wire id_stall_fpu = _id_stall_fpu_T_33 \| _id_stall_fpu_T_31; // @[RocketCore.scala:1287:{27,50}] reg dcache_blocked_blocked; // @[RocketCore.scala:1024:22] wire _dcache_blocked_blocked_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45, :1025:16] wire _dcache_blocked_blocked_T_1 = _dcache_blocked_blocked_T; // @[RocketCore.scala:1025:{16,35}] wire _dcache_blocked_blocked_T_2 = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63] wire _dcache_blocked_blocked_T_3 = _dcache_blocked_blocked_T_1 & _dcache_blocked_blocked_T_2; // @[RocketCore.scala:1025:{35,60,63}] wire _dcache_blocked_blocked_T_4 = dcache_blocked_blocked \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :1024:22, :1025:95] wire _dcache_blocked_blocked_T_5 = _dcache_blocked_blocked_T_4 \| io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1025:{95,116}] wire _dcache_blocked_blocked_T_6 = _dcache_blocked_blocked_T_3 & _dcache_blocked_blocked_T_5; // @[RocketCore.scala:1025:{60,83,116}] wire _dcache_blocked_T = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63, :1026:16] wire dcache_blocked = dcache_blocked_blocked & _dcache_blocked_T; // @[RocketCore.scala:1024:22, :1026:{13,16}] reg rocc_blocked; // @[RocketCore.scala:1028:25] wire _rocc_blocked_T = ~wb_xcpt; // @[RocketCore.scala:815:48, :1029:19, :1278:14] wire _rocc_blocked_T_2 = _rocc_blocked_T; // @[RocketCore.scala:1029:{19,28}] wire _rocc_blocked_T_3 = io_rocc_cmd_valid \| rocc_blocked; // @[RocketCore.scala:153:7, :1028:25, :1029:72] wire _rocc_blocked_T_4 = _rocc_blocked_T_2 & _rocc_blocked_T_3; // @[RocketCore.scala:1029:{28,50,72}] wire _ctrl_stalld_T = id_ex_hazard \| id_mem_hazard; // @[RocketCore.scala:991:35, :1000:37, :1032:18] wire _ctrl_stalld_T_1 = _ctrl_stalld_T \| id_wb_hazard; // @[RocketCore.scala:1010:35, :1032:{18,35}] wire _ctrl_stalld_T_2 = _ctrl_stalld_T_1 \| id_sboard_hazard; // @[RocketCore.scala:1032:{35,51}, :1287:50] wire _ctrl_stalld_T_3 = _ctrl_stalld_T_2; // @[RocketCore.scala:1032:{51,71}] wire _ctrl_stalld_T_4 = ex_reg_valid \| mem_reg_valid; // @[RocketCore.scala:248:35, :265:36, :1034:40] wire _ctrl_stalld_T_5 = _ctrl_stalld_T_4 \| wb_reg_valid; // @[RocketCore.scala:288:35, :1034:{40,57}] wire _ctrl_stalld_T_6 = _csr_io_singleStep & _ctrl_stalld_T_5; // @[RocketCore.scala:341:19, :1034:{23,57}] wire _ctrl_stalld_T_7 = _ctrl_stalld_T_3 \| _ctrl_stalld_T_6; // @[RocketCore.scala:1032:71, :1033:23, :1034:23] wire _ctrl_stalld_T_8 = id_csr_en & _csr_io_decode_0_fp_csr; // @[package.scala:81:59] wire _ctrl_stalld_T_9 = ~io_fpu_fcsr_rdy_0; // @[RocketCore.scala:153:7, :1035:45] wire _ctrl_stalld_T_10 = _ctrl_stalld_T_8 & _ctrl_stalld_T_9; // @[RocketCore.scala:1035:{15,42,45}] wire _ctrl_stalld_T_11 = _ctrl_stalld_T_7 \| _ctrl_stalld_T_10; // @[RocketCore.scala:1033:23, :1034:74, :1035:42] wire _ctrl_stalld_T_14 = _ctrl_stalld_T_11; // @[RocketCore.scala:1034:74, :1035:62] wire _ctrl_stalld_T_15 = id_ctrl_fp & id_stall_fpu; // @[RocketCore.scala:321:21, :1037:16, :1287:50] wire _ctrl_stalld_T_16 = _ctrl_stalld_T_14 \| _ctrl_stalld_T_15; // @[RocketCore.scala:1035:62, :1036:61, :1037:16] wire _ctrl_stalld_T_17 = id_ctrl_mem & dcache_blocked; // @[RocketCore.scala:321:21, :1026:13, :1038:17] wire _ctrl_stalld_T_18 = _ctrl_stalld_T_16 \| _ctrl_stalld_T_17; // @[RocketCore.scala:1036:61, :1037:32, :1038:17] wire _ctrl_stalld_T_19 = id_ctrl_rocc & rocc_blocked; // @[RocketCore.scala:321:21, :1028:25, :1039:18] wire _ctrl_stalld_T_20 = _ctrl_stalld_T_18 \| _ctrl_stalld_T_19; // @[RocketCore.scala:1037:32, :1038:35, :1039:18] wire _ctrl_stalld_T_21 = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26, :1040:65] wire _ctrl_stalld_T_22 = _div_io_resp_valid & _ctrl_stalld_T_21; // @[RocketCore.scala:511:19, :1040:{62,65}] wire _ctrl_stalld_T_23 = _div_io_req_ready \| _ctrl_stalld_T_22; // @[RocketCore.scala:511:19, :1040:{40,62}] wire _ctrl_stalld_T_24 = ~_ctrl_stalld_T_23; // @[RocketCore.scala:1040:{21,40}] wire _ctrl_stalld_T_25 = _ctrl_stalld_T_24 \| _div_io_req_valid_T; // @[RocketCore.scala:512:36, :1040:{21,75}] wire _ctrl_stalld_T_26 = id_ctrl_div & _ctrl_stalld_T_25; // @[RocketCore.scala:321:21, :1040:{17,75}] wire _ctrl_stalld_T_27 = _ctrl_stalld_T_20 \| _ctrl_stalld_T_26; // @[RocketCore.scala:1038:35, :1039:34, :1040:17] wire _ctrl_stalld_T_29 = _ctrl_stalld_T_27; // @[RocketCore.scala:1039:34, :1040:96] wire _ctrl_stalld_T_30 = _ctrl_stalld_T_29 \| id_do_fence; // @[RocketCore.scala:410:32, :1040:96, :1041:15] wire _ctrl_stalld_T_31 = _ctrl_stalld_T_30 \| _csr_io_csr_stall; // @[RocketCore.scala:341:19, :1041:15, :1042:17] wire _ctrl_stalld_T_32 = _ctrl_stalld_T_31 \| id_reg_pause; // @[RocketCore.scala:161:25, :1042:17, :1043:22] wire ctrl_stalld = _ctrl_stalld_T_32; // @[RocketCore.scala:1043:22, :1044:18] wire _ctrl_killd_T = ~_ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :1046:17] wire _ctrl_killd_T_1 = _ctrl_killd_T \| _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :1046:{17,40}] wire _ctrl_killd_T_2 = _ctrl_killd_T_1 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1046:{40,71}] wire _ctrl_killd_T_3 = _ctrl_killd_T_2 \| ctrl_stalld; // @[RocketCore.scala:1044:18, :1046:{71,89}] assign _ctrl_killd_T_4 = _ctrl_killd_T_3 \| _csr_io_interrupt; // @[RocketCore.scala:341:19, :1046:{89,104}] assign ctrl_killd = _ctrl_killd_T_4; // @[RocketCore.scala:338:24, :1046:104] assign _io_imem_req_bits_speculative_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1049:35] assign io_imem_req_bits_speculative_0 = _io_imem_req_bits_speculative_T; // @[RocketCore.scala:153:7, :1049:35] wire _io_imem_req_bits_pc_T = wb_xcpt \| _csr_io_eret; // @[RocketCore.scala:341:19, :1051:17, :1278:14] wire [39:0] _io_imem_req_bits_pc_T_1 = replay_wb ? wb_reg_pc : mem_npc; // @[RocketCore.scala:295:22, :619:139, :761:71, :1052:8] assign _io_imem_req_bits_pc_T_2 = _io_imem_req_bits_pc_T ? _csr_io_evec : _io_imem_req_bits_pc_T_1; // @[RocketCore.scala:341:19, :1051:{8,17}, :1052:8] assign io_imem_req_bits_pc_0 = _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:153:7, :1051:8] wire _io_imem_flush_icache_T = wb_reg_valid & wb_ctrl_fence_i; // @[RocketCore.scala:245:20, :288:35, :1054:40] wire _io_imem_flush_icache_T_1 = ~io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1054:62] assign _io_imem_flush_icache_T_2 = _io_imem_flush_icache_T & _io_imem_flush_icache_T_1; // @[RocketCore.scala:1054:{40,59,62}] assign io_imem_flush_icache_0 = _io_imem_flush_icache_T_2; // @[RocketCore.scala:153:7, :1054:59] wire _io_imem_might_request_imem_might_request_reg_T = ex_pc_valid \| mem_pc_valid; // @[RocketCore.scala:595:51, :614:54, :1056:43] wire _io_imem_might_request_imem_might_request_reg_T_1 = io_ptw_customCSRs_csrs_0_value_0[1]; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_2 = _io_imem_might_request_imem_might_request_reg_T \| _io_imem_might_request_imem_might_request_reg_T_1; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_3 = _io_imem_might_request_imem_might_request_reg_T_2; // @[RocketCore.scala:1056:{59,103}] wire _io_imem_progress_T = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47] wire _io_imem_progress_T_1 = wb_reg_valid & _io_imem_progress_T; // @[RocketCore.scala:288:35, :1059:{44,47}] reg io_imem_progress_REG; // @[RocketCore.scala:1059:30] assign io_imem_progress_0 = io_imem_progress_REG; // @[RocketCore.scala:153:7, :1059:30] assign _io_imem_sfence_valid_T = wb_reg_valid & wb_reg_sfence; // @[RocketCore.scala:288:35, :294:26, :1060:40] assign io_imem_sfence_valid_0 = _io_imem_sfence_valid_T; // @[RocketCore.scala:153:7, :1060:40] assign _io_imem_sfence_bits_rs1_T = wb_reg_mem_size[0]; // @[RocketCore.scala:296:28, :1061:45] assign io_imem_sfence_bits_rs1_0 = _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:153:7, :1061:45] assign _io_imem_sfence_bits_rs2_T = wb_reg_mem_size[1]; // @[RocketCore.scala:296:28, :1062:45] assign io_imem_sfence_bits_rs2_0 = _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:153:7, :1062:45] assign io_imem_sfence_bits_asid_0 = wb_reg_rs2[0]; // @[RocketCore.scala:153:7, :303:23, :1064:28] wire _ibuf_io_inst_0_ready_T = ~ctrl_stalld; // @[RocketCore.scala:1044:18, :1069:28] wire _io_imem_btb_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1071:48] wire _io_imem_btb_update_valid_T_1 = mem_reg_valid & _io_imem_btb_update_valid_T; // @[RocketCore.scala:265:36, :1071:{45,48}] wire _io_imem_btb_update_valid_T_2 = _io_imem_btb_update_valid_T_1 & mem_wrong_npc; // @[RocketCore.scala:621:8, :1071:{45,60}] wire _io_imem_btb_update_valid_T_3 = ~mem_cfi; // @[RocketCore.scala:625:50, :1071:81] wire _io_imem_btb_update_valid_T_4 = _io_imem_btb_update_valid_T_3 \| mem_cfi_taken; // @[RocketCore.scala:626:74, :1071:{81,90}] assign _io_imem_btb_update_valid_T_5 = _io_imem_btb_update_valid_T_2 & _io_imem_btb_update_valid_T_4; // @[RocketCore.scala:1071:{60,77,90}] assign io_imem_btb_update_valid_0 = _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:153:7, :1071:77] wire _GEN_70 = mem_ctrl_jal \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :1074:23] wire _io_imem_btb_update_bits_cfiType_T; // @[RocketCore.scala:1074:23] assign _io_imem_btb_update_bits_cfiType_T = _GEN_70; // @[RocketCore.scala:1074:23] wire _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:22] assign _io_imem_btb_update_bits_cfiType_T_8 = _GEN_70; // @[RocketCore.scala:1074:23, :1076:22] wire _io_imem_btb_update_bits_cfiType_T_1 = mem_waddr[0]; // @[RocketCore.scala:454:38, :1074:53] wire _io_imem_btb_update_bits_cfiType_T_2 = _io_imem_btb_update_bits_cfiType_T & _io_imem_btb_update_bits_cfiType_T_1; // @[RocketCore.scala:1074:{23,41,53}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_3 = mem_reg_inst[19:15]; // @[RocketCore.scala:278:25, :1075:39] wire [4:0] _io_imem_btb_update_bits_cfiType_T_4 = _io_imem_btb_update_bits_cfiType_T_3; // @[RocketCore.scala:1075:{39,47}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_5 = _io_imem_btb_update_bits_cfiType_T_4 & 5'h1B; // @[RocketCore.scala:1075:{47,64}] wire _io_imem_btb_update_bits_cfiType_T_6 = _io_imem_btb_update_bits_cfiType_T_5 == 5'h1; // @[RocketCore.scala:1075:64] wire _io_imem_btb_update_bits_cfiType_T_7 = mem_ctrl_jalr & _io_imem_btb_update_bits_cfiType_T_6; // @[RocketCore.scala:244:21, :1075:{23,64}] wire _io_imem_btb_update_bits_cfiType_T_9 = _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:{8,22}] wire [1:0] _io_imem_btb_update_bits_cfiType_T_10 = _io_imem_btb_update_bits_cfiType_T_7 ? 2'h3 : {1'h0, _io_imem_btb_update_bits_cfiType_T_9}; // @[RocketCore.scala:1075:{8,23}, :1076:8] assign _io_imem_btb_update_bits_cfiType_T_11 = _io_imem_btb_update_bits_cfiType_T_2 ? 2'h2 : _io_imem_btb_update_bits_cfiType_T_10; // @[RocketCore.scala:1074:{8,41}, :1075:8] assign io_imem_btb_update_bits_cfiType_0 = _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:153:7, :1074:8] assign io_imem_btb_update_bits_target_0 = io_imem_req_bits_pc_0[38:0]; // @[RocketCore.scala:153:7, :1078:34] wire [1:0] _io_imem_btb_update_bits_br_pc_T = {~mem_reg_rvc, 1'h0}; // @[RocketCore.scala:266:36, :1079:74] wire [40:0] _io_imem_btb_update_bits_br_pc_T_1 = {1'h0, mem_reg_pc} + {39'h0, _io_imem_btb_update_bits_br_pc_T}; // @[RocketCore.scala:277:23, :1079:{69,74}] wire [39:0] _io_imem_btb_update_bits_br_pc_T_2 = _io_imem_btb_update_bits_br_pc_T_1[39:0]; // @[RocketCore.scala:1079:69] assign io_imem_btb_update_bits_br_pc_0 = _io_imem_btb_update_bits_br_pc_T_2[38:0]; // @[RocketCore.scala:153:7, :1079:{33,69}] wire [38:0] _io_imem_btb_update_bits_pc_T = ~io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7, :1080:35] wire [38:0] _io_imem_btb_update_bits_pc_T_1 = {_io_imem_btb_update_bits_pc_T[38:2], 2'h3}; // @[RocketCore.scala:1080:{35,66}] assign _io_imem_btb_update_bits_pc_T_2 = ~_io_imem_btb_update_bits_pc_T_1; // @[RocketCore.scala:1080:{33,66}] assign io_imem_btb_update_bits_pc_0 = _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:153:7, :1080:33] wire _io_imem_bht_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1084:48] assign _io_imem_bht_update_valid_T_1 = mem_reg_valid & _io_imem_bht_update_valid_T; // @[RocketCore.scala:265:36, :1084:{45,48}] assign io_imem_bht_update_valid_0 = _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:153:7, :1084:45] wire _io_fpu_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :1094:19] assign _io_fpu_valid_T_1 = _io_fpu_valid_T & id_ctrl_fp; // @[RocketCore.scala:321:21, :1094:{19,31}] assign io_fpu_valid_0 = _io_fpu_valid_T_1; // @[RocketCore.scala:153:7, :1094:31] assign _io_fpu_ll_resp_val_T = dmem_resp_valid & dmem_resp_fpu; // @[RocketCore.scala:766:45, :768:44, :1099:41] assign io_fpu_ll_resp_val_0 = _io_fpu_ll_resp_val_T; // @[RocketCore.scala:153:7, :1099:41] assign io_fpu_ll_resp_type_0 = {1'h0, io_dmem_resp_bits_size_0}; // @[RocketCore.scala:153:7, :1101:23] assign _io_fpu_keep_clock_enabled_T = io_ptw_customCSRs_csrs_0_value_0[2]; // @[CustomCSRs.scala:45:59] assign io_fpu_keep_clock_enabled_0 = _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] assign _io_dmem_req_valid_T = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala:243:20, :248:35, :1130:41] assign io_dmem_req_valid_0 = _io_dmem_req_valid_T; // @[RocketCore.scala:153:7, :1130:41] wire [5:0] ex_dcache_tag = {ex_waddr, ex_ctrl_fp}; // @[RocketCore.scala:243:20, :453:36, :1131:26] assign io_dmem_req_bits_tag_0 = {1'h0, ex_dcache_tag}; // @[RocketCore.scala:153:7, :1131:26, :1133:25] wire _io_dmem_req_bits_signed_T_1 = ex_reg_inst[14]; // @[RocketCore.scala:259:24, :1136:75] wire _io_dmem_req_bits_signed_T_2 = _io_dmem_req_bits_signed_T_1; // @[RocketCore.scala:1136:{34,75}] assign _io_dmem_req_bits_signed_T_3 = ~_io_dmem_req_bits_signed_T_2; // @[RocketCore.scala:1136:{30,34}] assign io_dmem_req_bits_signed_0 = _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:153:7, :1136:30] wire [24:0] _io_dmem_req_bits_addr_a_T = ex_rs_0[63:39]; // @[RocketCore.scala:469:14, :1293:17] wire [24:0] io_dmem_req_bits_addr_a = _io_dmem_req_bits_addr_a_T; // @[RocketCore.scala:1293:{17,23}] wire _io_dmem_req_bits_addr_msb_T = io_dmem_req_bits_addr_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _io_dmem_req_bits_addr_msb_T_1 = &io_dmem_req_bits_addr_a; // @[RocketCore.scala:1293:23, :1294:34] wire _io_dmem_req_bits_addr_msb_T_2 = _io_dmem_req_bits_addr_msb_T \| _io_dmem_req_bits_addr_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _io_dmem_req_bits_addr_msb_T_3 = _alu_io_adder_out[39]; // @[RocketCore.scala:504:19, :1294:46] wire _io_dmem_req_bits_addr_msb_T_4 = _alu_io_adder_out[38]; // @[RocketCore.scala:504:19, :1294:54] wire _io_dmem_req_bits_addr_msb_T_5 = ~_io_dmem_req_bits_addr_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire io_dmem_req_bits_addr_msb = _io_dmem_req_bits_addr_msb_T_2 ? _io_dmem_req_bits_addr_msb_T_3 : _io_dmem_req_bits_addr_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [38:0] _io_dmem_req_bits_addr_T = _alu_io_adder_out[38:0]; // @[RocketCore.scala:504:19, :1295:16] assign _io_dmem_req_bits_addr_T_1 = {io_dmem_req_bits_addr_msb, _io_dmem_req_bits_addr_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] assign io_dmem_req_bits_addr_0 = _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:153:7, :1295:8] assign io_dmem_req_bits_dprv_0 = _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:153:7, :1140:31] assign io_dmem_req_bits_dv_0 = _io_dmem_req_bits_dv_T; // @[RocketCore.scala:153:7, :1141:37] wire _io_dmem_req_bits_no_resp_T_4 = _io_dmem_req_bits_no_resp_T \| _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_5 = _io_dmem_req_bits_no_resp_T_4 \| _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_6 = _io_dmem_req_bits_no_resp_T_5 \| _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_11 = _io_dmem_req_bits_no_resp_T_7 \| _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_12 = _io_dmem_req_bits_no_resp_T_11 \| _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_13 = _io_dmem_req_bits_no_resp_T_12 \| _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_19 = _io_dmem_req_bits_no_resp_T_14 \| _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_20 = _io_dmem_req_bits_no_resp_T_19 \| _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_21 = _io_dmem_req_bits_no_resp_T_20 \| _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_22 = _io_dmem_req_bits_no_resp_T_21 \| _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_23 = _io_dmem_req_bits_no_resp_T_13 \| _io_dmem_req_bits_no_resp_T_22; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_24 = _io_dmem_req_bits_no_resp_T_6 \| _io_dmem_req_bits_no_resp_T_23; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_25 = ~_io_dmem_req_bits_no_resp_T_24; // @[RocketCore.scala:1142:31] wire _io_dmem_req_bits_no_resp_T_26 = ~ex_ctrl_fp; // @[RocketCore.scala:243:20, :1142:60] wire _io_dmem_req_bits_no_resp_T_27 = ex_waddr == 5'h0; // @[RocketCore.scala:453:36, :1142:84] wire _io_dmem_req_bits_no_resp_T_28 = _io_dmem_req_bits_no_resp_T_26 & _io_dmem_req_bits_no_resp_T_27; // @[RocketCore.scala:1142:{60,72,84}] assign _io_dmem_req_bits_no_resp_T_29 = _io_dmem_req_bits_no_resp_T_25 \| _io_dmem_req_bits_no_resp_T_28; // @[RocketCore.scala:1142:{31,56,72}] assign io_dmem_req_bits_no_resp_0 = _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:153:7, :1142:56] assign _io_dmem_s1_data_data_T = mem_ctrl_fp ? io_fpu_store_data_0 : mem_reg_rs2; // @[RocketCore.scala:153:7, :244:21, :283:24, :1148:63] assign io_dmem_s1_data_data_0 = _io_dmem_s1_data_data_T; // @[RocketCore.scala:153:7, :1148:63] wire _io_dmem_s1_kill_T = killm_common \| mem_ldst_xcpt; // @[RocketCore.scala:700:68, :1151:35, :1278:14] wire _io_dmem_s1_kill_T_1 = _io_dmem_s1_kill_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :1151:{35,52}] assign _io_dmem_s1_kill_T_2 = _io_dmem_s1_kill_T_1; // @[RocketCore.scala:1151:{52,68}] assign io_dmem_s1_kill_0 = _io_dmem_s1_kill_T_2; // @[RocketCore.scala:153:7, :1151:68] wire _io_dmem_keep_clock_enabled_T = _ibuf_io_inst_0_valid & id_ctrl_mem; // @[RocketCore.scala:311:20, :321:21, :1154:55] wire _io_dmem_keep_clock_enabled_T_1 = ~_csr_io_csr_stall; // @[RocketCore.scala:341:19, :1154:73] assign _io_dmem_keep_clock_enabled_T_2 = _io_dmem_keep_clock_enabled_T & _io_dmem_keep_clock_enabled_T_1; // @[RocketCore.scala:1154:{55,70,73}] assign io_dmem_keep_clock_enabled_0 = _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:153:7, :1154:70] wire _io_rocc_cmd_valid_T_1 = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47, :1156:56] assign _io_rocc_cmd_valid_T_2 = _io_rocc_cmd_valid_T & _io_rocc_cmd_valid_T_1; // @[RocketCore.scala:1156:{37,53,56}] assign io_rocc_cmd_valid = _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:153:7, :1156:53] wire [6:0] _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_funct = _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs2 = _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs1 = _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xd = _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs1 = _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs2 = _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rd = _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:153:7, :1159:48] wire [6:0] _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_opcode = _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:153:7, :1159:48] assign _io_rocc_cmd_bits_inst_T = _io_rocc_cmd_bits_inst_WIRE_1[6:0]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_opcode = _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_1 = _io_rocc_cmd_bits_inst_WIRE_1[11:7]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rd = _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_2 = _io_rocc_cmd_bits_inst_WIRE_1[12]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs2 = _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_3 = _io_rocc_cmd_bits_inst_WIRE_1[13]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs1 = _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_4 = _io_rocc_cmd_bits_inst_WIRE_1[14]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xd = _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_5 = _io_rocc_cmd_bits_inst_WIRE_1[19:15]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs1 = _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_6 = _io_rocc_cmd_bits_inst_WIRE_1[24:20]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs2 = _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_7 = _io_rocc_cmd_bits_inst_WIRE_1[31:25]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_funct = _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] wire [4:0] _unpause_T = _csr_io_time[4:0]; // @[RocketCore.scala:341:19, :1164:28] wire _unpause_T_1 = _unpause_T == 5'h0; // @[RocketCore.scala:1164:{28,62}] wire _unpause_T_2 = _unpause_T_1 \| _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19, :1164:{62,70}] wire _unpause_T_3 = _unpause_T_2 \| io_dmem_perf_release_0; // @[RocketCore.scala:153:7, :1164:{70,94}] wire unpause = _unpause_T_3 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1164:{94,118}] reg icache_blocked_REG; // @[RocketCore.scala:1183:55] wire _icache_blocked_T = io_imem_resp_valid_0 \| icache_blocked_REG; // @[RocketCore.scala:153:7, :1183:{45,55}] wire icache_blocked = ~_icache_blocked_T; // @[RocketCore.scala:1183:{24,45}] wire _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1192:52] wire [63:0] _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1194:37] wire [4:0] _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1198:42] wire [4:0] _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1200:42] wire coreMonitorBundle_excpt; // @[RocketCore.scala:1186:31] wire [2:0] coreMonitorBundle_priv_mode; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_hartid; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_timer; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_valid; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_pc; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_wrenx; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd0src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd0val; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd1src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd1val; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_inst; // @[RocketCore.scala:1186:31] wire [63:0] _GEN_71 = {61'h0, io_hartid_0}; // @[RocketCore.scala:153:7, :1190:28] assign coreMonitorBundle_hartid = _GEN_71; // @[RocketCore.scala:1186:31, :1190:28] wire [63:0] xrfWriteBundle_hartid; // @[RocketCore.scala:1249:28] assign xrfWriteBundle_hartid = _GEN_71; // @[RocketCore.scala:1190:28, :1249:28] assign coreMonitorBundle_timer = _coreMonitorBundle_timer_T; // @[RocketCore.scala:1186:31, :1191:41] wire _coreMonitorBundle_valid_T = ~_csr_io_trace_0_exception; // @[RocketCore.scala:341:19, :1192:55] assign _coreMonitorBundle_valid_T_1 = _csr_io_trace_0_valid & _coreMonitorBundle_valid_T; // @[RocketCore.scala:341:19, :1192:{52,55}] assign coreMonitorBundle_valid = _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1186:31, :1192:52] wire [39:0] _coreMonitorBundle_pc_T; // @[RocketCore.scala:1193:48] wire _coreMonitorBundle_pc_T_1 = _coreMonitorBundle_pc_T[39]; // @[package.scala:132:38] wire [23:0] _coreMonitorBundle_pc_T_2 = {24{_coreMonitorBundle_pc_T_1}}; // @[package.scala:132:{20,38}] assign _coreMonitorBundle_pc_T_3 = {_coreMonitorBundle_pc_T_2, _coreMonitorBundle_pc_T}; // @[package.scala:132:{15,20}] assign coreMonitorBundle_pc = _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T = ~wb_set_sboard; // @[RocketCore.scala:756:69, :1194:40] assign _coreMonitorBundle_wrenx_T_1 = wb_wen & _coreMonitorBundle_wrenx_T; // @[RocketCore.scala:816:25, :1194:{37,40}] assign coreMonitorBundle_wrenx = _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1186:31, :1194:37] assign _coreMonitorBundle_rd0src_T = wb_reg_inst[19:15]; // @[RocketCore.scala:300:24, :1198:42] assign coreMonitorBundle_rd0src = _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1186:31, :1198:42] reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala:1199:46] reg [63:0] coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1199:38] assign coreMonitorBundle_rd0val = coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1186:31, :1199:38] assign _coreMonitorBundle_rd1src_T = wb_reg_inst[24:20]; // @[RocketCore.scala:300:24, :1200:42] assign coreMonitorBundle_rd1src = _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1186:31, :1200:42] reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala:1201:46] reg [63:0] coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1201:38] assign coreMonitorBundle_rd1val = coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1186:31, :1201:38]
Generate the Verilog code corresponding to this FIRRTL code module ZstdLiteralEncoder : input clock : Clock input reset : Reset output io : { flip src_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}, flip src_info2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}, flip dst_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { op : UInt<64>, cmpflag : UInt<64>, cmpval : UInt<64>}}, bytes_written : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, l2if : { lit_reader : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, dic_reader : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, dic_writer : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, hdr_writer : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, jt_writer : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, lit_writer : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}}, busy : UInt<1>} regreset dispatched_src_cnt : UInt<64>, clock, reset, UInt<64>(0h0) node _T = and(io.src_info.ready, io.src_info.valid) when _T : node _nxt_dispatched_src_cnt_T = add(dispatched_src_cnt, UInt<1>(0h1)) node nxt_dispatched_src_cnt = tail(_nxt_dispatched_src_cnt_T, 1) connect dispatched_src_cnt, nxt_dispatched_src_cnt regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "ZSTD_LITERAL_ENCODER src dispatched: %d\n", nxt_dispatched_src_cnt) : printf_1 inst controller of HufCompressorController connect controller.clock, clock connect controller.reset, reset connect controller.io.src_info_in, io.src_info connect controller.io.dst_info_in, io.dst_info connect io.bytes_written.bits, controller.io.total_write_bytes.bits connect io.bytes_written.valid, controller.io.total_write_bytes.valid connect controller.io.total_write_bytes.ready, io.bytes_written.ready node _T_5 = and(io.bytes_written.ready, io.bytes_written.valid) when _T_5 : regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "ZSTD_LITERAL_ENCODER written bytes: %d\n", io.bytes_written.bits) : printf_3 node _T_10 = and(io.src_info.ready, io.src_info.valid) when _T_10 : regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "ZSTD_LITERAL_ENCODER src size: %d\n", io.src_info.bits.isize) : printf_5 inst hdr_writer of HufCompressorMemwriter connect hdr_writer.clock, clock connect hdr_writer.reset, reset connect hdr_writer.io.l2io.no_memops_inflight, io.l2if.hdr_writer.no_memops_inflight connect hdr_writer.io.l2io.resp, io.l2if.hdr_writer.resp connect io.l2if.hdr_writer.req.bits, hdr_writer.io.l2io.req.bits connect io.l2if.hdr_writer.req.valid, hdr_writer.io.l2io.req.valid connect hdr_writer.io.l2io.req.ready, io.l2if.hdr_writer.req.ready connect hdr_writer.io.decompress_dest_info, controller.io.hdr_dst_info connect hdr_writer.io.memwrites_in, controller.io.hdr_writes connect hdr_writer.io.custom_write_value, controller.io.total_write_bytes2 inst jt_writer of EntropyCompressorMemwriter connect jt_writer.clock, clock connect jt_writer.reset, reset connect jt_writer.io.l2io.no_memops_inflight, io.l2if.jt_writer.no_memops_inflight connect jt_writer.io.l2io.resp, io.l2if.jt_writer.resp connect io.l2if.jt_writer.req.bits, jt_writer.io.l2io.req.bits connect io.l2if.jt_writer.req.valid, jt_writer.io.l2io.req.valid connect jt_writer.io.l2io.req.ready, io.l2if.jt_writer.req.ready connect jt_writer.io.decompress_dest_info, controller.io.jt_dst_info connect jt_writer.io.memwrites_in, controller.io.jt_writes inst dic_memloader of MemLoader connect dic_memloader.clock, clock connect dic_memloader.reset, reset connect dic_memloader.io.l2helperUser.no_memops_inflight, io.l2if.dic_reader.no_memops_inflight connect dic_memloader.io.l2helperUser.resp, io.l2if.dic_reader.resp connect io.l2if.dic_reader.req.bits, dic_memloader.io.l2helperUser.req.bits connect io.l2if.dic_reader.req.valid, dic_memloader.io.l2helperUser.req.valid connect dic_memloader.io.l2helperUser.req.ready, io.l2if.dic_reader.req.ready connect dic_memloader.io.src_info, io.src_info2 inst dic_builder of HufCompressorDicBuilder connect dic_builder.clock, clock connect dic_builder.reset, reset connect dic_builder.io.cnt_stream, dic_memloader.io.consumer connect controller.io.weight_bytes, dic_builder.io.header_written_bytes connect controller.io.header_size_info, dic_builder.io.header_size_info connect dic_builder.io.init_dictionary, controller.io.init_dictionary inst dic_writer of EntropyCompressorMemwriter_1 connect dic_writer.clock, clock connect dic_writer.reset, reset connect dic_writer.io.l2io.no_memops_inflight, io.l2if.dic_writer.no_memops_inflight connect dic_writer.io.l2io.resp, io.l2if.dic_writer.resp connect io.l2if.dic_writer.req.bits, dic_writer.io.l2io.req.bits connect io.l2if.dic_writer.req.valid, dic_writer.io.l2io.req.valid connect dic_writer.io.l2io.req.ready, io.l2if.dic_writer.req.ready connect dic_writer.io.decompress_dest_info, controller.io.weight_dst_info connect dic_writer.io.memwrites_in, dic_builder.io.header_writes inst lit_memloader of ReverseMemLoader connect lit_memloader.clock, clock connect lit_memloader.reset, reset connect lit_memloader.io.l2helperUser.no_memops_inflight, io.l2if.lit_reader.no_memops_inflight connect lit_memloader.io.l2helperUser.resp, io.l2if.lit_reader.resp connect io.l2if.lit_reader.req.bits, lit_memloader.io.l2helperUser.req.bits connect io.l2if.lit_reader.req.valid, lit_memloader.io.l2helperUser.req.valid connect lit_memloader.io.l2helperUser.req.ready, io.l2if.lit_reader.req.ready connect lit_memloader.io.src_info, controller.io.lit_src_info inst encoder of HufCompressorEncoder connect encoder.clock, clock connect encoder.reset, reset connect encoder.io.lit_stream, lit_memloader.io.consumer connect encoder.io.dic_info[0], dic_builder.io.dic_info[0] connect encoder.io.dic_info[1], dic_builder.io.dic_info[1] connect dic_builder.io.symbol_info[0], encoder.io.symbol_info[0] connect dic_builder.io.symbol_info[1], encoder.io.symbol_info[1] connect controller.io.compressed_bytes, encoder.io.compressed_bytes inst lit_memwriter of EntropyCompressorMemwriter_2 connect lit_memwriter.clock, clock connect lit_memwriter.reset, reset connect lit_memwriter.io.l2io.no_memops_inflight, io.l2if.lit_writer.no_memops_inflight connect lit_memwriter.io.l2io.resp, io.l2if.lit_writer.resp connect io.l2if.lit_writer.req.bits, lit_memwriter.io.l2io.req.bits connect io.l2if.lit_writer.req.valid, lit_memwriter.io.l2io.req.valid connect lit_memwriter.io.l2io.req.ready, io.l2if.lit_writer.req.ready connect lit_memwriter.io.decompress_dest_info, controller.io.lit_dst_info connect lit_memwriter.io.memwrites_in, encoder.io.memwrites_out node _done_T = eq(dispatched_src_cnt, controller.io.bufs_completed) node done = and(_done_T, hdr_writer.io.no_writes_inflight) node _io_busy_T = eq(done, UInt<1>(0h0)) connect io.busy, _io_busy_T	module ZstdLiteralEncoder( // @[ZstdLiteralEncoder.scala:62:7] input clock, // @[ZstdLiteralEncoder.scala:62:7] input reset, // @[ZstdLiteralEncoder.scala:62:7] output io_src_info_ready, // @[ZstdLiteralEncoder.scala:64:14] input io_src_info_valid, // @[ZstdLiteralEncoder.scala:64:14] input [63:0] io_src_info_bits_ip, // @[ZstdLiteralEncoder.scala:64:14] input [63:0] io_src_info_bits_isize, // @[ZstdLiteralEncoder.scala:64:14] output io_src_info2_ready, // @[ZstdLiteralEncoder.scala:64:14] input io_src_info2_valid, // @[ZstdLiteralEncoder.scala:64:14] input [63:0] io_src_info2_bits_ip, // @[ZstdLiteralEncoder.scala:64:14] input [63:0] io_src_info2_bits_isize, // @[ZstdLiteralEncoder.scala:64:14] output io_dst_info_ready, // @[ZstdLiteralEncoder.scala:64:14] input io_dst_info_valid, // @[ZstdLiteralEncoder.scala:64:14] input [63:0] io_dst_info_bits_op, // @[ZstdLiteralEncoder.scala:64:14] input [63:0] io_dst_info_bits_cmpflag, // @[ZstdLiteralEncoder.scala:64:14] input [63:0] io_dst_info_bits_cmpval, // @[ZstdLiteralEncoder.scala:64:14] input io_bytes_written_ready, // @[ZstdLiteralEncoder.scala:64:14] output io_bytes_written_valid, // @[ZstdLiteralEncoder.scala:64:14] output [63:0] io_bytes_written_bits, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_lit_reader_req_ready, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_lit_reader_req_valid, // @[ZstdLiteralEncoder.scala:64:14] output [70:0] io_l2if_lit_reader_req_bits_addr, // @[ZstdLiteralEncoder.scala:64:14] output [2:0] io_l2if_lit_reader_req_bits_size, // @[ZstdLiteralEncoder.scala:64:14] output [255:0] io_l2if_lit_reader_req_bits_data, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_lit_reader_req_bits_cmd, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_lit_reader_resp_ready, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_lit_reader_resp_valid, // @[ZstdLiteralEncoder.scala:64:14] input [255:0] io_l2if_lit_reader_resp_bits_data, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_lit_reader_no_memops_inflight, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_dic_reader_req_ready, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_dic_reader_req_valid, // @[ZstdLiteralEncoder.scala:64:14] output [70:0] io_l2if_dic_reader_req_bits_addr, // @[ZstdLiteralEncoder.scala:64:14] output [2:0] io_l2if_dic_reader_req_bits_size, // @[ZstdLiteralEncoder.scala:64:14] output [255:0] io_l2if_dic_reader_req_bits_data, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_dic_reader_req_bits_cmd, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_dic_reader_resp_ready, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_dic_reader_resp_valid, // @[ZstdLiteralEncoder.scala:64:14] input [255:0] io_l2if_dic_reader_resp_bits_data, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_dic_reader_no_memops_inflight, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_dic_writer_req_ready, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_dic_writer_req_valid, // @[ZstdLiteralEncoder.scala:64:14] output [63:0] io_l2if_dic_writer_req_bits_addr, // @[ZstdLiteralEncoder.scala:64:14] output [2:0] io_l2if_dic_writer_req_bits_size, // @[ZstdLiteralEncoder.scala:64:14] output [255:0] io_l2if_dic_writer_req_bits_data, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_dic_writer_req_bits_cmd, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_dic_writer_resp_ready, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_dic_writer_resp_valid, // @[ZstdLiteralEncoder.scala:64:14] input [255:0] io_l2if_dic_writer_resp_bits_data, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_dic_writer_no_memops_inflight, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_hdr_writer_req_ready, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_hdr_writer_req_valid, // @[ZstdLiteralEncoder.scala:64:14] output [63:0] io_l2if_hdr_writer_req_bits_addr, // @[ZstdLiteralEncoder.scala:64:14] output [2:0] io_l2if_hdr_writer_req_bits_size, // @[ZstdLiteralEncoder.scala:64:14] output [255:0] io_l2if_hdr_writer_req_bits_data, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_hdr_writer_req_bits_cmd, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_hdr_writer_resp_ready, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_hdr_writer_resp_valid, // @[ZstdLiteralEncoder.scala:64:14] input [255:0] io_l2if_hdr_writer_resp_bits_data, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_hdr_writer_no_memops_inflight, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_jt_writer_req_ready, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_jt_writer_req_valid, // @[ZstdLiteralEncoder.scala:64:14] output [63:0] io_l2if_jt_writer_req_bits_addr, // @[ZstdLiteralEncoder.scala:64:14] output [2:0] io_l2if_jt_writer_req_bits_size, // @[ZstdLiteralEncoder.scala:64:14] output [255:0] io_l2if_jt_writer_req_bits_data, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_jt_writer_req_bits_cmd, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_jt_writer_resp_ready, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_jt_writer_resp_valid, // @[ZstdLiteralEncoder.scala:64:14] input [255:0] io_l2if_jt_writer_resp_bits_data, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_jt_writer_no_memops_inflight, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_lit_writer_req_ready, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_lit_writer_req_valid, // @[ZstdLiteralEncoder.scala:64:14] output [63:0] io_l2if_lit_writer_req_bits_addr, // @[ZstdLiteralEncoder.scala:64:14] output [2:0] io_l2if_lit_writer_req_bits_size, // @[ZstdLiteralEncoder.scala:64:14] output [255:0] io_l2if_lit_writer_req_bits_data, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_lit_writer_req_bits_cmd, // @[ZstdLiteralEncoder.scala:64:14] output io_l2if_lit_writer_resp_ready, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_lit_writer_resp_valid, // @[ZstdLiteralEncoder.scala:64:14] input [255:0] io_l2if_lit_writer_resp_bits_data, // @[ZstdLiteralEncoder.scala:64:14] input io_l2if_lit_writer_no_memops_inflight, // @[ZstdLiteralEncoder.scala:64:14] output io_busy // @[ZstdLiteralEncoder.scala:64:14] ); wire _lit_memwriter_io_memwrites_in_ready; // @[ZstdLiteralEncoder.scala:127:29] wire _lit_memwriter_io_decompress_dest_info_ready; // @[ZstdLiteralEncoder.scala:127:29] wire [5:0] _encoder_io_lit_stream_user_consumed_bytes; // @[ZstdLiteralEncoder.scala:121:23] wire _encoder_io_lit_stream_output_ready; // @[ZstdLiteralEncoder.scala:121:23] wire _encoder_io_symbol_info_0_valid; // @[ZstdLiteralEncoder.scala:121:23] wire [7:0] _encoder_io_symbol_info_0_bits_symbol; // @[ZstdLiteralEncoder.scala:121:23] wire _encoder_io_symbol_info_0_bits_last_symbol; // @[ZstdLiteralEncoder.scala:121:23] wire _encoder_io_symbol_info_1_valid; // @[ZstdLiteralEncoder.scala:121:23] wire [7:0] _encoder_io_symbol_info_1_bits_symbol; // @[ZstdLiteralEncoder.scala:121:23] wire _encoder_io_symbol_info_1_bits_last_symbol; // @[ZstdLiteralEncoder.scala:121:23] wire _encoder_io_dic_info_0_ready; // @[ZstdLiteralEncoder.scala:121:23] wire _encoder_io_dic_info_1_ready; // @[ZstdLiteralEncoder.scala:121:23] wire _encoder_io_memwrites_out_valid; // @[ZstdLiteralEncoder.scala:121:23] wire [255:0] _encoder_io_memwrites_out_bits_data; // @[ZstdLiteralEncoder.scala:121:23] wire [5:0] _encoder_io_memwrites_out_bits_validbytes; // @[ZstdLiteralEncoder.scala:121:23] wire _encoder_io_memwrites_out_bits_end_of_message; // @[ZstdLiteralEncoder.scala:121:23] wire _encoder_io_compressed_bytes_valid; // @[ZstdLiteralEncoder.scala:121:23] wire [63:0] _encoder_io_compressed_bytes_bits; // @[ZstdLiteralEncoder.scala:121:23] wire _lit_memloader_io_src_info_ready; // @[ZstdLiteralEncoder.scala:117:29] wire [5:0] _lit_memloader_io_consumer_available_output_bytes; // @[ZstdLiteralEncoder.scala:117:29] wire _lit_memloader_io_consumer_output_valid; // @[ZstdLiteralEncoder.scala:117:29] wire [255:0] _lit_memloader_io_consumer_output_data; // @[ZstdLiteralEncoder.scala:117:29] wire _lit_memloader_io_consumer_output_last_chunk; // @[ZstdLiteralEncoder.scala:117:29] wire _dic_writer_io_memwrites_in_ready; // @[ZstdLiteralEncoder.scala:112:26] wire _dic_writer_io_decompress_dest_info_ready; // @[ZstdLiteralEncoder.scala:112:26] wire [5:0] _dic_builder_io_cnt_stream_user_consumed_bytes; // @[ZstdLiteralEncoder.scala:106:27] wire _dic_builder_io_cnt_stream_output_ready; // @[ZstdLiteralEncoder.scala:106:27] wire _dic_builder_io_symbol_info_0_ready; // @[ZstdLiteralEncoder.scala:106:27] wire _dic_builder_io_symbol_info_1_ready; // @[ZstdLiteralEncoder.scala:106:27] wire _dic_builder_io_dic_info_0_valid; // @[ZstdLiteralEncoder.scala:106:27] wire [31:0] _dic_builder_io_dic_info_0_bits_entry; // @[ZstdLiteralEncoder.scala:106:27] wire _dic_builder_io_dic_info_0_bits_from_last_symbol; // @[ZstdLiteralEncoder.scala:106:27] wire _dic_builder_io_dic_info_1_valid; // @[ZstdLiteralEncoder.scala:106:27] wire [31:0] _dic_builder_io_dic_info_1_bits_entry; // @[ZstdLiteralEncoder.scala:106:27] wire _dic_builder_io_dic_info_1_bits_from_last_symbol; // @[ZstdLiteralEncoder.scala:106:27] wire _dic_builder_io_header_writes_valid; // @[ZstdLiteralEncoder.scala:106:27] wire [255:0] _dic_builder_io_header_writes_bits_data; // @[ZstdLiteralEncoder.scala:106:27] wire [5:0] _dic_builder_io_header_writes_bits_validbytes; // @[ZstdLiteralEncoder.scala:106:27] wire _dic_builder_io_header_writes_bits_end_of_message; // @[ZstdLiteralEncoder.scala:106:27] wire _dic_builder_io_header_written_bytes_valid; // @[ZstdLiteralEncoder.scala:106:27] wire [63:0] _dic_builder_io_header_written_bytes_bits; // @[ZstdLiteralEncoder.scala:106:27] wire _dic_builder_io_header_size_info_valid; // @[ZstdLiteralEncoder.scala:106:27] wire [7:0] _dic_builder_io_header_size_info_bits; // @[ZstdLiteralEncoder.scala:106:27] wire _dic_builder_io_init_dictionary_ready; // @[ZstdLiteralEncoder.scala:106:27] wire [5:0] _dic_memloader_io_consumer_available_output_bytes; // @[ZstdLiteralEncoder.scala:102:29] wire _dic_memloader_io_consumer_output_valid; // @[ZstdLiteralEncoder.scala:102:29] wire [255:0] _dic_memloader_io_consumer_output_data; // @[ZstdLiteralEncoder.scala:102:29] wire _dic_memloader_io_consumer_output_last_chunk; // @[ZstdLiteralEncoder.scala:102:29] wire _jt_writer_io_memwrites_in_ready; // @[ZstdLiteralEncoder.scala:97:25] wire _jt_writer_io_decompress_dest_info_ready; // @[ZstdLiteralEncoder.scala:97:25] wire _hdr_writer_io_memwrites_in_ready; // @[ZstdLiteralEncoder.scala:91:26] wire _hdr_writer_io_decompress_dest_info_ready; // @[ZstdLiteralEncoder.scala:91:26] wire _hdr_writer_io_custom_write_value_ready; // @[ZstdLiteralEncoder.scala:91:26] wire _hdr_writer_io_no_writes_inflight; // @[ZstdLiteralEncoder.scala:91:26] wire _controller_io_lit_src_info_valid; // @[ZstdLiteralEncoder.scala:78:26] wire [63:0] _controller_io_lit_src_info_bits_ip; // @[ZstdLiteralEncoder.scala:78:26] wire [63:0] _controller_io_lit_src_info_bits_isize; // @[ZstdLiteralEncoder.scala:78:26] wire _controller_io_lit_dst_info_valid; // @[ZstdLiteralEncoder.scala:78:26] wire [63:0] _controller_io_lit_dst_info_bits_op; // @[ZstdLiteralEncoder.scala:78:26] wire [63:0] _controller_io_lit_dst_info_bits_cmpflag; // @[ZstdLiteralEncoder.scala:78:26] wire _controller_io_compressed_bytes_ready; // @[ZstdLiteralEncoder.scala:78:26] wire _controller_io_hdr_dst_info_valid; // @[ZstdLiteralEncoder.scala:78:26] wire [63:0] _controller_io_hdr_dst_info_bits_op; // @[ZstdLiteralEncoder.scala:78:26] wire [63:0] _controller_io_hdr_dst_info_bits_cmpflag; // @[ZstdLiteralEncoder.scala:78:26] wire _controller_io_hdr_writes_valid; // @[ZstdLiteralEncoder.scala:78:26] wire [255:0] _controller_io_hdr_writes_bits_data; // @[ZstdLiteralEncoder.scala:78:26] wire [5:0] _controller_io_hdr_writes_bits_validbytes; // @[ZstdLiteralEncoder.scala:78:26] wire _controller_io_jt_dst_info_valid; // @[ZstdLiteralEncoder.scala:78:26] wire [63:0] _controller_io_jt_dst_info_bits_op; // @[ZstdLiteralEncoder.scala:78:26] wire _controller_io_jt_writes_valid; // @[ZstdLiteralEncoder.scala:78:26] wire [255:0] _controller_io_jt_writes_bits_data; // @[ZstdLiteralEncoder.scala:78:26] wire _controller_io_weight_dst_info_valid; // @[ZstdLiteralEncoder.scala:78:26] wire [63:0] _controller_io_weight_dst_info_bits_op; // @[ZstdLiteralEncoder.scala:78:26] wire _controller_io_weight_bytes_ready; // @[ZstdLiteralEncoder.scala:78:26] wire _controller_io_header_size_info_ready; // @[ZstdLiteralEncoder.scala:78:26] wire _controller_io_total_write_bytes2_valid; // @[ZstdLiteralEncoder.scala:78:26] wire [63:0] _controller_io_total_write_bytes2_bits; // @[ZstdLiteralEncoder.scala:78:26] wire _controller_io_init_dictionary_valid; // @[ZstdLiteralEncoder.scala:78:26] wire [63:0] _controller_io_bufs_completed; // @[ZstdLiteralEncoder.scala:78:26] wire io_src_info_valid_0 = io_src_info_valid; // @[ZstdLiteralEncoder.scala:62:7] wire [63:0] io_src_info_bits_ip_0 = io_src_info_bits_ip; // @[ZstdLiteralEncoder.scala:62:7] wire [63:0] io_src_info_bits_isize_0 = io_src_info_bits_isize; // @[ZstdLiteralEncoder.scala:62:7] wire io_src_info2_valid_0 = io_src_info2_valid; // @[ZstdLiteralEncoder.scala:62:7] wire [63:0] io_src_info2_bits_ip_0 = io_src_info2_bits_ip; // @[ZstdLiteralEncoder.scala:62:7] wire [63:0] io_src_info2_bits_isize_0 = io_src_info2_bits_isize; // @[ZstdLiteralEncoder.scala:62:7] wire io_dst_info_valid_0 = io_dst_info_valid; // @[ZstdLiteralEncoder.scala:62:7] wire [63:0] io_dst_info_bits_op_0 = io_dst_info_bits_op; // @[ZstdLiteralEncoder.scala:62:7] wire [63:0] io_dst_info_bits_cmpflag_0 = io_dst_info_bits_cmpflag; // @[ZstdLiteralEncoder.scala:62:7] wire [63:0] io_dst_info_bits_cmpval_0 = io_dst_info_bits_cmpval; // @[ZstdLiteralEncoder.scala:62:7] wire io_bytes_written_ready_0 = io_bytes_written_ready; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_lit_reader_req_ready_0 = io_l2if_lit_reader_req_ready; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_lit_reader_resp_valid_0 = io_l2if_lit_reader_resp_valid; // @[ZstdLiteralEncoder.scala:62:7] wire [255:0] io_l2if_lit_reader_resp_bits_data_0 = io_l2if_lit_reader_resp_bits_data; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_lit_reader_no_memops_inflight_0 = io_l2if_lit_reader_no_memops_inflight; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_dic_reader_req_ready_0 = io_l2if_dic_reader_req_ready; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_dic_reader_resp_valid_0 = io_l2if_dic_reader_resp_valid; // @[ZstdLiteralEncoder.scala:62:7] wire [255:0] io_l2if_dic_reader_resp_bits_data_0 = io_l2if_dic_reader_resp_bits_data; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_dic_reader_no_memops_inflight_0 = io_l2if_dic_reader_no_memops_inflight; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_dic_writer_req_ready_0 = io_l2if_dic_writer_req_ready; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_dic_writer_resp_valid_0 = io_l2if_dic_writer_resp_valid; // @[ZstdLiteralEncoder.scala:62:7] wire [255:0] io_l2if_dic_writer_resp_bits_data_0 = io_l2if_dic_writer_resp_bits_data; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_dic_writer_no_memops_inflight_0 = io_l2if_dic_writer_no_memops_inflight; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_hdr_writer_req_ready_0 = io_l2if_hdr_writer_req_ready; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_hdr_writer_resp_valid_0 = io_l2if_hdr_writer_resp_valid; // @[ZstdLiteralEncoder.scala:62:7] wire [255:0] io_l2if_hdr_writer_resp_bits_data_0 = io_l2if_hdr_writer_resp_bits_data; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_hdr_writer_no_memops_inflight_0 = io_l2if_hdr_writer_no_memops_inflight; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_jt_writer_req_ready_0 = io_l2if_jt_writer_req_ready; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_jt_writer_resp_valid_0 = io_l2if_jt_writer_resp_valid; // @[ZstdLiteralEncoder.scala:62:7] wire [255:0] io_l2if_jt_writer_resp_bits_data_0 = io_l2if_jt_writer_resp_bits_data; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_jt_writer_no_memops_inflight_0 = io_l2if_jt_writer_no_memops_inflight; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_lit_writer_req_ready_0 = io_l2if_lit_writer_req_ready; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_lit_writer_resp_valid_0 = io_l2if_lit_writer_resp_valid; // @[ZstdLiteralEncoder.scala:62:7] wire [255:0] io_l2if_lit_writer_resp_bits_data_0 = io_l2if_lit_writer_resp_bits_data; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_lit_writer_no_memops_inflight_0 = io_l2if_lit_writer_no_memops_inflight; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_dic_writer_req_bits_cmd_0 = 1'h1; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_dic_writer_resp_ready_0 = 1'h1; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_hdr_writer_req_bits_cmd_0 = 1'h1; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_hdr_writer_resp_ready_0 = 1'h1; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_jt_writer_req_bits_cmd_0 = 1'h1; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_jt_writer_resp_ready_0 = 1'h1; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_lit_writer_req_bits_cmd_0 = 1'h1; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_lit_writer_resp_ready_0 = 1'h1; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_lit_reader_req_bits_cmd_0 = 1'h0; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_dic_reader_req_bits_cmd_0 = 1'h0; // @[ZstdLiteralEncoder.scala:62:7] wire [255:0] io_l2if_lit_reader_req_bits_data_0 = 256'h0; // @[ZstdLiteralEncoder.scala:62:7] wire [255:0] io_l2if_dic_reader_req_bits_data_0 = 256'h0; // @[ZstdLiteralEncoder.scala:62:7] wire [2:0] io_l2if_lit_reader_req_bits_size_0 = 3'h5; // @[ZstdLiteralEncoder.scala:62:7] wire [2:0] io_l2if_dic_reader_req_bits_size_0 = 3'h5; // @[ZstdLiteralEncoder.scala:62:7] wire _io_busy_T; // @[ZstdLiteralEncoder.scala:133:14] wire io_src_info_ready_0; // @[ZstdLiteralEncoder.scala:62:7] wire io_src_info2_ready_0; // @[ZstdLiteralEncoder.scala:62:7] wire io_dst_info_ready_0; // @[ZstdLiteralEncoder.scala:62:7] wire io_bytes_written_valid_0; // @[ZstdLiteralEncoder.scala:62:7] wire [63:0] io_bytes_written_bits_0; // @[ZstdLiteralEncoder.scala:62:7] wire [70:0] io_l2if_lit_reader_req_bits_addr_0; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_lit_reader_req_valid_0; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_lit_reader_resp_ready_0; // @[ZstdLiteralEncoder.scala:62:7] wire [70:0] io_l2if_dic_reader_req_bits_addr_0; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_dic_reader_req_valid_0; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_dic_reader_resp_ready_0; // @[ZstdLiteralEncoder.scala:62:7] wire [63:0] io_l2if_dic_writer_req_bits_addr_0; // @[ZstdLiteralEncoder.scala:62:7] wire [2:0] io_l2if_dic_writer_req_bits_size_0; // @[ZstdLiteralEncoder.scala:62:7] wire [255:0] io_l2if_dic_writer_req_bits_data_0; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_dic_writer_req_valid_0; // @[ZstdLiteralEncoder.scala:62:7] wire [63:0] io_l2if_hdr_writer_req_bits_addr_0; // @[ZstdLiteralEncoder.scala:62:7] wire [2:0] io_l2if_hdr_writer_req_bits_size_0; // @[ZstdLiteralEncoder.scala:62:7] wire [255:0] io_l2if_hdr_writer_req_bits_data_0; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_hdr_writer_req_valid_0; // @[ZstdLiteralEncoder.scala:62:7] wire [63:0] io_l2if_jt_writer_req_bits_addr_0; // @[ZstdLiteralEncoder.scala:62:7] wire [2:0] io_l2if_jt_writer_req_bits_size_0; // @[ZstdLiteralEncoder.scala:62:7] wire [255:0] io_l2if_jt_writer_req_bits_data_0; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_jt_writer_req_valid_0; // @[ZstdLiteralEncoder.scala:62:7] wire [63:0] io_l2if_lit_writer_req_bits_addr_0; // @[ZstdLiteralEncoder.scala:62:7] wire [2:0] io_l2if_lit_writer_req_bits_size_0; // @[ZstdLiteralEncoder.scala:62:7] wire [255:0] io_l2if_lit_writer_req_bits_data_0; // @[ZstdLiteralEncoder.scala:62:7] wire io_l2if_lit_writer_req_valid_0; // @[ZstdLiteralEncoder.scala:62:7] wire io_busy_0; // @[ZstdLiteralEncoder.scala:62:7] reg [63:0] dispatched_src_cnt; // @[ZstdLiteralEncoder.scala:70:35] wire _T_10 = io_src_info_ready_0 & io_src_info_valid_0; // @[Decoupled.scala:51:35] wire [64:0] _nxt_dispatched_src_cnt_T = {1'h0, dispatched_src_cnt} + 65'h1; // @[ZstdLiteralEncoder.scala:70:35, :73:53] wire [63:0] nxt_dispatched_src_cnt = _nxt_dispatched_src_cnt_T[63:0]; // @[ZstdLiteralEncoder.scala:73:53] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_43 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_43 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_43 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_62 connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags	module MulAddRecFN_e8_s24_43( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_43 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_43 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_62 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_8 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid \|\| io.clear \|\| io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state	module IssueSlot_8( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 \| io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 \| _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN \| ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN \| ~_T_12 \| p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module TLSplitACDxBENoC_be_router_15ClockSinkDomain : output auto : { egress_width_widget_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, ingress_id : UInt}}}, flip ingress_width_widget_in : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<148>, egress_id : UInt}}}, routers_debug_out : { va_stall : UInt[2], sa_stall : UInt[2]}, routers_source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip routers_dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}, flip clock_in : { clock : Clock, reset : Reset}} output clock : Clock output reset : Reset wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst routers of Router_31 connect routers.clock, childClock connect routers.reset, childReset inst ingress_width_widget of IngressWidthWidget_17 connect ingress_width_widget.clock, childClock connect ingress_width_widget.reset, childReset inst egress_width_widget of EgressWidthWidget_17 connect egress_width_widget.clock, childClock connect egress_width_widget.reset, childReset wire clockNodeIn : { clock : Clock, reset : Reset} invalidate clockNodeIn.reset invalidate clockNodeIn.clock connect egress_width_widget.auto.in, routers.auto.egress_nodes_out connect routers.auto.ingress_nodes_in, ingress_width_widget.auto.out connect clockNodeIn, auto.clock_in connect routers.auto.dest_nodes_in, auto.routers_dest_nodes_in connect routers.auto.source_nodes_out.vc_free, auto.routers_source_nodes_out.vc_free connect routers.auto.source_nodes_out.credit_return, auto.routers_source_nodes_out.credit_return connect auto.routers_source_nodes_out.flit, routers.auto.source_nodes_out.flit connect auto.routers_debug_out, routers.auto.debug_out connect ingress_width_widget.auto.in, auto.ingress_width_widget_in connect auto.egress_width_widget_out.flit.bits, egress_width_widget.auto.out.flit.bits connect auto.egress_width_widget_out.flit.valid, egress_width_widget.auto.out.flit.valid connect egress_width_widget.auto.out.flit.ready, auto.egress_width_widget_out.flit.ready connect childClock, clockNodeIn.clock connect childReset, clockNodeIn.reset connect clock, clockNodeIn.clock connect reset, clockNodeIn.reset	module TLSplitACDxBENoC_be_router_15ClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_egress_width_widget_out_flit_ready, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_valid, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_head, // @[LazyModuleImp.scala:107:25] output auto_egress_width_widget_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25] output [147:0] auto_egress_width_widget_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_ingress_width_widget_in_flit_ready, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_valid, // @[LazyModuleImp.scala:107:25] input auto_ingress_width_widget_in_flit_bits_head, // @[LazyModuleImp.scala:107:25] input [147:0] auto_ingress_width_widget_in_flit_bits_payload, // @[LazyModuleImp.scala:107:25] input [4:0] auto_ingress_width_widget_in_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [36:0] auto_routers_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [3:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output auto_routers_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [36:0] auto_routers_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [3:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25] output [1:0] auto_routers_dest_nodes_in_vc_free, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _egress_width_widget_auto_in_flit_ready; // @[WidthWidget.scala:111:43] wire _ingress_width_widget_auto_out_flit_valid; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_head; // @[WidthWidget.scala:88:44] wire _ingress_width_widget_auto_out_flit_bits_tail; // @[WidthWidget.scala:88:44] wire [36:0] _ingress_width_widget_auto_out_flit_bits_payload; // @[WidthWidget.scala:88:44] wire [4:0] _ingress_width_widget_auto_out_flit_bits_egress_id; // @[WidthWidget.scala:88:44] wire _routers_auto_egress_nodes_out_flit_valid; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_head; // @[NoC.scala:67:22] wire _routers_auto_egress_nodes_out_flit_bits_tail; // @[NoC.scala:67:22] wire [36:0] _routers_auto_egress_nodes_out_flit_bits_payload; // @[NoC.scala:67:22] wire _routers_auto_ingress_nodes_in_flit_ready; // @[NoC.scala:67:22] Router_31 routers ( // @[NoC.scala:67:22] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0), .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1), .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0), .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1), .auto_egress_nodes_out_flit_ready (_egress_width_widget_auto_in_flit_ready), // @[WidthWidget.scala:111:43] .auto_egress_nodes_out_flit_valid (_routers_auto_egress_nodes_out_flit_valid), .auto_egress_nodes_out_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), .auto_egress_nodes_out_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), .auto_egress_nodes_out_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), .auto_ingress_nodes_in_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), .auto_ingress_nodes_in_flit_valid (_ingress_width_widget_auto_out_flit_valid), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), // @[WidthWidget.scala:88:44] .auto_ingress_nodes_in_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id), // @[WidthWidget.scala:88:44] .auto_source_nodes_out_flit_0_valid (auto_routers_source_nodes_out_flit_0_valid), .auto_source_nodes_out_flit_0_bits_head (auto_routers_source_nodes_out_flit_0_bits_head), .auto_source_nodes_out_flit_0_bits_tail (auto_routers_source_nodes_out_flit_0_bits_tail), .auto_source_nodes_out_flit_0_bits_payload (auto_routers_source_nodes_out_flit_0_bits_payload), .auto_source_nodes_out_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id), .auto_source_nodes_out_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node), .auto_source_nodes_out_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id), .auto_source_nodes_out_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node), .auto_source_nodes_out_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id), .auto_source_nodes_out_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_flit_0_bits_virt_channel_id), .auto_source_nodes_out_credit_return (auto_routers_source_nodes_out_credit_return), .auto_source_nodes_out_vc_free (auto_routers_source_nodes_out_vc_free), .auto_dest_nodes_in_flit_0_valid (auto_routers_dest_nodes_in_flit_0_valid), .auto_dest_nodes_in_flit_0_bits_head (auto_routers_dest_nodes_in_flit_0_bits_head), .auto_dest_nodes_in_flit_0_bits_tail (auto_routers_dest_nodes_in_flit_0_bits_tail), .auto_dest_nodes_in_flit_0_bits_payload (auto_routers_dest_nodes_in_flit_0_bits_payload), .auto_dest_nodes_in_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_flit_0_bits_flow_vnet_id), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node), .auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_ingress_node_id), .auto_dest_nodes_in_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node), .auto_dest_nodes_in_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_flit_0_bits_flow_egress_node_id), .auto_dest_nodes_in_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_flit_0_bits_virt_channel_id), .auto_dest_nodes_in_credit_return (auto_routers_dest_nodes_in_credit_return), .auto_dest_nodes_in_vc_free (auto_routers_dest_nodes_in_vc_free) ); // @[NoC.scala:67:22] IngressWidthWidget ingress_width_widget ( // @[WidthWidget.scala:88:44] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (auto_ingress_width_widget_in_flit_ready), .auto_in_flit_valid (auto_ingress_width_widget_in_flit_valid), .auto_in_flit_bits_head (auto_ingress_width_widget_in_flit_bits_head), .auto_in_flit_bits_payload (auto_ingress_width_widget_in_flit_bits_payload), .auto_in_flit_bits_egress_id (auto_ingress_width_widget_in_flit_bits_egress_id), .auto_out_flit_ready (_routers_auto_ingress_nodes_in_flit_ready), // @[NoC.scala:67:22] .auto_out_flit_valid (_ingress_width_widget_auto_out_flit_valid), .auto_out_flit_bits_head (_ingress_width_widget_auto_out_flit_bits_head), .auto_out_flit_bits_tail (_ingress_width_widget_auto_out_flit_bits_tail), .auto_out_flit_bits_payload (_ingress_width_widget_auto_out_flit_bits_payload), .auto_out_flit_bits_egress_id (_ingress_width_widget_auto_out_flit_bits_egress_id) ); // @[WidthWidget.scala:88:44] EgressWidthWidget_1 egress_width_widget ( // @[WidthWidget.scala:111:43] .clock (auto_clock_in_clock), .reset (auto_clock_in_reset), .auto_in_flit_ready (_egress_width_widget_auto_in_flit_ready), .auto_in_flit_valid (_routers_auto_egress_nodes_out_flit_valid), // @[NoC.scala:67:22] .auto_in_flit_bits_head (_routers_auto_egress_nodes_out_flit_bits_head), // @[NoC.scala:67:22] .auto_in_flit_bits_tail (_routers_auto_egress_nodes_out_flit_bits_tail), // @[NoC.scala:67:22] .auto_in_flit_bits_payload (_routers_auto_egress_nodes_out_flit_bits_payload), // @[NoC.scala:67:22] .auto_out_flit_ready (auto_egress_width_widget_out_flit_ready), .auto_out_flit_valid (auto_egress_width_widget_out_flit_valid), .auto_out_flit_bits_head (auto_egress_width_widget_out_flit_bits_head), .auto_out_flit_bits_tail (auto_egress_width_widget_out_flit_bits_tail), .auto_out_flit_bits_payload (auto_egress_width_widget_out_flit_bits_payload) ); // @[WidthWidget.scala:111:43] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PixelRepeater_1 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { in : SInt<8>[16], mask : UInt<1>[16], laddr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, len : UInt<5>, pixel_repeats : UInt<8>, last : UInt<1>, tag : { data : UInt<512>, addr : UInt<14>, mask : UInt<1>[64], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { out : SInt<8>[16], mask : UInt<1>[16], laddr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, last : UInt<1>, tag : { data : UInt<512>, addr : UInt<14>, mask : UInt<1>[64], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}} reg req : { valid : UInt<1>, bits : { in : SInt<8>[16], mask : UInt<1>[16], laddr : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>}, len : UInt<5>, pixel_repeats : UInt<8>, last : UInt<1>, tag : { data : UInt<512>, addr : UInt<14>, mask : UInt<1>[64], is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<16>, len : UInt<16>, last : UInt<1>, bytes_read : UInt<8>, cmd_id : UInt<8>}}}, clock node _io_req_ready_T = eq(req.valid, UInt<1>(0h0)) node _io_req_ready_T_1 = eq(req.bits.pixel_repeats, UInt<1>(0h0)) node _io_req_ready_T_2 = and(io.resp.ready, _io_req_ready_T_1) node _io_req_ready_T_3 = or(_io_req_ready_T, _io_req_ready_T_2) connect io.req.ready, _io_req_ready_T_3 wire out_shift : UInt<4> node _out_shift_T = mul(req.bits.pixel_repeats, req.bits.len) connect out_shift, _out_shift_T node _T = asUInt(req.bits.in[0]) node _T_1 = asUInt(req.bits.in[1]) node _T_2 = asUInt(req.bits.in[2]) node _T_3 = asUInt(req.bits.in[3]) node _T_4 = asUInt(req.bits.in[4]) node _T_5 = asUInt(req.bits.in[5]) node _T_6 = asUInt(req.bits.in[6]) node _T_7 = asUInt(req.bits.in[7]) node _T_8 = asUInt(req.bits.in[8]) node _T_9 = asUInt(req.bits.in[9]) node _T_10 = asUInt(req.bits.in[10]) node _T_11 = asUInt(req.bits.in[11]) node _T_12 = asUInt(req.bits.in[12]) node _T_13 = asUInt(req.bits.in[13]) node _T_14 = asUInt(req.bits.in[14]) node _T_15 = asUInt(req.bits.in[15]) node lo_lo_lo = cat(_T_1, _T) node lo_lo_hi = cat(_T_3, _T_2) node lo_lo = cat(lo_lo_hi, lo_lo_lo) node lo_hi_lo = cat(_T_5, _T_4) node lo_hi_hi = cat(_T_7, _T_6) node lo_hi = cat(lo_hi_hi, lo_hi_lo) node lo = cat(lo_hi, lo_lo) node hi_lo_lo = cat(_T_9, _T_8) node hi_lo_hi = cat(_T_11, _T_10) node hi_lo = cat(hi_lo_hi, hi_lo_lo) node hi_hi_lo = cat(_T_13, _T_12) node hi_hi_hi = cat(_T_15, _T_14) node hi_hi = cat(hi_hi_hi, hi_hi_lo) node hi = cat(hi_hi, hi_lo) node _T_16 = cat(hi, lo) node _T_17 = mul(out_shift, UInt<4>(0h8)) node _T_18 = dshl(_T_16, _T_17) wire _WIRE : SInt<8>[16] wire _WIRE_1 : UInt<128> connect _WIRE_1, _T_18 node _T_19 = bits(_WIRE_1, 7, 0) node _T_20 = asSInt(_T_19) connect _WIRE[0], _T_20 node _T_21 = bits(_WIRE_1, 15, 8) node _T_22 = asSInt(_T_21) connect _WIRE[1], _T_22 node _T_23 = bits(_WIRE_1, 23, 16) node _T_24 = asSInt(_T_23) connect _WIRE[2], _T_24 node _T_25 = bits(_WIRE_1, 31, 24) node _T_26 = asSInt(_T_25) connect _WIRE[3], _T_26 node _T_27 = bits(_WIRE_1, 39, 32) node _T_28 = asSInt(_T_27) connect _WIRE[4], _T_28 node _T_29 = bits(_WIRE_1, 47, 40) node _T_30 = asSInt(_T_29) connect _WIRE[5], _T_30 node _T_31 = bits(_WIRE_1, 55, 48) node _T_32 = asSInt(_T_31) connect _WIRE[6], _T_32 node _T_33 = bits(_WIRE_1, 63, 56) node _T_34 = asSInt(_T_33) connect _WIRE[7], _T_34 node _T_35 = bits(_WIRE_1, 71, 64) node _T_36 = asSInt(_T_35) connect _WIRE[8], _T_36 node _T_37 = bits(_WIRE_1, 79, 72) node _T_38 = asSInt(_T_37) connect _WIRE[9], _T_38 node _T_39 = bits(_WIRE_1, 87, 80) node _T_40 = asSInt(_T_39) connect _WIRE[10], _T_40 node _T_41 = bits(_WIRE_1, 95, 88) node _T_42 = asSInt(_T_41) connect _WIRE[11], _T_42 node _T_43 = bits(_WIRE_1, 103, 96) node _T_44 = asSInt(_T_43) connect _WIRE[12], _T_44 node _T_45 = bits(_WIRE_1, 111, 104) node _T_46 = asSInt(_T_45) connect _WIRE[13], _T_46 node _T_47 = bits(_WIRE_1, 119, 112) node _T_48 = asSInt(_T_47) connect _WIRE[14], _T_48 node _T_49 = bits(_WIRE_1, 127, 120) node _T_50 = asSInt(_T_49) connect _WIRE[15], _T_50 connect io.resp.bits.out, _WIRE node lo_lo_lo_1 = cat(req.bits.mask[1], req.bits.mask[0]) node lo_lo_hi_1 = cat(req.bits.mask[3], req.bits.mask[2]) node lo_lo_1 = cat(lo_lo_hi_1, lo_lo_lo_1) node lo_hi_lo_1 = cat(req.bits.mask[5], req.bits.mask[4]) node lo_hi_hi_1 = cat(req.bits.mask[7], req.bits.mask[6]) node lo_hi_1 = cat(lo_hi_hi_1, lo_hi_lo_1) node lo_1 = cat(lo_hi_1, lo_lo_1) node hi_lo_lo_1 = cat(req.bits.mask[9], req.bits.mask[8]) node hi_lo_hi_1 = cat(req.bits.mask[11], req.bits.mask[10]) node hi_lo_1 = cat(hi_lo_hi_1, hi_lo_lo_1) node hi_hi_lo_1 = cat(req.bits.mask[13], req.bits.mask[12]) node hi_hi_hi_1 = cat(req.bits.mask[15], req.bits.mask[14]) node hi_hi_1 = cat(hi_hi_hi_1, hi_hi_lo_1) node hi_1 = cat(hi_hi_1, hi_lo_1) node _T_51 = cat(hi_1, lo_1) node _T_52 = mul(out_shift, UInt<1>(0h1)) node _T_53 = dshl(_T_51, _T_52) wire _WIRE_2 : UInt<1>[16] wire _WIRE_3 : UInt<16> connect _WIRE_3, _T_53 node _T_54 = bits(_WIRE_3, 0, 0) connect _WIRE_2[0], _T_54 node _T_55 = bits(_WIRE_3, 1, 1) connect _WIRE_2[1], _T_55 node _T_56 = bits(_WIRE_3, 2, 2) connect _WIRE_2[2], _T_56 node _T_57 = bits(_WIRE_3, 3, 3) connect _WIRE_2[3], _T_57 node _T_58 = bits(_WIRE_3, 4, 4) connect _WIRE_2[4], _T_58 node _T_59 = bits(_WIRE_3, 5, 5) connect _WIRE_2[5], _T_59 node _T_60 = bits(_WIRE_3, 6, 6) connect _WIRE_2[6], _T_60 node _T_61 = bits(_WIRE_3, 7, 7) connect _WIRE_2[7], _T_61 node _T_62 = bits(_WIRE_3, 8, 8) connect _WIRE_2[8], _T_62 node _T_63 = bits(_WIRE_3, 9, 9) connect _WIRE_2[9], _T_63 node _T_64 = bits(_WIRE_3, 10, 10) connect _WIRE_2[10], _T_64 node _T_65 = bits(_WIRE_3, 11, 11) connect _WIRE_2[11], _T_65 node _T_66 = bits(_WIRE_3, 12, 12) connect _WIRE_2[12], _T_66 node _T_67 = bits(_WIRE_3, 13, 13) connect _WIRE_2[13], _T_67 node _T_68 = bits(_WIRE_3, 14, 14) connect _WIRE_2[14], _T_68 node _T_69 = bits(_WIRE_3, 15, 15) connect _WIRE_2[15], _T_69 connect io.resp.bits.mask, _WIRE_2 node _io_resp_bits_last_T = eq(req.bits.pixel_repeats, UInt<1>(0h0)) node _io_resp_bits_last_T_1 = and(req.bits.last, _io_resp_bits_last_T) connect io.resp.bits.last, _io_resp_bits_last_T_1 connect io.resp.bits.tag, req.bits.tag node _T_70 = and(req.valid, req.bits.laddr.is_acc_addr) node _T_71 = gt(req.bits.pixel_repeats, UInt<1>(0h0)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PixelRepeater.scala:58 assert(!(req.valid && is_acc_addr && req.bits.pixel_repeats > 0.U))\n") : printf assert(clock, _T_73, UInt<1>(0h1), "") : assert node _sp_addr_T = bits(req.bits.laddr.data, 13, 0) node _sp_addr_T_1 = lt(_sp_addr_T, UInt<14>(0h2000)) node _sp_addr_underflow_T = add(UInt<1>(0h0), req.bits.pixel_repeats) node sp_addr_underflow = lt(req.bits.laddr.data, _sp_addr_underflow_T) wire sp_addr_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect sp_addr_result, req.bits.laddr node _sp_addr_result_data_T = sub(req.bits.laddr.data, req.bits.pixel_repeats) node _sp_addr_result_data_T_1 = tail(_sp_addr_result_data_T, 1) node _sp_addr_result_data_T_2 = mux(sp_addr_underflow, UInt<1>(0h0), _sp_addr_result_data_T_1) connect sp_addr_result.data, _sp_addr_result_data_T_2 node _sp_addr_underflow_T_1 = add(UInt<14>(0h2000), req.bits.pixel_repeats) node sp_addr_underflow_1 = lt(req.bits.laddr.data, _sp_addr_underflow_T_1) wire sp_addr_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect sp_addr_result_1, req.bits.laddr node _sp_addr_result_data_T_3 = sub(req.bits.laddr.data, req.bits.pixel_repeats) node _sp_addr_result_data_T_4 = tail(_sp_addr_result_data_T_3, 1) node _sp_addr_result_data_T_5 = mux(sp_addr_underflow_1, UInt<14>(0h2000), _sp_addr_result_data_T_4) connect sp_addr_result_1.data, _sp_addr_result_data_T_5 node sp_addr = mux(_sp_addr_T_1, sp_addr_result, sp_addr_result_1) node _underflow_T = eq(req.bits.laddr.is_acc_addr, UInt<1>(0h0)) node _underflow_T_1 = bits(req.bits.laddr.data, 13, 0) node _underflow_T_2 = lt(_underflow_T_1, UInt<14>(0h2000)) node _underflow_underflow_T = add(UInt<1>(0h0), req.bits.pixel_repeats) node underflow_underflow = lt(req.bits.laddr.data, _underflow_underflow_T) wire underflow_result : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect underflow_result, req.bits.laddr node _underflow_result_data_T = sub(req.bits.laddr.data, req.bits.pixel_repeats) node _underflow_result_data_T_1 = tail(_underflow_result_data_T, 1) node _underflow_result_data_T_2 = mux(underflow_underflow, UInt<1>(0h0), _underflow_result_data_T_1) connect underflow_result.data, _underflow_result_data_T_2 node _underflow_underflow_T_1 = add(UInt<14>(0h2000), req.bits.pixel_repeats) node underflow_underflow_1 = lt(req.bits.laddr.data, _underflow_underflow_T_1) wire underflow_result_1 : { is_acc_addr : UInt<1>, accumulate : UInt<1>, read_full_acc_row : UInt<1>, norm_cmd : UInt<3>, garbage : UInt<11>, garbage_bit : UInt<1>, data : UInt<14>} connect underflow_result_1, req.bits.laddr node _underflow_result_data_T_3 = sub(req.bits.laddr.data, req.bits.pixel_repeats) node _underflow_result_data_T_4 = tail(_underflow_result_data_T_3, 1) node _underflow_result_data_T_5 = mux(underflow_underflow_1, UInt<14>(0h2000), _underflow_result_data_T_4) connect underflow_result_1.data, _underflow_result_data_T_5 node _underflow_T_3 = mux(_underflow_T_2, underflow_underflow, underflow_underflow_1) node underflow = and(_underflow_T, _underflow_T_3) node _io_resp_bits_laddr_T = mux(req.bits.laddr.is_acc_addr, req.bits.laddr, sp_addr) connect io.resp.bits.laddr, _io_resp_bits_laddr_T node _io_resp_valid_T = eq(underflow, UInt<1>(0h0)) node _io_resp_valid_T_1 = and(req.valid, _io_resp_valid_T) connect io.resp.valid, _io_resp_valid_T_1 node _T_77 = and(io.resp.ready, io.resp.valid) node _T_78 = or(_T_77, underflow) when _T_78 : node _req_bits_pixel_repeats_T = sub(req.bits.pixel_repeats, UInt<1>(0h1)) node _req_bits_pixel_repeats_T_1 = tail(_req_bits_pixel_repeats_T, 1) connect req.bits.pixel_repeats, _req_bits_pixel_repeats_T_1 node _T_79 = eq(req.bits.pixel_repeats, UInt<1>(0h0)) when _T_79 : connect req.valid, UInt<1>(0h0) node _T_80 = and(io.req.ready, io.req.valid) when _T_80 : connect req.valid, UInt<1>(0h1) connect req.bits, io.req.bits node _req_bits_pixel_repeats_T_2 = sub(io.req.bits.pixel_repeats, UInt<1>(0h1)) node _req_bits_pixel_repeats_T_3 = tail(_req_bits_pixel_repeats_T_2, 1) connect req.bits.pixel_repeats, _req_bits_pixel_repeats_T_3 node _T_81 = asUInt(reset) when _T_81 : connect req.valid, UInt<1>(0h0)	module PixelRepeater_1( // @[PixelRepeater.scala:28:7] input clock, // @[PixelRepeater.scala:28:7] input reset, // @[PixelRepeater.scala:28:7] output io_req_ready, // @[PixelRepeater.scala:29:14] input io_req_valid, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_0, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_1, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_2, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_3, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_4, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_5, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_6, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_7, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_8, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_9, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_10, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_11, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_12, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_13, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_14, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_in_15, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_0, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_1, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_2, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_3, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_4, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_5, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_6, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_7, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_8, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_9, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_10, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_11, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_12, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_13, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_14, // @[PixelRepeater.scala:29:14] input io_req_bits_mask_15, // @[PixelRepeater.scala:29:14] input io_req_bits_laddr_is_acc_addr, // @[PixelRepeater.scala:29:14] input io_req_bits_laddr_accumulate, // @[PixelRepeater.scala:29:14] input io_req_bits_laddr_read_full_acc_row, // @[PixelRepeater.scala:29:14] input [2:0] io_req_bits_laddr_norm_cmd, // @[PixelRepeater.scala:29:14] input [10:0] io_req_bits_laddr_garbage, // @[PixelRepeater.scala:29:14] input io_req_bits_laddr_garbage_bit, // @[PixelRepeater.scala:29:14] input [13:0] io_req_bits_laddr_data, // @[PixelRepeater.scala:29:14] input [4:0] io_req_bits_len, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_pixel_repeats, // @[PixelRepeater.scala:29:14] input io_req_bits_last, // @[PixelRepeater.scala:29:14] input [511:0] io_req_bits_tag_data, // @[PixelRepeater.scala:29:14] input [13:0] io_req_bits_tag_addr, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_0, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_1, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_2, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_3, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_4, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_5, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_6, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_7, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_8, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_9, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_10, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_11, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_12, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_13, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_14, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_15, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_16, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_17, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_18, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_19, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_20, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_21, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_22, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_23, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_24, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_25, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_26, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_27, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_28, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_29, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_30, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_31, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_32, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_33, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_34, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_35, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_36, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_37, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_38, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_39, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_40, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_41, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_42, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_43, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_44, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_45, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_46, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_47, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_48, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_49, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_50, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_51, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_52, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_53, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_54, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_55, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_56, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_57, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_58, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_59, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_60, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_61, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_62, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_mask_63, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_is_acc, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_accumulate, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_has_acc_bitwidth, // @[PixelRepeater.scala:29:14] input [31:0] io_req_bits_tag_scale, // @[PixelRepeater.scala:29:14] input [15:0] io_req_bits_tag_repeats, // @[PixelRepeater.scala:29:14] input [15:0] io_req_bits_tag_pixel_repeats, // @[PixelRepeater.scala:29:14] input [15:0] io_req_bits_tag_len, // @[PixelRepeater.scala:29:14] input io_req_bits_tag_last, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_tag_bytes_read, // @[PixelRepeater.scala:29:14] input [7:0] io_req_bits_tag_cmd_id, // @[PixelRepeater.scala:29:14] input io_resp_ready, // @[PixelRepeater.scala:29:14] output io_resp_valid, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_0, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_1, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_2, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_3, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_4, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_5, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_6, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_7, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_8, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_9, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_10, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_11, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_12, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_13, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_14, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_out_15, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_0, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_1, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_2, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_3, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_4, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_5, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_6, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_7, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_8, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_9, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_10, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_11, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_12, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_13, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_14, // @[PixelRepeater.scala:29:14] output io_resp_bits_mask_15, // @[PixelRepeater.scala:29:14] output [13:0] io_resp_bits_laddr_data, // @[PixelRepeater.scala:29:14] output io_resp_bits_last, // @[PixelRepeater.scala:29:14] output io_resp_bits_tag_is_acc, // @[PixelRepeater.scala:29:14] output io_resp_bits_tag_accumulate, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_tag_bytes_read, // @[PixelRepeater.scala:29:14] output [7:0] io_resp_bits_tag_cmd_id // @[PixelRepeater.scala:29:14] ); wire io_req_valid_0 = io_req_valid; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_0_0 = io_req_bits_in_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_1_0 = io_req_bits_in_1; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_2_0 = io_req_bits_in_2; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_3_0 = io_req_bits_in_3; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_4_0 = io_req_bits_in_4; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_5_0 = io_req_bits_in_5; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_6_0 = io_req_bits_in_6; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_7_0 = io_req_bits_in_7; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_8_0 = io_req_bits_in_8; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_9_0 = io_req_bits_in_9; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_10_0 = io_req_bits_in_10; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_11_0 = io_req_bits_in_11; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_12_0 = io_req_bits_in_12; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_13_0 = io_req_bits_in_13; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_14_0 = io_req_bits_in_14; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_in_15_0 = io_req_bits_in_15; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_0_0 = io_req_bits_mask_0; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_1_0 = io_req_bits_mask_1; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_2_0 = io_req_bits_mask_2; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_3_0 = io_req_bits_mask_3; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_4_0 = io_req_bits_mask_4; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_5_0 = io_req_bits_mask_5; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_6_0 = io_req_bits_mask_6; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_7_0 = io_req_bits_mask_7; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_8_0 = io_req_bits_mask_8; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_9_0 = io_req_bits_mask_9; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_10_0 = io_req_bits_mask_10; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_11_0 = io_req_bits_mask_11; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_12_0 = io_req_bits_mask_12; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_13_0 = io_req_bits_mask_13; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_14_0 = io_req_bits_mask_14; // @[PixelRepeater.scala:28:7] wire io_req_bits_mask_15_0 = io_req_bits_mask_15; // @[PixelRepeater.scala:28:7] wire io_req_bits_laddr_is_acc_addr_0 = io_req_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:28:7] wire io_req_bits_laddr_accumulate_0 = io_req_bits_laddr_accumulate; // @[PixelRepeater.scala:28:7] wire io_req_bits_laddr_read_full_acc_row_0 = io_req_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:28:7] wire [2:0] io_req_bits_laddr_norm_cmd_0 = io_req_bits_laddr_norm_cmd; // @[PixelRepeater.scala:28:7] wire [10:0] io_req_bits_laddr_garbage_0 = io_req_bits_laddr_garbage; // @[PixelRepeater.scala:28:7] wire io_req_bits_laddr_garbage_bit_0 = io_req_bits_laddr_garbage_bit; // @[PixelRepeater.scala:28:7] wire [13:0] io_req_bits_laddr_data_0 = io_req_bits_laddr_data; // @[PixelRepeater.scala:28:7] wire [4:0] io_req_bits_len_0 = io_req_bits_len; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_pixel_repeats_0 = io_req_bits_pixel_repeats; // @[PixelRepeater.scala:28:7] wire io_req_bits_last_0 = io_req_bits_last; // @[PixelRepeater.scala:28:7] wire [511:0] io_req_bits_tag_data_0 = io_req_bits_tag_data; // @[PixelRepeater.scala:28:7] wire [13:0] io_req_bits_tag_addr_0 = io_req_bits_tag_addr; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_0_0 = io_req_bits_tag_mask_0; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_1_0 = io_req_bits_tag_mask_1; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_2_0 = io_req_bits_tag_mask_2; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_3_0 = io_req_bits_tag_mask_3; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_4_0 = io_req_bits_tag_mask_4; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_5_0 = io_req_bits_tag_mask_5; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_6_0 = io_req_bits_tag_mask_6; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_7_0 = io_req_bits_tag_mask_7; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_8_0 = io_req_bits_tag_mask_8; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_9_0 = io_req_bits_tag_mask_9; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_10_0 = io_req_bits_tag_mask_10; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_11_0 = io_req_bits_tag_mask_11; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_12_0 = io_req_bits_tag_mask_12; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_13_0 = io_req_bits_tag_mask_13; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_14_0 = io_req_bits_tag_mask_14; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_15_0 = io_req_bits_tag_mask_15; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_16_0 = io_req_bits_tag_mask_16; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_17_0 = io_req_bits_tag_mask_17; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_18_0 = io_req_bits_tag_mask_18; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_19_0 = io_req_bits_tag_mask_19; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_20_0 = io_req_bits_tag_mask_20; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_21_0 = io_req_bits_tag_mask_21; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_22_0 = io_req_bits_tag_mask_22; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_23_0 = io_req_bits_tag_mask_23; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_24_0 = io_req_bits_tag_mask_24; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_25_0 = io_req_bits_tag_mask_25; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_26_0 = io_req_bits_tag_mask_26; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_27_0 = io_req_bits_tag_mask_27; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_28_0 = io_req_bits_tag_mask_28; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_29_0 = io_req_bits_tag_mask_29; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_30_0 = io_req_bits_tag_mask_30; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_31_0 = io_req_bits_tag_mask_31; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_32_0 = io_req_bits_tag_mask_32; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_33_0 = io_req_bits_tag_mask_33; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_34_0 = io_req_bits_tag_mask_34; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_35_0 = io_req_bits_tag_mask_35; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_36_0 = io_req_bits_tag_mask_36; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_37_0 = io_req_bits_tag_mask_37; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_38_0 = io_req_bits_tag_mask_38; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_39_0 = io_req_bits_tag_mask_39; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_40_0 = io_req_bits_tag_mask_40; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_41_0 = io_req_bits_tag_mask_41; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_42_0 = io_req_bits_tag_mask_42; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_43_0 = io_req_bits_tag_mask_43; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_44_0 = io_req_bits_tag_mask_44; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_45_0 = io_req_bits_tag_mask_45; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_46_0 = io_req_bits_tag_mask_46; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_47_0 = io_req_bits_tag_mask_47; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_48_0 = io_req_bits_tag_mask_48; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_49_0 = io_req_bits_tag_mask_49; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_50_0 = io_req_bits_tag_mask_50; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_51_0 = io_req_bits_tag_mask_51; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_52_0 = io_req_bits_tag_mask_52; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_53_0 = io_req_bits_tag_mask_53; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_54_0 = io_req_bits_tag_mask_54; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_55_0 = io_req_bits_tag_mask_55; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_56_0 = io_req_bits_tag_mask_56; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_57_0 = io_req_bits_tag_mask_57; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_58_0 = io_req_bits_tag_mask_58; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_59_0 = io_req_bits_tag_mask_59; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_60_0 = io_req_bits_tag_mask_60; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_61_0 = io_req_bits_tag_mask_61; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_62_0 = io_req_bits_tag_mask_62; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_mask_63_0 = io_req_bits_tag_mask_63; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_is_acc_0 = io_req_bits_tag_is_acc; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_accumulate_0 = io_req_bits_tag_accumulate; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_has_acc_bitwidth_0 = io_req_bits_tag_has_acc_bitwidth; // @[PixelRepeater.scala:28:7] wire [31:0] io_req_bits_tag_scale_0 = io_req_bits_tag_scale; // @[PixelRepeater.scala:28:7] wire [15:0] io_req_bits_tag_repeats_0 = io_req_bits_tag_repeats; // @[PixelRepeater.scala:28:7] wire [15:0] io_req_bits_tag_pixel_repeats_0 = io_req_bits_tag_pixel_repeats; // @[PixelRepeater.scala:28:7] wire [15:0] io_req_bits_tag_len_0 = io_req_bits_tag_len; // @[PixelRepeater.scala:28:7] wire io_req_bits_tag_last_0 = io_req_bits_tag_last; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_tag_bytes_read_0 = io_req_bits_tag_bytes_read; // @[PixelRepeater.scala:28:7] wire [7:0] io_req_bits_tag_cmd_id_0 = io_req_bits_tag_cmd_id; // @[PixelRepeater.scala:28:7] wire io_resp_ready_0 = io_resp_ready; // @[PixelRepeater.scala:28:7] wire _io_req_ready_T_3; // @[PixelRepeater.scala:46:32] wire _io_resp_valid_T_1; // @[PixelRepeater.scala:72:32] wire _io_resp_bits_laddr_T_is_acc_addr; // @[PixelRepeater.scala:70:30] wire _io_resp_bits_laddr_T_accumulate; // @[PixelRepeater.scala:70:30] wire _io_resp_bits_laddr_T_read_full_acc_row; // @[PixelRepeater.scala:70:30] wire [2:0] _io_resp_bits_laddr_T_norm_cmd; // @[PixelRepeater.scala:70:30] wire [10:0] _io_resp_bits_laddr_T_garbage; // @[PixelRepeater.scala:70:30] wire _io_resp_bits_laddr_T_garbage_bit; // @[PixelRepeater.scala:70:30] wire [13:0] _io_resp_bits_laddr_T_data; // @[PixelRepeater.scala:70:30] wire _io_resp_bits_last_T_1; // @[PixelRepeater.scala:54:40] wire io_req_ready_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_0_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_1_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_2_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_3_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_4_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_5_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_6_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_7_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_8_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_9_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_10_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_11_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_12_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_13_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_14_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_out_15_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_0_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_1_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_2_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_3_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_4_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_5_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_6_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_7_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_8_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_9_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_10_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_11_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_12_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_13_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_14_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_mask_15_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:28:7] wire io_resp_bits_laddr_accumulate; // @[PixelRepeater.scala:28:7] wire io_resp_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:28:7] wire [2:0] io_resp_bits_laddr_norm_cmd; // @[PixelRepeater.scala:28:7] wire [10:0] io_resp_bits_laddr_garbage; // @[PixelRepeater.scala:28:7] wire io_resp_bits_laddr_garbage_bit; // @[PixelRepeater.scala:28:7] wire [13:0] io_resp_bits_laddr_data_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_1; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_2; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_3; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_4; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_5; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_6; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_7; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_8; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_9; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_10; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_11; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_12; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_13; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_14; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_15; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_16; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_17; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_18; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_19; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_20; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_21; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_22; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_23; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_24; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_25; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_26; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_27; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_28; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_29; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_30; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_31; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_32; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_33; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_34; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_35; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_36; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_37; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_38; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_39; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_40; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_41; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_42; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_43; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_44; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_45; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_46; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_47; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_48; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_49; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_50; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_51; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_52; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_53; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_54; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_55; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_56; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_57; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_58; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_59; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_60; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_61; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_62; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_mask_63; // @[PixelRepeater.scala:28:7] wire [511:0] io_resp_bits_tag_data; // @[PixelRepeater.scala:28:7] wire [13:0] io_resp_bits_tag_addr; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_is_acc_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_accumulate_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_has_acc_bitwidth; // @[PixelRepeater.scala:28:7] wire [31:0] io_resp_bits_tag_scale; // @[PixelRepeater.scala:28:7] wire [15:0] io_resp_bits_tag_repeats; // @[PixelRepeater.scala:28:7] wire [15:0] io_resp_bits_tag_pixel_repeats; // @[PixelRepeater.scala:28:7] wire [15:0] io_resp_bits_tag_len; // @[PixelRepeater.scala:28:7] wire io_resp_bits_tag_last; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_tag_bytes_read_0; // @[PixelRepeater.scala:28:7] wire [7:0] io_resp_bits_tag_cmd_id_0; // @[PixelRepeater.scala:28:7] wire io_resp_bits_last_0; // @[PixelRepeater.scala:28:7] wire io_resp_valid_0; // @[PixelRepeater.scala:28:7] reg req_valid; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_0; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_1; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_2; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_3; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_4; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_5; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_6; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_7; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_8; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_9; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_10; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_11; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_12; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_13; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_14; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_in_15; // @[PixelRepeater.scala:44:18] reg req_bits_mask_0; // @[PixelRepeater.scala:44:18] reg req_bits_mask_1; // @[PixelRepeater.scala:44:18] reg req_bits_mask_2; // @[PixelRepeater.scala:44:18] reg req_bits_mask_3; // @[PixelRepeater.scala:44:18] reg req_bits_mask_4; // @[PixelRepeater.scala:44:18] reg req_bits_mask_5; // @[PixelRepeater.scala:44:18] reg req_bits_mask_6; // @[PixelRepeater.scala:44:18] reg req_bits_mask_7; // @[PixelRepeater.scala:44:18] reg req_bits_mask_8; // @[PixelRepeater.scala:44:18] reg req_bits_mask_9; // @[PixelRepeater.scala:44:18] reg req_bits_mask_10; // @[PixelRepeater.scala:44:18] reg req_bits_mask_11; // @[PixelRepeater.scala:44:18] reg req_bits_mask_12; // @[PixelRepeater.scala:44:18] reg req_bits_mask_13; // @[PixelRepeater.scala:44:18] reg req_bits_mask_14; // @[PixelRepeater.scala:44:18] reg req_bits_mask_15; // @[PixelRepeater.scala:44:18] reg req_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:44:18] wire sp_addr_result_is_acc_addr = req_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:44:18] wire sp_addr_result_1_is_acc_addr = req_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:44:18] wire underflow_result_is_acc_addr = req_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:44:18] wire underflow_result_1_is_acc_addr = req_bits_laddr_is_acc_addr; // @[PixelRepeater.scala:44:18] reg req_bits_laddr_accumulate; // @[PixelRepeater.scala:44:18] wire sp_addr_result_accumulate = req_bits_laddr_accumulate; // @[PixelRepeater.scala:44:18] wire sp_addr_result_1_accumulate = req_bits_laddr_accumulate; // @[PixelRepeater.scala:44:18] wire underflow_result_accumulate = req_bits_laddr_accumulate; // @[PixelRepeater.scala:44:18] wire underflow_result_1_accumulate = req_bits_laddr_accumulate; // @[PixelRepeater.scala:44:18] reg req_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:44:18] wire sp_addr_result_read_full_acc_row = req_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:44:18] wire sp_addr_result_1_read_full_acc_row = req_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:44:18] wire underflow_result_read_full_acc_row = req_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:44:18] wire underflow_result_1_read_full_acc_row = req_bits_laddr_read_full_acc_row; // @[PixelRepeater.scala:44:18] reg [2:0] req_bits_laddr_norm_cmd; // @[PixelRepeater.scala:44:18] wire [2:0] sp_addr_result_norm_cmd = req_bits_laddr_norm_cmd; // @[PixelRepeater.scala:44:18] wire [2:0] sp_addr_result_1_norm_cmd = req_bits_laddr_norm_cmd; // @[PixelRepeater.scala:44:18] wire [2:0] underflow_result_norm_cmd = req_bits_laddr_norm_cmd; // @[PixelRepeater.scala:44:18] wire [2:0] underflow_result_1_norm_cmd = req_bits_laddr_norm_cmd; // @[PixelRepeater.scala:44:18] reg [10:0] req_bits_laddr_garbage; // @[PixelRepeater.scala:44:18] wire [10:0] sp_addr_result_garbage = req_bits_laddr_garbage; // @[PixelRepeater.scala:44:18] wire [10:0] sp_addr_result_1_garbage = req_bits_laddr_garbage; // @[PixelRepeater.scala:44:18] wire [10:0] underflow_result_garbage = req_bits_laddr_garbage; // @[PixelRepeater.scala:44:18] wire [10:0] underflow_result_1_garbage = req_bits_laddr_garbage; // @[PixelRepeater.scala:44:18] reg req_bits_laddr_garbage_bit; // @[PixelRepeater.scala:44:18] wire sp_addr_result_garbage_bit = req_bits_laddr_garbage_bit; // @[PixelRepeater.scala:44:18] wire sp_addr_result_1_garbage_bit = req_bits_laddr_garbage_bit; // @[PixelRepeater.scala:44:18] wire underflow_result_garbage_bit = req_bits_laddr_garbage_bit; // @[PixelRepeater.scala:44:18] wire underflow_result_1_garbage_bit = req_bits_laddr_garbage_bit; // @[PixelRepeater.scala:44:18] reg [13:0] req_bits_laddr_data; // @[PixelRepeater.scala:44:18] wire [13:0] _sp_addr_T = req_bits_laddr_data; // @[PixelRepeater.scala:44:18] wire [13:0] _underflow_T_1 = req_bits_laddr_data; // @[PixelRepeater.scala:44:18] reg [4:0] req_bits_len; // @[PixelRepeater.scala:44:18] reg [7:0] req_bits_pixel_repeats; // @[PixelRepeater.scala:44:18] reg req_bits_last; // @[PixelRepeater.scala:44:18] reg [511:0] req_bits_tag_data; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_data = req_bits_tag_data; // @[PixelRepeater.scala:28:7, :44:18] reg [13:0] req_bits_tag_addr; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_addr = req_bits_tag_addr; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_0; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_0 = req_bits_tag_mask_0; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_1; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_1 = req_bits_tag_mask_1; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_2; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_2 = req_bits_tag_mask_2; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_3; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_3 = req_bits_tag_mask_3; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_4; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_4 = req_bits_tag_mask_4; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_5; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_5 = req_bits_tag_mask_5; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_6; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_6 = req_bits_tag_mask_6; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_7; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_7 = req_bits_tag_mask_7; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_8; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_8 = req_bits_tag_mask_8; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_9; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_9 = req_bits_tag_mask_9; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_10; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_10 = req_bits_tag_mask_10; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_11; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_11 = req_bits_tag_mask_11; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_12; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_12 = req_bits_tag_mask_12; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_13; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_13 = req_bits_tag_mask_13; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_14; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_14 = req_bits_tag_mask_14; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_15; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_15 = req_bits_tag_mask_15; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_16; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_16 = req_bits_tag_mask_16; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_17; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_17 = req_bits_tag_mask_17; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_18; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_18 = req_bits_tag_mask_18; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_19; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_19 = req_bits_tag_mask_19; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_20; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_20 = req_bits_tag_mask_20; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_21; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_21 = req_bits_tag_mask_21; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_22; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_22 = req_bits_tag_mask_22; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_23; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_23 = req_bits_tag_mask_23; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_24; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_24 = req_bits_tag_mask_24; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_25; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_25 = req_bits_tag_mask_25; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_26; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_26 = req_bits_tag_mask_26; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_27; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_27 = req_bits_tag_mask_27; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_28; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_28 = req_bits_tag_mask_28; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_29; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_29 = req_bits_tag_mask_29; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_30; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_30 = req_bits_tag_mask_30; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_31; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_31 = req_bits_tag_mask_31; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_32; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_32 = req_bits_tag_mask_32; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_33; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_33 = req_bits_tag_mask_33; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_34; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_34 = req_bits_tag_mask_34; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_35; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_35 = req_bits_tag_mask_35; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_36; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_36 = req_bits_tag_mask_36; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_37; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_37 = req_bits_tag_mask_37; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_38; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_38 = req_bits_tag_mask_38; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_39; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_39 = req_bits_tag_mask_39; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_40; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_40 = req_bits_tag_mask_40; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_41; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_41 = req_bits_tag_mask_41; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_42; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_42 = req_bits_tag_mask_42; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_43; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_43 = req_bits_tag_mask_43; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_44; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_44 = req_bits_tag_mask_44; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_45; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_45 = req_bits_tag_mask_45; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_46; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_46 = req_bits_tag_mask_46; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_47; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_47 = req_bits_tag_mask_47; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_48; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_48 = req_bits_tag_mask_48; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_49; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_49 = req_bits_tag_mask_49; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_50; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_50 = req_bits_tag_mask_50; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_51; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_51 = req_bits_tag_mask_51; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_52; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_52 = req_bits_tag_mask_52; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_53; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_53 = req_bits_tag_mask_53; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_54; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_54 = req_bits_tag_mask_54; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_55; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_55 = req_bits_tag_mask_55; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_56; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_56 = req_bits_tag_mask_56; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_57; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_57 = req_bits_tag_mask_57; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_58; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_58 = req_bits_tag_mask_58; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_59; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_59 = req_bits_tag_mask_59; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_60; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_60 = req_bits_tag_mask_60; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_61; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_61 = req_bits_tag_mask_61; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_62; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_62 = req_bits_tag_mask_62; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_mask_63; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_mask_63 = req_bits_tag_mask_63; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_is_acc; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_is_acc_0 = req_bits_tag_is_acc; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_accumulate; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_accumulate_0 = req_bits_tag_accumulate; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_has_acc_bitwidth; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_has_acc_bitwidth = req_bits_tag_has_acc_bitwidth; // @[PixelRepeater.scala:28:7, :44:18] reg [31:0] req_bits_tag_scale; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_scale = req_bits_tag_scale; // @[PixelRepeater.scala:28:7, :44:18] reg [15:0] req_bits_tag_repeats; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_repeats = req_bits_tag_repeats; // @[PixelRepeater.scala:28:7, :44:18] reg [15:0] req_bits_tag_pixel_repeats; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_pixel_repeats = req_bits_tag_pixel_repeats; // @[PixelRepeater.scala:28:7, :44:18] reg [15:0] req_bits_tag_len; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_len = req_bits_tag_len; // @[PixelRepeater.scala:28:7, :44:18] reg req_bits_tag_last; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_last = req_bits_tag_last; // @[PixelRepeater.scala:28:7, :44:18] reg [7:0] req_bits_tag_bytes_read; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_bytes_read_0 = req_bits_tag_bytes_read; // @[PixelRepeater.scala:28:7, :44:18] reg [7:0] req_bits_tag_cmd_id; // @[PixelRepeater.scala:44:18] assign io_resp_bits_tag_cmd_id_0 = req_bits_tag_cmd_id; // @[PixelRepeater.scala:28:7, :44:18] wire _io_req_ready_T = ~req_valid; // @[PixelRepeater.scala:44:18, :46:21] wire _T_79 = req_bits_pixel_repeats == 8'h0; // @[PixelRepeater.scala:44:18, :46:76] wire _io_req_ready_T_1; // @[PixelRepeater.scala:46:76] assign _io_req_ready_T_1 = _T_79; // @[PixelRepeater.scala:46:76] wire _io_resp_bits_last_T; // @[PixelRepeater.scala:54:67] assign _io_resp_bits_last_T = _T_79; // @[PixelRepeater.scala:46:76, :54:67] wire _io_req_ready_T_2 = io_resp_ready_0 & _io_req_ready_T_1; // @[PixelRepeater.scala:28:7, :46:{50,76}] assign _io_req_ready_T_3 = _io_req_ready_T \| _io_req_ready_T_2; // @[PixelRepeater.scala:46:{21,32,50}] assign io_req_ready_0 = _io_req_ready_T_3; // @[PixelRepeater.scala:28:7, :46:32] wire [3:0] out_shift; // @[PixelRepeater.scala:48:25] wire [12:0] _out_shift_T = {5'h0, req_bits_pixel_repeats} * {8'h0, req_bits_len}; // @[PixelRepeater.scala:44:18, :49:41] assign out_shift = _out_shift_T[3:0]; // @[PixelRepeater.scala:48:25, :49:{15,41}] wire [15:0] lo_lo_lo = {req_bits_in_1, req_bits_in_0}; // @[PixelRepeater.scala:44:18, :51:38] wire [15:0] lo_lo_hi = {req_bits_in_3, req_bits_in_2}; // @[PixelRepeater.scala:44:18, :51:38] wire [31:0] lo_lo = {lo_lo_hi, lo_lo_lo}; // @[PixelRepeater.scala:51:38] wire [15:0] lo_hi_lo = {req_bits_in_5, req_bits_in_4}; // @[PixelRepeater.scala:44:18, :51:38] wire [15:0] lo_hi_hi = {req_bits_in_7, req_bits_in_6}; // @[PixelRepeater.scala:44:18, :51:38] wire [31:0] lo_hi = {lo_hi_hi, lo_hi_lo}; // @[PixelRepeater.scala:51:38] wire [63:0] lo = {lo_hi, lo_lo}; // @[PixelRepeater.scala:51:38] wire [15:0] hi_lo_lo = {req_bits_in_9, req_bits_in_8}; // @[PixelRepeater.scala:44:18, :51:38] wire [15:0] hi_lo_hi = {req_bits_in_11, req_bits_in_10}; // @[PixelRepeater.scala:44:18, :51:38] wire [31:0] hi_lo = {hi_lo_hi, hi_lo_lo}; // @[PixelRepeater.scala:51:38] wire [15:0] hi_hi_lo = {req_bits_in_13, req_bits_in_12}; // @[PixelRepeater.scala:44:18, :51:38] wire [15:0] hi_hi_hi = {req_bits_in_15, req_bits_in_14}; // @[PixelRepeater.scala:44:18, :51:38] wire [31:0] hi_hi = {hi_hi_hi, hi_hi_lo}; // @[PixelRepeater.scala:51:38] wire [63:0] hi = {hi_hi, hi_lo}; // @[PixelRepeater.scala:51:38] wire [382:0] _T_18 = {255'h0, hi, lo} << {376'h0, out_shift, 3'h0}; // @[PixelRepeater.scala:48:25, :51:{38,45}] assign io_resp_bits_out_0_0 = _T_18[7:0]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_1_0 = _T_18[15:8]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_2_0 = _T_18[23:16]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_3_0 = _T_18[31:24]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_4_0 = _T_18[39:32]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_5_0 = _T_18[47:40]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_6_0 = _T_18[55:48]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_7_0 = _T_18[63:56]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_8_0 = _T_18[71:64]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_9_0 = _T_18[79:72]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_10_0 = _T_18[87:80]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_11_0 = _T_18[95:88]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_12_0 = _T_18[103:96]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_13_0 = _T_18[111:104]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_14_0 = _T_18[119:112]; // @[PixelRepeater.scala:28:7, :51:{45,84}] assign io_resp_bits_out_15_0 = _T_18[127:120]; // @[PixelRepeater.scala:28:7, :51:{45,84}] wire [1:0] lo_lo_lo_1 = {req_bits_mask_1, req_bits_mask_0}; // @[PixelRepeater.scala:44:18, :52:41] wire [1:0] lo_lo_hi_1 = {req_bits_mask_3, req_bits_mask_2}; // @[PixelRepeater.scala:44:18, :52:41] wire [3:0] lo_lo_1 = {lo_lo_hi_1, lo_lo_lo_1}; // @[PixelRepeater.scala:52:41] wire [1:0] lo_hi_lo_1 = {req_bits_mask_5, req_bits_mask_4}; // @[PixelRepeater.scala:44:18, :52:41] wire [1:0] lo_hi_hi_1 = {req_bits_mask_7, req_bits_mask_6}; // @[PixelRepeater.scala:44:18, :52:41] wire [3:0] lo_hi_1 = {lo_hi_hi_1, lo_hi_lo_1}; // @[PixelRepeater.scala:52:41] wire [7:0] lo_1 = {lo_hi_1, lo_lo_1}; // @[PixelRepeater.scala:52:41] wire [1:0] hi_lo_lo_1 = {req_bits_mask_9, req_bits_mask_8}; // @[PixelRepeater.scala:44:18, :52:41] wire [1:0] hi_lo_hi_1 = {req_bits_mask_11, req_bits_mask_10}; // @[PixelRepeater.scala:44:18, :52:41] wire [3:0] hi_lo_1 = {hi_lo_hi_1, hi_lo_lo_1}; // @[PixelRepeater.scala:52:41] wire [1:0] hi_hi_lo_1 = {req_bits_mask_13, req_bits_mask_12}; // @[PixelRepeater.scala:44:18, :52:41] wire [1:0] hi_hi_hi_1 = {req_bits_mask_15, req_bits_mask_14}; // @[PixelRepeater.scala:44:18, :52:41] wire [3:0] hi_hi_1 = {hi_hi_hi_1, hi_hi_lo_1}; // @[PixelRepeater.scala:52:41] wire [7:0] hi_1 = {hi_hi_1, hi_lo_1}; // @[PixelRepeater.scala:52:41] wire [46:0] _T_53 = {31'h0, hi_1, lo_1} << out_shift; // @[PixelRepeater.scala:48:25, :52:{41,48}] assign io_resp_bits_mask_0_0 = _T_53[0]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_1_0 = _T_53[1]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_2_0 = _T_53[2]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_3_0 = _T_53[3]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_4_0 = _T_53[4]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_5_0 = _T_53[5]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_6_0 = _T_53[6]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_7_0 = _T_53[7]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_8_0 = _T_53[8]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_9_0 = _T_53[9]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_10_0 = _T_53[10]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_11_0 = _T_53[11]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_12_0 = _T_53[12]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_13_0 = _T_53[13]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_14_0 = _T_53[14]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign io_resp_bits_mask_15_0 = _T_53[15]; // @[PixelRepeater.scala:28:7, :52:{48,108}] assign _io_resp_bits_last_T_1 = req_bits_last & _io_resp_bits_last_T; // @[PixelRepeater.scala:44:18, :54:{40,67}] assign io_resp_bits_last_0 = _io_resp_bits_last_T_1; // @[PixelRepeater.scala:28:7, :54:40]
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_45 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<3>, vc_free : UInt<3>}} wire _in_flight_WIRE : UInt<1>[3] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) regreset in_flight : UInt<1>[3], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<3>(0h4)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_33 = and(_T_31, _T_32) node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_40 = and(_T_38, _T_39) node _T_41 = or(_T_12, _T_19) node _T_42 = or(_T_41, _T_26) node _T_43 = or(_T_42, _T_33) node _T_44 = or(_T_43, _T_40) node _T_45 = or(_T_5, _T_44) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_45, UInt<1>(0h1), "") : assert_1 node _T_49 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_50 = or(_T_49, UInt<1>(0h0)) node _T_51 = asUInt(reset) node _T_52 = eq(_T_51, UInt<1>(0h0)) when _T_52 : node _T_53 = eq(_T_50, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_50, UInt<1>(0h1), "") : assert_2 node _T_54 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_55 = or(_T_54, UInt<1>(0h0)) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3	module NoCMonitor_45( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h1; // @[Monitor.scala:21:46] wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 2'h2; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_255 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_255( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_24 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_233 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_234 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_235 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_236 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T	module AsyncResetSynchronizerShiftReg_w4_d3_i0_24( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_233 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_234 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_235 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_236 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_59 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<0>, vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `6` : UInt<1>[1], `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} inst route_buffer of Queue2_Flit_118 connect route_buffer.clock, clock connect route_buffer.reset, reset inst route_q of Queue2_RouteComputerResp_59 connect route_q.clock, clock connect route_q.reset, reset node _T = eq(UInt<1>(0h1), io.in.bits.egress_id) node _T_1 = eq(UInt<2>(0h3), io.in.bits.egress_id) node _T_2 = eq(UInt<3>(0h5), io.in.bits.egress_id) node _T_3 = eq(UInt<3>(0h7), io.in.bits.egress_id) node _T_4 = or(_T, _T_1) node _T_5 = or(_T_4, _T_2) node _T_6 = or(_T_5, _T_3) node _T_7 = eq(_T_6, UInt<1>(0h0)) node _T_8 = and(io.in.valid, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert connect route_buffer.io.enq.bits.head, io.in.bits.head connect route_buffer.io.enq.bits.tail, io.in.bits.tail connect route_buffer.io.enq.bits.flow.ingress_node, UInt<1>(0h0) connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<2>(0h3) connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1) node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<1>(0h1), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<2>(0h3), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<3>(0h5), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<3>(0h7), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<2>(0h2), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<3>(0h5), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<3>(0h6), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5) node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6) node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<3> connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10 connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<1>(0h1), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<2>(0h3), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<3>(0h5), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<3>(0h7), io.in.bits.egress_id) node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h1), UInt<1>(0h0)) node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5) node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6) node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7) wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1> connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10 connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE connect route_buffer.io.enq.bits.payload, io.in.bits.payload invalidate route_buffer.io.enq.bits.virt_channel_id connect io.router_req.bits.src_virt_id, UInt<1>(0h0) connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0)) node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T) node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest) node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2) connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3 node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready) node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head) node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0)) node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2) connect io.router_req.valid, _io_router_req_valid_T_3 node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0)) node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T) node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest) node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2) connect io.in.ready, _io_in_ready_T_3 node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid) connect route_q.io.enq.valid, _route_q_io_enq_valid_T connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0] connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1] connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2] connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3] connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4] connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5] connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6] connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7] connect route_q.io.enq.bits.vc_sel.`0`[8], io.router_resp.vc_sel.`0`[8] connect route_q.io.enq.bits.vc_sel.`0`[9], io.router_resp.vc_sel.`0`[9] connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0] connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0] connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0] connect route_q.io.enq.bits.vc_sel.`4`[0], io.router_resp.vc_sel.`4`[0] connect route_q.io.enq.bits.vc_sel.`5`[0], io.router_resp.vc_sel.`5`[0] connect route_q.io.enq.bits.vc_sel.`6`[0], io.router_resp.vc_sel.`6`[0] node _T_13 = and(io.in.ready, io.in.valid) node _T_14 = and(_T_13, io.in.bits.head) node _T_15 = and(_T_14, at_dest) when _T_15 : connect route_q.io.enq.valid, UInt<1>(0h1) connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[8], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`0`[9], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`4`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`5`[0], UInt<1>(0h0) connect route_q.io.enq.bits.vc_sel.`6`[0], UInt<1>(0h0) node _T_16 = eq(UInt<4>(0h8), io.in.bits.egress_id) when _T_16 : connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1) node _T_17 = eq(UInt<4>(0h9), io.in.bits.egress_id) when _T_17 : connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1) node _T_18 = eq(UInt<4>(0ha), io.in.bits.egress_id) when _T_18 : connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1) node _T_19 = eq(UInt<5>(0h14), io.in.bits.egress_id) when _T_19 : connect route_q.io.enq.bits.vc_sel.`4`[0], UInt<1>(0h1) node _T_20 = eq(UInt<5>(0h15), io.in.bits.egress_id) when _T_20 : connect route_q.io.enq.bits.vc_sel.`5`[0], UInt<1>(0h1) node _T_21 = eq(UInt<5>(0h16), io.in.bits.egress_id) when _T_21 : connect route_q.io.enq.bits.vc_sel.`6`[0], UInt<1>(0h1) node _T_22 = eq(route_q.io.enq.ready, UInt<1>(0h0)) node _T_23 = and(route_q.io.enq.valid, _T_22) node _T_24 = eq(_T_23, UInt<1>(0h0)) node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : node _T_27 = eq(_T_24, UInt<1>(0h0)) when _T_27 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1 assert(clock, _T_24, UInt<1>(0h1), "") : assert_1 inst vcalloc_buffer of Queue2_Flit_119 connect vcalloc_buffer.clock, clock connect vcalloc_buffer.reset, reset inst vcalloc_q of Queue1_VCAllocResp_59 connect vcalloc_q.clock, clock connect vcalloc_q.reset, reset connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0` connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1` connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2` connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3` connect io.vcalloc_req.bits.vc_sel.`4`, route_q.io.deq.bits.vc_sel.`4` connect io.vcalloc_req.bits.vc_sel.`5`, route_q.io.deq.bits.vc_sel.`5` connect io.vcalloc_req.bits.vc_sel.`6`, route_q.io.deq.bits.vc_sel.`6` connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0) node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T) node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1) node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3) node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4) connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5 node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid) node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head) node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready) node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T) node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1) node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3) node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4) node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0)) node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6) node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7) connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8 node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid) node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail) connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1 node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid) connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0] connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1] connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2] connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3] connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4] connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5] connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6] connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7] connect vcalloc_q.io.enq.bits.vc_sel.`0`[8], io.vcalloc_resp.vc_sel.`0`[8] connect vcalloc_q.io.enq.bits.vc_sel.`0`[9], io.vcalloc_resp.vc_sel.`0`[9] connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0] connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0] connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0] connect vcalloc_q.io.enq.bits.vc_sel.`4`[0], io.vcalloc_resp.vc_sel.`4`[0] connect vcalloc_q.io.enq.bits.vc_sel.`5`[0], io.vcalloc_resp.vc_sel.`5`[0] connect vcalloc_q.io.enq.bits.vc_sel.`6`[0], io.vcalloc_resp.vc_sel.`6`[0] node _T_28 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0)) node _T_29 = and(vcalloc_q.io.enq.valid, _T_28) node _T_30 = eq(_T_29, UInt<1>(0h0)) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2 assert(clock, _T_30, UInt<1>(0h1), "") : assert_2 connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0` connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1` connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2` connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3` connect io.salloc_req[0].bits.vc_sel.`4`, vcalloc_q.io.deq.bits.vc_sel.`4` connect io.salloc_req[0].bits.vc_sel.`5`, vcalloc_q.io.deq.bits.vc_sel.`5` connect io.salloc_req[0].bits.vc_sel.`6`, vcalloc_q.io.deq.bits.vc_sel.`6` connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node c_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node c_lo_hi = cat(c_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node c_lo = cat(c_lo_hi, c_lo_lo) node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node c_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node c_hi_hi = cat(c_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node c_hi = cat(c_hi_hi, c_hi_lo) node _c_T = cat(c_hi, c_lo) node c_lo_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0]) node c_lo_1 = cat(c_lo_hi_1, _c_T) node c_hi_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`4`[0], vcalloc_q.io.deq.bits.vc_sel.`3`[0]) node c_hi_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`6`[0], vcalloc_q.io.deq.bits.vc_sel.`5`[0]) node c_hi_1 = cat(c_hi_hi_1, c_hi_lo_1) node _c_T_1 = cat(c_hi_1, c_lo_1) node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node c_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node c_lo_hi_2 = cat(c_lo_hi_hi_1, io.out_credit_available.`0`[2]) node c_lo_2 = cat(c_lo_hi_2, c_lo_lo_1) node c_hi_lo_2 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node c_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node c_hi_hi_2 = cat(c_hi_hi_hi_1, io.out_credit_available.`0`[7]) node c_hi_2 = cat(c_hi_hi_2, c_hi_lo_2) node _c_T_2 = cat(c_hi_2, c_lo_2) node c_lo_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node c_lo_3 = cat(c_lo_hi_3, _c_T_2) node c_hi_lo_3 = cat(io.out_credit_available.`4`[0], io.out_credit_available.`3`[0]) node c_hi_hi_3 = cat(io.out_credit_available.`6`[0], io.out_credit_available.`5`[0]) node c_hi_3 = cat(c_hi_hi_3, c_hi_lo_3) node _c_T_3 = cat(c_hi_3, c_lo_3) node _c_T_4 = and(_c_T_1, _c_T_3) node c = neq(_c_T_4, UInt<1>(0h0)) node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid) node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c) node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0)) node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2) connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3 node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid) node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c) node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0)) node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2) connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3 node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T) connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1 reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}, clock connect io.out[0], out_bundle node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid) connect out_bundle.valid, _out_bundle_valid_T connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0) node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1]) node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4]) node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6]) node _out_channel_oh_T_6 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node _out_channel_oh_T_7 = or(_out_channel_oh_T_6, vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_channel_oh_0 = or(_out_channel_oh_T_7, vcalloc_q.io.deq.bits.vc_sel.`0`[9]) node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0]) node out_bundle_bits_out_virt_channel_lo_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3]) node out_bundle_bits_out_virt_channel_lo_hi = cat(out_bundle_bits_out_virt_channel_lo_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2]) node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo) node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[6], vcalloc_q.io.deq.bits.vc_sel.`0`[5]) node out_bundle_bits_out_virt_channel_hi_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[9], vcalloc_q.io.deq.bits.vc_sel.`0`[8]) node out_bundle_bits_out_virt_channel_hi_hi = cat(out_bundle_bits_out_virt_channel_hi_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[7]) node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo) node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo) node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 9, 8) node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 0) node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1) node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1) node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 7, 4) node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 0) node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2) node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2) node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 3, 2) node out_bundle_bits_out_virt_channel_lo_3 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 0) node _out_bundle_bits_out_virt_channel_T_5 = orr(out_bundle_bits_out_virt_channel_hi_3) node _out_bundle_bits_out_virt_channel_T_6 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_3) node _out_bundle_bits_out_virt_channel_T_7 = bits(_out_bundle_bits_out_virt_channel_T_6, 1, 1) node _out_bundle_bits_out_virt_channel_T_8 = cat(_out_bundle_bits_out_virt_channel_T_5, _out_bundle_bits_out_virt_channel_T_7) node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_8) node _out_bundle_bits_out_virt_channel_T_10 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_9) node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_10, UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_13 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_14 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_15 = mux(vcalloc_q.io.deq.bits.vc_sel.`4`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_16 = mux(vcalloc_q.io.deq.bits.vc_sel.`5`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_17 = mux(vcalloc_q.io.deq.bits.vc_sel.`6`[0], UInt<1>(0h0), UInt<1>(0h0)) node _out_bundle_bits_out_virt_channel_T_18 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_12) node _out_bundle_bits_out_virt_channel_T_19 = or(_out_bundle_bits_out_virt_channel_T_18, _out_bundle_bits_out_virt_channel_T_13) node _out_bundle_bits_out_virt_channel_T_20 = or(_out_bundle_bits_out_virt_channel_T_19, _out_bundle_bits_out_virt_channel_T_14) node _out_bundle_bits_out_virt_channel_T_21 = or(_out_bundle_bits_out_virt_channel_T_20, _out_bundle_bits_out_virt_channel_T_15) node _out_bundle_bits_out_virt_channel_T_22 = or(_out_bundle_bits_out_virt_channel_T_21, _out_bundle_bits_out_virt_channel_T_16) node _out_bundle_bits_out_virt_channel_T_23 = or(_out_bundle_bits_out_virt_channel_T_22, _out_bundle_bits_out_virt_channel_T_17) wire _out_bundle_bits_out_virt_channel_WIRE : UInt<4> connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_23 connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0)) node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T) connect io.debug.va_stall, _io_debug_va_stall_T_1 node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T) connect io.debug.sa_stall, _io_debug_sa_stall_T_1	module IngressUnit_59( // @[IngressUnit.scala:11:7] input clock, // @[IngressUnit.scala:11:7] input reset, // @[IngressUnit.scala:11:7] output [3:0] io_router_req_bits_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_router_req_bits_flow_egress_node_id, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_router_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14] output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_6_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_6_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_5_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_4_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14] input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14] input io_out_credit_available_6_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_5_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_4_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14] input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14] input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14] output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_6_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14] output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14] output io_out_0_valid, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14] output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14] output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14] output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14] output io_in_ready, // @[IngressUnit.scala:24:14] input io_in_valid, // @[IngressUnit.scala:24:14] input io_in_bits_head, // @[IngressUnit.scala:24:14] input io_in_bits_tail, // @[IngressUnit.scala:24:14] input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14] input [2:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14] ); wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_6_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_5_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_4_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25] wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25] wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30] wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30] wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30] wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30] wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30] wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30] wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23] wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23] wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28] wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28] wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28] wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28] wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28] wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 3'h1; // @[IngressUnit.scala:11:7, :30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 3'h3; // @[IngressUnit.scala:30:72] wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 3'h5; // @[IngressUnit.scala:30:72] wire [2:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_4} \| (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 3'h5 : 3'h0) \| ((&io_in_bits_egress_id) ? 3'h6 : 3'h0); // @[Mux.scala:30:73] wire [3:0] route_buffer_io_enq_bits_flow_egress_node = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_T_10}; // @[Mux.scala:30:73] wire [2:0] route_buffer_io_enq_bits_flow_egress_node_id = {2'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_4 \| _route_buffer_io_enq_bits_flow_egress_node_id_T_5 \| _route_buffer_io_enq_bits_flow_egress_node_id_T_6 \| (&io_in_bits_egress_id)}; // @[Mux.scala:30:73] wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & ~(\|_route_buffer_io_enq_bits_flow_egress_node_T_10); // @[Mux.scala:30:73] wire route_q_io_enq_valid = _GEN \| io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & (\|_route_buffer_io_enq_bits_flow_egress_node_T_10); // @[Mux.scala:30:73] wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}] wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid \| ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready \| ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready \| ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29] wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module TLAtomicAutomata_cbus : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_18 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in wire initval : { state : UInt<2>} connect initval.state, UInt<1>(0h0) wire _cam_s_WIRE : { state : UInt<2>}[1] connect _cam_s_WIRE[0], initval regreset cam_s : { state : UInt<2>}[1], clock, reset, _cam_s_WIRE reg cam_a : { bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, fifoId : UInt<1>, lut : UInt<4>}[1], clock reg cam_d : { data : UInt<64>, denied : UInt<1>, corrupt : UInt<1>}[1], clock node cam_free_0 = eq(cam_s[0].state, UInt<1>(0h0)) node cam_amo_0 = eq(cam_s[0].state, UInt<2>(0h2)) node _cam_abusy_T = eq(cam_s[0].state, UInt<2>(0h3)) node _cam_abusy_T_1 = eq(cam_s[0].state, UInt<2>(0h2)) node cam_abusy_0 = or(_cam_abusy_T, _cam_abusy_T_1) node cam_dmatch_0 = neq(cam_s[0].state, UInt<1>(0h0)) node _a_canLogical_T = leq(UInt<1>(0h0), nodeIn.a.bits.size) node _a_canLogical_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3)) node _a_canLogical_T_2 = and(_a_canLogical_T, _a_canLogical_T_1) node _a_canLogical_T_3 = or(UInt<1>(0h0), _a_canLogical_T_2) node _a_canLogical_T_4 = xor(nodeIn.a.bits.address, UInt<13>(0h1000)) node _a_canLogical_T_5 = cvt(_a_canLogical_T_4) node _a_canLogical_T_6 = and(_a_canLogical_T_5, asSInt(UInt<30>(0h1a311000))) node _a_canLogical_T_7 = asSInt(_a_canLogical_T_6) node _a_canLogical_T_8 = eq(_a_canLogical_T_7, asSInt(UInt<1>(0h0))) node _a_canLogical_T_9 = xor(nodeIn.a.bits.address, UInt<29>(0h10000000)) node _a_canLogical_T_10 = cvt(_a_canLogical_T_9) node _a_canLogical_T_11 = and(_a_canLogical_T_10, asSInt(UInt<30>(0h1a311000))) node _a_canLogical_T_12 = asSInt(_a_canLogical_T_11) node _a_canLogical_T_13 = eq(_a_canLogical_T_12, asSInt(UInt<1>(0h0))) node _a_canLogical_T_14 = or(_a_canLogical_T_8, _a_canLogical_T_13) node _a_canLogical_T_15 = and(_a_canLogical_T_3, _a_canLogical_T_14) node _a_canLogical_T_16 = or(UInt<1>(0h0), UInt<1>(0h0)) node _a_canLogical_T_17 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_canLogical_T_18 = cvt(_a_canLogical_T_17) node _a_canLogical_T_19 = and(_a_canLogical_T_18, asSInt(UInt<30>(0h1a311000))) node _a_canLogical_T_20 = asSInt(_a_canLogical_T_19) node _a_canLogical_T_21 = eq(_a_canLogical_T_20, asSInt(UInt<1>(0h0))) node _a_canLogical_T_22 = xor(nodeIn.a.bits.address, UInt<17>(0h10000)) node _a_canLogical_T_23 = cvt(_a_canLogical_T_22) node _a_canLogical_T_24 = and(_a_canLogical_T_23, asSInt(UInt<30>(0h1a310000))) node _a_canLogical_T_25 = asSInt(_a_canLogical_T_24) node _a_canLogical_T_26 = eq(_a_canLogical_T_25, asSInt(UInt<1>(0h0))) node _a_canLogical_T_27 = xor(nodeIn.a.bits.address, UInt<21>(0h100000)) node _a_canLogical_T_28 = cvt(_a_canLogical_T_27) node _a_canLogical_T_29 = and(_a_canLogical_T_28, asSInt(UInt<30>(0h1a301000))) node _a_canLogical_T_30 = asSInt(_a_canLogical_T_29) node _a_canLogical_T_31 = eq(_a_canLogical_T_30, asSInt(UInt<1>(0h0))) node _a_canLogical_T_32 = xor(nodeIn.a.bits.address, UInt<22>(0h300000)) node _a_canLogical_T_33 = cvt(_a_canLogical_T_32) node _a_canLogical_T_34 = and(_a_canLogical_T_33, asSInt(UInt<30>(0h1a310000))) node _a_canLogical_T_35 = asSInt(_a_canLogical_T_34) node _a_canLogical_T_36 = eq(_a_canLogical_T_35, asSInt(UInt<1>(0h0))) node _a_canLogical_T_37 = xor(nodeIn.a.bits.address, UInt<26>(0h2000000)) node _a_canLogical_T_38 = cvt(_a_canLogical_T_37) node _a_canLogical_T_39 = and(_a_canLogical_T_38, asSInt(UInt<30>(0h1a310000))) node _a_canLogical_T_40 = asSInt(_a_canLogical_T_39) node _a_canLogical_T_41 = eq(_a_canLogical_T_40, asSInt(UInt<1>(0h0))) node _a_canLogical_T_42 = xor(nodeIn.a.bits.address, UInt<26>(0h2010000)) node _a_canLogical_T_43 = cvt(_a_canLogical_T_42) node _a_canLogical_T_44 = and(_a_canLogical_T_43, asSInt(UInt<30>(0h1a311000))) node _a_canLogical_T_45 = asSInt(_a_canLogical_T_44) node _a_canLogical_T_46 = eq(_a_canLogical_T_45, asSInt(UInt<1>(0h0))) node _a_canLogical_T_47 = xor(nodeIn.a.bits.address, UInt<28>(0h8000000)) node _a_canLogical_T_48 = cvt(_a_canLogical_T_47) node _a_canLogical_T_49 = and(_a_canLogical_T_48, asSInt(UInt<30>(0h18000000))) node _a_canLogical_T_50 = asSInt(_a_canLogical_T_49) node _a_canLogical_T_51 = eq(_a_canLogical_T_50, asSInt(UInt<1>(0h0))) node _a_canLogical_T_52 = or(_a_canLogical_T_21, _a_canLogical_T_26) node _a_canLogical_T_53 = or(_a_canLogical_T_52, _a_canLogical_T_31) node _a_canLogical_T_54 = or(_a_canLogical_T_53, _a_canLogical_T_36) node _a_canLogical_T_55 = or(_a_canLogical_T_54, _a_canLogical_T_41) node _a_canLogical_T_56 = or(_a_canLogical_T_55, _a_canLogical_T_46) node _a_canLogical_T_57 = or(_a_canLogical_T_56, _a_canLogical_T_51) node _a_canLogical_T_58 = and(_a_canLogical_T_16, _a_canLogical_T_57) node _a_canLogical_T_59 = leq(UInt<2>(0h2), nodeIn.a.bits.size) node _a_canLogical_T_60 = leq(nodeIn.a.bits.size, UInt<2>(0h3)) node _a_canLogical_T_61 = and(_a_canLogical_T_59, _a_canLogical_T_60) node _a_canLogical_T_62 = or(UInt<1>(0h0), _a_canLogical_T_61) node _a_canLogical_T_63 = xor(nodeIn.a.bits.address, UInt<22>(0h200000)) node _a_canLogical_T_64 = cvt(_a_canLogical_T_63) node _a_canLogical_T_65 = and(_a_canLogical_T_64, asSInt(UInt<30>(0h1a311000))) node _a_canLogical_T_66 = asSInt(_a_canLogical_T_65) node _a_canLogical_T_67 = eq(_a_canLogical_T_66, asSInt(UInt<1>(0h0))) node _a_canLogical_T_68 = and(_a_canLogical_T_62, _a_canLogical_T_67) node _a_canLogical_T_69 = or(UInt<1>(0h0), _a_canLogical_T_15) node _a_canLogical_T_70 = or(_a_canLogical_T_69, _a_canLogical_T_58) node _a_canLogical_T_71 = or(_a_canLogical_T_70, _a_canLogical_T_68) node a_canLogical = and(UInt<1>(0h1), _a_canLogical_T_71) node _a_canArithmetic_T = leq(UInt<1>(0h0), nodeIn.a.bits.size) node _a_canArithmetic_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3)) node _a_canArithmetic_T_2 = and(_a_canArithmetic_T, _a_canArithmetic_T_1) node _a_canArithmetic_T_3 = or(UInt<1>(0h0), _a_canArithmetic_T_2) node _a_canArithmetic_T_4 = xor(nodeIn.a.bits.address, UInt<13>(0h1000)) node _a_canArithmetic_T_5 = cvt(_a_canArithmetic_T_4) node _a_canArithmetic_T_6 = and(_a_canArithmetic_T_5, asSInt(UInt<30>(0h1a311000))) node _a_canArithmetic_T_7 = asSInt(_a_canArithmetic_T_6) node _a_canArithmetic_T_8 = eq(_a_canArithmetic_T_7, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_9 = xor(nodeIn.a.bits.address, UInt<29>(0h10000000)) node _a_canArithmetic_T_10 = cvt(_a_canArithmetic_T_9) node _a_canArithmetic_T_11 = and(_a_canArithmetic_T_10, asSInt(UInt<30>(0h1a311000))) node _a_canArithmetic_T_12 = asSInt(_a_canArithmetic_T_11) node _a_canArithmetic_T_13 = eq(_a_canArithmetic_T_12, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_14 = or(_a_canArithmetic_T_8, _a_canArithmetic_T_13) node _a_canArithmetic_T_15 = and(_a_canArithmetic_T_3, _a_canArithmetic_T_14) node _a_canArithmetic_T_16 = or(UInt<1>(0h0), UInt<1>(0h0)) node _a_canArithmetic_T_17 = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_canArithmetic_T_18 = cvt(_a_canArithmetic_T_17) node _a_canArithmetic_T_19 = and(_a_canArithmetic_T_18, asSInt(UInt<30>(0h1a311000))) node _a_canArithmetic_T_20 = asSInt(_a_canArithmetic_T_19) node _a_canArithmetic_T_21 = eq(_a_canArithmetic_T_20, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_22 = xor(nodeIn.a.bits.address, UInt<17>(0h10000)) node _a_canArithmetic_T_23 = cvt(_a_canArithmetic_T_22) node _a_canArithmetic_T_24 = and(_a_canArithmetic_T_23, asSInt(UInt<30>(0h1a310000))) node _a_canArithmetic_T_25 = asSInt(_a_canArithmetic_T_24) node _a_canArithmetic_T_26 = eq(_a_canArithmetic_T_25, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_27 = xor(nodeIn.a.bits.address, UInt<21>(0h100000)) node _a_canArithmetic_T_28 = cvt(_a_canArithmetic_T_27) node _a_canArithmetic_T_29 = and(_a_canArithmetic_T_28, asSInt(UInt<30>(0h1a301000))) node _a_canArithmetic_T_30 = asSInt(_a_canArithmetic_T_29) node _a_canArithmetic_T_31 = eq(_a_canArithmetic_T_30, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_32 = xor(nodeIn.a.bits.address, UInt<22>(0h300000)) node _a_canArithmetic_T_33 = cvt(_a_canArithmetic_T_32) node _a_canArithmetic_T_34 = and(_a_canArithmetic_T_33, asSInt(UInt<30>(0h1a310000))) node _a_canArithmetic_T_35 = asSInt(_a_canArithmetic_T_34) node _a_canArithmetic_T_36 = eq(_a_canArithmetic_T_35, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_37 = xor(nodeIn.a.bits.address, UInt<26>(0h2000000)) node _a_canArithmetic_T_38 = cvt(_a_canArithmetic_T_37) node _a_canArithmetic_T_39 = and(_a_canArithmetic_T_38, asSInt(UInt<30>(0h1a310000))) node _a_canArithmetic_T_40 = asSInt(_a_canArithmetic_T_39) node _a_canArithmetic_T_41 = eq(_a_canArithmetic_T_40, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_42 = xor(nodeIn.a.bits.address, UInt<26>(0h2010000)) node _a_canArithmetic_T_43 = cvt(_a_canArithmetic_T_42) node _a_canArithmetic_T_44 = and(_a_canArithmetic_T_43, asSInt(UInt<30>(0h1a311000))) node _a_canArithmetic_T_45 = asSInt(_a_canArithmetic_T_44) node _a_canArithmetic_T_46 = eq(_a_canArithmetic_T_45, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_47 = xor(nodeIn.a.bits.address, UInt<28>(0h8000000)) node _a_canArithmetic_T_48 = cvt(_a_canArithmetic_T_47) node _a_canArithmetic_T_49 = and(_a_canArithmetic_T_48, asSInt(UInt<30>(0h18000000))) node _a_canArithmetic_T_50 = asSInt(_a_canArithmetic_T_49) node _a_canArithmetic_T_51 = eq(_a_canArithmetic_T_50, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_52 = or(_a_canArithmetic_T_21, _a_canArithmetic_T_26) node _a_canArithmetic_T_53 = or(_a_canArithmetic_T_52, _a_canArithmetic_T_31) node _a_canArithmetic_T_54 = or(_a_canArithmetic_T_53, _a_canArithmetic_T_36) node _a_canArithmetic_T_55 = or(_a_canArithmetic_T_54, _a_canArithmetic_T_41) node _a_canArithmetic_T_56 = or(_a_canArithmetic_T_55, _a_canArithmetic_T_46) node _a_canArithmetic_T_57 = or(_a_canArithmetic_T_56, _a_canArithmetic_T_51) node _a_canArithmetic_T_58 = and(_a_canArithmetic_T_16, _a_canArithmetic_T_57) node _a_canArithmetic_T_59 = leq(UInt<2>(0h2), nodeIn.a.bits.size) node _a_canArithmetic_T_60 = leq(nodeIn.a.bits.size, UInt<2>(0h3)) node _a_canArithmetic_T_61 = and(_a_canArithmetic_T_59, _a_canArithmetic_T_60) node _a_canArithmetic_T_62 = or(UInt<1>(0h0), _a_canArithmetic_T_61) node _a_canArithmetic_T_63 = xor(nodeIn.a.bits.address, UInt<22>(0h200000)) node _a_canArithmetic_T_64 = cvt(_a_canArithmetic_T_63) node _a_canArithmetic_T_65 = and(_a_canArithmetic_T_64, asSInt(UInt<30>(0h1a311000))) node _a_canArithmetic_T_66 = asSInt(_a_canArithmetic_T_65) node _a_canArithmetic_T_67 = eq(_a_canArithmetic_T_66, asSInt(UInt<1>(0h0))) node _a_canArithmetic_T_68 = and(_a_canArithmetic_T_62, _a_canArithmetic_T_67) node _a_canArithmetic_T_69 = or(UInt<1>(0h0), _a_canArithmetic_T_15) node _a_canArithmetic_T_70 = or(_a_canArithmetic_T_69, _a_canArithmetic_T_58) node _a_canArithmetic_T_71 = or(_a_canArithmetic_T_70, _a_canArithmetic_T_68) node a_canArithmetic = and(UInt<1>(0h1), _a_canArithmetic_T_71) node a_isLogical = eq(nodeIn.a.bits.opcode, UInt<2>(0h3)) node a_isArithmetic = eq(nodeIn.a.bits.opcode, UInt<2>(0h2)) node _a_isSupported_T = mux(a_isArithmetic, a_canArithmetic, UInt<1>(0h1)) node a_isSupported = mux(a_isLogical, a_canLogical, _a_isSupported_T) node _a_cam_por_put_T = or(UInt<1>(0h0), cam_amo_0) node _a_cam_sel_put_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node a_cam_sel_put_0 = and(cam_amo_0, _a_cam_sel_put_T) node _a_fifoId_T = xor(nodeIn.a.bits.address, UInt<1>(0h0)) node _a_fifoId_T_1 = cvt(_a_fifoId_T) node _a_fifoId_T_2 = and(_a_fifoId_T_1, asSInt(UInt<1>(0h0))) node _a_fifoId_T_3 = asSInt(_a_fifoId_T_2) node _a_fifoId_T_4 = eq(_a_fifoId_T_3, asSInt(UInt<1>(0h0))) node _a_cam_busy_T = eq(cam_a[0].fifoId, UInt<1>(0h0)) node a_cam_busy = and(cam_abusy_0, _a_cam_busy_T) node _a_cam_por_free_T = or(UInt<1>(0h0), cam_free_0) node _a_cam_sel_free_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node a_cam_sel_free_0 = and(cam_free_0, _a_cam_sel_free_T) node _indexes_T = bits(cam_a[0].bits.data, 0, 0) node _indexes_T_1 = bits(cam_d[0].data, 0, 0) node indexes_0 = cat(_indexes_T, _indexes_T_1) node _indexes_T_2 = bits(cam_a[0].bits.data, 1, 1) node _indexes_T_3 = bits(cam_d[0].data, 1, 1) node indexes_1 = cat(_indexes_T_2, _indexes_T_3) node _indexes_T_4 = bits(cam_a[0].bits.data, 2, 2) node _indexes_T_5 = bits(cam_d[0].data, 2, 2) node indexes_2 = cat(_indexes_T_4, _indexes_T_5) node _indexes_T_6 = bits(cam_a[0].bits.data, 3, 3) node _indexes_T_7 = bits(cam_d[0].data, 3, 3) node indexes_3 = cat(_indexes_T_6, _indexes_T_7) node _indexes_T_8 = bits(cam_a[0].bits.data, 4, 4) node _indexes_T_9 = bits(cam_d[0].data, 4, 4) node indexes_4 = cat(_indexes_T_8, _indexes_T_9) node _indexes_T_10 = bits(cam_a[0].bits.data, 5, 5) node _indexes_T_11 = bits(cam_d[0].data, 5, 5) node indexes_5 = cat(_indexes_T_10, _indexes_T_11) node _indexes_T_12 = bits(cam_a[0].bits.data, 6, 6) node _indexes_T_13 = bits(cam_d[0].data, 6, 6) node indexes_6 = cat(_indexes_T_12, _indexes_T_13) node _indexes_T_14 = bits(cam_a[0].bits.data, 7, 7) node _indexes_T_15 = bits(cam_d[0].data, 7, 7) node indexes_7 = cat(_indexes_T_14, _indexes_T_15) node _indexes_T_16 = bits(cam_a[0].bits.data, 8, 8) node _indexes_T_17 = bits(cam_d[0].data, 8, 8) node indexes_8 = cat(_indexes_T_16, _indexes_T_17) node _indexes_T_18 = bits(cam_a[0].bits.data, 9, 9) node _indexes_T_19 = bits(cam_d[0].data, 9, 9) node indexes_9 = cat(_indexes_T_18, _indexes_T_19) node _indexes_T_20 = bits(cam_a[0].bits.data, 10, 10) node _indexes_T_21 = bits(cam_d[0].data, 10, 10) node indexes_10 = cat(_indexes_T_20, _indexes_T_21) node _indexes_T_22 = bits(cam_a[0].bits.data, 11, 11) node _indexes_T_23 = bits(cam_d[0].data, 11, 11) node indexes_11 = cat(_indexes_T_22, _indexes_T_23) node _indexes_T_24 = bits(cam_a[0].bits.data, 12, 12) node _indexes_T_25 = bits(cam_d[0].data, 12, 12) node indexes_12 = cat(_indexes_T_24, _indexes_T_25) node _indexes_T_26 = bits(cam_a[0].bits.data, 13, 13) node _indexes_T_27 = bits(cam_d[0].data, 13, 13) node indexes_13 = cat(_indexes_T_26, _indexes_T_27) node _indexes_T_28 = bits(cam_a[0].bits.data, 14, 14) node _indexes_T_29 = bits(cam_d[0].data, 14, 14) node indexes_14 = cat(_indexes_T_28, _indexes_T_29) node _indexes_T_30 = bits(cam_a[0].bits.data, 15, 15) node _indexes_T_31 = bits(cam_d[0].data, 15, 15) node indexes_15 = cat(_indexes_T_30, _indexes_T_31) node _indexes_T_32 = bits(cam_a[0].bits.data, 16, 16) node _indexes_T_33 = bits(cam_d[0].data, 16, 16) node indexes_16 = cat(_indexes_T_32, _indexes_T_33) node _indexes_T_34 = bits(cam_a[0].bits.data, 17, 17) node _indexes_T_35 = bits(cam_d[0].data, 17, 17) node indexes_17 = cat(_indexes_T_34, _indexes_T_35) node _indexes_T_36 = bits(cam_a[0].bits.data, 18, 18) node _indexes_T_37 = bits(cam_d[0].data, 18, 18) node indexes_18 = cat(_indexes_T_36, _indexes_T_37) node _indexes_T_38 = bits(cam_a[0].bits.data, 19, 19) node _indexes_T_39 = bits(cam_d[0].data, 19, 19) node indexes_19 = cat(_indexes_T_38, _indexes_T_39) node _indexes_T_40 = bits(cam_a[0].bits.data, 20, 20) node _indexes_T_41 = bits(cam_d[0].data, 20, 20) node indexes_20 = cat(_indexes_T_40, _indexes_T_41) node _indexes_T_42 = bits(cam_a[0].bits.data, 21, 21) node _indexes_T_43 = bits(cam_d[0].data, 21, 21) node indexes_21 = cat(_indexes_T_42, _indexes_T_43) node _indexes_T_44 = bits(cam_a[0].bits.data, 22, 22) node _indexes_T_45 = bits(cam_d[0].data, 22, 22) node indexes_22 = cat(_indexes_T_44, _indexes_T_45) node _indexes_T_46 = bits(cam_a[0].bits.data, 23, 23) node _indexes_T_47 = bits(cam_d[0].data, 23, 23) node indexes_23 = cat(_indexes_T_46, _indexes_T_47) node _indexes_T_48 = bits(cam_a[0].bits.data, 24, 24) node _indexes_T_49 = bits(cam_d[0].data, 24, 24) node indexes_24 = cat(_indexes_T_48, _indexes_T_49) node _indexes_T_50 = bits(cam_a[0].bits.data, 25, 25) node _indexes_T_51 = bits(cam_d[0].data, 25, 25) node indexes_25 = cat(_indexes_T_50, _indexes_T_51) node _indexes_T_52 = bits(cam_a[0].bits.data, 26, 26) node _indexes_T_53 = bits(cam_d[0].data, 26, 26) node indexes_26 = cat(_indexes_T_52, _indexes_T_53) node _indexes_T_54 = bits(cam_a[0].bits.data, 27, 27) node _indexes_T_55 = bits(cam_d[0].data, 27, 27) node indexes_27 = cat(_indexes_T_54, _indexes_T_55) node _indexes_T_56 = bits(cam_a[0].bits.data, 28, 28) node _indexes_T_57 = bits(cam_d[0].data, 28, 28) node indexes_28 = cat(_indexes_T_56, _indexes_T_57) node _indexes_T_58 = bits(cam_a[0].bits.data, 29, 29) node _indexes_T_59 = bits(cam_d[0].data, 29, 29) node indexes_29 = cat(_indexes_T_58, _indexes_T_59) node _indexes_T_60 = bits(cam_a[0].bits.data, 30, 30) node _indexes_T_61 = bits(cam_d[0].data, 30, 30) node indexes_30 = cat(_indexes_T_60, _indexes_T_61) node _indexes_T_62 = bits(cam_a[0].bits.data, 31, 31) node _indexes_T_63 = bits(cam_d[0].data, 31, 31) node indexes_31 = cat(_indexes_T_62, _indexes_T_63) node _indexes_T_64 = bits(cam_a[0].bits.data, 32, 32) node _indexes_T_65 = bits(cam_d[0].data, 32, 32) node indexes_32 = cat(_indexes_T_64, _indexes_T_65) node _indexes_T_66 = bits(cam_a[0].bits.data, 33, 33) node _indexes_T_67 = bits(cam_d[0].data, 33, 33) node indexes_33 = cat(_indexes_T_66, _indexes_T_67) node _indexes_T_68 = bits(cam_a[0].bits.data, 34, 34) node _indexes_T_69 = bits(cam_d[0].data, 34, 34) node indexes_34 = cat(_indexes_T_68, _indexes_T_69) node _indexes_T_70 = bits(cam_a[0].bits.data, 35, 35) node _indexes_T_71 = bits(cam_d[0].data, 35, 35) node indexes_35 = cat(_indexes_T_70, _indexes_T_71) node _indexes_T_72 = bits(cam_a[0].bits.data, 36, 36) node _indexes_T_73 = bits(cam_d[0].data, 36, 36) node indexes_36 = cat(_indexes_T_72, _indexes_T_73) node _indexes_T_74 = bits(cam_a[0].bits.data, 37, 37) node _indexes_T_75 = bits(cam_d[0].data, 37, 37) node indexes_37 = cat(_indexes_T_74, _indexes_T_75) node _indexes_T_76 = bits(cam_a[0].bits.data, 38, 38) node _indexes_T_77 = bits(cam_d[0].data, 38, 38) node indexes_38 = cat(_indexes_T_76, _indexes_T_77) node _indexes_T_78 = bits(cam_a[0].bits.data, 39, 39) node _indexes_T_79 = bits(cam_d[0].data, 39, 39) node indexes_39 = cat(_indexes_T_78, _indexes_T_79) node _indexes_T_80 = bits(cam_a[0].bits.data, 40, 40) node _indexes_T_81 = bits(cam_d[0].data, 40, 40) node indexes_40 = cat(_indexes_T_80, _indexes_T_81) node _indexes_T_82 = bits(cam_a[0].bits.data, 41, 41) node _indexes_T_83 = bits(cam_d[0].data, 41, 41) node indexes_41 = cat(_indexes_T_82, _indexes_T_83) node _indexes_T_84 = bits(cam_a[0].bits.data, 42, 42) node _indexes_T_85 = bits(cam_d[0].data, 42, 42) node indexes_42 = cat(_indexes_T_84, _indexes_T_85) node _indexes_T_86 = bits(cam_a[0].bits.data, 43, 43) node _indexes_T_87 = bits(cam_d[0].data, 43, 43) node indexes_43 = cat(_indexes_T_86, _indexes_T_87) node _indexes_T_88 = bits(cam_a[0].bits.data, 44, 44) node _indexes_T_89 = bits(cam_d[0].data, 44, 44) node indexes_44 = cat(_indexes_T_88, _indexes_T_89) node _indexes_T_90 = bits(cam_a[0].bits.data, 45, 45) node _indexes_T_91 = bits(cam_d[0].data, 45, 45) node indexes_45 = cat(_indexes_T_90, _indexes_T_91) node _indexes_T_92 = bits(cam_a[0].bits.data, 46, 46) node _indexes_T_93 = bits(cam_d[0].data, 46, 46) node indexes_46 = cat(_indexes_T_92, _indexes_T_93) node _indexes_T_94 = bits(cam_a[0].bits.data, 47, 47) node _indexes_T_95 = bits(cam_d[0].data, 47, 47) node indexes_47 = cat(_indexes_T_94, _indexes_T_95) node _indexes_T_96 = bits(cam_a[0].bits.data, 48, 48) node _indexes_T_97 = bits(cam_d[0].data, 48, 48) node indexes_48 = cat(_indexes_T_96, _indexes_T_97) node _indexes_T_98 = bits(cam_a[0].bits.data, 49, 49) node _indexes_T_99 = bits(cam_d[0].data, 49, 49) node indexes_49 = cat(_indexes_T_98, _indexes_T_99) node _indexes_T_100 = bits(cam_a[0].bits.data, 50, 50) node _indexes_T_101 = bits(cam_d[0].data, 50, 50) node indexes_50 = cat(_indexes_T_100, _indexes_T_101) node _indexes_T_102 = bits(cam_a[0].bits.data, 51, 51) node _indexes_T_103 = bits(cam_d[0].data, 51, 51) node indexes_51 = cat(_indexes_T_102, _indexes_T_103) node _indexes_T_104 = bits(cam_a[0].bits.data, 52, 52) node _indexes_T_105 = bits(cam_d[0].data, 52, 52) node indexes_52 = cat(_indexes_T_104, _indexes_T_105) node _indexes_T_106 = bits(cam_a[0].bits.data, 53, 53) node _indexes_T_107 = bits(cam_d[0].data, 53, 53) node indexes_53 = cat(_indexes_T_106, _indexes_T_107) node _indexes_T_108 = bits(cam_a[0].bits.data, 54, 54) node _indexes_T_109 = bits(cam_d[0].data, 54, 54) node indexes_54 = cat(_indexes_T_108, _indexes_T_109) node _indexes_T_110 = bits(cam_a[0].bits.data, 55, 55) node _indexes_T_111 = bits(cam_d[0].data, 55, 55) node indexes_55 = cat(_indexes_T_110, _indexes_T_111) node _indexes_T_112 = bits(cam_a[0].bits.data, 56, 56) node _indexes_T_113 = bits(cam_d[0].data, 56, 56) node indexes_56 = cat(_indexes_T_112, _indexes_T_113) node _indexes_T_114 = bits(cam_a[0].bits.data, 57, 57) node _indexes_T_115 = bits(cam_d[0].data, 57, 57) node indexes_57 = cat(_indexes_T_114, _indexes_T_115) node _indexes_T_116 = bits(cam_a[0].bits.data, 58, 58) node _indexes_T_117 = bits(cam_d[0].data, 58, 58) node indexes_58 = cat(_indexes_T_116, _indexes_T_117) node _indexes_T_118 = bits(cam_a[0].bits.data, 59, 59) node _indexes_T_119 = bits(cam_d[0].data, 59, 59) node indexes_59 = cat(_indexes_T_118, _indexes_T_119) node _indexes_T_120 = bits(cam_a[0].bits.data, 60, 60) node _indexes_T_121 = bits(cam_d[0].data, 60, 60) node indexes_60 = cat(_indexes_T_120, _indexes_T_121) node _indexes_T_122 = bits(cam_a[0].bits.data, 61, 61) node _indexes_T_123 = bits(cam_d[0].data, 61, 61) node indexes_61 = cat(_indexes_T_122, _indexes_T_123) node _indexes_T_124 = bits(cam_a[0].bits.data, 62, 62) node _indexes_T_125 = bits(cam_d[0].data, 62, 62) node indexes_62 = cat(_indexes_T_124, _indexes_T_125) node _indexes_T_126 = bits(cam_a[0].bits.data, 63, 63) node _indexes_T_127 = bits(cam_d[0].data, 63, 63) node indexes_63 = cat(_indexes_T_126, _indexes_T_127) node _logic_out_T = dshr(cam_a[0].lut, indexes_0) node _logic_out_T_1 = bits(_logic_out_T, 0, 0) node _logic_out_T_2 = dshr(cam_a[0].lut, indexes_1) node _logic_out_T_3 = bits(_logic_out_T_2, 0, 0) node _logic_out_T_4 = dshr(cam_a[0].lut, indexes_2) node _logic_out_T_5 = bits(_logic_out_T_4, 0, 0) node _logic_out_T_6 = dshr(cam_a[0].lut, indexes_3) node _logic_out_T_7 = bits(_logic_out_T_6, 0, 0) node _logic_out_T_8 = dshr(cam_a[0].lut, indexes_4) node _logic_out_T_9 = bits(_logic_out_T_8, 0, 0) node _logic_out_T_10 = dshr(cam_a[0].lut, indexes_5) node _logic_out_T_11 = bits(_logic_out_T_10, 0, 0) node _logic_out_T_12 = dshr(cam_a[0].lut, indexes_6) node _logic_out_T_13 = bits(_logic_out_T_12, 0, 0) node _logic_out_T_14 = dshr(cam_a[0].lut, indexes_7) node _logic_out_T_15 = bits(_logic_out_T_14, 0, 0) node _logic_out_T_16 = dshr(cam_a[0].lut, indexes_8) node _logic_out_T_17 = bits(_logic_out_T_16, 0, 0) node _logic_out_T_18 = dshr(cam_a[0].lut, indexes_9) node _logic_out_T_19 = bits(_logic_out_T_18, 0, 0) node _logic_out_T_20 = dshr(cam_a[0].lut, indexes_10) node _logic_out_T_21 = bits(_logic_out_T_20, 0, 0) node _logic_out_T_22 = dshr(cam_a[0].lut, indexes_11) node _logic_out_T_23 = bits(_logic_out_T_22, 0, 0) node _logic_out_T_24 = dshr(cam_a[0].lut, indexes_12) node _logic_out_T_25 = bits(_logic_out_T_24, 0, 0) node _logic_out_T_26 = dshr(cam_a[0].lut, indexes_13) node _logic_out_T_27 = bits(_logic_out_T_26, 0, 0) node _logic_out_T_28 = dshr(cam_a[0].lut, indexes_14) node _logic_out_T_29 = bits(_logic_out_T_28, 0, 0) node _logic_out_T_30 = dshr(cam_a[0].lut, indexes_15) node _logic_out_T_31 = bits(_logic_out_T_30, 0, 0) node _logic_out_T_32 = dshr(cam_a[0].lut, indexes_16) node _logic_out_T_33 = bits(_logic_out_T_32, 0, 0) node _logic_out_T_34 = dshr(cam_a[0].lut, indexes_17) node _logic_out_T_35 = bits(_logic_out_T_34, 0, 0) node _logic_out_T_36 = dshr(cam_a[0].lut, indexes_18) node _logic_out_T_37 = bits(_logic_out_T_36, 0, 0) node _logic_out_T_38 = dshr(cam_a[0].lut, indexes_19) node _logic_out_T_39 = bits(_logic_out_T_38, 0, 0) node _logic_out_T_40 = dshr(cam_a[0].lut, indexes_20) node _logic_out_T_41 = bits(_logic_out_T_40, 0, 0) node _logic_out_T_42 = dshr(cam_a[0].lut, indexes_21) node _logic_out_T_43 = bits(_logic_out_T_42, 0, 0) node _logic_out_T_44 = dshr(cam_a[0].lut, indexes_22) node _logic_out_T_45 = bits(_logic_out_T_44, 0, 0) node _logic_out_T_46 = dshr(cam_a[0].lut, indexes_23) node _logic_out_T_47 = bits(_logic_out_T_46, 0, 0) node _logic_out_T_48 = dshr(cam_a[0].lut, indexes_24) node _logic_out_T_49 = bits(_logic_out_T_48, 0, 0) node _logic_out_T_50 = dshr(cam_a[0].lut, indexes_25) node _logic_out_T_51 = bits(_logic_out_T_50, 0, 0) node _logic_out_T_52 = dshr(cam_a[0].lut, indexes_26) node _logic_out_T_53 = bits(_logic_out_T_52, 0, 0) node _logic_out_T_54 = dshr(cam_a[0].lut, indexes_27) node _logic_out_T_55 = bits(_logic_out_T_54, 0, 0) node _logic_out_T_56 = dshr(cam_a[0].lut, indexes_28) node _logic_out_T_57 = bits(_logic_out_T_56, 0, 0) node _logic_out_T_58 = dshr(cam_a[0].lut, indexes_29) node _logic_out_T_59 = bits(_logic_out_T_58, 0, 0) node _logic_out_T_60 = dshr(cam_a[0].lut, indexes_30) node _logic_out_T_61 = bits(_logic_out_T_60, 0, 0) node _logic_out_T_62 = dshr(cam_a[0].lut, indexes_31) node _logic_out_T_63 = bits(_logic_out_T_62, 0, 0) node _logic_out_T_64 = dshr(cam_a[0].lut, indexes_32) node _logic_out_T_65 = bits(_logic_out_T_64, 0, 0) node _logic_out_T_66 = dshr(cam_a[0].lut, indexes_33) node _logic_out_T_67 = bits(_logic_out_T_66, 0, 0) node _logic_out_T_68 = dshr(cam_a[0].lut, indexes_34) node _logic_out_T_69 = bits(_logic_out_T_68, 0, 0) node _logic_out_T_70 = dshr(cam_a[0].lut, indexes_35) node _logic_out_T_71 = bits(_logic_out_T_70, 0, 0) node _logic_out_T_72 = dshr(cam_a[0].lut, indexes_36) node _logic_out_T_73 = bits(_logic_out_T_72, 0, 0) node _logic_out_T_74 = dshr(cam_a[0].lut, indexes_37) node _logic_out_T_75 = bits(_logic_out_T_74, 0, 0) node _logic_out_T_76 = dshr(cam_a[0].lut, indexes_38) node _logic_out_T_77 = bits(_logic_out_T_76, 0, 0) node _logic_out_T_78 = dshr(cam_a[0].lut, indexes_39) node _logic_out_T_79 = bits(_logic_out_T_78, 0, 0) node _logic_out_T_80 = dshr(cam_a[0].lut, indexes_40) node _logic_out_T_81 = bits(_logic_out_T_80, 0, 0) node _logic_out_T_82 = dshr(cam_a[0].lut, indexes_41) node _logic_out_T_83 = bits(_logic_out_T_82, 0, 0) node _logic_out_T_84 = dshr(cam_a[0].lut, indexes_42) node _logic_out_T_85 = bits(_logic_out_T_84, 0, 0) node _logic_out_T_86 = dshr(cam_a[0].lut, indexes_43) node _logic_out_T_87 = bits(_logic_out_T_86, 0, 0) node _logic_out_T_88 = dshr(cam_a[0].lut, indexes_44) node _logic_out_T_89 = bits(_logic_out_T_88, 0, 0) node _logic_out_T_90 = dshr(cam_a[0].lut, indexes_45) node _logic_out_T_91 = bits(_logic_out_T_90, 0, 0) node _logic_out_T_92 = dshr(cam_a[0].lut, indexes_46) node _logic_out_T_93 = bits(_logic_out_T_92, 0, 0) node _logic_out_T_94 = dshr(cam_a[0].lut, indexes_47) node _logic_out_T_95 = bits(_logic_out_T_94, 0, 0) node _logic_out_T_96 = dshr(cam_a[0].lut, indexes_48) node _logic_out_T_97 = bits(_logic_out_T_96, 0, 0) node _logic_out_T_98 = dshr(cam_a[0].lut, indexes_49) node _logic_out_T_99 = bits(_logic_out_T_98, 0, 0) node _logic_out_T_100 = dshr(cam_a[0].lut, indexes_50) node _logic_out_T_101 = bits(_logic_out_T_100, 0, 0) node _logic_out_T_102 = dshr(cam_a[0].lut, indexes_51) node _logic_out_T_103 = bits(_logic_out_T_102, 0, 0) node _logic_out_T_104 = dshr(cam_a[0].lut, indexes_52) node _logic_out_T_105 = bits(_logic_out_T_104, 0, 0) node _logic_out_T_106 = dshr(cam_a[0].lut, indexes_53) node _logic_out_T_107 = bits(_logic_out_T_106, 0, 0) node _logic_out_T_108 = dshr(cam_a[0].lut, indexes_54) node _logic_out_T_109 = bits(_logic_out_T_108, 0, 0) node _logic_out_T_110 = dshr(cam_a[0].lut, indexes_55) node _logic_out_T_111 = bits(_logic_out_T_110, 0, 0) node _logic_out_T_112 = dshr(cam_a[0].lut, indexes_56) node _logic_out_T_113 = bits(_logic_out_T_112, 0, 0) node _logic_out_T_114 = dshr(cam_a[0].lut, indexes_57) node _logic_out_T_115 = bits(_logic_out_T_114, 0, 0) node _logic_out_T_116 = dshr(cam_a[0].lut, indexes_58) node _logic_out_T_117 = bits(_logic_out_T_116, 0, 0) node _logic_out_T_118 = dshr(cam_a[0].lut, indexes_59) node _logic_out_T_119 = bits(_logic_out_T_118, 0, 0) node _logic_out_T_120 = dshr(cam_a[0].lut, indexes_60) node _logic_out_T_121 = bits(_logic_out_T_120, 0, 0) node _logic_out_T_122 = dshr(cam_a[0].lut, indexes_61) node _logic_out_T_123 = bits(_logic_out_T_122, 0, 0) node _logic_out_T_124 = dshr(cam_a[0].lut, indexes_62) node _logic_out_T_125 = bits(_logic_out_T_124, 0, 0) node _logic_out_T_126 = dshr(cam_a[0].lut, indexes_63) node _logic_out_T_127 = bits(_logic_out_T_126, 0, 0) node logic_out_lo_lo_lo_lo_lo = cat(_logic_out_T_3, _logic_out_T_1) node logic_out_lo_lo_lo_lo_hi = cat(_logic_out_T_7, _logic_out_T_5) node logic_out_lo_lo_lo_lo = cat(logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo) node logic_out_lo_lo_lo_hi_lo = cat(_logic_out_T_11, _logic_out_T_9) node logic_out_lo_lo_lo_hi_hi = cat(_logic_out_T_15, _logic_out_T_13) node logic_out_lo_lo_lo_hi = cat(logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo) node logic_out_lo_lo_lo = cat(logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo) node logic_out_lo_lo_hi_lo_lo = cat(_logic_out_T_19, _logic_out_T_17) node logic_out_lo_lo_hi_lo_hi = cat(_logic_out_T_23, _logic_out_T_21) node logic_out_lo_lo_hi_lo = cat(logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo) node logic_out_lo_lo_hi_hi_lo = cat(_logic_out_T_27, _logic_out_T_25) node logic_out_lo_lo_hi_hi_hi = cat(_logic_out_T_31, _logic_out_T_29) node logic_out_lo_lo_hi_hi = cat(logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo) node logic_out_lo_lo_hi = cat(logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo) node logic_out_lo_lo = cat(logic_out_lo_lo_hi, logic_out_lo_lo_lo) node logic_out_lo_hi_lo_lo_lo = cat(_logic_out_T_35, _logic_out_T_33) node logic_out_lo_hi_lo_lo_hi = cat(_logic_out_T_39, _logic_out_T_37) node logic_out_lo_hi_lo_lo = cat(logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo) node logic_out_lo_hi_lo_hi_lo = cat(_logic_out_T_43, _logic_out_T_41) node logic_out_lo_hi_lo_hi_hi = cat(_logic_out_T_47, _logic_out_T_45) node logic_out_lo_hi_lo_hi = cat(logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo) node logic_out_lo_hi_lo = cat(logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo) node logic_out_lo_hi_hi_lo_lo = cat(_logic_out_T_51, _logic_out_T_49) node logic_out_lo_hi_hi_lo_hi = cat(_logic_out_T_55, _logic_out_T_53) node logic_out_lo_hi_hi_lo = cat(logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo) node logic_out_lo_hi_hi_hi_lo = cat(_logic_out_T_59, _logic_out_T_57) node logic_out_lo_hi_hi_hi_hi = cat(_logic_out_T_63, _logic_out_T_61) node logic_out_lo_hi_hi_hi = cat(logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo) node logic_out_lo_hi_hi = cat(logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo) node logic_out_lo_hi = cat(logic_out_lo_hi_hi, logic_out_lo_hi_lo) node logic_out_lo = cat(logic_out_lo_hi, logic_out_lo_lo) node logic_out_hi_lo_lo_lo_lo = cat(_logic_out_T_67, _logic_out_T_65) node logic_out_hi_lo_lo_lo_hi = cat(_logic_out_T_71, _logic_out_T_69) node logic_out_hi_lo_lo_lo = cat(logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo) node logic_out_hi_lo_lo_hi_lo = cat(_logic_out_T_75, _logic_out_T_73) node logic_out_hi_lo_lo_hi_hi = cat(_logic_out_T_79, _logic_out_T_77) node logic_out_hi_lo_lo_hi = cat(logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo) node logic_out_hi_lo_lo = cat(logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo) node logic_out_hi_lo_hi_lo_lo = cat(_logic_out_T_83, _logic_out_T_81) node logic_out_hi_lo_hi_lo_hi = cat(_logic_out_T_87, _logic_out_T_85) node logic_out_hi_lo_hi_lo = cat(logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo) node logic_out_hi_lo_hi_hi_lo = cat(_logic_out_T_91, _logic_out_T_89) node logic_out_hi_lo_hi_hi_hi = cat(_logic_out_T_95, _logic_out_T_93) node logic_out_hi_lo_hi_hi = cat(logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo) node logic_out_hi_lo_hi = cat(logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo) node logic_out_hi_lo = cat(logic_out_hi_lo_hi, logic_out_hi_lo_lo) node logic_out_hi_hi_lo_lo_lo = cat(_logic_out_T_99, _logic_out_T_97) node logic_out_hi_hi_lo_lo_hi = cat(_logic_out_T_103, _logic_out_T_101) node logic_out_hi_hi_lo_lo = cat(logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo) node logic_out_hi_hi_lo_hi_lo = cat(_logic_out_T_107, _logic_out_T_105) node logic_out_hi_hi_lo_hi_hi = cat(_logic_out_T_111, _logic_out_T_109) node logic_out_hi_hi_lo_hi = cat(logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo) node logic_out_hi_hi_lo = cat(logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo) node logic_out_hi_hi_hi_lo_lo = cat(_logic_out_T_115, _logic_out_T_113) node logic_out_hi_hi_hi_lo_hi = cat(_logic_out_T_119, _logic_out_T_117) node logic_out_hi_hi_hi_lo = cat(logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo) node logic_out_hi_hi_hi_hi_lo = cat(_logic_out_T_123, _logic_out_T_121) node logic_out_hi_hi_hi_hi_hi = cat(_logic_out_T_127, _logic_out_T_125) node logic_out_hi_hi_hi_hi = cat(logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo) node logic_out_hi_hi_hi = cat(logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo) node logic_out_hi_hi = cat(logic_out_hi_hi_hi, logic_out_hi_hi_lo) node logic_out_hi = cat(logic_out_hi_hi, logic_out_hi_lo) node logic_out = cat(logic_out_hi, logic_out_lo) node unsigned = bits(cam_a[0].bits.param, 1, 1) node take_max = bits(cam_a[0].bits.param, 0, 0) node adder = bits(cam_a[0].bits.param, 2, 2) node _signSel_T = not(cam_a[0].bits.mask) node _signSel_T_1 = shr(cam_a[0].bits.mask, 1) node _signSel_T_2 = or(_signSel_T, _signSel_T_1) node signSel = not(_signSel_T_2) node _signbits_a_T = bits(cam_a[0].bits.data, 7, 7) node _signbits_a_T_1 = bits(cam_a[0].bits.data, 15, 15) node _signbits_a_T_2 = bits(cam_a[0].bits.data, 23, 23) node _signbits_a_T_3 = bits(cam_a[0].bits.data, 31, 31) node _signbits_a_T_4 = bits(cam_a[0].bits.data, 39, 39) node _signbits_a_T_5 = bits(cam_a[0].bits.data, 47, 47) node _signbits_a_T_6 = bits(cam_a[0].bits.data, 55, 55) node _signbits_a_T_7 = bits(cam_a[0].bits.data, 63, 63) node signbits_a_lo_lo = cat(_signbits_a_T_1, _signbits_a_T) node signbits_a_lo_hi = cat(_signbits_a_T_3, _signbits_a_T_2) node signbits_a_lo = cat(signbits_a_lo_hi, signbits_a_lo_lo) node signbits_a_hi_lo = cat(_signbits_a_T_5, _signbits_a_T_4) node signbits_a_hi_hi = cat(_signbits_a_T_7, _signbits_a_T_6) node signbits_a_hi = cat(signbits_a_hi_hi, signbits_a_hi_lo) node signbits_a = cat(signbits_a_hi, signbits_a_lo) node _signbits_d_T = bits(cam_d[0].data, 7, 7) node _signbits_d_T_1 = bits(cam_d[0].data, 15, 15) node _signbits_d_T_2 = bits(cam_d[0].data, 23, 23) node _signbits_d_T_3 = bits(cam_d[0].data, 31, 31) node _signbits_d_T_4 = bits(cam_d[0].data, 39, 39) node _signbits_d_T_5 = bits(cam_d[0].data, 47, 47) node _signbits_d_T_6 = bits(cam_d[0].data, 55, 55) node _signbits_d_T_7 = bits(cam_d[0].data, 63, 63) node signbits_d_lo_lo = cat(_signbits_d_T_1, _signbits_d_T) node signbits_d_lo_hi = cat(_signbits_d_T_3, _signbits_d_T_2) node signbits_d_lo = cat(signbits_d_lo_hi, signbits_d_lo_lo) node signbits_d_hi_lo = cat(_signbits_d_T_5, _signbits_d_T_4) node signbits_d_hi_hi = cat(_signbits_d_T_7, _signbits_d_T_6) node signbits_d_hi = cat(signbits_d_hi_hi, signbits_d_hi_lo) node signbits_d = cat(signbits_d_hi, signbits_d_lo) node _signbit_a_T = and(signbits_a, signSel) node _signbit_a_T_1 = shl(_signbit_a_T, 1) node signbit_a = bits(_signbit_a_T_1, 7, 0) node _signbit_d_T = and(signbits_d, signSel) node _signbit_d_T_1 = shl(_signbit_d_T, 1) node signbit_d = bits(_signbit_d_T_1, 7, 0) node _signext_a_T = shl(signbit_a, 1) node _signext_a_T_1 = bits(_signext_a_T, 7, 0) node _signext_a_T_2 = or(signbit_a, _signext_a_T_1) node _signext_a_T_3 = shl(_signext_a_T_2, 2) node _signext_a_T_4 = bits(_signext_a_T_3, 7, 0) node _signext_a_T_5 = or(_signext_a_T_2, _signext_a_T_4) node _signext_a_T_6 = shl(_signext_a_T_5, 4) node _signext_a_T_7 = bits(_signext_a_T_6, 7, 0) node _signext_a_T_8 = or(_signext_a_T_5, _signext_a_T_7) node _signext_a_T_9 = bits(_signext_a_T_8, 7, 0) node _signext_a_T_10 = bits(_signext_a_T_9, 0, 0) node _signext_a_T_11 = bits(_signext_a_T_9, 1, 1) node _signext_a_T_12 = bits(_signext_a_T_9, 2, 2) node _signext_a_T_13 = bits(_signext_a_T_9, 3, 3) node _signext_a_T_14 = bits(_signext_a_T_9, 4, 4) node _signext_a_T_15 = bits(_signext_a_T_9, 5, 5) node _signext_a_T_16 = bits(_signext_a_T_9, 6, 6) node _signext_a_T_17 = bits(_signext_a_T_9, 7, 7) node _signext_a_T_18 = mux(_signext_a_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_19 = mux(_signext_a_T_11, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_20 = mux(_signext_a_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_21 = mux(_signext_a_T_13, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_22 = mux(_signext_a_T_14, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_23 = mux(_signext_a_T_15, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_24 = mux(_signext_a_T_16, UInt<8>(0hff), UInt<8>(0h0)) node _signext_a_T_25 = mux(_signext_a_T_17, UInt<8>(0hff), UInt<8>(0h0)) node signext_a_lo_lo = cat(_signext_a_T_19, _signext_a_T_18) node signext_a_lo_hi = cat(_signext_a_T_21, _signext_a_T_20) node signext_a_lo = cat(signext_a_lo_hi, signext_a_lo_lo) node signext_a_hi_lo = cat(_signext_a_T_23, _signext_a_T_22) node signext_a_hi_hi = cat(_signext_a_T_25, _signext_a_T_24) node signext_a_hi = cat(signext_a_hi_hi, signext_a_hi_lo) node signext_a = cat(signext_a_hi, signext_a_lo) node _signext_d_T = shl(signbit_d, 1) node _signext_d_T_1 = bits(_signext_d_T, 7, 0) node _signext_d_T_2 = or(signbit_d, _signext_d_T_1) node _signext_d_T_3 = shl(_signext_d_T_2, 2) node _signext_d_T_4 = bits(_signext_d_T_3, 7, 0) node _signext_d_T_5 = or(_signext_d_T_2, _signext_d_T_4) node _signext_d_T_6 = shl(_signext_d_T_5, 4) node _signext_d_T_7 = bits(_signext_d_T_6, 7, 0) node _signext_d_T_8 = or(_signext_d_T_5, _signext_d_T_7) node _signext_d_T_9 = bits(_signext_d_T_8, 7, 0) node _signext_d_T_10 = bits(_signext_d_T_9, 0, 0) node _signext_d_T_11 = bits(_signext_d_T_9, 1, 1) node _signext_d_T_12 = bits(_signext_d_T_9, 2, 2) node _signext_d_T_13 = bits(_signext_d_T_9, 3, 3) node _signext_d_T_14 = bits(_signext_d_T_9, 4, 4) node _signext_d_T_15 = bits(_signext_d_T_9, 5, 5) node _signext_d_T_16 = bits(_signext_d_T_9, 6, 6) node _signext_d_T_17 = bits(_signext_d_T_9, 7, 7) node _signext_d_T_18 = mux(_signext_d_T_10, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_19 = mux(_signext_d_T_11, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_20 = mux(_signext_d_T_12, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_21 = mux(_signext_d_T_13, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_22 = mux(_signext_d_T_14, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_23 = mux(_signext_d_T_15, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_24 = mux(_signext_d_T_16, UInt<8>(0hff), UInt<8>(0h0)) node _signext_d_T_25 = mux(_signext_d_T_17, UInt<8>(0hff), UInt<8>(0h0)) node signext_d_lo_lo = cat(_signext_d_T_19, _signext_d_T_18) node signext_d_lo_hi = cat(_signext_d_T_21, _signext_d_T_20) node signext_d_lo = cat(signext_d_lo_hi, signext_d_lo_lo) node signext_d_hi_lo = cat(_signext_d_T_23, _signext_d_T_22) node signext_d_hi_hi = cat(_signext_d_T_25, _signext_d_T_24) node signext_d_hi = cat(signext_d_hi_hi, signext_d_hi_lo) node signext_d = cat(signext_d_hi, signext_d_lo) node _wide_mask_T = bits(cam_a[0].bits.mask, 0, 0) node _wide_mask_T_1 = bits(cam_a[0].bits.mask, 1, 1) node _wide_mask_T_2 = bits(cam_a[0].bits.mask, 2, 2) node _wide_mask_T_3 = bits(cam_a[0].bits.mask, 3, 3) node _wide_mask_T_4 = bits(cam_a[0].bits.mask, 4, 4) node _wide_mask_T_5 = bits(cam_a[0].bits.mask, 5, 5) node _wide_mask_T_6 = bits(cam_a[0].bits.mask, 6, 6) node _wide_mask_T_7 = bits(cam_a[0].bits.mask, 7, 7) node _wide_mask_T_8 = mux(_wide_mask_T, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_9 = mux(_wide_mask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_10 = mux(_wide_mask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_11 = mux(_wide_mask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_12 = mux(_wide_mask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_13 = mux(_wide_mask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_14 = mux(_wide_mask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _wide_mask_T_15 = mux(_wide_mask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node wide_mask_lo_lo = cat(_wide_mask_T_9, _wide_mask_T_8) node wide_mask_lo_hi = cat(_wide_mask_T_11, _wide_mask_T_10) node wide_mask_lo = cat(wide_mask_lo_hi, wide_mask_lo_lo) node wide_mask_hi_lo = cat(_wide_mask_T_13, _wide_mask_T_12) node wide_mask_hi_hi = cat(_wide_mask_T_15, _wide_mask_T_14) node wide_mask_hi = cat(wide_mask_hi_hi, wide_mask_hi_lo) node wide_mask = cat(wide_mask_hi, wide_mask_lo) node _a_a_ext_T = and(cam_a[0].bits.data, wide_mask) node a_a_ext = or(_a_a_ext_T, signext_a) node _a_d_ext_T = and(cam_d[0].data, wide_mask) node a_d_ext = or(_a_d_ext_T, signext_d) node _a_d_inv_T = not(a_d_ext) node a_d_inv = mux(adder, a_d_ext, _a_d_inv_T) node _adder_out_T = add(a_a_ext, a_d_inv) node adder_out = tail(_adder_out_T, 1) node _a_bigger_uneq_T = bits(a_a_ext, 63, 63) node a_bigger_uneq = eq(unsigned, _a_bigger_uneq_T) node _a_bigger_T = bits(a_a_ext, 63, 63) node _a_bigger_T_1 = bits(a_d_ext, 63, 63) node _a_bigger_T_2 = eq(_a_bigger_T, _a_bigger_T_1) node _a_bigger_T_3 = bits(adder_out, 63, 63) node _a_bigger_T_4 = eq(_a_bigger_T_3, UInt<1>(0h0)) node a_bigger = mux(_a_bigger_T_2, _a_bigger_T_4, a_bigger_uneq) node pick_a = eq(take_max, a_bigger) node _arith_out_T = mux(pick_a, cam_a[0].bits.data, cam_d[0].data) node arith_out = mux(adder, adder_out, _arith_out_T) node _amo_data_T = bits(cam_a[0].bits.opcode, 0, 0) node amo_data = mux(_amo_data_T, logic_out, arith_out) wire source_i : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} node _a_allow_T = eq(a_cam_busy, UInt<1>(0h0)) node _a_allow_T_1 = or(a_isSupported, cam_free_0) node a_allow = and(_a_allow_T, _a_allow_T_1) node _nodeIn_a_ready_T = and(source_i.ready, a_allow) connect nodeIn.a.ready, _nodeIn_a_ready_T node _source_i_valid_T = and(nodeIn.a.valid, a_allow) connect source_i.valid, _source_i_valid_T connect source_i.bits, nodeIn.a.bits node _T = eq(a_isSupported, UInt<1>(0h0)) when _T : connect source_i.bits.opcode, UInt<3>(0h4) connect source_i.bits.param, UInt<1>(0h0) wire source_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect source_c.valid, cam_amo_0 node _source_c_bits_T = or(cam_a[0].bits.corrupt, cam_d[0].corrupt) node _source_c_bits_legal_T = leq(UInt<1>(0h0), cam_a[0].bits.size) node _source_c_bits_legal_T_1 = leq(cam_a[0].bits.size, UInt<4>(0hc)) node _source_c_bits_legal_T_2 = and(_source_c_bits_legal_T, _source_c_bits_legal_T_1) node _source_c_bits_legal_T_3 = or(UInt<1>(0h0), _source_c_bits_legal_T_2) node _source_c_bits_legal_T_4 = xor(cam_a[0].bits.address, UInt<14>(0h3000)) node _source_c_bits_legal_T_5 = cvt(_source_c_bits_legal_T_4) node _source_c_bits_legal_T_6 = and(_source_c_bits_legal_T_5, asSInt(UInt<30>(0h1a313000))) node _source_c_bits_legal_T_7 = asSInt(_source_c_bits_legal_T_6) node _source_c_bits_legal_T_8 = eq(_source_c_bits_legal_T_7, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_9 = and(_source_c_bits_legal_T_3, _source_c_bits_legal_T_8) node _source_c_bits_legal_T_10 = leq(UInt<1>(0h0), cam_a[0].bits.size) node _source_c_bits_legal_T_11 = leq(cam_a[0].bits.size, UInt<3>(0h6)) node _source_c_bits_legal_T_12 = and(_source_c_bits_legal_T_10, _source_c_bits_legal_T_11) node _source_c_bits_legal_T_13 = or(UInt<1>(0h0), _source_c_bits_legal_T_12) node _source_c_bits_legal_T_14 = xor(cam_a[0].bits.address, UInt<1>(0h0)) node _source_c_bits_legal_T_15 = cvt(_source_c_bits_legal_T_14) node _source_c_bits_legal_T_16 = and(_source_c_bits_legal_T_15, asSInt(UInt<30>(0h1a312000))) node _source_c_bits_legal_T_17 = asSInt(_source_c_bits_legal_T_16) node _source_c_bits_legal_T_18 = eq(_source_c_bits_legal_T_17, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_19 = xor(cam_a[0].bits.address, UInt<21>(0h100000)) node _source_c_bits_legal_T_20 = cvt(_source_c_bits_legal_T_19) node _source_c_bits_legal_T_21 = and(_source_c_bits_legal_T_20, asSInt(UInt<30>(0h1a303000))) node _source_c_bits_legal_T_22 = asSInt(_source_c_bits_legal_T_21) node _source_c_bits_legal_T_23 = eq(_source_c_bits_legal_T_22, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_24 = xor(cam_a[0].bits.address, UInt<22>(0h200000)) node _source_c_bits_legal_T_25 = cvt(_source_c_bits_legal_T_24) node _source_c_bits_legal_T_26 = and(_source_c_bits_legal_T_25, asSInt(UInt<30>(0h1a313000))) node _source_c_bits_legal_T_27 = asSInt(_source_c_bits_legal_T_26) node _source_c_bits_legal_T_28 = eq(_source_c_bits_legal_T_27, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_29 = xor(cam_a[0].bits.address, UInt<22>(0h300000)) node _source_c_bits_legal_T_30 = cvt(_source_c_bits_legal_T_29) node _source_c_bits_legal_T_31 = and(_source_c_bits_legal_T_30, asSInt(UInt<30>(0h1a310000))) node _source_c_bits_legal_T_32 = asSInt(_source_c_bits_legal_T_31) node _source_c_bits_legal_T_33 = eq(_source_c_bits_legal_T_32, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_34 = xor(cam_a[0].bits.address, UInt<26>(0h2000000)) node _source_c_bits_legal_T_35 = cvt(_source_c_bits_legal_T_34) node _source_c_bits_legal_T_36 = and(_source_c_bits_legal_T_35, asSInt(UInt<30>(0h1a310000))) node _source_c_bits_legal_T_37 = asSInt(_source_c_bits_legal_T_36) node _source_c_bits_legal_T_38 = eq(_source_c_bits_legal_T_37, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_39 = xor(cam_a[0].bits.address, UInt<26>(0h2010000)) node _source_c_bits_legal_T_40 = cvt(_source_c_bits_legal_T_39) node _source_c_bits_legal_T_41 = and(_source_c_bits_legal_T_40, asSInt(UInt<30>(0h1a313000))) node _source_c_bits_legal_T_42 = asSInt(_source_c_bits_legal_T_41) node _source_c_bits_legal_T_43 = eq(_source_c_bits_legal_T_42, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_44 = xor(cam_a[0].bits.address, UInt<28>(0h8000000)) node _source_c_bits_legal_T_45 = cvt(_source_c_bits_legal_T_44) node _source_c_bits_legal_T_46 = and(_source_c_bits_legal_T_45, asSInt(UInt<30>(0h18000000))) node _source_c_bits_legal_T_47 = asSInt(_source_c_bits_legal_T_46) node _source_c_bits_legal_T_48 = eq(_source_c_bits_legal_T_47, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_49 = xor(cam_a[0].bits.address, UInt<29>(0h10000000)) node _source_c_bits_legal_T_50 = cvt(_source_c_bits_legal_T_49) node _source_c_bits_legal_T_51 = and(_source_c_bits_legal_T_50, asSInt(UInt<30>(0h1a313000))) node _source_c_bits_legal_T_52 = asSInt(_source_c_bits_legal_T_51) node _source_c_bits_legal_T_53 = eq(_source_c_bits_legal_T_52, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_54 = or(_source_c_bits_legal_T_18, _source_c_bits_legal_T_23) node _source_c_bits_legal_T_55 = or(_source_c_bits_legal_T_54, _source_c_bits_legal_T_28) node _source_c_bits_legal_T_56 = or(_source_c_bits_legal_T_55, _source_c_bits_legal_T_33) node _source_c_bits_legal_T_57 = or(_source_c_bits_legal_T_56, _source_c_bits_legal_T_38) node _source_c_bits_legal_T_58 = or(_source_c_bits_legal_T_57, _source_c_bits_legal_T_43) node _source_c_bits_legal_T_59 = or(_source_c_bits_legal_T_58, _source_c_bits_legal_T_48) node _source_c_bits_legal_T_60 = or(_source_c_bits_legal_T_59, _source_c_bits_legal_T_53) node _source_c_bits_legal_T_61 = and(_source_c_bits_legal_T_13, _source_c_bits_legal_T_60) node _source_c_bits_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) node _source_c_bits_legal_T_63 = xor(cam_a[0].bits.address, UInt<17>(0h10000)) node _source_c_bits_legal_T_64 = cvt(_source_c_bits_legal_T_63) node _source_c_bits_legal_T_65 = and(_source_c_bits_legal_T_64, asSInt(UInt<30>(0h1a310000))) node _source_c_bits_legal_T_66 = asSInt(_source_c_bits_legal_T_65) node _source_c_bits_legal_T_67 = eq(_source_c_bits_legal_T_66, asSInt(UInt<1>(0h0))) node _source_c_bits_legal_T_68 = and(_source_c_bits_legal_T_62, _source_c_bits_legal_T_67) node _source_c_bits_legal_T_69 = or(UInt<1>(0h0), _source_c_bits_legal_T_9) node _source_c_bits_legal_T_70 = or(_source_c_bits_legal_T_69, _source_c_bits_legal_T_61) node source_c_bits_legal = or(_source_c_bits_legal_T_70, _source_c_bits_legal_T_68) wire source_c_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} connect source_c_bits_a.opcode, UInt<1>(0h0) connect source_c_bits_a.param, UInt<1>(0h0) connect source_c_bits_a.size, cam_a[0].bits.size connect source_c_bits_a.source, cam_a[0].bits.source connect source_c_bits_a.address, cam_a[0].bits.address node _source_c_bits_a_mask_sizeOH_T = or(cam_a[0].bits.size, UInt<3>(0h0)) node source_c_bits_a_mask_sizeOH_shiftAmount = bits(_source_c_bits_a_mask_sizeOH_T, 1, 0) node _source_c_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), source_c_bits_a_mask_sizeOH_shiftAmount) node _source_c_bits_a_mask_sizeOH_T_2 = bits(_source_c_bits_a_mask_sizeOH_T_1, 2, 0) node source_c_bits_a_mask_sizeOH = or(_source_c_bits_a_mask_sizeOH_T_2, UInt<1>(0h1)) node source_c_bits_a_mask_sub_sub_sub_0_1 = geq(cam_a[0].bits.size, UInt<2>(0h3)) node source_c_bits_a_mask_sub_sub_size = bits(source_c_bits_a_mask_sizeOH, 2, 2) node source_c_bits_a_mask_sub_sub_bit = bits(cam_a[0].bits.address, 2, 2) node source_c_bits_a_mask_sub_sub_nbit = eq(source_c_bits_a_mask_sub_sub_bit, UInt<1>(0h0)) node source_c_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_nbit) node _source_c_bits_a_mask_sub_sub_acc_T = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_0_2) node source_c_bits_a_mask_sub_sub_0_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T) node source_c_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_bit) node _source_c_bits_a_mask_sub_sub_acc_T_1 = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_1_2) node source_c_bits_a_mask_sub_sub_1_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T_1) node source_c_bits_a_mask_sub_size = bits(source_c_bits_a_mask_sizeOH, 1, 1) node source_c_bits_a_mask_sub_bit = bits(cam_a[0].bits.address, 1, 1) node source_c_bits_a_mask_sub_nbit = eq(source_c_bits_a_mask_sub_bit, UInt<1>(0h0)) node source_c_bits_a_mask_sub_0_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_nbit) node _source_c_bits_a_mask_sub_acc_T = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_0_2) node source_c_bits_a_mask_sub_0_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T) node source_c_bits_a_mask_sub_1_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_bit) node _source_c_bits_a_mask_sub_acc_T_1 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_1_2) node source_c_bits_a_mask_sub_1_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T_1) node source_c_bits_a_mask_sub_2_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_nbit) node _source_c_bits_a_mask_sub_acc_T_2 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_2_2) node source_c_bits_a_mask_sub_2_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_2) node source_c_bits_a_mask_sub_3_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_bit) node _source_c_bits_a_mask_sub_acc_T_3 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_3_2) node source_c_bits_a_mask_sub_3_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_3) node source_c_bits_a_mask_size = bits(source_c_bits_a_mask_sizeOH, 0, 0) node source_c_bits_a_mask_bit = bits(cam_a[0].bits.address, 0, 0) node source_c_bits_a_mask_nbit = eq(source_c_bits_a_mask_bit, UInt<1>(0h0)) node source_c_bits_a_mask_eq = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq) node source_c_bits_a_mask_acc = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T) node source_c_bits_a_mask_eq_1 = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_1 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_1) node source_c_bits_a_mask_acc_1 = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T_1) node source_c_bits_a_mask_eq_2 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_2 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_2) node source_c_bits_a_mask_acc_2 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_2) node source_c_bits_a_mask_eq_3 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_3 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_3) node source_c_bits_a_mask_acc_3 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_3) node source_c_bits_a_mask_eq_4 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_4 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_4) node source_c_bits_a_mask_acc_4 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_4) node source_c_bits_a_mask_eq_5 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_5 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_5) node source_c_bits_a_mask_acc_5 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_5) node source_c_bits_a_mask_eq_6 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_nbit) node _source_c_bits_a_mask_acc_T_6 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_6) node source_c_bits_a_mask_acc_6 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_6) node source_c_bits_a_mask_eq_7 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_bit) node _source_c_bits_a_mask_acc_T_7 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_7) node source_c_bits_a_mask_acc_7 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_7) node source_c_bits_a_mask_lo_lo = cat(source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc) node source_c_bits_a_mask_lo_hi = cat(source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2) node source_c_bits_a_mask_lo = cat(source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo) node source_c_bits_a_mask_hi_lo = cat(source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4) node source_c_bits_a_mask_hi_hi = cat(source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6) node source_c_bits_a_mask_hi = cat(source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo) node _source_c_bits_a_mask_T = cat(source_c_bits_a_mask_hi, source_c_bits_a_mask_lo) connect source_c_bits_a.mask, _source_c_bits_a_mask_T connect source_c_bits_a.data, amo_data connect source_c_bits_a.corrupt, _source_c_bits_T connect source_c.bits, source_c_bits_a node _decode_T = dshl(UInt<12>(0hfff), nodeIn.a.bits.size) node _decode_T_1 = bits(_decode_T, 11, 0) node _decode_T_2 = not(_decode_T_1) node decode = shr(_decode_T_2, 3) node _opdata_T = bits(nodeIn.a.bits.opcode, 2, 2) node opdata = eq(_opdata_T, UInt<1>(0h0)) node _T_1 = mux(opdata, decode, UInt<1>(0h0)) regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) node idle = eq(beatsLeft, UInt<1>(0h0)) node latch = and(idle, nodeOut.a.ready) node _readys_T = cat(source_i.valid, source_c.valid) node _readys_T_1 = shl(_readys_T, 1) node _readys_T_2 = bits(_readys_T_1, 1, 0) node _readys_T_3 = or(_readys_T, _readys_T_2) node _readys_T_4 = bits(_readys_T_3, 1, 0) node _readys_T_5 = shl(_readys_T_4, 1) node _readys_T_6 = bits(_readys_T_5, 1, 0) node _readys_T_7 = not(_readys_T_6) node _readys_T_8 = bits(_readys_T_7, 0, 0) node _readys_T_9 = bits(_readys_T_7, 1, 1) wire readys : UInt<1>[2] connect readys[0], _readys_T_8 connect readys[1], _readys_T_9 node _winner_T = and(readys[0], source_c.valid) node _winner_T_1 = and(readys[1], source_i.valid) wire winner : UInt<1>[2] connect winner[0], _winner_T connect winner[1], _winner_T_1 node prefixOR_1 = or(UInt<1>(0h0), winner[0]) node _prefixOR_T = or(prefixOR_1, winner[1]) node _T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_3 = eq(winner[0], UInt<1>(0h0)) node _T_4 = or(_T_2, _T_3) node _T_5 = eq(prefixOR_1, UInt<1>(0h0)) node _T_6 = eq(winner[1], UInt<1>(0h0)) node _T_7 = or(_T_5, _T_6) node _T_8 = and(_T_4, _T_7) node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : node _T_11 = eq(_T_8, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _})\n") : printf assert(clock, _T_8, UInt<1>(0h1), "") : assert node _T_12 = or(source_c.valid, source_i.valid) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = or(winner[0], winner[1]) node _T_15 = or(_T_13, _T_14) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_))\n") : printf_1 assert(clock, _T_15, UInt<1>(0h1), "") : assert_1 node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0)) node maskedBeats_1 = mux(winner[1], _T_1, UInt<1>(0h0)) node initBeats = or(maskedBeats_0, maskedBeats_1) node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid) node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) connect beatsLeft, _beatsLeft_T_3 wire _state_WIRE : UInt<1>[2] connect _state_WIRE[0], UInt<1>(0h0) connect _state_WIRE[1], UInt<1>(0h0) regreset state : UInt<1>[2], clock, reset, _state_WIRE node muxState = mux(idle, winner, state) connect state, muxState node allowed = mux(idle, readys, state) node _source_c_ready_T = and(nodeOut.a.ready, allowed[0]) connect source_c.ready, _source_c_ready_T node _source_i_ready_T = and(nodeOut.a.ready, allowed[1]) connect source_i.ready, _source_i_ready_T node _nodeOut_a_valid_T = or(source_c.valid, source_i.valid) node _nodeOut_a_valid_T_1 = mux(state[0], source_c.valid, UInt<1>(0h0)) node _nodeOut_a_valid_T_2 = mux(state[1], source_i.valid, UInt<1>(0h0)) node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2) wire _nodeOut_a_valid_WIRE : UInt<1> connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3 node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE) connect nodeOut.a.valid, _nodeOut_a_valid_T_4 wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>} node _nodeOut_a_bits_T = mux(muxState[0], source_c.bits.corrupt, UInt<1>(0h0)) node _nodeOut_a_bits_T_1 = mux(muxState[1], source_i.bits.corrupt, UInt<1>(0h0)) node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1) wire _nodeOut_a_bits_WIRE_1 : UInt<1> connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2 connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1 node _nodeOut_a_bits_T_3 = mux(muxState[0], source_c.bits.data, UInt<1>(0h0)) node _nodeOut_a_bits_T_4 = mux(muxState[1], source_i.bits.data, UInt<1>(0h0)) node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4) wire _nodeOut_a_bits_WIRE_2 : UInt<64> connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5 connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2 node _nodeOut_a_bits_T_6 = mux(muxState[0], source_c.bits.mask, UInt<1>(0h0)) node _nodeOut_a_bits_T_7 = mux(muxState[1], source_i.bits.mask, UInt<1>(0h0)) node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7) wire _nodeOut_a_bits_WIRE_3 : UInt<8> connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8 connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3 wire _nodeOut_a_bits_WIRE_4 : { } connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4 wire _nodeOut_a_bits_WIRE_5 : { } connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5 node _nodeOut_a_bits_T_9 = mux(muxState[0], source_c.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_T_10 = mux(muxState[1], source_i.bits.address, UInt<1>(0h0)) node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10) wire _nodeOut_a_bits_WIRE_6 : UInt<29> connect _nodeOut_a_bits_WIRE_6, _nodeOut_a_bits_T_11 connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_6 node _nodeOut_a_bits_T_12 = mux(muxState[0], source_c.bits.source, UInt<1>(0h0)) node _nodeOut_a_bits_T_13 = mux(muxState[1], source_i.bits.source, UInt<1>(0h0)) node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13) wire _nodeOut_a_bits_WIRE_7 : UInt<7> connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_14 connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_7 node _nodeOut_a_bits_T_15 = mux(muxState[0], source_c.bits.size, UInt<1>(0h0)) node _nodeOut_a_bits_T_16 = mux(muxState[1], source_i.bits.size, UInt<1>(0h0)) node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16) wire _nodeOut_a_bits_WIRE_8 : UInt<4> connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_17 connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_8 node _nodeOut_a_bits_T_18 = mux(muxState[0], source_c.bits.param, UInt<1>(0h0)) node _nodeOut_a_bits_T_19 = mux(muxState[1], source_i.bits.param, UInt<1>(0h0)) node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19) wire _nodeOut_a_bits_WIRE_9 : UInt<3> connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_20 connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_9 node _nodeOut_a_bits_T_21 = mux(muxState[0], source_c.bits.opcode, UInt<1>(0h0)) node _nodeOut_a_bits_T_22 = mux(muxState[1], source_i.bits.opcode, UInt<1>(0h0)) node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22) wire _nodeOut_a_bits_WIRE_10 : UInt<3> connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_23 connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_10 connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode node _T_19 = and(source_i.ready, source_i.valid) node _T_20 = eq(a_isSupported, UInt<1>(0h0)) node _T_21 = and(_T_19, _T_20) when _T_21 : when a_cam_sel_free_0 : connect cam_a[0].fifoId, UInt<1>(0h0) connect cam_a[0].bits, nodeIn.a.bits node _cam_a_0_lut_T = bits(nodeIn.a.bits.param, 1, 0) node _cam_a_0_lut_T_1 = eq(UInt<3>(0h1), _cam_a_0_lut_T) node _cam_a_0_lut_T_2 = mux(_cam_a_0_lut_T_1, UInt<4>(0he), UInt<4>(0h8)) node _cam_a_0_lut_T_3 = eq(UInt<3>(0h0), _cam_a_0_lut_T) node _cam_a_0_lut_T_4 = mux(_cam_a_0_lut_T_3, UInt<3>(0h6), _cam_a_0_lut_T_2) node _cam_a_0_lut_T_5 = eq(UInt<3>(0h3), _cam_a_0_lut_T) node _cam_a_0_lut_T_6 = mux(_cam_a_0_lut_T_5, UInt<4>(0hc), _cam_a_0_lut_T_4) connect cam_a[0].lut, _cam_a_0_lut_T_6 when a_cam_sel_free_0 : connect cam_s[0].state, UInt<2>(0h3) node _T_22 = and(source_c.ready, source_c.valid) when _T_22 : when a_cam_sel_put_0 : connect cam_s[0].state, UInt<1>(0h1) node _d_first_T = and(nodeOut.d.ready, nodeOut.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T node d_cam_sel_raw_0 = eq(cam_a[0].bits.source, nodeIn.d.bits.source) node d_cam_sel_match_0 = and(d_cam_sel_raw_0, cam_dmatch_0) node d_cam_sel_0 = mux(UInt<1>(0h0), a_cam_sel_free_0, d_cam_sel_match_0) node d_cam_sel_any = or(UInt<1>(0h0), d_cam_sel_match_0) node d_ackd = eq(nodeOut.d.bits.opcode, UInt<1>(0h1)) node d_ack = eq(nodeOut.d.bits.opcode, UInt<1>(0h0)) node _T_23 = and(nodeOut.d.ready, nodeOut.d.valid) node _T_24 = and(_T_23, d_first) when _T_24 : node _T_25 = and(d_cam_sel_0, d_ackd) when _T_25 : connect cam_d[0].data, nodeOut.d.bits.data connect cam_d[0].denied, nodeOut.d.bits.denied connect cam_d[0].corrupt, nodeOut.d.bits.corrupt when d_cam_sel_0 : node _cam_s_0_state_T = mux(d_ackd, UInt<2>(0h2), UInt<1>(0h0)) connect cam_s[0].state, _cam_s_0_state_T node _d_drop_T = and(d_first, d_ackd) node d_drop = and(_d_drop_T, d_cam_sel_any) node _d_replace_T = and(d_first, d_ack) node d_replace = and(_d_replace_T, d_cam_sel_match_0) node _nodeIn_d_valid_T = eq(d_drop, UInt<1>(0h0)) node _nodeIn_d_valid_T_1 = and(nodeOut.d.valid, _nodeIn_d_valid_T) connect nodeIn.d.valid, _nodeIn_d_valid_T_1 node _nodeOut_d_ready_T = or(nodeIn.d.ready, d_drop) connect nodeOut.d.ready, _nodeOut_d_ready_T connect nodeIn.d.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn.d.bits.data, nodeOut.d.bits.data connect nodeIn.d.bits.denied, nodeOut.d.bits.denied connect nodeIn.d.bits.sink, nodeOut.d.bits.sink connect nodeIn.d.bits.source, nodeOut.d.bits.source connect nodeIn.d.bits.size, nodeOut.d.bits.size connect nodeIn.d.bits.param, nodeOut.d.bits.param connect nodeIn.d.bits.opcode, nodeOut.d.bits.opcode when d_replace : connect nodeIn.d.bits.opcode, UInt<1>(0h1) connect nodeIn.d.bits.data, cam_d[0].data node _nodeIn_d_bits_corrupt_T = or(cam_d[0].corrupt, nodeOut.d.bits.denied) connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_corrupt_T node _nodeIn_d_bits_denied_T = or(cam_d[0].denied, nodeOut.d.bits.denied) connect nodeIn.d.bits.denied, _nodeIn_d_bits_denied_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_38 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_39 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLAtomicAutomata_cbus( // @[AtomicAutomata.scala:36:9] input clock, // @[AtomicAutomata.scala:36:9] input reset, // @[AtomicAutomata.scala:36:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AtomicAutomata.scala:36:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AtomicAutomata.scala:36:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AtomicAutomata.scala:36:9] wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AtomicAutomata.scala:36:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AtomicAutomata.scala:36:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[AtomicAutomata.scala:36:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[AtomicAutomata.scala:36:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[AtomicAutomata.scala:36:9] wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[AtomicAutomata.scala:36:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _a_canLogical_T = 1'h1; // @[Parameters.scala:92:28] wire _a_canArithmetic_T = 1'h1; // @[Parameters.scala:92:28] wire _a_cam_sel_put_T = 1'h1; // @[AtomicAutomata.scala:103:83] wire _a_fifoId_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _a_cam_busy_T = 1'h1; // @[AtomicAutomata.scala:111:60] wire _a_cam_sel_free_T = 1'h1; // @[AtomicAutomata.scala:116:85] wire _source_c_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _source_c_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _a_canLogical_T_16 = 1'h0; // @[Parameters.scala:684:29] wire _a_canLogical_T_58 = 1'h0; // @[Parameters.scala:684:54] wire _a_canArithmetic_T_16 = 1'h0; // @[Parameters.scala:684:29] wire _a_canArithmetic_T_58 = 1'h0; // @[Parameters.scala:684:54] wire _source_c_bits_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _source_c_bits_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire maskedBeats_0 = 1'h0; // @[Arbiter.scala:82:69] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire [2:0] source_c_bits_opcode = 3'h0; // @[AtomicAutomata.scala:165:28] wire [2:0] source_c_bits_param = 3'h0; // @[AtomicAutomata.scala:165:28] wire [2:0] source_c_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] source_c_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73] wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73] wire [29:0] _a_fifoId_T_2 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _a_fifoId_T_3 = 30'h0; // @[Parameters.scala:137:46] wire [1:0] initval_state = 2'h0; // @[AtomicAutomata.scala:80:27] wire [1:0] _cam_s_WIRE_0_state = 2'h0; // @[AtomicAutomata.scala:82:50] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AtomicAutomata.scala:36:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AtomicAutomata.scala:36:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AtomicAutomata.scala:36:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[AtomicAutomata.scala:36:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[AtomicAutomata.scala:36:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_in_a_ready_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [1:0] auto_in_d_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [3:0] auto_in_d_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [6:0] auto_in_d_bits_source_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_sink_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_denied_0; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_in_d_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_in_d_valid_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9] wire [2:0] auto_out_a_bits_param_0; // @[AtomicAutomata.scala:36:9] wire [3:0] auto_out_a_bits_size_0; // @[AtomicAutomata.scala:36:9] wire [6:0] auto_out_a_bits_source_0; // @[AtomicAutomata.scala:36:9] wire [28:0] auto_out_a_bits_address_0; // @[AtomicAutomata.scala:36:9] wire [7:0] auto_out_a_bits_mask_0; // @[AtomicAutomata.scala:36:9] wire [63:0] auto_out_a_bits_data_0; // @[AtomicAutomata.scala:36:9] wire auto_out_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9] wire auto_out_a_valid_0; // @[AtomicAutomata.scala:36:9] wire auto_out_d_ready_0; // @[AtomicAutomata.scala:36:9] wire _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AtomicAutomata.scala:36:9] wire [3:0] source_i_bits_size = nodeIn_a_bits_size; // @[AtomicAutomata.scala:154:28] wire [6:0] source_i_bits_source = nodeIn_a_bits_source; // @[AtomicAutomata.scala:154:28] wire [28:0] _a_canLogical_T_17 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_17 = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] _a_fifoId_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31] wire [28:0] source_i_bits_address = nodeIn_a_bits_address; // @[AtomicAutomata.scala:154:28] wire [7:0] source_i_bits_mask = nodeIn_a_bits_mask; // @[AtomicAutomata.scala:154:28] wire [63:0] source_i_bits_data = nodeIn_a_bits_data; // @[AtomicAutomata.scala:154:28] wire source_i_bits_corrupt = nodeIn_a_bits_corrupt; // @[AtomicAutomata.scala:154:28] wire _nodeIn_d_valid_T_1; // @[AtomicAutomata.scala:241:35] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AtomicAutomata.scala:36:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[AtomicAutomata.scala:36:9] wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[AtomicAutomata.scala:36:9] wire [3:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[AtomicAutomata.scala:36:9] wire [6:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[AtomicAutomata.scala:36:9] wire [28:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[AtomicAutomata.scala:36:9] wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[AtomicAutomata.scala:36:9] wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[AtomicAutomata.scala:36:9] wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[AtomicAutomata.scala:36:9] wire _nodeOut_d_ready_T; // @[AtomicAutomata.scala:242:35] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[AtomicAutomata.scala:36:9] assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28] reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24] reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24] reg [3:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24] wire [3:0] source_c_bits_a_size = cam_a_0_bits_size; // @[Edges.scala:480:17] wire [3:0] _source_c_bits_a_mask_sizeOH_T = cam_a_0_bits_size; // @[Misc.scala:202:34] reg [6:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24] wire [6:0] source_c_bits_a_source = cam_a_0_bits_source; // @[Edges.scala:480:17] reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] wire [28:0] _source_c_bits_legal_T_14 = cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] wire [28:0] source_c_bits_a_address = cam_a_0_bits_address; // @[Edges.scala:480:17] reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24] reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24] reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24] reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24] wire cam_free_0 = ~(\|cam_s_0_state); // @[AtomicAutomata.scala:82:28, :86:44] wire _a_cam_por_free_T = cam_free_0; // @[AtomicAutomata.scala:86:44, :115:58] wire a_cam_sel_free_0 = cam_free_0; // @[AtomicAutomata.scala:86:44, :116:82] wire _GEN = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44] wire cam_amo_0; // @[AtomicAutomata.scala:87:44] assign cam_amo_0 = _GEN; // @[AtomicAutomata.scala:87:44] wire _cam_abusy_T_1; // @[AtomicAutomata.scala:88:68] assign _cam_abusy_T_1 = _GEN; // @[AtomicAutomata.scala:87:44, :88:68] wire _a_cam_por_put_T = cam_amo_0; // @[AtomicAutomata.scala:87:44, :102:56] wire a_cam_sel_put_0 = cam_amo_0; // @[AtomicAutomata.scala:87:44, :103:80] wire source_c_valid = cam_amo_0; // @[AtomicAutomata.scala:87:44, :165:28] wire _cam_abusy_T = &cam_s_0_state; // @[AtomicAutomata.scala:82:28, :88:49] wire cam_abusy_0 = _cam_abusy_T \| _cam_abusy_T_1; // @[AtomicAutomata.scala:88:{49,57,68}] wire a_cam_busy = cam_abusy_0; // @[AtomicAutomata.scala:88:57, :111:96] wire cam_dmatch_0 = \|cam_s_0_state; // @[AtomicAutomata.scala:82:28, :86:44, :89:49] wire _GEN_0 = nodeIn_a_bits_size < 4'h4; // @[Parameters.scala:92:38] wire _a_canLogical_T_1; // @[Parameters.scala:92:38] assign _a_canLogical_T_1 = _GEN_0; // @[Parameters.scala:92:38] wire _a_canLogical_T_60; // @[Parameters.scala:92:38] assign _a_canLogical_T_60 = _GEN_0; // @[Parameters.scala:92:38] wire _a_canArithmetic_T_1; // @[Parameters.scala:92:38] assign _a_canArithmetic_T_1 = _GEN_0; // @[Parameters.scala:92:38] wire _a_canArithmetic_T_60; // @[Parameters.scala:92:38] assign _a_canArithmetic_T_60 = _GEN_0; // @[Parameters.scala:92:38] wire _a_canLogical_T_2 = _a_canLogical_T_1; // @[Parameters.scala:92:{33,38}] wire _a_canLogical_T_3 = _a_canLogical_T_2; // @[Parameters.scala:684:29] wire [28:0] _GEN_1 = {nodeIn_a_bits_address[28:13], nodeIn_a_bits_address[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31] wire [28:0] _a_canLogical_T_4; // @[Parameters.scala:137:31] assign _a_canLogical_T_4 = _GEN_1; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_4; // @[Parameters.scala:137:31] assign _a_canArithmetic_T_4 = _GEN_1; // @[Parameters.scala:137:31] wire [29:0] _a_canLogical_T_5 = {1'h0, _a_canLogical_T_4}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canLogical_T_6 = _a_canLogical_T_5 & 30'h1A311000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canLogical_T_7 = _a_canLogical_T_6; // @[Parameters.scala:137:46] wire _a_canLogical_T_8 = _a_canLogical_T_7 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _GEN_2 = nodeIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31] wire [28:0] _a_canLogical_T_9; // @[Parameters.scala:137:31] assign _a_canLogical_T_9 = _GEN_2; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_9; // @[Parameters.scala:137:31] assign _a_canArithmetic_T_9 = _GEN_2; // @[Parameters.scala:137:31] wire [29:0] _a_canLogical_T_10 = {1'h0, _a_canLogical_T_9}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canLogical_T_11 = _a_canLogical_T_10 & 30'h1A311000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canLogical_T_12 = _a_canLogical_T_11; // @[Parameters.scala:137:46] wire _a_canLogical_T_13 = _a_canLogical_T_12 == 30'h0; // @[Parameters.scala:137:{46,59}] wire _a_canLogical_T_14 = _a_canLogical_T_8 \| _a_canLogical_T_13; // @[Parameters.scala:685:42] wire _a_canLogical_T_15 = _a_canLogical_T_3 & _a_canLogical_T_14; // @[Parameters.scala:684:{29,54}, :685:42] wire _a_canLogical_T_69 = _a_canLogical_T_15; // @[Parameters.scala:684:54, :686:26] wire [29:0] _a_canLogical_T_18 = {1'h0, _a_canLogical_T_17}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canLogical_T_19 = _a_canLogical_T_18 & 30'h1A311000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canLogical_T_20 = _a_canLogical_T_19; // @[Parameters.scala:137:46] wire _a_canLogical_T_21 = _a_canLogical_T_20 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _GEN_3 = {nodeIn_a_bits_address[28:17], nodeIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31] wire [28:0] _a_canLogical_T_22; // @[Parameters.scala:137:31] assign _a_canLogical_T_22 = _GEN_3; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_22; // @[Parameters.scala:137:31] assign _a_canArithmetic_T_22 = _GEN_3; // @[Parameters.scala:137:31] wire [29:0] _a_canLogical_T_23 = {1'h0, _a_canLogical_T_22}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canLogical_T_24 = _a_canLogical_T_23 & 30'h1A310000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canLogical_T_25 = _a_canLogical_T_24; // @[Parameters.scala:137:46] wire _a_canLogical_T_26 = _a_canLogical_T_25 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _GEN_4 = {nodeIn_a_bits_address[28:21], nodeIn_a_bits_address[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31] wire [28:0] _a_canLogical_T_27; // @[Parameters.scala:137:31] assign _a_canLogical_T_27 = _GEN_4; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_27; // @[Parameters.scala:137:31] assign _a_canArithmetic_T_27 = _GEN_4; // @[Parameters.scala:137:31] wire [29:0] _a_canLogical_T_28 = {1'h0, _a_canLogical_T_27}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canLogical_T_29 = _a_canLogical_T_28 & 30'h1A301000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canLogical_T_30 = _a_canLogical_T_29; // @[Parameters.scala:137:46] wire _a_canLogical_T_31 = _a_canLogical_T_30 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _GEN_5 = {nodeIn_a_bits_address[28:22], nodeIn_a_bits_address[21:0] ^ 22'h300000}; // @[Parameters.scala:137:31] wire [28:0] _a_canLogical_T_32; // @[Parameters.scala:137:31] assign _a_canLogical_T_32 = _GEN_5; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_32; // @[Parameters.scala:137:31] assign _a_canArithmetic_T_32 = _GEN_5; // @[Parameters.scala:137:31] wire [29:0] _a_canLogical_T_33 = {1'h0, _a_canLogical_T_32}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canLogical_T_34 = _a_canLogical_T_33 & 30'h1A310000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canLogical_T_35 = _a_canLogical_T_34; // @[Parameters.scala:137:46] wire _a_canLogical_T_36 = _a_canLogical_T_35 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _GEN_6 = {nodeIn_a_bits_address[28:26], nodeIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31] wire [28:0] _a_canLogical_T_37; // @[Parameters.scala:137:31] assign _a_canLogical_T_37 = _GEN_6; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_37; // @[Parameters.scala:137:31] assign _a_canArithmetic_T_37 = _GEN_6; // @[Parameters.scala:137:31] wire [29:0] _a_canLogical_T_38 = {1'h0, _a_canLogical_T_37}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canLogical_T_39 = _a_canLogical_T_38 & 30'h1A310000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canLogical_T_40 = _a_canLogical_T_39; // @[Parameters.scala:137:46] wire _a_canLogical_T_41 = _a_canLogical_T_40 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _GEN_7 = {nodeIn_a_bits_address[28:26], nodeIn_a_bits_address[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31] wire [28:0] _a_canLogical_T_42; // @[Parameters.scala:137:31] assign _a_canLogical_T_42 = _GEN_7; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_42; // @[Parameters.scala:137:31] assign _a_canArithmetic_T_42 = _GEN_7; // @[Parameters.scala:137:31] wire [29:0] _a_canLogical_T_43 = {1'h0, _a_canLogical_T_42}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canLogical_T_44 = _a_canLogical_T_43 & 30'h1A311000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canLogical_T_45 = _a_canLogical_T_44; // @[Parameters.scala:137:46] wire _a_canLogical_T_46 = _a_canLogical_T_45 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _GEN_8 = {nodeIn_a_bits_address[28], nodeIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31] wire [28:0] _a_canLogical_T_47; // @[Parameters.scala:137:31] assign _a_canLogical_T_47 = _GEN_8; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_47; // @[Parameters.scala:137:31] assign _a_canArithmetic_T_47 = _GEN_8; // @[Parameters.scala:137:31] wire [29:0] _a_canLogical_T_48 = {1'h0, _a_canLogical_T_47}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canLogical_T_49 = _a_canLogical_T_48 & 30'h18000000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canLogical_T_50 = _a_canLogical_T_49; // @[Parameters.scala:137:46] wire _a_canLogical_T_51 = _a_canLogical_T_50 == 30'h0; // @[Parameters.scala:137:{46,59}] wire _a_canLogical_T_52 = _a_canLogical_T_21 \| _a_canLogical_T_26; // @[Parameters.scala:685:42] wire _a_canLogical_T_53 = _a_canLogical_T_52 \| _a_canLogical_T_31; // @[Parameters.scala:685:42] wire _a_canLogical_T_54 = _a_canLogical_T_53 \| _a_canLogical_T_36; // @[Parameters.scala:685:42] wire _a_canLogical_T_55 = _a_canLogical_T_54 \| _a_canLogical_T_41; // @[Parameters.scala:685:42] wire _a_canLogical_T_56 = _a_canLogical_T_55 \| _a_canLogical_T_46; // @[Parameters.scala:685:42] wire _a_canLogical_T_57 = _a_canLogical_T_56 \| _a_canLogical_T_51; // @[Parameters.scala:685:42] wire _a_canLogical_T_59 = \|(nodeIn_a_bits_size[3:1]); // @[Parameters.scala:92:28] wire _a_canLogical_T_61 = _a_canLogical_T_59 & _a_canLogical_T_60; // @[Parameters.scala:92:{28,33,38}] wire _a_canLogical_T_62 = _a_canLogical_T_61; // @[Parameters.scala:684:29] wire [28:0] _GEN_9 = {nodeIn_a_bits_address[28:22], nodeIn_a_bits_address[21:0] ^ 22'h200000}; // @[Parameters.scala:137:31] wire [28:0] _a_canLogical_T_63; // @[Parameters.scala:137:31] assign _a_canLogical_T_63 = _GEN_9; // @[Parameters.scala:137:31] wire [28:0] _a_canArithmetic_T_63; // @[Parameters.scala:137:31] assign _a_canArithmetic_T_63 = _GEN_9; // @[Parameters.scala:137:31] wire [29:0] _a_canLogical_T_64 = {1'h0, _a_canLogical_T_63}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canLogical_T_65 = _a_canLogical_T_64 & 30'h1A311000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canLogical_T_66 = _a_canLogical_T_65; // @[Parameters.scala:137:46] wire _a_canLogical_T_67 = _a_canLogical_T_66 == 30'h0; // @[Parameters.scala:137:{46,59}] wire _a_canLogical_T_68 = _a_canLogical_T_62 & _a_canLogical_T_67; // @[Parameters.scala:684:{29,54}] wire _a_canLogical_T_70 = _a_canLogical_T_69; // @[Parameters.scala:686:26] wire _a_canLogical_T_71 = _a_canLogical_T_70 \| _a_canLogical_T_68; // @[Parameters.scala:684:54, :686:26] wire a_canLogical = _a_canLogical_T_71; // @[Parameters.scala:686:26] wire _a_canArithmetic_T_2 = _a_canArithmetic_T_1; // @[Parameters.scala:92:{33,38}] wire _a_canArithmetic_T_3 = _a_canArithmetic_T_2; // @[Parameters.scala:684:29] wire [29:0] _a_canArithmetic_T_5 = {1'h0, _a_canArithmetic_T_4}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_6 = _a_canArithmetic_T_5 & 30'h1A311000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canArithmetic_T_7 = _a_canArithmetic_T_6; // @[Parameters.scala:137:46] wire _a_canArithmetic_T_8 = _a_canArithmetic_T_7 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [29:0] _a_canArithmetic_T_10 = {1'h0, _a_canArithmetic_T_9}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_11 = _a_canArithmetic_T_10 & 30'h1A311000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canArithmetic_T_12 = _a_canArithmetic_T_11; // @[Parameters.scala:137:46] wire _a_canArithmetic_T_13 = _a_canArithmetic_T_12 == 30'h0; // @[Parameters.scala:137:{46,59}] wire _a_canArithmetic_T_14 = _a_canArithmetic_T_8 \| _a_canArithmetic_T_13; // @[Parameters.scala:685:42] wire _a_canArithmetic_T_15 = _a_canArithmetic_T_3 & _a_canArithmetic_T_14; // @[Parameters.scala:684:{29,54}, :685:42] wire _a_canArithmetic_T_69 = _a_canArithmetic_T_15; // @[Parameters.scala:684:54, :686:26] wire [29:0] _a_canArithmetic_T_18 = {1'h0, _a_canArithmetic_T_17}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_19 = _a_canArithmetic_T_18 & 30'h1A311000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canArithmetic_T_20 = _a_canArithmetic_T_19; // @[Parameters.scala:137:46] wire _a_canArithmetic_T_21 = _a_canArithmetic_T_20 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [29:0] _a_canArithmetic_T_23 = {1'h0, _a_canArithmetic_T_22}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_24 = _a_canArithmetic_T_23 & 30'h1A310000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canArithmetic_T_25 = _a_canArithmetic_T_24; // @[Parameters.scala:137:46] wire _a_canArithmetic_T_26 = _a_canArithmetic_T_25 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [29:0] _a_canArithmetic_T_28 = {1'h0, _a_canArithmetic_T_27}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_29 = _a_canArithmetic_T_28 & 30'h1A301000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canArithmetic_T_30 = _a_canArithmetic_T_29; // @[Parameters.scala:137:46] wire _a_canArithmetic_T_31 = _a_canArithmetic_T_30 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [29:0] _a_canArithmetic_T_33 = {1'h0, _a_canArithmetic_T_32}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_34 = _a_canArithmetic_T_33 & 30'h1A310000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canArithmetic_T_35 = _a_canArithmetic_T_34; // @[Parameters.scala:137:46] wire _a_canArithmetic_T_36 = _a_canArithmetic_T_35 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [29:0] _a_canArithmetic_T_38 = {1'h0, _a_canArithmetic_T_37}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_39 = _a_canArithmetic_T_38 & 30'h1A310000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canArithmetic_T_40 = _a_canArithmetic_T_39; // @[Parameters.scala:137:46] wire _a_canArithmetic_T_41 = _a_canArithmetic_T_40 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [29:0] _a_canArithmetic_T_43 = {1'h0, _a_canArithmetic_T_42}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_44 = _a_canArithmetic_T_43 & 30'h1A311000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canArithmetic_T_45 = _a_canArithmetic_T_44; // @[Parameters.scala:137:46] wire _a_canArithmetic_T_46 = _a_canArithmetic_T_45 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [29:0] _a_canArithmetic_T_48 = {1'h0, _a_canArithmetic_T_47}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_49 = _a_canArithmetic_T_48 & 30'h18000000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canArithmetic_T_50 = _a_canArithmetic_T_49; // @[Parameters.scala:137:46] wire _a_canArithmetic_T_51 = _a_canArithmetic_T_50 == 30'h0; // @[Parameters.scala:137:{46,59}] wire _a_canArithmetic_T_52 = _a_canArithmetic_T_21 \| _a_canArithmetic_T_26; // @[Parameters.scala:685:42] wire _a_canArithmetic_T_53 = _a_canArithmetic_T_52 \| _a_canArithmetic_T_31; // @[Parameters.scala:685:42] wire _a_canArithmetic_T_54 = _a_canArithmetic_T_53 \| _a_canArithmetic_T_36; // @[Parameters.scala:685:42] wire _a_canArithmetic_T_55 = _a_canArithmetic_T_54 \| _a_canArithmetic_T_41; // @[Parameters.scala:685:42] wire _a_canArithmetic_T_56 = _a_canArithmetic_T_55 \| _a_canArithmetic_T_46; // @[Parameters.scala:685:42] wire _a_canArithmetic_T_57 = _a_canArithmetic_T_56 \| _a_canArithmetic_T_51; // @[Parameters.scala:685:42] wire _a_canArithmetic_T_59 = \|(nodeIn_a_bits_size[3:1]); // @[Parameters.scala:92:28] wire _a_canArithmetic_T_61 = _a_canArithmetic_T_59 & _a_canArithmetic_T_60; // @[Parameters.scala:92:{28,33,38}] wire _a_canArithmetic_T_62 = _a_canArithmetic_T_61; // @[Parameters.scala:684:29] wire [29:0] _a_canArithmetic_T_64 = {1'h0, _a_canArithmetic_T_63}; // @[Parameters.scala:137:{31,41}] wire [29:0] _a_canArithmetic_T_65 = _a_canArithmetic_T_64 & 30'h1A311000; // @[Parameters.scala:137:{41,46}] wire [29:0] _a_canArithmetic_T_66 = _a_canArithmetic_T_65; // @[Parameters.scala:137:46] wire _a_canArithmetic_T_67 = _a_canArithmetic_T_66 == 30'h0; // @[Parameters.scala:137:{46,59}] wire _a_canArithmetic_T_68 = _a_canArithmetic_T_62 & _a_canArithmetic_T_67; // @[Parameters.scala:684:{29,54}] wire _a_canArithmetic_T_70 = _a_canArithmetic_T_69; // @[Parameters.scala:686:26] wire _a_canArithmetic_T_71 = _a_canArithmetic_T_70 \| _a_canArithmetic_T_68; // @[Parameters.scala:684:54, :686:26] wire a_canArithmetic = _a_canArithmetic_T_71; // @[Parameters.scala:686:26] wire a_isLogical = nodeIn_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala:96:47] wire a_isArithmetic = nodeIn_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala:97:47] wire _a_isSupported_T = ~a_isArithmetic \| a_canArithmetic; // @[AtomicAutomata.scala:95:45, :97:47, :98:63] wire a_isSupported = a_isLogical ? a_canLogical : _a_isSupported_T; // @[AtomicAutomata.scala:94:45, :96:47, :98:{32,63}] wire [29:0] _a_fifoId_T_1 = {1'h0, _a_fifoId_T}; // @[Parameters.scala:137:{31,41}] wire _indexes_T = cam_a_0_bits_data[0]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_1 = cam_d_0_data[0]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_0 = {_indexes_T, _indexes_T_1}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_2 = cam_a_0_bits_data[1]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_3 = cam_d_0_data[1]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_1 = {_indexes_T_2, _indexes_T_3}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_4 = cam_a_0_bits_data[2]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_5 = cam_d_0_data[2]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_2 = {_indexes_T_4, _indexes_T_5}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_6 = cam_a_0_bits_data[3]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_7 = cam_d_0_data[3]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_3 = {_indexes_T_6, _indexes_T_7}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_8 = cam_a_0_bits_data[4]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_9 = cam_d_0_data[4]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_4 = {_indexes_T_8, _indexes_T_9}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_10 = cam_a_0_bits_data[5]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_11 = cam_d_0_data[5]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_5 = {_indexes_T_10, _indexes_T_11}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_12 = cam_a_0_bits_data[6]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_13 = cam_d_0_data[6]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_6 = {_indexes_T_12, _indexes_T_13}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_14 = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_15 = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_7 = {_indexes_T_14, _indexes_T_15}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_16 = cam_a_0_bits_data[8]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_17 = cam_d_0_data[8]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_8 = {_indexes_T_16, _indexes_T_17}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_18 = cam_a_0_bits_data[9]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_19 = cam_d_0_data[9]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_9 = {_indexes_T_18, _indexes_T_19}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_20 = cam_a_0_bits_data[10]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_21 = cam_d_0_data[10]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_10 = {_indexes_T_20, _indexes_T_21}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_22 = cam_a_0_bits_data[11]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_23 = cam_d_0_data[11]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_11 = {_indexes_T_22, _indexes_T_23}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_24 = cam_a_0_bits_data[12]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_25 = cam_d_0_data[12]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_12 = {_indexes_T_24, _indexes_T_25}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_26 = cam_a_0_bits_data[13]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_27 = cam_d_0_data[13]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_13 = {_indexes_T_26, _indexes_T_27}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_28 = cam_a_0_bits_data[14]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_29 = cam_d_0_data[14]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_14 = {_indexes_T_28, _indexes_T_29}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_30 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_1 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_31 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_1 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_15 = {_indexes_T_30, _indexes_T_31}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_32 = cam_a_0_bits_data[16]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_33 = cam_d_0_data[16]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_16 = {_indexes_T_32, _indexes_T_33}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_34 = cam_a_0_bits_data[17]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_35 = cam_d_0_data[17]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_17 = {_indexes_T_34, _indexes_T_35}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_36 = cam_a_0_bits_data[18]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_37 = cam_d_0_data[18]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_18 = {_indexes_T_36, _indexes_T_37}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_38 = cam_a_0_bits_data[19]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_39 = cam_d_0_data[19]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_19 = {_indexes_T_38, _indexes_T_39}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_40 = cam_a_0_bits_data[20]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_41 = cam_d_0_data[20]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_20 = {_indexes_T_40, _indexes_T_41}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_42 = cam_a_0_bits_data[21]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_43 = cam_d_0_data[21]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_21 = {_indexes_T_42, _indexes_T_43}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_44 = cam_a_0_bits_data[22]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_45 = cam_d_0_data[22]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_22 = {_indexes_T_44, _indexes_T_45}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_46 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_2 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_47 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_2 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_23 = {_indexes_T_46, _indexes_T_47}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_48 = cam_a_0_bits_data[24]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_49 = cam_d_0_data[24]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_24 = {_indexes_T_48, _indexes_T_49}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_50 = cam_a_0_bits_data[25]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_51 = cam_d_0_data[25]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_25 = {_indexes_T_50, _indexes_T_51}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_52 = cam_a_0_bits_data[26]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_53 = cam_d_0_data[26]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_26 = {_indexes_T_52, _indexes_T_53}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_54 = cam_a_0_bits_data[27]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_55 = cam_d_0_data[27]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_27 = {_indexes_T_54, _indexes_T_55}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_56 = cam_a_0_bits_data[28]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_57 = cam_d_0_data[28]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_28 = {_indexes_T_56, _indexes_T_57}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_58 = cam_a_0_bits_data[29]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_59 = cam_d_0_data[29]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_29 = {_indexes_T_58, _indexes_T_59}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_60 = cam_a_0_bits_data[30]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_61 = cam_d_0_data[30]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_30 = {_indexes_T_60, _indexes_T_61}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_62 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_3 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_63 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_3 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_31 = {_indexes_T_62, _indexes_T_63}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_64 = cam_a_0_bits_data[32]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_65 = cam_d_0_data[32]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_32 = {_indexes_T_64, _indexes_T_65}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_66 = cam_a_0_bits_data[33]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_67 = cam_d_0_data[33]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_33 = {_indexes_T_66, _indexes_T_67}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_68 = cam_a_0_bits_data[34]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_69 = cam_d_0_data[34]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_34 = {_indexes_T_68, _indexes_T_69}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_70 = cam_a_0_bits_data[35]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_71 = cam_d_0_data[35]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_35 = {_indexes_T_70, _indexes_T_71}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_72 = cam_a_0_bits_data[36]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_73 = cam_d_0_data[36]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_36 = {_indexes_T_72, _indexes_T_73}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_74 = cam_a_0_bits_data[37]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_75 = cam_d_0_data[37]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_37 = {_indexes_T_74, _indexes_T_75}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_76 = cam_a_0_bits_data[38]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_77 = cam_d_0_data[38]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_38 = {_indexes_T_76, _indexes_T_77}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_78 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_4 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_79 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_4 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_39 = {_indexes_T_78, _indexes_T_79}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_80 = cam_a_0_bits_data[40]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_81 = cam_d_0_data[40]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_40 = {_indexes_T_80, _indexes_T_81}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_82 = cam_a_0_bits_data[41]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_83 = cam_d_0_data[41]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_41 = {_indexes_T_82, _indexes_T_83}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_84 = cam_a_0_bits_data[42]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_85 = cam_d_0_data[42]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_42 = {_indexes_T_84, _indexes_T_85}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_86 = cam_a_0_bits_data[43]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_87 = cam_d_0_data[43]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_43 = {_indexes_T_86, _indexes_T_87}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_88 = cam_a_0_bits_data[44]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_89 = cam_d_0_data[44]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_44 = {_indexes_T_88, _indexes_T_89}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_90 = cam_a_0_bits_data[45]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_91 = cam_d_0_data[45]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_45 = {_indexes_T_90, _indexes_T_91}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_92 = cam_a_0_bits_data[46]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_93 = cam_d_0_data[46]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_46 = {_indexes_T_92, _indexes_T_93}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_94 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_5 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_95 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_5 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_47 = {_indexes_T_94, _indexes_T_95}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_96 = cam_a_0_bits_data[48]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_97 = cam_d_0_data[48]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_48 = {_indexes_T_96, _indexes_T_97}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_98 = cam_a_0_bits_data[49]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_99 = cam_d_0_data[49]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_49 = {_indexes_T_98, _indexes_T_99}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_100 = cam_a_0_bits_data[50]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_101 = cam_d_0_data[50]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_50 = {_indexes_T_100, _indexes_T_101}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_102 = cam_a_0_bits_data[51]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_103 = cam_d_0_data[51]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_51 = {_indexes_T_102, _indexes_T_103}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_104 = cam_a_0_bits_data[52]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_105 = cam_d_0_data[52]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_52 = {_indexes_T_104, _indexes_T_105}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_106 = cam_a_0_bits_data[53]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_107 = cam_d_0_data[53]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_53 = {_indexes_T_106, _indexes_T_107}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_108 = cam_a_0_bits_data[54]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_109 = cam_d_0_data[54]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_54 = {_indexes_T_108, _indexes_T_109}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_110 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_6 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_111 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_6 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_55 = {_indexes_T_110, _indexes_T_111}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_112 = cam_a_0_bits_data[56]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_113 = cam_d_0_data[56]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_56 = {_indexes_T_112, _indexes_T_113}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_114 = cam_a_0_bits_data[57]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_115 = cam_d_0_data[57]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_57 = {_indexes_T_114, _indexes_T_115}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_116 = cam_a_0_bits_data[58]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_117 = cam_d_0_data[58]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_58 = {_indexes_T_116, _indexes_T_117}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_118 = cam_a_0_bits_data[59]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_119 = cam_d_0_data[59]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_59 = {_indexes_T_118, _indexes_T_119}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_120 = cam_a_0_bits_data[60]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_121 = cam_d_0_data[60]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_60 = {_indexes_T_120, _indexes_T_121}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_122 = cam_a_0_bits_data[61]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_123 = cam_d_0_data[61]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_61 = {_indexes_T_122, _indexes_T_123}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_124 = cam_a_0_bits_data[62]; // @[AtomicAutomata.scala:83:24, :119:63] wire _indexes_T_125 = cam_d_0_data[62]; // @[AtomicAutomata.scala:84:24, :119:73] wire [1:0] indexes_62 = {_indexes_T_124, _indexes_T_125}; // @[AtomicAutomata.scala:119:{59,63,73}] wire _indexes_T_126 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63] wire _signbits_a_T_7 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64] wire _indexes_T_127 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73] wire _signbits_d_T_7 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64] wire [1:0] indexes_63 = {_indexes_T_126, _indexes_T_127}; // @[AtomicAutomata.scala:119:{59,63,73}] wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_1 = _logic_out_T[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_3 = _logic_out_T_2[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_5 = _logic_out_T_4[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_7 = _logic_out_T_6[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_9 = _logic_out_T_8[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_11 = _logic_out_T_10[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_13 = _logic_out_T_12[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_15 = _logic_out_T_14[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_17 = _logic_out_T_16[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_19 = _logic_out_T_18[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_21 = _logic_out_T_20[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_23 = _logic_out_T_22[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_25 = _logic_out_T_24[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_27 = _logic_out_T_26[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_29 = _logic_out_T_28[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_31 = _logic_out_T_30[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_33 = _logic_out_T_32[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_35 = _logic_out_T_34[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_37 = _logic_out_T_36[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_39 = _logic_out_T_38[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_41 = _logic_out_T_40[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_43 = _logic_out_T_42[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_45 = _logic_out_T_44[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_47 = _logic_out_T_46[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_49 = _logic_out_T_48[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_51 = _logic_out_T_50[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_53 = _logic_out_T_52[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_55 = _logic_out_T_54[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_57 = _logic_out_T_56[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_59 = _logic_out_T_58[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_61 = _logic_out_T_60[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_63 = _logic_out_T_62[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_65 = _logic_out_T_64[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_67 = _logic_out_T_66[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_69 = _logic_out_T_68[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_71 = _logic_out_T_70[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_73 = _logic_out_T_72[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_75 = _logic_out_T_74[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_77 = _logic_out_T_76[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_79 = _logic_out_T_78[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_81 = _logic_out_T_80[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_83 = _logic_out_T_82[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_85 = _logic_out_T_84[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_87 = _logic_out_T_86[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_89 = _logic_out_T_88[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_91 = _logic_out_T_90[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_93 = _logic_out_T_92[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_95 = _logic_out_T_94[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_97 = _logic_out_T_96[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_99 = _logic_out_T_98[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_101 = _logic_out_T_100[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_103 = _logic_out_T_102[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_105 = _logic_out_T_104[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_107 = _logic_out_T_106[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_109 = _logic_out_T_108[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_111 = _logic_out_T_110[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_113 = _logic_out_T_112[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_115 = _logic_out_T_114[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_117 = _logic_out_T_116[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_119 = _logic_out_T_118[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_121 = _logic_out_T_120[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_123 = _logic_out_T_122[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_125 = _logic_out_T_124[0]; // @[AtomicAutomata.scala:120:57] wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala:83:24, :119:59, :120:57] wire _logic_out_T_127 = _logic_out_T_126[0]; // @[AtomicAutomata.scala:120:57] wire [1:0] logic_out_lo_lo_lo_lo_lo = {_logic_out_T_3, _logic_out_T_1}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_lo_lo_hi = {_logic_out_T_7, _logic_out_T_5}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_lo_lo = {logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_lo_hi_lo = {_logic_out_T_11, _logic_out_T_9}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_lo_hi_hi = {_logic_out_T_15, _logic_out_T_13}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_lo_hi = {logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_lo_lo = {logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_hi_lo_lo = {_logic_out_T_19, _logic_out_T_17}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_hi_lo_hi = {_logic_out_T_23, _logic_out_T_21}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_hi_lo = {logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_lo_hi_hi_lo = {_logic_out_T_27, _logic_out_T_25}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_lo_hi_hi_hi = {_logic_out_T_31, _logic_out_T_29}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_lo_hi_hi = {logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_lo_hi = {logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_lo_lo = {logic_out_lo_lo_hi, logic_out_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_lo_lo_lo = {_logic_out_T_35, _logic_out_T_33}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_lo_lo_hi = {_logic_out_T_39, _logic_out_T_37}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_lo_lo = {logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_lo_hi_lo = {_logic_out_T_43, _logic_out_T_41}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_lo_hi_hi = {_logic_out_T_47, _logic_out_T_45}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_lo_hi = {logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_hi_lo = {logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_hi_lo_lo = {_logic_out_T_51, _logic_out_T_49}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_hi_lo_hi = {_logic_out_T_55, _logic_out_T_53}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_hi_lo = {logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_lo_hi_hi_hi_lo = {_logic_out_T_59, _logic_out_T_57}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_lo_hi_hi_hi_hi = {_logic_out_T_63, _logic_out_T_61}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_lo_hi_hi_hi = {logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_lo_hi_hi = {logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_lo_hi = {logic_out_lo_hi_hi, logic_out_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [31:0] logic_out_lo = {logic_out_lo_hi, logic_out_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_lo_lo_lo = {_logic_out_T_67, _logic_out_T_65}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_lo_lo_hi = {_logic_out_T_71, _logic_out_T_69}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_lo_lo = {logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_lo_hi_lo = {_logic_out_T_75, _logic_out_T_73}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_lo_hi_hi = {_logic_out_T_79, _logic_out_T_77}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_lo_hi = {logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_lo_lo = {logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_hi_lo_lo = {_logic_out_T_83, _logic_out_T_81}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_hi_lo_hi = {_logic_out_T_87, _logic_out_T_85}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_hi_lo = {logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_lo_hi_hi_lo = {_logic_out_T_91, _logic_out_T_89}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_lo_hi_hi_hi = {_logic_out_T_95, _logic_out_T_93}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_lo_hi_hi = {logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_lo_hi = {logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_hi_lo = {logic_out_hi_lo_hi, logic_out_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_lo_lo_lo = {_logic_out_T_99, _logic_out_T_97}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_lo_lo_hi = {_logic_out_T_103, _logic_out_T_101}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_lo_lo = {logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_lo_hi_lo = {_logic_out_T_107, _logic_out_T_105}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_lo_hi_hi = {_logic_out_T_111, _logic_out_T_109}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_lo_hi = {logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_hi_lo = {logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_hi_lo_lo = {_logic_out_T_115, _logic_out_T_113}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_hi_lo_hi = {_logic_out_T_119, _logic_out_T_117}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_hi_lo = {logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28] wire [1:0] logic_out_hi_hi_hi_hi_lo = {_logic_out_T_123, _logic_out_T_121}; // @[AtomicAutomata.scala:120:{28,57}] wire [1:0] logic_out_hi_hi_hi_hi_hi = {_logic_out_T_127, _logic_out_T_125}; // @[AtomicAutomata.scala:120:{28,57}] wire [3:0] logic_out_hi_hi_hi_hi = {logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [7:0] logic_out_hi_hi_hi = {logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [15:0] logic_out_hi_hi = {logic_out_hi_hi_hi, logic_out_hi_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [31:0] logic_out_hi = {logic_out_hi_hi, logic_out_hi_lo}; // @[AtomicAutomata.scala:120:28] wire [63:0] logic_out = {logic_out_hi, logic_out_lo}; // @[AtomicAutomata.scala:120:28] wire unsigned_0 = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala:83:24, :123:42] wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala:83:24, :124:42] wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala:83:24, :125:39] wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24, :127:25] wire [6:0] _signSel_T_1 = cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:39] wire [7:0] _signSel_T_2 = {_signSel_T[7], _signSel_T[6:0] \| _signSel_T_1}; // @[AtomicAutomata.scala:127:{25,31,39}] wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala:127:{23,31}] wire [1:0] signbits_a_lo_lo = {_signbits_a_T_1, _signbits_a_T}; // @[AtomicAutomata.scala:128:{29,64}] wire [1:0] signbits_a_lo_hi = {_signbits_a_T_3, _signbits_a_T_2}; // @[AtomicAutomata.scala:128:{29,64}] wire [3:0] signbits_a_lo = {signbits_a_lo_hi, signbits_a_lo_lo}; // @[AtomicAutomata.scala:128:29] wire [1:0] signbits_a_hi_lo = {_signbits_a_T_5, _signbits_a_T_4}; // @[AtomicAutomata.scala:128:{29,64}] wire [1:0] signbits_a_hi_hi = {_signbits_a_T_7, _signbits_a_T_6}; // @[AtomicAutomata.scala:128:{29,64}] wire [3:0] signbits_a_hi = {signbits_a_hi_hi, signbits_a_hi_lo}; // @[AtomicAutomata.scala:128:29] wire [7:0] signbits_a = {signbits_a_hi, signbits_a_lo}; // @[AtomicAutomata.scala:128:29] wire [1:0] signbits_d_lo_lo = {_signbits_d_T_1, _signbits_d_T}; // @[AtomicAutomata.scala:129:{29,64}] wire [1:0] signbits_d_lo_hi = {_signbits_d_T_3, _signbits_d_T_2}; // @[AtomicAutomata.scala:129:{29,64}] wire [3:0] signbits_d_lo = {signbits_d_lo_hi, signbits_d_lo_lo}; // @[AtomicAutomata.scala:129:29] wire [1:0] signbits_d_hi_lo = {_signbits_d_T_5, _signbits_d_T_4}; // @[AtomicAutomata.scala:129:{29,64}] wire [1:0] signbits_d_hi_hi = {_signbits_d_T_7, _signbits_d_T_6}; // @[AtomicAutomata.scala:129:{29,64}] wire [3:0] signbits_d_hi = {signbits_d_hi_hi, signbits_d_hi_lo}; // @[AtomicAutomata.scala:129:29] wire [7:0] signbits_d = {signbits_d_hi, signbits_d_lo}; // @[AtomicAutomata.scala:129:29] wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala:127:23, :128:29, :131:38] wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala:131:{38,49}] wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala:131:{49,54}] wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala:127:23, :129:29, :132:38] wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala:132:{38,49}] wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala:132:{49,54}] wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala:253:48] wire [7:0] _signext_a_T_1 = _signext_a_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_2 = signbit_a \| _signext_a_T_1; // @[package.scala:253:{43,53}] wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_a_T_4 = _signext_a_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_5 = _signext_a_T_2 \| _signext_a_T_4; // @[package.scala:253:{43,53}] wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_a_T_7 = _signext_a_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_a_T_8 = _signext_a_T_5 \| _signext_a_T_7; // @[package.scala:253:{43,53}] wire [7:0] _signext_a_T_9 = _signext_a_T_8; // @[package.scala:253:43, :254:17] wire _signext_a_T_10 = _signext_a_T_9[0]; // @[package.scala:254:17] wire _signext_a_T_11 = _signext_a_T_9[1]; // @[package.scala:254:17] wire _signext_a_T_12 = _signext_a_T_9[2]; // @[package.scala:254:17] wire _signext_a_T_13 = _signext_a_T_9[3]; // @[package.scala:254:17] wire _signext_a_T_14 = _signext_a_T_9[4]; // @[package.scala:254:17] wire _signext_a_T_15 = _signext_a_T_9[5]; // @[package.scala:254:17] wire _signext_a_T_16 = _signext_a_T_9[6]; // @[package.scala:254:17] wire _signext_a_T_17 = _signext_a_T_9[7]; // @[package.scala:254:17] wire [7:0] _signext_a_T_18 = {8{_signext_a_T_10}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_19 = {8{_signext_a_T_11}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_20 = {8{_signext_a_T_12}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_21 = {8{_signext_a_T_13}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_22 = {8{_signext_a_T_14}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_23 = {8{_signext_a_T_15}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_24 = {8{_signext_a_T_16}}; // @[AtomicAutomata.scala:133:40] wire [7:0] _signext_a_T_25 = {8{_signext_a_T_17}}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_lo_lo = {_signext_a_T_19, _signext_a_T_18}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_lo_hi = {_signext_a_T_21, _signext_a_T_20}; // @[AtomicAutomata.scala:133:40] wire [31:0] signext_a_lo = {signext_a_lo_hi, signext_a_lo_lo}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_hi_lo = {_signext_a_T_23, _signext_a_T_22}; // @[AtomicAutomata.scala:133:40] wire [15:0] signext_a_hi_hi = {_signext_a_T_25, _signext_a_T_24}; // @[AtomicAutomata.scala:133:40] wire [31:0] signext_a_hi = {signext_a_hi_hi, signext_a_hi_lo}; // @[AtomicAutomata.scala:133:40] wire [63:0] signext_a = {signext_a_hi, signext_a_lo}; // @[AtomicAutomata.scala:133:40] wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala:253:48] wire [7:0] _signext_d_T_1 = _signext_d_T[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_2 = signbit_d \| _signext_d_T_1; // @[package.scala:253:{43,53}] wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_d_T_4 = _signext_d_T_3[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_5 = _signext_d_T_2 \| _signext_d_T_4; // @[package.scala:253:{43,53}] wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [7:0] _signext_d_T_7 = _signext_d_T_6[7:0]; // @[package.scala:253:{48,53}] wire [7:0] _signext_d_T_8 = _signext_d_T_5 \| _signext_d_T_7; // @[package.scala:253:{43,53}] wire [7:0] _signext_d_T_9 = _signext_d_T_8; // @[package.scala:253:43, :254:17] wire _signext_d_T_10 = _signext_d_T_9[0]; // @[package.scala:254:17] wire _signext_d_T_11 = _signext_d_T_9[1]; // @[package.scala:254:17] wire _signext_d_T_12 = _signext_d_T_9[2]; // @[package.scala:254:17] wire _signext_d_T_13 = _signext_d_T_9[3]; // @[package.scala:254:17] wire _signext_d_T_14 = _signext_d_T_9[4]; // @[package.scala:254:17] wire _signext_d_T_15 = _signext_d_T_9[5]; // @[package.scala:254:17] wire _signext_d_T_16 = _signext_d_T_9[6]; // @[package.scala:254:17] wire _signext_d_T_17 = _signext_d_T_9[7]; // @[package.scala:254:17] wire [7:0] _signext_d_T_18 = {8{_signext_d_T_10}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_19 = {8{_signext_d_T_11}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_20 = {8{_signext_d_T_12}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_21 = {8{_signext_d_T_13}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_22 = {8{_signext_d_T_14}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_23 = {8{_signext_d_T_15}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_24 = {8{_signext_d_T_16}}; // @[AtomicAutomata.scala:134:40] wire [7:0] _signext_d_T_25 = {8{_signext_d_T_17}}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_lo_lo = {_signext_d_T_19, _signext_d_T_18}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_lo_hi = {_signext_d_T_21, _signext_d_T_20}; // @[AtomicAutomata.scala:134:40] wire [31:0] signext_d_lo = {signext_d_lo_hi, signext_d_lo_lo}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_hi_lo = {_signext_d_T_23, _signext_d_T_22}; // @[AtomicAutomata.scala:134:40] wire [15:0] signext_d_hi_hi = {_signext_d_T_25, _signext_d_T_24}; // @[AtomicAutomata.scala:134:40] wire [31:0] signext_d_hi = {signext_d_hi_hi, signext_d_hi_lo}; // @[AtomicAutomata.scala:134:40] wire [63:0] signext_d = {signext_d_hi, signext_d_lo}; // @[AtomicAutomata.scala:134:40] wire _wide_mask_T = cam_a_0_bits_mask[0]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_1 = cam_a_0_bits_mask[1]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_2 = cam_a_0_bits_mask[2]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_3 = cam_a_0_bits_mask[3]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_4 = cam_a_0_bits_mask[4]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_5 = cam_a_0_bits_mask[5]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_6 = cam_a_0_bits_mask[6]; // @[AtomicAutomata.scala:83:24, :136:40] wire _wide_mask_T_7 = cam_a_0_bits_mask[7]; // @[AtomicAutomata.scala:83:24, :136:40] wire [7:0] _wide_mask_T_8 = {8{_wide_mask_T}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_9 = {8{_wide_mask_T_1}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_10 = {8{_wide_mask_T_2}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_11 = {8{_wide_mask_T_3}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_12 = {8{_wide_mask_T_4}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_13 = {8{_wide_mask_T_5}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_14 = {8{_wide_mask_T_6}}; // @[AtomicAutomata.scala:136:40] wire [7:0] _wide_mask_T_15 = {8{_wide_mask_T_7}}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_lo_lo = {_wide_mask_T_9, _wide_mask_T_8}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_lo_hi = {_wide_mask_T_11, _wide_mask_T_10}; // @[AtomicAutomata.scala:136:40] wire [31:0] wide_mask_lo = {wide_mask_lo_hi, wide_mask_lo_lo}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_hi_lo = {_wide_mask_T_13, _wide_mask_T_12}; // @[AtomicAutomata.scala:136:40] wire [15:0] wide_mask_hi_hi = {_wide_mask_T_15, _wide_mask_T_14}; // @[AtomicAutomata.scala:136:40] wire [31:0] wide_mask_hi = {wide_mask_hi_hi, wide_mask_hi_lo}; // @[AtomicAutomata.scala:136:40] wire [63:0] wide_mask = {wide_mask_hi, wide_mask_lo}; // @[AtomicAutomata.scala:136:40] wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala:83:24, :136:40, :137:28] wire [63:0] a_a_ext = _a_a_ext_T \| signext_a; // @[AtomicAutomata.scala:133:40, :137:{28,41}] wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala:84:24, :136:40, :138:28] wire [63:0] a_d_ext = _a_d_ext_T \| signext_d; // @[AtomicAutomata.scala:134:40, :138:{28,41}] wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala:138:41, :139:43] wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala:125:39, :138:41, :139:{26,43}] wire [64:0] _adder_out_T = {1'h0, a_a_ext} + {1'h0, a_d_inv}; // @[AtomicAutomata.scala:137:41, :139:26, :140:33] wire [63:0] adder_out = _adder_out_T[63:0]; // @[AtomicAutomata.scala:140:33] wire _a_bigger_uneq_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49] wire _a_bigger_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49, :143:35] wire a_bigger_uneq = unsigned_0 == _a_bigger_uneq_T; // @[AtomicAutomata.scala:123:42, :142:{38,49}] wire _a_bigger_T_1 = a_d_ext[63]; // @[AtomicAutomata.scala:138:41, :143:50] wire _a_bigger_T_2 = _a_bigger_T == _a_bigger_T_1; // @[AtomicAutomata.scala:143:{35,39,50}] wire _a_bigger_T_3 = adder_out[63]; // @[AtomicAutomata.scala:140:33, :143:65] wire _a_bigger_T_4 = ~_a_bigger_T_3; // @[AtomicAutomata.scala:143:{55,65}] wire a_bigger = _a_bigger_T_2 ? _a_bigger_T_4 : a_bigger_uneq; // @[AtomicAutomata.scala:142:38, :143:{27,39,55}] wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala:124:42, :143:27, :144:31] wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala:83:24, :84:24, :144:31, :145:50] wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala:125:39, :140:33, :145:{28,50}] wire _amo_data_T = cam_a_0_bits_opcode[0]; // @[AtomicAutomata.scala:83:24, :151:34] wire [63:0] amo_data = _amo_data_T ? logic_out : arith_out; // @[AtomicAutomata.scala:120:28, :145:28, :151:{14,34}] wire [63:0] source_c_bits_a_data = amo_data; // @[Edges.scala:480:17] wire _source_i_ready_T; // @[Arbiter.scala:94:31] wire _source_i_valid_T; // @[AtomicAutomata.scala:157:38] wire [2:0] source_i_bits_opcode; // @[AtomicAutomata.scala:154:28] wire [2:0] source_i_bits_param; // @[AtomicAutomata.scala:154:28] wire source_i_ready; // @[AtomicAutomata.scala:154:28] wire source_i_valid; // @[AtomicAutomata.scala:154:28] wire _a_allow_T = ~a_cam_busy; // @[AtomicAutomata.scala:111:96, :155:23] wire _a_allow_T_1 = a_isSupported \| cam_free_0; // @[AtomicAutomata.scala:86:44, :98:32, :155:53] wire a_allow = _a_allow_T & _a_allow_T_1; // @[AtomicAutomata.scala:155:{23,35,53}] assign _nodeIn_a_ready_T = source_i_ready & a_allow; // @[AtomicAutomata.scala:154:28, :155:35, :156:38] assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38] assign _source_i_valid_T = nodeIn_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38] assign source_i_valid = _source_i_valid_T; // @[AtomicAutomata.scala:154:28, :157:38] assign source_i_bits_opcode = a_isSupported ? nodeIn_a_bits_opcode : 3'h4; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :160:32] assign source_i_bits_param = a_isSupported ? nodeIn_a_bits_param : 3'h0; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :161:32] wire _source_c_ready_T; // @[Arbiter.scala:94:31] wire [7:0] source_c_bits_a_mask; // @[Edges.scala:480:17] wire source_c_bits_a_corrupt; // @[Edges.scala:480:17] wire [3:0] source_c_bits_size; // @[AtomicAutomata.scala:165:28] wire [6:0] source_c_bits_source; // @[AtomicAutomata.scala:165:28] wire [28:0] source_c_bits_address; // @[AtomicAutomata.scala:165:28] wire [7:0] source_c_bits_mask; // @[AtomicAutomata.scala:165:28] wire [63:0] source_c_bits_data; // @[AtomicAutomata.scala:165:28] wire source_c_bits_corrupt; // @[AtomicAutomata.scala:165:28] wire source_c_ready; // @[AtomicAutomata.scala:165:28] wire _source_c_bits_T = cam_a_0_bits_corrupt \| cam_d_0_corrupt; // @[AtomicAutomata.scala:83:24, :84:24, :172:45] assign source_c_bits_a_corrupt = _source_c_bits_T; // @[Edges.scala:480:17] wire _source_c_bits_legal_T_1 = cam_a_0_bits_size < 4'hD; // @[AtomicAutomata.scala:83:24] wire _source_c_bits_legal_T_2 = _source_c_bits_legal_T_1; // @[Parameters.scala:92:{33,38}] wire _source_c_bits_legal_T_3 = _source_c_bits_legal_T_2; // @[Parameters.scala:684:29] wire [28:0] _source_c_bits_legal_T_4 = {cam_a_0_bits_address[28:14], cam_a_0_bits_address[13:0] ^ 14'h3000}; // @[AtomicAutomata.scala:83:24] wire [29:0] _source_c_bits_legal_T_5 = {1'h0, _source_c_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [29:0] _source_c_bits_legal_T_6 = _source_c_bits_legal_T_5 & 30'h1A313000; // @[Parameters.scala:137:{41,46}] wire [29:0] _source_c_bits_legal_T_7 = _source_c_bits_legal_T_6; // @[Parameters.scala:137:46] wire _source_c_bits_legal_T_8 = _source_c_bits_legal_T_7 == 30'h0; // @[Parameters.scala:137:{46,59}] wire _source_c_bits_legal_T_9 = _source_c_bits_legal_T_3 & _source_c_bits_legal_T_8; // @[Parameters.scala:684:{29,54}] wire _source_c_bits_legal_T_69 = _source_c_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire _source_c_bits_legal_T_11 = cam_a_0_bits_size < 4'h7; // @[AtomicAutomata.scala:83:24] wire _source_c_bits_legal_T_12 = _source_c_bits_legal_T_11; // @[Parameters.scala:92:{33,38}] wire _source_c_bits_legal_T_13 = _source_c_bits_legal_T_12; // @[Parameters.scala:684:29] wire [29:0] _source_c_bits_legal_T_15 = {1'h0, _source_c_bits_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [29:0] _source_c_bits_legal_T_16 = _source_c_bits_legal_T_15 & 30'h1A312000; // @[Parameters.scala:137:{41,46}] wire [29:0] _source_c_bits_legal_T_17 = _source_c_bits_legal_T_16; // @[Parameters.scala:137:46] wire _source_c_bits_legal_T_18 = _source_c_bits_legal_T_17 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _source_c_bits_legal_T_19 = {cam_a_0_bits_address[28:21], cam_a_0_bits_address[20:0] ^ 21'h100000}; // @[AtomicAutomata.scala:83:24] wire [29:0] _source_c_bits_legal_T_20 = {1'h0, _source_c_bits_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [29:0] _source_c_bits_legal_T_21 = _source_c_bits_legal_T_20 & 30'h1A303000; // @[Parameters.scala:137:{41,46}] wire [29:0] _source_c_bits_legal_T_22 = _source_c_bits_legal_T_21; // @[Parameters.scala:137:46] wire _source_c_bits_legal_T_23 = _source_c_bits_legal_T_22 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _source_c_bits_legal_T_24 = {cam_a_0_bits_address[28:22], cam_a_0_bits_address[21:0] ^ 22'h200000}; // @[AtomicAutomata.scala:83:24] wire [29:0] _source_c_bits_legal_T_25 = {1'h0, _source_c_bits_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [29:0] _source_c_bits_legal_T_26 = _source_c_bits_legal_T_25 & 30'h1A313000; // @[Parameters.scala:137:{41,46}] wire [29:0] _source_c_bits_legal_T_27 = _source_c_bits_legal_T_26; // @[Parameters.scala:137:46] wire _source_c_bits_legal_T_28 = _source_c_bits_legal_T_27 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _source_c_bits_legal_T_29 = {cam_a_0_bits_address[28:22], cam_a_0_bits_address[21:0] ^ 22'h300000}; // @[AtomicAutomata.scala:83:24] wire [29:0] _source_c_bits_legal_T_30 = {1'h0, _source_c_bits_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [29:0] _source_c_bits_legal_T_31 = _source_c_bits_legal_T_30 & 30'h1A310000; // @[Parameters.scala:137:{41,46}] wire [29:0] _source_c_bits_legal_T_32 = _source_c_bits_legal_T_31; // @[Parameters.scala:137:46] wire _source_c_bits_legal_T_33 = _source_c_bits_legal_T_32 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _source_c_bits_legal_T_34 = {cam_a_0_bits_address[28:26], cam_a_0_bits_address[25:0] ^ 26'h2000000}; // @[AtomicAutomata.scala:83:24] wire [29:0] _source_c_bits_legal_T_35 = {1'h0, _source_c_bits_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [29:0] _source_c_bits_legal_T_36 = _source_c_bits_legal_T_35 & 30'h1A310000; // @[Parameters.scala:137:{41,46}] wire [29:0] _source_c_bits_legal_T_37 = _source_c_bits_legal_T_36; // @[Parameters.scala:137:46] wire _source_c_bits_legal_T_38 = _source_c_bits_legal_T_37 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _source_c_bits_legal_T_39 = {cam_a_0_bits_address[28:26], cam_a_0_bits_address[25:0] ^ 26'h2010000}; // @[AtomicAutomata.scala:83:24] wire [29:0] _source_c_bits_legal_T_40 = {1'h0, _source_c_bits_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [29:0] _source_c_bits_legal_T_41 = _source_c_bits_legal_T_40 & 30'h1A313000; // @[Parameters.scala:137:{41,46}] wire [29:0] _source_c_bits_legal_T_42 = _source_c_bits_legal_T_41; // @[Parameters.scala:137:46] wire _source_c_bits_legal_T_43 = _source_c_bits_legal_T_42 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _source_c_bits_legal_T_44 = {cam_a_0_bits_address[28], cam_a_0_bits_address[27:0] ^ 28'h8000000}; // @[AtomicAutomata.scala:83:24] wire [29:0] _source_c_bits_legal_T_45 = {1'h0, _source_c_bits_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [29:0] _source_c_bits_legal_T_46 = _source_c_bits_legal_T_45 & 30'h18000000; // @[Parameters.scala:137:{41,46}] wire [29:0] _source_c_bits_legal_T_47 = _source_c_bits_legal_T_46; // @[Parameters.scala:137:46] wire _source_c_bits_legal_T_48 = _source_c_bits_legal_T_47 == 30'h0; // @[Parameters.scala:137:{46,59}] wire [28:0] _source_c_bits_legal_T_49 = cam_a_0_bits_address ^ 29'h10000000; // @[AtomicAutomata.scala:83:24] wire [29:0] _source_c_bits_legal_T_50 = {1'h0, _source_c_bits_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [29:0] _source_c_bits_legal_T_51 = _source_c_bits_legal_T_50 & 30'h1A313000; // @[Parameters.scala:137:{41,46}] wire [29:0] _source_c_bits_legal_T_52 = _source_c_bits_legal_T_51; // @[Parameters.scala:137:46] wire _source_c_bits_legal_T_53 = _source_c_bits_legal_T_52 == 30'h0; // @[Parameters.scala:137:{46,59}] wire _source_c_bits_legal_T_54 = _source_c_bits_legal_T_18 \| _source_c_bits_legal_T_23; // @[Parameters.scala:685:42] wire _source_c_bits_legal_T_55 = _source_c_bits_legal_T_54 \| _source_c_bits_legal_T_28; // @[Parameters.scala:685:42] wire _source_c_bits_legal_T_56 = _source_c_bits_legal_T_55 \| _source_c_bits_legal_T_33; // @[Parameters.scala:685:42] wire _source_c_bits_legal_T_57 = _source_c_bits_legal_T_56 \| _source_c_bits_legal_T_38; // @[Parameters.scala:685:42] wire _source_c_bits_legal_T_58 = _source_c_bits_legal_T_57 \| _source_c_bits_legal_T_43; // @[Parameters.scala:685:42] wire _source_c_bits_legal_T_59 = _source_c_bits_legal_T_58 \| _source_c_bits_legal_T_48; // @[Parameters.scala:685:42] wire _source_c_bits_legal_T_60 = _source_c_bits_legal_T_59 \| _source_c_bits_legal_T_53; // @[Parameters.scala:685:42] wire _source_c_bits_legal_T_61 = _source_c_bits_legal_T_13 & _source_c_bits_legal_T_60; // @[Parameters.scala:684:{29,54}, :685:42] wire [28:0] _source_c_bits_legal_T_63 = {cam_a_0_bits_address[28:17], cam_a_0_bits_address[16:0] ^ 17'h10000}; // @[AtomicAutomata.scala:83:24] wire [29:0] _source_c_bits_legal_T_64 = {1'h0, _source_c_bits_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [29:0] _source_c_bits_legal_T_65 = _source_c_bits_legal_T_64 & 30'h1A310000; // @[Parameters.scala:137:{41,46}] wire [29:0] _source_c_bits_legal_T_66 = _source_c_bits_legal_T_65; // @[Parameters.scala:137:46] wire _source_c_bits_legal_T_67 = _source_c_bits_legal_T_66 == 30'h0; // @[Parameters.scala:137:{46,59}] wire _source_c_bits_legal_T_70 = _source_c_bits_legal_T_69 \| _source_c_bits_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire source_c_bits_legal = _source_c_bits_legal_T_70; // @[Parameters.scala:686:26] assign source_c_bits_size = source_c_bits_a_size; // @[Edges.scala:480:17] assign source_c_bits_source = source_c_bits_a_source; // @[Edges.scala:480:17] assign source_c_bits_address = source_c_bits_a_address; // @[Edges.scala:480:17] wire [7:0] _source_c_bits_a_mask_T; // @[Misc.scala:222:10] assign source_c_bits_mask = source_c_bits_a_mask; // @[Edges.scala:480:17] assign source_c_bits_data = source_c_bits_a_data; // @[Edges.scala:480:17] assign source_c_bits_corrupt = source_c_bits_a_corrupt; // @[Edges.scala:480:17] wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = _source_c_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _source_c_bits_a_mask_sizeOH_T_2 = _source_c_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] source_c_bits_a_mask_sizeOH = {_source_c_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 4'h2; // @[Misc.scala:206:21] wire source_c_bits_a_mask_sub_sub_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_sub_sub_bit = cam_a_0_bits_address[2]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_sub_sub_1_2 = source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire source_c_bits_a_mask_sub_sub_nbit = ~source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_sub_sub_0_2 = source_c_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_sub_acc_T = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 \| _source_c_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _source_c_bits_a_mask_sub_sub_acc_T_1 = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 \| _source_c_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire source_c_bits_a_mask_sub_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_sub_bit = cam_a_0_bits_address[1]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_sub_nbit = ~source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_sub_0_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_acc_T = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 \| _source_c_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_1_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_sub_acc_T_1 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 \| _source_c_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_2_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_sub_acc_T_2 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 \| _source_c_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_sub_3_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_sub_acc_T_3 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 \| _source_c_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire source_c_bits_a_mask_bit = cam_a_0_bits_address[0]; // @[Misc.scala:210:26] wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire source_c_bits_a_mask_eq = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T = source_c_bits_a_mask_size & source_c_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc = source_c_bits_a_mask_sub_0_1 \| _source_c_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_1 = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_1 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_1 = source_c_bits_a_mask_sub_0_1 \| _source_c_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_2 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_sub_1_1 \| _source_c_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_3 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_sub_1_1 \| _source_c_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_4 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_sub_2_1 \| _source_c_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_5 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_sub_2_1 \| _source_c_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _source_c_bits_a_mask_acc_T_6 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_sub_3_1 \| _source_c_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _source_c_bits_a_mask_acc_T_7 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_sub_3_1 \| _source_c_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] source_c_bits_a_mask_lo_lo = {source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] source_c_bits_a_mask_lo_hi = {source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] source_c_bits_a_mask_lo = {source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] source_c_bits_a_mask_hi_lo = {source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] source_c_bits_a_mask_hi_hi = {source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] source_c_bits_a_mask_hi = {source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _source_c_bits_a_mask_T = {source_c_bits_a_mask_hi, source_c_bits_a_mask_lo}; // @[Misc.scala:222:10] assign source_c_bits_a_mask = _source_c_bits_a_mask_T; // @[Misc.scala:222:10] wire [26:0] _decode_T = 27'hFFF << nodeIn_a_bits_size; // @[package.scala:243:71] wire [11:0] _decode_T_1 = _decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] decode = _decode_T_2[11:3]; // @[package.scala:243:46] wire _opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire opdata = ~_opdata_T; // @[Edges.scala:92:{28,37}] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24] wire [1:0] _readys_T = {source_i_valid, source_c_valid}; // @[AtomicAutomata.scala:154:28, :165:28] wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_T_3 = _readys_T \| _readys_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17] wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17] wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}] wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & source_c_valid; // @[AtomicAutomata.scala:165:28] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & source_i_valid; // @[AtomicAutomata.scala:154:28] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _nodeOut_a_valid_T = source_c_valid \| source_i_valid; // @[AtomicAutomata.scala:154:28, :165:28]
Generate the Verilog code corresponding to this FIRRTL code module MSHR_4 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<9>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<9>(0h1e0)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<9>(0h1e0)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<9>(0h1e0)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_4( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [8:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [8:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [8:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [8:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [8:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [8:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [8:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [8:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 9'h1E0; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 9'h1E0; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [8:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 9'h1E0; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_15 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}} wire _in_flight_WIRE : UInt<1>[8] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) connect _in_flight_WIRE[3], UInt<1>(0h0) connect _in_flight_WIRE[4], UInt<1>(0h0) connect _in_flight_WIRE[5], UInt<1>(0h0) connect _in_flight_WIRE[6], UInt<1>(0h0) connect _in_flight_WIRE[7], UInt<1>(0h0) regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_38 = and(_T_36, _T_37) node _T_39 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_40 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_41 = and(_T_39, _T_40) node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_45 = and(_T_43, _T_44) node _T_46 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_47 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_50 = and(_T_48, _T_49) node _T_51 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_54 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_55 = and(_T_53, _T_54) node _T_56 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_57 = and(_T_55, _T_56) node _T_58 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_59 = and(_T_57, _T_58) node _T_60 = or(_T_17, _T_24) node _T_61 = or(_T_60, _T_31) node _T_62 = or(_T_61, _T_38) node _T_63 = or(_T_62, _T_45) node _T_64 = or(_T_63, _T_52) node _T_65 = or(_T_64, _T_59) node _T_66 = or(_T_10, _T_65) node _T_67 = asUInt(reset) node _T_68 = eq(_T_67, UInt<1>(0h0)) when _T_68 : node _T_69 = eq(_T_66, UInt<1>(0h0)) when _T_69 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_66, UInt<1>(0h1), "") : assert_2 node _T_70 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_71 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_72 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_73 = and(_T_71, _T_72) node _T_74 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_75 = and(_T_73, _T_74) node _T_76 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_77 = and(_T_75, _T_76) node _T_78 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_79 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_80 = and(_T_78, _T_79) node _T_81 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_84 = and(_T_82, _T_83) node _T_85 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_86 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_87 = and(_T_85, _T_86) node _T_88 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_89 = and(_T_87, _T_88) node _T_90 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_91 = and(_T_89, _T_90) node _T_92 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_93 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_98 = and(_T_96, _T_97) node _T_99 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_100 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_101 = and(_T_99, _T_100) node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_105 = and(_T_103, _T_104) node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_107 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_112 = and(_T_110, _T_111) node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_114 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_119 = and(_T_117, _T_118) node _T_120 = or(_T_77, _T_84) node _T_121 = or(_T_120, _T_91) node _T_122 = or(_T_121, _T_98) node _T_123 = or(_T_122, _T_105) node _T_124 = or(_T_123, _T_112) node _T_125 = or(_T_124, _T_119) node _T_126 = or(_T_70, _T_125) node _T_127 = asUInt(reset) node _T_128 = eq(_T_127, UInt<1>(0h0)) when _T_128 : node _T_129 = eq(_T_126, UInt<1>(0h0)) when _T_129 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_126, UInt<1>(0h1), "") : assert_3 node _T_130 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_131 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_132 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_137 = and(_T_135, _T_136) node _T_138 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_139 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_142 = and(_T_140, _T_141) node _T_143 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_144 = and(_T_142, _T_143) node _T_145 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_146 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_149 = and(_T_147, _T_148) node _T_150 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_151 = and(_T_149, _T_150) node _T_152 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_153 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_156 = and(_T_154, _T_155) node _T_157 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_158 = and(_T_156, _T_157) node _T_159 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_160 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_165 = and(_T_163, _T_164) node _T_166 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_167 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_170 = and(_T_168, _T_169) node _T_171 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_172 = and(_T_170, _T_171) node _T_173 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_174 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_177 = and(_T_175, _T_176) node _T_178 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_179 = and(_T_177, _T_178) node _T_180 = or(_T_137, _T_144) node _T_181 = or(_T_180, _T_151) node _T_182 = or(_T_181, _T_158) node _T_183 = or(_T_182, _T_165) node _T_184 = or(_T_183, _T_172) node _T_185 = or(_T_184, _T_179) node _T_186 = or(_T_130, _T_185) node _T_187 = asUInt(reset) node _T_188 = eq(_T_187, UInt<1>(0h0)) when _T_188 : node _T_189 = eq(_T_186, UInt<1>(0h0)) when _T_189 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4 assert(clock, _T_186, UInt<1>(0h1), "") : assert_4 node _T_190 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) node _T_191 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_192 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_193 = and(_T_191, _T_192) node _T_194 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_195 = and(_T_193, _T_194) node _T_196 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_199 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_204 = and(_T_202, _T_203) node _T_205 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_206 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_207 = and(_T_205, _T_206) node _T_208 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_211 = and(_T_209, _T_210) node _T_212 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_213 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_214 = and(_T_212, _T_213) node _T_215 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_216 = and(_T_214, _T_215) node _T_217 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_218 = and(_T_216, _T_217) node _T_219 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_220 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_221 = and(_T_219, _T_220) node _T_222 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_223 = and(_T_221, _T_222) node _T_224 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_225 = and(_T_223, _T_224) node _T_226 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_227 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_230 = and(_T_228, _T_229) node _T_231 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_232 = and(_T_230, _T_231) node _T_233 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_234 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_235 = and(_T_233, _T_234) node _T_236 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_237 = and(_T_235, _T_236) node _T_238 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_239 = and(_T_237, _T_238) node _T_240 = or(_T_197, _T_204) node _T_241 = or(_T_240, _T_211) node _T_242 = or(_T_241, _T_218) node _T_243 = or(_T_242, _T_225) node _T_244 = or(_T_243, _T_232) node _T_245 = or(_T_244, _T_239) node _T_246 = or(_T_190, _T_245) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5 assert(clock, _T_246, UInt<1>(0h1), "") : assert_5 node _T_250 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_252 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_253 = and(_T_251, _T_252) node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_255 = and(_T_253, _T_254) node _T_256 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_257 = and(_T_255, _T_256) node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_259 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_260 = and(_T_258, _T_259) node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_262 = and(_T_260, _T_261) node _T_263 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_266 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_267 = and(_T_265, _T_266) node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_269 = and(_T_267, _T_268) node _T_270 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_271 = and(_T_269, _T_270) node _T_272 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_273 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_276 = and(_T_274, _T_275) node _T_277 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_278 = and(_T_276, _T_277) node _T_279 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_280 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_281 = and(_T_279, _T_280) node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_285 = and(_T_283, _T_284) node _T_286 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_287 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_288 = and(_T_286, _T_287) node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_292 = and(_T_290, _T_291) node _T_293 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_294 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_295 = and(_T_293, _T_294) node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_297 = and(_T_295, _T_296) node _T_298 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_299 = and(_T_297, _T_298) node _T_300 = or(_T_257, _T_264) node _T_301 = or(_T_300, _T_271) node _T_302 = or(_T_301, _T_278) node _T_303 = or(_T_302, _T_285) node _T_304 = or(_T_303, _T_292) node _T_305 = or(_T_304, _T_299) node _T_306 = or(_T_250, _T_305) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6 assert(clock, _T_306, UInt<1>(0h1), "") : assert_6 node _T_310 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6)) node _T_311 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_312 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_313 = and(_T_311, _T_312) node _T_314 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_315 = and(_T_313, _T_314) node _T_316 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_317 = and(_T_315, _T_316) node _T_318 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_319 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_322 = and(_T_320, _T_321) node _T_323 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_326 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_329 = and(_T_327, _T_328) node _T_330 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_331 = and(_T_329, _T_330) node _T_332 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_333 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_336 = and(_T_334, _T_335) node _T_337 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_338 = and(_T_336, _T_337) node _T_339 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_340 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_341 = and(_T_339, _T_340) node _T_342 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_343 = and(_T_341, _T_342) node _T_344 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_345 = and(_T_343, _T_344) node _T_346 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_347 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_348 = and(_T_346, _T_347) node _T_349 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_350 = and(_T_348, _T_349) node _T_351 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_354 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_355 = and(_T_353, _T_354) node _T_356 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_357 = and(_T_355, _T_356) node _T_358 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_359 = and(_T_357, _T_358) node _T_360 = or(_T_317, _T_324) node _T_361 = or(_T_360, _T_331) node _T_362 = or(_T_361, _T_338) node _T_363 = or(_T_362, _T_345) node _T_364 = or(_T_363, _T_352) node _T_365 = or(_T_364, _T_359) node _T_366 = or(_T_310, _T_365) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7 assert(clock, _T_366, UInt<1>(0h1), "") : assert_7 node _T_370 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7)) node _T_371 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_372 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_373 = and(_T_371, _T_372) node _T_374 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_375 = and(_T_373, _T_374) node _T_376 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_377 = and(_T_375, _T_376) node _T_378 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_379 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_380 = and(_T_378, _T_379) node _T_381 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_382 = and(_T_380, _T_381) node _T_383 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_384 = and(_T_382, _T_383) node _T_385 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_386 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h4)) node _T_387 = and(_T_385, _T_386) node _T_388 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_389 = and(_T_387, _T_388) node _T_390 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_391 = and(_T_389, _T_390) node _T_392 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6)) node _T_393 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_394 = and(_T_392, _T_393) node _T_395 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_398 = and(_T_396, _T_397) node _T_399 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha)) node _T_400 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_401 = and(_T_399, _T_400) node _T_402 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_405 = and(_T_403, _T_404) node _T_406 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3)) node _T_407 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) node _T_408 = and(_T_406, _T_407) node _T_409 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_412 = and(_T_410, _T_411) node _T_413 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5)) node _T_414 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0)) node _T_415 = and(_T_413, _T_414) node _T_416 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_419 = and(_T_417, _T_418) node _T_420 = or(_T_377, _T_384) node _T_421 = or(_T_420, _T_391) node _T_422 = or(_T_421, _T_398) node _T_423 = or(_T_422, _T_405) node _T_424 = or(_T_423, _T_412) node _T_425 = or(_T_424, _T_419) node _T_426 = or(_T_370, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U \|\| v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8 assert(clock, _T_426, UInt<1>(0h1), "") : assert_8	module NoCMonitor_15( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] reg in_flight_3; // @[Monitor.scala:16:26] reg in_flight_4; // @[Monitor.scala:16:26] reg in_flight_5; // @[Monitor.scala:16:26] reg in_flight_6; // @[Monitor.scala:16:26] reg in_flight_7; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module TLMasterACDToNoC_6 : input clock : Clock input reset : Reset output io : { flip tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}}, flits : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}} invalidate io.tilelink.e.bits.sink invalidate io.tilelink.e.valid invalidate io.tilelink.e.ready invalidate io.tilelink.d.bits.corrupt invalidate io.tilelink.d.bits.data invalidate io.tilelink.d.bits.denied invalidate io.tilelink.d.bits.sink invalidate io.tilelink.d.bits.source invalidate io.tilelink.d.bits.size invalidate io.tilelink.d.bits.param invalidate io.tilelink.d.bits.opcode invalidate io.tilelink.d.valid invalidate io.tilelink.d.ready invalidate io.tilelink.c.bits.corrupt invalidate io.tilelink.c.bits.data invalidate io.tilelink.c.bits.address invalidate io.tilelink.c.bits.source invalidate io.tilelink.c.bits.size invalidate io.tilelink.c.bits.param invalidate io.tilelink.c.bits.opcode invalidate io.tilelink.c.valid invalidate io.tilelink.c.ready invalidate io.tilelink.b.bits.corrupt invalidate io.tilelink.b.bits.data invalidate io.tilelink.b.bits.mask invalidate io.tilelink.b.bits.address invalidate io.tilelink.b.bits.source invalidate io.tilelink.b.bits.size invalidate io.tilelink.b.bits.param invalidate io.tilelink.b.bits.opcode invalidate io.tilelink.b.valid invalidate io.tilelink.b.ready invalidate io.tilelink.a.bits.corrupt invalidate io.tilelink.a.bits.data invalidate io.tilelink.a.bits.mask invalidate io.tilelink.a.bits.address invalidate io.tilelink.a.bits.source invalidate io.tilelink.a.bits.size invalidate io.tilelink.a.bits.param invalidate io.tilelink.a.bits.opcode invalidate io.tilelink.a.valid invalidate io.tilelink.a.ready inst a of TLAToNoC_6 connect a.clock, clock connect a.reset, reset inst c of TLCToNoC_6 connect c.clock, clock connect c.reset, reset inst d of TLDFromNoC_6 connect d.clock, clock connect d.reset, reset connect a.io.protocol, io.tilelink.a connect c.io.protocol, io.tilelink.c connect io.tilelink.d.bits, d.io.protocol.bits connect io.tilelink.d.valid, d.io.protocol.valid connect d.io.protocol.ready, io.tilelink.d.ready connect io.flits.a.bits, a.io.flit.bits connect io.flits.a.valid, a.io.flit.valid connect a.io.flit.ready, io.flits.a.ready connect io.flits.c.bits, c.io.flit.bits connect io.flits.c.valid, c.io.flit.valid connect c.io.flit.ready, io.flits.c.ready connect d.io.flit, io.flits.d	module TLMasterACDToNoC_6( // @[Tilelink.scala:72:7] input clock, // @[Tilelink.scala:72:7] input reset, // @[Tilelink.scala:72:7] output io_tilelink_a_ready, // @[Tilelink.scala:79:14] input io_tilelink_a_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:79:14] input [6:0] io_tilelink_a_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:79:14] input [15:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:79:14] input [127:0] io_tilelink_a_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_a_bits_corrupt, // @[Tilelink.scala:79:14] output io_tilelink_c_ready, // @[Tilelink.scala:79:14] input io_tilelink_c_valid, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:79:14] input [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:79:14] input [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:79:14] input [6:0] io_tilelink_c_bits_source, // @[Tilelink.scala:79:14] input [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:79:14] input [127:0] io_tilelink_c_bits_data, // @[Tilelink.scala:79:14] input io_tilelink_c_bits_corrupt, // @[Tilelink.scala:79:14] input io_tilelink_d_ready, // @[Tilelink.scala:79:14] output io_tilelink_d_valid, // @[Tilelink.scala:79:14] output [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:79:14] output [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:79:14] output [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:79:14] output [6:0] io_tilelink_d_bits_source, // @[Tilelink.scala:79:14] output [5:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_denied, // @[Tilelink.scala:79:14] output [127:0] io_tilelink_d_bits_data, // @[Tilelink.scala:79:14] output io_tilelink_d_bits_corrupt, // @[Tilelink.scala:79:14] input io_flits_a_ready, // @[Tilelink.scala:79:14] output io_flits_a_valid, // @[Tilelink.scala:79:14] output io_flits_a_bits_head, // @[Tilelink.scala:79:14] output io_flits_a_bits_tail, // @[Tilelink.scala:79:14] output [144:0] io_flits_a_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_a_bits_egress_id, // @[Tilelink.scala:79:14] input io_flits_c_ready, // @[Tilelink.scala:79:14] output io_flits_c_valid, // @[Tilelink.scala:79:14] output io_flits_c_bits_head, // @[Tilelink.scala:79:14] output io_flits_c_bits_tail, // @[Tilelink.scala:79:14] output [144:0] io_flits_c_bits_payload, // @[Tilelink.scala:79:14] output [4:0] io_flits_c_bits_egress_id, // @[Tilelink.scala:79:14] output io_flits_d_ready, // @[Tilelink.scala:79:14] input io_flits_d_valid, // @[Tilelink.scala:79:14] input io_flits_d_bits_head, // @[Tilelink.scala:79:14] input io_flits_d_bits_tail, // @[Tilelink.scala:79:14] input [144:0] io_flits_d_bits_payload // @[Tilelink.scala:79:14] ); wire [128:0] _c_io_flit_bits_payload; // @[Tilelink.scala:89:17] TLAToNoC_6 a ( // @[Tilelink.scala:88:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload), .io_flit_bits_egress_id (io_flits_a_bits_egress_id) ); // @[Tilelink.scala:88:17] TLCToNoC_6 c ( // @[Tilelink.scala:89:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (_c_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_c_bits_egress_id) ); // @[Tilelink.scala:89:17] TLDFromNoC_1 d ( // @[Tilelink.scala:90:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (io_flits_d_bits_payload[128:0]) // @[Tilelink.scala:97:14] ); // @[Tilelink.scala:90:17] assign io_flits_c_bits_payload = {16'h0, _c_io_flit_bits_payload}; // @[Tilelink.scala:72:7, :89:17, :96:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_222 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_222( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_111 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}, out_virt_channel : UInt<4>}}[1], debug : { va_stall : UInt<4>, sa_stall : UInt<4>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], flip credit_return : UInt<10>, flip vc_free : UInt<10>}} inst input_buffer of InputBuffer_111 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) connect input_buffer.io.deq[8].ready, UInt<1>(0h0) connect input_buffer.io.deq[9].ready, UInt<1>(0h0) inst route_arbiter of Arbiter10_RouteComputerReq_5 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, fifo_deps : UInt<10>}[10], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0ha)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[8], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[9], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1) node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id) when _T_10 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_11 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_12 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_13 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_13 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_14 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_14 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_15 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_15 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_16 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_16 : connect states[7].g, UInt<3>(0h2) node _route_arbiter_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h1)) connect route_arbiter.io.in[8].valid, _route_arbiter_io_in_8_valid_T connect route_arbiter.io.in[8].bits.flow.egress_node_id, states[8].flow.egress_node_id connect route_arbiter.io.in[8].bits.flow.egress_node, states[8].flow.egress_node connect route_arbiter.io.in[8].bits.flow.ingress_node_id, states[8].flow.ingress_node_id connect route_arbiter.io.in[8].bits.flow.ingress_node, states[8].flow.ingress_node connect route_arbiter.io.in[8].bits.flow.vnet_id, states[8].flow.vnet_id connect route_arbiter.io.in[8].bits.src_virt_id, UInt<4>(0h8) node _T_17 = and(route_arbiter.io.in[8].ready, route_arbiter.io.in[8].valid) when _T_17 : connect states[8].g, UInt<3>(0h2) node _route_arbiter_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h1)) connect route_arbiter.io.in[9].valid, _route_arbiter_io_in_9_valid_T connect route_arbiter.io.in[9].bits.flow.egress_node_id, states[9].flow.egress_node_id connect route_arbiter.io.in[9].bits.flow.egress_node, states[9].flow.egress_node connect route_arbiter.io.in[9].bits.flow.ingress_node_id, states[9].flow.ingress_node_id connect route_arbiter.io.in[9].bits.flow.ingress_node, states[9].flow.ingress_node connect route_arbiter.io.in[9].bits.flow.vnet_id, states[9].flow.vnet_id connect route_arbiter.io.in[9].bits.src_virt_id, UInt<4>(0h9) node _T_18 = and(route_arbiter.io.in[9].ready, route_arbiter.io.in[9].valid) when _T_18 : connect states[9].g, UInt<3>(0h2) node _T_19 = and(io.router_req.ready, io.router_req.valid) when _T_19 : node _T_20 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_20, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_24 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_24 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_25 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_25 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_26 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_26 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_27 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_27 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_28 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_28 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_29 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_29 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_30 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_30 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_31 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_31 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_32 = eq(UInt<4>(0h8), io.router_req.bits.src_virt_id) when _T_32 : connect states[8].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_33 = eq(UInt<4>(0h9), io.router_req.bits.src_virt_id) when _T_33 : connect states[9].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.router_resp.vc_sel.`2` regreset mask : UInt<10>, clock, reset, UInt<10>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}[10] wire vcalloc_vals : UInt<1>[10] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi = cat(vcalloc_filter_lo_hi_hi, vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi = cat(vcalloc_filter_hi_hi_hi, vcalloc_vals[7]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_filter_lo_hi_hi_1, vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[6], vcalloc_vals[5]) node vcalloc_filter_hi_hi_hi_1 = cat(vcalloc_vals[9], vcalloc_vals[8]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_filter_hi_hi_hi_1, vcalloc_vals[7]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = bits(_vcalloc_filter_T_4, 16, 16) node _vcalloc_filter_T_22 = bits(_vcalloc_filter_T_4, 17, 17) node _vcalloc_filter_T_23 = bits(_vcalloc_filter_T_4, 18, 18) node _vcalloc_filter_T_24 = bits(_vcalloc_filter_T_4, 19, 19) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_24, UInt<20>(0h80000), UInt<20>(0h0)) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_23, UInt<20>(0h40000), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_22, UInt<20>(0h20000), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_21, UInt<20>(0h10000), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_20, UInt<20>(0h8000), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_19, UInt<20>(0h4000), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_18, UInt<20>(0h2000), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_17, UInt<20>(0h1000), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_16, UInt<20>(0h800), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_15, UInt<20>(0h400), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_14, UInt<20>(0h200), _vcalloc_filter_T_34) node _vcalloc_filter_T_36 = mux(_vcalloc_filter_T_13, UInt<20>(0h100), _vcalloc_filter_T_35) node _vcalloc_filter_T_37 = mux(_vcalloc_filter_T_12, UInt<20>(0h80), _vcalloc_filter_T_36) node _vcalloc_filter_T_38 = mux(_vcalloc_filter_T_11, UInt<20>(0h40), _vcalloc_filter_T_37) node _vcalloc_filter_T_39 = mux(_vcalloc_filter_T_10, UInt<20>(0h20), _vcalloc_filter_T_38) node _vcalloc_filter_T_40 = mux(_vcalloc_filter_T_9, UInt<20>(0h10), _vcalloc_filter_T_39) node _vcalloc_filter_T_41 = mux(_vcalloc_filter_T_8, UInt<20>(0h8), _vcalloc_filter_T_40) node _vcalloc_filter_T_42 = mux(_vcalloc_filter_T_7, UInt<20>(0h4), _vcalloc_filter_T_41) node _vcalloc_filter_T_43 = mux(_vcalloc_filter_T_6, UInt<20>(0h2), _vcalloc_filter_T_42) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<20>(0h1), _vcalloc_filter_T_43) node _vcalloc_sel_T = bits(vcalloc_filter, 9, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 10) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_34 = and(io.router_req.ready, io.router_req.valid) when _T_34 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_35 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_36 = or(_T_35, vcalloc_vals[2]) node _T_37 = or(_T_36, vcalloc_vals[3]) node _T_38 = or(_T_37, vcalloc_vals[4]) node _T_39 = or(_T_38, vcalloc_vals[5]) node _T_40 = or(_T_39, vcalloc_vals[6]) node _T_41 = or(_T_40, vcalloc_vals[7]) node _T_42 = or(_T_41, vcalloc_vals[8]) node _T_43 = or(_T_42, vcalloc_vals[9]) when _T_43 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = not(UInt<9>(0h0)) node _mask_T_12 = not(UInt<10>(0h0)) node _mask_T_13 = bits(vcalloc_sel, 0, 0) node _mask_T_14 = bits(vcalloc_sel, 1, 1) node _mask_T_15 = bits(vcalloc_sel, 2, 2) node _mask_T_16 = bits(vcalloc_sel, 3, 3) node _mask_T_17 = bits(vcalloc_sel, 4, 4) node _mask_T_18 = bits(vcalloc_sel, 5, 5) node _mask_T_19 = bits(vcalloc_sel, 6, 6) node _mask_T_20 = bits(vcalloc_sel, 7, 7) node _mask_T_21 = bits(vcalloc_sel, 8, 8) node _mask_T_22 = bits(vcalloc_sel, 9, 9) node _mask_T_23 = mux(_mask_T_13, _mask_T_3, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_14, _mask_T_4, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_15, _mask_T_5, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_16, _mask_T_6, UInt<1>(0h0)) node _mask_T_27 = mux(_mask_T_17, _mask_T_7, UInt<1>(0h0)) node _mask_T_28 = mux(_mask_T_18, _mask_T_8, UInt<1>(0h0)) node _mask_T_29 = mux(_mask_T_19, _mask_T_9, UInt<1>(0h0)) node _mask_T_30 = mux(_mask_T_20, _mask_T_10, UInt<1>(0h0)) node _mask_T_31 = mux(_mask_T_21, _mask_T_11, UInt<1>(0h0)) node _mask_T_32 = mux(_mask_T_22, _mask_T_12, UInt<1>(0h0)) node _mask_T_33 = or(_mask_T_23, _mask_T_24) node _mask_T_34 = or(_mask_T_33, _mask_T_25) node _mask_T_35 = or(_mask_T_34, _mask_T_26) node _mask_T_36 = or(_mask_T_35, _mask_T_27) node _mask_T_37 = or(_mask_T_36, _mask_T_28) node _mask_T_38 = or(_mask_T_37, _mask_T_29) node _mask_T_39 = or(_mask_T_38, _mask_T_30) node _mask_T_40 = or(_mask_T_39, _mask_T_31) node _mask_T_41 = or(_mask_T_40, _mask_T_32) wire _mask_WIRE : UInt<10> connect _mask_WIRE, _mask_T_41 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) node _io_vcalloc_req_valid_T_7 = or(_io_vcalloc_req_valid_T_6, vcalloc_vals[8]) node _io_vcalloc_req_valid_T_8 = or(_io_vcalloc_req_valid_T_7, vcalloc_vals[9]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_8 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) node _io_vcalloc_req_bits_T_8 = bits(vcalloc_sel, 8, 8) node _io_vcalloc_req_bits_T_9 = bits(vcalloc_sel, 9, 9) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, in_vc : UInt<4>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}} wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[10] node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_23 = or(_io_vcalloc_req_bits_T_22, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_24 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_24, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_25, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_18) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_27, _io_vcalloc_req_bits_T_19) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_28 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_31) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_40, _io_vcalloc_req_bits_T_32) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_42, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_44 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_45 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_36) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_45, _io_vcalloc_req_bits_T_37) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_38) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_59 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_50) node _io_vcalloc_req_bits_T_60 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_60, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_57) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_66 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_67 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_67, _io_vcalloc_req_bits_T_68) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_75) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_76) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_92 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_98 = or(_io_vcalloc_req_bits_T_97, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_99 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_90) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_99, _io_vcalloc_req_bits_T_91) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_92) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_93) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_104 = or(_io_vcalloc_req_bits_T_103, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_104 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_110 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_111 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_112 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = or(_io_vcalloc_req_bits_T_105, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_116 = or(_io_vcalloc_req_bits_T_115, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_117 = or(_io_vcalloc_req_bits_T_116, _io_vcalloc_req_bits_T_108) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_117, _io_vcalloc_req_bits_T_109) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_110) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_111) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_112) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_113) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_114) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_123 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_135 = or(_io_vcalloc_req_bits_T_134, _io_vcalloc_req_bits_T_126) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_135, _io_vcalloc_req_bits_T_127) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_128) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_133) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_158 = or(_io_vcalloc_req_bits_T_157, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_159 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_160 = or(_io_vcalloc_req_bits_T_159, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_161 = or(_io_vcalloc_req_bits_T_160, _io_vcalloc_req_bits_T_152) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_161 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[8], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_162, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_165) node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_166) node _io_vcalloc_req_bits_T_176 = or(_io_vcalloc_req_bits_T_175, _io_vcalloc_req_bits_T_167) node _io_vcalloc_req_bits_T_177 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_168) node _io_vcalloc_req_bits_T_178 = or(_io_vcalloc_req_bits_T_177, _io_vcalloc_req_bits_T_169) node _io_vcalloc_req_bits_T_179 = or(_io_vcalloc_req_bits_T_178, _io_vcalloc_req_bits_T_170) node _io_vcalloc_req_bits_T_180 = or(_io_vcalloc_req_bits_T_179, _io_vcalloc_req_bits_T_171) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_180 connect _io_vcalloc_req_bits_WIRE_2[8], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_181 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_182 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_183 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_184 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`0`[9], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_182) node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_183) node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_184) node _io_vcalloc_req_bits_T_194 = or(_io_vcalloc_req_bits_T_193, _io_vcalloc_req_bits_T_185) node _io_vcalloc_req_bits_T_195 = or(_io_vcalloc_req_bits_T_194, _io_vcalloc_req_bits_T_186) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_195, _io_vcalloc_req_bits_T_187) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_188) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_190) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_199 connect _io_vcalloc_req_bits_WIRE_2[9], _io_vcalloc_req_bits_WIRE_12 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[1] node _io_vcalloc_req_bits_T_200 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_201 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_202 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_201) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_210, _io_vcalloc_req_bits_T_202) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_203) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_218 = or(_io_vcalloc_req_bits_T_217, _io_vcalloc_req_bits_T_209) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_218 connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_13 wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>[1] node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_227 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_228 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_219, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_233 = or(_io_vcalloc_req_bits_T_232, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_234 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_225) node _io_vcalloc_req_bits_T_235 = or(_io_vcalloc_req_bits_T_234, _io_vcalloc_req_bits_T_226) node _io_vcalloc_req_bits_T_236 = or(_io_vcalloc_req_bits_T_235, _io_vcalloc_req_bits_T_227) node _io_vcalloc_req_bits_T_237 = or(_io_vcalloc_req_bits_T_236, _io_vcalloc_req_bits_T_228) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_237 connect _io_vcalloc_req_bits_WIRE_15[0], _io_vcalloc_req_bits_WIRE_16 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_15 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_242 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_243 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_244 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_245 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_246 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_247 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_248 = or(_io_vcalloc_req_bits_T_238, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_249 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_240) node _io_vcalloc_req_bits_T_250 = or(_io_vcalloc_req_bits_T_249, _io_vcalloc_req_bits_T_241) node _io_vcalloc_req_bits_T_251 = or(_io_vcalloc_req_bits_T_250, _io_vcalloc_req_bits_T_242) node _io_vcalloc_req_bits_T_252 = or(_io_vcalloc_req_bits_T_251, _io_vcalloc_req_bits_T_243) node _io_vcalloc_req_bits_T_253 = or(_io_vcalloc_req_bits_T_252, _io_vcalloc_req_bits_T_244) node _io_vcalloc_req_bits_T_254 = or(_io_vcalloc_req_bits_T_253, _io_vcalloc_req_bits_T_245) node _io_vcalloc_req_bits_T_255 = or(_io_vcalloc_req_bits_T_254, _io_vcalloc_req_bits_T_246) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_255, _io_vcalloc_req_bits_T_247) wire _io_vcalloc_req_bits_WIRE_17 : UInt<4> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_256 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_17 wire _io_vcalloc_req_bits_WIRE_18 : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _io_vcalloc_req_bits_T_257 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_258 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_259 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_260 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_261 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_262 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_258) node _io_vcalloc_req_bits_T_268 = or(_io_vcalloc_req_bits_T_267, _io_vcalloc_req_bits_T_259) node _io_vcalloc_req_bits_T_269 = or(_io_vcalloc_req_bits_T_268, _io_vcalloc_req_bits_T_260) node _io_vcalloc_req_bits_T_270 = or(_io_vcalloc_req_bits_T_269, _io_vcalloc_req_bits_T_261) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_270, _io_vcalloc_req_bits_T_262) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_263) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_266) wire _io_vcalloc_req_bits_WIRE_19 : UInt<3> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_275 connect _io_vcalloc_req_bits_WIRE_18.egress_node_id, _io_vcalloc_req_bits_WIRE_19 node _io_vcalloc_req_bits_T_276 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_277 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_277) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_278) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_293 = or(_io_vcalloc_req_bits_T_292, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_294 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_20 : UInt<4> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_294 connect _io_vcalloc_req_bits_WIRE_18.egress_node, _io_vcalloc_req_bits_WIRE_20 node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_302 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_303 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_304 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_295, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_308 = or(_io_vcalloc_req_bits_T_307, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_309 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_300) node _io_vcalloc_req_bits_T_310 = or(_io_vcalloc_req_bits_T_309, _io_vcalloc_req_bits_T_301) node _io_vcalloc_req_bits_T_311 = or(_io_vcalloc_req_bits_T_310, _io_vcalloc_req_bits_T_302) node _io_vcalloc_req_bits_T_312 = or(_io_vcalloc_req_bits_T_311, _io_vcalloc_req_bits_T_303) node _io_vcalloc_req_bits_T_313 = or(_io_vcalloc_req_bits_T_312, _io_vcalloc_req_bits_T_304) wire _io_vcalloc_req_bits_WIRE_21 : UInt<2> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_313 connect _io_vcalloc_req_bits_WIRE_18.ingress_node_id, _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_317 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_318 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_319 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_320 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_321 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_322 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = or(_io_vcalloc_req_bits_T_314, _io_vcalloc_req_bits_T_315) node _io_vcalloc_req_bits_T_325 = or(_io_vcalloc_req_bits_T_324, _io_vcalloc_req_bits_T_316) node _io_vcalloc_req_bits_T_326 = or(_io_vcalloc_req_bits_T_325, _io_vcalloc_req_bits_T_317) node _io_vcalloc_req_bits_T_327 = or(_io_vcalloc_req_bits_T_326, _io_vcalloc_req_bits_T_318) node _io_vcalloc_req_bits_T_328 = or(_io_vcalloc_req_bits_T_327, _io_vcalloc_req_bits_T_319) node _io_vcalloc_req_bits_T_329 = or(_io_vcalloc_req_bits_T_328, _io_vcalloc_req_bits_T_320) node _io_vcalloc_req_bits_T_330 = or(_io_vcalloc_req_bits_T_329, _io_vcalloc_req_bits_T_321) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_330, _io_vcalloc_req_bits_T_322) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_323) wire _io_vcalloc_req_bits_WIRE_22 : UInt<4> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_332 connect _io_vcalloc_req_bits_WIRE_18.ingress_node, _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_333 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_334 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_335 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_336 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_337 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_8, vcalloc_reqs[8].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_9, vcalloc_reqs[9].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_334) node _io_vcalloc_req_bits_T_344 = or(_io_vcalloc_req_bits_T_343, _io_vcalloc_req_bits_T_335) node _io_vcalloc_req_bits_T_345 = or(_io_vcalloc_req_bits_T_344, _io_vcalloc_req_bits_T_336) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_345, _io_vcalloc_req_bits_T_337) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_338) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_342) wire _io_vcalloc_req_bits_WIRE_23 : UInt<3> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_351 connect _io_vcalloc_req_bits_WIRE_18.vnet_id, _io_vcalloc_req_bits_WIRE_23 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_18 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`0`[6] invalidate vcalloc_reqs[0].vc_sel.`0`[7] invalidate vcalloc_reqs[0].vc_sel.`0`[8] invalidate vcalloc_reqs[0].vc_sel.`0`[9] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`0`[3] invalidate vcalloc_reqs[1].vc_sel.`0`[4] invalidate vcalloc_reqs[1].vc_sel.`0`[5] invalidate vcalloc_reqs[1].vc_sel.`0`[6] invalidate vcalloc_reqs[1].vc_sel.`0`[7] invalidate vcalloc_reqs[1].vc_sel.`0`[8] invalidate vcalloc_reqs[1].vc_sel.`0`[9] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`2`[0] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].flow, states[2].flow node _T_44 = bits(vcalloc_sel, 2, 2) node _T_45 = and(vcalloc_vals[2], _T_44) node _T_46 = and(_T_45, io.vcalloc_req.ready) when _T_46 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].flow, states[3].flow node _T_47 = bits(vcalloc_sel, 3, 3) node _T_48 = and(vcalloc_vals[3], _T_47) node _T_49 = and(_T_48, io.vcalloc_req.ready) when _T_49 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].flow, states[4].flow node _T_50 = bits(vcalloc_sel, 4, 4) node _T_51 = and(vcalloc_vals[4], _T_50) node _T_52 = and(_T_51, io.vcalloc_req.ready) when _T_52 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].flow, states[5].flow node _T_53 = bits(vcalloc_sel, 5, 5) node _T_54 = and(vcalloc_vals[5], _T_53) node _T_55 = and(_T_54, io.vcalloc_req.ready) when _T_55 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].flow, states[6].flow node _T_56 = bits(vcalloc_sel, 6, 6) node _T_57 = and(vcalloc_vals[6], _T_56) node _T_58 = and(_T_57, io.vcalloc_req.ready) when _T_58 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].flow, states[7].flow node _T_59 = bits(vcalloc_sel, 7, 7) node _T_60 = and(vcalloc_vals[7], _T_59) node _T_61 = and(_T_60, io.vcalloc_req.ready) when _T_61 : connect states[7].g, UInt<3>(0h3) node _vcalloc_vals_8_T = eq(states[8].g, UInt<3>(0h2)) node _vcalloc_vals_8_T_1 = eq(states[8].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_8_T_2 = and(_vcalloc_vals_8_T, _vcalloc_vals_8_T_1) connect vcalloc_vals[8], _vcalloc_vals_8_T_2 connect vcalloc_reqs[8].in_vc, UInt<4>(0h8) connect vcalloc_reqs[8].vc_sel.`0`, states[8].vc_sel.`0` connect vcalloc_reqs[8].vc_sel.`1`, states[8].vc_sel.`1` connect vcalloc_reqs[8].vc_sel.`2`, states[8].vc_sel.`2` connect vcalloc_reqs[8].flow, states[8].flow node _T_62 = bits(vcalloc_sel, 8, 8) node _T_63 = and(vcalloc_vals[8], _T_62) node _T_64 = and(_T_63, io.vcalloc_req.ready) when _T_64 : connect states[8].g, UInt<3>(0h3) node _vcalloc_vals_9_T = eq(states[9].g, UInt<3>(0h2)) node _vcalloc_vals_9_T_1 = eq(states[9].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_9_T_2 = and(_vcalloc_vals_9_T, _vcalloc_vals_9_T_1) connect vcalloc_vals[9], _vcalloc_vals_9_T_2 connect vcalloc_reqs[9].in_vc, UInt<4>(0h9) connect vcalloc_reqs[9].vc_sel.`0`, states[9].vc_sel.`0` connect vcalloc_reqs[9].vc_sel.`1`, states[9].vc_sel.`1` connect vcalloc_reqs[9].vc_sel.`2`, states[9].vc_sel.`2` connect vcalloc_reqs[9].flow, states[9].flow node _T_65 = bits(vcalloc_sel, 9, 9) node _T_66 = and(vcalloc_vals[9], _T_65) node _T_67 = and(_T_66, io.vcalloc_req.ready) when _T_67 : connect states[9].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[5], vcalloc_vals[6]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(vcalloc_vals[8], vcalloc_vals[9]) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 1, 0) node _io_debug_va_stall_T_12 = add(vcalloc_vals[7], _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 1, 0) node _io_debug_va_stall_T_14 = add(_io_debug_va_stall_T_9, _io_debug_va_stall_T_13) node _io_debug_va_stall_T_15 = bits(_io_debug_va_stall_T_14, 2, 0) node _io_debug_va_stall_T_16 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_15) node _io_debug_va_stall_T_17 = bits(_io_debug_va_stall_T_16, 3, 0) node _io_debug_va_stall_T_18 = sub(_io_debug_va_stall_T_17, io.vcalloc_req.ready) node _io_debug_va_stall_T_19 = tail(_io_debug_va_stall_T_18, 1) connect io.debug.va_stall, _io_debug_va_stall_T_19 node _T_68 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_68 : node _T_69 = bits(vcalloc_sel, 0, 0) when _T_69 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].g, UInt<3>(0h3) node _T_70 = eq(states[0].g, UInt<3>(0h2)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_70, UInt<1>(0h1), "") : assert_3 node _T_74 = bits(vcalloc_sel, 1, 1) when _T_74 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].g, UInt<3>(0h3) node _T_75 = eq(states[1].g, UInt<3>(0h2)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_75, UInt<1>(0h1), "") : assert_4 node _T_79 = bits(vcalloc_sel, 2, 2) when _T_79 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].g, UInt<3>(0h3) node _T_80 = eq(states[2].g, UInt<3>(0h2)) node _T_81 = asUInt(reset) node _T_82 = eq(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = eq(_T_80, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_80, UInt<1>(0h1), "") : assert_5 node _T_84 = bits(vcalloc_sel, 3, 3) when _T_84 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].g, UInt<3>(0h3) node _T_85 = eq(states[3].g, UInt<3>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_85, UInt<1>(0h1), "") : assert_6 node _T_89 = bits(vcalloc_sel, 4, 4) when _T_89 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].g, UInt<3>(0h3) node _T_90 = eq(states[4].g, UInt<3>(0h2)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_90, UInt<1>(0h1), "") : assert_7 node _T_94 = bits(vcalloc_sel, 5, 5) when _T_94 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].g, UInt<3>(0h3) node _T_95 = eq(states[5].g, UInt<3>(0h2)) node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : node _T_98 = eq(_T_95, UInt<1>(0h0)) when _T_98 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_95, UInt<1>(0h1), "") : assert_8 node _T_99 = bits(vcalloc_sel, 6, 6) when _T_99 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].g, UInt<3>(0h3) node _T_100 = eq(states[6].g, UInt<3>(0h2)) node _T_101 = asUInt(reset) node _T_102 = eq(_T_101, UInt<1>(0h0)) when _T_102 : node _T_103 = eq(_T_100, UInt<1>(0h0)) when _T_103 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_100, UInt<1>(0h1), "") : assert_9 node _T_104 = bits(vcalloc_sel, 7, 7) when _T_104 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].g, UInt<3>(0h3) node _T_105 = eq(states[7].g, UInt<3>(0h2)) node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_T_105, UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_105, UInt<1>(0h1), "") : assert_10 node _T_109 = bits(vcalloc_sel, 8, 8) when _T_109 : connect states[8].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[8].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[8].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[8].g, UInt<3>(0h3) node _T_110 = eq(states[8].g, UInt<3>(0h2)) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_11 assert(clock, _T_110, UInt<1>(0h1), "") : assert_11 node _T_114 = bits(vcalloc_sel, 9, 9) when _T_114 : connect states[9].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[9].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[9].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[9].g, UInt<3>(0h3) node _T_115 = eq(states[9].g, UInt<3>(0h2)) node _T_116 = asUInt(reset) node _T_117 = eq(_T_116, UInt<1>(0h0)) when _T_117 : node _T_118 = eq(_T_115, UInt<1>(0h0)) when _T_118 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_12 assert(clock, _T_115, UInt<1>(0h1), "") : assert_12 inst salloc_arb of SwitchArbiter_297 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[8] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[9] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0] node credit_available_lo_lo = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_hi = cat(states[2].vc_sel.`0`[4], states[2].vc_sel.`0`[3]) node credit_available_lo_hi = cat(credit_available_lo_hi_hi, states[2].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[2].vc_sel.`0`[6], states[2].vc_sel.`0`[5]) node credit_available_hi_hi_hi = cat(states[2].vc_sel.`0`[9], states[2].vc_sel.`0`[8]) node credit_available_hi_hi = cat(credit_available_hi_hi_hi, states[2].vc_sel.`0`[7]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_hi_1 = cat(states[2].vc_sel.`2`[0], states[2].vc_sel.`1`[0]) node _credit_available_T_1 = cat(credit_available_hi_1, _credit_available_T) node credit_available_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_1 = cat(credit_available_lo_hi_hi_1, io.out_credit_available.`0`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_1 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_1 = cat(credit_available_hi_hi_hi_1, io.out_credit_available.`0`[7]) node credit_available_hi_2 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_1) node credit_available_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T_2) node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3) node credit_available = neq(_credit_available_T_4, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`0`[8], states[2].vc_sel.`0`[8] connect salloc_arb.io.in[2].bits.vc_sel.`0`[9], states[2].vc_sel.`0`[9] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_119 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_120 = and(_T_119, input_buffer.io.deq[2].bits.tail) when _T_120 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_2 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_hi_2 = cat(states[3].vc_sel.`0`[4], states[3].vc_sel.`0`[3]) node credit_available_lo_hi_2 = cat(credit_available_lo_hi_hi_2, states[3].vc_sel.`0`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[3].vc_sel.`0`[6], states[3].vc_sel.`0`[5]) node credit_available_hi_hi_hi_2 = cat(states[3].vc_sel.`0`[9], states[3].vc_sel.`0`[8]) node credit_available_hi_hi_2 = cat(credit_available_hi_hi_hi_2, states[3].vc_sel.`0`[7]) node credit_available_hi_4 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_5 = cat(credit_available_hi_4, credit_available_lo_2) node credit_available_hi_5 = cat(states[3].vc_sel.`2`[0], states[3].vc_sel.`1`[0]) node _credit_available_T_6 = cat(credit_available_hi_5, _credit_available_T_5) node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_3 = cat(credit_available_lo_hi_hi_3, io.out_credit_available.`0`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_3 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_3 = cat(credit_available_hi_hi_hi_3, io.out_credit_available.`0`[7]) node credit_available_hi_6 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_7 = cat(credit_available_hi_6, credit_available_lo_3) node credit_available_hi_7 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_8 = cat(credit_available_hi_7, _credit_available_T_7) node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8) node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_1) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`0`[8], states[3].vc_sel.`0`[8] connect salloc_arb.io.in[3].bits.vc_sel.`0`[9], states[3].vc_sel.`0`[9] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_121 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_122 = and(_T_121, input_buffer.io.deq[3].bits.tail) when _T_122 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_4 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_hi_4 = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3]) node credit_available_lo_hi_4 = cat(credit_available_lo_hi_hi_4, states[4].vc_sel.`0`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(states[4].vc_sel.`0`[6], states[4].vc_sel.`0`[5]) node credit_available_hi_hi_hi_4 = cat(states[4].vc_sel.`0`[9], states[4].vc_sel.`0`[8]) node credit_available_hi_hi_4 = cat(credit_available_hi_hi_hi_4, states[4].vc_sel.`0`[7]) node credit_available_hi_8 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_10 = cat(credit_available_hi_8, credit_available_lo_4) node credit_available_hi_9 = cat(states[4].vc_sel.`2`[0], states[4].vc_sel.`1`[0]) node _credit_available_T_11 = cat(credit_available_hi_9, _credit_available_T_10) node credit_available_lo_lo_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_5 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_5 = cat(credit_available_lo_hi_hi_5, io.out_credit_available.`0`[2]) node credit_available_lo_5 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_5 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_5 = cat(credit_available_hi_hi_hi_5, io.out_credit_available.`0`[7]) node credit_available_hi_10 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_12 = cat(credit_available_hi_10, credit_available_lo_5) node credit_available_hi_11 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_13 = cat(credit_available_hi_11, _credit_available_T_12) node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13) node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_2) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`0`[8], states[4].vc_sel.`0`[8] connect salloc_arb.io.in[4].bits.vc_sel.`0`[9], states[4].vc_sel.`0`[9] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_123 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_124 = and(_T_123, input_buffer.io.deq[4].bits.tail) when _T_124 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_6 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_hi_6 = cat(states[5].vc_sel.`0`[4], states[5].vc_sel.`0`[3]) node credit_available_lo_hi_6 = cat(credit_available_lo_hi_hi_6, states[5].vc_sel.`0`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(states[5].vc_sel.`0`[6], states[5].vc_sel.`0`[5]) node credit_available_hi_hi_hi_6 = cat(states[5].vc_sel.`0`[9], states[5].vc_sel.`0`[8]) node credit_available_hi_hi_6 = cat(credit_available_hi_hi_hi_6, states[5].vc_sel.`0`[7]) node credit_available_hi_12 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6) node _credit_available_T_15 = cat(credit_available_hi_12, credit_available_lo_6) node credit_available_hi_13 = cat(states[5].vc_sel.`2`[0], states[5].vc_sel.`1`[0]) node _credit_available_T_16 = cat(credit_available_hi_13, _credit_available_T_15) node credit_available_lo_lo_7 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_7 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_7 = cat(credit_available_lo_hi_hi_7, io.out_credit_available.`0`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_7 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_7 = cat(credit_available_hi_hi_hi_7, io.out_credit_available.`0`[7]) node credit_available_hi_14 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7) node _credit_available_T_17 = cat(credit_available_hi_14, credit_available_lo_7) node credit_available_hi_15 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_18 = cat(credit_available_hi_15, _credit_available_T_17) node _credit_available_T_19 = and(_credit_available_T_16, _credit_available_T_18) node credit_available_3 = neq(_credit_available_T_19, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_3) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`0`[8], states[5].vc_sel.`0`[8] connect salloc_arb.io.in[5].bits.vc_sel.`0`[9], states[5].vc_sel.`0`[9] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_125 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_126 = and(_T_125, input_buffer.io.deq[5].bits.tail) when _T_126 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_8 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_hi_8 = cat(states[6].vc_sel.`0`[4], states[6].vc_sel.`0`[3]) node credit_available_lo_hi_8 = cat(credit_available_lo_hi_hi_8, states[6].vc_sel.`0`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[6].vc_sel.`0`[6], states[6].vc_sel.`0`[5]) node credit_available_hi_hi_hi_8 = cat(states[6].vc_sel.`0`[9], states[6].vc_sel.`0`[8]) node credit_available_hi_hi_8 = cat(credit_available_hi_hi_hi_8, states[6].vc_sel.`0`[7]) node credit_available_hi_16 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8) node _credit_available_T_20 = cat(credit_available_hi_16, credit_available_lo_8) node credit_available_hi_17 = cat(states[6].vc_sel.`2`[0], states[6].vc_sel.`1`[0]) node _credit_available_T_21 = cat(credit_available_hi_17, _credit_available_T_20) node credit_available_lo_lo_9 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_9 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_9 = cat(credit_available_lo_hi_hi_9, io.out_credit_available.`0`[2]) node credit_available_lo_9 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_9 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_9 = cat(credit_available_hi_hi_hi_9, io.out_credit_available.`0`[7]) node credit_available_hi_18 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9) node _credit_available_T_22 = cat(credit_available_hi_18, credit_available_lo_9) node credit_available_hi_19 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_23 = cat(credit_available_hi_19, _credit_available_T_22) node _credit_available_T_24 = and(_credit_available_T_21, _credit_available_T_23) node credit_available_4 = neq(_credit_available_T_24, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_4) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`0`[8], states[6].vc_sel.`0`[8] connect salloc_arb.io.in[6].bits.vc_sel.`0`[9], states[6].vc_sel.`0`[9] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_127 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_128 = and(_T_127, input_buffer.io.deq[6].bits.tail) when _T_128 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_10 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_hi_10 = cat(states[7].vc_sel.`0`[4], states[7].vc_sel.`0`[3]) node credit_available_lo_hi_10 = cat(credit_available_lo_hi_hi_10, states[7].vc_sel.`0`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[7].vc_sel.`0`[6], states[7].vc_sel.`0`[5]) node credit_available_hi_hi_hi_10 = cat(states[7].vc_sel.`0`[9], states[7].vc_sel.`0`[8]) node credit_available_hi_hi_10 = cat(credit_available_hi_hi_hi_10, states[7].vc_sel.`0`[7]) node credit_available_hi_20 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10) node _credit_available_T_25 = cat(credit_available_hi_20, credit_available_lo_10) node credit_available_hi_21 = cat(states[7].vc_sel.`2`[0], states[7].vc_sel.`1`[0]) node _credit_available_T_26 = cat(credit_available_hi_21, _credit_available_T_25) node credit_available_lo_lo_11 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_11 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_11 = cat(credit_available_lo_hi_hi_11, io.out_credit_available.`0`[2]) node credit_available_lo_11 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_11 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_11 = cat(credit_available_hi_hi_hi_11, io.out_credit_available.`0`[7]) node credit_available_hi_22 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11) node _credit_available_T_27 = cat(credit_available_hi_22, credit_available_lo_11) node credit_available_hi_23 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_28 = cat(credit_available_hi_23, _credit_available_T_27) node _credit_available_T_29 = and(_credit_available_T_26, _credit_available_T_28) node credit_available_5 = neq(_credit_available_T_29, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_5) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`0`[8], states[7].vc_sel.`0`[8] connect salloc_arb.io.in[7].bits.vc_sel.`0`[9], states[7].vc_sel.`0`[9] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_129 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_130 = and(_T_129, input_buffer.io.deq[7].bits.tail) when _T_130 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node credit_available_lo_lo_12 = cat(states[8].vc_sel.`0`[1], states[8].vc_sel.`0`[0]) node credit_available_lo_hi_hi_12 = cat(states[8].vc_sel.`0`[4], states[8].vc_sel.`0`[3]) node credit_available_lo_hi_12 = cat(credit_available_lo_hi_hi_12, states[8].vc_sel.`0`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(states[8].vc_sel.`0`[6], states[8].vc_sel.`0`[5]) node credit_available_hi_hi_hi_12 = cat(states[8].vc_sel.`0`[9], states[8].vc_sel.`0`[8]) node credit_available_hi_hi_12 = cat(credit_available_hi_hi_hi_12, states[8].vc_sel.`0`[7]) node credit_available_hi_24 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12) node _credit_available_T_30 = cat(credit_available_hi_24, credit_available_lo_12) node credit_available_hi_25 = cat(states[8].vc_sel.`2`[0], states[8].vc_sel.`1`[0]) node _credit_available_T_31 = cat(credit_available_hi_25, _credit_available_T_30) node credit_available_lo_lo_13 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_13 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_13 = cat(credit_available_lo_hi_hi_13, io.out_credit_available.`0`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_13 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_13 = cat(credit_available_hi_hi_hi_13, io.out_credit_available.`0`[7]) node credit_available_hi_26 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13) node _credit_available_T_32 = cat(credit_available_hi_26, credit_available_lo_13) node credit_available_hi_27 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_33 = cat(credit_available_hi_27, _credit_available_T_32) node _credit_available_T_34 = and(_credit_available_T_31, _credit_available_T_33) node credit_available_6 = neq(_credit_available_T_34, UInt<1>(0h0)) node _salloc_arb_io_in_8_valid_T = eq(states[8].g, UInt<3>(0h3)) node _salloc_arb_io_in_8_valid_T_1 = and(_salloc_arb_io_in_8_valid_T, credit_available_6) node _salloc_arb_io_in_8_valid_T_2 = and(_salloc_arb_io_in_8_valid_T_1, input_buffer.io.deq[8].valid) connect salloc_arb.io.in[8].valid, _salloc_arb_io_in_8_valid_T_2 connect salloc_arb.io.in[8].bits.vc_sel.`0`[0], states[8].vc_sel.`0`[0] connect salloc_arb.io.in[8].bits.vc_sel.`0`[1], states[8].vc_sel.`0`[1] connect salloc_arb.io.in[8].bits.vc_sel.`0`[2], states[8].vc_sel.`0`[2] connect salloc_arb.io.in[8].bits.vc_sel.`0`[3], states[8].vc_sel.`0`[3] connect salloc_arb.io.in[8].bits.vc_sel.`0`[4], states[8].vc_sel.`0`[4] connect salloc_arb.io.in[8].bits.vc_sel.`0`[5], states[8].vc_sel.`0`[5] connect salloc_arb.io.in[8].bits.vc_sel.`0`[6], states[8].vc_sel.`0`[6] connect salloc_arb.io.in[8].bits.vc_sel.`0`[7], states[8].vc_sel.`0`[7] connect salloc_arb.io.in[8].bits.vc_sel.`0`[8], states[8].vc_sel.`0`[8] connect salloc_arb.io.in[8].bits.vc_sel.`0`[9], states[8].vc_sel.`0`[9] connect salloc_arb.io.in[8].bits.vc_sel.`1`[0], states[8].vc_sel.`1`[0] connect salloc_arb.io.in[8].bits.vc_sel.`2`[0], states[8].vc_sel.`2`[0] connect salloc_arb.io.in[8].bits.tail, input_buffer.io.deq[8].bits.tail node _T_131 = and(salloc_arb.io.in[8].ready, salloc_arb.io.in[8].valid) node _T_132 = and(_T_131, input_buffer.io.deq[8].bits.tail) when _T_132 : connect states[8].g, UInt<3>(0h0) connect input_buffer.io.deq[8].ready, salloc_arb.io.in[8].ready node credit_available_lo_lo_14 = cat(states[9].vc_sel.`0`[1], states[9].vc_sel.`0`[0]) node credit_available_lo_hi_hi_14 = cat(states[9].vc_sel.`0`[4], states[9].vc_sel.`0`[3]) node credit_available_lo_hi_14 = cat(credit_available_lo_hi_hi_14, states[9].vc_sel.`0`[2]) node credit_available_lo_14 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(states[9].vc_sel.`0`[6], states[9].vc_sel.`0`[5]) node credit_available_hi_hi_hi_14 = cat(states[9].vc_sel.`0`[9], states[9].vc_sel.`0`[8]) node credit_available_hi_hi_14 = cat(credit_available_hi_hi_hi_14, states[9].vc_sel.`0`[7]) node credit_available_hi_28 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14) node _credit_available_T_35 = cat(credit_available_hi_28, credit_available_lo_14) node credit_available_hi_29 = cat(states[9].vc_sel.`2`[0], states[9].vc_sel.`1`[0]) node _credit_available_T_36 = cat(credit_available_hi_29, _credit_available_T_35) node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_hi_15 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_lo_hi_15 = cat(credit_available_lo_hi_hi_15, io.out_credit_available.`0`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[6], io.out_credit_available.`0`[5]) node credit_available_hi_hi_hi_15 = cat(io.out_credit_available.`0`[9], io.out_credit_available.`0`[8]) node credit_available_hi_hi_15 = cat(credit_available_hi_hi_hi_15, io.out_credit_available.`0`[7]) node credit_available_hi_30 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15) node _credit_available_T_37 = cat(credit_available_hi_30, credit_available_lo_15) node credit_available_hi_31 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0]) node _credit_available_T_38 = cat(credit_available_hi_31, _credit_available_T_37) node _credit_available_T_39 = and(_credit_available_T_36, _credit_available_T_38) node credit_available_7 = neq(_credit_available_T_39, UInt<1>(0h0)) node _salloc_arb_io_in_9_valid_T = eq(states[9].g, UInt<3>(0h3)) node _salloc_arb_io_in_9_valid_T_1 = and(_salloc_arb_io_in_9_valid_T, credit_available_7) node _salloc_arb_io_in_9_valid_T_2 = and(_salloc_arb_io_in_9_valid_T_1, input_buffer.io.deq[9].valid) connect salloc_arb.io.in[9].valid, _salloc_arb_io_in_9_valid_T_2 connect salloc_arb.io.in[9].bits.vc_sel.`0`[0], states[9].vc_sel.`0`[0] connect salloc_arb.io.in[9].bits.vc_sel.`0`[1], states[9].vc_sel.`0`[1] connect salloc_arb.io.in[9].bits.vc_sel.`0`[2], states[9].vc_sel.`0`[2] connect salloc_arb.io.in[9].bits.vc_sel.`0`[3], states[9].vc_sel.`0`[3] connect salloc_arb.io.in[9].bits.vc_sel.`0`[4], states[9].vc_sel.`0`[4] connect salloc_arb.io.in[9].bits.vc_sel.`0`[5], states[9].vc_sel.`0`[5] connect salloc_arb.io.in[9].bits.vc_sel.`0`[6], states[9].vc_sel.`0`[6] connect salloc_arb.io.in[9].bits.vc_sel.`0`[7], states[9].vc_sel.`0`[7] connect salloc_arb.io.in[9].bits.vc_sel.`0`[8], states[9].vc_sel.`0`[8] connect salloc_arb.io.in[9].bits.vc_sel.`0`[9], states[9].vc_sel.`0`[9] connect salloc_arb.io.in[9].bits.vc_sel.`1`[0], states[9].vc_sel.`1`[0] connect salloc_arb.io.in[9].bits.vc_sel.`2`[0], states[9].vc_sel.`2`[0] connect salloc_arb.io.in[9].bits.tail, input_buffer.io.deq[9].bits.tail node _T_133 = and(salloc_arb.io.in[9].ready, salloc_arb.io.in[9].valid) node _T_134 = and(_T_133, input_buffer.io.deq[9].bits.tail) when _T_134 : connect states[9].g, UInt<3>(0h0) connect input_buffer.io.deq[9].ready, salloc_arb.io.in[9].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = eq(salloc_arb.io.in[8].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_17 = and(salloc_arb.io.in[8].valid, _io_debug_sa_stall_T_16) node _io_debug_sa_stall_T_18 = eq(salloc_arb.io.in[9].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_19 = and(salloc_arb.io.in[9].valid, _io_debug_sa_stall_T_18) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 1, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_23) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 1, 0) node _io_debug_sa_stall_T_30 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_31 = bits(_io_debug_sa_stall_T_30, 1, 0) node _io_debug_sa_stall_T_32 = add(_io_debug_sa_stall_T_15, _io_debug_sa_stall_T_31) node _io_debug_sa_stall_T_33 = bits(_io_debug_sa_stall_T_32, 1, 0) node _io_debug_sa_stall_T_34 = add(_io_debug_sa_stall_T_29, _io_debug_sa_stall_T_33) node _io_debug_sa_stall_T_35 = bits(_io_debug_sa_stall_T_34, 2, 0) node _io_debug_sa_stall_T_36 = add(_io_debug_sa_stall_T_27, _io_debug_sa_stall_T_35) node _io_debug_sa_stall_T_37 = bits(_io_debug_sa_stall_T_36, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_37 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<4>, out_vid : UInt<4>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _io_in_vc_free_T_10 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_18 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_19 = mux(_io_in_vc_free_T_9, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_20 = mux(_io_in_vc_free_T_10, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_12) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_13) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_14) node _io_in_vc_free_T_24 = or(_io_in_vc_free_T_23, _io_in_vc_free_T_15) node _io_in_vc_free_T_25 = or(_io_in_vc_free_T_24, _io_in_vc_free_T_16) node _io_in_vc_free_T_26 = or(_io_in_vc_free_T_25, _io_in_vc_free_T_17) node _io_in_vc_free_T_27 = or(_io_in_vc_free_T_26, _io_in_vc_free_T_18) node _io_in_vc_free_T_28 = or(_io_in_vc_free_T_27, _io_in_vc_free_T_19) node _io_in_vc_free_T_29 = or(_io_in_vc_free_T_28, _io_in_vc_free_T_20) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_29 node _io_in_vc_free_T_30 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_31 = mux(_io_in_vc_free_T_30, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_31 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 9, 8) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 7, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 7, 4) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 3, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node salloc_outs_0_vid_hi_2 = bits(_salloc_outs_0_vid_T_3, 3, 2) node salloc_outs_0_vid_lo_2 = bits(_salloc_outs_0_vid_T_3, 1, 0) node _salloc_outs_0_vid_T_4 = orr(salloc_outs_0_vid_hi_2) node _salloc_outs_0_vid_T_5 = or(salloc_outs_0_vid_hi_2, salloc_outs_0_vid_lo_2) node _salloc_outs_0_vid_T_6 = bits(_salloc_outs_0_vid_T_5, 1, 1) node _salloc_outs_0_vid_T_7 = cat(_salloc_outs_0_vid_T_4, _salloc_outs_0_vid_T_6) node _salloc_outs_0_vid_T_8 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_7) node _salloc_outs_0_vid_T_9 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_8) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_9 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _vc_sel_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _vc_sel_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]} wire _vc_sel_WIRE : UInt<1>[10] node _vc_sel_T_10 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_20 = or(_vc_sel_T_10, _vc_sel_T_11) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_12) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_13) node _vc_sel_T_23 = or(_vc_sel_T_22, _vc_sel_T_14) node _vc_sel_T_24 = or(_vc_sel_T_23, _vc_sel_T_15) node _vc_sel_T_25 = or(_vc_sel_T_24, _vc_sel_T_16) node _vc_sel_T_26 = or(_vc_sel_T_25, _vc_sel_T_17) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_18) node _vc_sel_T_28 = or(_vc_sel_T_27, _vc_sel_T_19) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_28 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_29 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_32 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_37 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_38 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_39 = or(_vc_sel_T_29, _vc_sel_T_30) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_31) node _vc_sel_T_41 = or(_vc_sel_T_40, _vc_sel_T_32) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_33) node _vc_sel_T_43 = or(_vc_sel_T_42, _vc_sel_T_34) node _vc_sel_T_44 = or(_vc_sel_T_43, _vc_sel_T_35) node _vc_sel_T_45 = or(_vc_sel_T_44, _vc_sel_T_36) node _vc_sel_T_46 = or(_vc_sel_T_45, _vc_sel_T_37) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_38) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_47 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_58 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_59 = or(_vc_sel_T_58, _vc_sel_T_50) node _vc_sel_T_60 = or(_vc_sel_T_59, _vc_sel_T_51) node _vc_sel_T_61 = or(_vc_sel_T_60, _vc_sel_T_52) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_53) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_54) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_55) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_56) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_57) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_66 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_67 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_68 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_76 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_77 = or(_vc_sel_T_67, _vc_sel_T_68) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_69) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_70) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_71) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_72) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_73) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_74) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_75) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_76) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_85 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_91 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_92 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_93 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_94 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_95 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_96 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_88) node _vc_sel_T_98 = or(_vc_sel_T_97, _vc_sel_T_89) node _vc_sel_T_99 = or(_vc_sel_T_98, _vc_sel_T_90) node _vc_sel_T_100 = or(_vc_sel_T_99, _vc_sel_T_91) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_92) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_93) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_94) node _vc_sel_T_104 = or(_vc_sel_T_103, _vc_sel_T_95) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_104 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_105 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_106 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_107 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_108 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_109 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_110 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_111 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_112 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_113 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_115 = or(_vc_sel_T_105, _vc_sel_T_106) node _vc_sel_T_116 = or(_vc_sel_T_115, _vc_sel_T_107) node _vc_sel_T_117 = or(_vc_sel_T_116, _vc_sel_T_108) node _vc_sel_T_118 = or(_vc_sel_T_117, _vc_sel_T_109) node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_110) node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_111) node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_112) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_113) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_114) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_123 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_124 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_125 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_126 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_127 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_128 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_134 = or(_vc_sel_T_124, _vc_sel_T_125) node _vc_sel_T_135 = or(_vc_sel_T_134, _vc_sel_T_126) node _vc_sel_T_136 = or(_vc_sel_T_135, _vc_sel_T_127) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_128) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_129) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_130) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_131) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_132) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_133) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_142 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_151 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_152 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_153 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_145) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_146) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_147) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_148) node _vc_sel_T_158 = or(_vc_sel_T_157, _vc_sel_T_149) node _vc_sel_T_159 = or(_vc_sel_T_158, _vc_sel_T_150) node _vc_sel_T_160 = or(_vc_sel_T_159, _vc_sel_T_151) node _vc_sel_T_161 = or(_vc_sel_T_160, _vc_sel_T_152) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_161 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 node _vc_sel_T_162 = mux(_vc_sel_T, states[0].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_166 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_167 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_168 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_169 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_170 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_171 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[8], UInt<1>(0h0)) node _vc_sel_T_172 = or(_vc_sel_T_162, _vc_sel_T_163) node _vc_sel_T_173 = or(_vc_sel_T_172, _vc_sel_T_164) node _vc_sel_T_174 = or(_vc_sel_T_173, _vc_sel_T_165) node _vc_sel_T_175 = or(_vc_sel_T_174, _vc_sel_T_166) node _vc_sel_T_176 = or(_vc_sel_T_175, _vc_sel_T_167) node _vc_sel_T_177 = or(_vc_sel_T_176, _vc_sel_T_168) node _vc_sel_T_178 = or(_vc_sel_T_177, _vc_sel_T_169) node _vc_sel_T_179 = or(_vc_sel_T_178, _vc_sel_T_170) node _vc_sel_T_180 = or(_vc_sel_T_179, _vc_sel_T_171) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_180 connect _vc_sel_WIRE[8], _vc_sel_WIRE_9 node _vc_sel_T_181 = mux(_vc_sel_T, states[0].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_182 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_183 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_184 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_185 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_186 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_187 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_188 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_8, states[8].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_9, states[9].vc_sel.`0`[9], UInt<1>(0h0)) node _vc_sel_T_191 = or(_vc_sel_T_181, _vc_sel_T_182) node _vc_sel_T_192 = or(_vc_sel_T_191, _vc_sel_T_183) node _vc_sel_T_193 = or(_vc_sel_T_192, _vc_sel_T_184) node _vc_sel_T_194 = or(_vc_sel_T_193, _vc_sel_T_185) node _vc_sel_T_195 = or(_vc_sel_T_194, _vc_sel_T_186) node _vc_sel_T_196 = or(_vc_sel_T_195, _vc_sel_T_187) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_188) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_189) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_190) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_199 connect _vc_sel_WIRE[9], _vc_sel_WIRE_10 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_11 : UInt<1>[1] node _vc_sel_T_200 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_201 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_202 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_203 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_8, states[8].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_9, states[9].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_210 = or(_vc_sel_T_200, _vc_sel_T_201) node _vc_sel_T_211 = or(_vc_sel_T_210, _vc_sel_T_202) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_203) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_204) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_205) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_206) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_207) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_208) node _vc_sel_T_218 = or(_vc_sel_T_217, _vc_sel_T_209) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_218 connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12 connect vc_sel.`1`, _vc_sel_WIRE_11 wire _vc_sel_WIRE_13 : UInt<1>[1] node _vc_sel_T_219 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_226 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_227 = mux(_vc_sel_T_8, states[8].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_228 = mux(_vc_sel_T_9, states[9].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_229 = or(_vc_sel_T_219, _vc_sel_T_220) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_221) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_222) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_223) node _vc_sel_T_233 = or(_vc_sel_T_232, _vc_sel_T_224) node _vc_sel_T_234 = or(_vc_sel_T_233, _vc_sel_T_225) node _vc_sel_T_235 = or(_vc_sel_T_234, _vc_sel_T_226) node _vc_sel_T_236 = or(_vc_sel_T_235, _vc_sel_T_227) node _vc_sel_T_237 = or(_vc_sel_T_236, _vc_sel_T_228) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_237 connect _vc_sel_WIRE_13[0], _vc_sel_WIRE_14 connect vc_sel.`2`, _vc_sel_WIRE_13 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node _channel_oh_T_6 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`0`[8]) node channel_oh_0 = or(_channel_oh_T_7, vc_sel.`0`[9]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_lo_hi = cat(virt_channel_lo_hi_hi, vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[6], vc_sel.`0`[5]) node virt_channel_hi_hi_hi = cat(vc_sel.`0`[9], vc_sel.`0`[8]) node virt_channel_hi_hi = cat(virt_channel_hi_hi_hi, vc_sel.`0`[7]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 9, 8) node virt_channel_lo_1 = bits(_virt_channel_T, 7, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 7, 4) node virt_channel_lo_2 = bits(_virt_channel_T_2, 3, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node virt_channel_hi_3 = bits(_virt_channel_T_4, 3, 2) node virt_channel_lo_3 = bits(_virt_channel_T_4, 1, 0) node _virt_channel_T_5 = orr(virt_channel_hi_3) node _virt_channel_T_6 = or(virt_channel_hi_3, virt_channel_lo_3) node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1) node _virt_channel_T_8 = cat(_virt_channel_T_5, _virt_channel_T_7) node _virt_channel_T_9 = cat(_virt_channel_T_3, _virt_channel_T_8) node _virt_channel_T_10 = cat(_virt_channel_T_1, _virt_channel_T_9) node _virt_channel_T_11 = mux(channel_oh_0, _virt_channel_T_10, UInt<1>(0h0)) node _virt_channel_T_12 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_13 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_14 = or(_virt_channel_T_11, _virt_channel_T_12) node _virt_channel_T_15 = or(_virt_channel_T_14, _virt_channel_T_13) wire virt_channel : UInt<4> connect virt_channel, _virt_channel_T_15 node _T_135 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_135 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_payload_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_17 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_18 = mux(_salloc_outs_0_flit_payload_T_8, input_buffer.io.deq[8].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_19 = mux(_salloc_outs_0_flit_payload_T_9, input_buffer.io.deq[9].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_23 = or(_salloc_outs_0_flit_payload_T_22, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_24 = or(_salloc_outs_0_flit_payload_T_23, _salloc_outs_0_flit_payload_T_15) node _salloc_outs_0_flit_payload_T_25 = or(_salloc_outs_0_flit_payload_T_24, _salloc_outs_0_flit_payload_T_16) node _salloc_outs_0_flit_payload_T_26 = or(_salloc_outs_0_flit_payload_T_25, _salloc_outs_0_flit_payload_T_17) node _salloc_outs_0_flit_payload_T_27 = or(_salloc_outs_0_flit_payload_T_26, _salloc_outs_0_flit_payload_T_18) node _salloc_outs_0_flit_payload_T_28 = or(_salloc_outs_0_flit_payload_T_27, _salloc_outs_0_flit_payload_T_19) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_28 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_head_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_17 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_18 = mux(_salloc_outs_0_flit_head_T_8, input_buffer.io.deq[8].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_19 = mux(_salloc_outs_0_flit_head_T_9, input_buffer.io.deq[9].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_23 = or(_salloc_outs_0_flit_head_T_22, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_24 = or(_salloc_outs_0_flit_head_T_23, _salloc_outs_0_flit_head_T_15) node _salloc_outs_0_flit_head_T_25 = or(_salloc_outs_0_flit_head_T_24, _salloc_outs_0_flit_head_T_16) node _salloc_outs_0_flit_head_T_26 = or(_salloc_outs_0_flit_head_T_25, _salloc_outs_0_flit_head_T_17) node _salloc_outs_0_flit_head_T_27 = or(_salloc_outs_0_flit_head_T_26, _salloc_outs_0_flit_head_T_18) node _salloc_outs_0_flit_head_T_28 = or(_salloc_outs_0_flit_head_T_27, _salloc_outs_0_flit_head_T_19) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_28 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_tail_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_17 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_18 = mux(_salloc_outs_0_flit_tail_T_8, input_buffer.io.deq[8].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_19 = mux(_salloc_outs_0_flit_tail_T_9, input_buffer.io.deq[9].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_23 = or(_salloc_outs_0_flit_tail_T_22, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_24 = or(_salloc_outs_0_flit_tail_T_23, _salloc_outs_0_flit_tail_T_15) node _salloc_outs_0_flit_tail_T_25 = or(_salloc_outs_0_flit_tail_T_24, _salloc_outs_0_flit_tail_T_16) node _salloc_outs_0_flit_tail_T_26 = or(_salloc_outs_0_flit_tail_T_25, _salloc_outs_0_flit_tail_T_17) node _salloc_outs_0_flit_tail_T_27 = or(_salloc_outs_0_flit_tail_T_26, _salloc_outs_0_flit_tail_T_18) node _salloc_outs_0_flit_tail_T_28 = or(_salloc_outs_0_flit_tail_T_27, _salloc_outs_0_flit_tail_T_19) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_28 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_flow_T_8 = bits(salloc_arb.io.chosen_oh[0], 8, 8) node _salloc_outs_0_flit_flow_T_9 = bits(salloc_arb.io.chosen_oh[0], 9, 9) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>} node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_23 = or(_salloc_outs_0_flit_flow_T_22, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_24 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_25 = or(_salloc_outs_0_flit_flow_T_24, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_25, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_18) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_27, _salloc_outs_0_flit_flow_T_19) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_28 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_30) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_31) node _salloc_outs_0_flit_flow_T_41 = or(_salloc_outs_0_flit_flow_T_40, _salloc_outs_0_flit_flow_T_32) node _salloc_outs_0_flit_flow_T_42 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_43 = or(_salloc_outs_0_flit_flow_T_42, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_44 = or(_salloc_outs_0_flit_flow_T_43, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_45 = or(_salloc_outs_0_flit_flow_T_44, _salloc_outs_0_flit_flow_T_36) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_45, _salloc_outs_0_flit_flow_T_37) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_38) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_47 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_48 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_49 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_50 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_51 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_52 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_49) node _salloc_outs_0_flit_flow_T_59 = or(_salloc_outs_0_flit_flow_T_58, _salloc_outs_0_flit_flow_T_50) node _salloc_outs_0_flit_flow_T_60 = or(_salloc_outs_0_flit_flow_T_59, _salloc_outs_0_flit_flow_T_51) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_60, _salloc_outs_0_flit_flow_T_52) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_53) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_57) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_66 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_67 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_67, _salloc_outs_0_flit_flow_T_68) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_83 = or(_salloc_outs_0_flit_flow_T_82, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_84 = or(_salloc_outs_0_flit_flow_T_83, _salloc_outs_0_flit_flow_T_75) node _salloc_outs_0_flit_flow_T_85 = or(_salloc_outs_0_flit_flow_T_84, _salloc_outs_0_flit_flow_T_76) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_85 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_86 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_87 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_88 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_89 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_90 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_91 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_92 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_93 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_94 = mux(_salloc_outs_0_flit_flow_T_8, states[8].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_95 = mux(_salloc_outs_0_flit_flow_T_9, states[9].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_96 = or(_salloc_outs_0_flit_flow_T_86, _salloc_outs_0_flit_flow_T_87) node _salloc_outs_0_flit_flow_T_97 = or(_salloc_outs_0_flit_flow_T_96, _salloc_outs_0_flit_flow_T_88) node _salloc_outs_0_flit_flow_T_98 = or(_salloc_outs_0_flit_flow_T_97, _salloc_outs_0_flit_flow_T_89) node _salloc_outs_0_flit_flow_T_99 = or(_salloc_outs_0_flit_flow_T_98, _salloc_outs_0_flit_flow_T_90) node _salloc_outs_0_flit_flow_T_100 = or(_salloc_outs_0_flit_flow_T_99, _salloc_outs_0_flit_flow_T_91) node _salloc_outs_0_flit_flow_T_101 = or(_salloc_outs_0_flit_flow_T_100, _salloc_outs_0_flit_flow_T_92) node _salloc_outs_0_flit_flow_T_102 = or(_salloc_outs_0_flit_flow_T_101, _salloc_outs_0_flit_flow_T_93) node _salloc_outs_0_flit_flow_T_103 = or(_salloc_outs_0_flit_flow_T_102, _salloc_outs_0_flit_flow_T_94) node _salloc_outs_0_flit_flow_T_104 = or(_salloc_outs_0_flit_flow_T_103, _salloc_outs_0_flit_flow_T_95) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_104 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`0`[6] invalidate states[0].vc_sel.`0`[7] invalidate states[0].vc_sel.`0`[8] invalidate states[0].vc_sel.`0`[9] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`2`[0] invalidate states[0].g invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`0`[3] invalidate states[1].vc_sel.`0`[4] invalidate states[1].vc_sel.`0`[5] invalidate states[1].vc_sel.`0`[6] invalidate states[1].vc_sel.`0`[7] invalidate states[1].vc_sel.`0`[8] invalidate states[1].vc_sel.`0`[9] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`2`[0] invalidate states[1].g connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`0`[2], UInt<1>(0h0) connect states[2].vc_sel.`0`[3], UInt<1>(0h0) connect states[2].vc_sel.`0`[4], UInt<1>(0h0) connect states[2].vc_sel.`0`[5], UInt<1>(0h0) connect states[2].vc_sel.`0`[6], UInt<1>(0h0) connect states[2].vc_sel.`0`[7], UInt<1>(0h0) connect states[2].vc_sel.`0`[8], UInt<1>(0h0) connect states[2].vc_sel.`0`[9], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`0`[1], UInt<1>(0h0) connect states[3].vc_sel.`0`[2], UInt<1>(0h0) connect states[3].vc_sel.`0`[3], UInt<1>(0h0) connect states[3].vc_sel.`0`[4], UInt<1>(0h0) connect states[3].vc_sel.`0`[5], UInt<1>(0h0) connect states[3].vc_sel.`0`[6], UInt<1>(0h0) connect states[3].vc_sel.`0`[7], UInt<1>(0h0) connect states[3].vc_sel.`0`[8], UInt<1>(0h0) connect states[3].vc_sel.`0`[9], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`0`[4], UInt<1>(0h0) connect states[4].vc_sel.`0`[5], UInt<1>(0h0) connect states[4].vc_sel.`0`[6], UInt<1>(0h0) connect states[4].vc_sel.`0`[7], UInt<1>(0h0) connect states[4].vc_sel.`0`[8], UInt<1>(0h0) connect states[4].vc_sel.`0`[9], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`0`[1], UInt<1>(0h0) connect states[5].vc_sel.`0`[2], UInt<1>(0h0) connect states[5].vc_sel.`0`[3], UInt<1>(0h0) connect states[5].vc_sel.`0`[4], UInt<1>(0h0) connect states[5].vc_sel.`0`[5], UInt<1>(0h0) connect states[5].vc_sel.`0`[6], UInt<1>(0h0) connect states[5].vc_sel.`0`[7], UInt<1>(0h0) connect states[5].vc_sel.`0`[8], UInt<1>(0h0) connect states[5].vc_sel.`0`[9], UInt<1>(0h0) connect states[6].vc_sel.`0`[0], UInt<1>(0h0) connect states[6].vc_sel.`0`[1], UInt<1>(0h0) connect states[6].vc_sel.`0`[2], UInt<1>(0h0) connect states[6].vc_sel.`0`[3], UInt<1>(0h0) connect states[6].vc_sel.`0`[4], UInt<1>(0h0) connect states[6].vc_sel.`0`[5], UInt<1>(0h0) connect states[6].vc_sel.`0`[6], UInt<1>(0h0) connect states[6].vc_sel.`0`[7], UInt<1>(0h0) connect states[6].vc_sel.`0`[8], UInt<1>(0h0) connect states[6].vc_sel.`0`[9], UInt<1>(0h0) connect states[7].vc_sel.`0`[0], UInt<1>(0h0) connect states[7].vc_sel.`0`[1], UInt<1>(0h0) connect states[7].vc_sel.`0`[2], UInt<1>(0h0) connect states[7].vc_sel.`0`[3], UInt<1>(0h0) connect states[7].vc_sel.`0`[4], UInt<1>(0h0) connect states[7].vc_sel.`0`[5], UInt<1>(0h0) connect states[7].vc_sel.`0`[6], UInt<1>(0h0) connect states[7].vc_sel.`0`[7], UInt<1>(0h0) connect states[7].vc_sel.`0`[8], UInt<1>(0h0) connect states[7].vc_sel.`0`[9], UInt<1>(0h0) connect states[8].vc_sel.`0`[0], UInt<1>(0h0) connect states[8].vc_sel.`0`[1], UInt<1>(0h0) connect states[8].vc_sel.`0`[2], UInt<1>(0h0) connect states[8].vc_sel.`0`[3], UInt<1>(0h0) connect states[8].vc_sel.`0`[4], UInt<1>(0h0) connect states[8].vc_sel.`0`[5], UInt<1>(0h0) connect states[8].vc_sel.`0`[6], UInt<1>(0h0) connect states[8].vc_sel.`0`[7], UInt<1>(0h0) connect states[8].vc_sel.`0`[8], UInt<1>(0h0) connect states[8].vc_sel.`0`[9], UInt<1>(0h0) connect states[9].vc_sel.`0`[0], UInt<1>(0h0) connect states[9].vc_sel.`0`[1], UInt<1>(0h0) connect states[9].vc_sel.`0`[2], UInt<1>(0h0) connect states[9].vc_sel.`0`[3], UInt<1>(0h0) connect states[9].vc_sel.`0`[4], UInt<1>(0h0) connect states[9].vc_sel.`0`[5], UInt<1>(0h0) connect states[9].vc_sel.`0`[6], UInt<1>(0h0) connect states[9].vc_sel.`0`[7], UInt<1>(0h0) connect states[9].vc_sel.`0`[8], UInt<1>(0h0) connect states[9].vc_sel.`0`[9], UInt<1>(0h0) node _T_136 = asUInt(reset) when _T_136 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0) connect states[8].g, UInt<3>(0h0) connect states[9].g, UInt<3>(0h0)	module InputUnit_111( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_8, // @[InputUnit.scala:170:14] input io_out_credit_available_0_9, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [9:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_9; // @[InputUnit.scala:266:32] wire vcalloc_vals_8; // @[InputUnit.scala:266:32] wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_8_g; // @[InputUnit.scala:192:19] reg states_8_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_8_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_9_g; // @[InputUnit.scala:192:19] reg states_9_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_9_vc_sel_1_0; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19] reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [9:0] mask; // @[InputUnit.scala:250:21] wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, 2'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_2 ? 20'h1000 : vcalloc_vals_3 ? 20'h2000 : vcalloc_vals_4 ? 20'h4000 : vcalloc_vals_5 ? 20'h8000 : vcalloc_vals_6 ? 20'h10000 : vcalloc_vals_7 ? 20'h20000 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71] wire [9:0] vcalloc_sel = vcalloc_filter[9:0] \| vcalloc_filter[19:10]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_2 \| vcalloc_vals_3 \| vcalloc_vals_4 \| vcalloc_vals_5 \| vcalloc_vals_6 \| vcalloc_vals_7 \| vcalloc_vals_8 \| vcalloc_vals_9; // @[package.scala:81:59] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36] wire _GEN_8 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module Tile_57 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_313 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_57( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_313 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ProbePicker : input clock : Clock input reset : Reset output auto : { flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_1.d.bits.corrupt invalidate nodeIn_1.d.bits.data invalidate nodeIn_1.d.bits.denied invalidate nodeIn_1.d.bits.sink invalidate nodeIn_1.d.bits.source invalidate nodeIn_1.d.bits.size invalidate nodeIn_1.d.bits.param invalidate nodeIn_1.d.bits.opcode invalidate nodeIn_1.d.valid invalidate nodeIn_1.d.ready invalidate nodeIn_1.a.bits.corrupt invalidate nodeIn_1.a.bits.data invalidate nodeIn_1.a.bits.mask invalidate nodeIn_1.a.bits.address invalidate nodeIn_1.a.bits.source invalidate nodeIn_1.a.bits.size invalidate nodeIn_1.a.bits.param invalidate nodeIn_1.a.bits.opcode invalidate nodeIn_1.a.valid invalidate nodeIn_1.a.ready inst monitor of TLMonitor_35 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready inst monitor_1 of TLMonitor_36 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, nodeIn_1.d.valid connect monitor_1.io.in.d.ready, nodeIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, nodeIn_1.a.valid connect monitor_1.io.in.a.ready, nodeIn_1.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect nodeIn, auto.in_0 connect nodeIn_1, auto.in_1 connect nodeOut, nodeIn connect x1_nodeOut, nodeIn_1	module ProbePicker( // @[ProbePicker.scala:42:9] input clock, // @[ProbePicker.scala:42:9] input reset, // @[ProbePicker.scala:42:9] output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_1_a_valid_0 = auto_in_1_a_valid; // @[ProbePicker.scala:42:9] wire [2:0] auto_in_1_a_bits_opcode_0 = auto_in_1_a_bits_opcode; // @[ProbePicker.scala:42:9] wire [2:0] auto_in_1_a_bits_param_0 = auto_in_1_a_bits_param; // @[ProbePicker.scala:42:9] wire [2:0] auto_in_1_a_bits_size_0 = auto_in_1_a_bits_size; // @[ProbePicker.scala:42:9] wire [3:0] auto_in_1_a_bits_source_0 = auto_in_1_a_bits_source; // @[ProbePicker.scala:42:9] wire [27:0] auto_in_1_a_bits_address_0 = auto_in_1_a_bits_address; // @[ProbePicker.scala:42:9] wire [7:0] auto_in_1_a_bits_mask_0 = auto_in_1_a_bits_mask; // @[ProbePicker.scala:42:9] wire [63:0] auto_in_1_a_bits_data_0 = auto_in_1_a_bits_data; // @[ProbePicker.scala:42:9] wire auto_in_1_a_bits_corrupt_0 = auto_in_1_a_bits_corrupt; // @[ProbePicker.scala:42:9] wire auto_in_1_d_ready_0 = auto_in_1_d_ready; // @[ProbePicker.scala:42:9] wire auto_in_0_a_valid_0 = auto_in_0_a_valid; // @[ProbePicker.scala:42:9] wire [2:0] auto_in_0_a_bits_opcode_0 = auto_in_0_a_bits_opcode; // @[ProbePicker.scala:42:9] wire [2:0] auto_in_0_a_bits_param_0 = auto_in_0_a_bits_param; // @[ProbePicker.scala:42:9] wire [2:0] auto_in_0_a_bits_size_0 = auto_in_0_a_bits_size; // @[ProbePicker.scala:42:9] wire [3:0] auto_in_0_a_bits_source_0 = auto_in_0_a_bits_source; // @[ProbePicker.scala:42:9] wire [31:0] auto_in_0_a_bits_address_0 = auto_in_0_a_bits_address; // @[ProbePicker.scala:42:9] wire [7:0] auto_in_0_a_bits_mask_0 = auto_in_0_a_bits_mask; // @[ProbePicker.scala:42:9] wire [63:0] auto_in_0_a_bits_data_0 = auto_in_0_a_bits_data; // @[ProbePicker.scala:42:9] wire auto_in_0_a_bits_corrupt_0 = auto_in_0_a_bits_corrupt; // @[ProbePicker.scala:42:9] wire auto_in_0_d_ready_0 = auto_in_0_d_ready; // @[ProbePicker.scala:42:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[ProbePicker.scala:42:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[ProbePicker.scala:42:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[ProbePicker.scala:42:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[ProbePicker.scala:42:9] wire [2:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[ProbePicker.scala:42:9] wire [3:0] auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[ProbePicker.scala:42:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[ProbePicker.scala:42:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[ProbePicker.scala:42:9] wire [63:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[ProbePicker.scala:42:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[ProbePicker.scala:42:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[ProbePicker.scala:42:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[ProbePicker.scala:42:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[ProbePicker.scala:42:9] wire [2:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[ProbePicker.scala:42:9] wire [3:0] auto_out_0_d_bits_source_0 = auto_out_0_d_bits_source; // @[ProbePicker.scala:42:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[ProbePicker.scala:42:9] wire [63:0] auto_out_0_d_bits_data_0 = auto_out_0_d_bits_data; // @[ProbePicker.scala:42:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[ProbePicker.scala:42:9] wire auto_in_0_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9] wire auto_out_0_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9] wire nodeIn_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9] wire nodeOut_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9] wire [1:0] auto_in_0_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9] wire [1:0] auto_out_0_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9] wire nodeIn_1_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9] wire nodeIn_1_a_valid = auto_in_1_a_valid_0; // @[ProbePicker.scala:42:9] wire [2:0] nodeIn_1_a_bits_opcode = auto_in_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9] wire [2:0] nodeIn_1_a_bits_param = auto_in_1_a_bits_param_0; // @[ProbePicker.scala:42:9] wire [2:0] nodeIn_1_a_bits_size = auto_in_1_a_bits_size_0; // @[ProbePicker.scala:42:9] wire [3:0] nodeIn_1_a_bits_source = auto_in_1_a_bits_source_0; // @[ProbePicker.scala:42:9] wire [27:0] nodeIn_1_a_bits_address = auto_in_1_a_bits_address_0; // @[ProbePicker.scala:42:9] wire [7:0] nodeIn_1_a_bits_mask = auto_in_1_a_bits_mask_0; // @[ProbePicker.scala:42:9] wire [63:0] nodeIn_1_a_bits_data = auto_in_1_a_bits_data_0; // @[ProbePicker.scala:42:9] wire nodeIn_1_a_bits_corrupt = auto_in_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9] wire nodeIn_1_d_ready = auto_in_1_d_ready_0; // @[ProbePicker.scala:42:9] wire nodeIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_0_a_valid_0; // @[ProbePicker.scala:42:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9] wire [2:0] nodeIn_a_bits_param = auto_in_0_a_bits_param_0; // @[ProbePicker.scala:42:9] wire [2:0] nodeIn_a_bits_size = auto_in_0_a_bits_size_0; // @[ProbePicker.scala:42:9] wire [3:0] nodeIn_a_bits_source = auto_in_0_a_bits_source_0; // @[ProbePicker.scala:42:9] wire [31:0] nodeIn_a_bits_address = auto_in_0_a_bits_address_0; // @[ProbePicker.scala:42:9] wire [7:0] nodeIn_a_bits_mask = auto_in_0_a_bits_mask_0; // @[ProbePicker.scala:42:9] wire [63:0] nodeIn_a_bits_data = auto_in_0_a_bits_data_0; // @[ProbePicker.scala:42:9] wire nodeIn_a_bits_corrupt = auto_in_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9] wire nodeIn_d_ready = auto_in_0_d_ready_0; // @[ProbePicker.scala:42:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[ProbePicker.scala:42:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[ProbePicker.scala:42:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[ProbePicker.scala:42:9] wire [2:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[ProbePicker.scala:42:9] wire [3:0] x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[ProbePicker.scala:42:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[ProbePicker.scala:42:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[ProbePicker.scala:42:9] wire [63:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[ProbePicker.scala:42:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[ProbePicker.scala:42:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[ProbePicker.scala:42:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9] wire [2:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[ProbePicker.scala:42:9] wire [3:0] nodeOut_d_bits_source = auto_out_0_d_bits_source_0; // @[ProbePicker.scala:42:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[ProbePicker.scala:42:9] wire [63:0] nodeOut_d_bits_data = auto_out_0_d_bits_data_0; // @[ProbePicker.scala:42:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9] wire auto_in_1_a_ready_0; // @[ProbePicker.scala:42:9] wire [2:0] auto_in_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9] wire [1:0] auto_in_1_d_bits_param_0; // @[ProbePicker.scala:42:9] wire [2:0] auto_in_1_d_bits_size_0; // @[ProbePicker.scala:42:9] wire [3:0] auto_in_1_d_bits_source_0; // @[ProbePicker.scala:42:9] wire auto_in_1_d_bits_sink_0; // @[ProbePicker.scala:42:9] wire auto_in_1_d_bits_denied_0; // @[ProbePicker.scala:42:9] wire [63:0] auto_in_1_d_bits_data_0; // @[ProbePicker.scala:42:9] wire auto_in_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9] wire auto_in_1_d_valid_0; // @[ProbePicker.scala:42:9] wire auto_in_0_a_ready_0; // @[ProbePicker.scala:42:9] wire [2:0] auto_in_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9] wire [2:0] auto_in_0_d_bits_size_0; // @[ProbePicker.scala:42:9] wire [3:0] auto_in_0_d_bits_source_0; // @[ProbePicker.scala:42:9] wire auto_in_0_d_bits_denied_0; // @[ProbePicker.scala:42:9] wire [63:0] auto_in_0_d_bits_data_0; // @[ProbePicker.scala:42:9] wire auto_in_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9] wire auto_in_0_d_valid_0; // @[ProbePicker.scala:42:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9] wire [2:0] auto_out_1_a_bits_param_0; // @[ProbePicker.scala:42:9] wire [2:0] auto_out_1_a_bits_size_0; // @[ProbePicker.scala:42:9] wire [3:0] auto_out_1_a_bits_source_0; // @[ProbePicker.scala:42:9] wire [27:0] auto_out_1_a_bits_address_0; // @[ProbePicker.scala:42:9] wire [7:0] auto_out_1_a_bits_mask_0; // @[ProbePicker.scala:42:9] wire [63:0] auto_out_1_a_bits_data_0; // @[ProbePicker.scala:42:9] wire auto_out_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9] wire auto_out_1_a_valid_0; // @[ProbePicker.scala:42:9] wire auto_out_1_d_ready_0; // @[ProbePicker.scala:42:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9] wire [2:0] auto_out_0_a_bits_param_0; // @[ProbePicker.scala:42:9] wire [2:0] auto_out_0_a_bits_size_0; // @[ProbePicker.scala:42:9] wire [3:0] auto_out_0_a_bits_source_0; // @[ProbePicker.scala:42:9] wire [31:0] auto_out_0_a_bits_address_0; // @[ProbePicker.scala:42:9] wire [7:0] auto_out_0_a_bits_mask_0; // @[ProbePicker.scala:42:9] wire [63:0] auto_out_0_a_bits_data_0; // @[ProbePicker.scala:42:9] wire auto_out_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9] wire auto_out_0_a_valid_0; // @[ProbePicker.scala:42:9] wire auto_out_0_d_ready_0; // @[ProbePicker.scala:42:9] assign auto_in_0_a_ready_0 = nodeIn_a_ready; // @[ProbePicker.scala:42:9] assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_0_d_valid_0 = nodeIn_d_valid; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_size_0 = nodeIn_d_bits_size; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_source_0 = nodeIn_d_bits_source; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_denied_0 = nodeIn_d_bits_denied; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_data_0 = nodeIn_d_bits_data; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_in_1_a_ready_0 = nodeIn_1_a_ready; // @[ProbePicker.scala:42:9] assign x1_nodeOut_a_valid = nodeIn_1_a_valid; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_param = nodeIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_size = nodeIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_source = nodeIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_mask = nodeIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_corrupt = nodeIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_d_ready = nodeIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_in_1_d_valid_0 = nodeIn_1_d_valid; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_opcode_0 = nodeIn_1_d_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_param_0 = nodeIn_1_d_bits_param; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_size_0 = nodeIn_1_d_bits_size; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_source_0 = nodeIn_1_d_bits_source; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_sink_0 = nodeIn_1_d_bits_sink; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_denied_0 = nodeIn_1_d_bits_denied; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_data_0 = nodeIn_1_d_bits_data; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_corrupt_0 = nodeIn_1_d_bits_corrupt; // @[ProbePicker.scala:42:9] assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_param_0 = nodeOut_a_bits_param; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_size_0 = nodeOut_a_bits_size; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_source_0 = nodeOut_a_bits_source; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_mask_0 = nodeOut_a_bits_mask; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[ProbePicker.scala:42:9] assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_1_a_ready = x1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_param_0 = x1_nodeOut_a_bits_param; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_size_0 = x1_nodeOut_a_bits_size; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_source_0 = x1_nodeOut_a_bits_source; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_mask_0 = x1_nodeOut_a_bits_mask; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_corrupt_0 = x1_nodeOut_a_bits_corrupt; // @[ProbePicker.scala:42:9] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[ProbePicker.scala:42:9] assign nodeIn_1_d_valid = x1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_1_d_bits_opcode = x1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_1_d_bits_param = x1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_1_d_bits_size = x1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_1_d_bits_source = x1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_1_d_bits_sink = x1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_1_d_bits_denied = x1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_1_d_bits_data = x1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign nodeIn_1_d_bits_corrupt = x1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] TLMonitor_35 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_36 monitor_1 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_1_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_1_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_1_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_1_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_1_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_1_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_1_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_1_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_1_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_1_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_1_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_1_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_1_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_1_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_1_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_1_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_1_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_1_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_1_a_ready = auto_in_1_a_ready_0; // @[ProbePicker.scala:42:9] assign auto_in_1_d_valid = auto_in_1_d_valid_0; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_opcode = auto_in_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_param = auto_in_1_d_bits_param_0; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_size = auto_in_1_d_bits_size_0; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_source = auto_in_1_d_bits_source_0; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_sink = auto_in_1_d_bits_sink_0; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_denied = auto_in_1_d_bits_denied_0; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_data = auto_in_1_d_bits_data_0; // @[ProbePicker.scala:42:9] assign auto_in_1_d_bits_corrupt = auto_in_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9] assign auto_in_0_a_ready = auto_in_0_a_ready_0; // @[ProbePicker.scala:42:9] assign auto_in_0_d_valid = auto_in_0_d_valid_0; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_opcode = auto_in_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_size = auto_in_0_d_bits_size_0; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_source = auto_in_0_d_bits_source_0; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_denied = auto_in_0_d_bits_denied_0; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_data = auto_in_0_d_bits_data_0; // @[ProbePicker.scala:42:9] assign auto_in_0_d_bits_corrupt = auto_in_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_param = auto_out_1_a_bits_param_0; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_size = auto_out_1_a_bits_size_0; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_source = auto_out_1_a_bits_source_0; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_mask = auto_out_1_a_bits_mask_0; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[ProbePicker.scala:42:9] assign auto_out_1_a_bits_corrupt = auto_out_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[ProbePicker.scala:42:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_param = auto_out_0_a_bits_param_0; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_size = auto_out_0_a_bits_size_0; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_source = auto_out_0_a_bits_source_0; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_mask = auto_out_0_a_bits_mask_0; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[ProbePicker.scala:42:9] assign auto_out_0_a_bits_corrupt = auto_out_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[ProbePicker.scala:42:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLROM : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_38 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect nodeIn, auto.in wire rom : UInt<64>[512] connect rom[0], UInt<64>(0h405051300000517) connect rom[1], UInt<64>(0h301022f330551073) connect rom[2], UInt<64>(0h12f2934122d293) connect rom[3], UInt<64>(0h3030107300028863) connect rom[4], UInt<64>(0h3445307322200513) connect rom[5], UInt<64>(0h3045107300800513) connect rom[6], UInt<64>(0h1050007330052073) connect rom[7], UInt<64>(0hffdff06f) connect rom[8], UInt<64>(0hf1402573020005b7) connect rom[9], UInt<64>(0h380006f00050463) connect rom[10], UInt<64>(0h10069300458613) connect rom[11], UInt<64>(0h46061300d62023) connect rom[12], UInt<64>(0hfe069ae3ffc62683) connect rom[13], UInt<64>(0h2c0006f) connect rom[14], UInt<64>(0h0) connect rom[15], UInt<64>(0h0) connect rom[16], UInt<64>(0h5a283f81ff06f) connect rom[17], UInt<64>(0h251513fe029ee3) connect rom[18], UInt<64>(0h5a02300b505b3) connect rom[19], UInt<64>(0h5250300001537) connect rom[20], UInt<64>(0hf140257334151073) connect rom[21], UInt<64>(0h185859300000597) connect rom[22], UInt<64>(0h3006307308000613) connect rom[23], UInt<64>(0h1330200073) connect rom[24], UInt<64>(0h1b0b0000edfe0dd0) connect rom[25], UInt<64>(0h5809000038000000) connect rom[26], UInt<64>(0h1100000028000000) connect rom[27], UInt<64>(0h10000000) connect rom[28], UInt<64>(0h20090000c3010000) connect rom[29], UInt<64>(0h0) connect rom[30], UInt<64>(0h0) connect rom[31], UInt<64>(0h1000000) connect rom[32], UInt<64>(0h400000003000000) connect rom[33], UInt<64>(0h100000000000000) connect rom[34], UInt<64>(0h400000003000000) connect rom[35], UInt<64>(0h10000000f000000) connect rom[36], UInt<64>(0h1500000003000000) connect rom[37], UInt<64>(0h2d6263751b000000) connect rom[38], UInt<64>(0h706968632c726162) connect rom[39], UInt<64>(0h7665642d64726179) connect rom[40], UInt<64>(0h300000000000000) connect rom[41], UInt<64>(0h2600000011000000) connect rom[42], UInt<64>(0h2c7261622d626375) connect rom[43], UInt<64>(0h6472617970696863) connect rom[44], UInt<64>(0h100000000000000) connect rom[45], UInt<64>(0h73657361696c61) connect rom[46], UInt<64>(0h1500000003000000) connect rom[47], UInt<64>(0h636f732f2c000000) connect rom[48], UInt<64>(0h406c61697265732f) connect rom[49], UInt<64>(0h3030303032303031) connect rom[50], UInt<64>(0h200000000000000) connect rom[51], UInt<64>(0h736f686301000000) connect rom[52], UInt<64>(0h300000000006e65) connect rom[53], UInt<64>(0h3400000015000000) connect rom[54], UInt<64>(0h7265732f636f732f) connect rom[55], UInt<64>(0h32303031406c6169) connect rom[56], UInt<64>(0h30303030) connect rom[57], UInt<64>(0h100000002000000) connect rom[58], UInt<64>(0h73757063) connect rom[59], UInt<64>(0h400000003000000) connect rom[60], UInt<64>(0h100000000000000) connect rom[61], UInt<64>(0h400000003000000) connect rom[62], UInt<64>(0hf000000) connect rom[63], UInt<64>(0h400000003000000) connect rom[64], UInt<64>(0h20a1070040000000) connect rom[65], UInt<64>(0h4075706301000000) connect rom[66], UInt<64>(0h300000000000030) connect rom[67], UInt<64>(0h5300000004000000) connect rom[68], UInt<64>(0h300000000000000) connect rom[69], UInt<64>(0h1b00000015000000) connect rom[70], UInt<64>(0h722c657669666973) connect rom[71], UInt<64>(0h72003074656b636f) connect rom[72], UInt<64>(0h76637369) connect rom[73], UInt<64>(0h400000003000000) connect rom[74], UInt<64>(0h75706363000000) connect rom[75], UInt<64>(0h400000003000000) connect rom[76], UInt<64>(0h10000006f000000) connect rom[77], UInt<64>(0h400000003000000) connect rom[78], UInt<64>(0h400000008e000000) connect rom[79], UInt<64>(0h400000003000000) connect rom[80], UInt<64>(0h40000000a1000000) connect rom[81], UInt<64>(0h400000003000000) connect rom[82], UInt<64>(0h100000ae000000) connect rom[83], UInt<64>(0h400000003000000) connect rom[84], UInt<64>(0hbb000000) connect rom[85], UInt<64>(0h2500000003000000) connect rom[86], UInt<64>(0h32337672bf000000) connect rom[87], UInt<64>(0h7363697a63616d69) connect rom[88], UInt<64>(0h636e6566697a5f72) connect rom[89], UInt<64>(0h6d7068697a5f6965) connect rom[90], UInt<64>(0h74656b636f72785f) connect rom[91], UInt<64>(0h300000000000000) connect rom[92], UInt<64>(0hc900000004000000) connect rom[93], UInt<64>(0h300000004000000) connect rom[94], UInt<64>(0hde00000004000000) connect rom[95], UInt<64>(0h300000008000000) connect rom[96], UInt<64>(0hef00000004000000) connect rom[97], UInt<64>(0h300000001000000) connect rom[98], UInt<64>(0hfb00000005000000) connect rom[99], UInt<64>(0h79616b6f) connect rom[100], UInt<64>(0h400000003000000) connect rom[101], UInt<64>(0h20a1070040000000) connect rom[102], UInt<64>(0h65746e6901000000) connect rom[103], UInt<64>(0h6f632d7470757272) connect rom[104], UInt<64>(0h72656c6c6f72746e) connect rom[105], UInt<64>(0h300000000000000) connect rom[106], UInt<64>(0h201000004000000) connect rom[107], UInt<64>(0h300000001000000) connect rom[108], UInt<64>(0h1b0000000f000000) connect rom[109], UInt<64>(0h70632c7663736972) connect rom[110], UInt<64>(0h63746e692d75) connect rom[111], UInt<64>(0h3000000) connect rom[112], UInt<64>(0h300000013010000) connect rom[113], UInt<64>(0h2801000004000000) connect rom[114], UInt<64>(0h200000002000000) connect rom[115], UInt<64>(0h200000002000000) connect rom[116], UInt<64>(0h6669746801000000) connect rom[117], UInt<64>(0h300000000000000) connect rom[118], UInt<64>(0h1b0000000a000000) connect rom[119], UInt<64>(0h666974682c626375) connect rom[120], UInt<64>(0h200000000000030) connect rom[121], UInt<64>(0h636f7301000000) connect rom[122], UInt<64>(0h400000003000000) connect rom[123], UInt<64>(0h100000000000000) connect rom[124], UInt<64>(0h400000003000000) connect rom[125], UInt<64>(0h10000000f000000) connect rom[126], UInt<64>(0h2000000003000000) connect rom[127], UInt<64>(0h2d6263751b000000) connect rom[128], UInt<64>(0h706968632c726162) connect rom[129], UInt<64>(0h636f732d64726179) connect rom[130], UInt<64>(0h2d656c706d697300) connect rom[131], UInt<64>(0h300000000737562) connect rom[132], UInt<64>(0h3001000000000000) connect rom[133], UInt<64>(0h746f6f6201000000) connect rom[134], UInt<64>(0h737365726464612d) connect rom[135], UInt<64>(0h303031406765722d) connect rom[136], UInt<64>(0h300000000000030) connect rom[137], UInt<64>(0hbb00000008000000) connect rom[138], UInt<64>(0h10000000100000) connect rom[139], UInt<64>(0h800000003000000) connect rom[140], UInt<64>(0h746e6f6337010000) connect rom[141], UInt<64>(0h2000000006c6f72) connect rom[142], UInt<64>(0h7375626301000000) connect rom[143], UInt<64>(0h6b636f6c635f) connect rom[144], UInt<64>(0h400000003000000) connect rom[145], UInt<64>(0h41010000) connect rom[146], UInt<64>(0h400000003000000) connect rom[147], UInt<64>(0h65cd1d53000000) connect rom[148], UInt<64>(0hb00000003000000) connect rom[149], UInt<64>(0h737562634e010000) connect rom[150], UInt<64>(0h6b636f6c635f) connect rom[151], UInt<64>(0hc00000003000000) connect rom[152], UInt<64>(0h657869661b000000) connect rom[153], UInt<64>(0h6b636f6c632d64) connect rom[154], UInt<64>(0h100000002000000) connect rom[155], UInt<64>(0h303240746e696c63) connect rom[156], UInt<64>(0h3030303030) connect rom[157], UInt<64>(0hd00000003000000) connect rom[158], UInt<64>(0h637369721b000000) connect rom[159], UInt<64>(0h30746e696c632c76) connect rom[160], UInt<64>(0h300000000000000) connect rom[161], UInt<64>(0h6101000010000000) connect rom[162], UInt<64>(0h300000002000000) connect rom[163], UInt<64>(0h700000002000000) connect rom[164], UInt<64>(0h800000003000000) connect rom[165], UInt<64>(0h2bb000000) connect rom[166], UInt<64>(0h300000000000100) connect rom[167], UInt<64>(0h3701000008000000) connect rom[168], UInt<64>(0h6c6f72746e6f63) connect rom[169], UInt<64>(0h100000002000000) connect rom[170], UInt<64>(0h61672d6b636f6c63) connect rom[171], UInt<64>(0h3030303140726574) connect rom[172], UInt<64>(0h300000000003030) connect rom[173], UInt<64>(0hbb00000008000000) connect rom[174], UInt<64>(0h10000000001000) connect rom[175], UInt<64>(0h800000003000000) connect rom[176], UInt<64>(0h746e6f6337010000) connect rom[177], UInt<64>(0h2000000006c6f72) connect rom[178], UInt<64>(0h7562656401000000) connect rom[179], UInt<64>(0h6f72746e6f632d67) connect rom[180], UInt<64>(0h304072656c6c) connect rom[181], UInt<64>(0h2100000003000000) connect rom[182], UInt<64>(0h696669731b000000) connect rom[183], UInt<64>(0h67756265642c6576) connect rom[184], UInt<64>(0h736972003331302d) connect rom[185], UInt<64>(0h67756265642c7663) connect rom[186], UInt<64>(0h3331302d) connect rom[187], UInt<64>(0h500000003000000) connect rom[188], UInt<64>(0h6761746a75010000) connect rom[189], UInt<64>(0h300000000000000) connect rom[190], UInt<64>(0h6101000008000000) connect rom[191], UInt<64>(0hffff000002000000) connect rom[192], UInt<64>(0h800000003000000) connect rom[193], UInt<64>(0hbb000000) connect rom[194], UInt<64>(0h300000000100000) connect rom[195], UInt<64>(0h3701000008000000) connect rom[196], UInt<64>(0h6c6f72746e6f63) connect rom[197], UInt<64>(0h100000002000000) connect rom[198], UInt<64>(0h303038406d697464) connect rom[199], UInt<64>(0h3030303030) connect rom[200], UInt<64>(0hd00000003000000) connect rom[201], UInt<64>(0h696669731b000000) connect rom[202], UInt<64>(0h306d6974642c6576) connect rom[203], UInt<64>(0h300000000000000) connect rom[204], UInt<64>(0hbb00000008000000) connect rom[205], UInt<64>(0h40000000000080) connect rom[206], UInt<64>(0h400000003000000) connect rom[207], UInt<64>(0h6d656d37010000) connect rom[208], UInt<64>(0h400000003000000) connect rom[209], UInt<64>(0h100000028010000) connect rom[210], UInt<64>(0h100000002000000) connect rom[211], UInt<64>(0h65642d726f727265) connect rom[212], UInt<64>(0h3030334065636976) connect rom[213], UInt<64>(0h300000000000030) connect rom[214], UInt<64>(0h1b0000000e000000) connect rom[215], UInt<64>(0h652c657669666973) connect rom[216], UInt<64>(0h30726f7272) connect rom[217], UInt<64>(0h800000003000000) connect rom[218], UInt<64>(0h300000bb000000) connect rom[219], UInt<64>(0h200000000100000) connect rom[220], UInt<64>(0h7375626601000000) connect rom[221], UInt<64>(0h6b636f6c635f) connect rom[222], UInt<64>(0h400000003000000) connect rom[223], UInt<64>(0h41010000) connect rom[224], UInt<64>(0h400000003000000) connect rom[225], UInt<64>(0h65cd1d53000000) connect rom[226], UInt<64>(0hb00000003000000) connect rom[227], UInt<64>(0h737562664e010000) connect rom[228], UInt<64>(0h6b636f6c635f) connect rom[229], UInt<64>(0hc00000003000000) connect rom[230], UInt<64>(0h657869661b000000) connect rom[231], UInt<64>(0h6b636f6c632d64) connect rom[232], UInt<64>(0h100000002000000) connect rom[233], UInt<64>(0h7075727265746e69) connect rom[234], UInt<64>(0h6f72746e6f632d74) connect rom[235], UInt<64>(0h3030634072656c6c) connect rom[236], UInt<64>(0h30303030) connect rom[237], UInt<64>(0h400000003000000) connect rom[238], UInt<64>(0h100000002010000) connect rom[239], UInt<64>(0hc00000003000000) connect rom[240], UInt<64>(0h637369721b000000) connect rom[241], UInt<64>(0h3063696c702c76) connect rom[242], UInt<64>(0h3000000) connect rom[243], UInt<64>(0h300000013010000) connect rom[244], UInt<64>(0h6101000008000000) connect rom[245], UInt<64>(0hb00000002000000) connect rom[246], UInt<64>(0h800000003000000) connect rom[247], UInt<64>(0hcbb000000) connect rom[248], UInt<64>(0h300000000000004) connect rom[249], UInt<64>(0h3701000008000000) connect rom[250], UInt<64>(0h6c6f72746e6f63) connect rom[251], UInt<64>(0h400000003000000) connect rom[252], UInt<64>(0h100000082010000) connect rom[253], UInt<64>(0h400000003000000) connect rom[254], UInt<64>(0h100000095010000) connect rom[255], UInt<64>(0h400000003000000) connect rom[256], UInt<64>(0h400000028010000) connect rom[257], UInt<64>(0h100000002000000) connect rom[258], UInt<64>(0h6f6c635f73756270) connect rom[259], UInt<64>(0h300000000006b63) connect rom[260], UInt<64>(0h4101000004000000) connect rom[261], UInt<64>(0h300000000000000) connect rom[262], UInt<64>(0h5300000004000000) connect rom[263], UInt<64>(0h30000000065cd1d) connect rom[264], UInt<64>(0h4e0100000b000000) connect rom[265], UInt<64>(0h6f6c635f73756270) connect rom[266], UInt<64>(0h300000000006b63) connect rom[267], UInt<64>(0h1b0000000c000000) connect rom[268], UInt<64>(0h6c632d6465786966) connect rom[269], UInt<64>(0h3000000006b636f) connect rom[270], UInt<64>(0h2801000004000000) connect rom[271], UInt<64>(0h200000003000000) connect rom[272], UInt<64>(0h406d6f7201000000) connect rom[273], UInt<64>(0h3030303031) connect rom[274], UInt<64>(0hc00000003000000) connect rom[275], UInt<64>(0h696669731b000000) connect rom[276], UInt<64>(0h306d6f722c6576) connect rom[277], UInt<64>(0h800000003000000) connect rom[278], UInt<64>(0h100bb000000) connect rom[279], UInt<64>(0h300000000000100) connect rom[280], UInt<64>(0h3701000004000000) connect rom[281], UInt<64>(0h2000000006d656d) connect rom[282], UInt<64>(0h7375627301000000) connect rom[283], UInt<64>(0h6b636f6c635f) connect rom[284], UInt<64>(0h400000003000000) connect rom[285], UInt<64>(0h41010000) connect rom[286], UInt<64>(0h400000003000000) connect rom[287], UInt<64>(0h65cd1d53000000) connect rom[288], UInt<64>(0hb00000003000000) connect rom[289], UInt<64>(0h737562734e010000) connect rom[290], UInt<64>(0h6b636f6c635f) connect rom[291], UInt<64>(0hc00000003000000) connect rom[292], UInt<64>(0h657869661b000000) connect rom[293], UInt<64>(0h6b636f6c632d64) connect rom[294], UInt<64>(0h100000002000000) connect rom[295], UInt<64>(0h31406c6169726573) connect rom[296], UInt<64>(0h30303030323030) connect rom[297], UInt<64>(0h400000003000000) connect rom[298], UInt<64>(0h3000000a0010000) connect rom[299], UInt<64>(0hd00000003000000) connect rom[300], UInt<64>(0h696669731b000000) connect rom[301], UInt<64>(0h30747261752c6576) connect rom[302], UInt<64>(0h300000000000000) connect rom[303], UInt<64>(0ha701000004000000) connect rom[304], UInt<64>(0h300000004000000) connect rom[305], UInt<64>(0hb801000004000000) connect rom[306], UInt<64>(0h300000001000000) connect rom[307], UInt<64>(0hbb00000008000000) connect rom[308], UInt<64>(0h10000000000210) connect rom[309], UInt<64>(0h800000003000000) connect rom[310], UInt<64>(0h746e6f6337010000) connect rom[311], UInt<64>(0h2000000006c6f72) connect rom[312], UInt<64>(0h656c697401000000) connect rom[313], UInt<64>(0h732d74657365722d) connect rom[314], UInt<64>(0h3131407265747465) connect rom[315], UInt<64>(0h30303030) connect rom[316], UInt<64>(0h800000003000000) connect rom[317], UInt<64>(0h1100bb000000) connect rom[318], UInt<64>(0h300000000100000) connect rom[319], UInt<64>(0h3701000008000000) connect rom[320], UInt<64>(0h6c6f72746e6f63) connect rom[321], UInt<64>(0h200000002000000) connect rom[322], UInt<64>(0h900000002000000) connect rom[323], UInt<64>(0h7373657264646123) connect rom[324], UInt<64>(0h2300736c6c65632d) connect rom[325], UInt<64>(0h6c65632d657a6973) connect rom[326], UInt<64>(0h61706d6f6300736c) connect rom[327], UInt<64>(0h6f6d00656c626974) connect rom[328], UInt<64>(0h69726573006c6564) connect rom[329], UInt<64>(0h6f64747300306c61) connect rom[330], UInt<64>(0h687461702d7475) connect rom[331], UInt<64>(0h65736162656d6974) connect rom[332], UInt<64>(0h6e6575716572662d) connect rom[333], UInt<64>(0h6b636f6c63007963) connect rom[334], UInt<64>(0h6e6575716572662d) connect rom[335], UInt<64>(0h6369766564007963) connect rom[336], UInt<64>(0h6800657079745f65) connect rom[337], UInt<64>(0h2d65726177647261) connect rom[338], UInt<64>(0h6572622d63657865) connect rom[339], UInt<64>(0h2d746e696f706b61) connect rom[340], UInt<64>(0h2d6900746e756f63) connect rom[341], UInt<64>(0h6c622d6568636163) connect rom[342], UInt<64>(0h657a69732d6b636f) connect rom[343], UInt<64>(0h65686361632d6900) connect rom[344], UInt<64>(0h2d6900737465732d) connect rom[345], UInt<64>(0h69732d6568636163) connect rom[346], UInt<64>(0h720067657200657a) connect rom[347], UInt<64>(0h6173692c76637369) connect rom[348], UInt<64>(0h702c766373697200) connect rom[349], UInt<64>(0h6c756e617267706d) connect rom[350], UInt<64>(0h6972007974697261) connect rom[351], UInt<64>(0h72706d702c766373) connect rom[352], UInt<64>(0h7300736e6f696765) connect rom[353], UInt<64>(0h74642c6576696669) connect rom[354], UInt<64>(0h7574617473006d69) connect rom[355], UInt<64>(0h7265746e69230073) connect rom[356], UInt<64>(0h6c65632d74707572) connect rom[357], UInt<64>(0h7265746e6900736c) connect rom[358], UInt<64>(0h6e6f632d74707572) connect rom[359], UInt<64>(0h72656c6c6f7274) connect rom[360], UInt<64>(0h656c646e616870) connect rom[361], UInt<64>(0h72007365676e6172) connect rom[362], UInt<64>(0h73656d616e2d6765) connect rom[363], UInt<64>(0h2d6b636f6c632300) connect rom[364], UInt<64>(0h6c6300736c6c6563) connect rom[365], UInt<64>(0h7074756f2d6b636f) connect rom[366], UInt<64>(0h73656d616e2d7475) connect rom[367], UInt<64>(0h75727265746e6900) connect rom[368], UInt<64>(0h657478652d737470) connect rom[369], UInt<64>(0h626564006465646e) connect rom[370], UInt<64>(0h63617474612d6775) connect rom[371], UInt<64>(0h2c76637369720068) connect rom[372], UInt<64>(0h6f6972702d78616d) connect rom[373], UInt<64>(0h7369720079746972) connect rom[374], UInt<64>(0h7665646e2c7663) connect rom[375], UInt<64>(0h6900736b636f6c63) connect rom[376], UInt<64>(0h747075727265746e) connect rom[377], UInt<64>(0h746e657261702d) connect rom[378], UInt<64>(0h7075727265746e69) connect rom[379], UInt<64>(0h7374) connect rom[380], UInt<64>(0h0) connect rom[381], UInt<64>(0h0) connect rom[382], UInt<64>(0h0) connect rom[383], UInt<64>(0h0) connect rom[384], UInt<64>(0h0) connect rom[385], UInt<64>(0h0) connect rom[386], UInt<64>(0h0) connect rom[387], UInt<64>(0h0) connect rom[388], UInt<64>(0h0) connect rom[389], UInt<64>(0h0) connect rom[390], UInt<64>(0h0) connect rom[391], UInt<64>(0h0) connect rom[392], UInt<64>(0h0) connect rom[393], UInt<64>(0h0) connect rom[394], UInt<64>(0h0) connect rom[395], UInt<64>(0h0) connect rom[396], UInt<64>(0h0) connect rom[397], UInt<64>(0h0) connect rom[398], UInt<64>(0h0) connect rom[399], UInt<64>(0h0) connect rom[400], UInt<64>(0h0) connect rom[401], UInt<64>(0h0) connect rom[402], UInt<64>(0h0) connect rom[403], UInt<64>(0h0) connect rom[404], UInt<64>(0h0) connect rom[405], UInt<64>(0h0) connect rom[406], UInt<64>(0h0) connect rom[407], UInt<64>(0h0) connect rom[408], UInt<64>(0h0) connect rom[409], UInt<64>(0h0) connect rom[410], UInt<64>(0h0) connect rom[411], UInt<64>(0h0) connect rom[412], UInt<64>(0h0) connect rom[413], UInt<64>(0h0) connect rom[414], UInt<64>(0h0) connect rom[415], UInt<64>(0h0) connect rom[416], UInt<64>(0h0) connect rom[417], UInt<64>(0h0) connect rom[418], UInt<64>(0h0) connect rom[419], UInt<64>(0h0) connect rom[420], UInt<64>(0h0) connect rom[421], UInt<64>(0h0) connect rom[422], UInt<64>(0h0) connect rom[423], UInt<64>(0h0) connect rom[424], UInt<64>(0h0) connect rom[425], UInt<64>(0h0) connect rom[426], UInt<64>(0h0) connect rom[427], UInt<64>(0h0) connect rom[428], UInt<64>(0h0) connect rom[429], UInt<64>(0h0) connect rom[430], UInt<64>(0h0) connect rom[431], UInt<64>(0h0) connect rom[432], UInt<64>(0h0) connect rom[433], UInt<64>(0h0) connect rom[434], UInt<64>(0h0) connect rom[435], UInt<64>(0h0) connect rom[436], UInt<64>(0h0) connect rom[437], UInt<64>(0h0) connect rom[438], UInt<64>(0h0) connect rom[439], UInt<64>(0h0) connect rom[440], UInt<64>(0h0) connect rom[441], UInt<64>(0h0) connect rom[442], UInt<64>(0h0) connect rom[443], UInt<64>(0h0) connect rom[444], UInt<64>(0h0) connect rom[445], UInt<64>(0h0) connect rom[446], UInt<64>(0h0) connect rom[447], UInt<64>(0h0) connect rom[448], UInt<64>(0h0) connect rom[449], UInt<64>(0h0) connect rom[450], UInt<64>(0h0) connect rom[451], UInt<64>(0h0) connect rom[452], UInt<64>(0h0) connect rom[453], UInt<64>(0h0) connect rom[454], UInt<64>(0h0) connect rom[455], UInt<64>(0h0) connect rom[456], UInt<64>(0h0) connect rom[457], UInt<64>(0h0) connect rom[458], UInt<64>(0h0) connect rom[459], UInt<64>(0h0) connect rom[460], UInt<64>(0h0) connect rom[461], UInt<64>(0h0) connect rom[462], UInt<64>(0h0) connect rom[463], UInt<64>(0h0) connect rom[464], UInt<64>(0h0) connect rom[465], UInt<64>(0h0) connect rom[466], UInt<64>(0h0) connect rom[467], UInt<64>(0h0) connect rom[468], UInt<64>(0h0) connect rom[469], UInt<64>(0h0) connect rom[470], UInt<64>(0h0) connect rom[471], UInt<64>(0h0) connect rom[472], UInt<64>(0h0) connect rom[473], UInt<64>(0h0) connect rom[474], UInt<64>(0h0) connect rom[475], UInt<64>(0h0) connect rom[476], UInt<64>(0h0) connect rom[477], UInt<64>(0h0) connect rom[478], UInt<64>(0h0) connect rom[479], UInt<64>(0h0) connect rom[480], UInt<64>(0h0) connect rom[481], UInt<64>(0h0) connect rom[482], UInt<64>(0h0) connect rom[483], UInt<64>(0h0) connect rom[484], UInt<64>(0h0) connect rom[485], UInt<64>(0h0) connect rom[486], UInt<64>(0h0) connect rom[487], UInt<64>(0h0) connect rom[488], UInt<64>(0h0) connect rom[489], UInt<64>(0h0) connect rom[490], UInt<64>(0h0) connect rom[491], UInt<64>(0h0) connect rom[492], UInt<64>(0h0) connect rom[493], UInt<64>(0h0) connect rom[494], UInt<64>(0h0) connect rom[495], UInt<64>(0h0) connect rom[496], UInt<64>(0h0) connect rom[497], UInt<64>(0h0) connect rom[498], UInt<64>(0h0) connect rom[499], UInt<64>(0h0) connect rom[500], UInt<64>(0h0) connect rom[501], UInt<64>(0h0) connect rom[502], UInt<64>(0h0) connect rom[503], UInt<64>(0h0) connect rom[504], UInt<64>(0h0) connect rom[505], UInt<64>(0h0) connect rom[506], UInt<64>(0h0) connect rom[507], UInt<64>(0h0) connect rom[508], UInt<64>(0h0) connect rom[509], UInt<64>(0h0) connect rom[510], UInt<64>(0h0) connect rom[511], UInt<64>(0h0) connect nodeIn.d.valid, nodeIn.a.valid connect nodeIn.a.ready, nodeIn.d.ready node index = bits(nodeIn.a.bits.address, 11, 3) node high = bits(nodeIn.a.bits.address, 15, 12) node _nodeIn_d_bits_T = orr(high) node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index]) wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h1) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, nodeIn.a.bits.size connect nodeIn_d_bits_d.source, nodeIn.a.bits.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1 connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)	module TLROM( // @[BootROM.scala:41:9] input clock, // @[BootROM.scala:41:9] input reset, // @[BootROM.scala:41:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9] wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9] wire [511:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h7374, 64'h7075727265746E69, 64'h746E657261702D, 64'h747075727265746E, 64'h6900736B636F6C63, 64'h7665646E2C7663, 64'h7369720079746972, 64'h6F6972702D78616D, 64'h2C76637369720068, 64'h63617474612D6775, 64'h626564006465646E, 64'h657478652D737470, 64'h75727265746E6900, 64'h73656D616E2D7475, 64'h7074756F2D6B636F, 64'h6C6300736C6C6563, 64'h2D6B636F6C632300, 64'h73656D616E2D6765, 64'h72007365676E6172, 64'h656C646E616870, 64'h72656C6C6F7274, 64'h6E6F632D74707572, 64'h7265746E6900736C, 64'h6C65632D74707572, 64'h7265746E69230073, 64'h7574617473006D69, 64'h74642C6576696669, 64'h7300736E6F696765, 64'h72706D702C766373, 64'h6972007974697261, 64'h6C756E617267706D, 64'h702C766373697200, 64'h6173692C76637369, 64'h720067657200657A, 64'h69732D6568636163, 64'h2D6900737465732D, 64'h65686361632D6900, 64'h657A69732D6B636F, 64'h6C622D6568636163, 64'h2D6900746E756F63, 64'h2D746E696F706B61, 64'h6572622D63657865, 64'h2D65726177647261, 64'h6800657079745F65, 64'h6369766564007963, 64'h6E6575716572662D, 64'h6B636F6C63007963, 64'h6E6575716572662D, 64'h65736162656D6974, 64'h687461702D7475, 64'h6F64747300306C61, 64'h69726573006C6564, 64'h6F6D00656C626974, 64'h61706D6F6300736C, 64'h6C65632D657A6973, 64'h2300736C6C65632D, 64'h7373657264646123, 64'h900000002000000, 64'h200000002000000, 64'h6C6F72746E6F63, 64'h3701000008000000, 64'h300000000100000, 64'h1100BB000000, 64'h800000003000000, 64'h30303030, 64'h3131407265747465, 64'h732D74657365722D, 64'h656C697401000000, 64'h2000000006C6F72, 64'h746E6F6337010000, 64'h800000003000000, 64'h10000000000210, 64'hBB00000008000000, 64'h300000001000000, 64'hB801000004000000, 64'h300000004000000, 64'hA701000004000000, 64'h300000000000000, 64'h30747261752C6576, 64'h696669731B000000, 64'hD00000003000000, 64'h3000000A0010000, 64'h400000003000000, 64'h30303030323030, 64'h31406C6169726573, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h737562734E010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'h41010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375627301000000, 64'h2000000006D656D, 64'h3701000004000000, 64'h300000000000100, 64'h100BB000000, 64'h800000003000000, 64'h306D6F722C6576, 64'h696669731B000000, 64'hC00000003000000, 64'h3030303031, 64'h406D6F7201000000, 64'h200000003000000, 64'h2801000004000000, 64'h3000000006B636F, 64'h6C632D6465786966, 64'h1B0000000C000000, 64'h300000000006B63, 64'h6F6C635F73756270, 64'h4E0100000B000000, 64'h30000000065CD1D, 64'h5300000004000000, 64'h300000000000000, 64'h4101000004000000, 64'h300000000006B63, 64'h6F6C635F73756270, 64'h100000002000000, 64'h400000028010000, 64'h400000003000000, 64'h100000095010000, 64'h400000003000000, 64'h100000082010000, 64'h400000003000000, 64'h6C6F72746E6F63, 64'h3701000008000000, 64'h300000000000004, 64'hCBB000000, 64'h800000003000000, 64'hB00000002000000, 64'h6101000008000000, 64'h300000013010000, 64'h3000000, 64'h3063696C702C76, 64'h637369721B000000, 64'hC00000003000000, 64'h100000002010000, 64'h400000003000000, 64'h30303030, 64'h3030634072656C6C, 64'h6F72746E6F632D74, 64'h7075727265746E69, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h737562664E010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'h41010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375626601000000, 64'h200000000100000, 64'h300000BB000000, 64'h800000003000000, 64'h30726F7272, 64'h652C657669666973, 64'h1B0000000E000000, 64'h300000000000030, 64'h3030334065636976, 64'h65642D726F727265, 64'h100000002000000, 64'h100000028010000, 64'h400000003000000, 64'h6D656D37010000, 64'h400000003000000, 64'h40000000000080, 64'hBB00000008000000, 64'h300000000000000, 64'h306D6974642C6576, 64'h696669731B000000, 64'hD00000003000000, 64'h3030303030, 64'h303038406D697464, 64'h100000002000000, 64'h6C6F72746E6F63, 64'h3701000008000000, 64'h300000000100000, 64'hBB000000, 64'h800000003000000, 64'hFFFF000002000000, 64'h6101000008000000, 64'h300000000000000, 64'h6761746A75010000, 64'h500000003000000, 64'h3331302D, 64'h67756265642C7663, 64'h736972003331302D, 64'h67756265642C6576, 64'h696669731B000000, 64'h2100000003000000, 64'h304072656C6C, 64'h6F72746E6F632D67, 64'h7562656401000000, 64'h2000000006C6F72, 64'h746E6F6337010000, 64'h800000003000000, 64'h10000000001000, 64'hBB00000008000000, 64'h300000000003030, 64'h3030303140726574, 64'h61672D6B636F6C63, 64'h100000002000000, 64'h6C6F72746E6F63, 64'h3701000008000000, 64'h300000000000100, 64'h2BB000000, 64'h800000003000000, 64'h700000002000000, 64'h300000002000000, 64'h6101000010000000, 64'h300000000000000, 64'h30746E696C632C76, 64'h637369721B000000, 64'hD00000003000000, 64'h3030303030, 64'h303240746E696C63, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h737562634E010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'h41010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375626301000000, 64'h2000000006C6F72, 64'h746E6F6337010000, 64'h800000003000000, 64'h10000000100000, 64'hBB00000008000000, 64'h300000000000030, 64'h303031406765722D, 64'h737365726464612D, 64'h746F6F6201000000, 64'h3001000000000000, 64'h300000000737562, 64'h2D656C706D697300, 64'h636F732D64726179, 64'h706968632C726162, 64'h2D6263751B000000, 64'h2000000003000000, 64'h10000000F000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h636F7301000000, 64'h200000000000030, 64'h666974682C626375, 64'h1B0000000A000000, 64'h300000000000000, 64'h6669746801000000, 64'h200000002000000, 64'h200000002000000, 64'h2801000004000000, 64'h300000013010000, 64'h3000000, 64'h63746E692D75, 64'h70632C7663736972, 64'h1B0000000F000000, 64'h300000001000000, 64'h201000004000000, 64'h300000000000000, 64'h72656C6C6F72746E, 64'h6F632D7470757272, 64'h65746E6901000000, 64'h20A1070040000000, 64'h400000003000000, 64'h79616B6F, 64'hFB00000005000000, 64'h300000001000000, 64'hEF00000004000000, 64'h300000008000000, 64'hDE00000004000000, 64'h300000004000000, 64'hC900000004000000, 64'h300000000000000, 64'h74656B636F72785F, 64'h6D7068697A5F6965, 64'h636E6566697A5F72, 64'h7363697A63616D69, 64'h32337672BF000000, 64'h2500000003000000, 64'hBB000000, 64'h400000003000000, 64'h100000AE000000, 64'h400000003000000, 64'h40000000A1000000, 64'h400000003000000, 64'h400000008E000000, 64'h400000003000000, 64'h10000006F000000, 64'h400000003000000, 64'h75706363000000, 64'h400000003000000, 64'h76637369, 64'h72003074656B636F, 64'h722C657669666973, 64'h1B00000015000000, 64'h300000000000000, 64'h5300000004000000, 64'h300000000000030, 64'h4075706301000000, 64'h20A1070040000000, 64'h400000003000000, 64'hF000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h73757063, 64'h100000002000000, 64'h30303030, 64'h32303031406C6169, 64'h7265732F636F732F, 64'h3400000015000000, 64'h300000000006E65, 64'h736F686301000000, 64'h200000000000000, 64'h3030303032303031, 64'h406C61697265732F, 64'h636F732F2C000000, 64'h1500000003000000, 64'h73657361696C61, 64'h100000000000000, 64'h6472617970696863, 64'h2C7261622D626375, 64'h2600000011000000, 64'h300000000000000, 64'h7665642D64726179, 64'h706968632C726162, 64'h2D6263751B000000, 64'h1500000003000000, 64'h10000000F000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h1000000, 64'h0, 64'h0, 64'h20090000C3010000, 64'h10000000, 64'h1100000028000000, 64'h5809000038000000, 64'h1B0B0000EDFE0DD0, 64'h1330200073, 64'h3006307308000613, 64'h185859300000597, 64'hF140257334151073, 64'h5250300001537, 64'h5A02300B505B3, 64'h251513FE029EE3, 64'h5A283F81FF06F, 64'h0, 64'h0, 64'h2C0006F, 64'hFE069AE3FFC62683, 64'h46061300D62023, 64'h10069300458613, 64'h380006F00050463, 64'hF1402573020005B7, 64'hFFDFF06F, 64'h1050007330052073, 64'h3045107300800513, 64'h3445307322200513, 64'h3030107300028863, 64'h12F2934122D293, 64'h301022F330551073, 64'h405051300000517}; wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22] wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22] wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22] wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22] wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22] wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22] wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22] wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22] wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22] wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22] wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22] wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22] wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22] wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22] wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22] wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22] wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22] wire [63:0] rom_19 = 64'h5250300001537; // @[BootROM.scala:50:22] wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22] wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22] wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22] wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22] wire [63:0] rom_24 = 64'h1B0B0000EDFE0DD0; // @[BootROM.scala:50:22] wire [63:0] rom_25 = 64'h5809000038000000; // @[BootROM.scala:50:22] wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22] wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22] wire [63:0] rom_28 = 64'h20090000C3010000; // @[BootROM.scala:50:22] wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22] wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22] wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22] wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22] wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22] wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22] wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22] wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22] wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22] wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22] wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22] wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22] wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22] wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22] wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22] wire [63:0] rom_69 = 64'h1B00000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_70 = 64'h722C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_71 = 64'h72003074656B636F; // @[BootROM.scala:50:22] wire [63:0] rom_72 = 64'h76637369; // @[BootROM.scala:50:22] wire [63:0] rom_74 = 64'h75706363000000; // @[BootROM.scala:50:22] wire [63:0] rom_76 = 64'h10000006F000000; // @[BootROM.scala:50:22] wire [63:0] rom_78 = 64'h400000008E000000; // @[BootROM.scala:50:22] wire [63:0] rom_80 = 64'h40000000A1000000; // @[BootROM.scala:50:22] wire [63:0] rom_82 = 64'h100000AE000000; // @[BootROM.scala:50:22] wire [63:0] rom_85 = 64'h2500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_86 = 64'h32337672BF000000; // @[BootROM.scala:50:22] wire [63:0] rom_87 = 64'h7363697A63616D69; // @[BootROM.scala:50:22] wire [63:0] rom_88 = 64'h636E6566697A5F72; // @[BootROM.scala:50:22] wire [63:0] rom_89 = 64'h6D7068697A5F6965; // @[BootROM.scala:50:22] wire [63:0] rom_90 = 64'h74656B636F72785F; // @[BootROM.scala:50:22] wire [63:0] rom_92 = 64'hC900000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_94 = 64'hDE00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_95 = 64'h300000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_96 = 64'hEF00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_98 = 64'hFB00000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_99 = 64'h79616B6F; // @[BootROM.scala:50:22] wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_101 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_102 = 64'h65746E6901000000; // @[BootROM.scala:50:22] wire [63:0] rom_103 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_104 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_106 = 64'h201000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_108 = 64'h1B0000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_109 = 64'h70632C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_110 = 64'h63746E692D75; // @[BootROM.scala:50:22] wire [63:0] rom_116 = 64'h6669746801000000; // @[BootROM.scala:50:22] wire [63:0] rom_118 = 64'h1B0000000A000000; // @[BootROM.scala:50:22] wire [63:0] rom_119 = 64'h666974682C626375; // @[BootROM.scala:50:22] wire [63:0] rom_120 = 64'h200000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_121 = 64'h636F7301000000; // @[BootROM.scala:50:22] wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_123 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_125 = 64'h10000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_126 = 64'h2000000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_127 = 64'h2D6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22] wire [63:0] rom_128 = 64'h706968632C726162; // @[BootROM.scala:50:22] wire [63:0] rom_129 = 64'h636F732D64726179; // @[BootROM.scala:50:22] wire [63:0] rom_130 = 64'h2D656C706D697300; // @[BootROM.scala:50:22] wire [63:0] rom_131 = 64'h300000000737562; // @[BootROM.scala:50:22] wire [63:0] rom_132 = 64'h3001000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_133 = 64'h746F6F6201000000; // @[BootROM.scala:50:22] wire [63:0] rom_134 = 64'h737365726464612D; // @[BootROM.scala:50:22] wire [63:0] rom_135 = 64'h303031406765722D; // @[BootROM.scala:50:22] wire [63:0] rom_138 = 64'h10000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_142 = 64'h7375626301000000; // @[BootROM.scala:50:22] wire [63:0] rom_149 = 64'h737562634E010000; // @[BootROM.scala:50:22] wire [63:0] rom_155 = 64'h303240746E696C63; // @[BootROM.scala:50:22] wire [63:0] rom_159 = 64'h30746E696C632C76; // @[BootROM.scala:50:22] wire [63:0] rom_161 = 64'h6101000010000000; // @[BootROM.scala:50:22] wire [63:0] rom_162 = 64'h300000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_163 = 64'h700000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_165 = 64'h2BB000000; // @[BootROM.scala:50:22] wire [63:0] rom_170 = 64'h61672D6B636F6C63; // @[BootROM.scala:50:22] wire [63:0] rom_171 = 64'h3030303140726574; // @[BootROM.scala:50:22] wire [63:0] rom_172 = 64'h300000000003030; // @[BootROM.scala:50:22] wire [63:0] rom_174 = 64'h10000000001000; // @[BootROM.scala:50:22] wire [63:0] rom_178 = 64'h7562656401000000; // @[BootROM.scala:50:22] wire [63:0] rom_179 = 64'h6F72746E6F632D67; // @[BootROM.scala:50:22] wire [63:0] rom_180 = 64'h304072656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_181 = 64'h2100000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_183 = 64'h67756265642C6576; // @[BootROM.scala:50:22] wire [63:0] rom_184 = 64'h736972003331302D; // @[BootROM.scala:50:22] wire [63:0] rom_185 = 64'h67756265642C7663; // @[BootROM.scala:50:22] wire [63:0] rom_186 = 64'h3331302D; // @[BootROM.scala:50:22] wire [63:0] rom_187 = 64'h500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_188 = 64'h6761746A75010000; // @[BootROM.scala:50:22] wire [63:0] rom_191 = 64'hFFFF000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_84 = 64'hBB000000; // @[BootROM.scala:50:22] wire [63:0] rom_193 = 64'hBB000000; // @[BootROM.scala:50:22] wire [63:0] rom_198 = 64'h303038406D697464; // @[BootROM.scala:50:22] wire [63:0] rom_156 = 64'h3030303030; // @[BootROM.scala:50:22] wire [63:0] rom_199 = 64'h3030303030; // @[BootROM.scala:50:22] wire [63:0] rom_202 = 64'h306D6974642C6576; // @[BootROM.scala:50:22] wire [63:0] rom_205 = 64'h40000000000080; // @[BootROM.scala:50:22] wire [63:0] rom_207 = 64'h6D656D37010000; // @[BootROM.scala:50:22] wire [63:0] rom_209 = 64'h100000028010000; // @[BootROM.scala:50:22] wire [63:0] rom_211 = 64'h65642D726F727265; // @[BootROM.scala:50:22] wire [63:0] rom_212 = 64'h3030334065636976; // @[BootROM.scala:50:22] wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_136 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_213 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_214 = 64'h1B0000000E000000; // @[BootROM.scala:50:22] wire [63:0] rom_215 = 64'h652C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_216 = 64'h30726F7272; // @[BootROM.scala:50:22] wire [63:0] rom_218 = 64'h300000BB000000; // @[BootROM.scala:50:22] wire [63:0] rom_219 = 64'h200000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_220 = 64'h7375626601000000; // @[BootROM.scala:50:22] wire [63:0] rom_227 = 64'h737562664E010000; // @[BootROM.scala:50:22] wire [63:0] rom_234 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22] wire [63:0] rom_235 = 64'h3030634072656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_238 = 64'h100000002010000; // @[BootROM.scala:50:22] wire [63:0] rom_158 = 64'h637369721B000000; // @[BootROM.scala:50:22] wire [63:0] rom_240 = 64'h637369721B000000; // @[BootROM.scala:50:22] wire [63:0] rom_241 = 64'h3063696C702C76; // @[BootROM.scala:50:22] wire [63:0] rom_111 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_242 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_112 = 64'h300000013010000; // @[BootROM.scala:50:22] wire [63:0] rom_243 = 64'h300000013010000; // @[BootROM.scala:50:22] wire [63:0] rom_190 = 64'h6101000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_244 = 64'h6101000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_245 = 64'hB00000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_247 = 64'hCBB000000; // @[BootROM.scala:50:22] wire [63:0] rom_248 = 64'h300000000000004; // @[BootROM.scala:50:22] wire [63:0] rom_252 = 64'h100000082010000; // @[BootROM.scala:50:22] wire [63:0] rom_254 = 64'h100000095010000; // @[BootROM.scala:50:22] wire [63:0] rom_256 = 64'h400000028010000; // @[BootROM.scala:50:22] wire [63:0] rom_260 = 64'h4101000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_262 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_263 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_264 = 64'h4E0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_258 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_265 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_259 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_266 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_267 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_268 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_269 = 64'h3000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_113 = 64'h2801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_270 = 64'h2801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_271 = 64'h200000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_272 = 64'h406D6F7201000000; // @[BootROM.scala:50:22] wire [63:0] rom_273 = 64'h3030303031; // @[BootROM.scala:50:22] wire [63:0] rom_276 = 64'h306D6F722C6576; // @[BootROM.scala:50:22] wire [63:0] rom_278 = 64'h100BB000000; // @[BootROM.scala:50:22] wire [63:0] rom_166 = 64'h300000000000100; // @[BootROM.scala:50:22] wire [63:0] rom_279 = 64'h300000000000100; // @[BootROM.scala:50:22] wire [63:0] rom_280 = 64'h3701000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_281 = 64'h2000000006D656D; // @[BootROM.scala:50:22] wire [63:0] rom_282 = 64'h7375627301000000; // @[BootROM.scala:50:22] wire [63:0] rom_145 = 64'h41010000; // @[BootROM.scala:50:22] wire [63:0] rom_223 = 64'h41010000; // @[BootROM.scala:50:22] wire [63:0] rom_285 = 64'h41010000; // @[BootROM.scala:50:22] wire [63:0] rom_147 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_225 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_287 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_148 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_226 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_288 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_289 = 64'h737562734E010000; // @[BootROM.scala:50:22] wire [63:0] rom_143 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_150 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_221 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_228 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_283 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_290 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_151 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_229 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_239 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_274 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_291 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_152 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_230 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_292 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_153 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_231 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_293 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_154 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_169 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_197 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_210 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_232 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_257 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_294 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_295 = 64'h31406C6169726573; // @[BootROM.scala:50:22] wire [63:0] rom_296 = 64'h30303030323030; // @[BootROM.scala:50:22] wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_73 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_75 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_77 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_79 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_81 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_83 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_100 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_122 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_124 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_144 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_146 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_206 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_208 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_222 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_224 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_237 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_251 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_253 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_255 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_284 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_286 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_297 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_298 = 64'h3000000A0010000; // @[BootROM.scala:50:22] wire [63:0] rom_157 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_200 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_299 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_182 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_201 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_275 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_300 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_301 = 64'h30747261752C6576; // @[BootROM.scala:50:22] wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_68 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_91 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_105 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_117 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_160 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_189 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_203 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_261 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_302 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_303 = 64'hA701000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_93 = 64'h300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_304 = 64'h300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_305 = 64'hB801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_97 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_107 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_306 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_137 = 64'hBB00000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_173 = 64'hBB00000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_204 = 64'hBB00000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_307 = 64'hBB00000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_308 = 64'h10000000000210; // @[BootROM.scala:50:22] wire [63:0] rom_140 = 64'h746E6F6337010000; // @[BootROM.scala:50:22] wire [63:0] rom_176 = 64'h746E6F6337010000; // @[BootROM.scala:50:22] wire [63:0] rom_310 = 64'h746E6F6337010000; // @[BootROM.scala:50:22] wire [63:0] rom_141 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_177 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_311 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_312 = 64'h656C697401000000; // @[BootROM.scala:50:22] wire [63:0] rom_313 = 64'h732D74657365722D; // @[BootROM.scala:50:22] wire [63:0] rom_314 = 64'h3131407265747465; // @[BootROM.scala:50:22] wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_236 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_315 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_139 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_164 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_175 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_192 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_217 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_246 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_277 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_309 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_316 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_317 = 64'h1100BB000000; // @[BootROM.scala:50:22] wire [63:0] rom_194 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_318 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_167 = 64'h3701000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_195 = 64'h3701000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_249 = 64'h3701000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_319 = 64'h3701000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_168 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_196 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_250 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_320 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_114 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_115 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_321 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_322 = 64'h900000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_323 = 64'h7373657264646123; // @[BootROM.scala:50:22] wire [63:0] rom_324 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22] wire [63:0] rom_325 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22] wire [63:0] rom_326 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22] wire [63:0] rom_327 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22] wire [63:0] rom_328 = 64'h69726573006C6564; // @[BootROM.scala:50:22] wire [63:0] rom_329 = 64'h6F64747300306C61; // @[BootROM.scala:50:22] wire [63:0] rom_330 = 64'h687461702D7475; // @[BootROM.scala:50:22] wire [63:0] rom_331 = 64'h65736162656D6974; // @[BootROM.scala:50:22] wire [63:0] rom_333 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22] wire [63:0] rom_332 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_334 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_335 = 64'h6369766564007963; // @[BootROM.scala:50:22] wire [63:0] rom_336 = 64'h6800657079745F65; // @[BootROM.scala:50:22] wire [63:0] rom_337 = 64'h2D65726177647261; // @[BootROM.scala:50:22] wire [63:0] rom_338 = 64'h6572622D63657865; // @[BootROM.scala:50:22] wire [63:0] rom_339 = 64'h2D746E696F706B61; // @[BootROM.scala:50:22] wire [63:0] rom_340 = 64'h2D6900746E756F63; // @[BootROM.scala:50:22] wire [63:0] rom_341 = 64'h6C622D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_342 = 64'h657A69732D6B636F; // @[BootROM.scala:50:22] wire [63:0] rom_343 = 64'h65686361632D6900; // @[BootROM.scala:50:22] wire [63:0] rom_344 = 64'h2D6900737465732D; // @[BootROM.scala:50:22] wire [63:0] rom_345 = 64'h69732D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_346 = 64'h720067657200657A; // @[BootROM.scala:50:22] wire [63:0] rom_347 = 64'h6173692C76637369; // @[BootROM.scala:50:22] wire [63:0] rom_348 = 64'h702C766373697200; // @[BootROM.scala:50:22] wire [63:0] rom_349 = 64'h6C756E617267706D; // @[BootROM.scala:50:22] wire [63:0] rom_350 = 64'h6972007974697261; // @[BootROM.scala:50:22] wire [63:0] rom_351 = 64'h72706D702C766373; // @[BootROM.scala:50:22] wire [63:0] rom_352 = 64'h7300736E6F696765; // @[BootROM.scala:50:22] wire [63:0] rom_353 = 64'h74642C6576696669; // @[BootROM.scala:50:22] wire [63:0] rom_354 = 64'h7574617473006D69; // @[BootROM.scala:50:22] wire [63:0] rom_355 = 64'h7265746E69230073; // @[BootROM.scala:50:22] wire [63:0] rom_356 = 64'h6C65632D74707572; // @[BootROM.scala:50:22] wire [63:0] rom_357 = 64'h7265746E6900736C; // @[BootROM.scala:50:22] wire [63:0] rom_358 = 64'h6E6F632D74707572; // @[BootROM.scala:50:22] wire [63:0] rom_359 = 64'h72656C6C6F7274; // @[BootROM.scala:50:22] wire [63:0] rom_360 = 64'h656C646E616870; // @[BootROM.scala:50:22] wire [63:0] rom_361 = 64'h72007365676E6172; // @[BootROM.scala:50:22] wire [63:0] rom_362 = 64'h73656D616E2D6765; // @[BootROM.scala:50:22] wire [63:0] rom_363 = 64'h2D6B636F6C632300; // @[BootROM.scala:50:22] wire [63:0] rom_364 = 64'h6C6300736C6C6563; // @[BootROM.scala:50:22] wire [63:0] rom_365 = 64'h7074756F2D6B636F; // @[BootROM.scala:50:22] wire [63:0] rom_366 = 64'h73656D616E2D7475; // @[BootROM.scala:50:22] wire [63:0] rom_367 = 64'h75727265746E6900; // @[BootROM.scala:50:22] wire [63:0] rom_368 = 64'h657478652D737470; // @[BootROM.scala:50:22] wire [63:0] rom_369 = 64'h626564006465646E; // @[BootROM.scala:50:22] wire [63:0] rom_370 = 64'h63617474612D6775; // @[BootROM.scala:50:22] wire [63:0] rom_371 = 64'h2C76637369720068; // @[BootROM.scala:50:22] wire [63:0] rom_372 = 64'h6F6972702D78616D; // @[BootROM.scala:50:22] wire [63:0] rom_373 = 64'h7369720079746972; // @[BootROM.scala:50:22] wire [63:0] rom_374 = 64'h7665646E2C7663; // @[BootROM.scala:50:22] wire [63:0] rom_375 = 64'h6900736B636F6C63; // @[BootROM.scala:50:22] wire [63:0] rom_376 = 64'h747075727265746E; // @[BootROM.scala:50:22] wire [63:0] rom_377 = 64'h746E657261702D; // @[BootROM.scala:50:22] wire [63:0] rom_233 = 64'h7075727265746E69; // @[BootROM.scala:50:22] wire [63:0] rom_378 = 64'h7075727265746E69; // @[BootROM.scala:50:22] wire [63:0] rom_379 = 64'h7374; // @[BootROM.scala:50:22] wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_380 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_381 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_382 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_383 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_384 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_385 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_386 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_387 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_388 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_389 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_390 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_391 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_392 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_393 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_394 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_395 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_396 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_397 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_398 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_399 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_400 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_401 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_402 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_403 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_404 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_405 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_406 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_407 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_408 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_409 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_410 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_411 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_412 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_413 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_414 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_415 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_416 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_417 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_418 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_419 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_420 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_421 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_422 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_423 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_424 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_425 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_426 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_427 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_428 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_429 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_430 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_431 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_432 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_433 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_434 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_435 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_436 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_437 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_438 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_439 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_440 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_441 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_442 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_443 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_444 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_445 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_446 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_447 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_448 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_449 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_450 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_451 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_452 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_453 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_454 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_455 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_456 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_457 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_458 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_459 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_460 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_461 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_462 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_463 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_464 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_465 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_466 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_467 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_468 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_469 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_470 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_471 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_472 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_473 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_474 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_475 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_476 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_477 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_478 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_479 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_480 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_481 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_482 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_483 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_484 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_485 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_486 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_487 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_488 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_489 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_490 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_491 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_492 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_493 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_494 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_495 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_496 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_497 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_498 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_499 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_500 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_501 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_502 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_503 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_504 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_505 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_506 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_507 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_508 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_509 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_510 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_511 = 64'h0; // @[BootROM.scala:50:22] wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17] wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9] wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[BootROM.scala:41:9] wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9] wire [10:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9] wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9] wire auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9] assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17] wire [10:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17] assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9] wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9] wire [8:0] index = nodeIn_a_bits_address[11:3]; // @[BootROM.scala:55:34] wire [3:0] high = nodeIn_a_bits_address[15:12]; // @[BootROM.scala:56:64] wire _nodeIn_d_bits_T = \|high; // @[BootROM.scala:56:64, :57:53] wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}] assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17] assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17] TLMonitor_38 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_8 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_12 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_8( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_12 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[7] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 node _source_ok_T_27 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_28 = or(_source_ok_T_27, _source_ok_WIRE[2]) node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[3]) node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[4]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[5]) node source_ok = or(_source_ok_T_31, _source_ok_WIRE[6]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = and(_T_11, _T_24) node _T_81 = and(_T_80, _T_37) node _T_82 = and(_T_81, _T_50) node _T_83 = and(_T_82, _T_63) node _T_84 = and(_T_83, _T_71) node _T_85 = and(_T_84, _T_79) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_85, UInt<1>(0h1), "") : assert_1 node _T_89 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_89 : node _T_90 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_91 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_92 = and(_T_90, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_94 = shr(io.in.a.bits.source, 2) node _T_95 = eq(_T_94, UInt<1>(0h0)) node _T_96 = leq(UInt<1>(0h0), uncommonBits_4) node _T_97 = and(_T_95, _T_96) node _T_98 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_99 = and(_T_97, _T_98) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_100 = shr(io.in.a.bits.source, 2) node _T_101 = eq(_T_100, UInt<1>(0h1)) node _T_102 = leq(UInt<1>(0h0), uncommonBits_5) node _T_103 = and(_T_101, _T_102) node _T_104 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_105 = and(_T_103, _T_104) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_106 = shr(io.in.a.bits.source, 2) node _T_107 = eq(_T_106, UInt<2>(0h2)) node _T_108 = leq(UInt<1>(0h0), uncommonBits_6) node _T_109 = and(_T_107, _T_108) node _T_110 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_111 = and(_T_109, _T_110) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_112 = shr(io.in.a.bits.source, 2) node _T_113 = eq(_T_112, UInt<2>(0h3)) node _T_114 = leq(UInt<1>(0h0), uncommonBits_7) node _T_115 = and(_T_113, _T_114) node _T_116 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_117 = and(_T_115, _T_116) node _T_118 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_119 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_120 = or(_T_93, _T_99) node _T_121 = or(_T_120, _T_105) node _T_122 = or(_T_121, _T_111) node _T_123 = or(_T_122, _T_117) node _T_124 = or(_T_123, _T_118) node _T_125 = or(_T_124, _T_119) node _T_126 = and(_T_92, _T_125) node _T_127 = or(UInt<1>(0h0), _T_126) node _T_128 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_129 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_130 = cvt(_T_129) node _T_131 = and(_T_130, asSInt(UInt<13>(0h1000))) node _T_132 = asSInt(_T_131) node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0))) node _T_134 = and(_T_128, _T_133) node _T_135 = or(UInt<1>(0h0), _T_134) node _T_136 = and(_T_127, _T_135) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_136, UInt<1>(0h1), "") : assert_2 node _T_140 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_141 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_142 = and(_T_140, _T_141) node _T_143 = or(UInt<1>(0h0), _T_142) node _T_144 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<13>(0h1000))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = and(_T_143, _T_148) node _T_150 = or(UInt<1>(0h0), _T_149) node _T_151 = and(UInt<1>(0h0), _T_150) node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(_T_151, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_151, UInt<1>(0h1), "") : assert_3 node _T_155 = asUInt(reset) node _T_156 = eq(_T_155, UInt<1>(0h0)) when _T_156 : node _T_157 = eq(source_ok, UInt<1>(0h0)) when _T_157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_158 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_159 = asUInt(reset) node _T_160 = eq(_T_159, UInt<1>(0h0)) when _T_160 : node _T_161 = eq(_T_158, UInt<1>(0h0)) when _T_161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_158, UInt<1>(0h1), "") : assert_5 node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : node _T_164 = eq(is_aligned, UInt<1>(0h0)) when _T_164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_165 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(_T_165, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_165, UInt<1>(0h1), "") : assert_7 node _T_169 = not(io.in.a.bits.mask) node _T_170 = eq(_T_169, UInt<1>(0h0)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_170, UInt<1>(0h1), "") : assert_8 node _T_174 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_175 = asUInt(reset) node _T_176 = eq(_T_175, UInt<1>(0h0)) when _T_176 : node _T_177 = eq(_T_174, UInt<1>(0h0)) when _T_177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_174, UInt<1>(0h1), "") : assert_9 node _T_178 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_178 : node _T_179 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_180 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_181 = and(_T_179, _T_180) node _T_182 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_183 = shr(io.in.a.bits.source, 2) node _T_184 = eq(_T_183, UInt<1>(0h0)) node _T_185 = leq(UInt<1>(0h0), uncommonBits_8) node _T_186 = and(_T_184, _T_185) node _T_187 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_188 = and(_T_186, _T_187) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_189 = shr(io.in.a.bits.source, 2) node _T_190 = eq(_T_189, UInt<1>(0h1)) node _T_191 = leq(UInt<1>(0h0), uncommonBits_9) node _T_192 = and(_T_190, _T_191) node _T_193 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_194 = and(_T_192, _T_193) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_195 = shr(io.in.a.bits.source, 2) node _T_196 = eq(_T_195, UInt<2>(0h2)) node _T_197 = leq(UInt<1>(0h0), uncommonBits_10) node _T_198 = and(_T_196, _T_197) node _T_199 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_200 = and(_T_198, _T_199) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_201 = shr(io.in.a.bits.source, 2) node _T_202 = eq(_T_201, UInt<2>(0h3)) node _T_203 = leq(UInt<1>(0h0), uncommonBits_11) node _T_204 = and(_T_202, _T_203) node _T_205 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_206 = and(_T_204, _T_205) node _T_207 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_208 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_209 = or(_T_182, _T_188) node _T_210 = or(_T_209, _T_194) node _T_211 = or(_T_210, _T_200) node _T_212 = or(_T_211, _T_206) node _T_213 = or(_T_212, _T_207) node _T_214 = or(_T_213, _T_208) node _T_215 = and(_T_181, _T_214) node _T_216 = or(UInt<1>(0h0), _T_215) node _T_217 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<13>(0h1000))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = and(_T_217, _T_222) node _T_224 = or(UInt<1>(0h0), _T_223) node _T_225 = and(_T_216, _T_224) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_225, UInt<1>(0h1), "") : assert_10 node _T_229 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_230 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_231 = and(_T_229, _T_230) node _T_232 = or(UInt<1>(0h0), _T_231) node _T_233 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_234 = cvt(_T_233) node _T_235 = and(_T_234, asSInt(UInt<13>(0h1000))) node _T_236 = asSInt(_T_235) node _T_237 = eq(_T_236, asSInt(UInt<1>(0h0))) node _T_238 = and(_T_232, _T_237) node _T_239 = or(UInt<1>(0h0), _T_238) node _T_240 = and(UInt<1>(0h0), _T_239) node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(_T_240, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_240, UInt<1>(0h1), "") : assert_11 node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(source_ok, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_247 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_247, UInt<1>(0h1), "") : assert_13 node _T_251 = asUInt(reset) node _T_252 = eq(_T_251, UInt<1>(0h0)) when _T_252 : node _T_253 = eq(is_aligned, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_254 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_254, UInt<1>(0h1), "") : assert_15 node _T_258 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_258, UInt<1>(0h1), "") : assert_16 node _T_262 = not(io.in.a.bits.mask) node _T_263 = eq(_T_262, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_263, UInt<1>(0h1), "") : assert_17 node _T_267 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_267, UInt<1>(0h1), "") : assert_18 node _T_271 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_271 : node _T_272 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_273 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_274 = and(_T_272, _T_273) node _T_275 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_276 = shr(io.in.a.bits.source, 2) node _T_277 = eq(_T_276, UInt<1>(0h0)) node _T_278 = leq(UInt<1>(0h0), uncommonBits_12) node _T_279 = and(_T_277, _T_278) node _T_280 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_281 = and(_T_279, _T_280) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_282 = shr(io.in.a.bits.source, 2) node _T_283 = eq(_T_282, UInt<1>(0h1)) node _T_284 = leq(UInt<1>(0h0), uncommonBits_13) node _T_285 = and(_T_283, _T_284) node _T_286 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_287 = and(_T_285, _T_286) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_288 = shr(io.in.a.bits.source, 2) node _T_289 = eq(_T_288, UInt<2>(0h2)) node _T_290 = leq(UInt<1>(0h0), uncommonBits_14) node _T_291 = and(_T_289, _T_290) node _T_292 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_293 = and(_T_291, _T_292) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_294 = shr(io.in.a.bits.source, 2) node _T_295 = eq(_T_294, UInt<2>(0h3)) node _T_296 = leq(UInt<1>(0h0), uncommonBits_15) node _T_297 = and(_T_295, _T_296) node _T_298 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_301 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_302 = or(_T_275, _T_281) node _T_303 = or(_T_302, _T_287) node _T_304 = or(_T_303, _T_293) node _T_305 = or(_T_304, _T_299) node _T_306 = or(_T_305, _T_300) node _T_307 = or(_T_306, _T_301) node _T_308 = and(_T_274, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_309, UInt<1>(0h1), "") : assert_19 node _T_313 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_314 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_315 = and(_T_313, _T_314) node _T_316 = or(UInt<1>(0h0), _T_315) node _T_317 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_318 = cvt(_T_317) node _T_319 = and(_T_318, asSInt(UInt<13>(0h1000))) node _T_320 = asSInt(_T_319) node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0))) node _T_322 = and(_T_316, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(_T_323, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_323, UInt<1>(0h1), "") : assert_20 node _T_327 = asUInt(reset) node _T_328 = eq(_T_327, UInt<1>(0h0)) when _T_328 : node _T_329 = eq(source_ok, UInt<1>(0h0)) when _T_329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_330 = asUInt(reset) node _T_331 = eq(_T_330, UInt<1>(0h0)) when _T_331 : node _T_332 = eq(is_aligned, UInt<1>(0h0)) when _T_332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_333 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_334 = asUInt(reset) node _T_335 = eq(_T_334, UInt<1>(0h0)) when _T_335 : node _T_336 = eq(_T_333, UInt<1>(0h0)) when _T_336 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_333, UInt<1>(0h1), "") : assert_23 node _T_337 = eq(io.in.a.bits.mask, mask) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_337, UInt<1>(0h1), "") : assert_24 node _T_341 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(_T_341, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_341, UInt<1>(0h1), "") : assert_25 node _T_345 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_345 : node _T_346 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_347 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_348 = and(_T_346, _T_347) node _T_349 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_350 = shr(io.in.a.bits.source, 2) node _T_351 = eq(_T_350, UInt<1>(0h0)) node _T_352 = leq(UInt<1>(0h0), uncommonBits_16) node _T_353 = and(_T_351, _T_352) node _T_354 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_355 = and(_T_353, _T_354) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_356 = shr(io.in.a.bits.source, 2) node _T_357 = eq(_T_356, UInt<1>(0h1)) node _T_358 = leq(UInt<1>(0h0), uncommonBits_17) node _T_359 = and(_T_357, _T_358) node _T_360 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_361 = and(_T_359, _T_360) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_362 = shr(io.in.a.bits.source, 2) node _T_363 = eq(_T_362, UInt<2>(0h2)) node _T_364 = leq(UInt<1>(0h0), uncommonBits_18) node _T_365 = and(_T_363, _T_364) node _T_366 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_367 = and(_T_365, _T_366) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_368 = shr(io.in.a.bits.source, 2) node _T_369 = eq(_T_368, UInt<2>(0h3)) node _T_370 = leq(UInt<1>(0h0), uncommonBits_19) node _T_371 = and(_T_369, _T_370) node _T_372 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_373 = and(_T_371, _T_372) node _T_374 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_375 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_376 = or(_T_349, _T_355) node _T_377 = or(_T_376, _T_361) node _T_378 = or(_T_377, _T_367) node _T_379 = or(_T_378, _T_373) node _T_380 = or(_T_379, _T_374) node _T_381 = or(_T_380, _T_375) node _T_382 = and(_T_348, _T_381) node _T_383 = or(UInt<1>(0h0), _T_382) node _T_384 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_385 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_386 = and(_T_384, _T_385) node _T_387 = or(UInt<1>(0h0), _T_386) node _T_388 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_389 = cvt(_T_388) node _T_390 = and(_T_389, asSInt(UInt<13>(0h1000))) node _T_391 = asSInt(_T_390) node _T_392 = eq(_T_391, asSInt(UInt<1>(0h0))) node _T_393 = and(_T_387, _T_392) node _T_394 = or(UInt<1>(0h0), _T_393) node _T_395 = and(_T_383, _T_394) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_395, UInt<1>(0h1), "") : assert_26 node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(source_ok, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(is_aligned, UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_405 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_405, UInt<1>(0h1), "") : assert_29 node _T_409 = eq(io.in.a.bits.mask, mask) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_409, UInt<1>(0h1), "") : assert_30 node _T_413 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_413 : node _T_414 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_415 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_416 = and(_T_414, _T_415) node _T_417 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_418 = shr(io.in.a.bits.source, 2) node _T_419 = eq(_T_418, UInt<1>(0h0)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_20) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_423 = and(_T_421, _T_422) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_424 = shr(io.in.a.bits.source, 2) node _T_425 = eq(_T_424, UInt<1>(0h1)) node _T_426 = leq(UInt<1>(0h0), uncommonBits_21) node _T_427 = and(_T_425, _T_426) node _T_428 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_429 = and(_T_427, _T_428) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_430 = shr(io.in.a.bits.source, 2) node _T_431 = eq(_T_430, UInt<2>(0h2)) node _T_432 = leq(UInt<1>(0h0), uncommonBits_22) node _T_433 = and(_T_431, _T_432) node _T_434 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_435 = and(_T_433, _T_434) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_436 = shr(io.in.a.bits.source, 2) node _T_437 = eq(_T_436, UInt<2>(0h3)) node _T_438 = leq(UInt<1>(0h0), uncommonBits_23) node _T_439 = and(_T_437, _T_438) node _T_440 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_444 = or(_T_417, _T_423) node _T_445 = or(_T_444, _T_429) node _T_446 = or(_T_445, _T_435) node _T_447 = or(_T_446, _T_441) node _T_448 = or(_T_447, _T_442) node _T_449 = or(_T_448, _T_443) node _T_450 = and(_T_416, _T_449) node _T_451 = or(UInt<1>(0h0), _T_450) node _T_452 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_453 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_454 = and(_T_452, _T_453) node _T_455 = or(UInt<1>(0h0), _T_454) node _T_456 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<13>(0h1000))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = and(_T_455, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = and(_T_451, _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_463, UInt<1>(0h1), "") : assert_31 node _T_467 = asUInt(reset) node _T_468 = eq(_T_467, UInt<1>(0h0)) when _T_468 : node _T_469 = eq(source_ok, UInt<1>(0h0)) when _T_469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(is_aligned, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_473 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_473, UInt<1>(0h1), "") : assert_34 node _T_477 = not(mask) node _T_478 = and(io.in.a.bits.mask, _T_477) node _T_479 = eq(_T_478, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_479, UInt<1>(0h1), "") : assert_35 node _T_483 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_483 : node _T_484 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_485 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_486 = and(_T_484, _T_485) node _T_487 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_488 = shr(io.in.a.bits.source, 2) node _T_489 = eq(_T_488, UInt<1>(0h0)) node _T_490 = leq(UInt<1>(0h0), uncommonBits_24) node _T_491 = and(_T_489, _T_490) node _T_492 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_493 = and(_T_491, _T_492) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_494 = shr(io.in.a.bits.source, 2) node _T_495 = eq(_T_494, UInt<1>(0h1)) node _T_496 = leq(UInt<1>(0h0), uncommonBits_25) node _T_497 = and(_T_495, _T_496) node _T_498 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_499 = and(_T_497, _T_498) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_500 = shr(io.in.a.bits.source, 2) node _T_501 = eq(_T_500, UInt<2>(0h2)) node _T_502 = leq(UInt<1>(0h0), uncommonBits_26) node _T_503 = and(_T_501, _T_502) node _T_504 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_505 = and(_T_503, _T_504) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_506 = shr(io.in.a.bits.source, 2) node _T_507 = eq(_T_506, UInt<2>(0h3)) node _T_508 = leq(UInt<1>(0h0), uncommonBits_27) node _T_509 = and(_T_507, _T_508) node _T_510 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_511 = and(_T_509, _T_510) node _T_512 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_513 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_514 = or(_T_487, _T_493) node _T_515 = or(_T_514, _T_499) node _T_516 = or(_T_515, _T_505) node _T_517 = or(_T_516, _T_511) node _T_518 = or(_T_517, _T_512) node _T_519 = or(_T_518, _T_513) node _T_520 = and(_T_486, _T_519) node _T_521 = or(UInt<1>(0h0), _T_520) node _T_522 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_523 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_524 = cvt(_T_523) node _T_525 = and(_T_524, asSInt(UInt<13>(0h1000))) node _T_526 = asSInt(_T_525) node _T_527 = eq(_T_526, asSInt(UInt<1>(0h0))) node _T_528 = and(_T_522, _T_527) node _T_529 = or(UInt<1>(0h0), _T_528) node _T_530 = and(_T_521, _T_529) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_530, UInt<1>(0h1), "") : assert_36 node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(source_ok, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(is_aligned, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_540 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_540, UInt<1>(0h1), "") : assert_39 node _T_544 = eq(io.in.a.bits.mask, mask) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_544, UInt<1>(0h1), "") : assert_40 node _T_548 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_548 : node _T_549 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_550 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_551 = and(_T_549, _T_550) node _T_552 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_553 = shr(io.in.a.bits.source, 2) node _T_554 = eq(_T_553, UInt<1>(0h0)) node _T_555 = leq(UInt<1>(0h0), uncommonBits_28) node _T_556 = and(_T_554, _T_555) node _T_557 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_558 = and(_T_556, _T_557) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_559 = shr(io.in.a.bits.source, 2) node _T_560 = eq(_T_559, UInt<1>(0h1)) node _T_561 = leq(UInt<1>(0h0), uncommonBits_29) node _T_562 = and(_T_560, _T_561) node _T_563 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_564 = and(_T_562, _T_563) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_565 = shr(io.in.a.bits.source, 2) node _T_566 = eq(_T_565, UInt<2>(0h2)) node _T_567 = leq(UInt<1>(0h0), uncommonBits_30) node _T_568 = and(_T_566, _T_567) node _T_569 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_570 = and(_T_568, _T_569) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_571 = shr(io.in.a.bits.source, 2) node _T_572 = eq(_T_571, UInt<2>(0h3)) node _T_573 = leq(UInt<1>(0h0), uncommonBits_31) node _T_574 = and(_T_572, _T_573) node _T_575 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_576 = and(_T_574, _T_575) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_578 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_579 = or(_T_552, _T_558) node _T_580 = or(_T_579, _T_564) node _T_581 = or(_T_580, _T_570) node _T_582 = or(_T_581, _T_576) node _T_583 = or(_T_582, _T_577) node _T_584 = or(_T_583, _T_578) node _T_585 = and(_T_551, _T_584) node _T_586 = or(UInt<1>(0h0), _T_585) node _T_587 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_588 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<13>(0h1000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = and(_T_587, _T_592) node _T_594 = or(UInt<1>(0h0), _T_593) node _T_595 = and(_T_586, _T_594) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_595, UInt<1>(0h1), "") : assert_41 node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(source_ok, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(is_aligned, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_605 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(_T_605, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_605, UInt<1>(0h1), "") : assert_44 node _T_609 = eq(io.in.a.bits.mask, mask) node _T_610 = asUInt(reset) node _T_611 = eq(_T_610, UInt<1>(0h0)) when _T_611 : node _T_612 = eq(_T_609, UInt<1>(0h0)) when _T_612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_609, UInt<1>(0h1), "") : assert_45 node _T_613 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_613 : node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_615 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_616 = and(_T_614, _T_615) node _T_617 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_618 = shr(io.in.a.bits.source, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = leq(UInt<1>(0h0), uncommonBits_32) node _T_621 = and(_T_619, _T_620) node _T_622 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_623 = and(_T_621, _T_622) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_624 = shr(io.in.a.bits.source, 2) node _T_625 = eq(_T_624, UInt<1>(0h1)) node _T_626 = leq(UInt<1>(0h0), uncommonBits_33) node _T_627 = and(_T_625, _T_626) node _T_628 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_629 = and(_T_627, _T_628) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_630 = shr(io.in.a.bits.source, 2) node _T_631 = eq(_T_630, UInt<2>(0h2)) node _T_632 = leq(UInt<1>(0h0), uncommonBits_34) node _T_633 = and(_T_631, _T_632) node _T_634 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_635 = and(_T_633, _T_634) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_636 = shr(io.in.a.bits.source, 2) node _T_637 = eq(_T_636, UInt<2>(0h3)) node _T_638 = leq(UInt<1>(0h0), uncommonBits_35) node _T_639 = and(_T_637, _T_638) node _T_640 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_641 = and(_T_639, _T_640) node _T_642 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_643 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_644 = or(_T_617, _T_623) node _T_645 = or(_T_644, _T_629) node _T_646 = or(_T_645, _T_635) node _T_647 = or(_T_646, _T_641) node _T_648 = or(_T_647, _T_642) node _T_649 = or(_T_648, _T_643) node _T_650 = and(_T_616, _T_649) node _T_651 = or(UInt<1>(0h0), _T_650) node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_653 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<13>(0h1000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = and(_T_651, _T_659) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_660, UInt<1>(0h1), "") : assert_46 node _T_664 = asUInt(reset) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(source_ok, UInt<1>(0h0)) when _T_666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(is_aligned, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_670 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_670, UInt<1>(0h1), "") : assert_49 node _T_674 = eq(io.in.a.bits.mask, mask) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_674, UInt<1>(0h1), "") : assert_50 node _T_678 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_678, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_682 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_T_682, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_682, UInt<1>(0h1), "") : assert_52 node _source_ok_T_32 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_33 = shr(io.in.d.bits.source, 2) node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0)) node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_39 = shr(io.in.d.bits.source, 2) node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h1)) node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<2>(0h2)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h3)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_T_57 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[7] connect _source_ok_WIRE_1[0], _source_ok_T_32 connect _source_ok_WIRE_1[1], _source_ok_T_38 connect _source_ok_WIRE_1[2], _source_ok_T_44 connect _source_ok_WIRE_1[3], _source_ok_T_50 connect _source_ok_WIRE_1[4], _source_ok_T_56 connect _source_ok_WIRE_1[5], _source_ok_T_57 connect _source_ok_WIRE_1[6], _source_ok_T_58 node _source_ok_T_59 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE_1[2]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE_1[3]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE_1[4]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[5]) node source_ok_1 = or(_source_ok_T_63, _source_ok_WIRE_1[6]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_686 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_686 : node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(source_ok_1, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_690 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_690, UInt<1>(0h1), "") : assert_54 node _T_694 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(_T_694, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_694, UInt<1>(0h1), "") : assert_55 node _T_698 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_698, UInt<1>(0h1), "") : assert_56 node _T_702 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_702, UInt<1>(0h1), "") : assert_57 node _T_706 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_706 : node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(source_ok_1, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(sink_ok, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_713 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_713, UInt<1>(0h1), "") : assert_60 node _T_717 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(_T_717, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_717, UInt<1>(0h1), "") : assert_61 node _T_721 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_721, UInt<1>(0h1), "") : assert_62 node _T_725 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_725, UInt<1>(0h1), "") : assert_63 node _T_729 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_730 = or(UInt<1>(0h0), _T_729) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_730, UInt<1>(0h1), "") : assert_64 node _T_734 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_734 : node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(source_ok_1, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(sink_ok, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_741 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_741, UInt<1>(0h1), "") : assert_67 node _T_745 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_745, UInt<1>(0h1), "") : assert_68 node _T_749 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_750 = asUInt(reset) node _T_751 = eq(_T_750, UInt<1>(0h0)) when _T_751 : node _T_752 = eq(_T_749, UInt<1>(0h0)) when _T_752 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_749, UInt<1>(0h1), "") : assert_69 node _T_753 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_754 = or(_T_753, io.in.d.bits.corrupt) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_754, UInt<1>(0h1), "") : assert_70 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_759, UInt<1>(0h1), "") : assert_71 node _T_763 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_763 : node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(source_ok_1, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_767 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_767, UInt<1>(0h1), "") : assert_73 node _T_771 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_771, UInt<1>(0h1), "") : assert_74 node _T_775 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_776 = or(UInt<1>(0h0), _T_775) node _T_777 = asUInt(reset) node _T_778 = eq(_T_777, UInt<1>(0h0)) when _T_778 : node _T_779 = eq(_T_776, UInt<1>(0h0)) when _T_779 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_776, UInt<1>(0h1), "") : assert_75 node _T_780 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_780 : node _T_781 = asUInt(reset) node _T_782 = eq(_T_781, UInt<1>(0h0)) when _T_782 : node _T_783 = eq(source_ok_1, UInt<1>(0h0)) when _T_783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_784 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_784, UInt<1>(0h1), "") : assert_77 node _T_788 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_789 = or(_T_788, io.in.d.bits.corrupt) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_789, UInt<1>(0h1), "") : assert_78 node _T_793 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_794 = or(UInt<1>(0h0), _T_793) node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(_T_794, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_794, UInt<1>(0h1), "") : assert_79 node _T_798 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_798 : node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(source_ok_1, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_802 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(_T_802, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_802, UInt<1>(0h1), "") : assert_81 node _T_806 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(_T_806, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_806, UInt<1>(0h1), "") : assert_82 node _T_810 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_811 = or(UInt<1>(0h0), _T_810) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_811, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_815 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_816 = asUInt(reset) node _T_817 = eq(_T_816, UInt<1>(0h0)) when _T_817 : node _T_818 = eq(_T_815, UInt<1>(0h0)) when _T_818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_815, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<7>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_819 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_820 = asUInt(reset) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(_T_819, UInt<1>(0h0)) when _T_822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_819, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_823 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_824 = asUInt(reset) node _T_825 = eq(_T_824, UInt<1>(0h0)) when _T_825 : node _T_826 = eq(_T_823, UInt<1>(0h0)) when _T_826 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_823, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_827 = eq(a_first, UInt<1>(0h0)) node _T_828 = and(io.in.a.valid, _T_827) when _T_828 : node _T_829 = eq(io.in.a.bits.opcode, opcode) node _T_830 = asUInt(reset) node _T_831 = eq(_T_830, UInt<1>(0h0)) when _T_831 : node _T_832 = eq(_T_829, UInt<1>(0h0)) when _T_832 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_829, UInt<1>(0h1), "") : assert_87 node _T_833 = eq(io.in.a.bits.param, param) node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(_T_833, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_833, UInt<1>(0h1), "") : assert_88 node _T_837 = eq(io.in.a.bits.size, size) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_837, UInt<1>(0h1), "") : assert_89 node _T_841 = eq(io.in.a.bits.source, source) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_841, UInt<1>(0h1), "") : assert_90 node _T_845 = eq(io.in.a.bits.address, address) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_845, UInt<1>(0h1), "") : assert_91 node _T_849 = and(io.in.a.ready, io.in.a.valid) node _T_850 = and(_T_849, a_first) when _T_850 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_851 = eq(d_first, UInt<1>(0h0)) node _T_852 = and(io.in.d.valid, _T_851) when _T_852 : node _T_853 = eq(io.in.d.bits.opcode, opcode_1) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_853, UInt<1>(0h1), "") : assert_92 node _T_857 = eq(io.in.d.bits.param, param_1) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_857, UInt<1>(0h1), "") : assert_93 node _T_861 = eq(io.in.d.bits.size, size_1) node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(_T_861, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_861, UInt<1>(0h1), "") : assert_94 node _T_865 = eq(io.in.d.bits.source, source_1) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_865, UInt<1>(0h1), "") : assert_95 node _T_869 = eq(io.in.d.bits.sink, sink) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_869, UInt<1>(0h1), "") : assert_96 node _T_873 = eq(io.in.d.bits.denied, denied) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_873, UInt<1>(0h1), "") : assert_97 node _T_877 = and(io.in.d.ready, io.in.d.valid) node _T_878 = and(_T_877, d_first) when _T_878 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_879 = and(io.in.a.valid, a_first_1) node _T_880 = and(_T_879, UInt<1>(0h1)) when _T_880 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_881 = and(io.in.a.ready, io.in.a.valid) node _T_882 = and(_T_881, a_first_1) node _T_883 = and(_T_882, UInt<1>(0h1)) when _T_883 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_884 = dshr(inflight, io.in.a.bits.source) node _T_885 = bits(_T_884, 0, 0) node _T_886 = eq(_T_885, UInt<1>(0h0)) node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(_T_886, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_886, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_890 = and(io.in.d.valid, d_first_1) node _T_891 = and(_T_890, UInt<1>(0h1)) node _T_892 = eq(d_release_ack, UInt<1>(0h0)) node _T_893 = and(_T_891, _T_892) when _T_893 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_894 = and(io.in.d.ready, io.in.d.valid) node _T_895 = and(_T_894, d_first_1) node _T_896 = and(_T_895, UInt<1>(0h1)) node _T_897 = eq(d_release_ack, UInt<1>(0h0)) node _T_898 = and(_T_896, _T_897) when _T_898 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_899 = and(io.in.d.valid, d_first_1) node _T_900 = and(_T_899, UInt<1>(0h1)) node _T_901 = eq(d_release_ack, UInt<1>(0h0)) node _T_902 = and(_T_900, _T_901) when _T_902 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_903 = dshr(inflight, io.in.d.bits.source) node _T_904 = bits(_T_903, 0, 0) node _T_905 = or(_T_904, same_cycle_resp) node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(_T_905, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_905, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_909 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_910 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_911 = or(_T_909, _T_910) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_911, UInt<1>(0h1), "") : assert_100 node _T_915 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_915, UInt<1>(0h1), "") : assert_101 else : node _T_919 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_920 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_921 = or(_T_919, _T_920) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_921, UInt<1>(0h1), "") : assert_102 node _T_925 = eq(io.in.d.bits.size, a_size_lookup) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_925, UInt<1>(0h1), "") : assert_103 node _T_929 = and(io.in.d.valid, d_first_1) node _T_930 = and(_T_929, a_first_1) node _T_931 = and(_T_930, io.in.a.valid) node _T_932 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_933 = and(_T_931, _T_932) node _T_934 = eq(d_release_ack, UInt<1>(0h0)) node _T_935 = and(_T_933, _T_934) when _T_935 : node _T_936 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_937 = or(_T_936, io.in.a.ready) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_937, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_92 node _T_941 = orr(inflight) node _T_942 = eq(_T_941, UInt<1>(0h0)) node _T_943 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_944 = or(_T_942, _T_943) node _T_945 = lt(watchdog, plusarg_reader.out) node _T_946 = or(_T_944, _T_945) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_946, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_950 = and(io.in.a.ready, io.in.a.valid) node _T_951 = and(io.in.d.ready, io.in.d.valid) node _T_952 = or(_T_950, _T_951) when _T_952 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_953 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<21>(0h0) connect _WIRE_8.bits.source, UInt<7>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_954 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_955 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_956 = and(_T_954, _T_955) node _T_957 = and(_T_953, _T_956) when _T_957 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_958 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_959 = and(_T_958, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_960 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_961 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_962 = and(_T_960, _T_961) node _T_963 = and(_T_959, _T_962) when _T_963 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_964 = dshr(inflight_1, _WIRE_15.bits.source) node _T_965 = bits(_T_964, 0, 0) node _T_966 = eq(_T_965, UInt<1>(0h0)) node _T_967 = asUInt(reset) node _T_968 = eq(_T_967, UInt<1>(0h0)) when _T_968 : node _T_969 = eq(_T_966, UInt<1>(0h0)) when _T_969 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_966, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_970 = and(io.in.d.valid, d_first_2) node _T_971 = and(_T_970, UInt<1>(0h1)) node _T_972 = and(_T_971, d_release_ack_1) when _T_972 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_973 = and(io.in.d.ready, io.in.d.valid) node _T_974 = and(_T_973, d_first_2) node _T_975 = and(_T_974, UInt<1>(0h1)) node _T_976 = and(_T_975, d_release_ack_1) when _T_976 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_977 = and(io.in.d.valid, d_first_2) node _T_978 = and(_T_977, UInt<1>(0h1)) node _T_979 = and(_T_978, d_release_ack_1) when _T_979 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_980 = dshr(inflight_1, io.in.d.bits.source) node _T_981 = bits(_T_980, 0, 0) node _T_982 = or(_T_981, same_cycle_resp_1) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_982, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_986 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_986, UInt<1>(0h1), "") : assert_108 else : node _T_990 = eq(io.in.d.bits.size, c_size_lookup) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_990, UInt<1>(0h1), "") : assert_109 node _T_994 = and(io.in.d.valid, d_first_2) node _T_995 = and(_T_994, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_996 = and(_T_995, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_997 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_998 = and(_T_996, _T_997) node _T_999 = and(_T_998, d_release_ack_1) node _T_1000 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1001 = and(_T_999, _T_1000) when _T_1001 : node _T_1002 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1003 = or(_T_1002, _WIRE_23.ready) node _T_1004 = asUInt(reset) node _T_1005 = eq(_T_1004, UInt<1>(0h0)) when _T_1005 : node _T_1006 = eq(_T_1003, UInt<1>(0h0)) when _T_1006 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1003, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_93 node _T_1007 = orr(inflight_1) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) node _T_1009 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1010 = or(_T_1008, _T_1009) node _T_1011 = lt(watchdog_1, plusarg_reader_1.out) node _T_1012 = or(_T_1010, _T_1011) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1016 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1017 = and(io.in.d.ready, io.in.d.valid) node _T_1018 = or(_T_1016, _T_1017) when _T_1018 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_28 = _source_ok_T_27 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_29 = _source_ok_T_28 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_31 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_33 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_39 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_45 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_51 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_34 = _source_ok_T_33 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_40 = _source_ok_T_39 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_46 = _source_ok_T_45 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_52 = _source_ok_T_51 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire _source_ok_T_57 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire _source_ok_T_58 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire _source_ok_T_59 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_63 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _T_950 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_950; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_950; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1018 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1018; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1018; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1018; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_883 = _T_950 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_883 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_883 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_883 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_883 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_883 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_929 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_929 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_898 = _T_1018 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_898 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_898 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_898 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_994 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_994 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_976 = _T_1018 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_976 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_976 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_976 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_311 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_311( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_30 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut	module MulFullRawFN_30( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T \| _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 \| io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 \| io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 \| _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 \| notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 \| io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_1 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_257 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a	module Tile_1( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_257 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BoomCore_1 : input clock : Clock input reset : Reset output io : { flip hartid : UInt<2>, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>, lip : UInt<1>[0]}, ifu : { flip fetchpacket : { flip ready : UInt<1>, valid : UInt<1>, bits : { uops : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}[3]}}, flip get_pc : { flip ftq_idx : UInt<5>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<3>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<8>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>, com_pc : UInt<40>, next_val : UInt<1>, next_pc : UInt<40>}[2], debug_ftq_idx : UInt<5>[3], flip debug_fetch_pc : UInt<40>[3], status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], mcontext : UInt<0>, scontext : UInt<0>, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, redirect_flush : UInt<1>, redirect_val : UInt<1>, redirect_pc : UInt, redirect_ftq_idx : UInt, redirect_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, commit : { valid : UInt<1>, bits : UInt<32>}, flush_icache : UInt<1>, flip perf : { acquire : UInt<1>, tlbMiss : UInt<1>}}, flip ptw : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[2]}, clock_enabled : UInt<1>}, flip rocc : { flip cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, flip exception : UInt<1>, flip csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}, flip lsu : { exe : { flip req : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, fresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}}[1], flip dis_uops : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}[3], dis_ldq_idx : UInt<5>[3], dis_stq_idx : UInt<5>[3], ldq_full : UInt<1>[3], stq_full : UInt<1>[3], flip fp_stdata : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, flip commit : { valids : UInt<1>[3], arch_valids : UInt<1>[3], uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3], fflags : { valid : UInt<1>, bits : UInt<5>}, debug_insts : UInt<32>[3], rbk_valids : UInt<1>[3], rollback : UInt<1>, debug_wdata : UInt<64>[3]}, flip commit_load_at_rob_head : UInt<1>, clr_bsy : { valid : UInt<1>, bits : UInt<7>}[2], clr_unsafe : { valid : UInt<1>, bits : UInt<7>}[1], flip fence_dmem : UInt<1>, spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], ld_miss : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip rob_pnr_idx : UInt<7>, flip rob_head_idx : UInt<7>, flip exception : UInt<1>, fencei_rdy : UInt<1>, lxcpt : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, cause : UInt<5>, badvaddr : UInt<40>}}, flip tsc_reg : UInt, perf : { acquire : UInt<1>, release : UInt<1>, tlbMiss : UInt<1>}}, ptw_tlb : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[2]}}, trace : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[3], time : UInt<64>, custom : { rob_empty : UInt<1>}}, fcsr_rm : UInt<3>} invalidate io.ptw_tlb.customCSRs.csrs[0].sdata invalidate io.ptw_tlb.customCSRs.csrs[0].set invalidate io.ptw_tlb.customCSRs.csrs[0].stall invalidate io.ptw_tlb.customCSRs.csrs[0].value invalidate io.ptw_tlb.customCSRs.csrs[0].wdata invalidate io.ptw_tlb.customCSRs.csrs[0].wen invalidate io.ptw_tlb.customCSRs.csrs[0].ren invalidate io.ptw_tlb.customCSRs.csrs[1].sdata invalidate io.ptw_tlb.customCSRs.csrs[1].set invalidate io.ptw_tlb.customCSRs.csrs[1].stall invalidate io.ptw_tlb.customCSRs.csrs[1].value invalidate io.ptw_tlb.customCSRs.csrs[1].wdata invalidate io.ptw_tlb.customCSRs.csrs[1].wen invalidate io.ptw_tlb.customCSRs.csrs[1].ren invalidate io.ptw_tlb.pmp[0].mask invalidate io.ptw_tlb.pmp[0].addr invalidate io.ptw_tlb.pmp[0].cfg.r invalidate io.ptw_tlb.pmp[0].cfg.w invalidate io.ptw_tlb.pmp[0].cfg.x invalidate io.ptw_tlb.pmp[0].cfg.a invalidate io.ptw_tlb.pmp[0].cfg.res invalidate io.ptw_tlb.pmp[0].cfg.l invalidate io.ptw_tlb.pmp[1].mask invalidate io.ptw_tlb.pmp[1].addr invalidate io.ptw_tlb.pmp[1].cfg.r invalidate io.ptw_tlb.pmp[1].cfg.w invalidate io.ptw_tlb.pmp[1].cfg.x invalidate io.ptw_tlb.pmp[1].cfg.a invalidate io.ptw_tlb.pmp[1].cfg.res invalidate io.ptw_tlb.pmp[1].cfg.l invalidate io.ptw_tlb.pmp[2].mask invalidate io.ptw_tlb.pmp[2].addr invalidate io.ptw_tlb.pmp[2].cfg.r invalidate io.ptw_tlb.pmp[2].cfg.w invalidate io.ptw_tlb.pmp[2].cfg.x invalidate io.ptw_tlb.pmp[2].cfg.a invalidate io.ptw_tlb.pmp[2].cfg.res invalidate io.ptw_tlb.pmp[2].cfg.l invalidate io.ptw_tlb.pmp[3].mask invalidate io.ptw_tlb.pmp[3].addr invalidate io.ptw_tlb.pmp[3].cfg.r invalidate io.ptw_tlb.pmp[3].cfg.w invalidate io.ptw_tlb.pmp[3].cfg.x invalidate io.ptw_tlb.pmp[3].cfg.a invalidate io.ptw_tlb.pmp[3].cfg.res invalidate io.ptw_tlb.pmp[3].cfg.l invalidate io.ptw_tlb.pmp[4].mask invalidate io.ptw_tlb.pmp[4].addr invalidate io.ptw_tlb.pmp[4].cfg.r invalidate io.ptw_tlb.pmp[4].cfg.w invalidate io.ptw_tlb.pmp[4].cfg.x invalidate io.ptw_tlb.pmp[4].cfg.a invalidate io.ptw_tlb.pmp[4].cfg.res invalidate io.ptw_tlb.pmp[4].cfg.l invalidate io.ptw_tlb.pmp[5].mask invalidate io.ptw_tlb.pmp[5].addr invalidate io.ptw_tlb.pmp[5].cfg.r invalidate io.ptw_tlb.pmp[5].cfg.w invalidate io.ptw_tlb.pmp[5].cfg.x invalidate io.ptw_tlb.pmp[5].cfg.a invalidate io.ptw_tlb.pmp[5].cfg.res invalidate io.ptw_tlb.pmp[5].cfg.l invalidate io.ptw_tlb.pmp[6].mask invalidate io.ptw_tlb.pmp[6].addr invalidate io.ptw_tlb.pmp[6].cfg.r invalidate io.ptw_tlb.pmp[6].cfg.w invalidate io.ptw_tlb.pmp[6].cfg.x invalidate io.ptw_tlb.pmp[6].cfg.a invalidate io.ptw_tlb.pmp[6].cfg.res invalidate io.ptw_tlb.pmp[6].cfg.l invalidate io.ptw_tlb.pmp[7].mask invalidate io.ptw_tlb.pmp[7].addr invalidate io.ptw_tlb.pmp[7].cfg.r invalidate io.ptw_tlb.pmp[7].cfg.w invalidate io.ptw_tlb.pmp[7].cfg.x invalidate io.ptw_tlb.pmp[7].cfg.a invalidate io.ptw_tlb.pmp[7].cfg.res invalidate io.ptw_tlb.pmp[7].cfg.l invalidate io.ptw_tlb.gstatus.uie invalidate io.ptw_tlb.gstatus.sie invalidate io.ptw_tlb.gstatus.hie invalidate io.ptw_tlb.gstatus.mie invalidate io.ptw_tlb.gstatus.upie invalidate io.ptw_tlb.gstatus.spie invalidate io.ptw_tlb.gstatus.ube invalidate io.ptw_tlb.gstatus.mpie invalidate io.ptw_tlb.gstatus.spp invalidate io.ptw_tlb.gstatus.vs invalidate io.ptw_tlb.gstatus.mpp invalidate io.ptw_tlb.gstatus.fs invalidate io.ptw_tlb.gstatus.xs invalidate io.ptw_tlb.gstatus.mprv invalidate io.ptw_tlb.gstatus.sum invalidate io.ptw_tlb.gstatus.mxr invalidate io.ptw_tlb.gstatus.tvm invalidate io.ptw_tlb.gstatus.tw invalidate io.ptw_tlb.gstatus.tsr invalidate io.ptw_tlb.gstatus.zero1 invalidate io.ptw_tlb.gstatus.sd_rv32 invalidate io.ptw_tlb.gstatus.uxl invalidate io.ptw_tlb.gstatus.sxl invalidate io.ptw_tlb.gstatus.sbe invalidate io.ptw_tlb.gstatus.mbe invalidate io.ptw_tlb.gstatus.gva invalidate io.ptw_tlb.gstatus.mpv invalidate io.ptw_tlb.gstatus.zero2 invalidate io.ptw_tlb.gstatus.sd invalidate io.ptw_tlb.gstatus.v invalidate io.ptw_tlb.gstatus.prv invalidate io.ptw_tlb.gstatus.dv invalidate io.ptw_tlb.gstatus.dprv invalidate io.ptw_tlb.gstatus.isa invalidate io.ptw_tlb.gstatus.wfi invalidate io.ptw_tlb.gstatus.cease invalidate io.ptw_tlb.gstatus.debug invalidate io.ptw_tlb.hstatus.zero1 invalidate io.ptw_tlb.hstatus.vsbe invalidate io.ptw_tlb.hstatus.gva invalidate io.ptw_tlb.hstatus.spv invalidate io.ptw_tlb.hstatus.spvp invalidate io.ptw_tlb.hstatus.hu invalidate io.ptw_tlb.hstatus.zero2 invalidate io.ptw_tlb.hstatus.vgein invalidate io.ptw_tlb.hstatus.zero3 invalidate io.ptw_tlb.hstatus.vtvm invalidate io.ptw_tlb.hstatus.vtw invalidate io.ptw_tlb.hstatus.vtsr invalidate io.ptw_tlb.hstatus.zero5 invalidate io.ptw_tlb.hstatus.vsxl invalidate io.ptw_tlb.hstatus.zero6 invalidate io.ptw_tlb.status.uie invalidate io.ptw_tlb.status.sie invalidate io.ptw_tlb.status.hie invalidate io.ptw_tlb.status.mie invalidate io.ptw_tlb.status.upie invalidate io.ptw_tlb.status.spie invalidate io.ptw_tlb.status.ube invalidate io.ptw_tlb.status.mpie invalidate io.ptw_tlb.status.spp invalidate io.ptw_tlb.status.vs invalidate io.ptw_tlb.status.mpp invalidate io.ptw_tlb.status.fs invalidate io.ptw_tlb.status.xs invalidate io.ptw_tlb.status.mprv invalidate io.ptw_tlb.status.sum invalidate io.ptw_tlb.status.mxr invalidate io.ptw_tlb.status.tvm invalidate io.ptw_tlb.status.tw invalidate io.ptw_tlb.status.tsr invalidate io.ptw_tlb.status.zero1 invalidate io.ptw_tlb.status.sd_rv32 invalidate io.ptw_tlb.status.uxl invalidate io.ptw_tlb.status.sxl invalidate io.ptw_tlb.status.sbe invalidate io.ptw_tlb.status.mbe invalidate io.ptw_tlb.status.gva invalidate io.ptw_tlb.status.mpv invalidate io.ptw_tlb.status.zero2 invalidate io.ptw_tlb.status.sd invalidate io.ptw_tlb.status.v invalidate io.ptw_tlb.status.prv invalidate io.ptw_tlb.status.dv invalidate io.ptw_tlb.status.dprv invalidate io.ptw_tlb.status.isa invalidate io.ptw_tlb.status.wfi invalidate io.ptw_tlb.status.cease invalidate io.ptw_tlb.status.debug invalidate io.ptw_tlb.vsatp.ppn invalidate io.ptw_tlb.vsatp.asid invalidate io.ptw_tlb.vsatp.mode invalidate io.ptw_tlb.hgatp.ppn invalidate io.ptw_tlb.hgatp.asid invalidate io.ptw_tlb.hgatp.mode invalidate io.ptw_tlb.ptbr.ppn invalidate io.ptw_tlb.ptbr.asid invalidate io.ptw_tlb.ptbr.mode invalidate io.ptw_tlb.resp.bits.gpa_is_pte invalidate io.ptw_tlb.resp.bits.gpa.bits invalidate io.ptw_tlb.resp.bits.gpa.valid invalidate io.ptw_tlb.resp.bits.homogeneous invalidate io.ptw_tlb.resp.bits.fragmented_superpage invalidate io.ptw_tlb.resp.bits.level invalidate io.ptw_tlb.resp.bits.pte.v invalidate io.ptw_tlb.resp.bits.pte.r invalidate io.ptw_tlb.resp.bits.pte.w invalidate io.ptw_tlb.resp.bits.pte.x invalidate io.ptw_tlb.resp.bits.pte.u invalidate io.ptw_tlb.resp.bits.pte.g invalidate io.ptw_tlb.resp.bits.pte.a invalidate io.ptw_tlb.resp.bits.pte.d invalidate io.ptw_tlb.resp.bits.pte.reserved_for_software invalidate io.ptw_tlb.resp.bits.pte.ppn invalidate io.ptw_tlb.resp.bits.pte.reserved_for_future invalidate io.ptw_tlb.resp.bits.hx invalidate io.ptw_tlb.resp.bits.hw invalidate io.ptw_tlb.resp.bits.hr invalidate io.ptw_tlb.resp.bits.gf invalidate io.ptw_tlb.resp.bits.pf invalidate io.ptw_tlb.resp.bits.ae_final invalidate io.ptw_tlb.resp.bits.ae_ptw invalidate io.ptw_tlb.resp.valid invalidate io.ptw_tlb.req.bits.bits.stage2 invalidate io.ptw_tlb.req.bits.bits.vstage1 invalidate io.ptw_tlb.req.bits.bits.need_gpa invalidate io.ptw_tlb.req.bits.bits.addr invalidate io.ptw_tlb.req.bits.valid invalidate io.ptw_tlb.req.valid invalidate io.ptw_tlb.req.ready invalidate io.ptw.clock_enabled invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.perf.pte_hit invalidate io.ptw.perf.pte_miss invalidate io.ptw.perf.l2hit invalidate io.ptw.perf.l2miss invalidate io.ptw.pmp[0].mask invalidate io.ptw.pmp[0].addr invalidate io.ptw.pmp[0].cfg.r invalidate io.ptw.pmp[0].cfg.w invalidate io.ptw.pmp[0].cfg.x invalidate io.ptw.pmp[0].cfg.a invalidate io.ptw.pmp[0].cfg.res invalidate io.ptw.pmp[0].cfg.l invalidate io.ptw.pmp[1].mask invalidate io.ptw.pmp[1].addr invalidate io.ptw.pmp[1].cfg.r invalidate io.ptw.pmp[1].cfg.w invalidate io.ptw.pmp[1].cfg.x invalidate io.ptw.pmp[1].cfg.a invalidate io.ptw.pmp[1].cfg.res invalidate io.ptw.pmp[1].cfg.l invalidate io.ptw.pmp[2].mask invalidate io.ptw.pmp[2].addr invalidate io.ptw.pmp[2].cfg.r invalidate io.ptw.pmp[2].cfg.w invalidate io.ptw.pmp[2].cfg.x invalidate io.ptw.pmp[2].cfg.a invalidate io.ptw.pmp[2].cfg.res invalidate io.ptw.pmp[2].cfg.l invalidate io.ptw.pmp[3].mask invalidate io.ptw.pmp[3].addr invalidate io.ptw.pmp[3].cfg.r invalidate io.ptw.pmp[3].cfg.w invalidate io.ptw.pmp[3].cfg.x invalidate io.ptw.pmp[3].cfg.a invalidate io.ptw.pmp[3].cfg.res invalidate io.ptw.pmp[3].cfg.l invalidate io.ptw.pmp[4].mask invalidate io.ptw.pmp[4].addr invalidate io.ptw.pmp[4].cfg.r invalidate io.ptw.pmp[4].cfg.w invalidate io.ptw.pmp[4].cfg.x invalidate io.ptw.pmp[4].cfg.a invalidate io.ptw.pmp[4].cfg.res invalidate io.ptw.pmp[4].cfg.l invalidate io.ptw.pmp[5].mask invalidate io.ptw.pmp[5].addr invalidate io.ptw.pmp[5].cfg.r invalidate io.ptw.pmp[5].cfg.w invalidate io.ptw.pmp[5].cfg.x invalidate io.ptw.pmp[5].cfg.a invalidate io.ptw.pmp[5].cfg.res invalidate io.ptw.pmp[5].cfg.l invalidate io.ptw.pmp[6].mask invalidate io.ptw.pmp[6].addr invalidate io.ptw.pmp[6].cfg.r invalidate io.ptw.pmp[6].cfg.w invalidate io.ptw.pmp[6].cfg.x invalidate io.ptw.pmp[6].cfg.a invalidate io.ptw.pmp[6].cfg.res invalidate io.ptw.pmp[6].cfg.l invalidate io.ptw.pmp[7].mask invalidate io.ptw.pmp[7].addr invalidate io.ptw.pmp[7].cfg.r invalidate io.ptw.pmp[7].cfg.w invalidate io.ptw.pmp[7].cfg.x invalidate io.ptw.pmp[7].cfg.a invalidate io.ptw.pmp[7].cfg.res invalidate io.ptw.pmp[7].cfg.l invalidate io.ptw.gstatus.uie invalidate io.ptw.gstatus.sie invalidate io.ptw.gstatus.hie invalidate io.ptw.gstatus.mie invalidate io.ptw.gstatus.upie invalidate io.ptw.gstatus.spie invalidate io.ptw.gstatus.ube invalidate io.ptw.gstatus.mpie invalidate io.ptw.gstatus.spp invalidate io.ptw.gstatus.vs invalidate io.ptw.gstatus.mpp invalidate io.ptw.gstatus.fs invalidate io.ptw.gstatus.xs invalidate io.ptw.gstatus.mprv invalidate io.ptw.gstatus.sum invalidate io.ptw.gstatus.mxr invalidate io.ptw.gstatus.tvm invalidate io.ptw.gstatus.tw invalidate io.ptw.gstatus.tsr invalidate io.ptw.gstatus.zero1 invalidate io.ptw.gstatus.sd_rv32 invalidate io.ptw.gstatus.uxl invalidate io.ptw.gstatus.sxl invalidate io.ptw.gstatus.sbe invalidate io.ptw.gstatus.mbe invalidate io.ptw.gstatus.gva invalidate io.ptw.gstatus.mpv invalidate io.ptw.gstatus.zero2 invalidate io.ptw.gstatus.sd invalidate io.ptw.gstatus.v invalidate io.ptw.gstatus.prv invalidate io.ptw.gstatus.dv invalidate io.ptw.gstatus.dprv invalidate io.ptw.gstatus.isa invalidate io.ptw.gstatus.wfi invalidate io.ptw.gstatus.cease invalidate io.ptw.gstatus.debug invalidate io.ptw.hstatus.zero1 invalidate io.ptw.hstatus.vsbe invalidate io.ptw.hstatus.gva invalidate io.ptw.hstatus.spv invalidate io.ptw.hstatus.spvp invalidate io.ptw.hstatus.hu invalidate io.ptw.hstatus.zero2 invalidate io.ptw.hstatus.vgein invalidate io.ptw.hstatus.zero3 invalidate io.ptw.hstatus.vtvm invalidate io.ptw.hstatus.vtw invalidate io.ptw.hstatus.vtsr invalidate io.ptw.hstatus.zero5 invalidate io.ptw.hstatus.vsxl invalidate io.ptw.hstatus.zero6 invalidate io.ptw.status.uie invalidate io.ptw.status.sie invalidate io.ptw.status.hie invalidate io.ptw.status.mie invalidate io.ptw.status.upie invalidate io.ptw.status.spie invalidate io.ptw.status.ube invalidate io.ptw.status.mpie invalidate io.ptw.status.spp invalidate io.ptw.status.vs invalidate io.ptw.status.mpp invalidate io.ptw.status.fs invalidate io.ptw.status.xs invalidate io.ptw.status.mprv invalidate io.ptw.status.sum invalidate io.ptw.status.mxr invalidate io.ptw.status.tvm invalidate io.ptw.status.tw invalidate io.ptw.status.tsr invalidate io.ptw.status.zero1 invalidate io.ptw.status.sd_rv32 invalidate io.ptw.status.uxl invalidate io.ptw.status.sxl invalidate io.ptw.status.sbe invalidate io.ptw.status.mbe invalidate io.ptw.status.gva invalidate io.ptw.status.mpv invalidate io.ptw.status.zero2 invalidate io.ptw.status.sd invalidate io.ptw.status.v invalidate io.ptw.status.prv invalidate io.ptw.status.dv invalidate io.ptw.status.dprv invalidate io.ptw.status.isa invalidate io.ptw.status.wfi invalidate io.ptw.status.cease invalidate io.ptw.status.debug invalidate io.ptw.sfence.bits.hg invalidate io.ptw.sfence.bits.hv invalidate io.ptw.sfence.bits.asid invalidate io.ptw.sfence.bits.addr invalidate io.ptw.sfence.bits.rs2 invalidate io.ptw.sfence.bits.rs1 invalidate io.ptw.sfence.valid invalidate io.ptw.vsatp.ppn invalidate io.ptw.vsatp.asid invalidate io.ptw.vsatp.mode invalidate io.ptw.hgatp.ppn invalidate io.ptw.hgatp.asid invalidate io.ptw.hgatp.mode invalidate io.ptw.ptbr.ppn invalidate io.ptw.ptbr.asid invalidate io.ptw.ptbr.mode invalidate io.ifu.perf.tlbMiss invalidate io.ifu.perf.acquire invalidate io.ifu.flush_icache invalidate io.ifu.commit.bits invalidate io.ifu.commit.valid invalidate io.ifu.redirect_ghist.ras_idx invalidate io.ifu.redirect_ghist.new_saw_branch_taken invalidate io.ifu.redirect_ghist.new_saw_branch_not_taken invalidate io.ifu.redirect_ghist.current_saw_branch_not_taken invalidate io.ifu.redirect_ghist.old_history invalidate io.ifu.redirect_ftq_idx invalidate io.ifu.redirect_pc invalidate io.ifu.redirect_val invalidate io.ifu.redirect_flush invalidate io.ifu.brupdate.b2.target_offset invalidate io.ifu.brupdate.b2.jalr_target invalidate io.ifu.brupdate.b2.pc_sel invalidate io.ifu.brupdate.b2.cfi_type invalidate io.ifu.brupdate.b2.taken invalidate io.ifu.brupdate.b2.mispredict invalidate io.ifu.brupdate.b2.valid invalidate io.ifu.brupdate.b2.uop.debug_tsrc invalidate io.ifu.brupdate.b2.uop.debug_fsrc invalidate io.ifu.brupdate.b2.uop.bp_xcpt_if invalidate io.ifu.brupdate.b2.uop.bp_debug_if invalidate io.ifu.brupdate.b2.uop.xcpt_ma_if invalidate io.ifu.brupdate.b2.uop.xcpt_ae_if invalidate io.ifu.brupdate.b2.uop.xcpt_pf_if invalidate io.ifu.brupdate.b2.uop.fp_single invalidate io.ifu.brupdate.b2.uop.fp_val invalidate io.ifu.brupdate.b2.uop.frs3_en invalidate io.ifu.brupdate.b2.uop.lrs2_rtype invalidate io.ifu.brupdate.b2.uop.lrs1_rtype invalidate io.ifu.brupdate.b2.uop.dst_rtype invalidate io.ifu.brupdate.b2.uop.ldst_val invalidate io.ifu.brupdate.b2.uop.lrs3 invalidate io.ifu.brupdate.b2.uop.lrs2 invalidate io.ifu.brupdate.b2.uop.lrs1 invalidate io.ifu.brupdate.b2.uop.ldst invalidate io.ifu.brupdate.b2.uop.ldst_is_rs1 invalidate io.ifu.brupdate.b2.uop.flush_on_commit invalidate io.ifu.brupdate.b2.uop.is_unique invalidate io.ifu.brupdate.b2.uop.is_sys_pc2epc invalidate io.ifu.brupdate.b2.uop.uses_stq invalidate io.ifu.brupdate.b2.uop.uses_ldq invalidate io.ifu.brupdate.b2.uop.is_amo invalidate io.ifu.brupdate.b2.uop.is_fencei invalidate io.ifu.brupdate.b2.uop.is_fence invalidate io.ifu.brupdate.b2.uop.mem_signed invalidate io.ifu.brupdate.b2.uop.mem_size invalidate io.ifu.brupdate.b2.uop.mem_cmd invalidate io.ifu.brupdate.b2.uop.bypassable invalidate io.ifu.brupdate.b2.uop.exc_cause invalidate io.ifu.brupdate.b2.uop.exception invalidate io.ifu.brupdate.b2.uop.stale_pdst invalidate io.ifu.brupdate.b2.uop.ppred_busy invalidate io.ifu.brupdate.b2.uop.prs3_busy invalidate io.ifu.brupdate.b2.uop.prs2_busy invalidate io.ifu.brupdate.b2.uop.prs1_busy invalidate io.ifu.brupdate.b2.uop.ppred invalidate io.ifu.brupdate.b2.uop.prs3 invalidate io.ifu.brupdate.b2.uop.prs2 invalidate io.ifu.brupdate.b2.uop.prs1 invalidate io.ifu.brupdate.b2.uop.pdst invalidate io.ifu.brupdate.b2.uop.rxq_idx invalidate io.ifu.brupdate.b2.uop.stq_idx invalidate io.ifu.brupdate.b2.uop.ldq_idx invalidate io.ifu.brupdate.b2.uop.rob_idx invalidate io.ifu.brupdate.b2.uop.csr_addr invalidate io.ifu.brupdate.b2.uop.imm_packed invalidate io.ifu.brupdate.b2.uop.taken invalidate io.ifu.brupdate.b2.uop.pc_lob invalidate io.ifu.brupdate.b2.uop.edge_inst invalidate io.ifu.brupdate.b2.uop.ftq_idx invalidate io.ifu.brupdate.b2.uop.br_tag invalidate io.ifu.brupdate.b2.uop.br_mask invalidate io.ifu.brupdate.b2.uop.is_sfb invalidate io.ifu.brupdate.b2.uop.is_jal invalidate io.ifu.brupdate.b2.uop.is_jalr invalidate io.ifu.brupdate.b2.uop.is_br invalidate io.ifu.brupdate.b2.uop.iw_p2_poisoned invalidate io.ifu.brupdate.b2.uop.iw_p1_poisoned invalidate io.ifu.brupdate.b2.uop.iw_state invalidate io.ifu.brupdate.b2.uop.ctrl.is_std invalidate io.ifu.brupdate.b2.uop.ctrl.is_sta invalidate io.ifu.brupdate.b2.uop.ctrl.is_load invalidate io.ifu.brupdate.b2.uop.ctrl.csr_cmd invalidate io.ifu.brupdate.b2.uop.ctrl.fcn_dw invalidate io.ifu.brupdate.b2.uop.ctrl.op_fcn invalidate io.ifu.brupdate.b2.uop.ctrl.imm_sel invalidate io.ifu.brupdate.b2.uop.ctrl.op2_sel invalidate io.ifu.brupdate.b2.uop.ctrl.op1_sel invalidate io.ifu.brupdate.b2.uop.ctrl.br_type invalidate io.ifu.brupdate.b2.uop.fu_code invalidate io.ifu.brupdate.b2.uop.iq_type invalidate io.ifu.brupdate.b2.uop.debug_pc invalidate io.ifu.brupdate.b2.uop.is_rvc invalidate io.ifu.brupdate.b2.uop.debug_inst invalidate io.ifu.brupdate.b2.uop.inst invalidate io.ifu.brupdate.b2.uop.uopc invalidate io.ifu.brupdate.b1.mispredict_mask invalidate io.ifu.brupdate.b1.resolve_mask invalidate io.ifu.sfence.bits.hg invalidate io.ifu.sfence.bits.hv invalidate io.ifu.sfence.bits.asid invalidate io.ifu.sfence.bits.addr invalidate io.ifu.sfence.bits.rs2 invalidate io.ifu.sfence.bits.rs1 invalidate io.ifu.sfence.valid invalidate io.ifu.scontext invalidate io.ifu.mcontext invalidate io.ifu.status.uie invalidate io.ifu.status.sie invalidate io.ifu.status.hie invalidate io.ifu.status.mie invalidate io.ifu.status.upie invalidate io.ifu.status.spie invalidate io.ifu.status.ube invalidate io.ifu.status.mpie invalidate io.ifu.status.spp invalidate io.ifu.status.vs invalidate io.ifu.status.mpp invalidate io.ifu.status.fs invalidate io.ifu.status.xs invalidate io.ifu.status.mprv invalidate io.ifu.status.sum invalidate io.ifu.status.mxr invalidate io.ifu.status.tvm invalidate io.ifu.status.tw invalidate io.ifu.status.tsr invalidate io.ifu.status.zero1 invalidate io.ifu.status.sd_rv32 invalidate io.ifu.status.uxl invalidate io.ifu.status.sxl invalidate io.ifu.status.sbe invalidate io.ifu.status.mbe invalidate io.ifu.status.gva invalidate io.ifu.status.mpv invalidate io.ifu.status.zero2 invalidate io.ifu.status.sd invalidate io.ifu.status.v invalidate io.ifu.status.prv invalidate io.ifu.status.dv invalidate io.ifu.status.dprv invalidate io.ifu.status.isa invalidate io.ifu.status.wfi invalidate io.ifu.status.cease invalidate io.ifu.status.debug invalidate io.ifu.debug_fetch_pc[0] invalidate io.ifu.debug_fetch_pc[1] invalidate io.ifu.debug_fetch_pc[2] invalidate io.ifu.debug_ftq_idx[0] invalidate io.ifu.debug_ftq_idx[1] invalidate io.ifu.debug_ftq_idx[2] invalidate io.ifu.get_pc[0].next_pc invalidate io.ifu.get_pc[0].next_val invalidate io.ifu.get_pc[0].com_pc invalidate io.ifu.get_pc[0].pc invalidate io.ifu.get_pc[0].ghist.ras_idx invalidate io.ifu.get_pc[0].ghist.new_saw_branch_taken invalidate io.ifu.get_pc[0].ghist.new_saw_branch_not_taken invalidate io.ifu.get_pc[0].ghist.current_saw_branch_not_taken invalidate io.ifu.get_pc[0].ghist.old_history invalidate io.ifu.get_pc[0].entry.start_bank invalidate io.ifu.get_pc[0].entry.ras_idx invalidate io.ifu.get_pc[0].entry.ras_top invalidate io.ifu.get_pc[0].entry.cfi_npc_plus4 invalidate io.ifu.get_pc[0].entry.cfi_is_ret invalidate io.ifu.get_pc[0].entry.cfi_is_call invalidate io.ifu.get_pc[0].entry.br_mask invalidate io.ifu.get_pc[0].entry.cfi_type invalidate io.ifu.get_pc[0].entry.cfi_mispredicted invalidate io.ifu.get_pc[0].entry.cfi_taken invalidate io.ifu.get_pc[0].entry.cfi_idx.bits invalidate io.ifu.get_pc[0].entry.cfi_idx.valid invalidate io.ifu.get_pc[0].ftq_idx invalidate io.ifu.get_pc[1].next_pc invalidate io.ifu.get_pc[1].next_val invalidate io.ifu.get_pc[1].com_pc invalidate io.ifu.get_pc[1].pc invalidate io.ifu.get_pc[1].ghist.ras_idx invalidate io.ifu.get_pc[1].ghist.new_saw_branch_taken invalidate io.ifu.get_pc[1].ghist.new_saw_branch_not_taken invalidate io.ifu.get_pc[1].ghist.current_saw_branch_not_taken invalidate io.ifu.get_pc[1].ghist.old_history invalidate io.ifu.get_pc[1].entry.start_bank invalidate io.ifu.get_pc[1].entry.ras_idx invalidate io.ifu.get_pc[1].entry.ras_top invalidate io.ifu.get_pc[1].entry.cfi_npc_plus4 invalidate io.ifu.get_pc[1].entry.cfi_is_ret invalidate io.ifu.get_pc[1].entry.cfi_is_call invalidate io.ifu.get_pc[1].entry.br_mask invalidate io.ifu.get_pc[1].entry.cfi_type invalidate io.ifu.get_pc[1].entry.cfi_mispredicted invalidate io.ifu.get_pc[1].entry.cfi_taken invalidate io.ifu.get_pc[1].entry.cfi_idx.bits invalidate io.ifu.get_pc[1].entry.cfi_idx.valid invalidate io.ifu.get_pc[1].ftq_idx invalidate io.ifu.fetchpacket.bits.uops[0].bits.debug_tsrc invalidate io.ifu.fetchpacket.bits.uops[0].bits.debug_fsrc invalidate io.ifu.fetchpacket.bits.uops[0].bits.bp_xcpt_if invalidate io.ifu.fetchpacket.bits.uops[0].bits.bp_debug_if invalidate io.ifu.fetchpacket.bits.uops[0].bits.xcpt_ma_if invalidate io.ifu.fetchpacket.bits.uops[0].bits.xcpt_ae_if invalidate io.ifu.fetchpacket.bits.uops[0].bits.xcpt_pf_if invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_single invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_val invalidate io.ifu.fetchpacket.bits.uops[0].bits.frs3_en invalidate io.ifu.fetchpacket.bits.uops[0].bits.lrs2_rtype invalidate io.ifu.fetchpacket.bits.uops[0].bits.lrs1_rtype invalidate io.ifu.fetchpacket.bits.uops[0].bits.dst_rtype invalidate io.ifu.fetchpacket.bits.uops[0].bits.ldst_val invalidate io.ifu.fetchpacket.bits.uops[0].bits.lrs3 invalidate io.ifu.fetchpacket.bits.uops[0].bits.lrs2 invalidate io.ifu.fetchpacket.bits.uops[0].bits.lrs1 invalidate io.ifu.fetchpacket.bits.uops[0].bits.ldst invalidate io.ifu.fetchpacket.bits.uops[0].bits.ldst_is_rs1 invalidate io.ifu.fetchpacket.bits.uops[0].bits.flush_on_commit invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_unique invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_sys_pc2epc invalidate io.ifu.fetchpacket.bits.uops[0].bits.uses_stq invalidate io.ifu.fetchpacket.bits.uops[0].bits.uses_ldq invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_amo invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_fencei invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_fence invalidate io.ifu.fetchpacket.bits.uops[0].bits.mem_signed invalidate io.ifu.fetchpacket.bits.uops[0].bits.mem_size invalidate io.ifu.fetchpacket.bits.uops[0].bits.mem_cmd invalidate io.ifu.fetchpacket.bits.uops[0].bits.bypassable invalidate io.ifu.fetchpacket.bits.uops[0].bits.exc_cause invalidate io.ifu.fetchpacket.bits.uops[0].bits.exception invalidate io.ifu.fetchpacket.bits.uops[0].bits.stale_pdst invalidate io.ifu.fetchpacket.bits.uops[0].bits.ppred_busy invalidate io.ifu.fetchpacket.bits.uops[0].bits.prs3_busy invalidate io.ifu.fetchpacket.bits.uops[0].bits.prs2_busy invalidate io.ifu.fetchpacket.bits.uops[0].bits.prs1_busy invalidate io.ifu.fetchpacket.bits.uops[0].bits.ppred invalidate io.ifu.fetchpacket.bits.uops[0].bits.prs3 invalidate io.ifu.fetchpacket.bits.uops[0].bits.prs2 invalidate io.ifu.fetchpacket.bits.uops[0].bits.prs1 invalidate io.ifu.fetchpacket.bits.uops[0].bits.pdst invalidate io.ifu.fetchpacket.bits.uops[0].bits.rxq_idx invalidate io.ifu.fetchpacket.bits.uops[0].bits.stq_idx invalidate io.ifu.fetchpacket.bits.uops[0].bits.ldq_idx invalidate io.ifu.fetchpacket.bits.uops[0].bits.rob_idx invalidate io.ifu.fetchpacket.bits.uops[0].bits.csr_addr invalidate io.ifu.fetchpacket.bits.uops[0].bits.imm_packed invalidate io.ifu.fetchpacket.bits.uops[0].bits.taken invalidate io.ifu.fetchpacket.bits.uops[0].bits.pc_lob invalidate io.ifu.fetchpacket.bits.uops[0].bits.edge_inst invalidate io.ifu.fetchpacket.bits.uops[0].bits.ftq_idx invalidate io.ifu.fetchpacket.bits.uops[0].bits.br_tag invalidate io.ifu.fetchpacket.bits.uops[0].bits.br_mask invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_sfb invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_jal invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_jalr invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_br invalidate io.ifu.fetchpacket.bits.uops[0].bits.iw_p2_poisoned invalidate io.ifu.fetchpacket.bits.uops[0].bits.iw_p1_poisoned invalidate io.ifu.fetchpacket.bits.uops[0].bits.iw_state invalidate io.ifu.fetchpacket.bits.uops[0].bits.ctrl.is_std invalidate io.ifu.fetchpacket.bits.uops[0].bits.ctrl.is_sta invalidate io.ifu.fetchpacket.bits.uops[0].bits.ctrl.is_load invalidate io.ifu.fetchpacket.bits.uops[0].bits.ctrl.csr_cmd invalidate io.ifu.fetchpacket.bits.uops[0].bits.ctrl.fcn_dw invalidate io.ifu.fetchpacket.bits.uops[0].bits.ctrl.op_fcn invalidate io.ifu.fetchpacket.bits.uops[0].bits.ctrl.imm_sel invalidate io.ifu.fetchpacket.bits.uops[0].bits.ctrl.op2_sel invalidate io.ifu.fetchpacket.bits.uops[0].bits.ctrl.op1_sel invalidate io.ifu.fetchpacket.bits.uops[0].bits.ctrl.br_type invalidate io.ifu.fetchpacket.bits.uops[0].bits.fu_code invalidate io.ifu.fetchpacket.bits.uops[0].bits.iq_type invalidate io.ifu.fetchpacket.bits.uops[0].bits.debug_pc invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_rvc invalidate io.ifu.fetchpacket.bits.uops[0].bits.debug_inst invalidate io.ifu.fetchpacket.bits.uops[0].bits.inst invalidate io.ifu.fetchpacket.bits.uops[0].bits.uopc invalidate io.ifu.fetchpacket.bits.uops[0].valid invalidate io.ifu.fetchpacket.bits.uops[1].bits.debug_tsrc invalidate io.ifu.fetchpacket.bits.uops[1].bits.debug_fsrc invalidate io.ifu.fetchpacket.bits.uops[1].bits.bp_xcpt_if invalidate io.ifu.fetchpacket.bits.uops[1].bits.bp_debug_if invalidate io.ifu.fetchpacket.bits.uops[1].bits.xcpt_ma_if invalidate io.ifu.fetchpacket.bits.uops[1].bits.xcpt_ae_if invalidate io.ifu.fetchpacket.bits.uops[1].bits.xcpt_pf_if invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_single invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_val invalidate io.ifu.fetchpacket.bits.uops[1].bits.frs3_en invalidate io.ifu.fetchpacket.bits.uops[1].bits.lrs2_rtype invalidate io.ifu.fetchpacket.bits.uops[1].bits.lrs1_rtype invalidate io.ifu.fetchpacket.bits.uops[1].bits.dst_rtype invalidate io.ifu.fetchpacket.bits.uops[1].bits.ldst_val invalidate io.ifu.fetchpacket.bits.uops[1].bits.lrs3 invalidate io.ifu.fetchpacket.bits.uops[1].bits.lrs2 invalidate io.ifu.fetchpacket.bits.uops[1].bits.lrs1 invalidate io.ifu.fetchpacket.bits.uops[1].bits.ldst invalidate io.ifu.fetchpacket.bits.uops[1].bits.ldst_is_rs1 invalidate io.ifu.fetchpacket.bits.uops[1].bits.flush_on_commit invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_unique invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_sys_pc2epc invalidate io.ifu.fetchpacket.bits.uops[1].bits.uses_stq invalidate io.ifu.fetchpacket.bits.uops[1].bits.uses_ldq invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_amo invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_fencei invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_fence invalidate io.ifu.fetchpacket.bits.uops[1].bits.mem_signed invalidate io.ifu.fetchpacket.bits.uops[1].bits.mem_size invalidate io.ifu.fetchpacket.bits.uops[1].bits.mem_cmd invalidate io.ifu.fetchpacket.bits.uops[1].bits.bypassable invalidate io.ifu.fetchpacket.bits.uops[1].bits.exc_cause invalidate io.ifu.fetchpacket.bits.uops[1].bits.exception invalidate io.ifu.fetchpacket.bits.uops[1].bits.stale_pdst invalidate io.ifu.fetchpacket.bits.uops[1].bits.ppred_busy invalidate io.ifu.fetchpacket.bits.uops[1].bits.prs3_busy invalidate io.ifu.fetchpacket.bits.uops[1].bits.prs2_busy invalidate io.ifu.fetchpacket.bits.uops[1].bits.prs1_busy invalidate io.ifu.fetchpacket.bits.uops[1].bits.ppred invalidate io.ifu.fetchpacket.bits.uops[1].bits.prs3 invalidate io.ifu.fetchpacket.bits.uops[1].bits.prs2 invalidate io.ifu.fetchpacket.bits.uops[1].bits.prs1 invalidate io.ifu.fetchpacket.bits.uops[1].bits.pdst invalidate io.ifu.fetchpacket.bits.uops[1].bits.rxq_idx invalidate io.ifu.fetchpacket.bits.uops[1].bits.stq_idx invalidate io.ifu.fetchpacket.bits.uops[1].bits.ldq_idx invalidate io.ifu.fetchpacket.bits.uops[1].bits.rob_idx invalidate io.ifu.fetchpacket.bits.uops[1].bits.csr_addr invalidate io.ifu.fetchpacket.bits.uops[1].bits.imm_packed invalidate io.ifu.fetchpacket.bits.uops[1].bits.taken invalidate io.ifu.fetchpacket.bits.uops[1].bits.pc_lob invalidate io.ifu.fetchpacket.bits.uops[1].bits.edge_inst invalidate io.ifu.fetchpacket.bits.uops[1].bits.ftq_idx invalidate io.ifu.fetchpacket.bits.uops[1].bits.br_tag invalidate io.ifu.fetchpacket.bits.uops[1].bits.br_mask invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_sfb invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_jal invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_jalr invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_br invalidate io.ifu.fetchpacket.bits.uops[1].bits.iw_p2_poisoned invalidate io.ifu.fetchpacket.bits.uops[1].bits.iw_p1_poisoned invalidate io.ifu.fetchpacket.bits.uops[1].bits.iw_state invalidate io.ifu.fetchpacket.bits.uops[1].bits.ctrl.is_std invalidate io.ifu.fetchpacket.bits.uops[1].bits.ctrl.is_sta invalidate io.ifu.fetchpacket.bits.uops[1].bits.ctrl.is_load invalidate io.ifu.fetchpacket.bits.uops[1].bits.ctrl.csr_cmd invalidate io.ifu.fetchpacket.bits.uops[1].bits.ctrl.fcn_dw invalidate io.ifu.fetchpacket.bits.uops[1].bits.ctrl.op_fcn invalidate io.ifu.fetchpacket.bits.uops[1].bits.ctrl.imm_sel invalidate io.ifu.fetchpacket.bits.uops[1].bits.ctrl.op2_sel invalidate io.ifu.fetchpacket.bits.uops[1].bits.ctrl.op1_sel invalidate io.ifu.fetchpacket.bits.uops[1].bits.ctrl.br_type invalidate io.ifu.fetchpacket.bits.uops[1].bits.fu_code invalidate io.ifu.fetchpacket.bits.uops[1].bits.iq_type invalidate io.ifu.fetchpacket.bits.uops[1].bits.debug_pc invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_rvc invalidate io.ifu.fetchpacket.bits.uops[1].bits.debug_inst invalidate io.ifu.fetchpacket.bits.uops[1].bits.inst invalidate io.ifu.fetchpacket.bits.uops[1].bits.uopc invalidate io.ifu.fetchpacket.bits.uops[1].valid invalidate io.ifu.fetchpacket.bits.uops[2].bits.debug_tsrc invalidate io.ifu.fetchpacket.bits.uops[2].bits.debug_fsrc invalidate io.ifu.fetchpacket.bits.uops[2].bits.bp_xcpt_if invalidate io.ifu.fetchpacket.bits.uops[2].bits.bp_debug_if invalidate io.ifu.fetchpacket.bits.uops[2].bits.xcpt_ma_if invalidate io.ifu.fetchpacket.bits.uops[2].bits.xcpt_ae_if invalidate io.ifu.fetchpacket.bits.uops[2].bits.xcpt_pf_if invalidate io.ifu.fetchpacket.bits.uops[2].bits.fp_single invalidate io.ifu.fetchpacket.bits.uops[2].bits.fp_val invalidate io.ifu.fetchpacket.bits.uops[2].bits.frs3_en invalidate io.ifu.fetchpacket.bits.uops[2].bits.lrs2_rtype invalidate io.ifu.fetchpacket.bits.uops[2].bits.lrs1_rtype invalidate io.ifu.fetchpacket.bits.uops[2].bits.dst_rtype invalidate io.ifu.fetchpacket.bits.uops[2].bits.ldst_val invalidate io.ifu.fetchpacket.bits.uops[2].bits.lrs3 invalidate io.ifu.fetchpacket.bits.uops[2].bits.lrs2 invalidate io.ifu.fetchpacket.bits.uops[2].bits.lrs1 invalidate io.ifu.fetchpacket.bits.uops[2].bits.ldst invalidate io.ifu.fetchpacket.bits.uops[2].bits.ldst_is_rs1 invalidate io.ifu.fetchpacket.bits.uops[2].bits.flush_on_commit invalidate io.ifu.fetchpacket.bits.uops[2].bits.is_unique invalidate io.ifu.fetchpacket.bits.uops[2].bits.is_sys_pc2epc invalidate io.ifu.fetchpacket.bits.uops[2].bits.uses_stq invalidate io.ifu.fetchpacket.bits.uops[2].bits.uses_ldq invalidate io.ifu.fetchpacket.bits.uops[2].bits.is_amo invalidate io.ifu.fetchpacket.bits.uops[2].bits.is_fencei invalidate io.ifu.fetchpacket.bits.uops[2].bits.is_fence invalidate io.ifu.fetchpacket.bits.uops[2].bits.mem_signed invalidate io.ifu.fetchpacket.bits.uops[2].bits.mem_size invalidate io.ifu.fetchpacket.bits.uops[2].bits.mem_cmd invalidate io.ifu.fetchpacket.bits.uops[2].bits.bypassable invalidate io.ifu.fetchpacket.bits.uops[2].bits.exc_cause invalidate io.ifu.fetchpacket.bits.uops[2].bits.exception invalidate io.ifu.fetchpacket.bits.uops[2].bits.stale_pdst invalidate io.ifu.fetchpacket.bits.uops[2].bits.ppred_busy invalidate io.ifu.fetchpacket.bits.uops[2].bits.prs3_busy invalidate io.ifu.fetchpacket.bits.uops[2].bits.prs2_busy invalidate io.ifu.fetchpacket.bits.uops[2].bits.prs1_busy invalidate io.ifu.fetchpacket.bits.uops[2].bits.ppred invalidate io.ifu.fetchpacket.bits.uops[2].bits.prs3 invalidate io.ifu.fetchpacket.bits.uops[2].bits.prs2 invalidate io.ifu.fetchpacket.bits.uops[2].bits.prs1 invalidate io.ifu.fetchpacket.bits.uops[2].bits.pdst invalidate io.ifu.fetchpacket.bits.uops[2].bits.rxq_idx invalidate io.ifu.fetchpacket.bits.uops[2].bits.stq_idx invalidate io.ifu.fetchpacket.bits.uops[2].bits.ldq_idx invalidate io.ifu.fetchpacket.bits.uops[2].bits.rob_idx invalidate io.ifu.fetchpacket.bits.uops[2].bits.csr_addr invalidate io.ifu.fetchpacket.bits.uops[2].bits.imm_packed invalidate io.ifu.fetchpacket.bits.uops[2].bits.taken invalidate io.ifu.fetchpacket.bits.uops[2].bits.pc_lob invalidate io.ifu.fetchpacket.bits.uops[2].bits.edge_inst invalidate io.ifu.fetchpacket.bits.uops[2].bits.ftq_idx invalidate io.ifu.fetchpacket.bits.uops[2].bits.br_tag invalidate io.ifu.fetchpacket.bits.uops[2].bits.br_mask invalidate io.ifu.fetchpacket.bits.uops[2].bits.is_sfb invalidate io.ifu.fetchpacket.bits.uops[2].bits.is_jal invalidate io.ifu.fetchpacket.bits.uops[2].bits.is_jalr invalidate io.ifu.fetchpacket.bits.uops[2].bits.is_br invalidate io.ifu.fetchpacket.bits.uops[2].bits.iw_p2_poisoned invalidate io.ifu.fetchpacket.bits.uops[2].bits.iw_p1_poisoned invalidate io.ifu.fetchpacket.bits.uops[2].bits.iw_state invalidate io.ifu.fetchpacket.bits.uops[2].bits.ctrl.is_std invalidate io.ifu.fetchpacket.bits.uops[2].bits.ctrl.is_sta invalidate io.ifu.fetchpacket.bits.uops[2].bits.ctrl.is_load invalidate io.ifu.fetchpacket.bits.uops[2].bits.ctrl.csr_cmd invalidate io.ifu.fetchpacket.bits.uops[2].bits.ctrl.fcn_dw invalidate io.ifu.fetchpacket.bits.uops[2].bits.ctrl.op_fcn invalidate io.ifu.fetchpacket.bits.uops[2].bits.ctrl.imm_sel invalidate io.ifu.fetchpacket.bits.uops[2].bits.ctrl.op2_sel invalidate io.ifu.fetchpacket.bits.uops[2].bits.ctrl.op1_sel invalidate io.ifu.fetchpacket.bits.uops[2].bits.ctrl.br_type invalidate io.ifu.fetchpacket.bits.uops[2].bits.fu_code invalidate io.ifu.fetchpacket.bits.uops[2].bits.iq_type invalidate io.ifu.fetchpacket.bits.uops[2].bits.debug_pc invalidate io.ifu.fetchpacket.bits.uops[2].bits.is_rvc invalidate io.ifu.fetchpacket.bits.uops[2].bits.debug_inst invalidate io.ifu.fetchpacket.bits.uops[2].bits.inst invalidate io.ifu.fetchpacket.bits.uops[2].bits.uopc invalidate io.ifu.fetchpacket.bits.uops[2].valid invalidate io.ifu.fetchpacket.valid invalidate io.ifu.fetchpacket.ready inst memExeUnit of ALUExeUnit_4 connect memExeUnit.clock, clock connect memExeUnit.reset, reset invalidate memExeUnit.io.ll_iresp.ready inst alu_exe_unit of ALUExeUnit_5 connect alu_exe_unit.clock, clock connect alu_exe_unit.reset, reset inst alu_exe_unit_1 of ALUExeUnit_6 connect alu_exe_unit_1.clock, clock connect alu_exe_unit_1.reset, reset inst alu_exe_unit_2 of ALUExeUnit_7 connect alu_exe_unit_2.clock, clock connect alu_exe_unit_2.reset, reset inst FpPipeline of FpPipeline_1 connect FpPipeline.clock, clock connect FpPipeline.reset, reset invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.flags invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.debug_tsrc invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.debug_fsrc invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.bp_xcpt_if invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.bp_debug_if invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.xcpt_ma_if invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.xcpt_ae_if invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.xcpt_pf_if invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.fp_single invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.fp_val invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.frs3_en invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.lrs2_rtype invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.lrs1_rtype invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.dst_rtype invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ldst_val invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.lrs3 invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.lrs2 invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.lrs1 invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ldst invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ldst_is_rs1 invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.flush_on_commit invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.is_unique invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.is_sys_pc2epc invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.uses_stq invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.uses_ldq invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.is_amo invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.is_fencei invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.is_fence invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.mem_signed invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.mem_size invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.mem_cmd invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.bypassable invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.exc_cause invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.exception invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.stale_pdst invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ppred_busy invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.prs3_busy invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.prs2_busy invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.prs1_busy invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ppred invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.prs3 invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.prs2 invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.prs1 invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.pdst invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.rxq_idx invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.stq_idx invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ldq_idx invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.rob_idx invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.csr_addr invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.imm_packed invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.taken invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.pc_lob invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.edge_inst invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ftq_idx invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.br_tag invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.br_mask invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.is_sfb invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.is_jal invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.is_jalr invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.is_br invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.iw_p2_poisoned invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.iw_p1_poisoned invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.iw_state invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ctrl.is_std invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ctrl.is_sta invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ctrl.is_load invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ctrl.csr_cmd invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ctrl.fcn_dw invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ctrl.op_fcn invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ctrl.imm_sel invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ctrl.op2_sel invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ctrl.op1_sel invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.ctrl.br_type invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.fu_code invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.iq_type invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.debug_pc invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.is_rvc invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.debug_inst invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.inst invalidate FpPipeline.io.ll_wports[0].bits.fflags.bits.uop.uopc invalidate FpPipeline.io.ll_wports[0].bits.fflags.valid invalidate FpPipeline.io.ll_wports[0].bits.predicated invalidate FpPipeline.io.ll_wports[0].bits.data invalidate FpPipeline.io.ll_wports[0].bits.uop.debug_tsrc invalidate FpPipeline.io.ll_wports[0].bits.uop.debug_fsrc invalidate FpPipeline.io.ll_wports[0].bits.uop.bp_xcpt_if invalidate FpPipeline.io.ll_wports[0].bits.uop.bp_debug_if invalidate FpPipeline.io.ll_wports[0].bits.uop.xcpt_ma_if invalidate FpPipeline.io.ll_wports[0].bits.uop.xcpt_ae_if invalidate FpPipeline.io.ll_wports[0].bits.uop.xcpt_pf_if invalidate FpPipeline.io.ll_wports[0].bits.uop.fp_single invalidate FpPipeline.io.ll_wports[0].bits.uop.fp_val invalidate FpPipeline.io.ll_wports[0].bits.uop.frs3_en invalidate FpPipeline.io.ll_wports[0].bits.uop.lrs2_rtype invalidate FpPipeline.io.ll_wports[0].bits.uop.lrs1_rtype invalidate FpPipeline.io.ll_wports[0].bits.uop.dst_rtype invalidate FpPipeline.io.ll_wports[0].bits.uop.ldst_val invalidate FpPipeline.io.ll_wports[0].bits.uop.lrs3 invalidate FpPipeline.io.ll_wports[0].bits.uop.lrs2 invalidate FpPipeline.io.ll_wports[0].bits.uop.lrs1 invalidate FpPipeline.io.ll_wports[0].bits.uop.ldst invalidate FpPipeline.io.ll_wports[0].bits.uop.ldst_is_rs1 invalidate FpPipeline.io.ll_wports[0].bits.uop.flush_on_commit invalidate FpPipeline.io.ll_wports[0].bits.uop.is_unique invalidate FpPipeline.io.ll_wports[0].bits.uop.is_sys_pc2epc invalidate FpPipeline.io.ll_wports[0].bits.uop.uses_stq invalidate FpPipeline.io.ll_wports[0].bits.uop.uses_ldq invalidate FpPipeline.io.ll_wports[0].bits.uop.is_amo invalidate FpPipeline.io.ll_wports[0].bits.uop.is_fencei invalidate FpPipeline.io.ll_wports[0].bits.uop.is_fence invalidate FpPipeline.io.ll_wports[0].bits.uop.mem_signed invalidate FpPipeline.io.ll_wports[0].bits.uop.mem_size invalidate FpPipeline.io.ll_wports[0].bits.uop.mem_cmd invalidate FpPipeline.io.ll_wports[0].bits.uop.bypassable invalidate FpPipeline.io.ll_wports[0].bits.uop.exc_cause invalidate FpPipeline.io.ll_wports[0].bits.uop.exception invalidate FpPipeline.io.ll_wports[0].bits.uop.stale_pdst invalidate FpPipeline.io.ll_wports[0].bits.uop.ppred_busy invalidate FpPipeline.io.ll_wports[0].bits.uop.prs3_busy invalidate FpPipeline.io.ll_wports[0].bits.uop.prs2_busy invalidate FpPipeline.io.ll_wports[0].bits.uop.prs1_busy invalidate FpPipeline.io.ll_wports[0].bits.uop.ppred invalidate FpPipeline.io.ll_wports[0].bits.uop.prs3 invalidate FpPipeline.io.ll_wports[0].bits.uop.prs2 invalidate FpPipeline.io.ll_wports[0].bits.uop.prs1 invalidate FpPipeline.io.ll_wports[0].bits.uop.pdst invalidate FpPipeline.io.ll_wports[0].bits.uop.rxq_idx invalidate FpPipeline.io.ll_wports[0].bits.uop.stq_idx invalidate FpPipeline.io.ll_wports[0].bits.uop.ldq_idx invalidate FpPipeline.io.ll_wports[0].bits.uop.rob_idx invalidate FpPipeline.io.ll_wports[0].bits.uop.csr_addr invalidate FpPipeline.io.ll_wports[0].bits.uop.imm_packed invalidate FpPipeline.io.ll_wports[0].bits.uop.taken invalidate FpPipeline.io.ll_wports[0].bits.uop.pc_lob invalidate FpPipeline.io.ll_wports[0].bits.uop.edge_inst invalidate FpPipeline.io.ll_wports[0].bits.uop.ftq_idx invalidate FpPipeline.io.ll_wports[0].bits.uop.br_tag invalidate FpPipeline.io.ll_wports[0].bits.uop.br_mask invalidate FpPipeline.io.ll_wports[0].bits.uop.is_sfb invalidate FpPipeline.io.ll_wports[0].bits.uop.is_jal invalidate FpPipeline.io.ll_wports[0].bits.uop.is_jalr invalidate FpPipeline.io.ll_wports[0].bits.uop.is_br invalidate FpPipeline.io.ll_wports[0].bits.uop.iw_p2_poisoned invalidate FpPipeline.io.ll_wports[0].bits.uop.iw_p1_poisoned invalidate FpPipeline.io.ll_wports[0].bits.uop.iw_state invalidate FpPipeline.io.ll_wports[0].bits.uop.ctrl.is_std invalidate FpPipeline.io.ll_wports[0].bits.uop.ctrl.is_sta invalidate FpPipeline.io.ll_wports[0].bits.uop.ctrl.is_load invalidate FpPipeline.io.ll_wports[0].bits.uop.ctrl.csr_cmd invalidate FpPipeline.io.ll_wports[0].bits.uop.ctrl.fcn_dw invalidate FpPipeline.io.ll_wports[0].bits.uop.ctrl.op_fcn invalidate FpPipeline.io.ll_wports[0].bits.uop.ctrl.imm_sel invalidate FpPipeline.io.ll_wports[0].bits.uop.ctrl.op2_sel invalidate FpPipeline.io.ll_wports[0].bits.uop.ctrl.op1_sel invalidate FpPipeline.io.ll_wports[0].bits.uop.ctrl.br_type invalidate FpPipeline.io.ll_wports[0].bits.uop.fu_code invalidate FpPipeline.io.ll_wports[0].bits.uop.iq_type invalidate FpPipeline.io.ll_wports[0].bits.uop.debug_pc invalidate FpPipeline.io.ll_wports[0].bits.uop.is_rvc invalidate FpPipeline.io.ll_wports[0].bits.uop.debug_inst invalidate FpPipeline.io.ll_wports[0].bits.uop.inst invalidate FpPipeline.io.ll_wports[0].bits.uop.uopc invalidate FpPipeline.io.ll_wports[0].valid invalidate FpPipeline.io.ll_wports[0].ready invalidate FpPipeline.io.wb_valids[0] invalidate FpPipeline.io.wb_valids[1] invalidate FpPipeline.io.wb_pdsts[0] invalidate FpPipeline.io.wb_pdsts[1] inst decode_units_0 of DecodeUnit_3 connect decode_units_0.clock, clock connect decode_units_0.reset, reset inst decode_units_1 of DecodeUnit_4 connect decode_units_1.clock, clock connect decode_units_1.reset, reset inst decode_units_2 of DecodeUnit_5 connect decode_units_2.clock, clock connect decode_units_2.reset, reset inst dec_brmask_logic of BranchMaskGenerationLogic_1 connect dec_brmask_logic.clock, clock connect dec_brmask_logic.reset, reset inst rename_stage of RenameStage_2 connect rename_stage.clock, clock connect rename_stage.reset, reset inst fp_rename_stage of RenameStage_3 connect fp_rename_stage.clock, clock connect fp_rename_stage.reset, reset inst pred_rename_stage of PredRenameStage_1 connect pred_rename_stage.clock, clock connect pred_rename_stage.reset, reset inst mem_issue_unit of IssueUnitCollapsing_4 connect mem_issue_unit.clock, clock connect mem_issue_unit.reset, reset inst int_issue_unit of IssueUnitCollapsing_5 connect int_issue_unit.clock, clock connect int_issue_unit.reset, reset inst dispatcher of BasicDispatcher_1 connect dispatcher.clock, clock connect dispatcher.reset, reset inst iregfile of RegisterFileSynthesizable_4 connect iregfile.clock, clock connect iregfile.reset, reset inst pregfile of RegisterFileSynthesizable_5 connect pregfile.clock, clock connect pregfile.reset, reset invalidate pregfile.io.write_ports[0].bits.data invalidate pregfile.io.write_ports[0].bits.addr invalidate pregfile.io.write_ports[0].valid invalidate pregfile.io.read_ports[0].data invalidate pregfile.io.read_ports[0].addr invalidate pregfile.io.read_ports[1].data invalidate pregfile.io.read_ports[1].addr invalidate pregfile.io.read_ports[2].data invalidate pregfile.io.read_ports[2].addr invalidate pregfile.io.read_ports[3].data invalidate pregfile.io.read_ports[3].addr inst ll_wbarb of Arbiter2_ExeUnitResp_5 connect ll_wbarb.clock, clock connect ll_wbarb.reset, reset inst iregister_read of RegisterRead_3 connect iregister_read.clock, clock connect iregister_read.reset, reset inst rob of Rob_1 connect rob.clock, clock connect rob.reset, reset wire int_iss_wakeups : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[7] wire int_ren_wakeups : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[7] wire pred_wakeup : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<1>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}} wire dec_valids : UInt<1>[3] wire dec_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3] wire dec_fire : UInt<1>[3] wire dec_ready : UInt<1> wire dec_xcpts : UInt<1>[3] wire ren_stalls : UInt<1>[3] wire dis_valids : UInt<1>[3] wire dis_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[3] wire dis_fire : UInt<1>[3] wire dis_ready : UInt<1> wire iss_valids : UInt<1>[4] wire iss_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[4] wire bypasses : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[5] wire pred_bypasses : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<1>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[1] reg brinfos : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}[3], clock wire brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}} wire b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>} reg b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}, clock connect brupdate.b1, b1 connect brupdate.b2, b2 connect brinfos[0], alu_exe_unit.io.brinfo node _brinfos_0_valid_T = eq(rob.io.flush.valid, UInt<1>(0h0)) node _brinfos_0_valid_T_1 = and(alu_exe_unit.io.brinfo.valid, _brinfos_0_valid_T) connect brinfos[0].valid, _brinfos_0_valid_T_1 connect brinfos[1], alu_exe_unit_1.io.brinfo node _brinfos_1_valid_T = eq(rob.io.flush.valid, UInt<1>(0h0)) node _brinfos_1_valid_T_1 = and(alu_exe_unit_1.io.brinfo.valid, _brinfos_1_valid_T) connect brinfos[1].valid, _brinfos_1_valid_T_1 connect brinfos[2], alu_exe_unit_2.io.brinfo node _brinfos_2_valid_T = eq(rob.io.flush.valid, UInt<1>(0h0)) node _brinfos_2_valid_T_1 = and(alu_exe_unit_2.io.brinfo.valid, _brinfos_2_valid_T) connect brinfos[2].valid, _brinfos_2_valid_T_1 node _b1_resolve_mask_T = dshl(brinfos[0].valid, brinfos[0].uop.br_tag) node _b1_resolve_mask_T_1 = dshl(brinfos[1].valid, brinfos[1].uop.br_tag) node _b1_resolve_mask_T_2 = dshl(brinfos[2].valid, brinfos[2].uop.br_tag) node _b1_resolve_mask_T_3 = or(_b1_resolve_mask_T, _b1_resolve_mask_T_1) node _b1_resolve_mask_T_4 = or(_b1_resolve_mask_T_3, _b1_resolve_mask_T_2) connect b1.resolve_mask, _b1_resolve_mask_T_4 node _b1_mispredict_mask_T = and(brinfos[0].valid, brinfos[0].mispredict) node _b1_mispredict_mask_T_1 = dshl(_b1_mispredict_mask_T, brinfos[0].uop.br_tag) node _b1_mispredict_mask_T_2 = and(brinfos[1].valid, brinfos[1].mispredict) node _b1_mispredict_mask_T_3 = dshl(_b1_mispredict_mask_T_2, brinfos[1].uop.br_tag) node _b1_mispredict_mask_T_4 = and(brinfos[2].valid, brinfos[2].mispredict) node _b1_mispredict_mask_T_5 = dshl(_b1_mispredict_mask_T_4, brinfos[2].uop.br_tag) node _b1_mispredict_mask_T_6 = or(_b1_mispredict_mask_T_1, _b1_mispredict_mask_T_3) node _b1_mispredict_mask_T_7 = or(_b1_mispredict_mask_T_6, _b1_mispredict_mask_T_5) connect b1.mispredict_mask, _b1_mispredict_mask_T_7 node _use_this_mispredict_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _use_this_mispredict_T_1 = and(brinfos[0].valid, brinfos[0].mispredict) node _use_this_mispredict_T_2 = lt(brinfos[0].uop.rob_idx, brinfos[0].uop.rob_idx) node _use_this_mispredict_T_3 = lt(brinfos[0].uop.rob_idx, rob.io.rob_head_idx) node _use_this_mispredict_T_4 = xor(_use_this_mispredict_T_2, _use_this_mispredict_T_3) node _use_this_mispredict_T_5 = lt(brinfos[0].uop.rob_idx, rob.io.rob_head_idx) node _use_this_mispredict_T_6 = xor(_use_this_mispredict_T_4, _use_this_mispredict_T_5) node _use_this_mispredict_T_7 = and(_use_this_mispredict_T_1, _use_this_mispredict_T_6) node use_this_mispredict = or(_use_this_mispredict_T, _use_this_mispredict_T_7) node _T = and(brinfos[0].valid, brinfos[0].mispredict) node _T_1 = or(UInt<1>(0h0), _T) node _T_2 = mux(use_this_mispredict, brinfos[0], brinfos[0]) node _use_this_mispredict_T_8 = eq(_T_1, UInt<1>(0h0)) node _use_this_mispredict_T_9 = and(brinfos[1].valid, brinfos[1].mispredict) node _use_this_mispredict_T_10 = lt(brinfos[1].uop.rob_idx, _T_2.uop.rob_idx) node _use_this_mispredict_T_11 = lt(brinfos[1].uop.rob_idx, rob.io.rob_head_idx) node _use_this_mispredict_T_12 = xor(_use_this_mispredict_T_10, _use_this_mispredict_T_11) node _use_this_mispredict_T_13 = lt(_T_2.uop.rob_idx, rob.io.rob_head_idx) node _use_this_mispredict_T_14 = xor(_use_this_mispredict_T_12, _use_this_mispredict_T_13) node _use_this_mispredict_T_15 = and(_use_this_mispredict_T_9, _use_this_mispredict_T_14) node use_this_mispredict_1 = or(_use_this_mispredict_T_8, _use_this_mispredict_T_15) node _T_3 = and(brinfos[1].valid, brinfos[1].mispredict) node _T_4 = or(_T_1, _T_3) node _T_5 = mux(use_this_mispredict_1, brinfos[1], _T_2) node _use_this_mispredict_T_16 = eq(_T_4, UInt<1>(0h0)) node _use_this_mispredict_T_17 = and(brinfos[2].valid, brinfos[2].mispredict) node _use_this_mispredict_T_18 = lt(brinfos[2].uop.rob_idx, _T_5.uop.rob_idx) node _use_this_mispredict_T_19 = lt(brinfos[2].uop.rob_idx, rob.io.rob_head_idx) node _use_this_mispredict_T_20 = xor(_use_this_mispredict_T_18, _use_this_mispredict_T_19) node _use_this_mispredict_T_21 = lt(_T_5.uop.rob_idx, rob.io.rob_head_idx) node _use_this_mispredict_T_22 = xor(_use_this_mispredict_T_20, _use_this_mispredict_T_21) node _use_this_mispredict_T_23 = and(_use_this_mispredict_T_17, _use_this_mispredict_T_22) node use_this_mispredict_2 = or(_use_this_mispredict_T_16, _use_this_mispredict_T_23) node _T_6 = and(brinfos[2].valid, brinfos[2].mispredict) node _T_7 = or(_T_4, _T_6) node _T_8 = mux(use_this_mispredict_2, brinfos[2], _T_5) connect b2.mispredict, _T_7 connect b2.cfi_type, _T_8.cfi_type connect b2.taken, _T_8.taken connect b2.pc_sel, _T_8.pc_sel wire b2_uop_out : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect b2_uop_out, _T_8.uop node _b2_uop_out_br_mask_T = not(brupdate.b1.resolve_mask) node _b2_uop_out_br_mask_T_1 = and(_T_8.uop.br_mask, _b2_uop_out_br_mask_T) connect b2_uop_out.br_mask, _b2_uop_out_br_mask_T_1 connect b2.uop, b2_uop_out reg b2_jalr_target_REG : UInt, clock connect b2_jalr_target_REG, alu_exe_unit.io.brinfo.jalr_target connect b2.jalr_target, b2_jalr_target_REG connect b2.target_offset, _T_8.target_offset node _T_9 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _T_10 = or(_T_9, brupdate.b2.mispredict) node _T_11 = and(_T_10, rob.io.commit.rollback) node _T_12 = eq(_T_11, UInt<1>(0h0)) node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : node _T_15 = eq(_T_12, UInt<1>(0h0)) when _T_15 : printf(clock, UInt<1>(0h1), "Assertion failed: Can't have a mispredict during rollback.\n at core.scala:224 assert (!((brupdate.b1.mispredict_mask =/= 0.U \|\| brupdate.b2.mispredict)\n") : printf assert(clock, _T_12, UInt<1>(0h1), "") : assert connect io.ifu.brupdate, brupdate connect memExeUnit.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect memExeUnit.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect memExeUnit.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect memExeUnit.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect memExeUnit.io.brupdate.b2.taken, brupdate.b2.taken connect memExeUnit.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect memExeUnit.io.brupdate.b2.valid, brupdate.b2.valid connect memExeUnit.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect memExeUnit.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect memExeUnit.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect memExeUnit.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect memExeUnit.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect memExeUnit.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect memExeUnit.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect memExeUnit.io.brupdate.b2.uop.fp_single, brupdate.b2.uop.fp_single connect memExeUnit.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect memExeUnit.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect memExeUnit.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect memExeUnit.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect memExeUnit.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect memExeUnit.io.brupdate.b2.uop.ldst_val, brupdate.b2.uop.ldst_val connect memExeUnit.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect memExeUnit.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect memExeUnit.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect memExeUnit.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect memExeUnit.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect memExeUnit.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect memExeUnit.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect memExeUnit.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect memExeUnit.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect memExeUnit.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect memExeUnit.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect memExeUnit.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect memExeUnit.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect memExeUnit.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect memExeUnit.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect memExeUnit.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect memExeUnit.io.brupdate.b2.uop.bypassable, brupdate.b2.uop.bypassable connect memExeUnit.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect memExeUnit.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect memExeUnit.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect memExeUnit.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect memExeUnit.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect memExeUnit.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect memExeUnit.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect memExeUnit.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect memExeUnit.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect memExeUnit.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect memExeUnit.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect memExeUnit.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect memExeUnit.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect memExeUnit.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect memExeUnit.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect memExeUnit.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect memExeUnit.io.brupdate.b2.uop.csr_addr, brupdate.b2.uop.csr_addr connect memExeUnit.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect memExeUnit.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect memExeUnit.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect memExeUnit.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect memExeUnit.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect memExeUnit.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect memExeUnit.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect memExeUnit.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect memExeUnit.io.brupdate.b2.uop.is_jal, brupdate.b2.uop.is_jal connect memExeUnit.io.brupdate.b2.uop.is_jalr, brupdate.b2.uop.is_jalr connect memExeUnit.io.brupdate.b2.uop.is_br, brupdate.b2.uop.is_br connect memExeUnit.io.brupdate.b2.uop.iw_p2_poisoned, brupdate.b2.uop.iw_p2_poisoned connect memExeUnit.io.brupdate.b2.uop.iw_p1_poisoned, brupdate.b2.uop.iw_p1_poisoned connect memExeUnit.io.brupdate.b2.uop.iw_state, brupdate.b2.uop.iw_state connect memExeUnit.io.brupdate.b2.uop.ctrl.is_std, brupdate.b2.uop.ctrl.is_std connect memExeUnit.io.brupdate.b2.uop.ctrl.is_sta, brupdate.b2.uop.ctrl.is_sta connect memExeUnit.io.brupdate.b2.uop.ctrl.is_load, brupdate.b2.uop.ctrl.is_load connect memExeUnit.io.brupdate.b2.uop.ctrl.csr_cmd, brupdate.b2.uop.ctrl.csr_cmd connect memExeUnit.io.brupdate.b2.uop.ctrl.fcn_dw, brupdate.b2.uop.ctrl.fcn_dw connect memExeUnit.io.brupdate.b2.uop.ctrl.op_fcn, brupdate.b2.uop.ctrl.op_fcn connect memExeUnit.io.brupdate.b2.uop.ctrl.imm_sel, brupdate.b2.uop.ctrl.imm_sel connect memExeUnit.io.brupdate.b2.uop.ctrl.op2_sel, brupdate.b2.uop.ctrl.op2_sel connect memExeUnit.io.brupdate.b2.uop.ctrl.op1_sel, brupdate.b2.uop.ctrl.op1_sel connect memExeUnit.io.brupdate.b2.uop.ctrl.br_type, brupdate.b2.uop.ctrl.br_type connect memExeUnit.io.brupdate.b2.uop.fu_code, brupdate.b2.uop.fu_code connect memExeUnit.io.brupdate.b2.uop.iq_type, brupdate.b2.uop.iq_type connect memExeUnit.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect memExeUnit.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect memExeUnit.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect memExeUnit.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect memExeUnit.io.brupdate.b2.uop.uopc, brupdate.b2.uop.uopc connect memExeUnit.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect memExeUnit.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect alu_exe_unit.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect alu_exe_unit.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect alu_exe_unit.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect alu_exe_unit.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect alu_exe_unit.io.brupdate.b2.taken, brupdate.b2.taken connect alu_exe_unit.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect alu_exe_unit.io.brupdate.b2.valid, brupdate.b2.valid connect alu_exe_unit.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect alu_exe_unit.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect alu_exe_unit.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect alu_exe_unit.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect alu_exe_unit.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect alu_exe_unit.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect alu_exe_unit.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect alu_exe_unit.io.brupdate.b2.uop.fp_single, brupdate.b2.uop.fp_single connect alu_exe_unit.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect alu_exe_unit.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect alu_exe_unit.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect alu_exe_unit.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect alu_exe_unit.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect alu_exe_unit.io.brupdate.b2.uop.ldst_val, brupdate.b2.uop.ldst_val connect alu_exe_unit.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect alu_exe_unit.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect alu_exe_unit.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect alu_exe_unit.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect alu_exe_unit.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect alu_exe_unit.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect alu_exe_unit.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect alu_exe_unit.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect alu_exe_unit.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect alu_exe_unit.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect alu_exe_unit.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect alu_exe_unit.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect alu_exe_unit.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect alu_exe_unit.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect alu_exe_unit.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect alu_exe_unit.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect alu_exe_unit.io.brupdate.b2.uop.bypassable, brupdate.b2.uop.bypassable connect alu_exe_unit.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect alu_exe_unit.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect alu_exe_unit.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect alu_exe_unit.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect alu_exe_unit.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect alu_exe_unit.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect alu_exe_unit.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect alu_exe_unit.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect alu_exe_unit.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect alu_exe_unit.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect alu_exe_unit.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect alu_exe_unit.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect alu_exe_unit.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect alu_exe_unit.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect alu_exe_unit.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect alu_exe_unit.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect alu_exe_unit.io.brupdate.b2.uop.csr_addr, brupdate.b2.uop.csr_addr connect alu_exe_unit.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect alu_exe_unit.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect alu_exe_unit.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect alu_exe_unit.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect alu_exe_unit.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect alu_exe_unit.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect alu_exe_unit.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect alu_exe_unit.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect alu_exe_unit.io.brupdate.b2.uop.is_jal, brupdate.b2.uop.is_jal connect alu_exe_unit.io.brupdate.b2.uop.is_jalr, brupdate.b2.uop.is_jalr connect alu_exe_unit.io.brupdate.b2.uop.is_br, brupdate.b2.uop.is_br connect alu_exe_unit.io.brupdate.b2.uop.iw_p2_poisoned, brupdate.b2.uop.iw_p2_poisoned connect alu_exe_unit.io.brupdate.b2.uop.iw_p1_poisoned, brupdate.b2.uop.iw_p1_poisoned connect alu_exe_unit.io.brupdate.b2.uop.iw_state, brupdate.b2.uop.iw_state connect alu_exe_unit.io.brupdate.b2.uop.ctrl.is_std, brupdate.b2.uop.ctrl.is_std connect alu_exe_unit.io.brupdate.b2.uop.ctrl.is_sta, brupdate.b2.uop.ctrl.is_sta connect alu_exe_unit.io.brupdate.b2.uop.ctrl.is_load, brupdate.b2.uop.ctrl.is_load connect alu_exe_unit.io.brupdate.b2.uop.ctrl.csr_cmd, brupdate.b2.uop.ctrl.csr_cmd connect alu_exe_unit.io.brupdate.b2.uop.ctrl.fcn_dw, brupdate.b2.uop.ctrl.fcn_dw connect alu_exe_unit.io.brupdate.b2.uop.ctrl.op_fcn, brupdate.b2.uop.ctrl.op_fcn connect alu_exe_unit.io.brupdate.b2.uop.ctrl.imm_sel, brupdate.b2.uop.ctrl.imm_sel connect alu_exe_unit.io.brupdate.b2.uop.ctrl.op2_sel, brupdate.b2.uop.ctrl.op2_sel connect alu_exe_unit.io.brupdate.b2.uop.ctrl.op1_sel, brupdate.b2.uop.ctrl.op1_sel connect alu_exe_unit.io.brupdate.b2.uop.ctrl.br_type, brupdate.b2.uop.ctrl.br_type connect alu_exe_unit.io.brupdate.b2.uop.fu_code, brupdate.b2.uop.fu_code connect alu_exe_unit.io.brupdate.b2.uop.iq_type, brupdate.b2.uop.iq_type connect alu_exe_unit.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect alu_exe_unit.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect alu_exe_unit.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect alu_exe_unit.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect alu_exe_unit.io.brupdate.b2.uop.uopc, brupdate.b2.uop.uopc connect alu_exe_unit.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect alu_exe_unit.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect alu_exe_unit_1.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect alu_exe_unit_1.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect alu_exe_unit_1.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect alu_exe_unit_1.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect alu_exe_unit_1.io.brupdate.b2.taken, brupdate.b2.taken connect alu_exe_unit_1.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect alu_exe_unit_1.io.brupdate.b2.valid, brupdate.b2.valid connect alu_exe_unit_1.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect alu_exe_unit_1.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect alu_exe_unit_1.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect alu_exe_unit_1.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect alu_exe_unit_1.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect alu_exe_unit_1.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect alu_exe_unit_1.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect alu_exe_unit_1.io.brupdate.b2.uop.fp_single, brupdate.b2.uop.fp_single connect alu_exe_unit_1.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect alu_exe_unit_1.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect alu_exe_unit_1.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect alu_exe_unit_1.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect alu_exe_unit_1.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect alu_exe_unit_1.io.brupdate.b2.uop.ldst_val, brupdate.b2.uop.ldst_val connect alu_exe_unit_1.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect alu_exe_unit_1.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect alu_exe_unit_1.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect alu_exe_unit_1.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect alu_exe_unit_1.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect alu_exe_unit_1.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect alu_exe_unit_1.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect alu_exe_unit_1.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect alu_exe_unit_1.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect alu_exe_unit_1.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect alu_exe_unit_1.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect alu_exe_unit_1.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect alu_exe_unit_1.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect alu_exe_unit_1.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect alu_exe_unit_1.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect alu_exe_unit_1.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect alu_exe_unit_1.io.brupdate.b2.uop.bypassable, brupdate.b2.uop.bypassable connect alu_exe_unit_1.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect alu_exe_unit_1.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect alu_exe_unit_1.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect alu_exe_unit_1.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect alu_exe_unit_1.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect alu_exe_unit_1.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect alu_exe_unit_1.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect alu_exe_unit_1.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect alu_exe_unit_1.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect alu_exe_unit_1.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect alu_exe_unit_1.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect alu_exe_unit_1.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect alu_exe_unit_1.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect alu_exe_unit_1.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect alu_exe_unit_1.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect alu_exe_unit_1.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect alu_exe_unit_1.io.brupdate.b2.uop.csr_addr, brupdate.b2.uop.csr_addr connect alu_exe_unit_1.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect alu_exe_unit_1.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect alu_exe_unit_1.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect alu_exe_unit_1.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect alu_exe_unit_1.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect alu_exe_unit_1.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect alu_exe_unit_1.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect alu_exe_unit_1.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect alu_exe_unit_1.io.brupdate.b2.uop.is_jal, brupdate.b2.uop.is_jal connect alu_exe_unit_1.io.brupdate.b2.uop.is_jalr, brupdate.b2.uop.is_jalr connect alu_exe_unit_1.io.brupdate.b2.uop.is_br, brupdate.b2.uop.is_br connect alu_exe_unit_1.io.brupdate.b2.uop.iw_p2_poisoned, brupdate.b2.uop.iw_p2_poisoned connect alu_exe_unit_1.io.brupdate.b2.uop.iw_p1_poisoned, brupdate.b2.uop.iw_p1_poisoned connect alu_exe_unit_1.io.brupdate.b2.uop.iw_state, brupdate.b2.uop.iw_state connect alu_exe_unit_1.io.brupdate.b2.uop.ctrl.is_std, brupdate.b2.uop.ctrl.is_std connect alu_exe_unit_1.io.brupdate.b2.uop.ctrl.is_sta, brupdate.b2.uop.ctrl.is_sta connect alu_exe_unit_1.io.brupdate.b2.uop.ctrl.is_load, brupdate.b2.uop.ctrl.is_load connect alu_exe_unit_1.io.brupdate.b2.uop.ctrl.csr_cmd, brupdate.b2.uop.ctrl.csr_cmd connect alu_exe_unit_1.io.brupdate.b2.uop.ctrl.fcn_dw, brupdate.b2.uop.ctrl.fcn_dw connect alu_exe_unit_1.io.brupdate.b2.uop.ctrl.op_fcn, brupdate.b2.uop.ctrl.op_fcn connect alu_exe_unit_1.io.brupdate.b2.uop.ctrl.imm_sel, brupdate.b2.uop.ctrl.imm_sel connect alu_exe_unit_1.io.brupdate.b2.uop.ctrl.op2_sel, brupdate.b2.uop.ctrl.op2_sel connect alu_exe_unit_1.io.brupdate.b2.uop.ctrl.op1_sel, brupdate.b2.uop.ctrl.op1_sel connect alu_exe_unit_1.io.brupdate.b2.uop.ctrl.br_type, brupdate.b2.uop.ctrl.br_type connect alu_exe_unit_1.io.brupdate.b2.uop.fu_code, brupdate.b2.uop.fu_code connect alu_exe_unit_1.io.brupdate.b2.uop.iq_type, brupdate.b2.uop.iq_type connect alu_exe_unit_1.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect alu_exe_unit_1.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect alu_exe_unit_1.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect alu_exe_unit_1.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect alu_exe_unit_1.io.brupdate.b2.uop.uopc, brupdate.b2.uop.uopc connect alu_exe_unit_1.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect alu_exe_unit_1.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect alu_exe_unit_2.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect alu_exe_unit_2.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect alu_exe_unit_2.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect alu_exe_unit_2.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect alu_exe_unit_2.io.brupdate.b2.taken, brupdate.b2.taken connect alu_exe_unit_2.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect alu_exe_unit_2.io.brupdate.b2.valid, brupdate.b2.valid connect alu_exe_unit_2.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect alu_exe_unit_2.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect alu_exe_unit_2.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect alu_exe_unit_2.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect alu_exe_unit_2.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect alu_exe_unit_2.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect alu_exe_unit_2.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect alu_exe_unit_2.io.brupdate.b2.uop.fp_single, brupdate.b2.uop.fp_single connect alu_exe_unit_2.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect alu_exe_unit_2.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect alu_exe_unit_2.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect alu_exe_unit_2.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect alu_exe_unit_2.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect alu_exe_unit_2.io.brupdate.b2.uop.ldst_val, brupdate.b2.uop.ldst_val connect alu_exe_unit_2.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect alu_exe_unit_2.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect alu_exe_unit_2.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect alu_exe_unit_2.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect alu_exe_unit_2.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect alu_exe_unit_2.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect alu_exe_unit_2.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect alu_exe_unit_2.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect alu_exe_unit_2.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect alu_exe_unit_2.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect alu_exe_unit_2.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect alu_exe_unit_2.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect alu_exe_unit_2.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect alu_exe_unit_2.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect alu_exe_unit_2.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect alu_exe_unit_2.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect alu_exe_unit_2.io.brupdate.b2.uop.bypassable, brupdate.b2.uop.bypassable connect alu_exe_unit_2.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect alu_exe_unit_2.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect alu_exe_unit_2.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect alu_exe_unit_2.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect alu_exe_unit_2.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect alu_exe_unit_2.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect alu_exe_unit_2.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect alu_exe_unit_2.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect alu_exe_unit_2.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect alu_exe_unit_2.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect alu_exe_unit_2.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect alu_exe_unit_2.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect alu_exe_unit_2.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect alu_exe_unit_2.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect alu_exe_unit_2.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect alu_exe_unit_2.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect alu_exe_unit_2.io.brupdate.b2.uop.csr_addr, brupdate.b2.uop.csr_addr connect alu_exe_unit_2.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect alu_exe_unit_2.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect alu_exe_unit_2.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect alu_exe_unit_2.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect alu_exe_unit_2.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect alu_exe_unit_2.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect alu_exe_unit_2.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect alu_exe_unit_2.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect alu_exe_unit_2.io.brupdate.b2.uop.is_jal, brupdate.b2.uop.is_jal connect alu_exe_unit_2.io.brupdate.b2.uop.is_jalr, brupdate.b2.uop.is_jalr connect alu_exe_unit_2.io.brupdate.b2.uop.is_br, brupdate.b2.uop.is_br connect alu_exe_unit_2.io.brupdate.b2.uop.iw_p2_poisoned, brupdate.b2.uop.iw_p2_poisoned connect alu_exe_unit_2.io.brupdate.b2.uop.iw_p1_poisoned, brupdate.b2.uop.iw_p1_poisoned connect alu_exe_unit_2.io.brupdate.b2.uop.iw_state, brupdate.b2.uop.iw_state connect alu_exe_unit_2.io.brupdate.b2.uop.ctrl.is_std, brupdate.b2.uop.ctrl.is_std connect alu_exe_unit_2.io.brupdate.b2.uop.ctrl.is_sta, brupdate.b2.uop.ctrl.is_sta connect alu_exe_unit_2.io.brupdate.b2.uop.ctrl.is_load, brupdate.b2.uop.ctrl.is_load connect alu_exe_unit_2.io.brupdate.b2.uop.ctrl.csr_cmd, brupdate.b2.uop.ctrl.csr_cmd connect alu_exe_unit_2.io.brupdate.b2.uop.ctrl.fcn_dw, brupdate.b2.uop.ctrl.fcn_dw connect alu_exe_unit_2.io.brupdate.b2.uop.ctrl.op_fcn, brupdate.b2.uop.ctrl.op_fcn connect alu_exe_unit_2.io.brupdate.b2.uop.ctrl.imm_sel, brupdate.b2.uop.ctrl.imm_sel connect alu_exe_unit_2.io.brupdate.b2.uop.ctrl.op2_sel, brupdate.b2.uop.ctrl.op2_sel connect alu_exe_unit_2.io.brupdate.b2.uop.ctrl.op1_sel, brupdate.b2.uop.ctrl.op1_sel connect alu_exe_unit_2.io.brupdate.b2.uop.ctrl.br_type, brupdate.b2.uop.ctrl.br_type connect alu_exe_unit_2.io.brupdate.b2.uop.fu_code, brupdate.b2.uop.fu_code connect alu_exe_unit_2.io.brupdate.b2.uop.iq_type, brupdate.b2.uop.iq_type connect alu_exe_unit_2.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect alu_exe_unit_2.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect alu_exe_unit_2.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect alu_exe_unit_2.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect alu_exe_unit_2.io.brupdate.b2.uop.uopc, brupdate.b2.uop.uopc connect alu_exe_unit_2.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect alu_exe_unit_2.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect FpPipeline.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect FpPipeline.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect FpPipeline.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect FpPipeline.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect FpPipeline.io.brupdate.b2.taken, brupdate.b2.taken connect FpPipeline.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect FpPipeline.io.brupdate.b2.valid, brupdate.b2.valid connect FpPipeline.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect FpPipeline.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect FpPipeline.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect FpPipeline.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect FpPipeline.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect FpPipeline.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect FpPipeline.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect FpPipeline.io.brupdate.b2.uop.fp_single, brupdate.b2.uop.fp_single connect FpPipeline.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect FpPipeline.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect FpPipeline.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect FpPipeline.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect FpPipeline.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect FpPipeline.io.brupdate.b2.uop.ldst_val, brupdate.b2.uop.ldst_val connect FpPipeline.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect FpPipeline.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect FpPipeline.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect FpPipeline.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect FpPipeline.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect FpPipeline.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect FpPipeline.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect FpPipeline.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect FpPipeline.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect FpPipeline.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect FpPipeline.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect FpPipeline.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect FpPipeline.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect FpPipeline.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect FpPipeline.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect FpPipeline.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect FpPipeline.io.brupdate.b2.uop.bypassable, brupdate.b2.uop.bypassable connect FpPipeline.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect FpPipeline.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect FpPipeline.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect FpPipeline.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect FpPipeline.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect FpPipeline.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect FpPipeline.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect FpPipeline.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect FpPipeline.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect FpPipeline.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect FpPipeline.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect FpPipeline.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect FpPipeline.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect FpPipeline.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect FpPipeline.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect FpPipeline.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect FpPipeline.io.brupdate.b2.uop.csr_addr, brupdate.b2.uop.csr_addr connect FpPipeline.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect FpPipeline.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect FpPipeline.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect FpPipeline.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect FpPipeline.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect FpPipeline.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect FpPipeline.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect FpPipeline.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect FpPipeline.io.brupdate.b2.uop.is_jal, brupdate.b2.uop.is_jal connect FpPipeline.io.brupdate.b2.uop.is_jalr, brupdate.b2.uop.is_jalr connect FpPipeline.io.brupdate.b2.uop.is_br, brupdate.b2.uop.is_br connect FpPipeline.io.brupdate.b2.uop.iw_p2_poisoned, brupdate.b2.uop.iw_p2_poisoned connect FpPipeline.io.brupdate.b2.uop.iw_p1_poisoned, brupdate.b2.uop.iw_p1_poisoned connect FpPipeline.io.brupdate.b2.uop.iw_state, brupdate.b2.uop.iw_state connect FpPipeline.io.brupdate.b2.uop.ctrl.is_std, brupdate.b2.uop.ctrl.is_std connect FpPipeline.io.brupdate.b2.uop.ctrl.is_sta, brupdate.b2.uop.ctrl.is_sta connect FpPipeline.io.brupdate.b2.uop.ctrl.is_load, brupdate.b2.uop.ctrl.is_load connect FpPipeline.io.brupdate.b2.uop.ctrl.csr_cmd, brupdate.b2.uop.ctrl.csr_cmd connect FpPipeline.io.brupdate.b2.uop.ctrl.fcn_dw, brupdate.b2.uop.ctrl.fcn_dw connect FpPipeline.io.brupdate.b2.uop.ctrl.op_fcn, brupdate.b2.uop.ctrl.op_fcn connect FpPipeline.io.brupdate.b2.uop.ctrl.imm_sel, brupdate.b2.uop.ctrl.imm_sel connect FpPipeline.io.brupdate.b2.uop.ctrl.op2_sel, brupdate.b2.uop.ctrl.op2_sel connect FpPipeline.io.brupdate.b2.uop.ctrl.op1_sel, brupdate.b2.uop.ctrl.op1_sel connect FpPipeline.io.brupdate.b2.uop.ctrl.br_type, brupdate.b2.uop.ctrl.br_type connect FpPipeline.io.brupdate.b2.uop.fu_code, brupdate.b2.uop.fu_code connect FpPipeline.io.brupdate.b2.uop.iq_type, brupdate.b2.uop.iq_type connect FpPipeline.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect FpPipeline.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect FpPipeline.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect FpPipeline.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect FpPipeline.io.brupdate.b2.uop.uopc, brupdate.b2.uop.uopc connect FpPipeline.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect FpPipeline.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect memExeUnit.io.lsu_io, io.lsu.exe[0] wire _hits_WIRE : UInt<1>[4] connect _hits_WIRE[0], UInt<1>(0h0) connect _hits_WIRE[1], UInt<1>(0h0) connect _hits_WIRE[2], UInt<1>(0h0) connect _hits_WIRE[3], UInt<1>(0h0) wire hits : UInt<1>[4] connect hits, _hits_WIRE wire _hits_WIRE_1 : UInt<1>[5] connect _hits_WIRE_1[0], UInt<1>(0h0) connect _hits_WIRE_1[1], UInt<1>(0h0) connect _hits_WIRE_1[2], UInt<1>(0h0) connect _hits_WIRE_1[3], UInt<1>(0h0) connect _hits_WIRE_1[4], UInt<1>(0h0) wire hits_1 : UInt<1>[5] connect hits_1, _hits_WIRE_1 wire _hits_WIRE_2 : UInt<1>[6] connect _hits_WIRE_2[0], UInt<1>(0h0) connect _hits_WIRE_2[1], UInt<1>(0h0) connect _hits_WIRE_2[2], UInt<1>(0h0) connect _hits_WIRE_2[3], UInt<1>(0h0) connect _hits_WIRE_2[4], UInt<1>(0h0) connect _hits_WIRE_2[5], UInt<1>(0h0) wire hits_2 : UInt<1>[6] connect hits_2, _hits_WIRE_2 inst csr of CSRFile_3 connect csr.clock, clock connect csr.reset, reset invalidate csr.io.inst[0] invalidate csr.io.inst[1] invalidate csr.io.inst[2] connect csr.io.rocc_interrupt, io.rocc.interrupt connect csr.io.mhtinst_read_pseudo, UInt<1>(0h0) wire custom_csrs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[2]} connect custom_csrs.csrs[0].stall, UInt<1>(0h0) connect custom_csrs.csrs[0].set, UInt<1>(0h0) invalidate custom_csrs.csrs[0].sdata connect custom_csrs.csrs[1].stall, UInt<1>(0h0) connect custom_csrs.csrs[1].set, UInt<1>(0h0) invalidate custom_csrs.csrs[1].sdata connect csr.io.customCSRs[0].sdata, custom_csrs.csrs[0].sdata connect csr.io.customCSRs[0].set, custom_csrs.csrs[0].set connect csr.io.customCSRs[0].stall, custom_csrs.csrs[0].stall connect custom_csrs.csrs[0].value, csr.io.customCSRs[0].value connect custom_csrs.csrs[0].wdata, csr.io.customCSRs[0].wdata connect custom_csrs.csrs[0].wen, csr.io.customCSRs[0].wen connect custom_csrs.csrs[0].ren, csr.io.customCSRs[0].ren connect csr.io.customCSRs[1].sdata, custom_csrs.csrs[1].sdata connect csr.io.customCSRs[1].set, custom_csrs.csrs[1].set connect csr.io.customCSRs[1].stall, custom_csrs.csrs[1].stall connect custom_csrs.csrs[1].value, csr.io.customCSRs[1].value connect custom_csrs.csrs[1].wdata, csr.io.customCSRs[1].wdata connect custom_csrs.csrs[1].wen, csr.io.customCSRs[1].wen connect custom_csrs.csrs[1].ren, csr.io.customCSRs[1].ren regreset debug_tsc_reg : UInt<64>, clock, reset, UInt<64>(0h0) regreset debug_irt_reg : UInt<64>, clock, reset, UInt<64>(0h0) reg debug_brs : UInt<64>[4], clock reg debug_jals : UInt<64>[4], clock reg debug_jalrs : UInt<64>[4], clock node _debug_brs_0_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<1>(0h0)) node _debug_brs_0_T_1 = and(rob.io.commit.arch_valids[0], _debug_brs_0_T) node _debug_brs_0_T_2 = and(_debug_brs_0_T_1, rob.io.commit.uops[0].is_br) node _debug_brs_0_T_3 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<1>(0h0)) node _debug_brs_0_T_4 = and(rob.io.commit.arch_valids[1], _debug_brs_0_T_3) node _debug_brs_0_T_5 = and(_debug_brs_0_T_4, rob.io.commit.uops[1].is_br) node _debug_brs_0_T_6 = eq(rob.io.commit.uops[2].debug_fsrc, UInt<1>(0h0)) node _debug_brs_0_T_7 = and(rob.io.commit.arch_valids[2], _debug_brs_0_T_6) node _debug_brs_0_T_8 = and(_debug_brs_0_T_7, rob.io.commit.uops[2].is_br) wire _debug_brs_0_WIRE : UInt<1>[3] connect _debug_brs_0_WIRE[0], _debug_brs_0_T_2 connect _debug_brs_0_WIRE[1], _debug_brs_0_T_5 connect _debug_brs_0_WIRE[2], _debug_brs_0_T_8 node _debug_brs_0_T_9 = add(_debug_brs_0_WIRE[1], _debug_brs_0_WIRE[2]) node _debug_brs_0_T_10 = bits(_debug_brs_0_T_9, 1, 0) node _debug_brs_0_T_11 = add(_debug_brs_0_WIRE[0], _debug_brs_0_T_10) node _debug_brs_0_T_12 = bits(_debug_brs_0_T_11, 1, 0) node _debug_brs_0_T_13 = add(debug_brs[0], _debug_brs_0_T_12) node _debug_brs_0_T_14 = tail(_debug_brs_0_T_13, 1) connect debug_brs[0], _debug_brs_0_T_14 node _debug_jals_0_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<1>(0h0)) node _debug_jals_0_T_1 = and(rob.io.commit.arch_valids[0], _debug_jals_0_T) node _debug_jals_0_T_2 = and(_debug_jals_0_T_1, rob.io.commit.uops[0].is_jal) node _debug_jals_0_T_3 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<1>(0h0)) node _debug_jals_0_T_4 = and(rob.io.commit.arch_valids[1], _debug_jals_0_T_3) node _debug_jals_0_T_5 = and(_debug_jals_0_T_4, rob.io.commit.uops[1].is_jal) node _debug_jals_0_T_6 = eq(rob.io.commit.uops[2].debug_fsrc, UInt<1>(0h0)) node _debug_jals_0_T_7 = and(rob.io.commit.arch_valids[2], _debug_jals_0_T_6) node _debug_jals_0_T_8 = and(_debug_jals_0_T_7, rob.io.commit.uops[2].is_jal) wire _debug_jals_0_WIRE : UInt<1>[3] connect _debug_jals_0_WIRE[0], _debug_jals_0_T_2 connect _debug_jals_0_WIRE[1], _debug_jals_0_T_5 connect _debug_jals_0_WIRE[2], _debug_jals_0_T_8 node _debug_jals_0_T_9 = add(_debug_jals_0_WIRE[1], _debug_jals_0_WIRE[2]) node _debug_jals_0_T_10 = bits(_debug_jals_0_T_9, 1, 0) node _debug_jals_0_T_11 = add(_debug_jals_0_WIRE[0], _debug_jals_0_T_10) node _debug_jals_0_T_12 = bits(_debug_jals_0_T_11, 1, 0) node _debug_jals_0_T_13 = add(debug_jals[0], _debug_jals_0_T_12) node _debug_jals_0_T_14 = tail(_debug_jals_0_T_13, 1) connect debug_jals[0], _debug_jals_0_T_14 node _debug_jalrs_0_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<1>(0h0)) node _debug_jalrs_0_T_1 = and(rob.io.commit.arch_valids[0], _debug_jalrs_0_T) node _debug_jalrs_0_T_2 = and(_debug_jalrs_0_T_1, rob.io.commit.uops[0].is_jalr) node _debug_jalrs_0_T_3 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<1>(0h0)) node _debug_jalrs_0_T_4 = and(rob.io.commit.arch_valids[1], _debug_jalrs_0_T_3) node _debug_jalrs_0_T_5 = and(_debug_jalrs_0_T_4, rob.io.commit.uops[1].is_jalr) node _debug_jalrs_0_T_6 = eq(rob.io.commit.uops[2].debug_fsrc, UInt<1>(0h0)) node _debug_jalrs_0_T_7 = and(rob.io.commit.arch_valids[2], _debug_jalrs_0_T_6) node _debug_jalrs_0_T_8 = and(_debug_jalrs_0_T_7, rob.io.commit.uops[2].is_jalr) wire _debug_jalrs_0_WIRE : UInt<1>[3] connect _debug_jalrs_0_WIRE[0], _debug_jalrs_0_T_2 connect _debug_jalrs_0_WIRE[1], _debug_jalrs_0_T_5 connect _debug_jalrs_0_WIRE[2], _debug_jalrs_0_T_8 node _debug_jalrs_0_T_9 = add(_debug_jalrs_0_WIRE[1], _debug_jalrs_0_WIRE[2]) node _debug_jalrs_0_T_10 = bits(_debug_jalrs_0_T_9, 1, 0) node _debug_jalrs_0_T_11 = add(_debug_jalrs_0_WIRE[0], _debug_jalrs_0_T_10) node _debug_jalrs_0_T_12 = bits(_debug_jalrs_0_T_11, 1, 0) node _debug_jalrs_0_T_13 = add(debug_jalrs[0], _debug_jalrs_0_T_12) node _debug_jalrs_0_T_14 = tail(_debug_jalrs_0_T_13, 1) connect debug_jalrs[0], _debug_jalrs_0_T_14 node _debug_brs_1_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<1>(0h1)) node _debug_brs_1_T_1 = and(rob.io.commit.arch_valids[0], _debug_brs_1_T) node _debug_brs_1_T_2 = and(_debug_brs_1_T_1, rob.io.commit.uops[0].is_br) node _debug_brs_1_T_3 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<1>(0h1)) node _debug_brs_1_T_4 = and(rob.io.commit.arch_valids[1], _debug_brs_1_T_3) node _debug_brs_1_T_5 = and(_debug_brs_1_T_4, rob.io.commit.uops[1].is_br) node _debug_brs_1_T_6 = eq(rob.io.commit.uops[2].debug_fsrc, UInt<1>(0h1)) node _debug_brs_1_T_7 = and(rob.io.commit.arch_valids[2], _debug_brs_1_T_6) node _debug_brs_1_T_8 = and(_debug_brs_1_T_7, rob.io.commit.uops[2].is_br) wire _debug_brs_1_WIRE : UInt<1>[3] connect _debug_brs_1_WIRE[0], _debug_brs_1_T_2 connect _debug_brs_1_WIRE[1], _debug_brs_1_T_5 connect _debug_brs_1_WIRE[2], _debug_brs_1_T_8 node _debug_brs_1_T_9 = add(_debug_brs_1_WIRE[1], _debug_brs_1_WIRE[2]) node _debug_brs_1_T_10 = bits(_debug_brs_1_T_9, 1, 0) node _debug_brs_1_T_11 = add(_debug_brs_1_WIRE[0], _debug_brs_1_T_10) node _debug_brs_1_T_12 = bits(_debug_brs_1_T_11, 1, 0) node _debug_brs_1_T_13 = add(debug_brs[1], _debug_brs_1_T_12) node _debug_brs_1_T_14 = tail(_debug_brs_1_T_13, 1) connect debug_brs[1], _debug_brs_1_T_14 node _debug_jals_1_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<1>(0h1)) node _debug_jals_1_T_1 = and(rob.io.commit.arch_valids[0], _debug_jals_1_T) node _debug_jals_1_T_2 = and(_debug_jals_1_T_1, rob.io.commit.uops[0].is_jal) node _debug_jals_1_T_3 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<1>(0h1)) node _debug_jals_1_T_4 = and(rob.io.commit.arch_valids[1], _debug_jals_1_T_3) node _debug_jals_1_T_5 = and(_debug_jals_1_T_4, rob.io.commit.uops[1].is_jal) node _debug_jals_1_T_6 = eq(rob.io.commit.uops[2].debug_fsrc, UInt<1>(0h1)) node _debug_jals_1_T_7 = and(rob.io.commit.arch_valids[2], _debug_jals_1_T_6) node _debug_jals_1_T_8 = and(_debug_jals_1_T_7, rob.io.commit.uops[2].is_jal) wire _debug_jals_1_WIRE : UInt<1>[3] connect _debug_jals_1_WIRE[0], _debug_jals_1_T_2 connect _debug_jals_1_WIRE[1], _debug_jals_1_T_5 connect _debug_jals_1_WIRE[2], _debug_jals_1_T_8 node _debug_jals_1_T_9 = add(_debug_jals_1_WIRE[1], _debug_jals_1_WIRE[2]) node _debug_jals_1_T_10 = bits(_debug_jals_1_T_9, 1, 0) node _debug_jals_1_T_11 = add(_debug_jals_1_WIRE[0], _debug_jals_1_T_10) node _debug_jals_1_T_12 = bits(_debug_jals_1_T_11, 1, 0) node _debug_jals_1_T_13 = add(debug_jals[1], _debug_jals_1_T_12) node _debug_jals_1_T_14 = tail(_debug_jals_1_T_13, 1) connect debug_jals[1], _debug_jals_1_T_14 node _debug_jalrs_1_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<1>(0h1)) node _debug_jalrs_1_T_1 = and(rob.io.commit.arch_valids[0], _debug_jalrs_1_T) node _debug_jalrs_1_T_2 = and(_debug_jalrs_1_T_1, rob.io.commit.uops[0].is_jalr) node _debug_jalrs_1_T_3 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<1>(0h1)) node _debug_jalrs_1_T_4 = and(rob.io.commit.arch_valids[1], _debug_jalrs_1_T_3) node _debug_jalrs_1_T_5 = and(_debug_jalrs_1_T_4, rob.io.commit.uops[1].is_jalr) node _debug_jalrs_1_T_6 = eq(rob.io.commit.uops[2].debug_fsrc, UInt<1>(0h1)) node _debug_jalrs_1_T_7 = and(rob.io.commit.arch_valids[2], _debug_jalrs_1_T_6) node _debug_jalrs_1_T_8 = and(_debug_jalrs_1_T_7, rob.io.commit.uops[2].is_jalr) wire _debug_jalrs_1_WIRE : UInt<1>[3] connect _debug_jalrs_1_WIRE[0], _debug_jalrs_1_T_2 connect _debug_jalrs_1_WIRE[1], _debug_jalrs_1_T_5 connect _debug_jalrs_1_WIRE[2], _debug_jalrs_1_T_8 node _debug_jalrs_1_T_9 = add(_debug_jalrs_1_WIRE[1], _debug_jalrs_1_WIRE[2]) node _debug_jalrs_1_T_10 = bits(_debug_jalrs_1_T_9, 1, 0) node _debug_jalrs_1_T_11 = add(_debug_jalrs_1_WIRE[0], _debug_jalrs_1_T_10) node _debug_jalrs_1_T_12 = bits(_debug_jalrs_1_T_11, 1, 0) node _debug_jalrs_1_T_13 = add(debug_jalrs[1], _debug_jalrs_1_T_12) node _debug_jalrs_1_T_14 = tail(_debug_jalrs_1_T_13, 1) connect debug_jalrs[1], _debug_jalrs_1_T_14 node _debug_brs_2_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<2>(0h2)) node _debug_brs_2_T_1 = and(rob.io.commit.arch_valids[0], _debug_brs_2_T) node _debug_brs_2_T_2 = and(_debug_brs_2_T_1, rob.io.commit.uops[0].is_br) node _debug_brs_2_T_3 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<2>(0h2)) node _debug_brs_2_T_4 = and(rob.io.commit.arch_valids[1], _debug_brs_2_T_3) node _debug_brs_2_T_5 = and(_debug_brs_2_T_4, rob.io.commit.uops[1].is_br) node _debug_brs_2_T_6 = eq(rob.io.commit.uops[2].debug_fsrc, UInt<2>(0h2)) node _debug_brs_2_T_7 = and(rob.io.commit.arch_valids[2], _debug_brs_2_T_6) node _debug_brs_2_T_8 = and(_debug_brs_2_T_7, rob.io.commit.uops[2].is_br) wire _debug_brs_2_WIRE : UInt<1>[3] connect _debug_brs_2_WIRE[0], _debug_brs_2_T_2 connect _debug_brs_2_WIRE[1], _debug_brs_2_T_5 connect _debug_brs_2_WIRE[2], _debug_brs_2_T_8 node _debug_brs_2_T_9 = add(_debug_brs_2_WIRE[1], _debug_brs_2_WIRE[2]) node _debug_brs_2_T_10 = bits(_debug_brs_2_T_9, 1, 0) node _debug_brs_2_T_11 = add(_debug_brs_2_WIRE[0], _debug_brs_2_T_10) node _debug_brs_2_T_12 = bits(_debug_brs_2_T_11, 1, 0) node _debug_brs_2_T_13 = add(debug_brs[2], _debug_brs_2_T_12) node _debug_brs_2_T_14 = tail(_debug_brs_2_T_13, 1) connect debug_brs[2], _debug_brs_2_T_14 node _debug_jals_2_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<2>(0h2)) node _debug_jals_2_T_1 = and(rob.io.commit.arch_valids[0], _debug_jals_2_T) node _debug_jals_2_T_2 = and(_debug_jals_2_T_1, rob.io.commit.uops[0].is_jal) node _debug_jals_2_T_3 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<2>(0h2)) node _debug_jals_2_T_4 = and(rob.io.commit.arch_valids[1], _debug_jals_2_T_3) node _debug_jals_2_T_5 = and(_debug_jals_2_T_4, rob.io.commit.uops[1].is_jal) node _debug_jals_2_T_6 = eq(rob.io.commit.uops[2].debug_fsrc, UInt<2>(0h2)) node _debug_jals_2_T_7 = and(rob.io.commit.arch_valids[2], _debug_jals_2_T_6) node _debug_jals_2_T_8 = and(_debug_jals_2_T_7, rob.io.commit.uops[2].is_jal) wire _debug_jals_2_WIRE : UInt<1>[3] connect _debug_jals_2_WIRE[0], _debug_jals_2_T_2 connect _debug_jals_2_WIRE[1], _debug_jals_2_T_5 connect _debug_jals_2_WIRE[2], _debug_jals_2_T_8 node _debug_jals_2_T_9 = add(_debug_jals_2_WIRE[1], _debug_jals_2_WIRE[2]) node _debug_jals_2_T_10 = bits(_debug_jals_2_T_9, 1, 0) node _debug_jals_2_T_11 = add(_debug_jals_2_WIRE[0], _debug_jals_2_T_10) node _debug_jals_2_T_12 = bits(_debug_jals_2_T_11, 1, 0) node _debug_jals_2_T_13 = add(debug_jals[2], _debug_jals_2_T_12) node _debug_jals_2_T_14 = tail(_debug_jals_2_T_13, 1) connect debug_jals[2], _debug_jals_2_T_14 node _debug_jalrs_2_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<2>(0h2)) node _debug_jalrs_2_T_1 = and(rob.io.commit.arch_valids[0], _debug_jalrs_2_T) node _debug_jalrs_2_T_2 = and(_debug_jalrs_2_T_1, rob.io.commit.uops[0].is_jalr) node _debug_jalrs_2_T_3 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<2>(0h2)) node _debug_jalrs_2_T_4 = and(rob.io.commit.arch_valids[1], _debug_jalrs_2_T_3) node _debug_jalrs_2_T_5 = and(_debug_jalrs_2_T_4, rob.io.commit.uops[1].is_jalr) node _debug_jalrs_2_T_6 = eq(rob.io.commit.uops[2].debug_fsrc, UInt<2>(0h2)) node _debug_jalrs_2_T_7 = and(rob.io.commit.arch_valids[2], _debug_jalrs_2_T_6) node _debug_jalrs_2_T_8 = and(_debug_jalrs_2_T_7, rob.io.commit.uops[2].is_jalr) wire _debug_jalrs_2_WIRE : UInt<1>[3] connect _debug_jalrs_2_WIRE[0], _debug_jalrs_2_T_2 connect _debug_jalrs_2_WIRE[1], _debug_jalrs_2_T_5 connect _debug_jalrs_2_WIRE[2], _debug_jalrs_2_T_8 node _debug_jalrs_2_T_9 = add(_debug_jalrs_2_WIRE[1], _debug_jalrs_2_WIRE[2]) node _debug_jalrs_2_T_10 = bits(_debug_jalrs_2_T_9, 1, 0) node _debug_jalrs_2_T_11 = add(_debug_jalrs_2_WIRE[0], _debug_jalrs_2_T_10) node _debug_jalrs_2_T_12 = bits(_debug_jalrs_2_T_11, 1, 0) node _debug_jalrs_2_T_13 = add(debug_jalrs[2], _debug_jalrs_2_T_12) node _debug_jalrs_2_T_14 = tail(_debug_jalrs_2_T_13, 1) connect debug_jalrs[2], _debug_jalrs_2_T_14 node _debug_brs_3_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<2>(0h3)) node _debug_brs_3_T_1 = and(rob.io.commit.arch_valids[0], _debug_brs_3_T) node _debug_brs_3_T_2 = and(_debug_brs_3_T_1, rob.io.commit.uops[0].is_br) node _debug_brs_3_T_3 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<2>(0h3)) node _debug_brs_3_T_4 = and(rob.io.commit.arch_valids[1], _debug_brs_3_T_3) node _debug_brs_3_T_5 = and(_debug_brs_3_T_4, rob.io.commit.uops[1].is_br) node _debug_brs_3_T_6 = eq(rob.io.commit.uops[2].debug_fsrc, UInt<2>(0h3)) node _debug_brs_3_T_7 = and(rob.io.commit.arch_valids[2], _debug_brs_3_T_6) node _debug_brs_3_T_8 = and(_debug_brs_3_T_7, rob.io.commit.uops[2].is_br) wire _debug_brs_3_WIRE : UInt<1>[3] connect _debug_brs_3_WIRE[0], _debug_brs_3_T_2 connect _debug_brs_3_WIRE[1], _debug_brs_3_T_5 connect _debug_brs_3_WIRE[2], _debug_brs_3_T_8 node _debug_brs_3_T_9 = add(_debug_brs_3_WIRE[1], _debug_brs_3_WIRE[2]) node _debug_brs_3_T_10 = bits(_debug_brs_3_T_9, 1, 0) node _debug_brs_3_T_11 = add(_debug_brs_3_WIRE[0], _debug_brs_3_T_10) node _debug_brs_3_T_12 = bits(_debug_brs_3_T_11, 1, 0) node _debug_brs_3_T_13 = add(debug_brs[3], _debug_brs_3_T_12) node _debug_brs_3_T_14 = tail(_debug_brs_3_T_13, 1) connect debug_brs[3], _debug_brs_3_T_14 node _debug_jals_3_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<2>(0h3)) node _debug_jals_3_T_1 = and(rob.io.commit.arch_valids[0], _debug_jals_3_T) node _debug_jals_3_T_2 = and(_debug_jals_3_T_1, rob.io.commit.uops[0].is_jal) node _debug_jals_3_T_3 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<2>(0h3)) node _debug_jals_3_T_4 = and(rob.io.commit.arch_valids[1], _debug_jals_3_T_3) node _debug_jals_3_T_5 = and(_debug_jals_3_T_4, rob.io.commit.uops[1].is_jal) node _debug_jals_3_T_6 = eq(rob.io.commit.uops[2].debug_fsrc, UInt<2>(0h3)) node _debug_jals_3_T_7 = and(rob.io.commit.arch_valids[2], _debug_jals_3_T_6) node _debug_jals_3_T_8 = and(_debug_jals_3_T_7, rob.io.commit.uops[2].is_jal) wire _debug_jals_3_WIRE : UInt<1>[3] connect _debug_jals_3_WIRE[0], _debug_jals_3_T_2 connect _debug_jals_3_WIRE[1], _debug_jals_3_T_5 connect _debug_jals_3_WIRE[2], _debug_jals_3_T_8 node _debug_jals_3_T_9 = add(_debug_jals_3_WIRE[1], _debug_jals_3_WIRE[2]) node _debug_jals_3_T_10 = bits(_debug_jals_3_T_9, 1, 0) node _debug_jals_3_T_11 = add(_debug_jals_3_WIRE[0], _debug_jals_3_T_10) node _debug_jals_3_T_12 = bits(_debug_jals_3_T_11, 1, 0) node _debug_jals_3_T_13 = add(debug_jals[3], _debug_jals_3_T_12) node _debug_jals_3_T_14 = tail(_debug_jals_3_T_13, 1) connect debug_jals[3], _debug_jals_3_T_14 node _debug_jalrs_3_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<2>(0h3)) node _debug_jalrs_3_T_1 = and(rob.io.commit.arch_valids[0], _debug_jalrs_3_T) node _debug_jalrs_3_T_2 = and(_debug_jalrs_3_T_1, rob.io.commit.uops[0].is_jalr) node _debug_jalrs_3_T_3 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<2>(0h3)) node _debug_jalrs_3_T_4 = and(rob.io.commit.arch_valids[1], _debug_jalrs_3_T_3) node _debug_jalrs_3_T_5 = and(_debug_jalrs_3_T_4, rob.io.commit.uops[1].is_jalr) node _debug_jalrs_3_T_6 = eq(rob.io.commit.uops[2].debug_fsrc, UInt<2>(0h3)) node _debug_jalrs_3_T_7 = and(rob.io.commit.arch_valids[2], _debug_jalrs_3_T_6) node _debug_jalrs_3_T_8 = and(_debug_jalrs_3_T_7, rob.io.commit.uops[2].is_jalr) wire _debug_jalrs_3_WIRE : UInt<1>[3] connect _debug_jalrs_3_WIRE[0], _debug_jalrs_3_T_2 connect _debug_jalrs_3_WIRE[1], _debug_jalrs_3_T_5 connect _debug_jalrs_3_WIRE[2], _debug_jalrs_3_T_8 node _debug_jalrs_3_T_9 = add(_debug_jalrs_3_WIRE[1], _debug_jalrs_3_WIRE[2]) node _debug_jalrs_3_T_10 = bits(_debug_jalrs_3_T_9, 1, 0) node _debug_jalrs_3_T_11 = add(_debug_jalrs_3_WIRE[0], _debug_jalrs_3_T_10) node _debug_jalrs_3_T_12 = bits(_debug_jalrs_3_T_11, 1, 0) node _debug_jalrs_3_T_13 = add(debug_jalrs[3], _debug_jalrs_3_T_12) node _debug_jalrs_3_T_14 = tail(_debug_jalrs_3_T_13, 1) connect debug_jalrs[3], _debug_jalrs_3_T_14 node _debug_tsc_reg_T = add(debug_tsc_reg, UInt<1>(0h1)) node _debug_tsc_reg_T_1 = tail(_debug_tsc_reg_T, 1) connect debug_tsc_reg, _debug_tsc_reg_T_1 node debug_irt_reg_hi = cat(rob.io.commit.arch_valids[2], rob.io.commit.arch_valids[1]) node _debug_irt_reg_T = cat(debug_irt_reg_hi, rob.io.commit.arch_valids[0]) node _debug_irt_reg_T_1 = bits(_debug_irt_reg_T, 0, 0) node _debug_irt_reg_T_2 = bits(_debug_irt_reg_T, 1, 1) node _debug_irt_reg_T_3 = bits(_debug_irt_reg_T, 2, 2) node _debug_irt_reg_T_4 = add(_debug_irt_reg_T_2, _debug_irt_reg_T_3) node _debug_irt_reg_T_5 = bits(_debug_irt_reg_T_4, 1, 0) node _debug_irt_reg_T_6 = add(_debug_irt_reg_T_1, _debug_irt_reg_T_5) node _debug_irt_reg_T_7 = bits(_debug_irt_reg_T_6, 1, 0) node _debug_irt_reg_T_8 = add(debug_irt_reg, _debug_irt_reg_T_7) node _debug_irt_reg_T_9 = tail(_debug_irt_reg_T_8, 1) connect debug_irt_reg, _debug_irt_reg_T_9 connect io.ifu.redirect_val, UInt<1>(0h0) connect io.ifu.redirect_flush, UInt<1>(0h0) connect io.ifu.status, csr.io.status connect io.ifu.bp, csr.io.bp connect io.ifu.mcontext, csr.io.mcontext connect io.ifu.scontext, csr.io.scontext node _io_ifu_flush_icache_T = and(rob.io.commit.arch_valids[0], rob.io.commit.uops[0].is_fencei) node _io_ifu_flush_icache_T_1 = and(dec_valids[0], dec_uops[0].is_jalr) node _io_ifu_flush_icache_T_2 = and(_io_ifu_flush_icache_T_1, csr.io.status.debug) reg io_ifu_flush_icache_REG : UInt<1>, clock connect io_ifu_flush_icache_REG, _io_ifu_flush_icache_T_2 node _io_ifu_flush_icache_T_3 = or(_io_ifu_flush_icache_T, io_ifu_flush_icache_REG) node _io_ifu_flush_icache_T_4 = and(rob.io.commit.arch_valids[1], rob.io.commit.uops[1].is_fencei) node _io_ifu_flush_icache_T_5 = and(dec_valids[1], dec_uops[1].is_jalr) node _io_ifu_flush_icache_T_6 = and(_io_ifu_flush_icache_T_5, csr.io.status.debug) reg io_ifu_flush_icache_REG_1 : UInt<1>, clock connect io_ifu_flush_icache_REG_1, _io_ifu_flush_icache_T_6 node _io_ifu_flush_icache_T_7 = or(_io_ifu_flush_icache_T_4, io_ifu_flush_icache_REG_1) node _io_ifu_flush_icache_T_8 = and(rob.io.commit.arch_valids[2], rob.io.commit.uops[2].is_fencei) node _io_ifu_flush_icache_T_9 = and(dec_valids[2], dec_uops[2].is_jalr) node _io_ifu_flush_icache_T_10 = and(_io_ifu_flush_icache_T_9, csr.io.status.debug) reg io_ifu_flush_icache_REG_2 : UInt<1>, clock connect io_ifu_flush_icache_REG_2, _io_ifu_flush_icache_T_10 node _io_ifu_flush_icache_T_11 = or(_io_ifu_flush_icache_T_8, io_ifu_flush_icache_REG_2) node _io_ifu_flush_icache_T_12 = or(_io_ifu_flush_icache_T_3, _io_ifu_flush_icache_T_7) node _io_ifu_flush_icache_T_13 = or(_io_ifu_flush_icache_T_12, _io_ifu_flush_icache_T_11) connect io.ifu.flush_icache, _io_ifu_flush_icache_T_13 reg REG : UInt<1>, clock connect REG, rob.io.flush.valid when REG : connect io.ifu.redirect_val, UInt<1>(0h1) connect io.ifu.redirect_flush, UInt<1>(0h1) reg flush_typ : UInt, clock connect flush_typ, rob.io.flush.bits.flush_typ wire _new_ghist_WIRE : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect _new_ghist_WIRE.ras_idx, UInt<5>(0h0) connect _new_ghist_WIRE.new_saw_branch_taken, UInt<1>(0h0) connect _new_ghist_WIRE.new_saw_branch_not_taken, UInt<1>(0h0) connect _new_ghist_WIRE.current_saw_branch_not_taken, UInt<1>(0h0) connect _new_ghist_WIRE.old_history, UInt<64>(0h0) wire new_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect new_ghist, _new_ghist_WIRE connect new_ghist.current_saw_branch_not_taken, UInt<1>(0h1) connect new_ghist.ras_idx, io.ifu.get_pc[0].entry.ras_idx connect io.ifu.redirect_ghist, new_ghist node _T_16 = bits(flush_typ, 0, 0) when _T_16 : node _io_ifu_redirect_pc_T = eq(flush_typ, UInt<2>(0h3)) reg io_ifu_redirect_pc_REG : UInt, clock connect io_ifu_redirect_pc_REG, csr.io.evec reg io_ifu_redirect_pc_REG_1 : UInt, clock connect io_ifu_redirect_pc_REG_1, io_ifu_redirect_pc_REG node _io_ifu_redirect_pc_T_1 = mux(_io_ifu_redirect_pc_T, io_ifu_redirect_pc_REG_1, csr.io.evec) connect io.ifu.redirect_pc, _io_ifu_redirect_pc_T_1 else : node _flush_pc_T = not(io.ifu.get_pc[0].pc) node _flush_pc_T_1 = or(_flush_pc_T, UInt<6>(0h3f)) node _flush_pc_T_2 = not(_flush_pc_T_1) reg flush_pc_REG : UInt, clock connect flush_pc_REG, rob.io.flush.bits.pc_lob node _flush_pc_T_3 = add(_flush_pc_T_2, flush_pc_REG) node _flush_pc_T_4 = tail(_flush_pc_T_3, 1) reg flush_pc_REG_1 : UInt<1>, clock connect flush_pc_REG_1, rob.io.flush.bits.edge_inst node _flush_pc_T_5 = mux(flush_pc_REG_1, UInt<2>(0h2), UInt<1>(0h0)) node _flush_pc_T_6 = sub(_flush_pc_T_4, _flush_pc_T_5) node flush_pc = tail(_flush_pc_T_6, 1) reg flush_pc_next_REG : UInt<1>, clock connect flush_pc_next_REG, rob.io.flush.bits.is_rvc node _flush_pc_next_T = mux(flush_pc_next_REG, UInt<2>(0h2), UInt<3>(0h4)) node _flush_pc_next_T_1 = add(flush_pc, _flush_pc_next_T) node flush_pc_next = tail(_flush_pc_next_T_1, 1) node _io_ifu_redirect_pc_T_2 = eq(flush_typ, UInt<2>(0h2)) node _io_ifu_redirect_pc_T_3 = mux(_io_ifu_redirect_pc_T_2, flush_pc, flush_pc_next) connect io.ifu.redirect_pc, _io_ifu_redirect_pc_T_3 reg io_ifu_redirect_ftq_idx_REG : UInt, clock connect io_ifu_redirect_ftq_idx_REG, rob.io.flush.bits.ftq_idx connect io.ifu.redirect_ftq_idx, io_ifu_redirect_ftq_idx_REG else : reg REG_1 : UInt<1>, clock connect REG_1, rob.io.flush.valid node _T_17 = eq(REG_1, UInt<1>(0h0)) node _T_18 = and(brupdate.b2.mispredict, _T_17) when _T_18 : node _block_pc_T = not(io.ifu.get_pc[1].pc) node _block_pc_T_1 = or(_block_pc_T, UInt<6>(0h3f)) node block_pc = not(_block_pc_T_1) node uop_maybe_pc = or(block_pc, brupdate.b2.uop.pc_lob) node _npc_T = or(brupdate.b2.uop.is_rvc, brupdate.b2.uop.edge_inst) node _npc_T_1 = mux(_npc_T, UInt<2>(0h2), UInt<3>(0h4)) node _npc_T_2 = add(uop_maybe_pc, _npc_T_1) node npc = tail(_npc_T_2, 1) wire jal_br_target : UInt<40> node _jal_br_target_T = asSInt(uop_maybe_pc) node _jal_br_target_T_1 = add(_jal_br_target_T, brupdate.b2.target_offset) node _jal_br_target_T_2 = tail(_jal_br_target_T_1, 1) node _jal_br_target_T_3 = asSInt(_jal_br_target_T_2) node _jal_br_target_T_4 = mux(brupdate.b2.uop.edge_inst, UInt<39>(0h7fffffffff), UInt<39>(0h0)) node _jal_br_target_T_5 = shl(_jal_br_target_T_4, 1) node _jal_br_target_T_6 = asSInt(_jal_br_target_T_5) node _jal_br_target_T_7 = add(_jal_br_target_T_3, _jal_br_target_T_6) node _jal_br_target_T_8 = tail(_jal_br_target_T_7, 1) node _jal_br_target_T_9 = asSInt(_jal_br_target_T_8) node _jal_br_target_T_10 = asUInt(_jal_br_target_T_9) connect jal_br_target, _jal_br_target_T_10 node _bj_addr_T = eq(brupdate.b2.cfi_type, UInt<3>(0h3)) node bj_addr = mux(_bj_addr_T, brupdate.b2.jalr_target, jal_br_target) node _mispredict_target_T = eq(brupdate.b2.pc_sel, UInt<2>(0h0)) node mispredict_target = mux(_mispredict_target_T, npc, bj_addr) connect io.ifu.redirect_val, UInt<1>(0h1) connect io.ifu.redirect_pc, mispredict_target connect io.ifu.redirect_flush, UInt<1>(0h1) connect io.ifu.redirect_ftq_idx, brupdate.b2.uop.ftq_idx node _use_same_ghist_T = eq(brupdate.b2.cfi_type, UInt<3>(0h1)) node _use_same_ghist_T_1 = eq(brupdate.b2.taken, UInt<1>(0h0)) node _use_same_ghist_T_2 = and(_use_same_ghist_T, _use_same_ghist_T_1) node _use_same_ghist_T_3 = not(block_pc) node _use_same_ghist_T_4 = or(_use_same_ghist_T_3, UInt<3>(0h7)) node _use_same_ghist_T_5 = not(_use_same_ghist_T_4) node _use_same_ghist_T_6 = not(npc) node _use_same_ghist_T_7 = or(_use_same_ghist_T_6, UInt<3>(0h7)) node _use_same_ghist_T_8 = not(_use_same_ghist_T_7) node _use_same_ghist_T_9 = eq(_use_same_ghist_T_5, _use_same_ghist_T_8) node use_same_ghist = and(_use_same_ghist_T_2, _use_same_ghist_T_9) node _cfi_idx_T = eq(io.ifu.get_pc[1].entry.start_bank, UInt<1>(0h1)) node _cfi_idx_T_1 = shl(UInt<1>(0h1), 3) node _cfi_idx_T_2 = mux(_cfi_idx_T, _cfi_idx_T_1, UInt<1>(0h0)) node _cfi_idx_T_3 = xor(brupdate.b2.uop.pc_lob, _cfi_idx_T_2) node cfi_idx = bits(_cfi_idx_T_3, 3, 1) node _next_ghist_T = eq(brupdate.b2.cfi_type, UInt<3>(0h1)) node _next_ghist_T_1 = eq(io.ifu.get_pc[1].entry.cfi_idx.bits, cfi_idx) node _next_ghist_T_2 = and(io.ifu.get_pc[1].entry.cfi_is_call, _next_ghist_T_1) node _next_ghist_T_3 = eq(io.ifu.get_pc[1].entry.cfi_idx.bits, cfi_idx) node _next_ghist_T_4 = and(io.ifu.get_pc[1].entry.cfi_is_ret, _next_ghist_T_3) node next_ghist_cfi_idx_fixed = bits(cfi_idx, 2, 0) node next_ghist_cfi_idx_oh = dshl(UInt<1>(0h1), next_ghist_cfi_idx_fixed) wire next_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} node _next_ghist_not_taken_branches_T = dshr(next_ghist_cfi_idx_oh, UInt<1>(0h0)) node _next_ghist_not_taken_branches_T_1 = dshr(next_ghist_cfi_idx_oh, UInt<1>(0h1)) node _next_ghist_not_taken_branches_T_2 = dshr(next_ghist_cfi_idx_oh, UInt<2>(0h2)) node _next_ghist_not_taken_branches_T_3 = dshr(next_ghist_cfi_idx_oh, UInt<2>(0h3)) node _next_ghist_not_taken_branches_T_4 = dshr(next_ghist_cfi_idx_oh, UInt<3>(0h4)) node _next_ghist_not_taken_branches_T_5 = dshr(next_ghist_cfi_idx_oh, UInt<3>(0h5)) node _next_ghist_not_taken_branches_T_6 = dshr(next_ghist_cfi_idx_oh, UInt<3>(0h6)) node _next_ghist_not_taken_branches_T_7 = dshr(next_ghist_cfi_idx_oh, UInt<3>(0h7)) node _next_ghist_not_taken_branches_T_8 = or(_next_ghist_not_taken_branches_T, _next_ghist_not_taken_branches_T_1) node _next_ghist_not_taken_branches_T_9 = or(_next_ghist_not_taken_branches_T_8, _next_ghist_not_taken_branches_T_2) node _next_ghist_not_taken_branches_T_10 = or(_next_ghist_not_taken_branches_T_9, _next_ghist_not_taken_branches_T_3) node _next_ghist_not_taken_branches_T_11 = or(_next_ghist_not_taken_branches_T_10, _next_ghist_not_taken_branches_T_4) node _next_ghist_not_taken_branches_T_12 = or(_next_ghist_not_taken_branches_T_11, _next_ghist_not_taken_branches_T_5) node _next_ghist_not_taken_branches_T_13 = or(_next_ghist_not_taken_branches_T_12, _next_ghist_not_taken_branches_T_6) node _next_ghist_not_taken_branches_T_14 = or(_next_ghist_not_taken_branches_T_13, _next_ghist_not_taken_branches_T_7) node _next_ghist_not_taken_branches_T_15 = and(_next_ghist_T, brupdate.b2.taken) node _next_ghist_not_taken_branches_T_16 = mux(_next_ghist_not_taken_branches_T_15, next_ghist_cfi_idx_oh, UInt<8>(0h0)) node _next_ghist_not_taken_branches_T_17 = not(_next_ghist_not_taken_branches_T_16) node _next_ghist_not_taken_branches_T_18 = and(_next_ghist_not_taken_branches_T_14, _next_ghist_not_taken_branches_T_17) node _next_ghist_not_taken_branches_T_19 = not(UInt<8>(0h0)) node _next_ghist_not_taken_branches_T_20 = mux(UInt<1>(0h1), _next_ghist_not_taken_branches_T_18, _next_ghist_not_taken_branches_T_19) node next_ghist_not_taken_branches = and(io.ifu.get_pc[1].entry.br_mask, _next_ghist_not_taken_branches_T_20) node _next_ghist_base_T = shl(io.ifu.get_pc[1].ghist.old_history, 1) node _next_ghist_base_T_1 = or(_next_ghist_base_T, UInt<1>(0h1)) node _next_ghist_base_T_2 = shl(io.ifu.get_pc[1].ghist.old_history, 1) node _next_ghist_base_T_3 = mux(io.ifu.get_pc[1].ghist.new_saw_branch_not_taken, _next_ghist_base_T_2, io.ifu.get_pc[1].ghist.old_history) node next_ghist_base = mux(io.ifu.get_pc[1].ghist.new_saw_branch_taken, _next_ghist_base_T_1, _next_ghist_base_T_3) node _next_ghist_cfi_in_bank_0_T = and(UInt<1>(0h1), brupdate.b2.taken) node _next_ghist_cfi_in_bank_0_T_1 = lt(next_ghist_cfi_idx_fixed, UInt<3>(0h4)) node next_ghist_cfi_in_bank_0 = and(_next_ghist_cfi_in_bank_0_T, _next_ghist_cfi_in_bank_0_T_1) node _next_ghist_ignore_second_bank_T = bits(io.ifu.get_pc[1].pc, 5, 3) node _next_ghist_ignore_second_bank_T_1 = eq(_next_ghist_ignore_second_bank_T, UInt<3>(0h7)) node _next_ghist_ignore_second_bank_T_2 = and(UInt<1>(0h1), _next_ghist_ignore_second_bank_T_1) node next_ghist_ignore_second_bank = or(next_ghist_cfi_in_bank_0, _next_ghist_ignore_second_bank_T_2) node _next_ghist_first_bank_saw_not_taken_T = bits(next_ghist_not_taken_branches, 3, 0) node _next_ghist_first_bank_saw_not_taken_T_1 = neq(_next_ghist_first_bank_saw_not_taken_T, UInt<1>(0h0)) node next_ghist_first_bank_saw_not_taken = or(_next_ghist_first_bank_saw_not_taken_T_1, io.ifu.get_pc[1].ghist.current_saw_branch_not_taken) connect next_ghist.current_saw_branch_not_taken, UInt<1>(0h0) when next_ghist_ignore_second_bank : node _next_ghist_new_history_old_history_T = shl(io.ifu.get_pc[1].ghist.old_history, 1) node _next_ghist_new_history_old_history_T_1 = or(_next_ghist_new_history_old_history_T, UInt<1>(0h1)) node _next_ghist_new_history_old_history_T_2 = shl(io.ifu.get_pc[1].ghist.old_history, 1) node _next_ghist_new_history_old_history_T_3 = mux(io.ifu.get_pc[1].ghist.new_saw_branch_not_taken, _next_ghist_new_history_old_history_T_2, io.ifu.get_pc[1].ghist.old_history) node _next_ghist_new_history_old_history_T_4 = mux(io.ifu.get_pc[1].ghist.new_saw_branch_taken, _next_ghist_new_history_old_history_T_1, _next_ghist_new_history_old_history_T_3) connect next_ghist.old_history, _next_ghist_new_history_old_history_T_4 connect next_ghist.new_saw_branch_not_taken, next_ghist_first_bank_saw_not_taken node _next_ghist_new_history_new_saw_branch_taken_T = and(_next_ghist_T, next_ghist_cfi_in_bank_0) connect next_ghist.new_saw_branch_taken, _next_ghist_new_history_new_saw_branch_taken_T else : node _next_ghist_new_history_old_history_T_5 = and(_next_ghist_T, next_ghist_cfi_in_bank_0) node _next_ghist_new_history_old_history_T_6 = shl(io.ifu.get_pc[1].ghist.old_history, 1) node _next_ghist_new_history_old_history_T_7 = or(_next_ghist_new_history_old_history_T_6, UInt<1>(0h1)) node _next_ghist_new_history_old_history_T_8 = shl(io.ifu.get_pc[1].ghist.old_history, 1) node _next_ghist_new_history_old_history_T_9 = mux(io.ifu.get_pc[1].ghist.new_saw_branch_not_taken, _next_ghist_new_history_old_history_T_8, io.ifu.get_pc[1].ghist.old_history) node _next_ghist_new_history_old_history_T_10 = mux(io.ifu.get_pc[1].ghist.new_saw_branch_taken, _next_ghist_new_history_old_history_T_7, _next_ghist_new_history_old_history_T_9) node _next_ghist_new_history_old_history_T_11 = shl(_next_ghist_new_history_old_history_T_10, 1) node _next_ghist_new_history_old_history_T_12 = or(_next_ghist_new_history_old_history_T_11, UInt<1>(0h1)) node _next_ghist_new_history_old_history_T_13 = shl(io.ifu.get_pc[1].ghist.old_history, 1) node _next_ghist_new_history_old_history_T_14 = or(_next_ghist_new_history_old_history_T_13, UInt<1>(0h1)) node _next_ghist_new_history_old_history_T_15 = shl(io.ifu.get_pc[1].ghist.old_history, 1) node _next_ghist_new_history_old_history_T_16 = mux(io.ifu.get_pc[1].ghist.new_saw_branch_not_taken, _next_ghist_new_history_old_history_T_15, io.ifu.get_pc[1].ghist.old_history) node _next_ghist_new_history_old_history_T_17 = mux(io.ifu.get_pc[1].ghist.new_saw_branch_taken, _next_ghist_new_history_old_history_T_14, _next_ghist_new_history_old_history_T_16) node _next_ghist_new_history_old_history_T_18 = shl(_next_ghist_new_history_old_history_T_17, 1) node _next_ghist_new_history_old_history_T_19 = shl(io.ifu.get_pc[1].ghist.old_history, 1) node _next_ghist_new_history_old_history_T_20 = or(_next_ghist_new_history_old_history_T_19, UInt<1>(0h1)) node _next_ghist_new_history_old_history_T_21 = shl(io.ifu.get_pc[1].ghist.old_history, 1) node _next_ghist_new_history_old_history_T_22 = mux(io.ifu.get_pc[1].ghist.new_saw_branch_not_taken, _next_ghist_new_history_old_history_T_21, io.ifu.get_pc[1].ghist.old_history) node _next_ghist_new_history_old_history_T_23 = mux(io.ifu.get_pc[1].ghist.new_saw_branch_taken, _next_ghist_new_history_old_history_T_20, _next_ghist_new_history_old_history_T_22) node _next_ghist_new_history_old_history_T_24 = mux(next_ghist_first_bank_saw_not_taken, _next_ghist_new_history_old_history_T_18, _next_ghist_new_history_old_history_T_23) node _next_ghist_new_history_old_history_T_25 = mux(_next_ghist_new_history_old_history_T_5, _next_ghist_new_history_old_history_T_12, _next_ghist_new_history_old_history_T_24) connect next_ghist.old_history, _next_ghist_new_history_old_history_T_25 node _next_ghist_new_history_new_saw_branch_not_taken_T = bits(next_ghist_not_taken_branches, 7, 4) node _next_ghist_new_history_new_saw_branch_not_taken_T_1 = neq(_next_ghist_new_history_new_saw_branch_not_taken_T, UInt<1>(0h0)) connect next_ghist.new_saw_branch_not_taken, _next_ghist_new_history_new_saw_branch_not_taken_T_1 node _next_ghist_new_history_new_saw_branch_taken_T_1 = and(UInt<1>(0h1), brupdate.b2.taken) node _next_ghist_new_history_new_saw_branch_taken_T_2 = and(_next_ghist_new_history_new_saw_branch_taken_T_1, _next_ghist_T) node _next_ghist_new_history_new_saw_branch_taken_T_3 = eq(next_ghist_cfi_in_bank_0, UInt<1>(0h0)) node _next_ghist_new_history_new_saw_branch_taken_T_4 = and(_next_ghist_new_history_new_saw_branch_taken_T_2, _next_ghist_new_history_new_saw_branch_taken_T_3) connect next_ghist.new_saw_branch_taken, _next_ghist_new_history_new_saw_branch_taken_T_4 node _next_ghist_new_history_ras_idx_T = and(UInt<1>(0h1), _next_ghist_T_2) node _next_ghist_new_history_ras_idx_T_1 = add(io.ifu.get_pc[1].ghist.ras_idx, UInt<1>(0h1)) node _next_ghist_new_history_ras_idx_T_2 = tail(_next_ghist_new_history_ras_idx_T_1, 1) node _next_ghist_new_history_ras_idx_T_3 = bits(_next_ghist_new_history_ras_idx_T_2, 4, 0) node _next_ghist_new_history_ras_idx_T_4 = and(UInt<1>(0h1), _next_ghist_T_4) node _next_ghist_new_history_ras_idx_T_5 = sub(io.ifu.get_pc[1].ghist.ras_idx, UInt<1>(0h1)) node _next_ghist_new_history_ras_idx_T_6 = tail(_next_ghist_new_history_ras_idx_T_5, 1) node _next_ghist_new_history_ras_idx_T_7 = bits(_next_ghist_new_history_ras_idx_T_6, 4, 0) node _next_ghist_new_history_ras_idx_T_8 = mux(_next_ghist_new_history_ras_idx_T_4, _next_ghist_new_history_ras_idx_T_7, io.ifu.get_pc[1].ghist.ras_idx) node _next_ghist_new_history_ras_idx_T_9 = mux(_next_ghist_new_history_ras_idx_T, _next_ghist_new_history_ras_idx_T_3, _next_ghist_new_history_ras_idx_T_8) connect next_ghist.ras_idx, _next_ghist_new_history_ras_idx_T_9 node _io_ifu_redirect_ghist_T = mux(use_same_ghist, io.ifu.get_pc[1].ghist, next_ghist) connect io.ifu.redirect_ghist, _io_ifu_redirect_ghist_T connect io.ifu.redirect_ghist.current_saw_branch_not_taken, use_same_ghist else : node _T_19 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _T_20 = or(rob.io.flush_frontend, _T_19) when _T_20 : connect io.ifu.redirect_flush, UInt<1>(0h1) node _youngest_com_idx_T = mux(rob.io.commit.valids[1], UInt<1>(0h1), UInt<2>(0h2)) node _youngest_com_idx_T_1 = mux(rob.io.commit.valids[2], UInt<1>(0h0), _youngest_com_idx_T) node _youngest_com_idx_T_2 = sub(UInt<2>(0h2), _youngest_com_idx_T_1) node youngest_com_idx = tail(_youngest_com_idx_T_2, 1) node _io_ifu_commit_valid_T = or(rob.io.commit.valids[0], rob.io.commit.valids[1]) node _io_ifu_commit_valid_T_1 = or(_io_ifu_commit_valid_T, rob.io.commit.valids[2]) node _io_ifu_commit_valid_T_2 = or(_io_ifu_commit_valid_T_1, rob.io.com_xcpt.valid) connect io.ifu.commit.valid, _io_ifu_commit_valid_T_2 node _io_ifu_commit_bits_T = mux(rob.io.com_xcpt.valid, rob.io.com_xcpt.bits.ftq_idx, rob.io.commit.uops[youngest_com_idx].ftq_idx) connect io.ifu.commit.bits, _io_ifu_commit_bits_T node _T_21 = or(rob.io.commit.valids[0], rob.io.commit.valids[1]) node _T_22 = or(_T_21, rob.io.commit.valids[2]) node _T_23 = and(_T_22, rob.io.com_xcpt.valid) node _T_24 = eq(_T_23, UInt<1>(0h0)) node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : node _T_27 = eq(_T_24, UInt<1>(0h0)) when _T_27 : printf(clock, UInt<1>(0h1), "Assertion failed: ROB can't commit and except in same cycle!\n at core.scala:471 assert(!(rob.io.commit.valids.reduce(_\|_) && rob.io.com_xcpt.valid),\n") : printf_1 assert(clock, _T_24, UInt<1>(0h1), "") : assert_1 reg REG_2 : UInt<1>, clock connect REG_2, io.lsu.exe[0].req.bits.sfence.valid when REG_2 : reg io_ifu_sfence_REG : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, clock connect io_ifu_sfence_REG.bits.hg, io.lsu.exe[0].req.bits.sfence.bits.hg connect io_ifu_sfence_REG.bits.hv, io.lsu.exe[0].req.bits.sfence.bits.hv connect io_ifu_sfence_REG.bits.asid, io.lsu.exe[0].req.bits.sfence.bits.asid connect io_ifu_sfence_REG.bits.addr, io.lsu.exe[0].req.bits.sfence.bits.addr connect io_ifu_sfence_REG.bits.rs2, io.lsu.exe[0].req.bits.sfence.bits.rs2 connect io_ifu_sfence_REG.bits.rs1, io.lsu.exe[0].req.bits.sfence.bits.rs1 connect io_ifu_sfence_REG.valid, io.lsu.exe[0].req.bits.sfence.valid connect io.ifu.sfence, io_ifu_sfence_REG regreset dec_finished_mask : UInt<3>, clock, reset, UInt<3>(0h0) connect io.ifu.fetchpacket.ready, dec_ready node _dec_valids_0_T = and(io.ifu.fetchpacket.valid, io.ifu.fetchpacket.bits.uops[0].valid) node _dec_valids_0_T_1 = bits(dec_finished_mask, 0, 0) node _dec_valids_0_T_2 = eq(_dec_valids_0_T_1, UInt<1>(0h0)) node _dec_valids_0_T_3 = and(_dec_valids_0_T, _dec_valids_0_T_2) connect dec_valids[0], _dec_valids_0_T_3 connect decode_units_0.io.enq.uop.debug_tsrc, io.ifu.fetchpacket.bits.uops[0].bits.debug_tsrc connect decode_units_0.io.enq.uop.debug_fsrc, io.ifu.fetchpacket.bits.uops[0].bits.debug_fsrc connect decode_units_0.io.enq.uop.bp_xcpt_if, io.ifu.fetchpacket.bits.uops[0].bits.bp_xcpt_if connect decode_units_0.io.enq.uop.bp_debug_if, io.ifu.fetchpacket.bits.uops[0].bits.bp_debug_if connect decode_units_0.io.enq.uop.xcpt_ma_if, io.ifu.fetchpacket.bits.uops[0].bits.xcpt_ma_if connect decode_units_0.io.enq.uop.xcpt_ae_if, io.ifu.fetchpacket.bits.uops[0].bits.xcpt_ae_if connect decode_units_0.io.enq.uop.xcpt_pf_if, io.ifu.fetchpacket.bits.uops[0].bits.xcpt_pf_if connect decode_units_0.io.enq.uop.fp_single, io.ifu.fetchpacket.bits.uops[0].bits.fp_single connect decode_units_0.io.enq.uop.fp_val, io.ifu.fetchpacket.bits.uops[0].bits.fp_val connect decode_units_0.io.enq.uop.frs3_en, io.ifu.fetchpacket.bits.uops[0].bits.frs3_en connect decode_units_0.io.enq.uop.lrs2_rtype, io.ifu.fetchpacket.bits.uops[0].bits.lrs2_rtype connect decode_units_0.io.enq.uop.lrs1_rtype, io.ifu.fetchpacket.bits.uops[0].bits.lrs1_rtype connect decode_units_0.io.enq.uop.dst_rtype, io.ifu.fetchpacket.bits.uops[0].bits.dst_rtype connect decode_units_0.io.enq.uop.ldst_val, io.ifu.fetchpacket.bits.uops[0].bits.ldst_val connect decode_units_0.io.enq.uop.lrs3, io.ifu.fetchpacket.bits.uops[0].bits.lrs3 connect decode_units_0.io.enq.uop.lrs2, io.ifu.fetchpacket.bits.uops[0].bits.lrs2 connect decode_units_0.io.enq.uop.lrs1, io.ifu.fetchpacket.bits.uops[0].bits.lrs1 connect decode_units_0.io.enq.uop.ldst, io.ifu.fetchpacket.bits.uops[0].bits.ldst connect decode_units_0.io.enq.uop.ldst_is_rs1, io.ifu.fetchpacket.bits.uops[0].bits.ldst_is_rs1 connect decode_units_0.io.enq.uop.flush_on_commit, io.ifu.fetchpacket.bits.uops[0].bits.flush_on_commit connect decode_units_0.io.enq.uop.is_unique, io.ifu.fetchpacket.bits.uops[0].bits.is_unique connect decode_units_0.io.enq.uop.is_sys_pc2epc, io.ifu.fetchpacket.bits.uops[0].bits.is_sys_pc2epc connect decode_units_0.io.enq.uop.uses_stq, io.ifu.fetchpacket.bits.uops[0].bits.uses_stq connect decode_units_0.io.enq.uop.uses_ldq, io.ifu.fetchpacket.bits.uops[0].bits.uses_ldq connect decode_units_0.io.enq.uop.is_amo, io.ifu.fetchpacket.bits.uops[0].bits.is_amo connect decode_units_0.io.enq.uop.is_fencei, io.ifu.fetchpacket.bits.uops[0].bits.is_fencei connect decode_units_0.io.enq.uop.is_fence, io.ifu.fetchpacket.bits.uops[0].bits.is_fence connect decode_units_0.io.enq.uop.mem_signed, io.ifu.fetchpacket.bits.uops[0].bits.mem_signed connect decode_units_0.io.enq.uop.mem_size, io.ifu.fetchpacket.bits.uops[0].bits.mem_size connect decode_units_0.io.enq.uop.mem_cmd, io.ifu.fetchpacket.bits.uops[0].bits.mem_cmd connect decode_units_0.io.enq.uop.bypassable, io.ifu.fetchpacket.bits.uops[0].bits.bypassable connect decode_units_0.io.enq.uop.exc_cause, io.ifu.fetchpacket.bits.uops[0].bits.exc_cause connect decode_units_0.io.enq.uop.exception, io.ifu.fetchpacket.bits.uops[0].bits.exception connect decode_units_0.io.enq.uop.stale_pdst, io.ifu.fetchpacket.bits.uops[0].bits.stale_pdst connect decode_units_0.io.enq.uop.ppred_busy, io.ifu.fetchpacket.bits.uops[0].bits.ppred_busy connect decode_units_0.io.enq.uop.prs3_busy, io.ifu.fetchpacket.bits.uops[0].bits.prs3_busy connect decode_units_0.io.enq.uop.prs2_busy, io.ifu.fetchpacket.bits.uops[0].bits.prs2_busy connect decode_units_0.io.enq.uop.prs1_busy, io.ifu.fetchpacket.bits.uops[0].bits.prs1_busy connect decode_units_0.io.enq.uop.ppred, io.ifu.fetchpacket.bits.uops[0].bits.ppred connect decode_units_0.io.enq.uop.prs3, io.ifu.fetchpacket.bits.uops[0].bits.prs3 connect decode_units_0.io.enq.uop.prs2, io.ifu.fetchpacket.bits.uops[0].bits.prs2 connect decode_units_0.io.enq.uop.prs1, io.ifu.fetchpacket.bits.uops[0].bits.prs1 connect decode_units_0.io.enq.uop.pdst, io.ifu.fetchpacket.bits.uops[0].bits.pdst connect decode_units_0.io.enq.uop.rxq_idx, io.ifu.fetchpacket.bits.uops[0].bits.rxq_idx connect decode_units_0.io.enq.uop.stq_idx, io.ifu.fetchpacket.bits.uops[0].bits.stq_idx connect decode_units_0.io.enq.uop.ldq_idx, io.ifu.fetchpacket.bits.uops[0].bits.ldq_idx connect decode_units_0.io.enq.uop.rob_idx, io.ifu.fetchpacket.bits.uops[0].bits.rob_idx connect decode_units_0.io.enq.uop.csr_addr, io.ifu.fetchpacket.bits.uops[0].bits.csr_addr connect decode_units_0.io.enq.uop.imm_packed, io.ifu.fetchpacket.bits.uops[0].bits.imm_packed connect decode_units_0.io.enq.uop.taken, io.ifu.fetchpacket.bits.uops[0].bits.taken connect decode_units_0.io.enq.uop.pc_lob, io.ifu.fetchpacket.bits.uops[0].bits.pc_lob connect decode_units_0.io.enq.uop.edge_inst, io.ifu.fetchpacket.bits.uops[0].bits.edge_inst connect decode_units_0.io.enq.uop.ftq_idx, io.ifu.fetchpacket.bits.uops[0].bits.ftq_idx connect decode_units_0.io.enq.uop.br_tag, io.ifu.fetchpacket.bits.uops[0].bits.br_tag connect decode_units_0.io.enq.uop.br_mask, io.ifu.fetchpacket.bits.uops[0].bits.br_mask connect decode_units_0.io.enq.uop.is_sfb, io.ifu.fetchpacket.bits.uops[0].bits.is_sfb connect decode_units_0.io.enq.uop.is_jal, io.ifu.fetchpacket.bits.uops[0].bits.is_jal connect decode_units_0.io.enq.uop.is_jalr, io.ifu.fetchpacket.bits.uops[0].bits.is_jalr connect decode_units_0.io.enq.uop.is_br, io.ifu.fetchpacket.bits.uops[0].bits.is_br connect decode_units_0.io.enq.uop.iw_p2_poisoned, io.ifu.fetchpacket.bits.uops[0].bits.iw_p2_poisoned connect decode_units_0.io.enq.uop.iw_p1_poisoned, io.ifu.fetchpacket.bits.uops[0].bits.iw_p1_poisoned connect decode_units_0.io.enq.uop.iw_state, io.ifu.fetchpacket.bits.uops[0].bits.iw_state connect decode_units_0.io.enq.uop.ctrl.is_std, io.ifu.fetchpacket.bits.uops[0].bits.ctrl.is_std connect decode_units_0.io.enq.uop.ctrl.is_sta, io.ifu.fetchpacket.bits.uops[0].bits.ctrl.is_sta connect decode_units_0.io.enq.uop.ctrl.is_load, io.ifu.fetchpacket.bits.uops[0].bits.ctrl.is_load connect decode_units_0.io.enq.uop.ctrl.csr_cmd, io.ifu.fetchpacket.bits.uops[0].bits.ctrl.csr_cmd connect decode_units_0.io.enq.uop.ctrl.fcn_dw, io.ifu.fetchpacket.bits.uops[0].bits.ctrl.fcn_dw connect decode_units_0.io.enq.uop.ctrl.op_fcn, io.ifu.fetchpacket.bits.uops[0].bits.ctrl.op_fcn connect decode_units_0.io.enq.uop.ctrl.imm_sel, io.ifu.fetchpacket.bits.uops[0].bits.ctrl.imm_sel connect decode_units_0.io.enq.uop.ctrl.op2_sel, io.ifu.fetchpacket.bits.uops[0].bits.ctrl.op2_sel connect decode_units_0.io.enq.uop.ctrl.op1_sel, io.ifu.fetchpacket.bits.uops[0].bits.ctrl.op1_sel connect decode_units_0.io.enq.uop.ctrl.br_type, io.ifu.fetchpacket.bits.uops[0].bits.ctrl.br_type connect decode_units_0.io.enq.uop.fu_code, io.ifu.fetchpacket.bits.uops[0].bits.fu_code connect decode_units_0.io.enq.uop.iq_type, io.ifu.fetchpacket.bits.uops[0].bits.iq_type connect decode_units_0.io.enq.uop.debug_pc, io.ifu.fetchpacket.bits.uops[0].bits.debug_pc connect decode_units_0.io.enq.uop.is_rvc, io.ifu.fetchpacket.bits.uops[0].bits.is_rvc connect decode_units_0.io.enq.uop.debug_inst, io.ifu.fetchpacket.bits.uops[0].bits.debug_inst connect decode_units_0.io.enq.uop.inst, io.ifu.fetchpacket.bits.uops[0].bits.inst connect decode_units_0.io.enq.uop.uopc, io.ifu.fetchpacket.bits.uops[0].bits.uopc connect decode_units_0.io.status.uie, csr.io.status.uie connect decode_units_0.io.status.sie, csr.io.status.sie connect decode_units_0.io.status.hie, csr.io.status.hie connect decode_units_0.io.status.mie, csr.io.status.mie connect decode_units_0.io.status.upie, csr.io.status.upie connect decode_units_0.io.status.spie, csr.io.status.spie connect decode_units_0.io.status.ube, csr.io.status.ube connect decode_units_0.io.status.mpie, csr.io.status.mpie connect decode_units_0.io.status.spp, csr.io.status.spp connect decode_units_0.io.status.vs, csr.io.status.vs connect decode_units_0.io.status.mpp, csr.io.status.mpp connect decode_units_0.io.status.fs, csr.io.status.fs connect decode_units_0.io.status.xs, csr.io.status.xs connect decode_units_0.io.status.mprv, csr.io.status.mprv connect decode_units_0.io.status.sum, csr.io.status.sum connect decode_units_0.io.status.mxr, csr.io.status.mxr connect decode_units_0.io.status.tvm, csr.io.status.tvm connect decode_units_0.io.status.tw, csr.io.status.tw connect decode_units_0.io.status.tsr, csr.io.status.tsr connect decode_units_0.io.status.zero1, csr.io.status.zero1 connect decode_units_0.io.status.sd_rv32, csr.io.status.sd_rv32 connect decode_units_0.io.status.uxl, csr.io.status.uxl connect decode_units_0.io.status.sxl, csr.io.status.sxl connect decode_units_0.io.status.sbe, csr.io.status.sbe connect decode_units_0.io.status.mbe, csr.io.status.mbe connect decode_units_0.io.status.gva, csr.io.status.gva connect decode_units_0.io.status.mpv, csr.io.status.mpv connect decode_units_0.io.status.zero2, csr.io.status.zero2 connect decode_units_0.io.status.sd, csr.io.status.sd connect decode_units_0.io.status.v, csr.io.status.v connect decode_units_0.io.status.prv, csr.io.status.prv connect decode_units_0.io.status.dv, csr.io.status.dv connect decode_units_0.io.status.dprv, csr.io.status.dprv connect decode_units_0.io.status.isa, csr.io.status.isa connect decode_units_0.io.status.wfi, csr.io.status.wfi connect decode_units_0.io.status.cease, csr.io.status.cease connect decode_units_0.io.status.debug, csr.io.status.debug connect decode_units_0.io.csr_decode, csr.io.decode[0] connect decode_units_0.io.interrupt, csr.io.interrupt connect decode_units_0.io.interrupt_cause, csr.io.interrupt_cause connect dec_uops[0], decode_units_0.io.deq.uop node _dec_valids_1_T = and(io.ifu.fetchpacket.valid, io.ifu.fetchpacket.bits.uops[1].valid) node _dec_valids_1_T_1 = bits(dec_finished_mask, 1, 1) node _dec_valids_1_T_2 = eq(_dec_valids_1_T_1, UInt<1>(0h0)) node _dec_valids_1_T_3 = and(_dec_valids_1_T, _dec_valids_1_T_2) connect dec_valids[1], _dec_valids_1_T_3 connect decode_units_1.io.enq.uop.debug_tsrc, io.ifu.fetchpacket.bits.uops[1].bits.debug_tsrc connect decode_units_1.io.enq.uop.debug_fsrc, io.ifu.fetchpacket.bits.uops[1].bits.debug_fsrc connect decode_units_1.io.enq.uop.bp_xcpt_if, io.ifu.fetchpacket.bits.uops[1].bits.bp_xcpt_if connect decode_units_1.io.enq.uop.bp_debug_if, io.ifu.fetchpacket.bits.uops[1].bits.bp_debug_if connect decode_units_1.io.enq.uop.xcpt_ma_if, io.ifu.fetchpacket.bits.uops[1].bits.xcpt_ma_if connect decode_units_1.io.enq.uop.xcpt_ae_if, io.ifu.fetchpacket.bits.uops[1].bits.xcpt_ae_if connect decode_units_1.io.enq.uop.xcpt_pf_if, io.ifu.fetchpacket.bits.uops[1].bits.xcpt_pf_if connect decode_units_1.io.enq.uop.fp_single, io.ifu.fetchpacket.bits.uops[1].bits.fp_single connect decode_units_1.io.enq.uop.fp_val, io.ifu.fetchpacket.bits.uops[1].bits.fp_val connect decode_units_1.io.enq.uop.frs3_en, io.ifu.fetchpacket.bits.uops[1].bits.frs3_en connect decode_units_1.io.enq.uop.lrs2_rtype, io.ifu.fetchpacket.bits.uops[1].bits.lrs2_rtype connect decode_units_1.io.enq.uop.lrs1_rtype, io.ifu.fetchpacket.bits.uops[1].bits.lrs1_rtype connect decode_units_1.io.enq.uop.dst_rtype, io.ifu.fetchpacket.bits.uops[1].bits.dst_rtype connect decode_units_1.io.enq.uop.ldst_val, io.ifu.fetchpacket.bits.uops[1].bits.ldst_val connect decode_units_1.io.enq.uop.lrs3, io.ifu.fetchpacket.bits.uops[1].bits.lrs3 connect decode_units_1.io.enq.uop.lrs2, io.ifu.fetchpacket.bits.uops[1].bits.lrs2 connect decode_units_1.io.enq.uop.lrs1, io.ifu.fetchpacket.bits.uops[1].bits.lrs1 connect decode_units_1.io.enq.uop.ldst, io.ifu.fetchpacket.bits.uops[1].bits.ldst connect decode_units_1.io.enq.uop.ldst_is_rs1, io.ifu.fetchpacket.bits.uops[1].bits.ldst_is_rs1 connect decode_units_1.io.enq.uop.flush_on_commit, io.ifu.fetchpacket.bits.uops[1].bits.flush_on_commit connect decode_units_1.io.enq.uop.is_unique, io.ifu.fetchpacket.bits.uops[1].bits.is_unique connect decode_units_1.io.enq.uop.is_sys_pc2epc, io.ifu.fetchpacket.bits.uops[1].bits.is_sys_pc2epc connect decode_units_1.io.enq.uop.uses_stq, io.ifu.fetchpacket.bits.uops[1].bits.uses_stq connect decode_units_1.io.enq.uop.uses_ldq, io.ifu.fetchpacket.bits.uops[1].bits.uses_ldq connect decode_units_1.io.enq.uop.is_amo, io.ifu.fetchpacket.bits.uops[1].bits.is_amo connect decode_units_1.io.enq.uop.is_fencei, io.ifu.fetchpacket.bits.uops[1].bits.is_fencei connect decode_units_1.io.enq.uop.is_fence, io.ifu.fetchpacket.bits.uops[1].bits.is_fence connect decode_units_1.io.enq.uop.mem_signed, io.ifu.fetchpacket.bits.uops[1].bits.mem_signed connect decode_units_1.io.enq.uop.mem_size, io.ifu.fetchpacket.bits.uops[1].bits.mem_size connect decode_units_1.io.enq.uop.mem_cmd, io.ifu.fetchpacket.bits.uops[1].bits.mem_cmd connect decode_units_1.io.enq.uop.bypassable, io.ifu.fetchpacket.bits.uops[1].bits.bypassable connect decode_units_1.io.enq.uop.exc_cause, io.ifu.fetchpacket.bits.uops[1].bits.exc_cause connect decode_units_1.io.enq.uop.exception, io.ifu.fetchpacket.bits.uops[1].bits.exception connect decode_units_1.io.enq.uop.stale_pdst, io.ifu.fetchpacket.bits.uops[1].bits.stale_pdst connect decode_units_1.io.enq.uop.ppred_busy, io.ifu.fetchpacket.bits.uops[1].bits.ppred_busy connect decode_units_1.io.enq.uop.prs3_busy, io.ifu.fetchpacket.bits.uops[1].bits.prs3_busy connect decode_units_1.io.enq.uop.prs2_busy, io.ifu.fetchpacket.bits.uops[1].bits.prs2_busy connect decode_units_1.io.enq.uop.prs1_busy, io.ifu.fetchpacket.bits.uops[1].bits.prs1_busy connect decode_units_1.io.enq.uop.ppred, io.ifu.fetchpacket.bits.uops[1].bits.ppred connect decode_units_1.io.enq.uop.prs3, io.ifu.fetchpacket.bits.uops[1].bits.prs3 connect decode_units_1.io.enq.uop.prs2, io.ifu.fetchpacket.bits.uops[1].bits.prs2 connect decode_units_1.io.enq.uop.prs1, io.ifu.fetchpacket.bits.uops[1].bits.prs1 connect decode_units_1.io.enq.uop.pdst, io.ifu.fetchpacket.bits.uops[1].bits.pdst connect decode_units_1.io.enq.uop.rxq_idx, io.ifu.fetchpacket.bits.uops[1].bits.rxq_idx connect decode_units_1.io.enq.uop.stq_idx, io.ifu.fetchpacket.bits.uops[1].bits.stq_idx connect decode_units_1.io.enq.uop.ldq_idx, io.ifu.fetchpacket.bits.uops[1].bits.ldq_idx connect decode_units_1.io.enq.uop.rob_idx, io.ifu.fetchpacket.bits.uops[1].bits.rob_idx connect decode_units_1.io.enq.uop.csr_addr, io.ifu.fetchpacket.bits.uops[1].bits.csr_addr connect decode_units_1.io.enq.uop.imm_packed, io.ifu.fetchpacket.bits.uops[1].bits.imm_packed connect decode_units_1.io.enq.uop.taken, io.ifu.fetchpacket.bits.uops[1].bits.taken connect decode_units_1.io.enq.uop.pc_lob, io.ifu.fetchpacket.bits.uops[1].bits.pc_lob connect decode_units_1.io.enq.uop.edge_inst, io.ifu.fetchpacket.bits.uops[1].bits.edge_inst connect decode_units_1.io.enq.uop.ftq_idx, io.ifu.fetchpacket.bits.uops[1].bits.ftq_idx connect decode_units_1.io.enq.uop.br_tag, io.ifu.fetchpacket.bits.uops[1].bits.br_tag connect decode_units_1.io.enq.uop.br_mask, io.ifu.fetchpacket.bits.uops[1].bits.br_mask connect decode_units_1.io.enq.uop.is_sfb, io.ifu.fetchpacket.bits.uops[1].bits.is_sfb connect decode_units_1.io.enq.uop.is_jal, io.ifu.fetchpacket.bits.uops[1].bits.is_jal connect decode_units_1.io.enq.uop.is_jalr, io.ifu.fetchpacket.bits.uops[1].bits.is_jalr connect decode_units_1.io.enq.uop.is_br, io.ifu.fetchpacket.bits.uops[1].bits.is_br connect decode_units_1.io.enq.uop.iw_p2_poisoned, io.ifu.fetchpacket.bits.uops[1].bits.iw_p2_poisoned connect decode_units_1.io.enq.uop.iw_p1_poisoned, io.ifu.fetchpacket.bits.uops[1].bits.iw_p1_poisoned connect decode_units_1.io.enq.uop.iw_state, io.ifu.fetchpacket.bits.uops[1].bits.iw_state connect decode_units_1.io.enq.uop.ctrl.is_std, io.ifu.fetchpacket.bits.uops[1].bits.ctrl.is_std connect decode_units_1.io.enq.uop.ctrl.is_sta, io.ifu.fetchpacket.bits.uops[1].bits.ctrl.is_sta connect decode_units_1.io.enq.uop.ctrl.is_load, io.ifu.fetchpacket.bits.uops[1].bits.ctrl.is_load connect decode_units_1.io.enq.uop.ctrl.csr_cmd, io.ifu.fetchpacket.bits.uops[1].bits.ctrl.csr_cmd connect decode_units_1.io.enq.uop.ctrl.fcn_dw, io.ifu.fetchpacket.bits.uops[1].bits.ctrl.fcn_dw connect decode_units_1.io.enq.uop.ctrl.op_fcn, io.ifu.fetchpacket.bits.uops[1].bits.ctrl.op_fcn connect decode_units_1.io.enq.uop.ctrl.imm_sel, io.ifu.fetchpacket.bits.uops[1].bits.ctrl.imm_sel connect decode_units_1.io.enq.uop.ctrl.op2_sel, io.ifu.fetchpacket.bits.uops[1].bits.ctrl.op2_sel connect decode_units_1.io.enq.uop.ctrl.op1_sel, io.ifu.fetchpacket.bits.uops[1].bits.ctrl.op1_sel connect decode_units_1.io.enq.uop.ctrl.br_type, io.ifu.fetchpacket.bits.uops[1].bits.ctrl.br_type connect decode_units_1.io.enq.uop.fu_code, io.ifu.fetchpacket.bits.uops[1].bits.fu_code connect decode_units_1.io.enq.uop.iq_type, io.ifu.fetchpacket.bits.uops[1].bits.iq_type connect decode_units_1.io.enq.uop.debug_pc, io.ifu.fetchpacket.bits.uops[1].bits.debug_pc connect decode_units_1.io.enq.uop.is_rvc, io.ifu.fetchpacket.bits.uops[1].bits.is_rvc connect decode_units_1.io.enq.uop.debug_inst, io.ifu.fetchpacket.bits.uops[1].bits.debug_inst connect decode_units_1.io.enq.uop.inst, io.ifu.fetchpacket.bits.uops[1].bits.inst connect decode_units_1.io.enq.uop.uopc, io.ifu.fetchpacket.bits.uops[1].bits.uopc connect decode_units_1.io.status.uie, csr.io.status.uie connect decode_units_1.io.status.sie, csr.io.status.sie connect decode_units_1.io.status.hie, csr.io.status.hie connect decode_units_1.io.status.mie, csr.io.status.mie connect decode_units_1.io.status.upie, csr.io.status.upie connect decode_units_1.io.status.spie, csr.io.status.spie connect decode_units_1.io.status.ube, csr.io.status.ube connect decode_units_1.io.status.mpie, csr.io.status.mpie connect decode_units_1.io.status.spp, csr.io.status.spp connect decode_units_1.io.status.vs, csr.io.status.vs connect decode_units_1.io.status.mpp, csr.io.status.mpp connect decode_units_1.io.status.fs, csr.io.status.fs connect decode_units_1.io.status.xs, csr.io.status.xs connect decode_units_1.io.status.mprv, csr.io.status.mprv connect decode_units_1.io.status.sum, csr.io.status.sum connect decode_units_1.io.status.mxr, csr.io.status.mxr connect decode_units_1.io.status.tvm, csr.io.status.tvm connect decode_units_1.io.status.tw, csr.io.status.tw connect decode_units_1.io.status.tsr, csr.io.status.tsr connect decode_units_1.io.status.zero1, csr.io.status.zero1 connect decode_units_1.io.status.sd_rv32, csr.io.status.sd_rv32 connect decode_units_1.io.status.uxl, csr.io.status.uxl connect decode_units_1.io.status.sxl, csr.io.status.sxl connect decode_units_1.io.status.sbe, csr.io.status.sbe connect decode_units_1.io.status.mbe, csr.io.status.mbe connect decode_units_1.io.status.gva, csr.io.status.gva connect decode_units_1.io.status.mpv, csr.io.status.mpv connect decode_units_1.io.status.zero2, csr.io.status.zero2 connect decode_units_1.io.status.sd, csr.io.status.sd connect decode_units_1.io.status.v, csr.io.status.v connect decode_units_1.io.status.prv, csr.io.status.prv connect decode_units_1.io.status.dv, csr.io.status.dv connect decode_units_1.io.status.dprv, csr.io.status.dprv connect decode_units_1.io.status.isa, csr.io.status.isa connect decode_units_1.io.status.wfi, csr.io.status.wfi connect decode_units_1.io.status.cease, csr.io.status.cease connect decode_units_1.io.status.debug, csr.io.status.debug connect decode_units_1.io.csr_decode, csr.io.decode[1] connect decode_units_1.io.interrupt, csr.io.interrupt connect decode_units_1.io.interrupt_cause, csr.io.interrupt_cause connect dec_uops[1], decode_units_1.io.deq.uop node _dec_valids_2_T = and(io.ifu.fetchpacket.valid, io.ifu.fetchpacket.bits.uops[2].valid) node _dec_valids_2_T_1 = bits(dec_finished_mask, 2, 2) node _dec_valids_2_T_2 = eq(_dec_valids_2_T_1, UInt<1>(0h0)) node _dec_valids_2_T_3 = and(_dec_valids_2_T, _dec_valids_2_T_2) connect dec_valids[2], _dec_valids_2_T_3 connect decode_units_2.io.enq.uop.debug_tsrc, io.ifu.fetchpacket.bits.uops[2].bits.debug_tsrc connect decode_units_2.io.enq.uop.debug_fsrc, io.ifu.fetchpacket.bits.uops[2].bits.debug_fsrc connect decode_units_2.io.enq.uop.bp_xcpt_if, io.ifu.fetchpacket.bits.uops[2].bits.bp_xcpt_if connect decode_units_2.io.enq.uop.bp_debug_if, io.ifu.fetchpacket.bits.uops[2].bits.bp_debug_if connect decode_units_2.io.enq.uop.xcpt_ma_if, io.ifu.fetchpacket.bits.uops[2].bits.xcpt_ma_if connect decode_units_2.io.enq.uop.xcpt_ae_if, io.ifu.fetchpacket.bits.uops[2].bits.xcpt_ae_if connect decode_units_2.io.enq.uop.xcpt_pf_if, io.ifu.fetchpacket.bits.uops[2].bits.xcpt_pf_if connect decode_units_2.io.enq.uop.fp_single, io.ifu.fetchpacket.bits.uops[2].bits.fp_single connect decode_units_2.io.enq.uop.fp_val, io.ifu.fetchpacket.bits.uops[2].bits.fp_val connect decode_units_2.io.enq.uop.frs3_en, io.ifu.fetchpacket.bits.uops[2].bits.frs3_en connect decode_units_2.io.enq.uop.lrs2_rtype, io.ifu.fetchpacket.bits.uops[2].bits.lrs2_rtype connect decode_units_2.io.enq.uop.lrs1_rtype, io.ifu.fetchpacket.bits.uops[2].bits.lrs1_rtype connect decode_units_2.io.enq.uop.dst_rtype, io.ifu.fetchpacket.bits.uops[2].bits.dst_rtype connect decode_units_2.io.enq.uop.ldst_val, io.ifu.fetchpacket.bits.uops[2].bits.ldst_val connect decode_units_2.io.enq.uop.lrs3, io.ifu.fetchpacket.bits.uops[2].bits.lrs3 connect decode_units_2.io.enq.uop.lrs2, io.ifu.fetchpacket.bits.uops[2].bits.lrs2 connect decode_units_2.io.enq.uop.lrs1, io.ifu.fetchpacket.bits.uops[2].bits.lrs1 connect decode_units_2.io.enq.uop.ldst, io.ifu.fetchpacket.bits.uops[2].bits.ldst connect decode_units_2.io.enq.uop.ldst_is_rs1, io.ifu.fetchpacket.bits.uops[2].bits.ldst_is_rs1 connect decode_units_2.io.enq.uop.flush_on_commit, io.ifu.fetchpacket.bits.uops[2].bits.flush_on_commit connect decode_units_2.io.enq.uop.is_unique, io.ifu.fetchpacket.bits.uops[2].bits.is_unique connect decode_units_2.io.enq.uop.is_sys_pc2epc, io.ifu.fetchpacket.bits.uops[2].bits.is_sys_pc2epc connect decode_units_2.io.enq.uop.uses_stq, io.ifu.fetchpacket.bits.uops[2].bits.uses_stq connect decode_units_2.io.enq.uop.uses_ldq, io.ifu.fetchpacket.bits.uops[2].bits.uses_ldq connect decode_units_2.io.enq.uop.is_amo, io.ifu.fetchpacket.bits.uops[2].bits.is_amo connect decode_units_2.io.enq.uop.is_fencei, io.ifu.fetchpacket.bits.uops[2].bits.is_fencei connect decode_units_2.io.enq.uop.is_fence, io.ifu.fetchpacket.bits.uops[2].bits.is_fence connect decode_units_2.io.enq.uop.mem_signed, io.ifu.fetchpacket.bits.uops[2].bits.mem_signed connect decode_units_2.io.enq.uop.mem_size, io.ifu.fetchpacket.bits.uops[2].bits.mem_size connect decode_units_2.io.enq.uop.mem_cmd, io.ifu.fetchpacket.bits.uops[2].bits.mem_cmd connect decode_units_2.io.enq.uop.bypassable, io.ifu.fetchpacket.bits.uops[2].bits.bypassable connect decode_units_2.io.enq.uop.exc_cause, io.ifu.fetchpacket.bits.uops[2].bits.exc_cause connect decode_units_2.io.enq.uop.exception, io.ifu.fetchpacket.bits.uops[2].bits.exception connect decode_units_2.io.enq.uop.stale_pdst, io.ifu.fetchpacket.bits.uops[2].bits.stale_pdst connect decode_units_2.io.enq.uop.ppred_busy, io.ifu.fetchpacket.bits.uops[2].bits.ppred_busy connect decode_units_2.io.enq.uop.prs3_busy, io.ifu.fetchpacket.bits.uops[2].bits.prs3_busy connect decode_units_2.io.enq.uop.prs2_busy, io.ifu.fetchpacket.bits.uops[2].bits.prs2_busy connect decode_units_2.io.enq.uop.prs1_busy, io.ifu.fetchpacket.bits.uops[2].bits.prs1_busy connect decode_units_2.io.enq.uop.ppred, io.ifu.fetchpacket.bits.uops[2].bits.ppred connect decode_units_2.io.enq.uop.prs3, io.ifu.fetchpacket.bits.uops[2].bits.prs3 connect decode_units_2.io.enq.uop.prs2, io.ifu.fetchpacket.bits.uops[2].bits.prs2 connect decode_units_2.io.enq.uop.prs1, io.ifu.fetchpacket.bits.uops[2].bits.prs1 connect decode_units_2.io.enq.uop.pdst, io.ifu.fetchpacket.bits.uops[2].bits.pdst connect decode_units_2.io.enq.uop.rxq_idx, io.ifu.fetchpacket.bits.uops[2].bits.rxq_idx connect decode_units_2.io.enq.uop.stq_idx, io.ifu.fetchpacket.bits.uops[2].bits.stq_idx connect decode_units_2.io.enq.uop.ldq_idx, io.ifu.fetchpacket.bits.uops[2].bits.ldq_idx connect decode_units_2.io.enq.uop.rob_idx, io.ifu.fetchpacket.bits.uops[2].bits.rob_idx connect decode_units_2.io.enq.uop.csr_addr, io.ifu.fetchpacket.bits.uops[2].bits.csr_addr connect decode_units_2.io.enq.uop.imm_packed, io.ifu.fetchpacket.bits.uops[2].bits.imm_packed connect decode_units_2.io.enq.uop.taken, io.ifu.fetchpacket.bits.uops[2].bits.taken connect decode_units_2.io.enq.uop.pc_lob, io.ifu.fetchpacket.bits.uops[2].bits.pc_lob connect decode_units_2.io.enq.uop.edge_inst, io.ifu.fetchpacket.bits.uops[2].bits.edge_inst connect decode_units_2.io.enq.uop.ftq_idx, io.ifu.fetchpacket.bits.uops[2].bits.ftq_idx connect decode_units_2.io.enq.uop.br_tag, io.ifu.fetchpacket.bits.uops[2].bits.br_tag connect decode_units_2.io.enq.uop.br_mask, io.ifu.fetchpacket.bits.uops[2].bits.br_mask connect decode_units_2.io.enq.uop.is_sfb, io.ifu.fetchpacket.bits.uops[2].bits.is_sfb connect decode_units_2.io.enq.uop.is_jal, io.ifu.fetchpacket.bits.uops[2].bits.is_jal connect decode_units_2.io.enq.uop.is_jalr, io.ifu.fetchpacket.bits.uops[2].bits.is_jalr connect decode_units_2.io.enq.uop.is_br, io.ifu.fetchpacket.bits.uops[2].bits.is_br connect decode_units_2.io.enq.uop.iw_p2_poisoned, io.ifu.fetchpacket.bits.uops[2].bits.iw_p2_poisoned connect decode_units_2.io.enq.uop.iw_p1_poisoned, io.ifu.fetchpacket.bits.uops[2].bits.iw_p1_poisoned connect decode_units_2.io.enq.uop.iw_state, io.ifu.fetchpacket.bits.uops[2].bits.iw_state connect decode_units_2.io.enq.uop.ctrl.is_std, io.ifu.fetchpacket.bits.uops[2].bits.ctrl.is_std connect decode_units_2.io.enq.uop.ctrl.is_sta, io.ifu.fetchpacket.bits.uops[2].bits.ctrl.is_sta connect decode_units_2.io.enq.uop.ctrl.is_load, io.ifu.fetchpacket.bits.uops[2].bits.ctrl.is_load connect decode_units_2.io.enq.uop.ctrl.csr_cmd, io.ifu.fetchpacket.bits.uops[2].bits.ctrl.csr_cmd connect decode_units_2.io.enq.uop.ctrl.fcn_dw, io.ifu.fetchpacket.bits.uops[2].bits.ctrl.fcn_dw connect decode_units_2.io.enq.uop.ctrl.op_fcn, io.ifu.fetchpacket.bits.uops[2].bits.ctrl.op_fcn connect decode_units_2.io.enq.uop.ctrl.imm_sel, io.ifu.fetchpacket.bits.uops[2].bits.ctrl.imm_sel connect decode_units_2.io.enq.uop.ctrl.op2_sel, io.ifu.fetchpacket.bits.uops[2].bits.ctrl.op2_sel connect decode_units_2.io.enq.uop.ctrl.op1_sel, io.ifu.fetchpacket.bits.uops[2].bits.ctrl.op1_sel connect decode_units_2.io.enq.uop.ctrl.br_type, io.ifu.fetchpacket.bits.uops[2].bits.ctrl.br_type connect decode_units_2.io.enq.uop.fu_code, io.ifu.fetchpacket.bits.uops[2].bits.fu_code connect decode_units_2.io.enq.uop.iq_type, io.ifu.fetchpacket.bits.uops[2].bits.iq_type connect decode_units_2.io.enq.uop.debug_pc, io.ifu.fetchpacket.bits.uops[2].bits.debug_pc connect decode_units_2.io.enq.uop.is_rvc, io.ifu.fetchpacket.bits.uops[2].bits.is_rvc connect decode_units_2.io.enq.uop.debug_inst, io.ifu.fetchpacket.bits.uops[2].bits.debug_inst connect decode_units_2.io.enq.uop.inst, io.ifu.fetchpacket.bits.uops[2].bits.inst connect decode_units_2.io.enq.uop.uopc, io.ifu.fetchpacket.bits.uops[2].bits.uopc connect decode_units_2.io.status.uie, csr.io.status.uie connect decode_units_2.io.status.sie, csr.io.status.sie connect decode_units_2.io.status.hie, csr.io.status.hie connect decode_units_2.io.status.mie, csr.io.status.mie connect decode_units_2.io.status.upie, csr.io.status.upie connect decode_units_2.io.status.spie, csr.io.status.spie connect decode_units_2.io.status.ube, csr.io.status.ube connect decode_units_2.io.status.mpie, csr.io.status.mpie connect decode_units_2.io.status.spp, csr.io.status.spp connect decode_units_2.io.status.vs, csr.io.status.vs connect decode_units_2.io.status.mpp, csr.io.status.mpp connect decode_units_2.io.status.fs, csr.io.status.fs connect decode_units_2.io.status.xs, csr.io.status.xs connect decode_units_2.io.status.mprv, csr.io.status.mprv connect decode_units_2.io.status.sum, csr.io.status.sum connect decode_units_2.io.status.mxr, csr.io.status.mxr connect decode_units_2.io.status.tvm, csr.io.status.tvm connect decode_units_2.io.status.tw, csr.io.status.tw connect decode_units_2.io.status.tsr, csr.io.status.tsr connect decode_units_2.io.status.zero1, csr.io.status.zero1 connect decode_units_2.io.status.sd_rv32, csr.io.status.sd_rv32 connect decode_units_2.io.status.uxl, csr.io.status.uxl connect decode_units_2.io.status.sxl, csr.io.status.sxl connect decode_units_2.io.status.sbe, csr.io.status.sbe connect decode_units_2.io.status.mbe, csr.io.status.mbe connect decode_units_2.io.status.gva, csr.io.status.gva connect decode_units_2.io.status.mpv, csr.io.status.mpv connect decode_units_2.io.status.zero2, csr.io.status.zero2 connect decode_units_2.io.status.sd, csr.io.status.sd connect decode_units_2.io.status.v, csr.io.status.v connect decode_units_2.io.status.prv, csr.io.status.prv connect decode_units_2.io.status.dv, csr.io.status.dv connect decode_units_2.io.status.dprv, csr.io.status.dprv connect decode_units_2.io.status.isa, csr.io.status.isa connect decode_units_2.io.status.wfi, csr.io.status.wfi connect decode_units_2.io.status.cease, csr.io.status.cease connect decode_units_2.io.status.debug, csr.io.status.debug connect decode_units_2.io.csr_decode, csr.io.decode[2] connect decode_units_2.io.interrupt, csr.io.interrupt connect decode_units_2.io.interrupt_cause, csr.io.interrupt_cause connect dec_uops[2], decode_units_2.io.deq.uop wire jmp_pc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>} wire xcpt_pc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>} wire flush_pc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>} inst ftq_arb of Arbiter3_UInt5_1 connect ftq_arb.clock, clock connect ftq_arb.reset, reset connect ftq_arb.io.in[0], flush_pc_req connect ftq_arb.io.in[1], jmp_pc_req connect ftq_arb.io.in[2], xcpt_pc_req connect io.ifu.get_pc[0].ftq_idx, ftq_arb.io.out.bits connect ftq_arb.io.out.ready, UInt<1>(0h1) node _jmp_pc_req_valid_T = eq(iss_uops[1].fu_code, UInt<10>(0h2)) node _jmp_pc_req_valid_T_1 = and(iss_valids[1], _jmp_pc_req_valid_T) reg jmp_pc_req_valid_REG : UInt<1>, clock connect jmp_pc_req_valid_REG, _jmp_pc_req_valid_T_1 connect jmp_pc_req.valid, jmp_pc_req_valid_REG reg jmp_pc_req_bits_REG : UInt, clock connect jmp_pc_req_bits_REG, iss_uops[1].ftq_idx connect jmp_pc_req.bits, jmp_pc_req_bits_REG invalidate alu_exe_unit.io.get_ftq_pc.next_pc invalidate alu_exe_unit.io.get_ftq_pc.next_val invalidate alu_exe_unit.io.get_ftq_pc.com_pc invalidate alu_exe_unit.io.get_ftq_pc.pc invalidate alu_exe_unit.io.get_ftq_pc.ghist.ras_idx invalidate alu_exe_unit.io.get_ftq_pc.ghist.new_saw_branch_taken invalidate alu_exe_unit.io.get_ftq_pc.ghist.new_saw_branch_not_taken invalidate alu_exe_unit.io.get_ftq_pc.ghist.current_saw_branch_not_taken invalidate alu_exe_unit.io.get_ftq_pc.ghist.old_history invalidate alu_exe_unit.io.get_ftq_pc.entry.start_bank invalidate alu_exe_unit.io.get_ftq_pc.entry.ras_idx invalidate alu_exe_unit.io.get_ftq_pc.entry.ras_top invalidate alu_exe_unit.io.get_ftq_pc.entry.cfi_npc_plus4 invalidate alu_exe_unit.io.get_ftq_pc.entry.cfi_is_ret invalidate alu_exe_unit.io.get_ftq_pc.entry.cfi_is_call invalidate alu_exe_unit.io.get_ftq_pc.entry.br_mask invalidate alu_exe_unit.io.get_ftq_pc.entry.cfi_type invalidate alu_exe_unit.io.get_ftq_pc.entry.cfi_mispredicted invalidate alu_exe_unit.io.get_ftq_pc.entry.cfi_taken invalidate alu_exe_unit.io.get_ftq_pc.entry.cfi_idx.bits invalidate alu_exe_unit.io.get_ftq_pc.entry.cfi_idx.valid invalidate alu_exe_unit.io.get_ftq_pc.ftq_idx connect alu_exe_unit.io.get_ftq_pc.pc, io.ifu.get_pc[0].pc connect alu_exe_unit.io.get_ftq_pc.entry.start_bank, io.ifu.get_pc[0].entry.start_bank connect alu_exe_unit.io.get_ftq_pc.entry.ras_idx, io.ifu.get_pc[0].entry.ras_idx connect alu_exe_unit.io.get_ftq_pc.entry.ras_top, io.ifu.get_pc[0].entry.ras_top connect alu_exe_unit.io.get_ftq_pc.entry.cfi_npc_plus4, io.ifu.get_pc[0].entry.cfi_npc_plus4 connect alu_exe_unit.io.get_ftq_pc.entry.cfi_is_ret, io.ifu.get_pc[0].entry.cfi_is_ret connect alu_exe_unit.io.get_ftq_pc.entry.cfi_is_call, io.ifu.get_pc[0].entry.cfi_is_call connect alu_exe_unit.io.get_ftq_pc.entry.br_mask, io.ifu.get_pc[0].entry.br_mask connect alu_exe_unit.io.get_ftq_pc.entry.cfi_type, io.ifu.get_pc[0].entry.cfi_type connect alu_exe_unit.io.get_ftq_pc.entry.cfi_mispredicted, io.ifu.get_pc[0].entry.cfi_mispredicted connect alu_exe_unit.io.get_ftq_pc.entry.cfi_taken, io.ifu.get_pc[0].entry.cfi_taken connect alu_exe_unit.io.get_ftq_pc.entry.cfi_idx.bits, io.ifu.get_pc[0].entry.cfi_idx.bits connect alu_exe_unit.io.get_ftq_pc.entry.cfi_idx.valid, io.ifu.get_pc[0].entry.cfi_idx.valid connect alu_exe_unit.io.get_ftq_pc.next_val, io.ifu.get_pc[0].next_val connect alu_exe_unit.io.get_ftq_pc.next_pc, io.ifu.get_pc[0].next_pc node _xcpt_idx_T = mux(dec_xcpts[1], UInt<1>(0h1), UInt<2>(0h2)) node xcpt_idx = mux(dec_xcpts[0], UInt<1>(0h0), _xcpt_idx_T) node _xcpt_pc_req_valid_T = or(dec_xcpts[0], dec_xcpts[1]) node _xcpt_pc_req_valid_T_1 = or(_xcpt_pc_req_valid_T, dec_xcpts[2]) connect xcpt_pc_req.valid, _xcpt_pc_req_valid_T_1 connect xcpt_pc_req.bits, dec_uops[xcpt_idx].ftq_idx connect rob.io.xcpt_fetch_pc, io.ifu.get_pc[0].pc connect flush_pc_req.valid, rob.io.flush.valid connect flush_pc_req.bits, rob.io.flush.bits.ftq_idx connect io.ifu.get_pc[1].ftq_idx, _T_8.uop.ftq_idx node _T_28 = and(dec_uops[0].exception, dec_valids[0]) node _T_29 = and(dec_uops[1].exception, dec_valids[1]) node _T_30 = and(dec_uops[2].exception, dec_valids[2]) connect dec_xcpts[0], _T_28 connect dec_xcpts[1], _T_29 connect dec_xcpts[2], _T_30 node _dec_xcpt_stall_T = or(dec_xcpts[0], dec_xcpts[1]) node _dec_xcpt_stall_T_1 = or(_dec_xcpt_stall_T, dec_xcpts[2]) node _dec_xcpt_stall_T_2 = eq(xcpt_pc_req.ready, UInt<1>(0h0)) node dec_xcpt_stall = and(_dec_xcpt_stall_T_1, _dec_xcpt_stall_T_2) wire branch_mask_full : UInt<1>[3] node _dec_hazards_T = eq(dis_ready, UInt<1>(0h0)) node _dec_hazards_T_1 = or(_dec_hazards_T, rob.io.commit.rollback) node _dec_hazards_T_2 = or(_dec_hazards_T_1, dec_xcpt_stall) node _dec_hazards_T_3 = or(_dec_hazards_T_2, branch_mask_full[0]) node _dec_hazards_T_4 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _dec_hazards_T_5 = or(_dec_hazards_T_3, _dec_hazards_T_4) node _dec_hazards_T_6 = or(_dec_hazards_T_5, brupdate.b2.mispredict) node _dec_hazards_T_7 = or(_dec_hazards_T_6, io.ifu.redirect_flush) node dec_hazards_0 = and(dec_valids[0], _dec_hazards_T_7) node _dec_hazards_T_8 = eq(dis_ready, UInt<1>(0h0)) node _dec_hazards_T_9 = or(_dec_hazards_T_8, rob.io.commit.rollback) node _dec_hazards_T_10 = or(_dec_hazards_T_9, dec_xcpt_stall) node _dec_hazards_T_11 = or(_dec_hazards_T_10, branch_mask_full[1]) node _dec_hazards_T_12 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _dec_hazards_T_13 = or(_dec_hazards_T_11, _dec_hazards_T_12) node _dec_hazards_T_14 = or(_dec_hazards_T_13, brupdate.b2.mispredict) node _dec_hazards_T_15 = or(_dec_hazards_T_14, io.ifu.redirect_flush) node dec_hazards_1 = and(dec_valids[1], _dec_hazards_T_15) node _dec_hazards_T_16 = eq(dis_ready, UInt<1>(0h0)) node _dec_hazards_T_17 = or(_dec_hazards_T_16, rob.io.commit.rollback) node _dec_hazards_T_18 = or(_dec_hazards_T_17, dec_xcpt_stall) node _dec_hazards_T_19 = or(_dec_hazards_T_18, branch_mask_full[2]) node _dec_hazards_T_20 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _dec_hazards_T_21 = or(_dec_hazards_T_19, _dec_hazards_T_20) node _dec_hazards_T_22 = or(_dec_hazards_T_21, brupdate.b2.mispredict) node _dec_hazards_T_23 = or(_dec_hazards_T_22, io.ifu.redirect_flush) node dec_hazards_2 = and(dec_valids[2], _dec_hazards_T_23) node dec_stalls_0 = or(UInt<1>(0h0), dec_hazards_0) node dec_stalls_1 = or(dec_stalls_0, dec_hazards_1) node dec_stalls_2 = or(dec_stalls_1, dec_hazards_2) node _T_31 = eq(dec_stalls_0, UInt<1>(0h0)) node _T_32 = and(dec_valids[0], _T_31) node _T_33 = eq(dec_stalls_1, UInt<1>(0h0)) node _T_34 = and(dec_valids[1], _T_33) node _T_35 = eq(dec_stalls_2, UInt<1>(0h0)) node _T_36 = and(dec_valids[2], _T_35) connect dec_fire[0], _T_32 connect dec_fire[1], _T_34 connect dec_fire[2], _T_36 connect dec_ready, dec_fire[2] node _T_37 = or(dec_ready, io.ifu.redirect_flush) when _T_37 : connect dec_finished_mask, UInt<1>(0h0) else : node dec_finished_mask_hi = cat(dec_fire[2], dec_fire[1]) node _dec_finished_mask_T = cat(dec_finished_mask_hi, dec_fire[0]) node _dec_finished_mask_T_1 = or(_dec_finished_mask_T, dec_finished_mask) connect dec_finished_mask, _dec_finished_mask_T_1 connect dec_brmask_logic.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect dec_brmask_logic.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect dec_brmask_logic.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect dec_brmask_logic.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect dec_brmask_logic.io.brupdate.b2.taken, brupdate.b2.taken connect dec_brmask_logic.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect dec_brmask_logic.io.brupdate.b2.valid, brupdate.b2.valid connect dec_brmask_logic.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect dec_brmask_logic.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect dec_brmask_logic.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect dec_brmask_logic.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect dec_brmask_logic.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect dec_brmask_logic.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect dec_brmask_logic.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect dec_brmask_logic.io.brupdate.b2.uop.fp_single, brupdate.b2.uop.fp_single connect dec_brmask_logic.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect dec_brmask_logic.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect dec_brmask_logic.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect dec_brmask_logic.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect dec_brmask_logic.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect dec_brmask_logic.io.brupdate.b2.uop.ldst_val, brupdate.b2.uop.ldst_val connect dec_brmask_logic.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect dec_brmask_logic.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect dec_brmask_logic.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect dec_brmask_logic.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect dec_brmask_logic.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect dec_brmask_logic.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect dec_brmask_logic.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect dec_brmask_logic.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect dec_brmask_logic.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect dec_brmask_logic.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect dec_brmask_logic.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect dec_brmask_logic.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect dec_brmask_logic.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect dec_brmask_logic.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect dec_brmask_logic.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect dec_brmask_logic.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect dec_brmask_logic.io.brupdate.b2.uop.bypassable, brupdate.b2.uop.bypassable connect dec_brmask_logic.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect dec_brmask_logic.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect dec_brmask_logic.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect dec_brmask_logic.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect dec_brmask_logic.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect dec_brmask_logic.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect dec_brmask_logic.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect dec_brmask_logic.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect dec_brmask_logic.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect dec_brmask_logic.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect dec_brmask_logic.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect dec_brmask_logic.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect dec_brmask_logic.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect dec_brmask_logic.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect dec_brmask_logic.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect dec_brmask_logic.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect dec_brmask_logic.io.brupdate.b2.uop.csr_addr, brupdate.b2.uop.csr_addr connect dec_brmask_logic.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect dec_brmask_logic.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect dec_brmask_logic.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect dec_brmask_logic.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect dec_brmask_logic.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect dec_brmask_logic.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect dec_brmask_logic.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect dec_brmask_logic.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect dec_brmask_logic.io.brupdate.b2.uop.is_jal, brupdate.b2.uop.is_jal connect dec_brmask_logic.io.brupdate.b2.uop.is_jalr, brupdate.b2.uop.is_jalr connect dec_brmask_logic.io.brupdate.b2.uop.is_br, brupdate.b2.uop.is_br connect dec_brmask_logic.io.brupdate.b2.uop.iw_p2_poisoned, brupdate.b2.uop.iw_p2_poisoned connect dec_brmask_logic.io.brupdate.b2.uop.iw_p1_poisoned, brupdate.b2.uop.iw_p1_poisoned connect dec_brmask_logic.io.brupdate.b2.uop.iw_state, brupdate.b2.uop.iw_state connect dec_brmask_logic.io.brupdate.b2.uop.ctrl.is_std, brupdate.b2.uop.ctrl.is_std connect dec_brmask_logic.io.brupdate.b2.uop.ctrl.is_sta, brupdate.b2.uop.ctrl.is_sta connect dec_brmask_logic.io.brupdate.b2.uop.ctrl.is_load, brupdate.b2.uop.ctrl.is_load connect dec_brmask_logic.io.brupdate.b2.uop.ctrl.csr_cmd, brupdate.b2.uop.ctrl.csr_cmd connect dec_brmask_logic.io.brupdate.b2.uop.ctrl.fcn_dw, brupdate.b2.uop.ctrl.fcn_dw connect dec_brmask_logic.io.brupdate.b2.uop.ctrl.op_fcn, brupdate.b2.uop.ctrl.op_fcn connect dec_brmask_logic.io.brupdate.b2.uop.ctrl.imm_sel, brupdate.b2.uop.ctrl.imm_sel connect dec_brmask_logic.io.brupdate.b2.uop.ctrl.op2_sel, brupdate.b2.uop.ctrl.op2_sel connect dec_brmask_logic.io.brupdate.b2.uop.ctrl.op1_sel, brupdate.b2.uop.ctrl.op1_sel connect dec_brmask_logic.io.brupdate.b2.uop.ctrl.br_type, brupdate.b2.uop.ctrl.br_type connect dec_brmask_logic.io.brupdate.b2.uop.fu_code, brupdate.b2.uop.fu_code connect dec_brmask_logic.io.brupdate.b2.uop.iq_type, brupdate.b2.uop.iq_type connect dec_brmask_logic.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect dec_brmask_logic.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect dec_brmask_logic.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect dec_brmask_logic.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect dec_brmask_logic.io.brupdate.b2.uop.uopc, brupdate.b2.uop.uopc connect dec_brmask_logic.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect dec_brmask_logic.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask reg dec_brmask_logic_io_flush_pipeline_REG : UInt<1>, clock connect dec_brmask_logic_io_flush_pipeline_REG, rob.io.flush.valid connect dec_brmask_logic.io.flush_pipeline, dec_brmask_logic_io_flush_pipeline_REG node _dec_brmask_logic_io_is_branch_0_T = bits(dec_finished_mask, 0, 0) node _dec_brmask_logic_io_is_branch_0_T_1 = eq(_dec_brmask_logic_io_is_branch_0_T, UInt<1>(0h0)) node _dec_brmask_logic_io_is_branch_0_T_2 = eq(dec_uops[0].is_sfb, UInt<1>(0h0)) node _dec_brmask_logic_io_is_branch_0_T_3 = and(dec_uops[0].is_br, _dec_brmask_logic_io_is_branch_0_T_2) node _dec_brmask_logic_io_is_branch_0_T_4 = or(_dec_brmask_logic_io_is_branch_0_T_3, dec_uops[0].is_jalr) node _dec_brmask_logic_io_is_branch_0_T_5 = and(_dec_brmask_logic_io_is_branch_0_T_1, _dec_brmask_logic_io_is_branch_0_T_4) connect dec_brmask_logic.io.is_branch[0], _dec_brmask_logic_io_is_branch_0_T_5 node _dec_brmask_logic_io_will_fire_0_T = eq(dec_uops[0].is_sfb, UInt<1>(0h0)) node _dec_brmask_logic_io_will_fire_0_T_1 = and(dec_uops[0].is_br, _dec_brmask_logic_io_will_fire_0_T) node _dec_brmask_logic_io_will_fire_0_T_2 = or(_dec_brmask_logic_io_will_fire_0_T_1, dec_uops[0].is_jalr) node _dec_brmask_logic_io_will_fire_0_T_3 = and(dec_fire[0], _dec_brmask_logic_io_will_fire_0_T_2) connect dec_brmask_logic.io.will_fire[0], _dec_brmask_logic_io_will_fire_0_T_3 connect dec_uops[0].br_tag, dec_brmask_logic.io.br_tag[0] connect dec_uops[0].br_mask, dec_brmask_logic.io.br_mask[0] node _dec_brmask_logic_io_is_branch_1_T = bits(dec_finished_mask, 1, 1) node _dec_brmask_logic_io_is_branch_1_T_1 = eq(_dec_brmask_logic_io_is_branch_1_T, UInt<1>(0h0)) node _dec_brmask_logic_io_is_branch_1_T_2 = eq(dec_uops[1].is_sfb, UInt<1>(0h0)) node _dec_brmask_logic_io_is_branch_1_T_3 = and(dec_uops[1].is_br, _dec_brmask_logic_io_is_branch_1_T_2) node _dec_brmask_logic_io_is_branch_1_T_4 = or(_dec_brmask_logic_io_is_branch_1_T_3, dec_uops[1].is_jalr) node _dec_brmask_logic_io_is_branch_1_T_5 = and(_dec_brmask_logic_io_is_branch_1_T_1, _dec_brmask_logic_io_is_branch_1_T_4) connect dec_brmask_logic.io.is_branch[1], _dec_brmask_logic_io_is_branch_1_T_5 node _dec_brmask_logic_io_will_fire_1_T = eq(dec_uops[1].is_sfb, UInt<1>(0h0)) node _dec_brmask_logic_io_will_fire_1_T_1 = and(dec_uops[1].is_br, _dec_brmask_logic_io_will_fire_1_T) node _dec_brmask_logic_io_will_fire_1_T_2 = or(_dec_brmask_logic_io_will_fire_1_T_1, dec_uops[1].is_jalr) node _dec_brmask_logic_io_will_fire_1_T_3 = and(dec_fire[1], _dec_brmask_logic_io_will_fire_1_T_2) connect dec_brmask_logic.io.will_fire[1], _dec_brmask_logic_io_will_fire_1_T_3 connect dec_uops[1].br_tag, dec_brmask_logic.io.br_tag[1] connect dec_uops[1].br_mask, dec_brmask_logic.io.br_mask[1] node _dec_brmask_logic_io_is_branch_2_T = bits(dec_finished_mask, 2, 2) node _dec_brmask_logic_io_is_branch_2_T_1 = eq(_dec_brmask_logic_io_is_branch_2_T, UInt<1>(0h0)) node _dec_brmask_logic_io_is_branch_2_T_2 = eq(dec_uops[2].is_sfb, UInt<1>(0h0)) node _dec_brmask_logic_io_is_branch_2_T_3 = and(dec_uops[2].is_br, _dec_brmask_logic_io_is_branch_2_T_2) node _dec_brmask_logic_io_is_branch_2_T_4 = or(_dec_brmask_logic_io_is_branch_2_T_3, dec_uops[2].is_jalr) node _dec_brmask_logic_io_is_branch_2_T_5 = and(_dec_brmask_logic_io_is_branch_2_T_1, _dec_brmask_logic_io_is_branch_2_T_4) connect dec_brmask_logic.io.is_branch[2], _dec_brmask_logic_io_is_branch_2_T_5 node _dec_brmask_logic_io_will_fire_2_T = eq(dec_uops[2].is_sfb, UInt<1>(0h0)) node _dec_brmask_logic_io_will_fire_2_T_1 = and(dec_uops[2].is_br, _dec_brmask_logic_io_will_fire_2_T) node _dec_brmask_logic_io_will_fire_2_T_2 = or(_dec_brmask_logic_io_will_fire_2_T_1, dec_uops[2].is_jalr) node _dec_brmask_logic_io_will_fire_2_T_3 = and(dec_fire[2], _dec_brmask_logic_io_will_fire_2_T_2) connect dec_brmask_logic.io.will_fire[2], _dec_brmask_logic_io_will_fire_2_T_3 connect dec_uops[2].br_tag, dec_brmask_logic.io.br_tag[2] connect dec_uops[2].br_mask, dec_brmask_logic.io.br_mask[2] connect branch_mask_full, dec_brmask_logic.io.is_full connect rename_stage.io.kill, io.ifu.redirect_flush connect rename_stage.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect rename_stage.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect rename_stage.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect rename_stage.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect rename_stage.io.brupdate.b2.taken, brupdate.b2.taken connect rename_stage.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect rename_stage.io.brupdate.b2.valid, brupdate.b2.valid connect rename_stage.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect rename_stage.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect rename_stage.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect rename_stage.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect rename_stage.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect rename_stage.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect rename_stage.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect rename_stage.io.brupdate.b2.uop.fp_single, brupdate.b2.uop.fp_single connect rename_stage.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect rename_stage.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect rename_stage.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect rename_stage.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect rename_stage.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect rename_stage.io.brupdate.b2.uop.ldst_val, brupdate.b2.uop.ldst_val connect rename_stage.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect rename_stage.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect rename_stage.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect rename_stage.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect rename_stage.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect rename_stage.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect rename_stage.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect rename_stage.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect rename_stage.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect rename_stage.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect rename_stage.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect rename_stage.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect rename_stage.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect rename_stage.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect rename_stage.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect rename_stage.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect rename_stage.io.brupdate.b2.uop.bypassable, brupdate.b2.uop.bypassable connect rename_stage.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect rename_stage.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect rename_stage.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect rename_stage.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect rename_stage.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect rename_stage.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect rename_stage.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect rename_stage.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect rename_stage.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect rename_stage.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect rename_stage.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect rename_stage.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect rename_stage.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect rename_stage.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect rename_stage.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect rename_stage.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect rename_stage.io.brupdate.b2.uop.csr_addr, brupdate.b2.uop.csr_addr connect rename_stage.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect rename_stage.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect rename_stage.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect rename_stage.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect rename_stage.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect rename_stage.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect rename_stage.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect rename_stage.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect rename_stage.io.brupdate.b2.uop.is_jal, brupdate.b2.uop.is_jal connect rename_stage.io.brupdate.b2.uop.is_jalr, brupdate.b2.uop.is_jalr connect rename_stage.io.brupdate.b2.uop.is_br, brupdate.b2.uop.is_br connect rename_stage.io.brupdate.b2.uop.iw_p2_poisoned, brupdate.b2.uop.iw_p2_poisoned connect rename_stage.io.brupdate.b2.uop.iw_p1_poisoned, brupdate.b2.uop.iw_p1_poisoned connect rename_stage.io.brupdate.b2.uop.iw_state, brupdate.b2.uop.iw_state connect rename_stage.io.brupdate.b2.uop.ctrl.is_std, brupdate.b2.uop.ctrl.is_std connect rename_stage.io.brupdate.b2.uop.ctrl.is_sta, brupdate.b2.uop.ctrl.is_sta connect rename_stage.io.brupdate.b2.uop.ctrl.is_load, brupdate.b2.uop.ctrl.is_load connect rename_stage.io.brupdate.b2.uop.ctrl.csr_cmd, brupdate.b2.uop.ctrl.csr_cmd connect rename_stage.io.brupdate.b2.uop.ctrl.fcn_dw, brupdate.b2.uop.ctrl.fcn_dw connect rename_stage.io.brupdate.b2.uop.ctrl.op_fcn, brupdate.b2.uop.ctrl.op_fcn connect rename_stage.io.brupdate.b2.uop.ctrl.imm_sel, brupdate.b2.uop.ctrl.imm_sel connect rename_stage.io.brupdate.b2.uop.ctrl.op2_sel, brupdate.b2.uop.ctrl.op2_sel connect rename_stage.io.brupdate.b2.uop.ctrl.op1_sel, brupdate.b2.uop.ctrl.op1_sel connect rename_stage.io.brupdate.b2.uop.ctrl.br_type, brupdate.b2.uop.ctrl.br_type connect rename_stage.io.brupdate.b2.uop.fu_code, brupdate.b2.uop.fu_code connect rename_stage.io.brupdate.b2.uop.iq_type, brupdate.b2.uop.iq_type connect rename_stage.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect rename_stage.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect rename_stage.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect rename_stage.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect rename_stage.io.brupdate.b2.uop.uopc, brupdate.b2.uop.uopc connect rename_stage.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect rename_stage.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect rename_stage.io.debug_rob_empty, rob.io.empty connect rename_stage.io.dec_fire[0], dec_fire[0] connect rename_stage.io.dec_fire[1], dec_fire[1] connect rename_stage.io.dec_fire[2], dec_fire[2] connect rename_stage.io.dec_uops[0].debug_tsrc, dec_uops[0].debug_tsrc connect rename_stage.io.dec_uops[0].debug_fsrc, dec_uops[0].debug_fsrc connect rename_stage.io.dec_uops[0].bp_xcpt_if, dec_uops[0].bp_xcpt_if connect rename_stage.io.dec_uops[0].bp_debug_if, dec_uops[0].bp_debug_if connect rename_stage.io.dec_uops[0].xcpt_ma_if, dec_uops[0].xcpt_ma_if connect rename_stage.io.dec_uops[0].xcpt_ae_if, dec_uops[0].xcpt_ae_if connect rename_stage.io.dec_uops[0].xcpt_pf_if, dec_uops[0].xcpt_pf_if connect rename_stage.io.dec_uops[0].fp_single, dec_uops[0].fp_single connect rename_stage.io.dec_uops[0].fp_val, dec_uops[0].fp_val connect rename_stage.io.dec_uops[0].frs3_en, dec_uops[0].frs3_en connect rename_stage.io.dec_uops[0].lrs2_rtype, dec_uops[0].lrs2_rtype connect rename_stage.io.dec_uops[0].lrs1_rtype, dec_uops[0].lrs1_rtype connect rename_stage.io.dec_uops[0].dst_rtype, dec_uops[0].dst_rtype connect rename_stage.io.dec_uops[0].ldst_val, dec_uops[0].ldst_val connect rename_stage.io.dec_uops[0].lrs3, dec_uops[0].lrs3 connect rename_stage.io.dec_uops[0].lrs2, dec_uops[0].lrs2 connect rename_stage.io.dec_uops[0].lrs1, dec_uops[0].lrs1 connect rename_stage.io.dec_uops[0].ldst, dec_uops[0].ldst connect rename_stage.io.dec_uops[0].ldst_is_rs1, dec_uops[0].ldst_is_rs1 connect rename_stage.io.dec_uops[0].flush_on_commit, dec_uops[0].flush_on_commit connect rename_stage.io.dec_uops[0].is_unique, dec_uops[0].is_unique connect rename_stage.io.dec_uops[0].is_sys_pc2epc, dec_uops[0].is_sys_pc2epc connect rename_stage.io.dec_uops[0].uses_stq, dec_uops[0].uses_stq connect rename_stage.io.dec_uops[0].uses_ldq, dec_uops[0].uses_ldq connect rename_stage.io.dec_uops[0].is_amo, dec_uops[0].is_amo connect rename_stage.io.dec_uops[0].is_fencei, dec_uops[0].is_fencei connect rename_stage.io.dec_uops[0].is_fence, dec_uops[0].is_fence connect rename_stage.io.dec_uops[0].mem_signed, dec_uops[0].mem_signed connect rename_stage.io.dec_uops[0].mem_size, dec_uops[0].mem_size connect rename_stage.io.dec_uops[0].mem_cmd, dec_uops[0].mem_cmd connect rename_stage.io.dec_uops[0].bypassable, dec_uops[0].bypassable connect rename_stage.io.dec_uops[0].exc_cause, dec_uops[0].exc_cause connect rename_stage.io.dec_uops[0].exception, dec_uops[0].exception connect rename_stage.io.dec_uops[0].stale_pdst, dec_uops[0].stale_pdst connect rename_stage.io.dec_uops[0].ppred_busy, dec_uops[0].ppred_busy connect rename_stage.io.dec_uops[0].prs3_busy, dec_uops[0].prs3_busy connect rename_stage.io.dec_uops[0].prs2_busy, dec_uops[0].prs2_busy connect rename_stage.io.dec_uops[0].prs1_busy, dec_uops[0].prs1_busy connect rename_stage.io.dec_uops[0].ppred, dec_uops[0].ppred connect rename_stage.io.dec_uops[0].prs3, dec_uops[0].prs3 connect rename_stage.io.dec_uops[0].prs2, dec_uops[0].prs2 connect rename_stage.io.dec_uops[0].prs1, dec_uops[0].prs1 connect rename_stage.io.dec_uops[0].pdst, dec_uops[0].pdst connect rename_stage.io.dec_uops[0].rxq_idx, dec_uops[0].rxq_idx connect rename_stage.io.dec_uops[0].stq_idx, dec_uops[0].stq_idx connect rename_stage.io.dec_uops[0].ldq_idx, dec_uops[0].ldq_idx connect rename_stage.io.dec_uops[0].rob_idx, dec_uops[0].rob_idx connect rename_stage.io.dec_uops[0].csr_addr, dec_uops[0].csr_addr connect rename_stage.io.dec_uops[0].imm_packed, dec_uops[0].imm_packed connect rename_stage.io.dec_uops[0].taken, dec_uops[0].taken connect rename_stage.io.dec_uops[0].pc_lob, dec_uops[0].pc_lob connect rename_stage.io.dec_uops[0].edge_inst, dec_uops[0].edge_inst connect rename_stage.io.dec_uops[0].ftq_idx, dec_uops[0].ftq_idx connect rename_stage.io.dec_uops[0].br_tag, dec_uops[0].br_tag connect rename_stage.io.dec_uops[0].br_mask, dec_uops[0].br_mask connect rename_stage.io.dec_uops[0].is_sfb, dec_uops[0].is_sfb connect rename_stage.io.dec_uops[0].is_jal, dec_uops[0].is_jal connect rename_stage.io.dec_uops[0].is_jalr, dec_uops[0].is_jalr connect rename_stage.io.dec_uops[0].is_br, dec_uops[0].is_br connect rename_stage.io.dec_uops[0].iw_p2_poisoned, dec_uops[0].iw_p2_poisoned connect rename_stage.io.dec_uops[0].iw_p1_poisoned, dec_uops[0].iw_p1_poisoned connect rename_stage.io.dec_uops[0].iw_state, dec_uops[0].iw_state connect rename_stage.io.dec_uops[0].ctrl.is_std, dec_uops[0].ctrl.is_std connect rename_stage.io.dec_uops[0].ctrl.is_sta, dec_uops[0].ctrl.is_sta connect rename_stage.io.dec_uops[0].ctrl.is_load, dec_uops[0].ctrl.is_load connect rename_stage.io.dec_uops[0].ctrl.csr_cmd, dec_uops[0].ctrl.csr_cmd connect rename_stage.io.dec_uops[0].ctrl.fcn_dw, dec_uops[0].ctrl.fcn_dw connect rename_stage.io.dec_uops[0].ctrl.op_fcn, dec_uops[0].ctrl.op_fcn connect rename_stage.io.dec_uops[0].ctrl.imm_sel, dec_uops[0].ctrl.imm_sel connect rename_stage.io.dec_uops[0].ctrl.op2_sel, dec_uops[0].ctrl.op2_sel connect rename_stage.io.dec_uops[0].ctrl.op1_sel, dec_uops[0].ctrl.op1_sel connect rename_stage.io.dec_uops[0].ctrl.br_type, dec_uops[0].ctrl.br_type connect rename_stage.io.dec_uops[0].fu_code, dec_uops[0].fu_code connect rename_stage.io.dec_uops[0].iq_type, dec_uops[0].iq_type connect rename_stage.io.dec_uops[0].debug_pc, dec_uops[0].debug_pc connect rename_stage.io.dec_uops[0].is_rvc, dec_uops[0].is_rvc connect rename_stage.io.dec_uops[0].debug_inst, dec_uops[0].debug_inst connect rename_stage.io.dec_uops[0].inst, dec_uops[0].inst connect rename_stage.io.dec_uops[0].uopc, dec_uops[0].uopc connect rename_stage.io.dec_uops[1].debug_tsrc, dec_uops[1].debug_tsrc connect rename_stage.io.dec_uops[1].debug_fsrc, dec_uops[1].debug_fsrc connect rename_stage.io.dec_uops[1].bp_xcpt_if, dec_uops[1].bp_xcpt_if connect rename_stage.io.dec_uops[1].bp_debug_if, dec_uops[1].bp_debug_if connect rename_stage.io.dec_uops[1].xcpt_ma_if, dec_uops[1].xcpt_ma_if connect rename_stage.io.dec_uops[1].xcpt_ae_if, dec_uops[1].xcpt_ae_if connect rename_stage.io.dec_uops[1].xcpt_pf_if, dec_uops[1].xcpt_pf_if connect rename_stage.io.dec_uops[1].fp_single, dec_uops[1].fp_single connect rename_stage.io.dec_uops[1].fp_val, dec_uops[1].fp_val connect rename_stage.io.dec_uops[1].frs3_en, dec_uops[1].frs3_en connect rename_stage.io.dec_uops[1].lrs2_rtype, dec_uops[1].lrs2_rtype connect rename_stage.io.dec_uops[1].lrs1_rtype, dec_uops[1].lrs1_rtype connect rename_stage.io.dec_uops[1].dst_rtype, dec_uops[1].dst_rtype connect rename_stage.io.dec_uops[1].ldst_val, dec_uops[1].ldst_val connect rename_stage.io.dec_uops[1].lrs3, dec_uops[1].lrs3 connect rename_stage.io.dec_uops[1].lrs2, dec_uops[1].lrs2 connect rename_stage.io.dec_uops[1].lrs1, dec_uops[1].lrs1 connect rename_stage.io.dec_uops[1].ldst, dec_uops[1].ldst connect rename_stage.io.dec_uops[1].ldst_is_rs1, dec_uops[1].ldst_is_rs1 connect rename_stage.io.dec_uops[1].flush_on_commit, dec_uops[1].flush_on_commit connect rename_stage.io.dec_uops[1].is_unique, dec_uops[1].is_unique connect rename_stage.io.dec_uops[1].is_sys_pc2epc, dec_uops[1].is_sys_pc2epc connect rename_stage.io.dec_uops[1].uses_stq, dec_uops[1].uses_stq connect rename_stage.io.dec_uops[1].uses_ldq, dec_uops[1].uses_ldq connect rename_stage.io.dec_uops[1].is_amo, dec_uops[1].is_amo connect rename_stage.io.dec_uops[1].is_fencei, dec_uops[1].is_fencei connect rename_stage.io.dec_uops[1].is_fence, dec_uops[1].is_fence connect rename_stage.io.dec_uops[1].mem_signed, dec_uops[1].mem_signed connect rename_stage.io.dec_uops[1].mem_size, dec_uops[1].mem_size connect rename_stage.io.dec_uops[1].mem_cmd, dec_uops[1].mem_cmd connect rename_stage.io.dec_uops[1].bypassable, dec_uops[1].bypassable connect rename_stage.io.dec_uops[1].exc_cause, dec_uops[1].exc_cause connect rename_stage.io.dec_uops[1].exception, dec_uops[1].exception connect rename_stage.io.dec_uops[1].stale_pdst, dec_uops[1].stale_pdst connect rename_stage.io.dec_uops[1].ppred_busy, dec_uops[1].ppred_busy connect rename_stage.io.dec_uops[1].prs3_busy, dec_uops[1].prs3_busy connect rename_stage.io.dec_uops[1].prs2_busy, dec_uops[1].prs2_busy connect rename_stage.io.dec_uops[1].prs1_busy, dec_uops[1].prs1_busy connect rename_stage.io.dec_uops[1].ppred, dec_uops[1].ppred connect rename_stage.io.dec_uops[1].prs3, dec_uops[1].prs3 connect rename_stage.io.dec_uops[1].prs2, dec_uops[1].prs2 connect rename_stage.io.dec_uops[1].prs1, dec_uops[1].prs1 connect rename_stage.io.dec_uops[1].pdst, dec_uops[1].pdst connect rename_stage.io.dec_uops[1].rxq_idx, dec_uops[1].rxq_idx connect rename_stage.io.dec_uops[1].stq_idx, dec_uops[1].stq_idx connect rename_stage.io.dec_uops[1].ldq_idx, dec_uops[1].ldq_idx connect rename_stage.io.dec_uops[1].rob_idx, dec_uops[1].rob_idx connect rename_stage.io.dec_uops[1].csr_addr, dec_uops[1].csr_addr connect rename_stage.io.dec_uops[1].imm_packed, dec_uops[1].imm_packed connect rename_stage.io.dec_uops[1].taken, dec_uops[1].taken connect rename_stage.io.dec_uops[1].pc_lob, dec_uops[1].pc_lob connect rename_stage.io.dec_uops[1].edge_inst, dec_uops[1].edge_inst connect rename_stage.io.dec_uops[1].ftq_idx, dec_uops[1].ftq_idx connect rename_stage.io.dec_uops[1].br_tag, dec_uops[1].br_tag connect rename_stage.io.dec_uops[1].br_mask, dec_uops[1].br_mask connect rename_stage.io.dec_uops[1].is_sfb, dec_uops[1].is_sfb connect rename_stage.io.dec_uops[1].is_jal, dec_uops[1].is_jal connect rename_stage.io.dec_uops[1].is_jalr, dec_uops[1].is_jalr connect rename_stage.io.dec_uops[1].is_br, dec_uops[1].is_br connect rename_stage.io.dec_uops[1].iw_p2_poisoned, dec_uops[1].iw_p2_poisoned connect rename_stage.io.dec_uops[1].iw_p1_poisoned, dec_uops[1].iw_p1_poisoned connect rename_stage.io.dec_uops[1].iw_state, dec_uops[1].iw_state connect rename_stage.io.dec_uops[1].ctrl.is_std, dec_uops[1].ctrl.is_std connect rename_stage.io.dec_uops[1].ctrl.is_sta, dec_uops[1].ctrl.is_sta connect rename_stage.io.dec_uops[1].ctrl.is_load, dec_uops[1].ctrl.is_load connect rename_stage.io.dec_uops[1].ctrl.csr_cmd, dec_uops[1].ctrl.csr_cmd connect rename_stage.io.dec_uops[1].ctrl.fcn_dw, dec_uops[1].ctrl.fcn_dw connect rename_stage.io.dec_uops[1].ctrl.op_fcn, dec_uops[1].ctrl.op_fcn connect rename_stage.io.dec_uops[1].ctrl.imm_sel, dec_uops[1].ctrl.imm_sel connect rename_stage.io.dec_uops[1].ctrl.op2_sel, dec_uops[1].ctrl.op2_sel connect rename_stage.io.dec_uops[1].ctrl.op1_sel, dec_uops[1].ctrl.op1_sel connect rename_stage.io.dec_uops[1].ctrl.br_type, dec_uops[1].ctrl.br_type connect rename_stage.io.dec_uops[1].fu_code, dec_uops[1].fu_code connect rename_stage.io.dec_uops[1].iq_type, dec_uops[1].iq_type connect rename_stage.io.dec_uops[1].debug_pc, dec_uops[1].debug_pc connect rename_stage.io.dec_uops[1].is_rvc, dec_uops[1].is_rvc connect rename_stage.io.dec_uops[1].debug_inst, dec_uops[1].debug_inst connect rename_stage.io.dec_uops[1].inst, dec_uops[1].inst connect rename_stage.io.dec_uops[1].uopc, dec_uops[1].uopc connect rename_stage.io.dec_uops[2].debug_tsrc, dec_uops[2].debug_tsrc connect rename_stage.io.dec_uops[2].debug_fsrc, dec_uops[2].debug_fsrc connect rename_stage.io.dec_uops[2].bp_xcpt_if, dec_uops[2].bp_xcpt_if connect rename_stage.io.dec_uops[2].bp_debug_if, dec_uops[2].bp_debug_if connect rename_stage.io.dec_uops[2].xcpt_ma_if, dec_uops[2].xcpt_ma_if connect rename_stage.io.dec_uops[2].xcpt_ae_if, dec_uops[2].xcpt_ae_if connect rename_stage.io.dec_uops[2].xcpt_pf_if, dec_uops[2].xcpt_pf_if connect rename_stage.io.dec_uops[2].fp_single, dec_uops[2].fp_single connect rename_stage.io.dec_uops[2].fp_val, dec_uops[2].fp_val connect rename_stage.io.dec_uops[2].frs3_en, dec_uops[2].frs3_en connect rename_stage.io.dec_uops[2].lrs2_rtype, dec_uops[2].lrs2_rtype connect rename_stage.io.dec_uops[2].lrs1_rtype, dec_uops[2].lrs1_rtype connect rename_stage.io.dec_uops[2].dst_rtype, dec_uops[2].dst_rtype connect rename_stage.io.dec_uops[2].ldst_val, dec_uops[2].ldst_val connect rename_stage.io.dec_uops[2].lrs3, dec_uops[2].lrs3 connect rename_stage.io.dec_uops[2].lrs2, dec_uops[2].lrs2 connect rename_stage.io.dec_uops[2].lrs1, dec_uops[2].lrs1 connect rename_stage.io.dec_uops[2].ldst, dec_uops[2].ldst connect rename_stage.io.dec_uops[2].ldst_is_rs1, dec_uops[2].ldst_is_rs1 connect rename_stage.io.dec_uops[2].flush_on_commit, dec_uops[2].flush_on_commit connect rename_stage.io.dec_uops[2].is_unique, dec_uops[2].is_unique connect rename_stage.io.dec_uops[2].is_sys_pc2epc, dec_uops[2].is_sys_pc2epc connect rename_stage.io.dec_uops[2].uses_stq, dec_uops[2].uses_stq connect rename_stage.io.dec_uops[2].uses_ldq, dec_uops[2].uses_ldq connect rename_stage.io.dec_uops[2].is_amo, dec_uops[2].is_amo connect rename_stage.io.dec_uops[2].is_fencei, dec_uops[2].is_fencei connect rename_stage.io.dec_uops[2].is_fence, dec_uops[2].is_fence connect rename_stage.io.dec_uops[2].mem_signed, dec_uops[2].mem_signed connect rename_stage.io.dec_uops[2].mem_size, dec_uops[2].mem_size connect rename_stage.io.dec_uops[2].mem_cmd, dec_uops[2].mem_cmd connect rename_stage.io.dec_uops[2].bypassable, dec_uops[2].bypassable connect rename_stage.io.dec_uops[2].exc_cause, dec_uops[2].exc_cause connect rename_stage.io.dec_uops[2].exception, dec_uops[2].exception connect rename_stage.io.dec_uops[2].stale_pdst, dec_uops[2].stale_pdst connect rename_stage.io.dec_uops[2].ppred_busy, dec_uops[2].ppred_busy connect rename_stage.io.dec_uops[2].prs3_busy, dec_uops[2].prs3_busy connect rename_stage.io.dec_uops[2].prs2_busy, dec_uops[2].prs2_busy connect rename_stage.io.dec_uops[2].prs1_busy, dec_uops[2].prs1_busy connect rename_stage.io.dec_uops[2].ppred, dec_uops[2].ppred connect rename_stage.io.dec_uops[2].prs3, dec_uops[2].prs3 connect rename_stage.io.dec_uops[2].prs2, dec_uops[2].prs2 connect rename_stage.io.dec_uops[2].prs1, dec_uops[2].prs1 connect rename_stage.io.dec_uops[2].pdst, dec_uops[2].pdst connect rename_stage.io.dec_uops[2].rxq_idx, dec_uops[2].rxq_idx connect rename_stage.io.dec_uops[2].stq_idx, dec_uops[2].stq_idx connect rename_stage.io.dec_uops[2].ldq_idx, dec_uops[2].ldq_idx connect rename_stage.io.dec_uops[2].rob_idx, dec_uops[2].rob_idx connect rename_stage.io.dec_uops[2].csr_addr, dec_uops[2].csr_addr connect rename_stage.io.dec_uops[2].imm_packed, dec_uops[2].imm_packed connect rename_stage.io.dec_uops[2].taken, dec_uops[2].taken connect rename_stage.io.dec_uops[2].pc_lob, dec_uops[2].pc_lob connect rename_stage.io.dec_uops[2].edge_inst, dec_uops[2].edge_inst connect rename_stage.io.dec_uops[2].ftq_idx, dec_uops[2].ftq_idx connect rename_stage.io.dec_uops[2].br_tag, dec_uops[2].br_tag connect rename_stage.io.dec_uops[2].br_mask, dec_uops[2].br_mask connect rename_stage.io.dec_uops[2].is_sfb, dec_uops[2].is_sfb connect rename_stage.io.dec_uops[2].is_jal, dec_uops[2].is_jal connect rename_stage.io.dec_uops[2].is_jalr, dec_uops[2].is_jalr connect rename_stage.io.dec_uops[2].is_br, dec_uops[2].is_br connect rename_stage.io.dec_uops[2].iw_p2_poisoned, dec_uops[2].iw_p2_poisoned connect rename_stage.io.dec_uops[2].iw_p1_poisoned, dec_uops[2].iw_p1_poisoned connect rename_stage.io.dec_uops[2].iw_state, dec_uops[2].iw_state connect rename_stage.io.dec_uops[2].ctrl.is_std, dec_uops[2].ctrl.is_std connect rename_stage.io.dec_uops[2].ctrl.is_sta, dec_uops[2].ctrl.is_sta connect rename_stage.io.dec_uops[2].ctrl.is_load, dec_uops[2].ctrl.is_load connect rename_stage.io.dec_uops[2].ctrl.csr_cmd, dec_uops[2].ctrl.csr_cmd connect rename_stage.io.dec_uops[2].ctrl.fcn_dw, dec_uops[2].ctrl.fcn_dw connect rename_stage.io.dec_uops[2].ctrl.op_fcn, dec_uops[2].ctrl.op_fcn connect rename_stage.io.dec_uops[2].ctrl.imm_sel, dec_uops[2].ctrl.imm_sel connect rename_stage.io.dec_uops[2].ctrl.op2_sel, dec_uops[2].ctrl.op2_sel connect rename_stage.io.dec_uops[2].ctrl.op1_sel, dec_uops[2].ctrl.op1_sel connect rename_stage.io.dec_uops[2].ctrl.br_type, dec_uops[2].ctrl.br_type connect rename_stage.io.dec_uops[2].fu_code, dec_uops[2].fu_code connect rename_stage.io.dec_uops[2].iq_type, dec_uops[2].iq_type connect rename_stage.io.dec_uops[2].debug_pc, dec_uops[2].debug_pc connect rename_stage.io.dec_uops[2].is_rvc, dec_uops[2].is_rvc connect rename_stage.io.dec_uops[2].debug_inst, dec_uops[2].debug_inst connect rename_stage.io.dec_uops[2].inst, dec_uops[2].inst connect rename_stage.io.dec_uops[2].uopc, dec_uops[2].uopc connect rename_stage.io.dis_fire[0], dis_fire[0] connect rename_stage.io.dis_fire[1], dis_fire[1] connect rename_stage.io.dis_fire[2], dis_fire[2] connect rename_stage.io.dis_ready, dis_ready connect rename_stage.io.com_valids[0], rob.io.commit.valids[0] connect rename_stage.io.com_valids[1], rob.io.commit.valids[1] connect rename_stage.io.com_valids[2], rob.io.commit.valids[2] connect rename_stage.io.com_uops[0].debug_tsrc, rob.io.commit.uops[0].debug_tsrc connect rename_stage.io.com_uops[0].debug_fsrc, rob.io.commit.uops[0].debug_fsrc connect rename_stage.io.com_uops[0].bp_xcpt_if, rob.io.commit.uops[0].bp_xcpt_if connect rename_stage.io.com_uops[0].bp_debug_if, rob.io.commit.uops[0].bp_debug_if connect rename_stage.io.com_uops[0].xcpt_ma_if, rob.io.commit.uops[0].xcpt_ma_if connect rename_stage.io.com_uops[0].xcpt_ae_if, rob.io.commit.uops[0].xcpt_ae_if connect rename_stage.io.com_uops[0].xcpt_pf_if, rob.io.commit.uops[0].xcpt_pf_if connect rename_stage.io.com_uops[0].fp_single, rob.io.commit.uops[0].fp_single connect rename_stage.io.com_uops[0].fp_val, rob.io.commit.uops[0].fp_val connect rename_stage.io.com_uops[0].frs3_en, rob.io.commit.uops[0].frs3_en connect rename_stage.io.com_uops[0].lrs2_rtype, rob.io.commit.uops[0].lrs2_rtype connect rename_stage.io.com_uops[0].lrs1_rtype, rob.io.commit.uops[0].lrs1_rtype connect rename_stage.io.com_uops[0].dst_rtype, rob.io.commit.uops[0].dst_rtype connect rename_stage.io.com_uops[0].ldst_val, rob.io.commit.uops[0].ldst_val connect rename_stage.io.com_uops[0].lrs3, rob.io.commit.uops[0].lrs3 connect rename_stage.io.com_uops[0].lrs2, rob.io.commit.uops[0].lrs2 connect rename_stage.io.com_uops[0].lrs1, rob.io.commit.uops[0].lrs1 connect rename_stage.io.com_uops[0].ldst, rob.io.commit.uops[0].ldst connect rename_stage.io.com_uops[0].ldst_is_rs1, rob.io.commit.uops[0].ldst_is_rs1 connect rename_stage.io.com_uops[0].flush_on_commit, rob.io.commit.uops[0].flush_on_commit connect rename_stage.io.com_uops[0].is_unique, rob.io.commit.uops[0].is_unique connect rename_stage.io.com_uops[0].is_sys_pc2epc, rob.io.commit.uops[0].is_sys_pc2epc connect rename_stage.io.com_uops[0].uses_stq, rob.io.commit.uops[0].uses_stq connect rename_stage.io.com_uops[0].uses_ldq, rob.io.commit.uops[0].uses_ldq connect rename_stage.io.com_uops[0].is_amo, rob.io.commit.uops[0].is_amo connect rename_stage.io.com_uops[0].is_fencei, rob.io.commit.uops[0].is_fencei connect rename_stage.io.com_uops[0].is_fence, rob.io.commit.uops[0].is_fence connect rename_stage.io.com_uops[0].mem_signed, rob.io.commit.uops[0].mem_signed connect rename_stage.io.com_uops[0].mem_size, rob.io.commit.uops[0].mem_size connect rename_stage.io.com_uops[0].mem_cmd, rob.io.commit.uops[0].mem_cmd connect rename_stage.io.com_uops[0].bypassable, rob.io.commit.uops[0].bypassable connect rename_stage.io.com_uops[0].exc_cause, rob.io.commit.uops[0].exc_cause connect rename_stage.io.com_uops[0].exception, rob.io.commit.uops[0].exception connect rename_stage.io.com_uops[0].stale_pdst, rob.io.commit.uops[0].stale_pdst connect rename_stage.io.com_uops[0].ppred_busy, rob.io.commit.uops[0].ppred_busy connect rename_stage.io.com_uops[0].prs3_busy, rob.io.commit.uops[0].prs3_busy connect rename_stage.io.com_uops[0].prs2_busy, rob.io.commit.uops[0].prs2_busy connect rename_stage.io.com_uops[0].prs1_busy, rob.io.commit.uops[0].prs1_busy connect rename_stage.io.com_uops[0].ppred, rob.io.commit.uops[0].ppred connect rename_stage.io.com_uops[0].prs3, rob.io.commit.uops[0].prs3 connect rename_stage.io.com_uops[0].prs2, rob.io.commit.uops[0].prs2 connect rename_stage.io.com_uops[0].prs1, rob.io.commit.uops[0].prs1 connect rename_stage.io.com_uops[0].pdst, rob.io.commit.uops[0].pdst connect rename_stage.io.com_uops[0].rxq_idx, rob.io.commit.uops[0].rxq_idx connect rename_stage.io.com_uops[0].stq_idx, rob.io.commit.uops[0].stq_idx connect rename_stage.io.com_uops[0].ldq_idx, rob.io.commit.uops[0].ldq_idx connect rename_stage.io.com_uops[0].rob_idx, rob.io.commit.uops[0].rob_idx connect rename_stage.io.com_uops[0].csr_addr, rob.io.commit.uops[0].csr_addr connect rename_stage.io.com_uops[0].imm_packed, rob.io.commit.uops[0].imm_packed connect rename_stage.io.com_uops[0].taken, rob.io.commit.uops[0].taken connect rename_stage.io.com_uops[0].pc_lob, rob.io.commit.uops[0].pc_lob connect rename_stage.io.com_uops[0].edge_inst, rob.io.commit.uops[0].edge_inst connect rename_stage.io.com_uops[0].ftq_idx, rob.io.commit.uops[0].ftq_idx connect rename_stage.io.com_uops[0].br_tag, rob.io.commit.uops[0].br_tag connect rename_stage.io.com_uops[0].br_mask, rob.io.commit.uops[0].br_mask connect rename_stage.io.com_uops[0].is_sfb, rob.io.commit.uops[0].is_sfb connect rename_stage.io.com_uops[0].is_jal, rob.io.commit.uops[0].is_jal connect rename_stage.io.com_uops[0].is_jalr, rob.io.commit.uops[0].is_jalr connect rename_stage.io.com_uops[0].is_br, rob.io.commit.uops[0].is_br connect rename_stage.io.com_uops[0].iw_p2_poisoned, rob.io.commit.uops[0].iw_p2_poisoned connect rename_stage.io.com_uops[0].iw_p1_poisoned, rob.io.commit.uops[0].iw_p1_poisoned connect rename_stage.io.com_uops[0].iw_state, rob.io.commit.uops[0].iw_state connect rename_stage.io.com_uops[0].ctrl.is_std, rob.io.commit.uops[0].ctrl.is_std connect rename_stage.io.com_uops[0].ctrl.is_sta, rob.io.commit.uops[0].ctrl.is_sta connect rename_stage.io.com_uops[0].ctrl.is_load, rob.io.commit.uops[0].ctrl.is_load connect rename_stage.io.com_uops[0].ctrl.csr_cmd, rob.io.commit.uops[0].ctrl.csr_cmd connect rename_stage.io.com_uops[0].ctrl.fcn_dw, rob.io.commit.uops[0].ctrl.fcn_dw connect rename_stage.io.com_uops[0].ctrl.op_fcn, rob.io.commit.uops[0].ctrl.op_fcn connect rename_stage.io.com_uops[0].ctrl.imm_sel, rob.io.commit.uops[0].ctrl.imm_sel connect rename_stage.io.com_uops[0].ctrl.op2_sel, rob.io.commit.uops[0].ctrl.op2_sel connect rename_stage.io.com_uops[0].ctrl.op1_sel, rob.io.commit.uops[0].ctrl.op1_sel connect rename_stage.io.com_uops[0].ctrl.br_type, rob.io.commit.uops[0].ctrl.br_type connect rename_stage.io.com_uops[0].fu_code, rob.io.commit.uops[0].fu_code connect rename_stage.io.com_uops[0].iq_type, rob.io.commit.uops[0].iq_type connect rename_stage.io.com_uops[0].debug_pc, rob.io.commit.uops[0].debug_pc connect rename_stage.io.com_uops[0].is_rvc, rob.io.commit.uops[0].is_rvc connect rename_stage.io.com_uops[0].debug_inst, rob.io.commit.uops[0].debug_inst connect rename_stage.io.com_uops[0].inst, rob.io.commit.uops[0].inst connect rename_stage.io.com_uops[0].uopc, rob.io.commit.uops[0].uopc connect rename_stage.io.com_uops[1].debug_tsrc, rob.io.commit.uops[1].debug_tsrc connect rename_stage.io.com_uops[1].debug_fsrc, rob.io.commit.uops[1].debug_fsrc connect rename_stage.io.com_uops[1].bp_xcpt_if, rob.io.commit.uops[1].bp_xcpt_if connect rename_stage.io.com_uops[1].bp_debug_if, rob.io.commit.uops[1].bp_debug_if connect rename_stage.io.com_uops[1].xcpt_ma_if, rob.io.commit.uops[1].xcpt_ma_if connect rename_stage.io.com_uops[1].xcpt_ae_if, rob.io.commit.uops[1].xcpt_ae_if connect rename_stage.io.com_uops[1].xcpt_pf_if, rob.io.commit.uops[1].xcpt_pf_if connect rename_stage.io.com_uops[1].fp_single, rob.io.commit.uops[1].fp_single connect rename_stage.io.com_uops[1].fp_val, rob.io.commit.uops[1].fp_val connect rename_stage.io.com_uops[1].frs3_en, rob.io.commit.uops[1].frs3_en connect rename_stage.io.com_uops[1].lrs2_rtype, rob.io.commit.uops[1].lrs2_rtype connect rename_stage.io.com_uops[1].lrs1_rtype, rob.io.commit.uops[1].lrs1_rtype connect rename_stage.io.com_uops[1].dst_rtype, rob.io.commit.uops[1].dst_rtype connect rename_stage.io.com_uops[1].ldst_val, rob.io.commit.uops[1].ldst_val connect rename_stage.io.com_uops[1].lrs3, rob.io.commit.uops[1].lrs3 connect rename_stage.io.com_uops[1].lrs2, rob.io.commit.uops[1].lrs2 connect rename_stage.io.com_uops[1].lrs1, rob.io.commit.uops[1].lrs1 connect rename_stage.io.com_uops[1].ldst, rob.io.commit.uops[1].ldst connect rename_stage.io.com_uops[1].ldst_is_rs1, rob.io.commit.uops[1].ldst_is_rs1 connect rename_stage.io.com_uops[1].flush_on_commit, rob.io.commit.uops[1].flush_on_commit connect rename_stage.io.com_uops[1].is_unique, rob.io.commit.uops[1].is_unique connect rename_stage.io.com_uops[1].is_sys_pc2epc, rob.io.commit.uops[1].is_sys_pc2epc connect rename_stage.io.com_uops[1].uses_stq, rob.io.commit.uops[1].uses_stq connect rename_stage.io.com_uops[1].uses_ldq, rob.io.commit.uops[1].uses_ldq connect rename_stage.io.com_uops[1].is_amo, rob.io.commit.uops[1].is_amo connect rename_stage.io.com_uops[1].is_fencei, rob.io.commit.uops[1].is_fencei connect rename_stage.io.com_uops[1].is_fence, rob.io.commit.uops[1].is_fence connect rename_stage.io.com_uops[1].mem_signed, rob.io.commit.uops[1].mem_signed connect rename_stage.io.com_uops[1].mem_size, rob.io.commit.uops[1].mem_size connect rename_stage.io.com_uops[1].mem_cmd, rob.io.commit.uops[1].mem_cmd connect rename_stage.io.com_uops[1].bypassable, rob.io.commit.uops[1].bypassable connect rename_stage.io.com_uops[1].exc_cause, rob.io.commit.uops[1].exc_cause connect rename_stage.io.com_uops[1].exception, rob.io.commit.uops[1].exception connect rename_stage.io.com_uops[1].stale_pdst, rob.io.commit.uops[1].stale_pdst connect rename_stage.io.com_uops[1].ppred_busy, rob.io.commit.uops[1].ppred_busy connect rename_stage.io.com_uops[1].prs3_busy, rob.io.commit.uops[1].prs3_busy connect rename_stage.io.com_uops[1].prs2_busy, rob.io.commit.uops[1].prs2_busy connect rename_stage.io.com_uops[1].prs1_busy, rob.io.commit.uops[1].prs1_busy connect rename_stage.io.com_uops[1].ppred, rob.io.commit.uops[1].ppred connect rename_stage.io.com_uops[1].prs3, rob.io.commit.uops[1].prs3 connect rename_stage.io.com_uops[1].prs2, rob.io.commit.uops[1].prs2 connect rename_stage.io.com_uops[1].prs1, rob.io.commit.uops[1].prs1 connect rename_stage.io.com_uops[1].pdst, rob.io.commit.uops[1].pdst connect rename_stage.io.com_uops[1].rxq_idx, rob.io.commit.uops[1].rxq_idx connect rename_stage.io.com_uops[1].stq_idx, rob.io.commit.uops[1].stq_idx connect rename_stage.io.com_uops[1].ldq_idx, rob.io.commit.uops[1].ldq_idx connect rename_stage.io.com_uops[1].rob_idx, rob.io.commit.uops[1].rob_idx connect rename_stage.io.com_uops[1].csr_addr, rob.io.commit.uops[1].csr_addr connect rename_stage.io.com_uops[1].imm_packed, rob.io.commit.uops[1].imm_packed connect rename_stage.io.com_uops[1].taken, rob.io.commit.uops[1].taken connect rename_stage.io.com_uops[1].pc_lob, rob.io.commit.uops[1].pc_lob connect rename_stage.io.com_uops[1].edge_inst, rob.io.commit.uops[1].edge_inst connect rename_stage.io.com_uops[1].ftq_idx, rob.io.commit.uops[1].ftq_idx connect rename_stage.io.com_uops[1].br_tag, rob.io.commit.uops[1].br_tag connect rename_stage.io.com_uops[1].br_mask, rob.io.commit.uops[1].br_mask connect rename_stage.io.com_uops[1].is_sfb, rob.io.commit.uops[1].is_sfb connect rename_stage.io.com_uops[1].is_jal, rob.io.commit.uops[1].is_jal connect rename_stage.io.com_uops[1].is_jalr, rob.io.commit.uops[1].is_jalr connect rename_stage.io.com_uops[1].is_br, rob.io.commit.uops[1].is_br connect rename_stage.io.com_uops[1].iw_p2_poisoned, rob.io.commit.uops[1].iw_p2_poisoned connect rename_stage.io.com_uops[1].iw_p1_poisoned, rob.io.commit.uops[1].iw_p1_poisoned connect rename_stage.io.com_uops[1].iw_state, rob.io.commit.uops[1].iw_state connect rename_stage.io.com_uops[1].ctrl.is_std, rob.io.commit.uops[1].ctrl.is_std connect rename_stage.io.com_uops[1].ctrl.is_sta, rob.io.commit.uops[1].ctrl.is_sta connect rename_stage.io.com_uops[1].ctrl.is_load, rob.io.commit.uops[1].ctrl.is_load connect rename_stage.io.com_uops[1].ctrl.csr_cmd, rob.io.commit.uops[1].ctrl.csr_cmd connect rename_stage.io.com_uops[1].ctrl.fcn_dw, rob.io.commit.uops[1].ctrl.fcn_dw connect rename_stage.io.com_uops[1].ctrl.op_fcn, rob.io.commit.uops[1].ctrl.op_fcn connect rename_stage.io.com_uops[1].ctrl.imm_sel, rob.io.commit.uops[1].ctrl.imm_sel connect rename_stage.io.com_uops[1].ctrl.op2_sel, rob.io.commit.uops[1].ctrl.op2_sel connect rename_stage.io.com_uops[1].ctrl.op1_sel, rob.io.commit.uops[1].ctrl.op1_sel connect rename_stage.io.com_uops[1].ctrl.br_type, rob.io.commit.uops[1].ctrl.br_type connect rename_stage.io.com_uops[1].fu_code, rob.io.commit.uops[1].fu_code connect rename_stage.io.com_uops[1].iq_type, rob.io.commit.uops[1].iq_type connect rename_stage.io.com_uops[1].debug_pc, rob.io.commit.uops[1].debug_pc connect rename_stage.io.com_uops[1].is_rvc, rob.io.commit.uops[1].is_rvc connect rename_stage.io.com_uops[1].debug_inst, rob.io.commit.uops[1].debug_inst connect rename_stage.io.com_uops[1].inst, rob.io.commit.uops[1].inst connect rename_stage.io.com_uops[1].uopc, rob.io.commit.uops[1].uopc connect rename_stage.io.com_uops[2].debug_tsrc, rob.io.commit.uops[2].debug_tsrc connect rename_stage.io.com_uops[2].debug_fsrc, rob.io.commit.uops[2].debug_fsrc connect rename_stage.io.com_uops[2].bp_xcpt_if, rob.io.commit.uops[2].bp_xcpt_if connect rename_stage.io.com_uops[2].bp_debug_if, rob.io.commit.uops[2].bp_debug_if connect rename_stage.io.com_uops[2].xcpt_ma_if, rob.io.commit.uops[2].xcpt_ma_if connect rename_stage.io.com_uops[2].xcpt_ae_if, rob.io.commit.uops[2].xcpt_ae_if connect rename_stage.io.com_uops[2].xcpt_pf_if, rob.io.commit.uops[2].xcpt_pf_if connect rename_stage.io.com_uops[2].fp_single, rob.io.commit.uops[2].fp_single connect rename_stage.io.com_uops[2].fp_val, rob.io.commit.uops[2].fp_val connect rename_stage.io.com_uops[2].frs3_en, rob.io.commit.uops[2].frs3_en connect rename_stage.io.com_uops[2].lrs2_rtype, rob.io.commit.uops[2].lrs2_rtype connect rename_stage.io.com_uops[2].lrs1_rtype, rob.io.commit.uops[2].lrs1_rtype connect rename_stage.io.com_uops[2].dst_rtype, rob.io.commit.uops[2].dst_rtype connect rename_stage.io.com_uops[2].ldst_val, rob.io.commit.uops[2].ldst_val connect rename_stage.io.com_uops[2].lrs3, rob.io.commit.uops[2].lrs3 connect rename_stage.io.com_uops[2].lrs2, rob.io.commit.uops[2].lrs2 connect rename_stage.io.com_uops[2].lrs1, rob.io.commit.uops[2].lrs1 connect rename_stage.io.com_uops[2].ldst, rob.io.commit.uops[2].ldst connect rename_stage.io.com_uops[2].ldst_is_rs1, rob.io.commit.uops[2].ldst_is_rs1 connect rename_stage.io.com_uops[2].flush_on_commit, rob.io.commit.uops[2].flush_on_commit connect rename_stage.io.com_uops[2].is_unique, rob.io.commit.uops[2].is_unique connect rename_stage.io.com_uops[2].is_sys_pc2epc, rob.io.commit.uops[2].is_sys_pc2epc connect rename_stage.io.com_uops[2].uses_stq, rob.io.commit.uops[2].uses_stq connect rename_stage.io.com_uops[2].uses_ldq, rob.io.commit.uops[2].uses_ldq connect rename_stage.io.com_uops[2].is_amo, rob.io.commit.uops[2].is_amo connect rename_stage.io.com_uops[2].is_fencei, rob.io.commit.uops[2].is_fencei connect rename_stage.io.com_uops[2].is_fence, rob.io.commit.uops[2].is_fence connect rename_stage.io.com_uops[2].mem_signed, rob.io.commit.uops[2].mem_signed connect rename_stage.io.com_uops[2].mem_size, rob.io.commit.uops[2].mem_size connect rename_stage.io.com_uops[2].mem_cmd, rob.io.commit.uops[2].mem_cmd connect rename_stage.io.com_uops[2].bypassable, rob.io.commit.uops[2].bypassable connect rename_stage.io.com_uops[2].exc_cause, rob.io.commit.uops[2].exc_cause connect rename_stage.io.com_uops[2].exception, rob.io.commit.uops[2].exception connect rename_stage.io.com_uops[2].stale_pdst, rob.io.commit.uops[2].stale_pdst connect rename_stage.io.com_uops[2].ppred_busy, rob.io.commit.uops[2].ppred_busy connect rename_stage.io.com_uops[2].prs3_busy, rob.io.commit.uops[2].prs3_busy connect rename_stage.io.com_uops[2].prs2_busy, rob.io.commit.uops[2].prs2_busy connect rename_stage.io.com_uops[2].prs1_busy, rob.io.commit.uops[2].prs1_busy connect rename_stage.io.com_uops[2].ppred, rob.io.commit.uops[2].ppred connect rename_stage.io.com_uops[2].prs3, rob.io.commit.uops[2].prs3 connect rename_stage.io.com_uops[2].prs2, rob.io.commit.uops[2].prs2 connect rename_stage.io.com_uops[2].prs1, rob.io.commit.uops[2].prs1 connect rename_stage.io.com_uops[2].pdst, rob.io.commit.uops[2].pdst connect rename_stage.io.com_uops[2].rxq_idx, rob.io.commit.uops[2].rxq_idx connect rename_stage.io.com_uops[2].stq_idx, rob.io.commit.uops[2].stq_idx connect rename_stage.io.com_uops[2].ldq_idx, rob.io.commit.uops[2].ldq_idx connect rename_stage.io.com_uops[2].rob_idx, rob.io.commit.uops[2].rob_idx connect rename_stage.io.com_uops[2].csr_addr, rob.io.commit.uops[2].csr_addr connect rename_stage.io.com_uops[2].imm_packed, rob.io.commit.uops[2].imm_packed connect rename_stage.io.com_uops[2].taken, rob.io.commit.uops[2].taken connect rename_stage.io.com_uops[2].pc_lob, rob.io.commit.uops[2].pc_lob connect rename_stage.io.com_uops[2].edge_inst, rob.io.commit.uops[2].edge_inst connect rename_stage.io.com_uops[2].ftq_idx, rob.io.commit.uops[2].ftq_idx connect rename_stage.io.com_uops[2].br_tag, rob.io.commit.uops[2].br_tag connect rename_stage.io.com_uops[2].br_mask, rob.io.commit.uops[2].br_mask connect rename_stage.io.com_uops[2].is_sfb, rob.io.commit.uops[2].is_sfb connect rename_stage.io.com_uops[2].is_jal, rob.io.commit.uops[2].is_jal connect rename_stage.io.com_uops[2].is_jalr, rob.io.commit.uops[2].is_jalr connect rename_stage.io.com_uops[2].is_br, rob.io.commit.uops[2].is_br connect rename_stage.io.com_uops[2].iw_p2_poisoned, rob.io.commit.uops[2].iw_p2_poisoned connect rename_stage.io.com_uops[2].iw_p1_poisoned, rob.io.commit.uops[2].iw_p1_poisoned connect rename_stage.io.com_uops[2].iw_state, rob.io.commit.uops[2].iw_state connect rename_stage.io.com_uops[2].ctrl.is_std, rob.io.commit.uops[2].ctrl.is_std connect rename_stage.io.com_uops[2].ctrl.is_sta, rob.io.commit.uops[2].ctrl.is_sta connect rename_stage.io.com_uops[2].ctrl.is_load, rob.io.commit.uops[2].ctrl.is_load connect rename_stage.io.com_uops[2].ctrl.csr_cmd, rob.io.commit.uops[2].ctrl.csr_cmd connect rename_stage.io.com_uops[2].ctrl.fcn_dw, rob.io.commit.uops[2].ctrl.fcn_dw connect rename_stage.io.com_uops[2].ctrl.op_fcn, rob.io.commit.uops[2].ctrl.op_fcn connect rename_stage.io.com_uops[2].ctrl.imm_sel, rob.io.commit.uops[2].ctrl.imm_sel connect rename_stage.io.com_uops[2].ctrl.op2_sel, rob.io.commit.uops[2].ctrl.op2_sel connect rename_stage.io.com_uops[2].ctrl.op1_sel, rob.io.commit.uops[2].ctrl.op1_sel connect rename_stage.io.com_uops[2].ctrl.br_type, rob.io.commit.uops[2].ctrl.br_type connect rename_stage.io.com_uops[2].fu_code, rob.io.commit.uops[2].fu_code connect rename_stage.io.com_uops[2].iq_type, rob.io.commit.uops[2].iq_type connect rename_stage.io.com_uops[2].debug_pc, rob.io.commit.uops[2].debug_pc connect rename_stage.io.com_uops[2].is_rvc, rob.io.commit.uops[2].is_rvc connect rename_stage.io.com_uops[2].debug_inst, rob.io.commit.uops[2].debug_inst connect rename_stage.io.com_uops[2].inst, rob.io.commit.uops[2].inst connect rename_stage.io.com_uops[2].uopc, rob.io.commit.uops[2].uopc connect rename_stage.io.rbk_valids[0], rob.io.commit.rbk_valids[0] connect rename_stage.io.rbk_valids[1], rob.io.commit.rbk_valids[1] connect rename_stage.io.rbk_valids[2], rob.io.commit.rbk_valids[2] connect rename_stage.io.rollback, rob.io.commit.rollback connect fp_rename_stage.io.kill, io.ifu.redirect_flush connect fp_rename_stage.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect fp_rename_stage.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect fp_rename_stage.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect fp_rename_stage.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect fp_rename_stage.io.brupdate.b2.taken, brupdate.b2.taken connect fp_rename_stage.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect fp_rename_stage.io.brupdate.b2.valid, brupdate.b2.valid connect fp_rename_stage.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect fp_rename_stage.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect fp_rename_stage.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect fp_rename_stage.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect fp_rename_stage.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect fp_rename_stage.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect fp_rename_stage.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect fp_rename_stage.io.brupdate.b2.uop.fp_single, brupdate.b2.uop.fp_single connect fp_rename_stage.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect fp_rename_stage.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect fp_rename_stage.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect fp_rename_stage.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect fp_rename_stage.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect fp_rename_stage.io.brupdate.b2.uop.ldst_val, brupdate.b2.uop.ldst_val connect fp_rename_stage.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect fp_rename_stage.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect fp_rename_stage.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect fp_rename_stage.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect fp_rename_stage.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect fp_rename_stage.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect fp_rename_stage.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect fp_rename_stage.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect fp_rename_stage.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect fp_rename_stage.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect fp_rename_stage.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect fp_rename_stage.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect fp_rename_stage.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect fp_rename_stage.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect fp_rename_stage.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect fp_rename_stage.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect fp_rename_stage.io.brupdate.b2.uop.bypassable, brupdate.b2.uop.bypassable connect fp_rename_stage.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect fp_rename_stage.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect fp_rename_stage.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect fp_rename_stage.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect fp_rename_stage.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect fp_rename_stage.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect fp_rename_stage.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect fp_rename_stage.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect fp_rename_stage.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect fp_rename_stage.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect fp_rename_stage.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect fp_rename_stage.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect fp_rename_stage.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect fp_rename_stage.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect fp_rename_stage.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect fp_rename_stage.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect fp_rename_stage.io.brupdate.b2.uop.csr_addr, brupdate.b2.uop.csr_addr connect fp_rename_stage.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect fp_rename_stage.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect fp_rename_stage.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect fp_rename_stage.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect fp_rename_stage.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect fp_rename_stage.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect fp_rename_stage.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect fp_rename_stage.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect fp_rename_stage.io.brupdate.b2.uop.is_jal, brupdate.b2.uop.is_jal connect fp_rename_stage.io.brupdate.b2.uop.is_jalr, brupdate.b2.uop.is_jalr connect fp_rename_stage.io.brupdate.b2.uop.is_br, brupdate.b2.uop.is_br connect fp_rename_stage.io.brupdate.b2.uop.iw_p2_poisoned, brupdate.b2.uop.iw_p2_poisoned connect fp_rename_stage.io.brupdate.b2.uop.iw_p1_poisoned, brupdate.b2.uop.iw_p1_poisoned connect fp_rename_stage.io.brupdate.b2.uop.iw_state, brupdate.b2.uop.iw_state connect fp_rename_stage.io.brupdate.b2.uop.ctrl.is_std, brupdate.b2.uop.ctrl.is_std connect fp_rename_stage.io.brupdate.b2.uop.ctrl.is_sta, brupdate.b2.uop.ctrl.is_sta connect fp_rename_stage.io.brupdate.b2.uop.ctrl.is_load, brupdate.b2.uop.ctrl.is_load connect fp_rename_stage.io.brupdate.b2.uop.ctrl.csr_cmd, brupdate.b2.uop.ctrl.csr_cmd connect fp_rename_stage.io.brupdate.b2.uop.ctrl.fcn_dw, brupdate.b2.uop.ctrl.fcn_dw connect fp_rename_stage.io.brupdate.b2.uop.ctrl.op_fcn, brupdate.b2.uop.ctrl.op_fcn connect fp_rename_stage.io.brupdate.b2.uop.ctrl.imm_sel, brupdate.b2.uop.ctrl.imm_sel connect fp_rename_stage.io.brupdate.b2.uop.ctrl.op2_sel, brupdate.b2.uop.ctrl.op2_sel connect fp_rename_stage.io.brupdate.b2.uop.ctrl.op1_sel, brupdate.b2.uop.ctrl.op1_sel connect fp_rename_stage.io.brupdate.b2.uop.ctrl.br_type, brupdate.b2.uop.ctrl.br_type connect fp_rename_stage.io.brupdate.b2.uop.fu_code, brupdate.b2.uop.fu_code connect fp_rename_stage.io.brupdate.b2.uop.iq_type, brupdate.b2.uop.iq_type connect fp_rename_stage.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect fp_rename_stage.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect fp_rename_stage.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect fp_rename_stage.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect fp_rename_stage.io.brupdate.b2.uop.uopc, brupdate.b2.uop.uopc connect fp_rename_stage.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect fp_rename_stage.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect fp_rename_stage.io.debug_rob_empty, rob.io.empty connect fp_rename_stage.io.dec_fire[0], dec_fire[0] connect fp_rename_stage.io.dec_fire[1], dec_fire[1] connect fp_rename_stage.io.dec_fire[2], dec_fire[2] connect fp_rename_stage.io.dec_uops[0].debug_tsrc, dec_uops[0].debug_tsrc connect fp_rename_stage.io.dec_uops[0].debug_fsrc, dec_uops[0].debug_fsrc connect fp_rename_stage.io.dec_uops[0].bp_xcpt_if, dec_uops[0].bp_xcpt_if connect fp_rename_stage.io.dec_uops[0].bp_debug_if, dec_uops[0].bp_debug_if connect fp_rename_stage.io.dec_uops[0].xcpt_ma_if, dec_uops[0].xcpt_ma_if connect fp_rename_stage.io.dec_uops[0].xcpt_ae_if, dec_uops[0].xcpt_ae_if connect fp_rename_stage.io.dec_uops[0].xcpt_pf_if, dec_uops[0].xcpt_pf_if connect fp_rename_stage.io.dec_uops[0].fp_single, dec_uops[0].fp_single connect fp_rename_stage.io.dec_uops[0].fp_val, dec_uops[0].fp_val connect fp_rename_stage.io.dec_uops[0].frs3_en, dec_uops[0].frs3_en connect fp_rename_stage.io.dec_uops[0].lrs2_rtype, dec_uops[0].lrs2_rtype connect fp_rename_stage.io.dec_uops[0].lrs1_rtype, dec_uops[0].lrs1_rtype connect fp_rename_stage.io.dec_uops[0].dst_rtype, dec_uops[0].dst_rtype connect fp_rename_stage.io.dec_uops[0].ldst_val, dec_uops[0].ldst_val connect fp_rename_stage.io.dec_uops[0].lrs3, dec_uops[0].lrs3 connect fp_rename_stage.io.dec_uops[0].lrs2, dec_uops[0].lrs2 connect fp_rename_stage.io.dec_uops[0].lrs1, dec_uops[0].lrs1 connect fp_rename_stage.io.dec_uops[0].ldst, dec_uops[0].ldst connect fp_rename_stage.io.dec_uops[0].ldst_is_rs1, dec_uops[0].ldst_is_rs1 connect fp_rename_stage.io.dec_uops[0].flush_on_commit, dec_uops[0].flush_on_commit connect fp_rename_stage.io.dec_uops[0].is_unique, dec_uops[0].is_unique connect fp_rename_stage.io.dec_uops[0].is_sys_pc2epc, dec_uops[0].is_sys_pc2epc connect fp_rename_stage.io.dec_uops[0].uses_stq, dec_uops[0].uses_stq connect fp_rename_stage.io.dec_uops[0].uses_ldq, dec_uops[0].uses_ldq connect fp_rename_stage.io.dec_uops[0].is_amo, dec_uops[0].is_amo connect fp_rename_stage.io.dec_uops[0].is_fencei, dec_uops[0].is_fencei connect fp_rename_stage.io.dec_uops[0].is_fence, dec_uops[0].is_fence connect fp_rename_stage.io.dec_uops[0].mem_signed, dec_uops[0].mem_signed connect fp_rename_stage.io.dec_uops[0].mem_size, dec_uops[0].mem_size connect fp_rename_stage.io.dec_uops[0].mem_cmd, dec_uops[0].mem_cmd connect fp_rename_stage.io.dec_uops[0].bypassable, dec_uops[0].bypassable connect fp_rename_stage.io.dec_uops[0].exc_cause, dec_uops[0].exc_cause connect fp_rename_stage.io.dec_uops[0].exception, dec_uops[0].exception connect fp_rename_stage.io.dec_uops[0].stale_pdst, dec_uops[0].stale_pdst connect fp_rename_stage.io.dec_uops[0].ppred_busy, dec_uops[0].ppred_busy connect fp_rename_stage.io.dec_uops[0].prs3_busy, dec_uops[0].prs3_busy connect fp_rename_stage.io.dec_uops[0].prs2_busy, dec_uops[0].prs2_busy connect fp_rename_stage.io.dec_uops[0].prs1_busy, dec_uops[0].prs1_busy connect fp_rename_stage.io.dec_uops[0].ppred, dec_uops[0].ppred connect fp_rename_stage.io.dec_uops[0].prs3, dec_uops[0].prs3 connect fp_rename_stage.io.dec_uops[0].prs2, dec_uops[0].prs2 connect fp_rename_stage.io.dec_uops[0].prs1, dec_uops[0].prs1 connect fp_rename_stage.io.dec_uops[0].pdst, dec_uops[0].pdst connect fp_rename_stage.io.dec_uops[0].rxq_idx, dec_uops[0].rxq_idx connect fp_rename_stage.io.dec_uops[0].stq_idx, dec_uops[0].stq_idx connect fp_rename_stage.io.dec_uops[0].ldq_idx, dec_uops[0].ldq_idx connect fp_rename_stage.io.dec_uops[0].rob_idx, dec_uops[0].rob_idx connect fp_rename_stage.io.dec_uops[0].csr_addr, dec_uops[0].csr_addr connect fp_rename_stage.io.dec_uops[0].imm_packed, dec_uops[0].imm_packed connect fp_rename_stage.io.dec_uops[0].taken, dec_uops[0].taken connect fp_rename_stage.io.dec_uops[0].pc_lob, dec_uops[0].pc_lob connect fp_rename_stage.io.dec_uops[0].edge_inst, dec_uops[0].edge_inst connect fp_rename_stage.io.dec_uops[0].ftq_idx, dec_uops[0].ftq_idx connect fp_rename_stage.io.dec_uops[0].br_tag, dec_uops[0].br_tag connect fp_rename_stage.io.dec_uops[0].br_mask, dec_uops[0].br_mask connect fp_rename_stage.io.dec_uops[0].is_sfb, dec_uops[0].is_sfb connect fp_rename_stage.io.dec_uops[0].is_jal, dec_uops[0].is_jal connect fp_rename_stage.io.dec_uops[0].is_jalr, dec_uops[0].is_jalr connect fp_rename_stage.io.dec_uops[0].is_br, dec_uops[0].is_br connect fp_rename_stage.io.dec_uops[0].iw_p2_poisoned, dec_uops[0].iw_p2_poisoned connect fp_rename_stage.io.dec_uops[0].iw_p1_poisoned, dec_uops[0].iw_p1_poisoned connect fp_rename_stage.io.dec_uops[0].iw_state, dec_uops[0].iw_state connect fp_rename_stage.io.dec_uops[0].ctrl.is_std, dec_uops[0].ctrl.is_std connect fp_rename_stage.io.dec_uops[0].ctrl.is_sta, dec_uops[0].ctrl.is_sta connect fp_rename_stage.io.dec_uops[0].ctrl.is_load, dec_uops[0].ctrl.is_load connect fp_rename_stage.io.dec_uops[0].ctrl.csr_cmd, dec_uops[0].ctrl.csr_cmd connect fp_rename_stage.io.dec_uops[0].ctrl.fcn_dw, dec_uops[0].ctrl.fcn_dw connect fp_rename_stage.io.dec_uops[0].ctrl.op_fcn, dec_uops[0].ctrl.op_fcn connect fp_rename_stage.io.dec_uops[0].ctrl.imm_sel, dec_uops[0].ctrl.imm_sel connect fp_rename_stage.io.dec_uops[0].ctrl.op2_sel, dec_uops[0].ctrl.op2_sel connect fp_rename_stage.io.dec_uops[0].ctrl.op1_sel, dec_uops[0].ctrl.op1_sel connect fp_rename_stage.io.dec_uops[0].ctrl.br_type, dec_uops[0].ctrl.br_type connect fp_rename_stage.io.dec_uops[0].fu_code, dec_uops[0].fu_code connect fp_rename_stage.io.dec_uops[0].iq_type, dec_uops[0].iq_type connect fp_rename_stage.io.dec_uops[0].debug_pc, dec_uops[0].debug_pc connect fp_rename_stage.io.dec_uops[0].is_rvc, dec_uops[0].is_rvc connect fp_rename_stage.io.dec_uops[0].debug_inst, dec_uops[0].debug_inst connect fp_rename_stage.io.dec_uops[0].inst, dec_uops[0].inst connect fp_rename_stage.io.dec_uops[0].uopc, dec_uops[0].uopc connect fp_rename_stage.io.dec_uops[1].debug_tsrc, dec_uops[1].debug_tsrc connect fp_rename_stage.io.dec_uops[1].debug_fsrc, dec_uops[1].debug_fsrc connect fp_rename_stage.io.dec_uops[1].bp_xcpt_if, dec_uops[1].bp_xcpt_if connect fp_rename_stage.io.dec_uops[1].bp_debug_if, dec_uops[1].bp_debug_if connect fp_rename_stage.io.dec_uops[1].xcpt_ma_if, dec_uops[1].xcpt_ma_if connect fp_rename_stage.io.dec_uops[1].xcpt_ae_if, dec_uops[1].xcpt_ae_if connect fp_rename_stage.io.dec_uops[1].xcpt_pf_if, dec_uops[1].xcpt_pf_if connect fp_rename_stage.io.dec_uops[1].fp_single, dec_uops[1].fp_single connect fp_rename_stage.io.dec_uops[1].fp_val, dec_uops[1].fp_val connect fp_rename_stage.io.dec_uops[1].frs3_en, dec_uops[1].frs3_en connect fp_rename_stage.io.dec_uops[1].lrs2_rtype, dec_uops[1].lrs2_rtype connect fp_rename_stage.io.dec_uops[1].lrs1_rtype, dec_uops[1].lrs1_rtype connect fp_rename_stage.io.dec_uops[1].dst_rtype, dec_uops[1].dst_rtype connect fp_rename_stage.io.dec_uops[1].ldst_val, dec_uops[1].ldst_val connect fp_rename_stage.io.dec_uops[1].lrs3, dec_uops[1].lrs3 connect fp_rename_stage.io.dec_uops[1].lrs2, dec_uops[1].lrs2 connect fp_rename_stage.io.dec_uops[1].lrs1, dec_uops[1].lrs1 connect fp_rename_stage.io.dec_uops[1].ldst, dec_uops[1].ldst connect fp_rename_stage.io.dec_uops[1].ldst_is_rs1, dec_uops[1].ldst_is_rs1 connect fp_rename_stage.io.dec_uops[1].flush_on_commit, dec_uops[1].flush_on_commit connect fp_rename_stage.io.dec_uops[1].is_unique, dec_uops[1].is_unique connect fp_rename_stage.io.dec_uops[1].is_sys_pc2epc, dec_uops[1].is_sys_pc2epc connect fp_rename_stage.io.dec_uops[1].uses_stq, dec_uops[1].uses_stq connect fp_rename_stage.io.dec_uops[1].uses_ldq, dec_uops[1].uses_ldq connect fp_rename_stage.io.dec_uops[1].is_amo, dec_uops[1].is_amo connect fp_rename_stage.io.dec_uops[1].is_fencei, dec_uops[1].is_fencei connect fp_rename_stage.io.dec_uops[1].is_fence, dec_uops[1].is_fence connect fp_rename_stage.io.dec_uops[1].mem_signed, dec_uops[1].mem_signed connect fp_rename_stage.io.dec_uops[1].mem_size, dec_uops[1].mem_size connect fp_rename_stage.io.dec_uops[1].mem_cmd, dec_uops[1].mem_cmd connect fp_rename_stage.io.dec_uops[1].bypassable, dec_uops[1].bypassable connect fp_rename_stage.io.dec_uops[1].exc_cause, dec_uops[1].exc_cause connect fp_rename_stage.io.dec_uops[1].exception, dec_uops[1].exception connect fp_rename_stage.io.dec_uops[1].stale_pdst, dec_uops[1].stale_pdst connect fp_rename_stage.io.dec_uops[1].ppred_busy, dec_uops[1].ppred_busy connect fp_rename_stage.io.dec_uops[1].prs3_busy, dec_uops[1].prs3_busy connect fp_rename_stage.io.dec_uops[1].prs2_busy, dec_uops[1].prs2_busy connect fp_rename_stage.io.dec_uops[1].prs1_busy, dec_uops[1].prs1_busy connect fp_rename_stage.io.dec_uops[1].ppred, dec_uops[1].ppred connect fp_rename_stage.io.dec_uops[1].prs3, dec_uops[1].prs3 connect fp_rename_stage.io.dec_uops[1].prs2, dec_uops[1].prs2 connect fp_rename_stage.io.dec_uops[1].prs1, dec_uops[1].prs1 connect fp_rename_stage.io.dec_uops[1].pdst, dec_uops[1].pdst connect fp_rename_stage.io.dec_uops[1].rxq_idx, dec_uops[1].rxq_idx connect fp_rename_stage.io.dec_uops[1].stq_idx, dec_uops[1].stq_idx connect fp_rename_stage.io.dec_uops[1].ldq_idx, dec_uops[1].ldq_idx connect fp_rename_stage.io.dec_uops[1].rob_idx, dec_uops[1].rob_idx connect fp_rename_stage.io.dec_uops[1].csr_addr, dec_uops[1].csr_addr connect fp_rename_stage.io.dec_uops[1].imm_packed, dec_uops[1].imm_packed connect fp_rename_stage.io.dec_uops[1].taken, dec_uops[1].taken connect fp_rename_stage.io.dec_uops[1].pc_lob, dec_uops[1].pc_lob connect fp_rename_stage.io.dec_uops[1].edge_inst, dec_uops[1].edge_inst connect fp_rename_stage.io.dec_uops[1].ftq_idx, dec_uops[1].ftq_idx connect fp_rename_stage.io.dec_uops[1].br_tag, dec_uops[1].br_tag connect fp_rename_stage.io.dec_uops[1].br_mask, dec_uops[1].br_mask connect fp_rename_stage.io.dec_uops[1].is_sfb, dec_uops[1].is_sfb connect fp_rename_stage.io.dec_uops[1].is_jal, dec_uops[1].is_jal connect fp_rename_stage.io.dec_uops[1].is_jalr, dec_uops[1].is_jalr connect fp_rename_stage.io.dec_uops[1].is_br, dec_uops[1].is_br connect fp_rename_stage.io.dec_uops[1].iw_p2_poisoned, dec_uops[1].iw_p2_poisoned connect fp_rename_stage.io.dec_uops[1].iw_p1_poisoned, dec_uops[1].iw_p1_poisoned connect fp_rename_stage.io.dec_uops[1].iw_state, dec_uops[1].iw_state connect fp_rename_stage.io.dec_uops[1].ctrl.is_std, dec_uops[1].ctrl.is_std connect fp_rename_stage.io.dec_uops[1].ctrl.is_sta, dec_uops[1].ctrl.is_sta connect fp_rename_stage.io.dec_uops[1].ctrl.is_load, dec_uops[1].ctrl.is_load connect fp_rename_stage.io.dec_uops[1].ctrl.csr_cmd, dec_uops[1].ctrl.csr_cmd connect fp_rename_stage.io.dec_uops[1].ctrl.fcn_dw, dec_uops[1].ctrl.fcn_dw connect fp_rename_stage.io.dec_uops[1].ctrl.op_fcn, dec_uops[1].ctrl.op_fcn connect fp_rename_stage.io.dec_uops[1].ctrl.imm_sel, dec_uops[1].ctrl.imm_sel connect fp_rename_stage.io.dec_uops[1].ctrl.op2_sel, dec_uops[1].ctrl.op2_sel connect fp_rename_stage.io.dec_uops[1].ctrl.op1_sel, dec_uops[1].ctrl.op1_sel connect fp_rename_stage.io.dec_uops[1].ctrl.br_type, dec_uops[1].ctrl.br_type connect fp_rename_stage.io.dec_uops[1].fu_code, dec_uops[1].fu_code connect fp_rename_stage.io.dec_uops[1].iq_type, dec_uops[1].iq_type connect fp_rename_stage.io.dec_uops[1].debug_pc, dec_uops[1].debug_pc connect fp_rename_stage.io.dec_uops[1].is_rvc, dec_uops[1].is_rvc connect fp_rename_stage.io.dec_uops[1].debug_inst, dec_uops[1].debug_inst connect fp_rename_stage.io.dec_uops[1].inst, dec_uops[1].inst connect fp_rename_stage.io.dec_uops[1].uopc, dec_uops[1].uopc connect fp_rename_stage.io.dec_uops[2].debug_tsrc, dec_uops[2].debug_tsrc connect fp_rename_stage.io.dec_uops[2].debug_fsrc, dec_uops[2].debug_fsrc connect fp_rename_stage.io.dec_uops[2].bp_xcpt_if, dec_uops[2].bp_xcpt_if connect fp_rename_stage.io.dec_uops[2].bp_debug_if, dec_uops[2].bp_debug_if connect fp_rename_stage.io.dec_uops[2].xcpt_ma_if, dec_uops[2].xcpt_ma_if connect fp_rename_stage.io.dec_uops[2].xcpt_ae_if, dec_uops[2].xcpt_ae_if connect fp_rename_stage.io.dec_uops[2].xcpt_pf_if, dec_uops[2].xcpt_pf_if connect fp_rename_stage.io.dec_uops[2].fp_single, dec_uops[2].fp_single connect fp_rename_stage.io.dec_uops[2].fp_val, dec_uops[2].fp_val connect fp_rename_stage.io.dec_uops[2].frs3_en, dec_uops[2].frs3_en connect fp_rename_stage.io.dec_uops[2].lrs2_rtype, dec_uops[2].lrs2_rtype connect fp_rename_stage.io.dec_uops[2].lrs1_rtype, dec_uops[2].lrs1_rtype connect fp_rename_stage.io.dec_uops[2].dst_rtype, dec_uops[2].dst_rtype connect fp_rename_stage.io.dec_uops[2].ldst_val, dec_uops[2].ldst_val connect fp_rename_stage.io.dec_uops[2].lrs3, dec_uops[2].lrs3 connect fp_rename_stage.io.dec_uops[2].lrs2, dec_uops[2].lrs2 connect fp_rename_stage.io.dec_uops[2].lrs1, dec_uops[2].lrs1 connect fp_rename_stage.io.dec_uops[2].ldst, dec_uops[2].ldst connect fp_rename_stage.io.dec_uops[2].ldst_is_rs1, dec_uops[2].ldst_is_rs1 connect fp_rename_stage.io.dec_uops[2].flush_on_commit, dec_uops[2].flush_on_commit connect fp_rename_stage.io.dec_uops[2].is_unique, dec_uops[2].is_unique connect fp_rename_stage.io.dec_uops[2].is_sys_pc2epc, dec_uops[2].is_sys_pc2epc connect fp_rename_stage.io.dec_uops[2].uses_stq, dec_uops[2].uses_stq connect fp_rename_stage.io.dec_uops[2].uses_ldq, dec_uops[2].uses_ldq connect fp_rename_stage.io.dec_uops[2].is_amo, dec_uops[2].is_amo connect fp_rename_stage.io.dec_uops[2].is_fencei, dec_uops[2].is_fencei connect fp_rename_stage.io.dec_uops[2].is_fence, dec_uops[2].is_fence connect fp_rename_stage.io.dec_uops[2].mem_signed, dec_uops[2].mem_signed connect fp_rename_stage.io.dec_uops[2].mem_size, dec_uops[2].mem_size connect fp_rename_stage.io.dec_uops[2].mem_cmd, dec_uops[2].mem_cmd connect fp_rename_stage.io.dec_uops[2].bypassable, dec_uops[2].bypassable connect fp_rename_stage.io.dec_uops[2].exc_cause, dec_uops[2].exc_cause connect fp_rename_stage.io.dec_uops[2].exception, dec_uops[2].exception connect fp_rename_stage.io.dec_uops[2].stale_pdst, dec_uops[2].stale_pdst connect fp_rename_stage.io.dec_uops[2].ppred_busy, dec_uops[2].ppred_busy connect fp_rename_stage.io.dec_uops[2].prs3_busy, dec_uops[2].prs3_busy connect fp_rename_stage.io.dec_uops[2].prs2_busy, dec_uops[2].prs2_busy connect fp_rename_stage.io.dec_uops[2].prs1_busy, dec_uops[2].prs1_busy connect fp_rename_stage.io.dec_uops[2].ppred, dec_uops[2].ppred connect fp_rename_stage.io.dec_uops[2].prs3, dec_uops[2].prs3 connect fp_rename_stage.io.dec_uops[2].prs2, dec_uops[2].prs2 connect fp_rename_stage.io.dec_uops[2].prs1, dec_uops[2].prs1 connect fp_rename_stage.io.dec_uops[2].pdst, dec_uops[2].pdst connect fp_rename_stage.io.dec_uops[2].rxq_idx, dec_uops[2].rxq_idx connect fp_rename_stage.io.dec_uops[2].stq_idx, dec_uops[2].stq_idx connect fp_rename_stage.io.dec_uops[2].ldq_idx, dec_uops[2].ldq_idx connect fp_rename_stage.io.dec_uops[2].rob_idx, dec_uops[2].rob_idx connect fp_rename_stage.io.dec_uops[2].csr_addr, dec_uops[2].csr_addr connect fp_rename_stage.io.dec_uops[2].imm_packed, dec_uops[2].imm_packed connect fp_rename_stage.io.dec_uops[2].taken, dec_uops[2].taken connect fp_rename_stage.io.dec_uops[2].pc_lob, dec_uops[2].pc_lob connect fp_rename_stage.io.dec_uops[2].edge_inst, dec_uops[2].edge_inst connect fp_rename_stage.io.dec_uops[2].ftq_idx, dec_uops[2].ftq_idx connect fp_rename_stage.io.dec_uops[2].br_tag, dec_uops[2].br_tag connect fp_rename_stage.io.dec_uops[2].br_mask, dec_uops[2].br_mask connect fp_rename_stage.io.dec_uops[2].is_sfb, dec_uops[2].is_sfb connect fp_rename_stage.io.dec_uops[2].is_jal, dec_uops[2].is_jal connect fp_rename_stage.io.dec_uops[2].is_jalr, dec_uops[2].is_jalr connect fp_rename_stage.io.dec_uops[2].is_br, dec_uops[2].is_br connect fp_rename_stage.io.dec_uops[2].iw_p2_poisoned, dec_uops[2].iw_p2_poisoned connect fp_rename_stage.io.dec_uops[2].iw_p1_poisoned, dec_uops[2].iw_p1_poisoned connect fp_rename_stage.io.dec_uops[2].iw_state, dec_uops[2].iw_state connect fp_rename_stage.io.dec_uops[2].ctrl.is_std, dec_uops[2].ctrl.is_std connect fp_rename_stage.io.dec_uops[2].ctrl.is_sta, dec_uops[2].ctrl.is_sta connect fp_rename_stage.io.dec_uops[2].ctrl.is_load, dec_uops[2].ctrl.is_load connect fp_rename_stage.io.dec_uops[2].ctrl.csr_cmd, dec_uops[2].ctrl.csr_cmd connect fp_rename_stage.io.dec_uops[2].ctrl.fcn_dw, dec_uops[2].ctrl.fcn_dw connect fp_rename_stage.io.dec_uops[2].ctrl.op_fcn, dec_uops[2].ctrl.op_fcn connect fp_rename_stage.io.dec_uops[2].ctrl.imm_sel, dec_uops[2].ctrl.imm_sel connect fp_rename_stage.io.dec_uops[2].ctrl.op2_sel, dec_uops[2].ctrl.op2_sel connect fp_rename_stage.io.dec_uops[2].ctrl.op1_sel, dec_uops[2].ctrl.op1_sel connect fp_rename_stage.io.dec_uops[2].ctrl.br_type, dec_uops[2].ctrl.br_type connect fp_rename_stage.io.dec_uops[2].fu_code, dec_uops[2].fu_code connect fp_rename_stage.io.dec_uops[2].iq_type, dec_uops[2].iq_type connect fp_rename_stage.io.dec_uops[2].debug_pc, dec_uops[2].debug_pc connect fp_rename_stage.io.dec_uops[2].is_rvc, dec_uops[2].is_rvc connect fp_rename_stage.io.dec_uops[2].debug_inst, dec_uops[2].debug_inst connect fp_rename_stage.io.dec_uops[2].inst, dec_uops[2].inst connect fp_rename_stage.io.dec_uops[2].uopc, dec_uops[2].uopc connect fp_rename_stage.io.dis_fire[0], dis_fire[0] connect fp_rename_stage.io.dis_fire[1], dis_fire[1] connect fp_rename_stage.io.dis_fire[2], dis_fire[2] connect fp_rename_stage.io.dis_ready, dis_ready connect fp_rename_stage.io.com_valids[0], rob.io.commit.valids[0] connect fp_rename_stage.io.com_valids[1], rob.io.commit.valids[1] connect fp_rename_stage.io.com_valids[2], rob.io.commit.valids[2] connect fp_rename_stage.io.com_uops[0].debug_tsrc, rob.io.commit.uops[0].debug_tsrc connect fp_rename_stage.io.com_uops[0].debug_fsrc, rob.io.commit.uops[0].debug_fsrc connect fp_rename_stage.io.com_uops[0].bp_xcpt_if, rob.io.commit.uops[0].bp_xcpt_if connect fp_rename_stage.io.com_uops[0].bp_debug_if, rob.io.commit.uops[0].bp_debug_if connect fp_rename_stage.io.com_uops[0].xcpt_ma_if, rob.io.commit.uops[0].xcpt_ma_if connect fp_rename_stage.io.com_uops[0].xcpt_ae_if, rob.io.commit.uops[0].xcpt_ae_if connect fp_rename_stage.io.com_uops[0].xcpt_pf_if, rob.io.commit.uops[0].xcpt_pf_if connect fp_rename_stage.io.com_uops[0].fp_single, rob.io.commit.uops[0].fp_single connect fp_rename_stage.io.com_uops[0].fp_val, rob.io.commit.uops[0].fp_val connect fp_rename_stage.io.com_uops[0].frs3_en, rob.io.commit.uops[0].frs3_en connect fp_rename_stage.io.com_uops[0].lrs2_rtype, rob.io.commit.uops[0].lrs2_rtype connect fp_rename_stage.io.com_uops[0].lrs1_rtype, rob.io.commit.uops[0].lrs1_rtype connect fp_rename_stage.io.com_uops[0].dst_rtype, rob.io.commit.uops[0].dst_rtype connect fp_rename_stage.io.com_uops[0].ldst_val, rob.io.commit.uops[0].ldst_val connect fp_rename_stage.io.com_uops[0].lrs3, rob.io.commit.uops[0].lrs3 connect fp_rename_stage.io.com_uops[0].lrs2, rob.io.commit.uops[0].lrs2 connect fp_rename_stage.io.com_uops[0].lrs1, rob.io.commit.uops[0].lrs1 connect fp_rename_stage.io.com_uops[0].ldst, rob.io.commit.uops[0].ldst connect fp_rename_stage.io.com_uops[0].ldst_is_rs1, rob.io.commit.uops[0].ldst_is_rs1 connect fp_rename_stage.io.com_uops[0].flush_on_commit, rob.io.commit.uops[0].flush_on_commit connect fp_rename_stage.io.com_uops[0].is_unique, rob.io.commit.uops[0].is_unique connect fp_rename_stage.io.com_uops[0].is_sys_pc2epc, rob.io.commit.uops[0].is_sys_pc2epc connect fp_rename_stage.io.com_uops[0].uses_stq, rob.io.commit.uops[0].uses_stq connect fp_rename_stage.io.com_uops[0].uses_ldq, rob.io.commit.uops[0].uses_ldq connect fp_rename_stage.io.com_uops[0].is_amo, rob.io.commit.uops[0].is_amo connect fp_rename_stage.io.com_uops[0].is_fencei, rob.io.commit.uops[0].is_fencei connect fp_rename_stage.io.com_uops[0].is_fence, rob.io.commit.uops[0].is_fence connect fp_rename_stage.io.com_uops[0].mem_signed, rob.io.commit.uops[0].mem_signed connect fp_rename_stage.io.com_uops[0].mem_size, rob.io.commit.uops[0].mem_size connect fp_rename_stage.io.com_uops[0].mem_cmd, rob.io.commit.uops[0].mem_cmd connect fp_rename_stage.io.com_uops[0].bypassable, rob.io.commit.uops[0].bypassable connect fp_rename_stage.io.com_uops[0].exc_cause, rob.io.commit.uops[0].exc_cause connect fp_rename_stage.io.com_uops[0].exception, rob.io.commit.uops[0].exception connect fp_rename_stage.io.com_uops[0].stale_pdst, rob.io.commit.uops[0].stale_pdst connect fp_rename_stage.io.com_uops[0].ppred_busy, rob.io.commit.uops[0].ppred_busy connect fp_rename_stage.io.com_uops[0].prs3_busy, rob.io.commit.uops[0].prs3_busy connect fp_rename_stage.io.com_uops[0].prs2_busy, rob.io.commit.uops[0].prs2_busy connect fp_rename_stage.io.com_uops[0].prs1_busy, rob.io.commit.uops[0].prs1_busy connect fp_rename_stage.io.com_uops[0].ppred, rob.io.commit.uops[0].ppred connect fp_rename_stage.io.com_uops[0].prs3, rob.io.commit.uops[0].prs3 connect fp_rename_stage.io.com_uops[0].prs2, rob.io.commit.uops[0].prs2 connect fp_rename_stage.io.com_uops[0].prs1, rob.io.commit.uops[0].prs1 connect fp_rename_stage.io.com_uops[0].pdst, rob.io.commit.uops[0].pdst connect fp_rename_stage.io.com_uops[0].rxq_idx, rob.io.commit.uops[0].rxq_idx connect fp_rename_stage.io.com_uops[0].stq_idx, rob.io.commit.uops[0].stq_idx connect fp_rename_stage.io.com_uops[0].ldq_idx, rob.io.commit.uops[0].ldq_idx connect fp_rename_stage.io.com_uops[0].rob_idx, rob.io.commit.uops[0].rob_idx connect fp_rename_stage.io.com_uops[0].csr_addr, rob.io.commit.uops[0].csr_addr connect fp_rename_stage.io.com_uops[0].imm_packed, rob.io.commit.uops[0].imm_packed connect fp_rename_stage.io.com_uops[0].taken, rob.io.commit.uops[0].taken connect fp_rename_stage.io.com_uops[0].pc_lob, rob.io.commit.uops[0].pc_lob connect fp_rename_stage.io.com_uops[0].edge_inst, rob.io.commit.uops[0].edge_inst connect fp_rename_stage.io.com_uops[0].ftq_idx, rob.io.commit.uops[0].ftq_idx connect fp_rename_stage.io.com_uops[0].br_tag, rob.io.commit.uops[0].br_tag connect fp_rename_stage.io.com_uops[0].br_mask, rob.io.commit.uops[0].br_mask connect fp_rename_stage.io.com_uops[0].is_sfb, rob.io.commit.uops[0].is_sfb connect fp_rename_stage.io.com_uops[0].is_jal, rob.io.commit.uops[0].is_jal connect fp_rename_stage.io.com_uops[0].is_jalr, rob.io.commit.uops[0].is_jalr connect fp_rename_stage.io.com_uops[0].is_br, rob.io.commit.uops[0].is_br connect fp_rename_stage.io.com_uops[0].iw_p2_poisoned, rob.io.commit.uops[0].iw_p2_poisoned connect fp_rename_stage.io.com_uops[0].iw_p1_poisoned, rob.io.commit.uops[0].iw_p1_poisoned connect fp_rename_stage.io.com_uops[0].iw_state, rob.io.commit.uops[0].iw_state connect fp_rename_stage.io.com_uops[0].ctrl.is_std, rob.io.commit.uops[0].ctrl.is_std connect fp_rename_stage.io.com_uops[0].ctrl.is_sta, rob.io.commit.uops[0].ctrl.is_sta connect fp_rename_stage.io.com_uops[0].ctrl.is_load, rob.io.commit.uops[0].ctrl.is_load connect fp_rename_stage.io.com_uops[0].ctrl.csr_cmd, rob.io.commit.uops[0].ctrl.csr_cmd connect fp_rename_stage.io.com_uops[0].ctrl.fcn_dw, rob.io.commit.uops[0].ctrl.fcn_dw connect fp_rename_stage.io.com_uops[0].ctrl.op_fcn, rob.io.commit.uops[0].ctrl.op_fcn connect fp_rename_stage.io.com_uops[0].ctrl.imm_sel, rob.io.commit.uops[0].ctrl.imm_sel connect fp_rename_stage.io.com_uops[0].ctrl.op2_sel, rob.io.commit.uops[0].ctrl.op2_sel connect fp_rename_stage.io.com_uops[0].ctrl.op1_sel, rob.io.commit.uops[0].ctrl.op1_sel connect fp_rename_stage.io.com_uops[0].ctrl.br_type, rob.io.commit.uops[0].ctrl.br_type connect fp_rename_stage.io.com_uops[0].fu_code, rob.io.commit.uops[0].fu_code connect fp_rename_stage.io.com_uops[0].iq_type, rob.io.commit.uops[0].iq_type connect fp_rename_stage.io.com_uops[0].debug_pc, rob.io.commit.uops[0].debug_pc connect fp_rename_stage.io.com_uops[0].is_rvc, rob.io.commit.uops[0].is_rvc connect fp_rename_stage.io.com_uops[0].debug_inst, rob.io.commit.uops[0].debug_inst connect fp_rename_stage.io.com_uops[0].inst, rob.io.commit.uops[0].inst connect fp_rename_stage.io.com_uops[0].uopc, rob.io.commit.uops[0].uopc connect fp_rename_stage.io.com_uops[1].debug_tsrc, rob.io.commit.uops[1].debug_tsrc connect fp_rename_stage.io.com_uops[1].debug_fsrc, rob.io.commit.uops[1].debug_fsrc connect fp_rename_stage.io.com_uops[1].bp_xcpt_if, rob.io.commit.uops[1].bp_xcpt_if connect fp_rename_stage.io.com_uops[1].bp_debug_if, rob.io.commit.uops[1].bp_debug_if connect fp_rename_stage.io.com_uops[1].xcpt_ma_if, rob.io.commit.uops[1].xcpt_ma_if connect fp_rename_stage.io.com_uops[1].xcpt_ae_if, rob.io.commit.uops[1].xcpt_ae_if connect fp_rename_stage.io.com_uops[1].xcpt_pf_if, rob.io.commit.uops[1].xcpt_pf_if connect fp_rename_stage.io.com_uops[1].fp_single, rob.io.commit.uops[1].fp_single connect fp_rename_stage.io.com_uops[1].fp_val, rob.io.commit.uops[1].fp_val connect fp_rename_stage.io.com_uops[1].frs3_en, rob.io.commit.uops[1].frs3_en connect fp_rename_stage.io.com_uops[1].lrs2_rtype, rob.io.commit.uops[1].lrs2_rtype connect fp_rename_stage.io.com_uops[1].lrs1_rtype, rob.io.commit.uops[1].lrs1_rtype connect fp_rename_stage.io.com_uops[1].dst_rtype, rob.io.commit.uops[1].dst_rtype connect fp_rename_stage.io.com_uops[1].ldst_val, rob.io.commit.uops[1].ldst_val connect fp_rename_stage.io.com_uops[1].lrs3, rob.io.commit.uops[1].lrs3 connect fp_rename_stage.io.com_uops[1].lrs2, rob.io.commit.uops[1].lrs2 connect fp_rename_stage.io.com_uops[1].lrs1, rob.io.commit.uops[1].lrs1 connect fp_rename_stage.io.com_uops[1].ldst, rob.io.commit.uops[1].ldst connect fp_rename_stage.io.com_uops[1].ldst_is_rs1, rob.io.commit.uops[1].ldst_is_rs1 connect fp_rename_stage.io.com_uops[1].flush_on_commit, rob.io.commit.uops[1].flush_on_commit connect fp_rename_stage.io.com_uops[1].is_unique, rob.io.commit.uops[1].is_unique connect fp_rename_stage.io.com_uops[1].is_sys_pc2epc, rob.io.commit.uops[1].is_sys_pc2epc connect fp_rename_stage.io.com_uops[1].uses_stq, rob.io.commit.uops[1].uses_stq connect fp_rename_stage.io.com_uops[1].uses_ldq, rob.io.commit.uops[1].uses_ldq connect fp_rename_stage.io.com_uops[1].is_amo, rob.io.commit.uops[1].is_amo connect fp_rename_stage.io.com_uops[1].is_fencei, rob.io.commit.uops[1].is_fencei connect fp_rename_stage.io.com_uops[1].is_fence, rob.io.commit.uops[1].is_fence connect fp_rename_stage.io.com_uops[1].mem_signed, rob.io.commit.uops[1].mem_signed connect fp_rename_stage.io.com_uops[1].mem_size, rob.io.commit.uops[1].mem_size connect fp_rename_stage.io.com_uops[1].mem_cmd, rob.io.commit.uops[1].mem_cmd connect fp_rename_stage.io.com_uops[1].bypassable, rob.io.commit.uops[1].bypassable connect fp_rename_stage.io.com_uops[1].exc_cause, rob.io.commit.uops[1].exc_cause connect fp_rename_stage.io.com_uops[1].exception, rob.io.commit.uops[1].exception connect fp_rename_stage.io.com_uops[1].stale_pdst, rob.io.commit.uops[1].stale_pdst connect fp_rename_stage.io.com_uops[1].ppred_busy, rob.io.commit.uops[1].ppred_busy connect fp_rename_stage.io.com_uops[1].prs3_busy, rob.io.commit.uops[1].prs3_busy connect fp_rename_stage.io.com_uops[1].prs2_busy, rob.io.commit.uops[1].prs2_busy connect fp_rename_stage.io.com_uops[1].prs1_busy, rob.io.commit.uops[1].prs1_busy connect fp_rename_stage.io.com_uops[1].ppred, rob.io.commit.uops[1].ppred connect fp_rename_stage.io.com_uops[1].prs3, rob.io.commit.uops[1].prs3 connect fp_rename_stage.io.com_uops[1].prs2, rob.io.commit.uops[1].prs2 connect fp_rename_stage.io.com_uops[1].prs1, rob.io.commit.uops[1].prs1 connect fp_rename_stage.io.com_uops[1].pdst, rob.io.commit.uops[1].pdst connect fp_rename_stage.io.com_uops[1].rxq_idx, rob.io.commit.uops[1].rxq_idx connect fp_rename_stage.io.com_uops[1].stq_idx, rob.io.commit.uops[1].stq_idx connect fp_rename_stage.io.com_uops[1].ldq_idx, rob.io.commit.uops[1].ldq_idx connect fp_rename_stage.io.com_uops[1].rob_idx, rob.io.commit.uops[1].rob_idx connect fp_rename_stage.io.com_uops[1].csr_addr, rob.io.commit.uops[1].csr_addr connect fp_rename_stage.io.com_uops[1].imm_packed, rob.io.commit.uops[1].imm_packed connect fp_rename_stage.io.com_uops[1].taken, rob.io.commit.uops[1].taken connect fp_rename_stage.io.com_uops[1].pc_lob, rob.io.commit.uops[1].pc_lob connect fp_rename_stage.io.com_uops[1].edge_inst, rob.io.commit.uops[1].edge_inst connect fp_rename_stage.io.com_uops[1].ftq_idx, rob.io.commit.uops[1].ftq_idx connect fp_rename_stage.io.com_uops[1].br_tag, rob.io.commit.uops[1].br_tag connect fp_rename_stage.io.com_uops[1].br_mask, rob.io.commit.uops[1].br_mask connect fp_rename_stage.io.com_uops[1].is_sfb, rob.io.commit.uops[1].is_sfb connect fp_rename_stage.io.com_uops[1].is_jal, rob.io.commit.uops[1].is_jal connect fp_rename_stage.io.com_uops[1].is_jalr, rob.io.commit.uops[1].is_jalr connect fp_rename_stage.io.com_uops[1].is_br, rob.io.commit.uops[1].is_br connect fp_rename_stage.io.com_uops[1].iw_p2_poisoned, rob.io.commit.uops[1].iw_p2_poisoned connect fp_rename_stage.io.com_uops[1].iw_p1_poisoned, rob.io.commit.uops[1].iw_p1_poisoned connect fp_rename_stage.io.com_uops[1].iw_state, rob.io.commit.uops[1].iw_state connect fp_rename_stage.io.com_uops[1].ctrl.is_std, rob.io.commit.uops[1].ctrl.is_std connect fp_rename_stage.io.com_uops[1].ctrl.is_sta, rob.io.commit.uops[1].ctrl.is_sta connect fp_rename_stage.io.com_uops[1].ctrl.is_load, rob.io.commit.uops[1].ctrl.is_load connect fp_rename_stage.io.com_uops[1].ctrl.csr_cmd, rob.io.commit.uops[1].ctrl.csr_cmd connect fp_rename_stage.io.com_uops[1].ctrl.fcn_dw, rob.io.commit.uops[1].ctrl.fcn_dw connect fp_rename_stage.io.com_uops[1].ctrl.op_fcn, rob.io.commit.uops[1].ctrl.op_fcn connect fp_rename_stage.io.com_uops[1].ctrl.imm_sel, rob.io.commit.uops[1].ctrl.imm_sel connect fp_rename_stage.io.com_uops[1].ctrl.op2_sel, rob.io.commit.uops[1].ctrl.op2_sel connect fp_rename_stage.io.com_uops[1].ctrl.op1_sel, rob.io.commit.uops[1].ctrl.op1_sel connect fp_rename_stage.io.com_uops[1].ctrl.br_type, rob.io.commit.uops[1].ctrl.br_type connect fp_rename_stage.io.com_uops[1].fu_code, rob.io.commit.uops[1].fu_code connect fp_rename_stage.io.com_uops[1].iq_type, rob.io.commit.uops[1].iq_type connect fp_rename_stage.io.com_uops[1].debug_pc, rob.io.commit.uops[1].debug_pc connect fp_rename_stage.io.com_uops[1].is_rvc, rob.io.commit.uops[1].is_rvc connect fp_rename_stage.io.com_uops[1].debug_inst, rob.io.commit.uops[1].debug_inst connect fp_rename_stage.io.com_uops[1].inst, rob.io.commit.uops[1].inst connect fp_rename_stage.io.com_uops[1].uopc, rob.io.commit.uops[1].uopc connect fp_rename_stage.io.com_uops[2].debug_tsrc, rob.io.commit.uops[2].debug_tsrc connect fp_rename_stage.io.com_uops[2].debug_fsrc, rob.io.commit.uops[2].debug_fsrc connect fp_rename_stage.io.com_uops[2].bp_xcpt_if, rob.io.commit.uops[2].bp_xcpt_if connect fp_rename_stage.io.com_uops[2].bp_debug_if, rob.io.commit.uops[2].bp_debug_if connect fp_rename_stage.io.com_uops[2].xcpt_ma_if, rob.io.commit.uops[2].xcpt_ma_if connect fp_rename_stage.io.com_uops[2].xcpt_ae_if, rob.io.commit.uops[2].xcpt_ae_if connect fp_rename_stage.io.com_uops[2].xcpt_pf_if, rob.io.commit.uops[2].xcpt_pf_if connect fp_rename_stage.io.com_uops[2].fp_single, rob.io.commit.uops[2].fp_single connect fp_rename_stage.io.com_uops[2].fp_val, rob.io.commit.uops[2].fp_val connect fp_rename_stage.io.com_uops[2].frs3_en, rob.io.commit.uops[2].frs3_en connect fp_rename_stage.io.com_uops[2].lrs2_rtype, rob.io.commit.uops[2].lrs2_rtype connect fp_rename_stage.io.com_uops[2].lrs1_rtype, rob.io.commit.uops[2].lrs1_rtype connect fp_rename_stage.io.com_uops[2].dst_rtype, rob.io.commit.uops[2].dst_rtype connect fp_rename_stage.io.com_uops[2].ldst_val, rob.io.commit.uops[2].ldst_val connect fp_rename_stage.io.com_uops[2].lrs3, rob.io.commit.uops[2].lrs3 connect fp_rename_stage.io.com_uops[2].lrs2, rob.io.commit.uops[2].lrs2 connect fp_rename_stage.io.com_uops[2].lrs1, rob.io.commit.uops[2].lrs1 connect fp_rename_stage.io.com_uops[2].ldst, rob.io.commit.uops[2].ldst connect fp_rename_stage.io.com_uops[2].ldst_is_rs1, rob.io.commit.uops[2].ldst_is_rs1 connect fp_rename_stage.io.com_uops[2].flush_on_commit, rob.io.commit.uops[2].flush_on_commit connect fp_rename_stage.io.com_uops[2].is_unique, rob.io.commit.uops[2].is_unique connect fp_rename_stage.io.com_uops[2].is_sys_pc2epc, rob.io.commit.uops[2].is_sys_pc2epc connect fp_rename_stage.io.com_uops[2].uses_stq, rob.io.commit.uops[2].uses_stq connect fp_rename_stage.io.com_uops[2].uses_ldq, rob.io.commit.uops[2].uses_ldq connect fp_rename_stage.io.com_uops[2].is_amo, rob.io.commit.uops[2].is_amo connect fp_rename_stage.io.com_uops[2].is_fencei, rob.io.commit.uops[2].is_fencei connect fp_rename_stage.io.com_uops[2].is_fence, rob.io.commit.uops[2].is_fence connect fp_rename_stage.io.com_uops[2].mem_signed, rob.io.commit.uops[2].mem_signed connect fp_rename_stage.io.com_uops[2].mem_size, rob.io.commit.uops[2].mem_size connect fp_rename_stage.io.com_uops[2].mem_cmd, rob.io.commit.uops[2].mem_cmd connect fp_rename_stage.io.com_uops[2].bypassable, rob.io.commit.uops[2].bypassable connect fp_rename_stage.io.com_uops[2].exc_cause, rob.io.commit.uops[2].exc_cause connect fp_rename_stage.io.com_uops[2].exception, rob.io.commit.uops[2].exception connect fp_rename_stage.io.com_uops[2].stale_pdst, rob.io.commit.uops[2].stale_pdst connect fp_rename_stage.io.com_uops[2].ppred_busy, rob.io.commit.uops[2].ppred_busy connect fp_rename_stage.io.com_uops[2].prs3_busy, rob.io.commit.uops[2].prs3_busy connect fp_rename_stage.io.com_uops[2].prs2_busy, rob.io.commit.uops[2].prs2_busy connect fp_rename_stage.io.com_uops[2].prs1_busy, rob.io.commit.uops[2].prs1_busy connect fp_rename_stage.io.com_uops[2].ppred, rob.io.commit.uops[2].ppred connect fp_rename_stage.io.com_uops[2].prs3, rob.io.commit.uops[2].prs3 connect fp_rename_stage.io.com_uops[2].prs2, rob.io.commit.uops[2].prs2 connect fp_rename_stage.io.com_uops[2].prs1, rob.io.commit.uops[2].prs1 connect fp_rename_stage.io.com_uops[2].pdst, rob.io.commit.uops[2].pdst connect fp_rename_stage.io.com_uops[2].rxq_idx, rob.io.commit.uops[2].rxq_idx connect fp_rename_stage.io.com_uops[2].stq_idx, rob.io.commit.uops[2].stq_idx connect fp_rename_stage.io.com_uops[2].ldq_idx, rob.io.commit.uops[2].ldq_idx connect fp_rename_stage.io.com_uops[2].rob_idx, rob.io.commit.uops[2].rob_idx connect fp_rename_stage.io.com_uops[2].csr_addr, rob.io.commit.uops[2].csr_addr connect fp_rename_stage.io.com_uops[2].imm_packed, rob.io.commit.uops[2].imm_packed connect fp_rename_stage.io.com_uops[2].taken, rob.io.commit.uops[2].taken connect fp_rename_stage.io.com_uops[2].pc_lob, rob.io.commit.uops[2].pc_lob connect fp_rename_stage.io.com_uops[2].edge_inst, rob.io.commit.uops[2].edge_inst connect fp_rename_stage.io.com_uops[2].ftq_idx, rob.io.commit.uops[2].ftq_idx connect fp_rename_stage.io.com_uops[2].br_tag, rob.io.commit.uops[2].br_tag connect fp_rename_stage.io.com_uops[2].br_mask, rob.io.commit.uops[2].br_mask connect fp_rename_stage.io.com_uops[2].is_sfb, rob.io.commit.uops[2].is_sfb connect fp_rename_stage.io.com_uops[2].is_jal, rob.io.commit.uops[2].is_jal connect fp_rename_stage.io.com_uops[2].is_jalr, rob.io.commit.uops[2].is_jalr connect fp_rename_stage.io.com_uops[2].is_br, rob.io.commit.uops[2].is_br connect fp_rename_stage.io.com_uops[2].iw_p2_poisoned, rob.io.commit.uops[2].iw_p2_poisoned connect fp_rename_stage.io.com_uops[2].iw_p1_poisoned, rob.io.commit.uops[2].iw_p1_poisoned connect fp_rename_stage.io.com_uops[2].iw_state, rob.io.commit.uops[2].iw_state connect fp_rename_stage.io.com_uops[2].ctrl.is_std, rob.io.commit.uops[2].ctrl.is_std connect fp_rename_stage.io.com_uops[2].ctrl.is_sta, rob.io.commit.uops[2].ctrl.is_sta connect fp_rename_stage.io.com_uops[2].ctrl.is_load, rob.io.commit.uops[2].ctrl.is_load connect fp_rename_stage.io.com_uops[2].ctrl.csr_cmd, rob.io.commit.uops[2].ctrl.csr_cmd connect fp_rename_stage.io.com_uops[2].ctrl.fcn_dw, rob.io.commit.uops[2].ctrl.fcn_dw connect fp_rename_stage.io.com_uops[2].ctrl.op_fcn, rob.io.commit.uops[2].ctrl.op_fcn connect fp_rename_stage.io.com_uops[2].ctrl.imm_sel, rob.io.commit.uops[2].ctrl.imm_sel connect fp_rename_stage.io.com_uops[2].ctrl.op2_sel, rob.io.commit.uops[2].ctrl.op2_sel connect fp_rename_stage.io.com_uops[2].ctrl.op1_sel, rob.io.commit.uops[2].ctrl.op1_sel connect fp_rename_stage.io.com_uops[2].ctrl.br_type, rob.io.commit.uops[2].ctrl.br_type connect fp_rename_stage.io.com_uops[2].fu_code, rob.io.commit.uops[2].fu_code connect fp_rename_stage.io.com_uops[2].iq_type, rob.io.commit.uops[2].iq_type connect fp_rename_stage.io.com_uops[2].debug_pc, rob.io.commit.uops[2].debug_pc connect fp_rename_stage.io.com_uops[2].is_rvc, rob.io.commit.uops[2].is_rvc connect fp_rename_stage.io.com_uops[2].debug_inst, rob.io.commit.uops[2].debug_inst connect fp_rename_stage.io.com_uops[2].inst, rob.io.commit.uops[2].inst connect fp_rename_stage.io.com_uops[2].uopc, rob.io.commit.uops[2].uopc connect fp_rename_stage.io.rbk_valids[0], rob.io.commit.rbk_valids[0] connect fp_rename_stage.io.rbk_valids[1], rob.io.commit.rbk_valids[1] connect fp_rename_stage.io.rbk_valids[2], rob.io.commit.rbk_valids[2] connect fp_rename_stage.io.rollback, rob.io.commit.rollback connect pred_rename_stage.io.kill, io.ifu.redirect_flush connect pred_rename_stage.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect pred_rename_stage.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect pred_rename_stage.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect pred_rename_stage.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect pred_rename_stage.io.brupdate.b2.taken, brupdate.b2.taken connect pred_rename_stage.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect pred_rename_stage.io.brupdate.b2.valid, brupdate.b2.valid connect pred_rename_stage.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect pred_rename_stage.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect pred_rename_stage.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect pred_rename_stage.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect pred_rename_stage.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect pred_rename_stage.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect pred_rename_stage.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect pred_rename_stage.io.brupdate.b2.uop.fp_single, brupdate.b2.uop.fp_single connect pred_rename_stage.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect pred_rename_stage.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect pred_rename_stage.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect pred_rename_stage.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect pred_rename_stage.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect pred_rename_stage.io.brupdate.b2.uop.ldst_val, brupdate.b2.uop.ldst_val connect pred_rename_stage.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect pred_rename_stage.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect pred_rename_stage.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect pred_rename_stage.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect pred_rename_stage.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect pred_rename_stage.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect pred_rename_stage.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect pred_rename_stage.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect pred_rename_stage.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect pred_rename_stage.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect pred_rename_stage.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect pred_rename_stage.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect pred_rename_stage.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect pred_rename_stage.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect pred_rename_stage.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect pred_rename_stage.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect pred_rename_stage.io.brupdate.b2.uop.bypassable, brupdate.b2.uop.bypassable connect pred_rename_stage.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect pred_rename_stage.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect pred_rename_stage.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect pred_rename_stage.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect pred_rename_stage.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect pred_rename_stage.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect pred_rename_stage.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect pred_rename_stage.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect pred_rename_stage.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect pred_rename_stage.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect pred_rename_stage.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect pred_rename_stage.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect pred_rename_stage.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect pred_rename_stage.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect pred_rename_stage.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect pred_rename_stage.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect pred_rename_stage.io.brupdate.b2.uop.csr_addr, brupdate.b2.uop.csr_addr connect pred_rename_stage.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect pred_rename_stage.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect pred_rename_stage.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect pred_rename_stage.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect pred_rename_stage.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect pred_rename_stage.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect pred_rename_stage.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect pred_rename_stage.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect pred_rename_stage.io.brupdate.b2.uop.is_jal, brupdate.b2.uop.is_jal connect pred_rename_stage.io.brupdate.b2.uop.is_jalr, brupdate.b2.uop.is_jalr connect pred_rename_stage.io.brupdate.b2.uop.is_br, brupdate.b2.uop.is_br connect pred_rename_stage.io.brupdate.b2.uop.iw_p2_poisoned, brupdate.b2.uop.iw_p2_poisoned connect pred_rename_stage.io.brupdate.b2.uop.iw_p1_poisoned, brupdate.b2.uop.iw_p1_poisoned connect pred_rename_stage.io.brupdate.b2.uop.iw_state, brupdate.b2.uop.iw_state connect pred_rename_stage.io.brupdate.b2.uop.ctrl.is_std, brupdate.b2.uop.ctrl.is_std connect pred_rename_stage.io.brupdate.b2.uop.ctrl.is_sta, brupdate.b2.uop.ctrl.is_sta connect pred_rename_stage.io.brupdate.b2.uop.ctrl.is_load, brupdate.b2.uop.ctrl.is_load connect pred_rename_stage.io.brupdate.b2.uop.ctrl.csr_cmd, brupdate.b2.uop.ctrl.csr_cmd connect pred_rename_stage.io.brupdate.b2.uop.ctrl.fcn_dw, brupdate.b2.uop.ctrl.fcn_dw connect pred_rename_stage.io.brupdate.b2.uop.ctrl.op_fcn, brupdate.b2.uop.ctrl.op_fcn connect pred_rename_stage.io.brupdate.b2.uop.ctrl.imm_sel, brupdate.b2.uop.ctrl.imm_sel connect pred_rename_stage.io.brupdate.b2.uop.ctrl.op2_sel, brupdate.b2.uop.ctrl.op2_sel connect pred_rename_stage.io.brupdate.b2.uop.ctrl.op1_sel, brupdate.b2.uop.ctrl.op1_sel connect pred_rename_stage.io.brupdate.b2.uop.ctrl.br_type, brupdate.b2.uop.ctrl.br_type connect pred_rename_stage.io.brupdate.b2.uop.fu_code, brupdate.b2.uop.fu_code connect pred_rename_stage.io.brupdate.b2.uop.iq_type, brupdate.b2.uop.iq_type connect pred_rename_stage.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect pred_rename_stage.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect pred_rename_stage.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect pred_rename_stage.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect pred_rename_stage.io.brupdate.b2.uop.uopc, brupdate.b2.uop.uopc connect pred_rename_stage.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect pred_rename_stage.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect pred_rename_stage.io.debug_rob_empty, rob.io.empty connect pred_rename_stage.io.dec_fire[0], dec_fire[0] connect pred_rename_stage.io.dec_fire[1], dec_fire[1] connect pred_rename_stage.io.dec_fire[2], dec_fire[2] connect pred_rename_stage.io.dec_uops[0].debug_tsrc, dec_uops[0].debug_tsrc connect pred_rename_stage.io.dec_uops[0].debug_fsrc, dec_uops[0].debug_fsrc connect pred_rename_stage.io.dec_uops[0].bp_xcpt_if, dec_uops[0].bp_xcpt_if connect pred_rename_stage.io.dec_uops[0].bp_debug_if, dec_uops[0].bp_debug_if connect pred_rename_stage.io.dec_uops[0].xcpt_ma_if, dec_uops[0].xcpt_ma_if connect pred_rename_stage.io.dec_uops[0].xcpt_ae_if, dec_uops[0].xcpt_ae_if connect pred_rename_stage.io.dec_uops[0].xcpt_pf_if, dec_uops[0].xcpt_pf_if connect pred_rename_stage.io.dec_uops[0].fp_single, dec_uops[0].fp_single connect pred_rename_stage.io.dec_uops[0].fp_val, dec_uops[0].fp_val connect pred_rename_stage.io.dec_uops[0].frs3_en, dec_uops[0].frs3_en connect pred_rename_stage.io.dec_uops[0].lrs2_rtype, dec_uops[0].lrs2_rtype connect pred_rename_stage.io.dec_uops[0].lrs1_rtype, dec_uops[0].lrs1_rtype connect pred_rename_stage.io.dec_uops[0].dst_rtype, dec_uops[0].dst_rtype connect pred_rename_stage.io.dec_uops[0].ldst_val, dec_uops[0].ldst_val connect pred_rename_stage.io.dec_uops[0].lrs3, dec_uops[0].lrs3 connect pred_rename_stage.io.dec_uops[0].lrs2, dec_uops[0].lrs2 connect pred_rename_stage.io.dec_uops[0].lrs1, dec_uops[0].lrs1 connect pred_rename_stage.io.dec_uops[0].ldst, dec_uops[0].ldst connect pred_rename_stage.io.dec_uops[0].ldst_is_rs1, dec_uops[0].ldst_is_rs1 connect pred_rename_stage.io.dec_uops[0].flush_on_commit, dec_uops[0].flush_on_commit connect pred_rename_stage.io.dec_uops[0].is_unique, dec_uops[0].is_unique connect pred_rename_stage.io.dec_uops[0].is_sys_pc2epc, dec_uops[0].is_sys_pc2epc connect pred_rename_stage.io.dec_uops[0].uses_stq, dec_uops[0].uses_stq connect pred_rename_stage.io.dec_uops[0].uses_ldq, dec_uops[0].uses_ldq connect pred_rename_stage.io.dec_uops[0].is_amo, dec_uops[0].is_amo connect pred_rename_stage.io.dec_uops[0].is_fencei, dec_uops[0].is_fencei connect pred_rename_stage.io.dec_uops[0].is_fence, dec_uops[0].is_fence connect pred_rename_stage.io.dec_uops[0].mem_signed, dec_uops[0].mem_signed connect pred_rename_stage.io.dec_uops[0].mem_size, dec_uops[0].mem_size connect pred_rename_stage.io.dec_uops[0].mem_cmd, dec_uops[0].mem_cmd connect pred_rename_stage.io.dec_uops[0].bypassable, dec_uops[0].bypassable connect pred_rename_stage.io.dec_uops[0].exc_cause, dec_uops[0].exc_cause connect pred_rename_stage.io.dec_uops[0].exception, dec_uops[0].exception connect pred_rename_stage.io.dec_uops[0].stale_pdst, dec_uops[0].stale_pdst connect pred_rename_stage.io.dec_uops[0].ppred_busy, dec_uops[0].ppred_busy connect pred_rename_stage.io.dec_uops[0].prs3_busy, dec_uops[0].prs3_busy connect pred_rename_stage.io.dec_uops[0].prs2_busy, dec_uops[0].prs2_busy connect pred_rename_stage.io.dec_uops[0].prs1_busy, dec_uops[0].prs1_busy connect pred_rename_stage.io.dec_uops[0].ppred, dec_uops[0].ppred connect pred_rename_stage.io.dec_uops[0].prs3, dec_uops[0].prs3 connect pred_rename_stage.io.dec_uops[0].prs2, dec_uops[0].prs2 connect pred_rename_stage.io.dec_uops[0].prs1, dec_uops[0].prs1 connect pred_rename_stage.io.dec_uops[0].pdst, dec_uops[0].pdst connect pred_rename_stage.io.dec_uops[0].rxq_idx, dec_uops[0].rxq_idx connect pred_rename_stage.io.dec_uops[0].stq_idx, dec_uops[0].stq_idx connect pred_rename_stage.io.dec_uops[0].ldq_idx, dec_uops[0].ldq_idx connect pred_rename_stage.io.dec_uops[0].rob_idx, dec_uops[0].rob_idx connect pred_rename_stage.io.dec_uops[0].csr_addr, dec_uops[0].csr_addr connect pred_rename_stage.io.dec_uops[0].imm_packed, dec_uops[0].imm_packed connect pred_rename_stage.io.dec_uops[0].taken, dec_uops[0].taken connect pred_rename_stage.io.dec_uops[0].pc_lob, dec_uops[0].pc_lob connect pred_rename_stage.io.dec_uops[0].edge_inst, dec_uops[0].edge_inst connect pred_rename_stage.io.dec_uops[0].ftq_idx, dec_uops[0].ftq_idx connect pred_rename_stage.io.dec_uops[0].br_tag, dec_uops[0].br_tag connect pred_rename_stage.io.dec_uops[0].br_mask, dec_uops[0].br_mask connect pred_rename_stage.io.dec_uops[0].is_sfb, dec_uops[0].is_sfb connect pred_rename_stage.io.dec_uops[0].is_jal, dec_uops[0].is_jal connect pred_rename_stage.io.dec_uops[0].is_jalr, dec_uops[0].is_jalr connect pred_rename_stage.io.dec_uops[0].is_br, dec_uops[0].is_br connect pred_rename_stage.io.dec_uops[0].iw_p2_poisoned, dec_uops[0].iw_p2_poisoned connect pred_rename_stage.io.dec_uops[0].iw_p1_poisoned, dec_uops[0].iw_p1_poisoned connect pred_rename_stage.io.dec_uops[0].iw_state, dec_uops[0].iw_state connect pred_rename_stage.io.dec_uops[0].ctrl.is_std, dec_uops[0].ctrl.is_std connect pred_rename_stage.io.dec_uops[0].ctrl.is_sta, dec_uops[0].ctrl.is_sta connect pred_rename_stage.io.dec_uops[0].ctrl.is_load, dec_uops[0].ctrl.is_load connect pred_rename_stage.io.dec_uops[0].ctrl.csr_cmd, dec_uops[0].ctrl.csr_cmd connect pred_rename_stage.io.dec_uops[0].ctrl.fcn_dw, dec_uops[0].ctrl.fcn_dw connect pred_rename_stage.io.dec_uops[0].ctrl.op_fcn, dec_uops[0].ctrl.op_fcn connect pred_rename_stage.io.dec_uops[0].ctrl.imm_sel, dec_uops[0].ctrl.imm_sel connect pred_rename_stage.io.dec_uops[0].ctrl.op2_sel, dec_uops[0].ctrl.op2_sel connect pred_rename_stage.io.dec_uops[0].ctrl.op1_sel, dec_uops[0].ctrl.op1_sel connect pred_rename_stage.io.dec_uops[0].ctrl.br_type, dec_uops[0].ctrl.br_type connect pred_rename_stage.io.dec_uops[0].fu_code, dec_uops[0].fu_code connect pred_rename_stage.io.dec_uops[0].iq_type, dec_uops[0].iq_type connect pred_rename_stage.io.dec_uops[0].debug_pc, dec_uops[0].debug_pc connect pred_rename_stage.io.dec_uops[0].is_rvc, dec_uops[0].is_rvc connect pred_rename_stage.io.dec_uops[0].debug_inst, dec_uops[0].debug_inst connect pred_rename_stage.io.dec_uops[0].inst, dec_uops[0].inst connect pred_rename_stage.io.dec_uops[0].uopc, dec_uops[0].uopc connect pred_rename_stage.io.dec_uops[1].debug_tsrc, dec_uops[1].debug_tsrc connect pred_rename_stage.io.dec_uops[1].debug_fsrc, dec_uops[1].debug_fsrc connect pred_rename_stage.io.dec_uops[1].bp_xcpt_if, dec_uops[1].bp_xcpt_if connect pred_rename_stage.io.dec_uops[1].bp_debug_if, dec_uops[1].bp_debug_if connect pred_rename_stage.io.dec_uops[1].xcpt_ma_if, dec_uops[1].xcpt_ma_if connect pred_rename_stage.io.dec_uops[1].xcpt_ae_if, dec_uops[1].xcpt_ae_if connect pred_rename_stage.io.dec_uops[1].xcpt_pf_if, dec_uops[1].xcpt_pf_if connect pred_rename_stage.io.dec_uops[1].fp_single, dec_uops[1].fp_single connect pred_rename_stage.io.dec_uops[1].fp_val, dec_uops[1].fp_val connect pred_rename_stage.io.dec_uops[1].frs3_en, dec_uops[1].frs3_en connect pred_rename_stage.io.dec_uops[1].lrs2_rtype, dec_uops[1].lrs2_rtype connect pred_rename_stage.io.dec_uops[1].lrs1_rtype, dec_uops[1].lrs1_rtype connect pred_rename_stage.io.dec_uops[1].dst_rtype, dec_uops[1].dst_rtype connect pred_rename_stage.io.dec_uops[1].ldst_val, dec_uops[1].ldst_val connect pred_rename_stage.io.dec_uops[1].lrs3, dec_uops[1].lrs3 connect pred_rename_stage.io.dec_uops[1].lrs2, dec_uops[1].lrs2 connect pred_rename_stage.io.dec_uops[1].lrs1, dec_uops[1].lrs1 connect pred_rename_stage.io.dec_uops[1].ldst, dec_uops[1].ldst connect pred_rename_stage.io.dec_uops[1].ldst_is_rs1, dec_uops[1].ldst_is_rs1 connect pred_rename_stage.io.dec_uops[1].flush_on_commit, dec_uops[1].flush_on_commit connect pred_rename_stage.io.dec_uops[1].is_unique, dec_uops[1].is_unique connect pred_rename_stage.io.dec_uops[1].is_sys_pc2epc, dec_uops[1].is_sys_pc2epc connect pred_rename_stage.io.dec_uops[1].uses_stq, dec_uops[1].uses_stq connect pred_rename_stage.io.dec_uops[1].uses_ldq, dec_uops[1].uses_ldq connect pred_rename_stage.io.dec_uops[1].is_amo, dec_uops[1].is_amo connect pred_rename_stage.io.dec_uops[1].is_fencei, dec_uops[1].is_fencei connect pred_rename_stage.io.dec_uops[1].is_fence, dec_uops[1].is_fence connect pred_rename_stage.io.dec_uops[1].mem_signed, dec_uops[1].mem_signed connect pred_rename_stage.io.dec_uops[1].mem_size, dec_uops[1].mem_size connect pred_rename_stage.io.dec_uops[1].mem_cmd, dec_uops[1].mem_cmd connect pred_rename_stage.io.dec_uops[1].bypassable, dec_uops[1].bypassable connect pred_rename_stage.io.dec_uops[1].exc_cause, dec_uops[1].exc_cause connect pred_rename_stage.io.dec_uops[1].exception, dec_uops[1].exception connect pred_rename_stage.io.dec_uops[1].stale_pdst, dec_uops[1].stale_pdst connect pred_rename_stage.io.dec_uops[1].ppred_busy, dec_uops[1].ppred_busy connect pred_rename_stage.io.dec_uops[1].prs3_busy, dec_uops[1].prs3_busy connect pred_rename_stage.io.dec_uops[1].prs2_busy, dec_uops[1].prs2_busy connect pred_rename_stage.io.dec_uops[1].prs1_busy, dec_uops[1].prs1_busy connect pred_rename_stage.io.dec_uops[1].ppred, dec_uops[1].ppred connect pred_rename_stage.io.dec_uops[1].prs3, dec_uops[1].prs3 connect pred_rename_stage.io.dec_uops[1].prs2, dec_uops[1].prs2 connect pred_rename_stage.io.dec_uops[1].prs1, dec_uops[1].prs1 connect pred_rename_stage.io.dec_uops[1].pdst, dec_uops[1].pdst connect pred_rename_stage.io.dec_uops[1].rxq_idx, dec_uops[1].rxq_idx connect pred_rename_stage.io.dec_uops[1].stq_idx, dec_uops[1].stq_idx connect pred_rename_stage.io.dec_uops[1].ldq_idx, dec_uops[1].ldq_idx connect pred_rename_stage.io.dec_uops[1].rob_idx, dec_uops[1].rob_idx connect pred_rename_stage.io.dec_uops[1].csr_addr, dec_uops[1].csr_addr connect pred_rename_stage.io.dec_uops[1].imm_packed, dec_uops[1].imm_packed connect pred_rename_stage.io.dec_uops[1].taken, dec_uops[1].taken connect pred_rename_stage.io.dec_uops[1].pc_lob, dec_uops[1].pc_lob connect pred_rename_stage.io.dec_uops[1].edge_inst, dec_uops[1].edge_inst connect pred_rename_stage.io.dec_uops[1].ftq_idx, dec_uops[1].ftq_idx connect pred_rename_stage.io.dec_uops[1].br_tag, dec_uops[1].br_tag connect pred_rename_stage.io.dec_uops[1].br_mask, dec_uops[1].br_mask connect pred_rename_stage.io.dec_uops[1].is_sfb, dec_uops[1].is_sfb connect pred_rename_stage.io.dec_uops[1].is_jal, dec_uops[1].is_jal connect pred_rename_stage.io.dec_uops[1].is_jalr, dec_uops[1].is_jalr connect pred_rename_stage.io.dec_uops[1].is_br, dec_uops[1].is_br connect pred_rename_stage.io.dec_uops[1].iw_p2_poisoned, dec_uops[1].iw_p2_poisoned connect pred_rename_stage.io.dec_uops[1].iw_p1_poisoned, dec_uops[1].iw_p1_poisoned connect pred_rename_stage.io.dec_uops[1].iw_state, dec_uops[1].iw_state connect pred_rename_stage.io.dec_uops[1].ctrl.is_std, dec_uops[1].ctrl.is_std connect pred_rename_stage.io.dec_uops[1].ctrl.is_sta, dec_uops[1].ctrl.is_sta connect pred_rename_stage.io.dec_uops[1].ctrl.is_load, dec_uops[1].ctrl.is_load connect pred_rename_stage.io.dec_uops[1].ctrl.csr_cmd, dec_uops[1].ctrl.csr_cmd connect pred_rename_stage.io.dec_uops[1].ctrl.fcn_dw, dec_uops[1].ctrl.fcn_dw connect pred_rename_stage.io.dec_uops[1].ctrl.op_fcn, dec_uops[1].ctrl.op_fcn connect pred_rename_stage.io.dec_uops[1].ctrl.imm_sel, dec_uops[1].ctrl.imm_sel connect pred_rename_stage.io.dec_uops[1].ctrl.op2_sel, dec_uops[1].ctrl.op2_sel connect pred_rename_stage.io.dec_uops[1].ctrl.op1_sel, dec_uops[1].ctrl.op1_sel connect pred_rename_stage.io.dec_uops[1].ctrl.br_type, dec_uops[1].ctrl.br_type connect pred_rename_stage.io.dec_uops[1].fu_code, dec_uops[1].fu_code connect pred_rename_stage.io.dec_uops[1].iq_type, dec_uops[1].iq_type connect pred_rename_stage.io.dec_uops[1].debug_pc, dec_uops[1].debug_pc connect pred_rename_stage.io.dec_uops[1].is_rvc, dec_uops[1].is_rvc connect pred_rename_stage.io.dec_uops[1].debug_inst, dec_uops[1].debug_inst connect pred_rename_stage.io.dec_uops[1].inst, dec_uops[1].inst connect pred_rename_stage.io.dec_uops[1].uopc, dec_uops[1].uopc connect pred_rename_stage.io.dec_uops[2].debug_tsrc, dec_uops[2].debug_tsrc connect pred_rename_stage.io.dec_uops[2].debug_fsrc, dec_uops[2].debug_fsrc connect pred_rename_stage.io.dec_uops[2].bp_xcpt_if, dec_uops[2].bp_xcpt_if connect pred_rename_stage.io.dec_uops[2].bp_debug_if, dec_uops[2].bp_debug_if connect pred_rename_stage.io.dec_uops[2].xcpt_ma_if, dec_uops[2].xcpt_ma_if connect pred_rename_stage.io.dec_uops[2].xcpt_ae_if, dec_uops[2].xcpt_ae_if connect pred_rename_stage.io.dec_uops[2].xcpt_pf_if, dec_uops[2].xcpt_pf_if connect pred_rename_stage.io.dec_uops[2].fp_single, dec_uops[2].fp_single connect pred_rename_stage.io.dec_uops[2].fp_val, dec_uops[2].fp_val connect pred_rename_stage.io.dec_uops[2].frs3_en, dec_uops[2].frs3_en connect pred_rename_stage.io.dec_uops[2].lrs2_rtype, dec_uops[2].lrs2_rtype connect pred_rename_stage.io.dec_uops[2].lrs1_rtype, dec_uops[2].lrs1_rtype connect pred_rename_stage.io.dec_uops[2].dst_rtype, dec_uops[2].dst_rtype connect pred_rename_stage.io.dec_uops[2].ldst_val, dec_uops[2].ldst_val connect pred_rename_stage.io.dec_uops[2].lrs3, dec_uops[2].lrs3 connect pred_rename_stage.io.dec_uops[2].lrs2, dec_uops[2].lrs2 connect pred_rename_stage.io.dec_uops[2].lrs1, dec_uops[2].lrs1 connect pred_rename_stage.io.dec_uops[2].ldst, dec_uops[2].ldst connect pred_rename_stage.io.dec_uops[2].ldst_is_rs1, dec_uops[2].ldst_is_rs1 connect pred_rename_stage.io.dec_uops[2].flush_on_commit, dec_uops[2].flush_on_commit connect pred_rename_stage.io.dec_uops[2].is_unique, dec_uops[2].is_unique connect pred_rename_stage.io.dec_uops[2].is_sys_pc2epc, dec_uops[2].is_sys_pc2epc connect pred_rename_stage.io.dec_uops[2].uses_stq, dec_uops[2].uses_stq connect pred_rename_stage.io.dec_uops[2].uses_ldq, dec_uops[2].uses_ldq connect pred_rename_stage.io.dec_uops[2].is_amo, dec_uops[2].is_amo connect pred_rename_stage.io.dec_uops[2].is_fencei, dec_uops[2].is_fencei connect pred_rename_stage.io.dec_uops[2].is_fence, dec_uops[2].is_fence connect pred_rename_stage.io.dec_uops[2].mem_signed, dec_uops[2].mem_signed connect pred_rename_stage.io.dec_uops[2].mem_size, dec_uops[2].mem_size connect pred_rename_stage.io.dec_uops[2].mem_cmd, dec_uops[2].mem_cmd connect pred_rename_stage.io.dec_uops[2].bypassable, dec_uops[2].bypassable connect pred_rename_stage.io.dec_uops[2].exc_cause, dec_uops[2].exc_cause connect pred_rename_stage.io.dec_uops[2].exception, dec_uops[2].exception connect pred_rename_stage.io.dec_uops[2].stale_pdst, dec_uops[2].stale_pdst connect pred_rename_stage.io.dec_uops[2].ppred_busy, dec_uops[2].ppred_busy connect pred_rename_stage.io.dec_uops[2].prs3_busy, dec_uops[2].prs3_busy connect pred_rename_stage.io.dec_uops[2].prs2_busy, dec_uops[2].prs2_busy connect pred_rename_stage.io.dec_uops[2].prs1_busy, dec_uops[2].prs1_busy connect pred_rename_stage.io.dec_uops[2].ppred, dec_uops[2].ppred connect pred_rename_stage.io.dec_uops[2].prs3, dec_uops[2].prs3 connect pred_rename_stage.io.dec_uops[2].prs2, dec_uops[2].prs2 connect pred_rename_stage.io.dec_uops[2].prs1, dec_uops[2].prs1 connect pred_rename_stage.io.dec_uops[2].pdst, dec_uops[2].pdst connect pred_rename_stage.io.dec_uops[2].rxq_idx, dec_uops[2].rxq_idx connect pred_rename_stage.io.dec_uops[2].stq_idx, dec_uops[2].stq_idx connect pred_rename_stage.io.dec_uops[2].ldq_idx, dec_uops[2].ldq_idx connect pred_rename_stage.io.dec_uops[2].rob_idx, dec_uops[2].rob_idx connect pred_rename_stage.io.dec_uops[2].csr_addr, dec_uops[2].csr_addr connect pred_rename_stage.io.dec_uops[2].imm_packed, dec_uops[2].imm_packed connect pred_rename_stage.io.dec_uops[2].taken, dec_uops[2].taken connect pred_rename_stage.io.dec_uops[2].pc_lob, dec_uops[2].pc_lob connect pred_rename_stage.io.dec_uops[2].edge_inst, dec_uops[2].edge_inst connect pred_rename_stage.io.dec_uops[2].ftq_idx, dec_uops[2].ftq_idx connect pred_rename_stage.io.dec_uops[2].br_tag, dec_uops[2].br_tag connect pred_rename_stage.io.dec_uops[2].br_mask, dec_uops[2].br_mask connect pred_rename_stage.io.dec_uops[2].is_sfb, dec_uops[2].is_sfb connect pred_rename_stage.io.dec_uops[2].is_jal, dec_uops[2].is_jal connect pred_rename_stage.io.dec_uops[2].is_jalr, dec_uops[2].is_jalr connect pred_rename_stage.io.dec_uops[2].is_br, dec_uops[2].is_br connect pred_rename_stage.io.dec_uops[2].iw_p2_poisoned, dec_uops[2].iw_p2_poisoned connect pred_rename_stage.io.dec_uops[2].iw_p1_poisoned, dec_uops[2].iw_p1_poisoned connect pred_rename_stage.io.dec_uops[2].iw_state, dec_uops[2].iw_state connect pred_rename_stage.io.dec_uops[2].ctrl.is_std, dec_uops[2].ctrl.is_std connect pred_rename_stage.io.dec_uops[2].ctrl.is_sta, dec_uops[2].ctrl.is_sta connect pred_rename_stage.io.dec_uops[2].ctrl.is_load, dec_uops[2].ctrl.is_load connect pred_rename_stage.io.dec_uops[2].ctrl.csr_cmd, dec_uops[2].ctrl.csr_cmd connect pred_rename_stage.io.dec_uops[2].ctrl.fcn_dw, dec_uops[2].ctrl.fcn_dw connect pred_rename_stage.io.dec_uops[2].ctrl.op_fcn, dec_uops[2].ctrl.op_fcn connect pred_rename_stage.io.dec_uops[2].ctrl.imm_sel, dec_uops[2].ctrl.imm_sel connect pred_rename_stage.io.dec_uops[2].ctrl.op2_sel, dec_uops[2].ctrl.op2_sel connect pred_rename_stage.io.dec_uops[2].ctrl.op1_sel, dec_uops[2].ctrl.op1_sel connect pred_rename_stage.io.dec_uops[2].ctrl.br_type, dec_uops[2].ctrl.br_type connect pred_rename_stage.io.dec_uops[2].fu_code, dec_uops[2].fu_code connect pred_rename_stage.io.dec_uops[2].iq_type, dec_uops[2].iq_type connect pred_rename_stage.io.dec_uops[2].debug_pc, dec_uops[2].debug_pc connect pred_rename_stage.io.dec_uops[2].is_rvc, dec_uops[2].is_rvc connect pred_rename_stage.io.dec_uops[2].debug_inst, dec_uops[2].debug_inst connect pred_rename_stage.io.dec_uops[2].inst, dec_uops[2].inst connect pred_rename_stage.io.dec_uops[2].uopc, dec_uops[2].uopc connect pred_rename_stage.io.dis_fire[0], dis_fire[0] connect pred_rename_stage.io.dis_fire[1], dis_fire[1] connect pred_rename_stage.io.dis_fire[2], dis_fire[2] connect pred_rename_stage.io.dis_ready, dis_ready connect pred_rename_stage.io.com_valids[0], rob.io.commit.valids[0] connect pred_rename_stage.io.com_valids[1], rob.io.commit.valids[1] connect pred_rename_stage.io.com_valids[2], rob.io.commit.valids[2] connect pred_rename_stage.io.com_uops[0].debug_tsrc, rob.io.commit.uops[0].debug_tsrc connect pred_rename_stage.io.com_uops[0].debug_fsrc, rob.io.commit.uops[0].debug_fsrc connect pred_rename_stage.io.com_uops[0].bp_xcpt_if, rob.io.commit.uops[0].bp_xcpt_if connect pred_rename_stage.io.com_uops[0].bp_debug_if, rob.io.commit.uops[0].bp_debug_if connect pred_rename_stage.io.com_uops[0].xcpt_ma_if, rob.io.commit.uops[0].xcpt_ma_if connect pred_rename_stage.io.com_uops[0].xcpt_ae_if, rob.io.commit.uops[0].xcpt_ae_if connect pred_rename_stage.io.com_uops[0].xcpt_pf_if, rob.io.commit.uops[0].xcpt_pf_if connect pred_rename_stage.io.com_uops[0].fp_single, rob.io.commit.uops[0].fp_single connect pred_rename_stage.io.com_uops[0].fp_val, rob.io.commit.uops[0].fp_val connect pred_rename_stage.io.com_uops[0].frs3_en, rob.io.commit.uops[0].frs3_en connect pred_rename_stage.io.com_uops[0].lrs2_rtype, rob.io.commit.uops[0].lrs2_rtype connect pred_rename_stage.io.com_uops[0].lrs1_rtype, rob.io.commit.uops[0].lrs1_rtype connect pred_rename_stage.io.com_uops[0].dst_rtype, rob.io.commit.uops[0].dst_rtype connect pred_rename_stage.io.com_uops[0].ldst_val, rob.io.commit.uops[0].ldst_val connect pred_rename_stage.io.com_uops[0].lrs3, rob.io.commit.uops[0].lrs3 connect pred_rename_stage.io.com_uops[0].lrs2, rob.io.commit.uops[0].lrs2 connect pred_rename_stage.io.com_uops[0].lrs1, rob.io.commit.uops[0].lrs1 connect pred_rename_stage.io.com_uops[0].ldst, rob.io.commit.uops[0].ldst connect pred_rename_stage.io.com_uops[0].ldst_is_rs1, rob.io.commit.uops[0].ldst_is_rs1 connect pred_rename_stage.io.com_uops[0].flush_on_commit, rob.io.commit.uops[0].flush_on_commit connect pred_rename_stage.io.com_uops[0].is_unique, rob.io.commit.uops[0].is_unique connect pred_rename_stage.io.com_uops[0].is_sys_pc2epc, rob.io.commit.uops[0].is_sys_pc2epc connect pred_rename_stage.io.com_uops[0].uses_stq, rob.io.commit.uops[0].uses_stq connect pred_rename_stage.io.com_uops[0].uses_ldq, rob.io.commit.uops[0].uses_ldq connect pred_rename_stage.io.com_uops[0].is_amo, rob.io.commit.uops[0].is_amo connect pred_rename_stage.io.com_uops[0].is_fencei, rob.io.commit.uops[0].is_fencei connect pred_rename_stage.io.com_uops[0].is_fence, rob.io.commit.uops[0].is_fence connect pred_rename_stage.io.com_uops[0].mem_signed, rob.io.commit.uops[0].mem_signed connect pred_rename_stage.io.com_uops[0].mem_size, rob.io.commit.uops[0].mem_size connect pred_rename_stage.io.com_uops[0].mem_cmd, rob.io.commit.uops[0].mem_cmd connect pred_rename_stage.io.com_uops[0].bypassable, rob.io.commit.uops[0].bypassable connect pred_rename_stage.io.com_uops[0].exc_cause, rob.io.commit.uops[0].exc_cause connect pred_rename_stage.io.com_uops[0].exception, rob.io.commit.uops[0].exception connect pred_rename_stage.io.com_uops[0].stale_pdst, rob.io.commit.uops[0].stale_pdst connect pred_rename_stage.io.com_uops[0].ppred_busy, rob.io.commit.uops[0].ppred_busy connect pred_rename_stage.io.com_uops[0].prs3_busy, rob.io.commit.uops[0].prs3_busy connect pred_rename_stage.io.com_uops[0].prs2_busy, rob.io.commit.uops[0].prs2_busy connect pred_rename_stage.io.com_uops[0].prs1_busy, rob.io.commit.uops[0].prs1_busy connect pred_rename_stage.io.com_uops[0].ppred, rob.io.commit.uops[0].ppred connect pred_rename_stage.io.com_uops[0].prs3, rob.io.commit.uops[0].prs3 connect pred_rename_stage.io.com_uops[0].prs2, rob.io.commit.uops[0].prs2 connect pred_rename_stage.io.com_uops[0].prs1, rob.io.commit.uops[0].prs1 connect pred_rename_stage.io.com_uops[0].pdst, rob.io.commit.uops[0].pdst connect pred_rename_stage.io.com_uops[0].rxq_idx, rob.io.commit.uops[0].rxq_idx connect pred_rename_stage.io.com_uops[0].stq_idx, rob.io.commit.uops[0].stq_idx connect pred_rename_stage.io.com_uops[0].ldq_idx, rob.io.commit.uops[0].ldq_idx connect pred_rename_stage.io.com_uops[0].rob_idx, rob.io.commit.uops[0].rob_idx connect pred_rename_stage.io.com_uops[0].csr_addr, rob.io.commit.uops[0].csr_addr connect pred_rename_stage.io.com_uops[0].imm_packed, rob.io.commit.uops[0].imm_packed connect pred_rename_stage.io.com_uops[0].taken, rob.io.commit.uops[0].taken connect pred_rename_stage.io.com_uops[0].pc_lob, rob.io.commit.uops[0].pc_lob connect pred_rename_stage.io.com_uops[0].edge_inst, rob.io.commit.uops[0].edge_inst connect pred_rename_stage.io.com_uops[0].ftq_idx, rob.io.commit.uops[0].ftq_idx connect pred_rename_stage.io.com_uops[0].br_tag, rob.io.commit.uops[0].br_tag connect pred_rename_stage.io.com_uops[0].br_mask, rob.io.commit.uops[0].br_mask connect pred_rename_stage.io.com_uops[0].is_sfb, rob.io.commit.uops[0].is_sfb connect pred_rename_stage.io.com_uops[0].is_jal, rob.io.commit.uops[0].is_jal connect pred_rename_stage.io.com_uops[0].is_jalr, rob.io.commit.uops[0].is_jalr connect pred_rename_stage.io.com_uops[0].is_br, rob.io.commit.uops[0].is_br connect pred_rename_stage.io.com_uops[0].iw_p2_poisoned, rob.io.commit.uops[0].iw_p2_poisoned connect pred_rename_stage.io.com_uops[0].iw_p1_poisoned, rob.io.commit.uops[0].iw_p1_poisoned connect pred_rename_stage.io.com_uops[0].iw_state, rob.io.commit.uops[0].iw_state connect pred_rename_stage.io.com_uops[0].ctrl.is_std, rob.io.commit.uops[0].ctrl.is_std connect pred_rename_stage.io.com_uops[0].ctrl.is_sta, rob.io.commit.uops[0].ctrl.is_sta connect pred_rename_stage.io.com_uops[0].ctrl.is_load, rob.io.commit.uops[0].ctrl.is_load connect pred_rename_stage.io.com_uops[0].ctrl.csr_cmd, rob.io.commit.uops[0].ctrl.csr_cmd connect pred_rename_stage.io.com_uops[0].ctrl.fcn_dw, rob.io.commit.uops[0].ctrl.fcn_dw connect pred_rename_stage.io.com_uops[0].ctrl.op_fcn, rob.io.commit.uops[0].ctrl.op_fcn connect pred_rename_stage.io.com_uops[0].ctrl.imm_sel, rob.io.commit.uops[0].ctrl.imm_sel connect pred_rename_stage.io.com_uops[0].ctrl.op2_sel, rob.io.commit.uops[0].ctrl.op2_sel connect pred_rename_stage.io.com_uops[0].ctrl.op1_sel, rob.io.commit.uops[0].ctrl.op1_sel connect pred_rename_stage.io.com_uops[0].ctrl.br_type, rob.io.commit.uops[0].ctrl.br_type connect pred_rename_stage.io.com_uops[0].fu_code, rob.io.commit.uops[0].fu_code connect pred_rename_stage.io.com_uops[0].iq_type, rob.io.commit.uops[0].iq_type connect pred_rename_stage.io.com_uops[0].debug_pc, rob.io.commit.uops[0].debug_pc connect pred_rename_stage.io.com_uops[0].is_rvc, rob.io.commit.uops[0].is_rvc connect pred_rename_stage.io.com_uops[0].debug_inst, rob.io.commit.uops[0].debug_inst connect pred_rename_stage.io.com_uops[0].inst, rob.io.commit.uops[0].inst connect pred_rename_stage.io.com_uops[0].uopc, rob.io.commit.uops[0].uopc connect pred_rename_stage.io.com_uops[1].debug_tsrc, rob.io.commit.uops[1].debug_tsrc connect pred_rename_stage.io.com_uops[1].debug_fsrc, rob.io.commit.uops[1].debug_fsrc connect pred_rename_stage.io.com_uops[1].bp_xcpt_if, rob.io.commit.uops[1].bp_xcpt_if connect pred_rename_stage.io.com_uops[1].bp_debug_if, rob.io.commit.uops[1].bp_debug_if connect pred_rename_stage.io.com_uops[1].xcpt_ma_if, rob.io.commit.uops[1].xcpt_ma_if connect pred_rename_stage.io.com_uops[1].xcpt_ae_if, rob.io.commit.uops[1].xcpt_ae_if connect pred_rename_stage.io.com_uops[1].xcpt_pf_if, rob.io.commit.uops[1].xcpt_pf_if connect pred_rename_stage.io.com_uops[1].fp_single, rob.io.commit.uops[1].fp_single connect pred_rename_stage.io.com_uops[1].fp_val, rob.io.commit.uops[1].fp_val connect pred_rename_stage.io.com_uops[1].frs3_en, rob.io.commit.uops[1].frs3_en connect pred_rename_stage.io.com_uops[1].lrs2_rtype, rob.io.commit.uops[1].lrs2_rtype connect pred_rename_stage.io.com_uops[1].lrs1_rtype, rob.io.commit.uops[1].lrs1_rtype connect pred_rename_stage.io.com_uops[1].dst_rtype, rob.io.commit.uops[1].dst_rtype connect pred_rename_stage.io.com_uops[1].ldst_val, rob.io.commit.uops[1].ldst_val connect pred_rename_stage.io.com_uops[1].lrs3, rob.io.commit.uops[1].lrs3 connect pred_rename_stage.io.com_uops[1].lrs2, rob.io.commit.uops[1].lrs2 connect pred_rename_stage.io.com_uops[1].lrs1, rob.io.commit.uops[1].lrs1 connect pred_rename_stage.io.com_uops[1].ldst, rob.io.commit.uops[1].ldst connect pred_rename_stage.io.com_uops[1].ldst_is_rs1, rob.io.commit.uops[1].ldst_is_rs1 connect pred_rename_stage.io.com_uops[1].flush_on_commit, rob.io.commit.uops[1].flush_on_commit connect pred_rename_stage.io.com_uops[1].is_unique, rob.io.commit.uops[1].is_unique connect pred_rename_stage.io.com_uops[1].is_sys_pc2epc, rob.io.commit.uops[1].is_sys_pc2epc connect pred_rename_stage.io.com_uops[1].uses_stq, rob.io.commit.uops[1].uses_stq connect pred_rename_stage.io.com_uops[1].uses_ldq, rob.io.commit.uops[1].uses_ldq connect pred_rename_stage.io.com_uops[1].is_amo, rob.io.commit.uops[1].is_amo connect pred_rename_stage.io.com_uops[1].is_fencei, rob.io.commit.uops[1].is_fencei connect pred_rename_stage.io.com_uops[1].is_fence, rob.io.commit.uops[1].is_fence connect pred_rename_stage.io.com_uops[1].mem_signed, rob.io.commit.uops[1].mem_signed connect pred_rename_stage.io.com_uops[1].mem_size, rob.io.commit.uops[1].mem_size connect pred_rename_stage.io.com_uops[1].mem_cmd, rob.io.commit.uops[1].mem_cmd connect pred_rename_stage.io.com_uops[1].bypassable, rob.io.commit.uops[1].bypassable connect pred_rename_stage.io.com_uops[1].exc_cause, rob.io.commit.uops[1].exc_cause connect pred_rename_stage.io.com_uops[1].exception, rob.io.commit.uops[1].exception connect pred_rename_stage.io.com_uops[1].stale_pdst, rob.io.commit.uops[1].stale_pdst connect pred_rename_stage.io.com_uops[1].ppred_busy, rob.io.commit.uops[1].ppred_busy connect pred_rename_stage.io.com_uops[1].prs3_busy, rob.io.commit.uops[1].prs3_busy connect pred_rename_stage.io.com_uops[1].prs2_busy, rob.io.commit.uops[1].prs2_busy connect pred_rename_stage.io.com_uops[1].prs1_busy, rob.io.commit.uops[1].prs1_busy connect pred_rename_stage.io.com_uops[1].ppred, rob.io.commit.uops[1].ppred connect pred_rename_stage.io.com_uops[1].prs3, rob.io.commit.uops[1].prs3 connect pred_rename_stage.io.com_uops[1].prs2, rob.io.commit.uops[1].prs2 connect pred_rename_stage.io.com_uops[1].prs1, rob.io.commit.uops[1].prs1 connect pred_rename_stage.io.com_uops[1].pdst, rob.io.commit.uops[1].pdst connect pred_rename_stage.io.com_uops[1].rxq_idx, rob.io.commit.uops[1].rxq_idx connect pred_rename_stage.io.com_uops[1].stq_idx, rob.io.commit.uops[1].stq_idx connect pred_rename_stage.io.com_uops[1].ldq_idx, rob.io.commit.uops[1].ldq_idx connect pred_rename_stage.io.com_uops[1].rob_idx, rob.io.commit.uops[1].rob_idx connect pred_rename_stage.io.com_uops[1].csr_addr, rob.io.commit.uops[1].csr_addr connect pred_rename_stage.io.com_uops[1].imm_packed, rob.io.commit.uops[1].imm_packed connect pred_rename_stage.io.com_uops[1].taken, rob.io.commit.uops[1].taken connect pred_rename_stage.io.com_uops[1].pc_lob, rob.io.commit.uops[1].pc_lob connect pred_rename_stage.io.com_uops[1].edge_inst, rob.io.commit.uops[1].edge_inst connect pred_rename_stage.io.com_uops[1].ftq_idx, rob.io.commit.uops[1].ftq_idx connect pred_rename_stage.io.com_uops[1].br_tag, rob.io.commit.uops[1].br_tag connect pred_rename_stage.io.com_uops[1].br_mask, rob.io.commit.uops[1].br_mask connect pred_rename_stage.io.com_uops[1].is_sfb, rob.io.commit.uops[1].is_sfb connect pred_rename_stage.io.com_uops[1].is_jal, rob.io.commit.uops[1].is_jal connect pred_rename_stage.io.com_uops[1].is_jalr, rob.io.commit.uops[1].is_jalr connect pred_rename_stage.io.com_uops[1].is_br, rob.io.commit.uops[1].is_br connect pred_rename_stage.io.com_uops[1].iw_p2_poisoned, rob.io.commit.uops[1].iw_p2_poisoned connect pred_rename_stage.io.com_uops[1].iw_p1_poisoned, rob.io.commit.uops[1].iw_p1_poisoned connect pred_rename_stage.io.com_uops[1].iw_state, rob.io.commit.uops[1].iw_state connect pred_rename_stage.io.com_uops[1].ctrl.is_std, rob.io.commit.uops[1].ctrl.is_std connect pred_rename_stage.io.com_uops[1].ctrl.is_sta, rob.io.commit.uops[1].ctrl.is_sta connect pred_rename_stage.io.com_uops[1].ctrl.is_load, rob.io.commit.uops[1].ctrl.is_load connect pred_rename_stage.io.com_uops[1].ctrl.csr_cmd, rob.io.commit.uops[1].ctrl.csr_cmd connect pred_rename_stage.io.com_uops[1].ctrl.fcn_dw, rob.io.commit.uops[1].ctrl.fcn_dw connect pred_rename_stage.io.com_uops[1].ctrl.op_fcn, rob.io.commit.uops[1].ctrl.op_fcn connect pred_rename_stage.io.com_uops[1].ctrl.imm_sel, rob.io.commit.uops[1].ctrl.imm_sel connect pred_rename_stage.io.com_uops[1].ctrl.op2_sel, rob.io.commit.uops[1].ctrl.op2_sel connect pred_rename_stage.io.com_uops[1].ctrl.op1_sel, rob.io.commit.uops[1].ctrl.op1_sel connect pred_rename_stage.io.com_uops[1].ctrl.br_type, rob.io.commit.uops[1].ctrl.br_type connect pred_rename_stage.io.com_uops[1].fu_code, rob.io.commit.uops[1].fu_code connect pred_rename_stage.io.com_uops[1].iq_type, rob.io.commit.uops[1].iq_type connect pred_rename_stage.io.com_uops[1].debug_pc, rob.io.commit.uops[1].debug_pc connect pred_rename_stage.io.com_uops[1].is_rvc, rob.io.commit.uops[1].is_rvc connect pred_rename_stage.io.com_uops[1].debug_inst, rob.io.commit.uops[1].debug_inst connect pred_rename_stage.io.com_uops[1].inst, rob.io.commit.uops[1].inst connect pred_rename_stage.io.com_uops[1].uopc, rob.io.commit.uops[1].uopc connect pred_rename_stage.io.com_uops[2].debug_tsrc, rob.io.commit.uops[2].debug_tsrc connect pred_rename_stage.io.com_uops[2].debug_fsrc, rob.io.commit.uops[2].debug_fsrc connect pred_rename_stage.io.com_uops[2].bp_xcpt_if, rob.io.commit.uops[2].bp_xcpt_if connect pred_rename_stage.io.com_uops[2].bp_debug_if, rob.io.commit.uops[2].bp_debug_if connect pred_rename_stage.io.com_uops[2].xcpt_ma_if, rob.io.commit.uops[2].xcpt_ma_if connect pred_rename_stage.io.com_uops[2].xcpt_ae_if, rob.io.commit.uops[2].xcpt_ae_if connect pred_rename_stage.io.com_uops[2].xcpt_pf_if, rob.io.commit.uops[2].xcpt_pf_if connect pred_rename_stage.io.com_uops[2].fp_single, rob.io.commit.uops[2].fp_single connect pred_rename_stage.io.com_uops[2].fp_val, rob.io.commit.uops[2].fp_val connect pred_rename_stage.io.com_uops[2].frs3_en, rob.io.commit.uops[2].frs3_en connect pred_rename_stage.io.com_uops[2].lrs2_rtype, rob.io.commit.uops[2].lrs2_rtype connect pred_rename_stage.io.com_uops[2].lrs1_rtype, rob.io.commit.uops[2].lrs1_rtype connect pred_rename_stage.io.com_uops[2].dst_rtype, rob.io.commit.uops[2].dst_rtype connect pred_rename_stage.io.com_uops[2].ldst_val, rob.io.commit.uops[2].ldst_val connect pred_rename_stage.io.com_uops[2].lrs3, rob.io.commit.uops[2].lrs3 connect pred_rename_stage.io.com_uops[2].lrs2, rob.io.commit.uops[2].lrs2 connect pred_rename_stage.io.com_uops[2].lrs1, rob.io.commit.uops[2].lrs1 connect pred_rename_stage.io.com_uops[2].ldst, rob.io.commit.uops[2].ldst connect pred_rename_stage.io.com_uops[2].ldst_is_rs1, rob.io.commit.uops[2].ldst_is_rs1 connect pred_rename_stage.io.com_uops[2].flush_on_commit, rob.io.commit.uops[2].flush_on_commit connect pred_rename_stage.io.com_uops[2].is_unique, rob.io.commit.uops[2].is_unique connect pred_rename_stage.io.com_uops[2].is_sys_pc2epc, rob.io.commit.uops[2].is_sys_pc2epc connect pred_rename_stage.io.com_uops[2].uses_stq, rob.io.commit.uops[2].uses_stq connect pred_rename_stage.io.com_uops[2].uses_ldq, rob.io.commit.uops[2].uses_ldq connect pred_rename_stage.io.com_uops[2].is_amo, rob.io.commit.uops[2].is_amo connect pred_rename_stage.io.com_uops[2].is_fencei, rob.io.commit.uops[2].is_fencei connect pred_rename_stage.io.com_uops[2].is_fence, rob.io.commit.uops[2].is_fence connect pred_rename_stage.io.com_uops[2].mem_signed, rob.io.commit.uops[2].mem_signed connect pred_rename_stage.io.com_uops[2].mem_size, rob.io.commit.uops[2].mem_size connect pred_rename_stage.io.com_uops[2].mem_cmd, rob.io.commit.uops[2].mem_cmd connect pred_rename_stage.io.com_uops[2].bypassable, rob.io.commit.uops[2].bypassable connect pred_rename_stage.io.com_uops[2].exc_cause, rob.io.commit.uops[2].exc_cause connect pred_rename_stage.io.com_uops[2].exception, rob.io.commit.uops[2].exception connect pred_rename_stage.io.com_uops[2].stale_pdst, rob.io.commit.uops[2].stale_pdst connect pred_rename_stage.io.com_uops[2].ppred_busy, rob.io.commit.uops[2].ppred_busy connect pred_rename_stage.io.com_uops[2].prs3_busy, rob.io.commit.uops[2].prs3_busy connect pred_rename_stage.io.com_uops[2].prs2_busy, rob.io.commit.uops[2].prs2_busy connect pred_rename_stage.io.com_uops[2].prs1_busy, rob.io.commit.uops[2].prs1_busy connect pred_rename_stage.io.com_uops[2].ppred, rob.io.commit.uops[2].ppred connect pred_rename_stage.io.com_uops[2].prs3, rob.io.commit.uops[2].prs3 connect pred_rename_stage.io.com_uops[2].prs2, rob.io.commit.uops[2].prs2 connect pred_rename_stage.io.com_uops[2].prs1, rob.io.commit.uops[2].prs1 connect pred_rename_stage.io.com_uops[2].pdst, rob.io.commit.uops[2].pdst connect pred_rename_stage.io.com_uops[2].rxq_idx, rob.io.commit.uops[2].rxq_idx connect pred_rename_stage.io.com_uops[2].stq_idx, rob.io.commit.uops[2].stq_idx connect pred_rename_stage.io.com_uops[2].ldq_idx, rob.io.commit.uops[2].ldq_idx connect pred_rename_stage.io.com_uops[2].rob_idx, rob.io.commit.uops[2].rob_idx connect pred_rename_stage.io.com_uops[2].csr_addr, rob.io.commit.uops[2].csr_addr connect pred_rename_stage.io.com_uops[2].imm_packed, rob.io.commit.uops[2].imm_packed connect pred_rename_stage.io.com_uops[2].taken, rob.io.commit.uops[2].taken connect pred_rename_stage.io.com_uops[2].pc_lob, rob.io.commit.uops[2].pc_lob connect pred_rename_stage.io.com_uops[2].edge_inst, rob.io.commit.uops[2].edge_inst connect pred_rename_stage.io.com_uops[2].ftq_idx, rob.io.commit.uops[2].ftq_idx connect pred_rename_stage.io.com_uops[2].br_tag, rob.io.commit.uops[2].br_tag connect pred_rename_stage.io.com_uops[2].br_mask, rob.io.commit.uops[2].br_mask connect pred_rename_stage.io.com_uops[2].is_sfb, rob.io.commit.uops[2].is_sfb connect pred_rename_stage.io.com_uops[2].is_jal, rob.io.commit.uops[2].is_jal connect pred_rename_stage.io.com_uops[2].is_jalr, rob.io.commit.uops[2].is_jalr connect pred_rename_stage.io.com_uops[2].is_br, rob.io.commit.uops[2].is_br connect pred_rename_stage.io.com_uops[2].iw_p2_poisoned, rob.io.commit.uops[2].iw_p2_poisoned connect pred_rename_stage.io.com_uops[2].iw_p1_poisoned, rob.io.commit.uops[2].iw_p1_poisoned connect pred_rename_stage.io.com_uops[2].iw_state, rob.io.commit.uops[2].iw_state connect pred_rename_stage.io.com_uops[2].ctrl.is_std, rob.io.commit.uops[2].ctrl.is_std connect pred_rename_stage.io.com_uops[2].ctrl.is_sta, rob.io.commit.uops[2].ctrl.is_sta connect pred_rename_stage.io.com_uops[2].ctrl.is_load, rob.io.commit.uops[2].ctrl.is_load connect pred_rename_stage.io.com_uops[2].ctrl.csr_cmd, rob.io.commit.uops[2].ctrl.csr_cmd connect pred_rename_stage.io.com_uops[2].ctrl.fcn_dw, rob.io.commit.uops[2].ctrl.fcn_dw connect pred_rename_stage.io.com_uops[2].ctrl.op_fcn, rob.io.commit.uops[2].ctrl.op_fcn connect pred_rename_stage.io.com_uops[2].ctrl.imm_sel, rob.io.commit.uops[2].ctrl.imm_sel connect pred_rename_stage.io.com_uops[2].ctrl.op2_sel, rob.io.commit.uops[2].ctrl.op2_sel connect pred_rename_stage.io.com_uops[2].ctrl.op1_sel, rob.io.commit.uops[2].ctrl.op1_sel connect pred_rename_stage.io.com_uops[2].ctrl.br_type, rob.io.commit.uops[2].ctrl.br_type connect pred_rename_stage.io.com_uops[2].fu_code, rob.io.commit.uops[2].fu_code connect pred_rename_stage.io.com_uops[2].iq_type, rob.io.commit.uops[2].iq_type connect pred_rename_stage.io.com_uops[2].debug_pc, rob.io.commit.uops[2].debug_pc connect pred_rename_stage.io.com_uops[2].is_rvc, rob.io.commit.uops[2].is_rvc connect pred_rename_stage.io.com_uops[2].debug_inst, rob.io.commit.uops[2].debug_inst connect pred_rename_stage.io.com_uops[2].inst, rob.io.commit.uops[2].inst connect pred_rename_stage.io.com_uops[2].uopc, rob.io.commit.uops[2].uopc connect pred_rename_stage.io.rbk_valids[0], rob.io.commit.rbk_valids[0] connect pred_rename_stage.io.rbk_valids[1], rob.io.commit.rbk_valids[1] connect pred_rename_stage.io.rbk_valids[2], rob.io.commit.rbk_valids[2] connect pred_rename_stage.io.rollback, rob.io.commit.rollback connect dis_uops, rename_stage.io.ren2_uops connect dis_valids, rename_stage.io.ren2_mask connect ren_stalls, rename_stage.io.ren_stalls wire p_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate p_uop.debug_tsrc invalidate p_uop.debug_fsrc invalidate p_uop.bp_xcpt_if invalidate p_uop.bp_debug_if invalidate p_uop.xcpt_ma_if invalidate p_uop.xcpt_ae_if invalidate p_uop.xcpt_pf_if invalidate p_uop.fp_single invalidate p_uop.fp_val invalidate p_uop.frs3_en invalidate p_uop.lrs2_rtype invalidate p_uop.lrs1_rtype invalidate p_uop.dst_rtype invalidate p_uop.ldst_val invalidate p_uop.lrs3 invalidate p_uop.lrs2 invalidate p_uop.lrs1 invalidate p_uop.ldst invalidate p_uop.ldst_is_rs1 invalidate p_uop.flush_on_commit invalidate p_uop.is_unique invalidate p_uop.is_sys_pc2epc invalidate p_uop.uses_stq invalidate p_uop.uses_ldq invalidate p_uop.is_amo invalidate p_uop.is_fencei invalidate p_uop.is_fence invalidate p_uop.mem_signed invalidate p_uop.mem_size invalidate p_uop.mem_cmd invalidate p_uop.bypassable invalidate p_uop.exc_cause invalidate p_uop.exception invalidate p_uop.stale_pdst invalidate p_uop.ppred_busy invalidate p_uop.prs3_busy invalidate p_uop.prs2_busy invalidate p_uop.prs1_busy invalidate p_uop.ppred invalidate p_uop.prs3 invalidate p_uop.prs2 invalidate p_uop.prs1 invalidate p_uop.pdst invalidate p_uop.rxq_idx invalidate p_uop.stq_idx invalidate p_uop.ldq_idx invalidate p_uop.rob_idx invalidate p_uop.csr_addr invalidate p_uop.imm_packed invalidate p_uop.taken invalidate p_uop.pc_lob invalidate p_uop.edge_inst invalidate p_uop.ftq_idx invalidate p_uop.br_tag invalidate p_uop.br_mask invalidate p_uop.is_sfb invalidate p_uop.is_jal invalidate p_uop.is_jalr invalidate p_uop.is_br invalidate p_uop.iw_p2_poisoned invalidate p_uop.iw_p1_poisoned invalidate p_uop.iw_state invalidate p_uop.ctrl.is_std invalidate p_uop.ctrl.is_sta invalidate p_uop.ctrl.is_load invalidate p_uop.ctrl.csr_cmd invalidate p_uop.ctrl.fcn_dw invalidate p_uop.ctrl.op_fcn invalidate p_uop.ctrl.imm_sel invalidate p_uop.ctrl.op2_sel invalidate p_uop.ctrl.op1_sel invalidate p_uop.ctrl.br_type invalidate p_uop.fu_code invalidate p_uop.iq_type invalidate p_uop.debug_pc invalidate p_uop.is_rvc invalidate p_uop.debug_inst invalidate p_uop.inst invalidate p_uop.uopc connect p_uop.uopc, UInt<7>(0h0) connect p_uop.bypassable, UInt<1>(0h0) connect p_uop.fp_val, UInt<1>(0h0) connect p_uop.uses_stq, UInt<1>(0h0) connect p_uop.uses_ldq, UInt<1>(0h0) connect p_uop.pdst, UInt<1>(0h0) connect p_uop.dst_rtype, UInt<2>(0h2) wire p_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate p_uop_cs.is_std invalidate p_uop_cs.is_sta invalidate p_uop_cs.is_load invalidate p_uop_cs.csr_cmd invalidate p_uop_cs.fcn_dw invalidate p_uop_cs.op_fcn invalidate p_uop_cs.imm_sel invalidate p_uop_cs.op2_sel invalidate p_uop_cs.op1_sel invalidate p_uop_cs.br_type connect p_uop_cs.br_type, UInt<4>(0h0) connect p_uop_cs.csr_cmd, UInt<3>(0h0) connect p_uop_cs.is_load, UInt<1>(0h0) connect p_uop_cs.is_sta, UInt<1>(0h0) connect p_uop_cs.is_std, UInt<1>(0h0) connect p_uop.ctrl, p_uop_cs node _dis_uops_0_prs1_T = eq(dis_uops[0].lrs1_rtype, UInt<2>(0h1)) node _dis_uops_0_prs1_T_1 = eq(dis_uops[0].lrs1_rtype, UInt<2>(0h0)) node _dis_uops_0_prs1_T_2 = mux(_dis_uops_0_prs1_T_1, rename_stage.io.ren2_uops[0].prs1, dis_uops[0].lrs1) node _dis_uops_0_prs1_T_3 = mux(_dis_uops_0_prs1_T, fp_rename_stage.io.ren2_uops[0].prs1, _dis_uops_0_prs1_T_2) connect dis_uops[0].prs1, _dis_uops_0_prs1_T_3 node _dis_uops_0_prs2_T = eq(dis_uops[0].lrs2_rtype, UInt<2>(0h1)) node _dis_uops_0_prs2_T_1 = mux(_dis_uops_0_prs2_T, fp_rename_stage.io.ren2_uops[0].prs2, rename_stage.io.ren2_uops[0].prs2) connect dis_uops[0].prs2, _dis_uops_0_prs2_T_1 connect dis_uops[0].prs3, fp_rename_stage.io.ren2_uops[0].prs3 connect dis_uops[0].ppred, p_uop.ppred node _dis_uops_0_pdst_T = eq(dis_uops[0].dst_rtype, UInt<2>(0h1)) node _dis_uops_0_pdst_T_1 = eq(dis_uops[0].dst_rtype, UInt<2>(0h0)) node _dis_uops_0_pdst_T_2 = mux(_dis_uops_0_pdst_T_1, rename_stage.io.ren2_uops[0].pdst, p_uop.pdst) node _dis_uops_0_pdst_T_3 = mux(_dis_uops_0_pdst_T, fp_rename_stage.io.ren2_uops[0].pdst, _dis_uops_0_pdst_T_2) connect dis_uops[0].pdst, _dis_uops_0_pdst_T_3 node _dis_uops_0_stale_pdst_T = eq(dis_uops[0].dst_rtype, UInt<2>(0h1)) node _dis_uops_0_stale_pdst_T_1 = mux(_dis_uops_0_stale_pdst_T, fp_rename_stage.io.ren2_uops[0].stale_pdst, rename_stage.io.ren2_uops[0].stale_pdst) connect dis_uops[0].stale_pdst, _dis_uops_0_stale_pdst_T_1 node _dis_uops_0_prs1_busy_T = eq(dis_uops[0].lrs1_rtype, UInt<2>(0h0)) node _dis_uops_0_prs1_busy_T_1 = and(rename_stage.io.ren2_uops[0].prs1_busy, _dis_uops_0_prs1_busy_T) node _dis_uops_0_prs1_busy_T_2 = eq(dis_uops[0].lrs1_rtype, UInt<2>(0h1)) node _dis_uops_0_prs1_busy_T_3 = and(fp_rename_stage.io.ren2_uops[0].prs1_busy, _dis_uops_0_prs1_busy_T_2) node _dis_uops_0_prs1_busy_T_4 = or(_dis_uops_0_prs1_busy_T_1, _dis_uops_0_prs1_busy_T_3) connect dis_uops[0].prs1_busy, _dis_uops_0_prs1_busy_T_4 node _dis_uops_0_prs2_busy_T = eq(dis_uops[0].lrs2_rtype, UInt<2>(0h0)) node _dis_uops_0_prs2_busy_T_1 = and(rename_stage.io.ren2_uops[0].prs2_busy, _dis_uops_0_prs2_busy_T) node _dis_uops_0_prs2_busy_T_2 = eq(dis_uops[0].lrs2_rtype, UInt<2>(0h1)) node _dis_uops_0_prs2_busy_T_3 = and(fp_rename_stage.io.ren2_uops[0].prs2_busy, _dis_uops_0_prs2_busy_T_2) node _dis_uops_0_prs2_busy_T_4 = or(_dis_uops_0_prs2_busy_T_1, _dis_uops_0_prs2_busy_T_3) connect dis_uops[0].prs2_busy, _dis_uops_0_prs2_busy_T_4 node _dis_uops_0_prs3_busy_T = and(fp_rename_stage.io.ren2_uops[0].prs3_busy, dis_uops[0].frs3_en) connect dis_uops[0].prs3_busy, _dis_uops_0_prs3_busy_T node _dis_uops_0_ppred_busy_T = eq(dis_uops[0].is_br, UInt<1>(0h0)) node _dis_uops_0_ppred_busy_T_1 = and(_dis_uops_0_ppred_busy_T, dis_uops[0].is_sfb) node _dis_uops_0_ppred_busy_T_2 = and(_dis_uops_0_ppred_busy_T_1, UInt<1>(0h0)) node _dis_uops_0_ppred_busy_T_3 = and(p_uop.ppred_busy, _dis_uops_0_ppred_busy_T_2) connect dis_uops[0].ppred_busy, _dis_uops_0_ppred_busy_T_3 node _ren_stalls_0_T = or(rename_stage.io.ren_stalls[0], fp_rename_stage.io.ren_stalls[0]) node _ren_stalls_0_T_1 = or(_ren_stalls_0_T, UInt<1>(0h0)) connect ren_stalls[0], _ren_stalls_0_T_1 wire p_uop_1 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate p_uop_1.debug_tsrc invalidate p_uop_1.debug_fsrc invalidate p_uop_1.bp_xcpt_if invalidate p_uop_1.bp_debug_if invalidate p_uop_1.xcpt_ma_if invalidate p_uop_1.xcpt_ae_if invalidate p_uop_1.xcpt_pf_if invalidate p_uop_1.fp_single invalidate p_uop_1.fp_val invalidate p_uop_1.frs3_en invalidate p_uop_1.lrs2_rtype invalidate p_uop_1.lrs1_rtype invalidate p_uop_1.dst_rtype invalidate p_uop_1.ldst_val invalidate p_uop_1.lrs3 invalidate p_uop_1.lrs2 invalidate p_uop_1.lrs1 invalidate p_uop_1.ldst invalidate p_uop_1.ldst_is_rs1 invalidate p_uop_1.flush_on_commit invalidate p_uop_1.is_unique invalidate p_uop_1.is_sys_pc2epc invalidate p_uop_1.uses_stq invalidate p_uop_1.uses_ldq invalidate p_uop_1.is_amo invalidate p_uop_1.is_fencei invalidate p_uop_1.is_fence invalidate p_uop_1.mem_signed invalidate p_uop_1.mem_size invalidate p_uop_1.mem_cmd invalidate p_uop_1.bypassable invalidate p_uop_1.exc_cause invalidate p_uop_1.exception invalidate p_uop_1.stale_pdst invalidate p_uop_1.ppred_busy invalidate p_uop_1.prs3_busy invalidate p_uop_1.prs2_busy invalidate p_uop_1.prs1_busy invalidate p_uop_1.ppred invalidate p_uop_1.prs3 invalidate p_uop_1.prs2 invalidate p_uop_1.prs1 invalidate p_uop_1.pdst invalidate p_uop_1.rxq_idx invalidate p_uop_1.stq_idx invalidate p_uop_1.ldq_idx invalidate p_uop_1.rob_idx invalidate p_uop_1.csr_addr invalidate p_uop_1.imm_packed invalidate p_uop_1.taken invalidate p_uop_1.pc_lob invalidate p_uop_1.edge_inst invalidate p_uop_1.ftq_idx invalidate p_uop_1.br_tag invalidate p_uop_1.br_mask invalidate p_uop_1.is_sfb invalidate p_uop_1.is_jal invalidate p_uop_1.is_jalr invalidate p_uop_1.is_br invalidate p_uop_1.iw_p2_poisoned invalidate p_uop_1.iw_p1_poisoned invalidate p_uop_1.iw_state invalidate p_uop_1.ctrl.is_std invalidate p_uop_1.ctrl.is_sta invalidate p_uop_1.ctrl.is_load invalidate p_uop_1.ctrl.csr_cmd invalidate p_uop_1.ctrl.fcn_dw invalidate p_uop_1.ctrl.op_fcn invalidate p_uop_1.ctrl.imm_sel invalidate p_uop_1.ctrl.op2_sel invalidate p_uop_1.ctrl.op1_sel invalidate p_uop_1.ctrl.br_type invalidate p_uop_1.fu_code invalidate p_uop_1.iq_type invalidate p_uop_1.debug_pc invalidate p_uop_1.is_rvc invalidate p_uop_1.debug_inst invalidate p_uop_1.inst invalidate p_uop_1.uopc connect p_uop_1.uopc, UInt<7>(0h0) connect p_uop_1.bypassable, UInt<1>(0h0) connect p_uop_1.fp_val, UInt<1>(0h0) connect p_uop_1.uses_stq, UInt<1>(0h0) connect p_uop_1.uses_ldq, UInt<1>(0h0) connect p_uop_1.pdst, UInt<1>(0h0) connect p_uop_1.dst_rtype, UInt<2>(0h2) wire p_uop_cs_1 : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate p_uop_cs_1.is_std invalidate p_uop_cs_1.is_sta invalidate p_uop_cs_1.is_load invalidate p_uop_cs_1.csr_cmd invalidate p_uop_cs_1.fcn_dw invalidate p_uop_cs_1.op_fcn invalidate p_uop_cs_1.imm_sel invalidate p_uop_cs_1.op2_sel invalidate p_uop_cs_1.op1_sel invalidate p_uop_cs_1.br_type connect p_uop_cs_1.br_type, UInt<4>(0h0) connect p_uop_cs_1.csr_cmd, UInt<3>(0h0) connect p_uop_cs_1.is_load, UInt<1>(0h0) connect p_uop_cs_1.is_sta, UInt<1>(0h0) connect p_uop_cs_1.is_std, UInt<1>(0h0) connect p_uop_1.ctrl, p_uop_cs_1 node _dis_uops_1_prs1_T = eq(dis_uops[1].lrs1_rtype, UInt<2>(0h1)) node _dis_uops_1_prs1_T_1 = eq(dis_uops[1].lrs1_rtype, UInt<2>(0h0)) node _dis_uops_1_prs1_T_2 = mux(_dis_uops_1_prs1_T_1, rename_stage.io.ren2_uops[1].prs1, dis_uops[1].lrs1) node _dis_uops_1_prs1_T_3 = mux(_dis_uops_1_prs1_T, fp_rename_stage.io.ren2_uops[1].prs1, _dis_uops_1_prs1_T_2) connect dis_uops[1].prs1, _dis_uops_1_prs1_T_3 node _dis_uops_1_prs2_T = eq(dis_uops[1].lrs2_rtype, UInt<2>(0h1)) node _dis_uops_1_prs2_T_1 = mux(_dis_uops_1_prs2_T, fp_rename_stage.io.ren2_uops[1].prs2, rename_stage.io.ren2_uops[1].prs2) connect dis_uops[1].prs2, _dis_uops_1_prs2_T_1 connect dis_uops[1].prs3, fp_rename_stage.io.ren2_uops[1].prs3 connect dis_uops[1].ppred, p_uop_1.ppred node _dis_uops_1_pdst_T = eq(dis_uops[1].dst_rtype, UInt<2>(0h1)) node _dis_uops_1_pdst_T_1 = eq(dis_uops[1].dst_rtype, UInt<2>(0h0)) node _dis_uops_1_pdst_T_2 = mux(_dis_uops_1_pdst_T_1, rename_stage.io.ren2_uops[1].pdst, p_uop_1.pdst) node _dis_uops_1_pdst_T_3 = mux(_dis_uops_1_pdst_T, fp_rename_stage.io.ren2_uops[1].pdst, _dis_uops_1_pdst_T_2) connect dis_uops[1].pdst, _dis_uops_1_pdst_T_3 node _dis_uops_1_stale_pdst_T = eq(dis_uops[1].dst_rtype, UInt<2>(0h1)) node _dis_uops_1_stale_pdst_T_1 = mux(_dis_uops_1_stale_pdst_T, fp_rename_stage.io.ren2_uops[1].stale_pdst, rename_stage.io.ren2_uops[1].stale_pdst) connect dis_uops[1].stale_pdst, _dis_uops_1_stale_pdst_T_1 node _dis_uops_1_prs1_busy_T = eq(dis_uops[1].lrs1_rtype, UInt<2>(0h0)) node _dis_uops_1_prs1_busy_T_1 = and(rename_stage.io.ren2_uops[1].prs1_busy, _dis_uops_1_prs1_busy_T) node _dis_uops_1_prs1_busy_T_2 = eq(dis_uops[1].lrs1_rtype, UInt<2>(0h1)) node _dis_uops_1_prs1_busy_T_3 = and(fp_rename_stage.io.ren2_uops[1].prs1_busy, _dis_uops_1_prs1_busy_T_2) node _dis_uops_1_prs1_busy_T_4 = or(_dis_uops_1_prs1_busy_T_1, _dis_uops_1_prs1_busy_T_3) connect dis_uops[1].prs1_busy, _dis_uops_1_prs1_busy_T_4 node _dis_uops_1_prs2_busy_T = eq(dis_uops[1].lrs2_rtype, UInt<2>(0h0)) node _dis_uops_1_prs2_busy_T_1 = and(rename_stage.io.ren2_uops[1].prs2_busy, _dis_uops_1_prs2_busy_T) node _dis_uops_1_prs2_busy_T_2 = eq(dis_uops[1].lrs2_rtype, UInt<2>(0h1)) node _dis_uops_1_prs2_busy_T_3 = and(fp_rename_stage.io.ren2_uops[1].prs2_busy, _dis_uops_1_prs2_busy_T_2) node _dis_uops_1_prs2_busy_T_4 = or(_dis_uops_1_prs2_busy_T_1, _dis_uops_1_prs2_busy_T_3) connect dis_uops[1].prs2_busy, _dis_uops_1_prs2_busy_T_4 node _dis_uops_1_prs3_busy_T = and(fp_rename_stage.io.ren2_uops[1].prs3_busy, dis_uops[1].frs3_en) connect dis_uops[1].prs3_busy, _dis_uops_1_prs3_busy_T node _dis_uops_1_ppred_busy_T = eq(dis_uops[1].is_br, UInt<1>(0h0)) node _dis_uops_1_ppred_busy_T_1 = and(_dis_uops_1_ppred_busy_T, dis_uops[1].is_sfb) node _dis_uops_1_ppred_busy_T_2 = and(_dis_uops_1_ppred_busy_T_1, UInt<1>(0h0)) node _dis_uops_1_ppred_busy_T_3 = and(p_uop_1.ppred_busy, _dis_uops_1_ppred_busy_T_2) connect dis_uops[1].ppred_busy, _dis_uops_1_ppred_busy_T_3 node _ren_stalls_1_T = or(rename_stage.io.ren_stalls[1], fp_rename_stage.io.ren_stalls[1]) node _ren_stalls_1_T_1 = or(_ren_stalls_1_T, UInt<1>(0h0)) connect ren_stalls[1], _ren_stalls_1_T_1 wire p_uop_2 : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate p_uop_2.debug_tsrc invalidate p_uop_2.debug_fsrc invalidate p_uop_2.bp_xcpt_if invalidate p_uop_2.bp_debug_if invalidate p_uop_2.xcpt_ma_if invalidate p_uop_2.xcpt_ae_if invalidate p_uop_2.xcpt_pf_if invalidate p_uop_2.fp_single invalidate p_uop_2.fp_val invalidate p_uop_2.frs3_en invalidate p_uop_2.lrs2_rtype invalidate p_uop_2.lrs1_rtype invalidate p_uop_2.dst_rtype invalidate p_uop_2.ldst_val invalidate p_uop_2.lrs3 invalidate p_uop_2.lrs2 invalidate p_uop_2.lrs1 invalidate p_uop_2.ldst invalidate p_uop_2.ldst_is_rs1 invalidate p_uop_2.flush_on_commit invalidate p_uop_2.is_unique invalidate p_uop_2.is_sys_pc2epc invalidate p_uop_2.uses_stq invalidate p_uop_2.uses_ldq invalidate p_uop_2.is_amo invalidate p_uop_2.is_fencei invalidate p_uop_2.is_fence invalidate p_uop_2.mem_signed invalidate p_uop_2.mem_size invalidate p_uop_2.mem_cmd invalidate p_uop_2.bypassable invalidate p_uop_2.exc_cause invalidate p_uop_2.exception invalidate p_uop_2.stale_pdst invalidate p_uop_2.ppred_busy invalidate p_uop_2.prs3_busy invalidate p_uop_2.prs2_busy invalidate p_uop_2.prs1_busy invalidate p_uop_2.ppred invalidate p_uop_2.prs3 invalidate p_uop_2.prs2 invalidate p_uop_2.prs1 invalidate p_uop_2.pdst invalidate p_uop_2.rxq_idx invalidate p_uop_2.stq_idx invalidate p_uop_2.ldq_idx invalidate p_uop_2.rob_idx invalidate p_uop_2.csr_addr invalidate p_uop_2.imm_packed invalidate p_uop_2.taken invalidate p_uop_2.pc_lob invalidate p_uop_2.edge_inst invalidate p_uop_2.ftq_idx invalidate p_uop_2.br_tag invalidate p_uop_2.br_mask invalidate p_uop_2.is_sfb invalidate p_uop_2.is_jal invalidate p_uop_2.is_jalr invalidate p_uop_2.is_br invalidate p_uop_2.iw_p2_poisoned invalidate p_uop_2.iw_p1_poisoned invalidate p_uop_2.iw_state invalidate p_uop_2.ctrl.is_std invalidate p_uop_2.ctrl.is_sta invalidate p_uop_2.ctrl.is_load invalidate p_uop_2.ctrl.csr_cmd invalidate p_uop_2.ctrl.fcn_dw invalidate p_uop_2.ctrl.op_fcn invalidate p_uop_2.ctrl.imm_sel invalidate p_uop_2.ctrl.op2_sel invalidate p_uop_2.ctrl.op1_sel invalidate p_uop_2.ctrl.br_type invalidate p_uop_2.fu_code invalidate p_uop_2.iq_type invalidate p_uop_2.debug_pc invalidate p_uop_2.is_rvc invalidate p_uop_2.debug_inst invalidate p_uop_2.inst invalidate p_uop_2.uopc connect p_uop_2.uopc, UInt<7>(0h0) connect p_uop_2.bypassable, UInt<1>(0h0) connect p_uop_2.fp_val, UInt<1>(0h0) connect p_uop_2.uses_stq, UInt<1>(0h0) connect p_uop_2.uses_ldq, UInt<1>(0h0) connect p_uop_2.pdst, UInt<1>(0h0) connect p_uop_2.dst_rtype, UInt<2>(0h2) wire p_uop_cs_2 : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate p_uop_cs_2.is_std invalidate p_uop_cs_2.is_sta invalidate p_uop_cs_2.is_load invalidate p_uop_cs_2.csr_cmd invalidate p_uop_cs_2.fcn_dw invalidate p_uop_cs_2.op_fcn invalidate p_uop_cs_2.imm_sel invalidate p_uop_cs_2.op2_sel invalidate p_uop_cs_2.op1_sel invalidate p_uop_cs_2.br_type connect p_uop_cs_2.br_type, UInt<4>(0h0) connect p_uop_cs_2.csr_cmd, UInt<3>(0h0) connect p_uop_cs_2.is_load, UInt<1>(0h0) connect p_uop_cs_2.is_sta, UInt<1>(0h0) connect p_uop_cs_2.is_std, UInt<1>(0h0) connect p_uop_2.ctrl, p_uop_cs_2 node _dis_uops_2_prs1_T = eq(dis_uops[2].lrs1_rtype, UInt<2>(0h1)) node _dis_uops_2_prs1_T_1 = eq(dis_uops[2].lrs1_rtype, UInt<2>(0h0)) node _dis_uops_2_prs1_T_2 = mux(_dis_uops_2_prs1_T_1, rename_stage.io.ren2_uops[2].prs1, dis_uops[2].lrs1) node _dis_uops_2_prs1_T_3 = mux(_dis_uops_2_prs1_T, fp_rename_stage.io.ren2_uops[2].prs1, _dis_uops_2_prs1_T_2) connect dis_uops[2].prs1, _dis_uops_2_prs1_T_3 node _dis_uops_2_prs2_T = eq(dis_uops[2].lrs2_rtype, UInt<2>(0h1)) node _dis_uops_2_prs2_T_1 = mux(_dis_uops_2_prs2_T, fp_rename_stage.io.ren2_uops[2].prs2, rename_stage.io.ren2_uops[2].prs2) connect dis_uops[2].prs2, _dis_uops_2_prs2_T_1 connect dis_uops[2].prs3, fp_rename_stage.io.ren2_uops[2].prs3 connect dis_uops[2].ppred, p_uop_2.ppred node _dis_uops_2_pdst_T = eq(dis_uops[2].dst_rtype, UInt<2>(0h1)) node _dis_uops_2_pdst_T_1 = eq(dis_uops[2].dst_rtype, UInt<2>(0h0)) node _dis_uops_2_pdst_T_2 = mux(_dis_uops_2_pdst_T_1, rename_stage.io.ren2_uops[2].pdst, p_uop_2.pdst) node _dis_uops_2_pdst_T_3 = mux(_dis_uops_2_pdst_T, fp_rename_stage.io.ren2_uops[2].pdst, _dis_uops_2_pdst_T_2) connect dis_uops[2].pdst, _dis_uops_2_pdst_T_3 node _dis_uops_2_stale_pdst_T = eq(dis_uops[2].dst_rtype, UInt<2>(0h1)) node _dis_uops_2_stale_pdst_T_1 = mux(_dis_uops_2_stale_pdst_T, fp_rename_stage.io.ren2_uops[2].stale_pdst, rename_stage.io.ren2_uops[2].stale_pdst) connect dis_uops[2].stale_pdst, _dis_uops_2_stale_pdst_T_1 node _dis_uops_2_prs1_busy_T = eq(dis_uops[2].lrs1_rtype, UInt<2>(0h0)) node _dis_uops_2_prs1_busy_T_1 = and(rename_stage.io.ren2_uops[2].prs1_busy, _dis_uops_2_prs1_busy_T) node _dis_uops_2_prs1_busy_T_2 = eq(dis_uops[2].lrs1_rtype, UInt<2>(0h1)) node _dis_uops_2_prs1_busy_T_3 = and(fp_rename_stage.io.ren2_uops[2].prs1_busy, _dis_uops_2_prs1_busy_T_2) node _dis_uops_2_prs1_busy_T_4 = or(_dis_uops_2_prs1_busy_T_1, _dis_uops_2_prs1_busy_T_3) connect dis_uops[2].prs1_busy, _dis_uops_2_prs1_busy_T_4 node _dis_uops_2_prs2_busy_T = eq(dis_uops[2].lrs2_rtype, UInt<2>(0h0)) node _dis_uops_2_prs2_busy_T_1 = and(rename_stage.io.ren2_uops[2].prs2_busy, _dis_uops_2_prs2_busy_T) node _dis_uops_2_prs2_busy_T_2 = eq(dis_uops[2].lrs2_rtype, UInt<2>(0h1)) node _dis_uops_2_prs2_busy_T_3 = and(fp_rename_stage.io.ren2_uops[2].prs2_busy, _dis_uops_2_prs2_busy_T_2) node _dis_uops_2_prs2_busy_T_4 = or(_dis_uops_2_prs2_busy_T_1, _dis_uops_2_prs2_busy_T_3) connect dis_uops[2].prs2_busy, _dis_uops_2_prs2_busy_T_4 node _dis_uops_2_prs3_busy_T = and(fp_rename_stage.io.ren2_uops[2].prs3_busy, dis_uops[2].frs3_en) connect dis_uops[2].prs3_busy, _dis_uops_2_prs3_busy_T node _dis_uops_2_ppred_busy_T = eq(dis_uops[2].is_br, UInt<1>(0h0)) node _dis_uops_2_ppred_busy_T_1 = and(_dis_uops_2_ppred_busy_T, dis_uops[2].is_sfb) node _dis_uops_2_ppred_busy_T_2 = and(_dis_uops_2_ppred_busy_T_1, UInt<1>(0h0)) node _dis_uops_2_ppred_busy_T_3 = and(p_uop_2.ppred_busy, _dis_uops_2_ppred_busy_T_2) connect dis_uops[2].ppred_busy, _dis_uops_2_ppred_busy_T_3 node _ren_stalls_2_T = or(rename_stage.io.ren_stalls[2], fp_rename_stage.io.ren_stalls[2]) node _ren_stalls_2_T_1 = or(_ren_stalls_2_T, UInt<1>(0h0)) connect ren_stalls[2], _ren_stalls_2_T_1 node dis_prior_slot_valid_1 = or(UInt<1>(0h0), dis_valids[0]) node dis_prior_slot_valid_2 = or(dis_prior_slot_valid_1, dis_valids[1]) node dis_prior_slot_valid_3 = or(dis_prior_slot_valid_2, dis_valids[2]) node _dis_prior_slot_unique_T = and(dis_valids[0], dis_uops[0].is_unique) node dis_prior_slot_unique_1 = or(UInt<1>(0h0), _dis_prior_slot_unique_T) node _dis_prior_slot_unique_T_1 = and(dis_valids[1], dis_uops[1].is_unique) node dis_prior_slot_unique_2 = or(dis_prior_slot_unique_1, _dis_prior_slot_unique_T_1) node _dis_prior_slot_unique_T_2 = and(dis_valids[2], dis_uops[2].is_unique) node dis_prior_slot_unique_3 = or(dis_prior_slot_unique_2, _dis_prior_slot_unique_T_2) node _wait_for_empty_pipeline_T = bits(custom_csrs.csrs[0].value, 3, 3) node _wait_for_empty_pipeline_T_1 = or(dis_uops[0].is_unique, _wait_for_empty_pipeline_T) node _wait_for_empty_pipeline_T_2 = eq(rob.io.empty, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_3 = eq(io.lsu.fencei_rdy, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_4 = or(_wait_for_empty_pipeline_T_2, _wait_for_empty_pipeline_T_3) node _wait_for_empty_pipeline_T_5 = or(_wait_for_empty_pipeline_T_4, UInt<1>(0h0)) node wait_for_empty_pipeline_0 = and(_wait_for_empty_pipeline_T_1, _wait_for_empty_pipeline_T_5) node _wait_for_empty_pipeline_T_6 = bits(custom_csrs.csrs[0].value, 3, 3) node _wait_for_empty_pipeline_T_7 = or(dis_uops[1].is_unique, _wait_for_empty_pipeline_T_6) node _wait_for_empty_pipeline_T_8 = eq(rob.io.empty, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_9 = eq(io.lsu.fencei_rdy, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_10 = or(_wait_for_empty_pipeline_T_8, _wait_for_empty_pipeline_T_9) node _wait_for_empty_pipeline_T_11 = or(_wait_for_empty_pipeline_T_10, dis_prior_slot_valid_1) node wait_for_empty_pipeline_1 = and(_wait_for_empty_pipeline_T_7, _wait_for_empty_pipeline_T_11) node _wait_for_empty_pipeline_T_12 = bits(custom_csrs.csrs[0].value, 3, 3) node _wait_for_empty_pipeline_T_13 = or(dis_uops[2].is_unique, _wait_for_empty_pipeline_T_12) node _wait_for_empty_pipeline_T_14 = eq(rob.io.empty, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_15 = eq(io.lsu.fencei_rdy, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_16 = or(_wait_for_empty_pipeline_T_14, _wait_for_empty_pipeline_T_15) node _wait_for_empty_pipeline_T_17 = or(_wait_for_empty_pipeline_T_16, dis_prior_slot_valid_2) node wait_for_empty_pipeline_2 = and(_wait_for_empty_pipeline_T_13, _wait_for_empty_pipeline_T_17) node _wait_for_rocc_T = or(dis_uops[0].is_fence, dis_uops[0].is_fencei) node _wait_for_rocc_T_1 = or(io.rocc.busy, UInt<1>(0h0)) node wait_for_rocc_0 = and(_wait_for_rocc_T, _wait_for_rocc_T_1) node _wait_for_rocc_T_2 = or(dis_uops[1].is_fence, dis_uops[1].is_fencei) node _wait_for_rocc_T_3 = or(io.rocc.busy, UInt<1>(0h0)) node wait_for_rocc_1 = and(_wait_for_rocc_T_2, _wait_for_rocc_T_3) node _wait_for_rocc_T_4 = or(dis_uops[2].is_fence, dis_uops[2].is_fencei) node _wait_for_rocc_T_5 = or(io.rocc.busy, UInt<1>(0h0)) node wait_for_rocc_2 = and(_wait_for_rocc_T_4, _wait_for_rocc_T_5) node _block_rocc_T = eq(dis_uops[0].uopc, UInt<7>(0h6c)) node _block_rocc_T_1 = and(dis_valids[0], _block_rocc_T) node _block_rocc_T_2 = eq(dis_uops[1].uopc, UInt<7>(0h6c)) node _block_rocc_T_3 = and(dis_valids[1], _block_rocc_T_2) node _block_rocc_T_4 = eq(dis_uops[2].uopc, UInt<7>(0h6c)) node _block_rocc_T_5 = and(dis_valids[2], _block_rocc_T_4) node block_rocc_1 = or(UInt<1>(0h0), _block_rocc_T_1) node block_rocc_2 = or(block_rocc_1, _block_rocc_T_3) node block_rocc_3 = or(block_rocc_2, _block_rocc_T_5) node _dis_rocc_alloc_stall_T = eq(dis_uops[0].uopc, UInt<7>(0h6c)) node _dis_rocc_alloc_stall_T_1 = eq(dis_uops[1].uopc, UInt<7>(0h6c)) node _dis_rocc_alloc_stall_T_2 = eq(dis_uops[2].uopc, UInt<7>(0h6c)) node _dis_hazards_T = eq(rob.io.ready, UInt<1>(0h0)) node _dis_hazards_T_1 = or(_dis_hazards_T, ren_stalls[0]) node _dis_hazards_T_2 = and(io.lsu.ldq_full[0], dis_uops[0].uses_ldq) node _dis_hazards_T_3 = or(_dis_hazards_T_1, _dis_hazards_T_2) node _dis_hazards_T_4 = and(io.lsu.stq_full[0], dis_uops[0].uses_stq) node _dis_hazards_T_5 = or(_dis_hazards_T_3, _dis_hazards_T_4) node _dis_hazards_T_6 = eq(dispatcher.io.ren_uops[0].ready, UInt<1>(0h0)) node _dis_hazards_T_7 = or(_dis_hazards_T_5, _dis_hazards_T_6) node _dis_hazards_T_8 = or(_dis_hazards_T_7, wait_for_empty_pipeline_0) node _dis_hazards_T_9 = or(_dis_hazards_T_8, wait_for_rocc_0) node _dis_hazards_T_10 = or(_dis_hazards_T_9, UInt<1>(0h0)) node _dis_hazards_T_11 = or(_dis_hazards_T_10, UInt<1>(0h0)) node _dis_hazards_T_12 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _dis_hazards_T_13 = or(_dis_hazards_T_11, _dis_hazards_T_12) node _dis_hazards_T_14 = or(_dis_hazards_T_13, brupdate.b2.mispredict) node _dis_hazards_T_15 = or(_dis_hazards_T_14, io.ifu.redirect_flush) node dis_hazards_0 = and(dis_valids[0], _dis_hazards_T_15) node _dis_hazards_T_16 = eq(rob.io.ready, UInt<1>(0h0)) node _dis_hazards_T_17 = or(_dis_hazards_T_16, ren_stalls[1]) node _dis_hazards_T_18 = and(io.lsu.ldq_full[1], dis_uops[1].uses_ldq) node _dis_hazards_T_19 = or(_dis_hazards_T_17, _dis_hazards_T_18) node _dis_hazards_T_20 = and(io.lsu.stq_full[1], dis_uops[1].uses_stq) node _dis_hazards_T_21 = or(_dis_hazards_T_19, _dis_hazards_T_20) node _dis_hazards_T_22 = eq(dispatcher.io.ren_uops[1].ready, UInt<1>(0h0)) node _dis_hazards_T_23 = or(_dis_hazards_T_21, _dis_hazards_T_22) node _dis_hazards_T_24 = or(_dis_hazards_T_23, wait_for_empty_pipeline_1) node _dis_hazards_T_25 = or(_dis_hazards_T_24, wait_for_rocc_1) node _dis_hazards_T_26 = or(_dis_hazards_T_25, dis_prior_slot_unique_1) node _dis_hazards_T_27 = or(_dis_hazards_T_26, UInt<1>(0h0)) node _dis_hazards_T_28 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _dis_hazards_T_29 = or(_dis_hazards_T_27, _dis_hazards_T_28) node _dis_hazards_T_30 = or(_dis_hazards_T_29, brupdate.b2.mispredict) node _dis_hazards_T_31 = or(_dis_hazards_T_30, io.ifu.redirect_flush) node dis_hazards_1 = and(dis_valids[1], _dis_hazards_T_31) node _dis_hazards_T_32 = eq(rob.io.ready, UInt<1>(0h0)) node _dis_hazards_T_33 = or(_dis_hazards_T_32, ren_stalls[2]) node _dis_hazards_T_34 = and(io.lsu.ldq_full[2], dis_uops[2].uses_ldq) node _dis_hazards_T_35 = or(_dis_hazards_T_33, _dis_hazards_T_34) node _dis_hazards_T_36 = and(io.lsu.stq_full[2], dis_uops[2].uses_stq) node _dis_hazards_T_37 = or(_dis_hazards_T_35, _dis_hazards_T_36) node _dis_hazards_T_38 = eq(dispatcher.io.ren_uops[2].ready, UInt<1>(0h0)) node _dis_hazards_T_39 = or(_dis_hazards_T_37, _dis_hazards_T_38) node _dis_hazards_T_40 = or(_dis_hazards_T_39, wait_for_empty_pipeline_2) node _dis_hazards_T_41 = or(_dis_hazards_T_40, wait_for_rocc_2) node _dis_hazards_T_42 = or(_dis_hazards_T_41, dis_prior_slot_unique_2) node _dis_hazards_T_43 = or(_dis_hazards_T_42, UInt<1>(0h0)) node _dis_hazards_T_44 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _dis_hazards_T_45 = or(_dis_hazards_T_43, _dis_hazards_T_44) node _dis_hazards_T_46 = or(_dis_hazards_T_45, brupdate.b2.mispredict) node _dis_hazards_T_47 = or(_dis_hazards_T_46, io.ifu.redirect_flush) node dis_hazards_2 = and(dis_valids[2], _dis_hazards_T_47) node _io_lsu_fence_dmem_T = and(dis_valids[0], wait_for_empty_pipeline_0) node _io_lsu_fence_dmem_T_1 = and(dis_valids[1], wait_for_empty_pipeline_1) node _io_lsu_fence_dmem_T_2 = and(dis_valids[2], wait_for_empty_pipeline_2) node _io_lsu_fence_dmem_T_3 = or(_io_lsu_fence_dmem_T, _io_lsu_fence_dmem_T_1) node _io_lsu_fence_dmem_T_4 = or(_io_lsu_fence_dmem_T_3, _io_lsu_fence_dmem_T_2) connect io.lsu.fence_dmem, _io_lsu_fence_dmem_T_4 node dis_stalls_0 = or(UInt<1>(0h0), dis_hazards_0) node dis_stalls_1 = or(dis_stalls_0, dis_hazards_1) node dis_stalls_2 = or(dis_stalls_1, dis_hazards_2) node _T_38 = eq(dis_stalls_0, UInt<1>(0h0)) node _T_39 = and(dis_valids[0], _T_38) node _T_40 = eq(dis_stalls_1, UInt<1>(0h0)) node _T_41 = and(dis_valids[1], _T_40) node _T_42 = eq(dis_stalls_2, UInt<1>(0h0)) node _T_43 = and(dis_valids[2], _T_42) connect dis_fire[0], _T_39 connect dis_fire[1], _T_41 connect dis_fire[2], _T_43 node _dis_ready_T = eq(dis_stalls_2, UInt<1>(0h0)) connect dis_ready, _dis_ready_T connect dis_uops[0].ldq_idx, io.lsu.dis_ldq_idx[0] connect dis_uops[0].stq_idx, io.lsu.dis_stq_idx[0] connect dis_uops[1].ldq_idx, io.lsu.dis_ldq_idx[1] connect dis_uops[1].stq_idx, io.lsu.dis_stq_idx[1] connect dis_uops[2].ldq_idx, io.lsu.dis_ldq_idx[2] connect dis_uops[2].stq_idx, io.lsu.dis_stq_idx[2] connect rob.io.enq_valids[0], dis_fire[0] connect rob.io.enq_valids[1], dis_fire[1] connect rob.io.enq_valids[2], dis_fire[2] connect rob.io.enq_uops[0].debug_tsrc, dis_uops[0].debug_tsrc connect rob.io.enq_uops[0].debug_fsrc, dis_uops[0].debug_fsrc connect rob.io.enq_uops[0].bp_xcpt_if, dis_uops[0].bp_xcpt_if connect rob.io.enq_uops[0].bp_debug_if, dis_uops[0].bp_debug_if connect rob.io.enq_uops[0].xcpt_ma_if, dis_uops[0].xcpt_ma_if connect rob.io.enq_uops[0].xcpt_ae_if, dis_uops[0].xcpt_ae_if connect rob.io.enq_uops[0].xcpt_pf_if, dis_uops[0].xcpt_pf_if connect rob.io.enq_uops[0].fp_single, dis_uops[0].fp_single connect rob.io.enq_uops[0].fp_val, dis_uops[0].fp_val connect rob.io.enq_uops[0].frs3_en, dis_uops[0].frs3_en connect rob.io.enq_uops[0].lrs2_rtype, dis_uops[0].lrs2_rtype connect rob.io.enq_uops[0].lrs1_rtype, dis_uops[0].lrs1_rtype connect rob.io.enq_uops[0].dst_rtype, dis_uops[0].dst_rtype connect rob.io.enq_uops[0].ldst_val, dis_uops[0].ldst_val connect rob.io.enq_uops[0].lrs3, dis_uops[0].lrs3 connect rob.io.enq_uops[0].lrs2, dis_uops[0].lrs2 connect rob.io.enq_uops[0].lrs1, dis_uops[0].lrs1 connect rob.io.enq_uops[0].ldst, dis_uops[0].ldst connect rob.io.enq_uops[0].ldst_is_rs1, dis_uops[0].ldst_is_rs1 connect rob.io.enq_uops[0].flush_on_commit, dis_uops[0].flush_on_commit connect rob.io.enq_uops[0].is_unique, dis_uops[0].is_unique connect rob.io.enq_uops[0].is_sys_pc2epc, dis_uops[0].is_sys_pc2epc connect rob.io.enq_uops[0].uses_stq, dis_uops[0].uses_stq connect rob.io.enq_uops[0].uses_ldq, dis_uops[0].uses_ldq connect rob.io.enq_uops[0].is_amo, dis_uops[0].is_amo connect rob.io.enq_uops[0].is_fencei, dis_uops[0].is_fencei connect rob.io.enq_uops[0].is_fence, dis_uops[0].is_fence connect rob.io.enq_uops[0].mem_signed, dis_uops[0].mem_signed connect rob.io.enq_uops[0].mem_size, dis_uops[0].mem_size connect rob.io.enq_uops[0].mem_cmd, dis_uops[0].mem_cmd connect rob.io.enq_uops[0].bypassable, dis_uops[0].bypassable connect rob.io.enq_uops[0].exc_cause, dis_uops[0].exc_cause connect rob.io.enq_uops[0].exception, dis_uops[0].exception connect rob.io.enq_uops[0].stale_pdst, dis_uops[0].stale_pdst connect rob.io.enq_uops[0].ppred_busy, dis_uops[0].ppred_busy connect rob.io.enq_uops[0].prs3_busy, dis_uops[0].prs3_busy connect rob.io.enq_uops[0].prs2_busy, dis_uops[0].prs2_busy connect rob.io.enq_uops[0].prs1_busy, dis_uops[0].prs1_busy connect rob.io.enq_uops[0].ppred, dis_uops[0].ppred connect rob.io.enq_uops[0].prs3, dis_uops[0].prs3 connect rob.io.enq_uops[0].prs2, dis_uops[0].prs2 connect rob.io.enq_uops[0].prs1, dis_uops[0].prs1 connect rob.io.enq_uops[0].pdst, dis_uops[0].pdst connect rob.io.enq_uops[0].rxq_idx, dis_uops[0].rxq_idx connect rob.io.enq_uops[0].stq_idx, dis_uops[0].stq_idx connect rob.io.enq_uops[0].ldq_idx, dis_uops[0].ldq_idx connect rob.io.enq_uops[0].rob_idx, dis_uops[0].rob_idx connect rob.io.enq_uops[0].csr_addr, dis_uops[0].csr_addr connect rob.io.enq_uops[0].imm_packed, dis_uops[0].imm_packed connect rob.io.enq_uops[0].taken, dis_uops[0].taken connect rob.io.enq_uops[0].pc_lob, dis_uops[0].pc_lob connect rob.io.enq_uops[0].edge_inst, dis_uops[0].edge_inst connect rob.io.enq_uops[0].ftq_idx, dis_uops[0].ftq_idx connect rob.io.enq_uops[0].br_tag, dis_uops[0].br_tag connect rob.io.enq_uops[0].br_mask, dis_uops[0].br_mask connect rob.io.enq_uops[0].is_sfb, dis_uops[0].is_sfb connect rob.io.enq_uops[0].is_jal, dis_uops[0].is_jal connect rob.io.enq_uops[0].is_jalr, dis_uops[0].is_jalr connect rob.io.enq_uops[0].is_br, dis_uops[0].is_br connect rob.io.enq_uops[0].iw_p2_poisoned, dis_uops[0].iw_p2_poisoned connect rob.io.enq_uops[0].iw_p1_poisoned, dis_uops[0].iw_p1_poisoned connect rob.io.enq_uops[0].iw_state, dis_uops[0].iw_state connect rob.io.enq_uops[0].ctrl.is_std, dis_uops[0].ctrl.is_std connect rob.io.enq_uops[0].ctrl.is_sta, dis_uops[0].ctrl.is_sta connect rob.io.enq_uops[0].ctrl.is_load, dis_uops[0].ctrl.is_load connect rob.io.enq_uops[0].ctrl.csr_cmd, dis_uops[0].ctrl.csr_cmd connect rob.io.enq_uops[0].ctrl.fcn_dw, dis_uops[0].ctrl.fcn_dw connect rob.io.enq_uops[0].ctrl.op_fcn, dis_uops[0].ctrl.op_fcn connect rob.io.enq_uops[0].ctrl.imm_sel, dis_uops[0].ctrl.imm_sel connect rob.io.enq_uops[0].ctrl.op2_sel, dis_uops[0].ctrl.op2_sel connect rob.io.enq_uops[0].ctrl.op1_sel, dis_uops[0].ctrl.op1_sel connect rob.io.enq_uops[0].ctrl.br_type, dis_uops[0].ctrl.br_type connect rob.io.enq_uops[0].fu_code, dis_uops[0].fu_code connect rob.io.enq_uops[0].iq_type, dis_uops[0].iq_type connect rob.io.enq_uops[0].debug_pc, dis_uops[0].debug_pc connect rob.io.enq_uops[0].is_rvc, dis_uops[0].is_rvc connect rob.io.enq_uops[0].debug_inst, dis_uops[0].debug_inst connect rob.io.enq_uops[0].inst, dis_uops[0].inst connect rob.io.enq_uops[0].uopc, dis_uops[0].uopc connect rob.io.enq_uops[1].debug_tsrc, dis_uops[1].debug_tsrc connect rob.io.enq_uops[1].debug_fsrc, dis_uops[1].debug_fsrc connect rob.io.enq_uops[1].bp_xcpt_if, dis_uops[1].bp_xcpt_if connect rob.io.enq_uops[1].bp_debug_if, dis_uops[1].bp_debug_if connect rob.io.enq_uops[1].xcpt_ma_if, dis_uops[1].xcpt_ma_if connect rob.io.enq_uops[1].xcpt_ae_if, dis_uops[1].xcpt_ae_if connect rob.io.enq_uops[1].xcpt_pf_if, dis_uops[1].xcpt_pf_if connect rob.io.enq_uops[1].fp_single, dis_uops[1].fp_single connect rob.io.enq_uops[1].fp_val, dis_uops[1].fp_val connect rob.io.enq_uops[1].frs3_en, dis_uops[1].frs3_en connect rob.io.enq_uops[1].lrs2_rtype, dis_uops[1].lrs2_rtype connect rob.io.enq_uops[1].lrs1_rtype, dis_uops[1].lrs1_rtype connect rob.io.enq_uops[1].dst_rtype, dis_uops[1].dst_rtype connect rob.io.enq_uops[1].ldst_val, dis_uops[1].ldst_val connect rob.io.enq_uops[1].lrs3, dis_uops[1].lrs3 connect rob.io.enq_uops[1].lrs2, dis_uops[1].lrs2 connect rob.io.enq_uops[1].lrs1, dis_uops[1].lrs1 connect rob.io.enq_uops[1].ldst, dis_uops[1].ldst connect rob.io.enq_uops[1].ldst_is_rs1, dis_uops[1].ldst_is_rs1 connect rob.io.enq_uops[1].flush_on_commit, dis_uops[1].flush_on_commit connect rob.io.enq_uops[1].is_unique, dis_uops[1].is_unique connect rob.io.enq_uops[1].is_sys_pc2epc, dis_uops[1].is_sys_pc2epc connect rob.io.enq_uops[1].uses_stq, dis_uops[1].uses_stq connect rob.io.enq_uops[1].uses_ldq, dis_uops[1].uses_ldq connect rob.io.enq_uops[1].is_amo, dis_uops[1].is_amo connect rob.io.enq_uops[1].is_fencei, dis_uops[1].is_fencei connect rob.io.enq_uops[1].is_fence, dis_uops[1].is_fence connect rob.io.enq_uops[1].mem_signed, dis_uops[1].mem_signed connect rob.io.enq_uops[1].mem_size, dis_uops[1].mem_size connect rob.io.enq_uops[1].mem_cmd, dis_uops[1].mem_cmd connect rob.io.enq_uops[1].bypassable, dis_uops[1].bypassable connect rob.io.enq_uops[1].exc_cause, dis_uops[1].exc_cause connect rob.io.enq_uops[1].exception, dis_uops[1].exception connect rob.io.enq_uops[1].stale_pdst, dis_uops[1].stale_pdst connect rob.io.enq_uops[1].ppred_busy, dis_uops[1].ppred_busy connect rob.io.enq_uops[1].prs3_busy, dis_uops[1].prs3_busy connect rob.io.enq_uops[1].prs2_busy, dis_uops[1].prs2_busy connect rob.io.enq_uops[1].prs1_busy, dis_uops[1].prs1_busy connect rob.io.enq_uops[1].ppred, dis_uops[1].ppred connect rob.io.enq_uops[1].prs3, dis_uops[1].prs3 connect rob.io.enq_uops[1].prs2, dis_uops[1].prs2 connect rob.io.enq_uops[1].prs1, dis_uops[1].prs1 connect rob.io.enq_uops[1].pdst, dis_uops[1].pdst connect rob.io.enq_uops[1].rxq_idx, dis_uops[1].rxq_idx connect rob.io.enq_uops[1].stq_idx, dis_uops[1].stq_idx connect rob.io.enq_uops[1].ldq_idx, dis_uops[1].ldq_idx connect rob.io.enq_uops[1].rob_idx, dis_uops[1].rob_idx connect rob.io.enq_uops[1].csr_addr, dis_uops[1].csr_addr connect rob.io.enq_uops[1].imm_packed, dis_uops[1].imm_packed connect rob.io.enq_uops[1].taken, dis_uops[1].taken connect rob.io.enq_uops[1].pc_lob, dis_uops[1].pc_lob connect rob.io.enq_uops[1].edge_inst, dis_uops[1].edge_inst connect rob.io.enq_uops[1].ftq_idx, dis_uops[1].ftq_idx connect rob.io.enq_uops[1].br_tag, dis_uops[1].br_tag connect rob.io.enq_uops[1].br_mask, dis_uops[1].br_mask connect rob.io.enq_uops[1].is_sfb, dis_uops[1].is_sfb connect rob.io.enq_uops[1].is_jal, dis_uops[1].is_jal connect rob.io.enq_uops[1].is_jalr, dis_uops[1].is_jalr connect rob.io.enq_uops[1].is_br, dis_uops[1].is_br connect rob.io.enq_uops[1].iw_p2_poisoned, dis_uops[1].iw_p2_poisoned connect rob.io.enq_uops[1].iw_p1_poisoned, dis_uops[1].iw_p1_poisoned connect rob.io.enq_uops[1].iw_state, dis_uops[1].iw_state connect rob.io.enq_uops[1].ctrl.is_std, dis_uops[1].ctrl.is_std connect rob.io.enq_uops[1].ctrl.is_sta, dis_uops[1].ctrl.is_sta connect rob.io.enq_uops[1].ctrl.is_load, dis_uops[1].ctrl.is_load connect rob.io.enq_uops[1].ctrl.csr_cmd, dis_uops[1].ctrl.csr_cmd connect rob.io.enq_uops[1].ctrl.fcn_dw, dis_uops[1].ctrl.fcn_dw connect rob.io.enq_uops[1].ctrl.op_fcn, dis_uops[1].ctrl.op_fcn connect rob.io.enq_uops[1].ctrl.imm_sel, dis_uops[1].ctrl.imm_sel connect rob.io.enq_uops[1].ctrl.op2_sel, dis_uops[1].ctrl.op2_sel connect rob.io.enq_uops[1].ctrl.op1_sel, dis_uops[1].ctrl.op1_sel connect rob.io.enq_uops[1].ctrl.br_type, dis_uops[1].ctrl.br_type connect rob.io.enq_uops[1].fu_code, dis_uops[1].fu_code connect rob.io.enq_uops[1].iq_type, dis_uops[1].iq_type connect rob.io.enq_uops[1].debug_pc, dis_uops[1].debug_pc connect rob.io.enq_uops[1].is_rvc, dis_uops[1].is_rvc connect rob.io.enq_uops[1].debug_inst, dis_uops[1].debug_inst connect rob.io.enq_uops[1].inst, dis_uops[1].inst connect rob.io.enq_uops[1].uopc, dis_uops[1].uopc connect rob.io.enq_uops[2].debug_tsrc, dis_uops[2].debug_tsrc connect rob.io.enq_uops[2].debug_fsrc, dis_uops[2].debug_fsrc connect rob.io.enq_uops[2].bp_xcpt_if, dis_uops[2].bp_xcpt_if connect rob.io.enq_uops[2].bp_debug_if, dis_uops[2].bp_debug_if connect rob.io.enq_uops[2].xcpt_ma_if, dis_uops[2].xcpt_ma_if connect rob.io.enq_uops[2].xcpt_ae_if, dis_uops[2].xcpt_ae_if connect rob.io.enq_uops[2].xcpt_pf_if, dis_uops[2].xcpt_pf_if connect rob.io.enq_uops[2].fp_single, dis_uops[2].fp_single connect rob.io.enq_uops[2].fp_val, dis_uops[2].fp_val connect rob.io.enq_uops[2].frs3_en, dis_uops[2].frs3_en connect rob.io.enq_uops[2].lrs2_rtype, dis_uops[2].lrs2_rtype connect rob.io.enq_uops[2].lrs1_rtype, dis_uops[2].lrs1_rtype connect rob.io.enq_uops[2].dst_rtype, dis_uops[2].dst_rtype connect rob.io.enq_uops[2].ldst_val, dis_uops[2].ldst_val connect rob.io.enq_uops[2].lrs3, dis_uops[2].lrs3 connect rob.io.enq_uops[2].lrs2, dis_uops[2].lrs2 connect rob.io.enq_uops[2].lrs1, dis_uops[2].lrs1 connect rob.io.enq_uops[2].ldst, dis_uops[2].ldst connect rob.io.enq_uops[2].ldst_is_rs1, dis_uops[2].ldst_is_rs1 connect rob.io.enq_uops[2].flush_on_commit, dis_uops[2].flush_on_commit connect rob.io.enq_uops[2].is_unique, dis_uops[2].is_unique connect rob.io.enq_uops[2].is_sys_pc2epc, dis_uops[2].is_sys_pc2epc connect rob.io.enq_uops[2].uses_stq, dis_uops[2].uses_stq connect rob.io.enq_uops[2].uses_ldq, dis_uops[2].uses_ldq connect rob.io.enq_uops[2].is_amo, dis_uops[2].is_amo connect rob.io.enq_uops[2].is_fencei, dis_uops[2].is_fencei connect rob.io.enq_uops[2].is_fence, dis_uops[2].is_fence connect rob.io.enq_uops[2].mem_signed, dis_uops[2].mem_signed connect rob.io.enq_uops[2].mem_size, dis_uops[2].mem_size connect rob.io.enq_uops[2].mem_cmd, dis_uops[2].mem_cmd connect rob.io.enq_uops[2].bypassable, dis_uops[2].bypassable connect rob.io.enq_uops[2].exc_cause, dis_uops[2].exc_cause connect rob.io.enq_uops[2].exception, dis_uops[2].exception connect rob.io.enq_uops[2].stale_pdst, dis_uops[2].stale_pdst connect rob.io.enq_uops[2].ppred_busy, dis_uops[2].ppred_busy connect rob.io.enq_uops[2].prs3_busy, dis_uops[2].prs3_busy connect rob.io.enq_uops[2].prs2_busy, dis_uops[2].prs2_busy connect rob.io.enq_uops[2].prs1_busy, dis_uops[2].prs1_busy connect rob.io.enq_uops[2].ppred, dis_uops[2].ppred connect rob.io.enq_uops[2].prs3, dis_uops[2].prs3 connect rob.io.enq_uops[2].prs2, dis_uops[2].prs2 connect rob.io.enq_uops[2].prs1, dis_uops[2].prs1 connect rob.io.enq_uops[2].pdst, dis_uops[2].pdst connect rob.io.enq_uops[2].rxq_idx, dis_uops[2].rxq_idx connect rob.io.enq_uops[2].stq_idx, dis_uops[2].stq_idx connect rob.io.enq_uops[2].ldq_idx, dis_uops[2].ldq_idx connect rob.io.enq_uops[2].rob_idx, dis_uops[2].rob_idx connect rob.io.enq_uops[2].csr_addr, dis_uops[2].csr_addr connect rob.io.enq_uops[2].imm_packed, dis_uops[2].imm_packed connect rob.io.enq_uops[2].taken, dis_uops[2].taken connect rob.io.enq_uops[2].pc_lob, dis_uops[2].pc_lob connect rob.io.enq_uops[2].edge_inst, dis_uops[2].edge_inst connect rob.io.enq_uops[2].ftq_idx, dis_uops[2].ftq_idx connect rob.io.enq_uops[2].br_tag, dis_uops[2].br_tag connect rob.io.enq_uops[2].br_mask, dis_uops[2].br_mask connect rob.io.enq_uops[2].is_sfb, dis_uops[2].is_sfb connect rob.io.enq_uops[2].is_jal, dis_uops[2].is_jal connect rob.io.enq_uops[2].is_jalr, dis_uops[2].is_jalr connect rob.io.enq_uops[2].is_br, dis_uops[2].is_br connect rob.io.enq_uops[2].iw_p2_poisoned, dis_uops[2].iw_p2_poisoned connect rob.io.enq_uops[2].iw_p1_poisoned, dis_uops[2].iw_p1_poisoned connect rob.io.enq_uops[2].iw_state, dis_uops[2].iw_state connect rob.io.enq_uops[2].ctrl.is_std, dis_uops[2].ctrl.is_std connect rob.io.enq_uops[2].ctrl.is_sta, dis_uops[2].ctrl.is_sta connect rob.io.enq_uops[2].ctrl.is_load, dis_uops[2].ctrl.is_load connect rob.io.enq_uops[2].ctrl.csr_cmd, dis_uops[2].ctrl.csr_cmd connect rob.io.enq_uops[2].ctrl.fcn_dw, dis_uops[2].ctrl.fcn_dw connect rob.io.enq_uops[2].ctrl.op_fcn, dis_uops[2].ctrl.op_fcn connect rob.io.enq_uops[2].ctrl.imm_sel, dis_uops[2].ctrl.imm_sel connect rob.io.enq_uops[2].ctrl.op2_sel, dis_uops[2].ctrl.op2_sel connect rob.io.enq_uops[2].ctrl.op1_sel, dis_uops[2].ctrl.op1_sel connect rob.io.enq_uops[2].ctrl.br_type, dis_uops[2].ctrl.br_type connect rob.io.enq_uops[2].fu_code, dis_uops[2].fu_code connect rob.io.enq_uops[2].iq_type, dis_uops[2].iq_type connect rob.io.enq_uops[2].debug_pc, dis_uops[2].debug_pc connect rob.io.enq_uops[2].is_rvc, dis_uops[2].is_rvc connect rob.io.enq_uops[2].debug_inst, dis_uops[2].debug_inst connect rob.io.enq_uops[2].inst, dis_uops[2].inst connect rob.io.enq_uops[2].uopc, dis_uops[2].uopc connect rob.io.enq_partial_stall, dis_stalls_2 connect rob.io.debug_tsc, debug_tsc_reg connect rob.io.csr_stall, csr.io.csr_stall node _T_44 = or(dis_fire[0], dis_fire[1]) node _T_45 = or(_T_44, dis_fire[2]) node _T_46 = mux(dis_fire[1], UInt<1>(0h1), UInt<2>(0h2)) node _T_47 = mux(dis_fire[0], UInt<1>(0h0), _T_46) node _T_48 = and(_T_45, dis_uops[_T_47].is_sys_pc2epc) reg REG_3 : UInt<1>, clock connect REG_3, _T_48 when REG_3 : connect io.ifu.commit.valid, UInt<1>(0h1) node _io_ifu_commit_bits_T_1 = mux(dis_valids[1], UInt<1>(0h1), UInt<2>(0h2)) node _io_ifu_commit_bits_T_2 = mux(dis_valids[0], UInt<1>(0h0), _io_ifu_commit_bits_T_1) reg io_ifu_commit_bits_REG : UInt, clock connect io_ifu_commit_bits_REG, dis_uops[_io_ifu_commit_bits_T_2].ftq_idx connect io.ifu.commit.bits, io_ifu_commit_bits_REG node _dis_uops_0_rob_idx_T = dshr(rob.io.rob_tail_idx, UInt<2>(0h2)) node _dis_uops_0_rob_idx_T_1 = cat(_dis_uops_0_rob_idx_T, UInt<2>(0h0)) connect dis_uops[0].rob_idx, _dis_uops_0_rob_idx_T_1 node _dis_uops_1_rob_idx_T = dshr(rob.io.rob_tail_idx, UInt<2>(0h2)) node _dis_uops_1_rob_idx_T_1 = cat(_dis_uops_1_rob_idx_T, UInt<2>(0h1)) connect dis_uops[1].rob_idx, _dis_uops_1_rob_idx_T_1 node _dis_uops_2_rob_idx_T = dshr(rob.io.rob_tail_idx, UInt<2>(0h2)) node _dis_uops_2_rob_idx_T_1 = cat(_dis_uops_2_rob_idx_T, UInt<2>(0h2)) connect dis_uops[2].rob_idx, _dis_uops_2_rob_idx_T_1 connect dispatcher.io.ren_uops[0].valid, dis_fire[0] connect dispatcher.io.ren_uops[0].bits.debug_tsrc, dis_uops[0].debug_tsrc connect dispatcher.io.ren_uops[0].bits.debug_fsrc, dis_uops[0].debug_fsrc connect dispatcher.io.ren_uops[0].bits.bp_xcpt_if, dis_uops[0].bp_xcpt_if connect dispatcher.io.ren_uops[0].bits.bp_debug_if, dis_uops[0].bp_debug_if connect dispatcher.io.ren_uops[0].bits.xcpt_ma_if, dis_uops[0].xcpt_ma_if connect dispatcher.io.ren_uops[0].bits.xcpt_ae_if, dis_uops[0].xcpt_ae_if connect dispatcher.io.ren_uops[0].bits.xcpt_pf_if, dis_uops[0].xcpt_pf_if connect dispatcher.io.ren_uops[0].bits.fp_single, dis_uops[0].fp_single connect dispatcher.io.ren_uops[0].bits.fp_val, dis_uops[0].fp_val connect dispatcher.io.ren_uops[0].bits.frs3_en, dis_uops[0].frs3_en connect dispatcher.io.ren_uops[0].bits.lrs2_rtype, dis_uops[0].lrs2_rtype connect dispatcher.io.ren_uops[0].bits.lrs1_rtype, dis_uops[0].lrs1_rtype connect dispatcher.io.ren_uops[0].bits.dst_rtype, dis_uops[0].dst_rtype connect dispatcher.io.ren_uops[0].bits.ldst_val, dis_uops[0].ldst_val connect dispatcher.io.ren_uops[0].bits.lrs3, dis_uops[0].lrs3 connect dispatcher.io.ren_uops[0].bits.lrs2, dis_uops[0].lrs2 connect dispatcher.io.ren_uops[0].bits.lrs1, dis_uops[0].lrs1 connect dispatcher.io.ren_uops[0].bits.ldst, dis_uops[0].ldst connect dispatcher.io.ren_uops[0].bits.ldst_is_rs1, dis_uops[0].ldst_is_rs1 connect dispatcher.io.ren_uops[0].bits.flush_on_commit, dis_uops[0].flush_on_commit connect dispatcher.io.ren_uops[0].bits.is_unique, dis_uops[0].is_unique connect dispatcher.io.ren_uops[0].bits.is_sys_pc2epc, dis_uops[0].is_sys_pc2epc connect dispatcher.io.ren_uops[0].bits.uses_stq, dis_uops[0].uses_stq connect dispatcher.io.ren_uops[0].bits.uses_ldq, dis_uops[0].uses_ldq connect dispatcher.io.ren_uops[0].bits.is_amo, dis_uops[0].is_amo connect dispatcher.io.ren_uops[0].bits.is_fencei, dis_uops[0].is_fencei connect dispatcher.io.ren_uops[0].bits.is_fence, dis_uops[0].is_fence connect dispatcher.io.ren_uops[0].bits.mem_signed, dis_uops[0].mem_signed connect dispatcher.io.ren_uops[0].bits.mem_size, dis_uops[0].mem_size connect dispatcher.io.ren_uops[0].bits.mem_cmd, dis_uops[0].mem_cmd connect dispatcher.io.ren_uops[0].bits.bypassable, dis_uops[0].bypassable connect dispatcher.io.ren_uops[0].bits.exc_cause, dis_uops[0].exc_cause connect dispatcher.io.ren_uops[0].bits.exception, dis_uops[0].exception connect dispatcher.io.ren_uops[0].bits.stale_pdst, dis_uops[0].stale_pdst connect dispatcher.io.ren_uops[0].bits.ppred_busy, dis_uops[0].ppred_busy connect dispatcher.io.ren_uops[0].bits.prs3_busy, dis_uops[0].prs3_busy connect dispatcher.io.ren_uops[0].bits.prs2_busy, dis_uops[0].prs2_busy connect dispatcher.io.ren_uops[0].bits.prs1_busy, dis_uops[0].prs1_busy connect dispatcher.io.ren_uops[0].bits.ppred, dis_uops[0].ppred connect dispatcher.io.ren_uops[0].bits.prs3, dis_uops[0].prs3 connect dispatcher.io.ren_uops[0].bits.prs2, dis_uops[0].prs2 connect dispatcher.io.ren_uops[0].bits.prs1, dis_uops[0].prs1 connect dispatcher.io.ren_uops[0].bits.pdst, dis_uops[0].pdst connect dispatcher.io.ren_uops[0].bits.rxq_idx, dis_uops[0].rxq_idx connect dispatcher.io.ren_uops[0].bits.stq_idx, dis_uops[0].stq_idx connect dispatcher.io.ren_uops[0].bits.ldq_idx, dis_uops[0].ldq_idx connect dispatcher.io.ren_uops[0].bits.rob_idx, dis_uops[0].rob_idx connect dispatcher.io.ren_uops[0].bits.csr_addr, dis_uops[0].csr_addr connect dispatcher.io.ren_uops[0].bits.imm_packed, dis_uops[0].imm_packed connect dispatcher.io.ren_uops[0].bits.taken, dis_uops[0].taken connect dispatcher.io.ren_uops[0].bits.pc_lob, dis_uops[0].pc_lob connect dispatcher.io.ren_uops[0].bits.edge_inst, dis_uops[0].edge_inst connect dispatcher.io.ren_uops[0].bits.ftq_idx, dis_uops[0].ftq_idx connect dispatcher.io.ren_uops[0].bits.br_tag, dis_uops[0].br_tag connect dispatcher.io.ren_uops[0].bits.br_mask, dis_uops[0].br_mask connect dispatcher.io.ren_uops[0].bits.is_sfb, dis_uops[0].is_sfb connect dispatcher.io.ren_uops[0].bits.is_jal, dis_uops[0].is_jal connect dispatcher.io.ren_uops[0].bits.is_jalr, dis_uops[0].is_jalr connect dispatcher.io.ren_uops[0].bits.is_br, dis_uops[0].is_br connect dispatcher.io.ren_uops[0].bits.iw_p2_poisoned, dis_uops[0].iw_p2_poisoned connect dispatcher.io.ren_uops[0].bits.iw_p1_poisoned, dis_uops[0].iw_p1_poisoned connect dispatcher.io.ren_uops[0].bits.iw_state, dis_uops[0].iw_state connect dispatcher.io.ren_uops[0].bits.ctrl.is_std, dis_uops[0].ctrl.is_std connect dispatcher.io.ren_uops[0].bits.ctrl.is_sta, dis_uops[0].ctrl.is_sta connect dispatcher.io.ren_uops[0].bits.ctrl.is_load, dis_uops[0].ctrl.is_load connect dispatcher.io.ren_uops[0].bits.ctrl.csr_cmd, dis_uops[0].ctrl.csr_cmd connect dispatcher.io.ren_uops[0].bits.ctrl.fcn_dw, dis_uops[0].ctrl.fcn_dw connect dispatcher.io.ren_uops[0].bits.ctrl.op_fcn, dis_uops[0].ctrl.op_fcn connect dispatcher.io.ren_uops[0].bits.ctrl.imm_sel, dis_uops[0].ctrl.imm_sel connect dispatcher.io.ren_uops[0].bits.ctrl.op2_sel, dis_uops[0].ctrl.op2_sel connect dispatcher.io.ren_uops[0].bits.ctrl.op1_sel, dis_uops[0].ctrl.op1_sel connect dispatcher.io.ren_uops[0].bits.ctrl.br_type, dis_uops[0].ctrl.br_type connect dispatcher.io.ren_uops[0].bits.fu_code, dis_uops[0].fu_code connect dispatcher.io.ren_uops[0].bits.iq_type, dis_uops[0].iq_type connect dispatcher.io.ren_uops[0].bits.debug_pc, dis_uops[0].debug_pc connect dispatcher.io.ren_uops[0].bits.is_rvc, dis_uops[0].is_rvc connect dispatcher.io.ren_uops[0].bits.debug_inst, dis_uops[0].debug_inst connect dispatcher.io.ren_uops[0].bits.inst, dis_uops[0].inst connect dispatcher.io.ren_uops[0].bits.uopc, dis_uops[0].uopc connect dispatcher.io.ren_uops[1].valid, dis_fire[1] connect dispatcher.io.ren_uops[1].bits.debug_tsrc, dis_uops[1].debug_tsrc connect dispatcher.io.ren_uops[1].bits.debug_fsrc, dis_uops[1].debug_fsrc connect dispatcher.io.ren_uops[1].bits.bp_xcpt_if, dis_uops[1].bp_xcpt_if connect dispatcher.io.ren_uops[1].bits.bp_debug_if, dis_uops[1].bp_debug_if connect dispatcher.io.ren_uops[1].bits.xcpt_ma_if, dis_uops[1].xcpt_ma_if connect dispatcher.io.ren_uops[1].bits.xcpt_ae_if, dis_uops[1].xcpt_ae_if connect dispatcher.io.ren_uops[1].bits.xcpt_pf_if, dis_uops[1].xcpt_pf_if connect dispatcher.io.ren_uops[1].bits.fp_single, dis_uops[1].fp_single connect dispatcher.io.ren_uops[1].bits.fp_val, dis_uops[1].fp_val connect dispatcher.io.ren_uops[1].bits.frs3_en, dis_uops[1].frs3_en connect dispatcher.io.ren_uops[1].bits.lrs2_rtype, dis_uops[1].lrs2_rtype connect dispatcher.io.ren_uops[1].bits.lrs1_rtype, dis_uops[1].lrs1_rtype connect dispatcher.io.ren_uops[1].bits.dst_rtype, dis_uops[1].dst_rtype connect dispatcher.io.ren_uops[1].bits.ldst_val, dis_uops[1].ldst_val connect dispatcher.io.ren_uops[1].bits.lrs3, dis_uops[1].lrs3 connect dispatcher.io.ren_uops[1].bits.lrs2, dis_uops[1].lrs2 connect dispatcher.io.ren_uops[1].bits.lrs1, dis_uops[1].lrs1 connect dispatcher.io.ren_uops[1].bits.ldst, dis_uops[1].ldst connect dispatcher.io.ren_uops[1].bits.ldst_is_rs1, dis_uops[1].ldst_is_rs1 connect dispatcher.io.ren_uops[1].bits.flush_on_commit, dis_uops[1].flush_on_commit connect dispatcher.io.ren_uops[1].bits.is_unique, dis_uops[1].is_unique connect dispatcher.io.ren_uops[1].bits.is_sys_pc2epc, dis_uops[1].is_sys_pc2epc connect dispatcher.io.ren_uops[1].bits.uses_stq, dis_uops[1].uses_stq connect dispatcher.io.ren_uops[1].bits.uses_ldq, dis_uops[1].uses_ldq connect dispatcher.io.ren_uops[1].bits.is_amo, dis_uops[1].is_amo connect dispatcher.io.ren_uops[1].bits.is_fencei, dis_uops[1].is_fencei connect dispatcher.io.ren_uops[1].bits.is_fence, dis_uops[1].is_fence connect dispatcher.io.ren_uops[1].bits.mem_signed, dis_uops[1].mem_signed connect dispatcher.io.ren_uops[1].bits.mem_size, dis_uops[1].mem_size connect dispatcher.io.ren_uops[1].bits.mem_cmd, dis_uops[1].mem_cmd connect dispatcher.io.ren_uops[1].bits.bypassable, dis_uops[1].bypassable connect dispatcher.io.ren_uops[1].bits.exc_cause, dis_uops[1].exc_cause connect dispatcher.io.ren_uops[1].bits.exception, dis_uops[1].exception connect dispatcher.io.ren_uops[1].bits.stale_pdst, dis_uops[1].stale_pdst connect dispatcher.io.ren_uops[1].bits.ppred_busy, dis_uops[1].ppred_busy connect dispatcher.io.ren_uops[1].bits.prs3_busy, dis_uops[1].prs3_busy connect dispatcher.io.ren_uops[1].bits.prs2_busy, dis_uops[1].prs2_busy connect dispatcher.io.ren_uops[1].bits.prs1_busy, dis_uops[1].prs1_busy connect dispatcher.io.ren_uops[1].bits.ppred, dis_uops[1].ppred connect dispatcher.io.ren_uops[1].bits.prs3, dis_uops[1].prs3 connect dispatcher.io.ren_uops[1].bits.prs2, dis_uops[1].prs2 connect dispatcher.io.ren_uops[1].bits.prs1, dis_uops[1].prs1 connect dispatcher.io.ren_uops[1].bits.pdst, dis_uops[1].pdst connect dispatcher.io.ren_uops[1].bits.rxq_idx, dis_uops[1].rxq_idx connect dispatcher.io.ren_uops[1].bits.stq_idx, dis_uops[1].stq_idx connect dispatcher.io.ren_uops[1].bits.ldq_idx, dis_uops[1].ldq_idx connect dispatcher.io.ren_uops[1].bits.rob_idx, dis_uops[1].rob_idx connect dispatcher.io.ren_uops[1].bits.csr_addr, dis_uops[1].csr_addr connect dispatcher.io.ren_uops[1].bits.imm_packed, dis_uops[1].imm_packed connect dispatcher.io.ren_uops[1].bits.taken, dis_uops[1].taken connect dispatcher.io.ren_uops[1].bits.pc_lob, dis_uops[1].pc_lob connect dispatcher.io.ren_uops[1].bits.edge_inst, dis_uops[1].edge_inst connect dispatcher.io.ren_uops[1].bits.ftq_idx, dis_uops[1].ftq_idx connect dispatcher.io.ren_uops[1].bits.br_tag, dis_uops[1].br_tag connect dispatcher.io.ren_uops[1].bits.br_mask, dis_uops[1].br_mask connect dispatcher.io.ren_uops[1].bits.is_sfb, dis_uops[1].is_sfb connect dispatcher.io.ren_uops[1].bits.is_jal, dis_uops[1].is_jal connect dispatcher.io.ren_uops[1].bits.is_jalr, dis_uops[1].is_jalr connect dispatcher.io.ren_uops[1].bits.is_br, dis_uops[1].is_br connect dispatcher.io.ren_uops[1].bits.iw_p2_poisoned, dis_uops[1].iw_p2_poisoned connect dispatcher.io.ren_uops[1].bits.iw_p1_poisoned, dis_uops[1].iw_p1_poisoned connect dispatcher.io.ren_uops[1].bits.iw_state, dis_uops[1].iw_state connect dispatcher.io.ren_uops[1].bits.ctrl.is_std, dis_uops[1].ctrl.is_std connect dispatcher.io.ren_uops[1].bits.ctrl.is_sta, dis_uops[1].ctrl.is_sta connect dispatcher.io.ren_uops[1].bits.ctrl.is_load, dis_uops[1].ctrl.is_load connect dispatcher.io.ren_uops[1].bits.ctrl.csr_cmd, dis_uops[1].ctrl.csr_cmd connect dispatcher.io.ren_uops[1].bits.ctrl.fcn_dw, dis_uops[1].ctrl.fcn_dw connect dispatcher.io.ren_uops[1].bits.ctrl.op_fcn, dis_uops[1].ctrl.op_fcn connect dispatcher.io.ren_uops[1].bits.ctrl.imm_sel, dis_uops[1].ctrl.imm_sel connect dispatcher.io.ren_uops[1].bits.ctrl.op2_sel, dis_uops[1].ctrl.op2_sel connect dispatcher.io.ren_uops[1].bits.ctrl.op1_sel, dis_uops[1].ctrl.op1_sel connect dispatcher.io.ren_uops[1].bits.ctrl.br_type, dis_uops[1].ctrl.br_type connect dispatcher.io.ren_uops[1].bits.fu_code, dis_uops[1].fu_code connect dispatcher.io.ren_uops[1].bits.iq_type, dis_uops[1].iq_type connect dispatcher.io.ren_uops[1].bits.debug_pc, dis_uops[1].debug_pc connect dispatcher.io.ren_uops[1].bits.is_rvc, dis_uops[1].is_rvc connect dispatcher.io.ren_uops[1].bits.debug_inst, dis_uops[1].debug_inst connect dispatcher.io.ren_uops[1].bits.inst, dis_uops[1].inst connect dispatcher.io.ren_uops[1].bits.uopc, dis_uops[1].uopc connect dispatcher.io.ren_uops[2].valid, dis_fire[2] connect dispatcher.io.ren_uops[2].bits.debug_tsrc, dis_uops[2].debug_tsrc connect dispatcher.io.ren_uops[2].bits.debug_fsrc, dis_uops[2].debug_fsrc connect dispatcher.io.ren_uops[2].bits.bp_xcpt_if, dis_uops[2].bp_xcpt_if connect dispatcher.io.ren_uops[2].bits.bp_debug_if, dis_uops[2].bp_debug_if connect dispatcher.io.ren_uops[2].bits.xcpt_ma_if, dis_uops[2].xcpt_ma_if connect dispatcher.io.ren_uops[2].bits.xcpt_ae_if, dis_uops[2].xcpt_ae_if connect dispatcher.io.ren_uops[2].bits.xcpt_pf_if, dis_uops[2].xcpt_pf_if connect dispatcher.io.ren_uops[2].bits.fp_single, dis_uops[2].fp_single connect dispatcher.io.ren_uops[2].bits.fp_val, dis_uops[2].fp_val connect dispatcher.io.ren_uops[2].bits.frs3_en, dis_uops[2].frs3_en connect dispatcher.io.ren_uops[2].bits.lrs2_rtype, dis_uops[2].lrs2_rtype connect dispatcher.io.ren_uops[2].bits.lrs1_rtype, dis_uops[2].lrs1_rtype connect dispatcher.io.ren_uops[2].bits.dst_rtype, dis_uops[2].dst_rtype connect dispatcher.io.ren_uops[2].bits.ldst_val, dis_uops[2].ldst_val connect dispatcher.io.ren_uops[2].bits.lrs3, dis_uops[2].lrs3 connect dispatcher.io.ren_uops[2].bits.lrs2, dis_uops[2].lrs2 connect dispatcher.io.ren_uops[2].bits.lrs1, dis_uops[2].lrs1 connect dispatcher.io.ren_uops[2].bits.ldst, dis_uops[2].ldst connect dispatcher.io.ren_uops[2].bits.ldst_is_rs1, dis_uops[2].ldst_is_rs1 connect dispatcher.io.ren_uops[2].bits.flush_on_commit, dis_uops[2].flush_on_commit connect dispatcher.io.ren_uops[2].bits.is_unique, dis_uops[2].is_unique connect dispatcher.io.ren_uops[2].bits.is_sys_pc2epc, dis_uops[2].is_sys_pc2epc connect dispatcher.io.ren_uops[2].bits.uses_stq, dis_uops[2].uses_stq connect dispatcher.io.ren_uops[2].bits.uses_ldq, dis_uops[2].uses_ldq connect dispatcher.io.ren_uops[2].bits.is_amo, dis_uops[2].is_amo connect dispatcher.io.ren_uops[2].bits.is_fencei, dis_uops[2].is_fencei connect dispatcher.io.ren_uops[2].bits.is_fence, dis_uops[2].is_fence connect dispatcher.io.ren_uops[2].bits.mem_signed, dis_uops[2].mem_signed connect dispatcher.io.ren_uops[2].bits.mem_size, dis_uops[2].mem_size connect dispatcher.io.ren_uops[2].bits.mem_cmd, dis_uops[2].mem_cmd connect dispatcher.io.ren_uops[2].bits.bypassable, dis_uops[2].bypassable connect dispatcher.io.ren_uops[2].bits.exc_cause, dis_uops[2].exc_cause connect dispatcher.io.ren_uops[2].bits.exception, dis_uops[2].exception connect dispatcher.io.ren_uops[2].bits.stale_pdst, dis_uops[2].stale_pdst connect dispatcher.io.ren_uops[2].bits.ppred_busy, dis_uops[2].ppred_busy connect dispatcher.io.ren_uops[2].bits.prs3_busy, dis_uops[2].prs3_busy connect dispatcher.io.ren_uops[2].bits.prs2_busy, dis_uops[2].prs2_busy connect dispatcher.io.ren_uops[2].bits.prs1_busy, dis_uops[2].prs1_busy connect dispatcher.io.ren_uops[2].bits.ppred, dis_uops[2].ppred connect dispatcher.io.ren_uops[2].bits.prs3, dis_uops[2].prs3 connect dispatcher.io.ren_uops[2].bits.prs2, dis_uops[2].prs2 connect dispatcher.io.ren_uops[2].bits.prs1, dis_uops[2].prs1 connect dispatcher.io.ren_uops[2].bits.pdst, dis_uops[2].pdst connect dispatcher.io.ren_uops[2].bits.rxq_idx, dis_uops[2].rxq_idx connect dispatcher.io.ren_uops[2].bits.stq_idx, dis_uops[2].stq_idx connect dispatcher.io.ren_uops[2].bits.ldq_idx, dis_uops[2].ldq_idx connect dispatcher.io.ren_uops[2].bits.rob_idx, dis_uops[2].rob_idx connect dispatcher.io.ren_uops[2].bits.csr_addr, dis_uops[2].csr_addr connect dispatcher.io.ren_uops[2].bits.imm_packed, dis_uops[2].imm_packed connect dispatcher.io.ren_uops[2].bits.taken, dis_uops[2].taken connect dispatcher.io.ren_uops[2].bits.pc_lob, dis_uops[2].pc_lob connect dispatcher.io.ren_uops[2].bits.edge_inst, dis_uops[2].edge_inst connect dispatcher.io.ren_uops[2].bits.ftq_idx, dis_uops[2].ftq_idx connect dispatcher.io.ren_uops[2].bits.br_tag, dis_uops[2].br_tag connect dispatcher.io.ren_uops[2].bits.br_mask, dis_uops[2].br_mask connect dispatcher.io.ren_uops[2].bits.is_sfb, dis_uops[2].is_sfb connect dispatcher.io.ren_uops[2].bits.is_jal, dis_uops[2].is_jal connect dispatcher.io.ren_uops[2].bits.is_jalr, dis_uops[2].is_jalr connect dispatcher.io.ren_uops[2].bits.is_br, dis_uops[2].is_br connect dispatcher.io.ren_uops[2].bits.iw_p2_poisoned, dis_uops[2].iw_p2_poisoned connect dispatcher.io.ren_uops[2].bits.iw_p1_poisoned, dis_uops[2].iw_p1_poisoned connect dispatcher.io.ren_uops[2].bits.iw_state, dis_uops[2].iw_state connect dispatcher.io.ren_uops[2].bits.ctrl.is_std, dis_uops[2].ctrl.is_std connect dispatcher.io.ren_uops[2].bits.ctrl.is_sta, dis_uops[2].ctrl.is_sta connect dispatcher.io.ren_uops[2].bits.ctrl.is_load, dis_uops[2].ctrl.is_load connect dispatcher.io.ren_uops[2].bits.ctrl.csr_cmd, dis_uops[2].ctrl.csr_cmd connect dispatcher.io.ren_uops[2].bits.ctrl.fcn_dw, dis_uops[2].ctrl.fcn_dw connect dispatcher.io.ren_uops[2].bits.ctrl.op_fcn, dis_uops[2].ctrl.op_fcn connect dispatcher.io.ren_uops[2].bits.ctrl.imm_sel, dis_uops[2].ctrl.imm_sel connect dispatcher.io.ren_uops[2].bits.ctrl.op2_sel, dis_uops[2].ctrl.op2_sel connect dispatcher.io.ren_uops[2].bits.ctrl.op1_sel, dis_uops[2].ctrl.op1_sel connect dispatcher.io.ren_uops[2].bits.ctrl.br_type, dis_uops[2].ctrl.br_type connect dispatcher.io.ren_uops[2].bits.fu_code, dis_uops[2].fu_code connect dispatcher.io.ren_uops[2].bits.iq_type, dis_uops[2].iq_type connect dispatcher.io.ren_uops[2].bits.debug_pc, dis_uops[2].debug_pc connect dispatcher.io.ren_uops[2].bits.is_rvc, dis_uops[2].is_rvc connect dispatcher.io.ren_uops[2].bits.debug_inst, dis_uops[2].debug_inst connect dispatcher.io.ren_uops[2].bits.inst, dis_uops[2].inst connect dispatcher.io.ren_uops[2].bits.uopc, dis_uops[2].uopc connect mem_issue_unit.io.dis_uops[0], dispatcher.io.dis_uops.`0`[0] connect mem_issue_unit.io.dis_uops[1], dispatcher.io.dis_uops.`0`[1] connect mem_issue_unit.io.dis_uops[2], dispatcher.io.dis_uops.`0`[2] connect int_issue_unit.io.dis_uops[0], dispatcher.io.dis_uops.`1`[0] connect int_issue_unit.io.dis_uops[1], dispatcher.io.dis_uops.`1`[1] connect int_issue_unit.io.dis_uops[2], dispatcher.io.dis_uops.`1`[2] connect FpPipeline.io.dis_uops[0], dispatcher.io.dis_uops.`2`[0] connect FpPipeline.io.dis_uops[1], dispatcher.io.dis_uops.`2`[1] connect FpPipeline.io.dis_uops[2], dispatcher.io.dis_uops.`2`[2] node _int_iss_wakeups_0_valid_T = and(ll_wbarb.io.out.ready, ll_wbarb.io.out.valid) node _int_iss_wakeups_0_valid_T_1 = eq(ll_wbarb.io.out.bits.uop.dst_rtype, UInt<2>(0h0)) node _int_iss_wakeups_0_valid_T_2 = and(_int_iss_wakeups_0_valid_T, _int_iss_wakeups_0_valid_T_1) connect int_iss_wakeups[0].valid, _int_iss_wakeups_0_valid_T_2 connect int_iss_wakeups[0].bits, ll_wbarb.io.out.bits node _int_ren_wakeups_0_valid_T = and(ll_wbarb.io.out.ready, ll_wbarb.io.out.valid) node _int_ren_wakeups_0_valid_T_1 = eq(ll_wbarb.io.out.bits.uop.dst_rtype, UInt<2>(0h0)) node _int_ren_wakeups_0_valid_T_2 = and(_int_ren_wakeups_0_valid_T, _int_ren_wakeups_0_valid_T_1) connect int_ren_wakeups[0].valid, _int_ren_wakeups_0_valid_T_2 connect int_ren_wakeups[0].bits, ll_wbarb.io.out.bits wire fast_wakeup : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}} wire slow_wakeup : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}} invalidate fast_wakeup.bits.fflags.bits.flags invalidate fast_wakeup.bits.fflags.bits.uop.debug_tsrc invalidate fast_wakeup.bits.fflags.bits.uop.debug_fsrc invalidate fast_wakeup.bits.fflags.bits.uop.bp_xcpt_if invalidate fast_wakeup.bits.fflags.bits.uop.bp_debug_if invalidate fast_wakeup.bits.fflags.bits.uop.xcpt_ma_if invalidate fast_wakeup.bits.fflags.bits.uop.xcpt_ae_if invalidate fast_wakeup.bits.fflags.bits.uop.xcpt_pf_if invalidate fast_wakeup.bits.fflags.bits.uop.fp_single invalidate fast_wakeup.bits.fflags.bits.uop.fp_val invalidate fast_wakeup.bits.fflags.bits.uop.frs3_en invalidate fast_wakeup.bits.fflags.bits.uop.lrs2_rtype invalidate fast_wakeup.bits.fflags.bits.uop.lrs1_rtype invalidate fast_wakeup.bits.fflags.bits.uop.dst_rtype invalidate fast_wakeup.bits.fflags.bits.uop.ldst_val invalidate fast_wakeup.bits.fflags.bits.uop.lrs3 invalidate fast_wakeup.bits.fflags.bits.uop.lrs2 invalidate fast_wakeup.bits.fflags.bits.uop.lrs1 invalidate fast_wakeup.bits.fflags.bits.uop.ldst invalidate fast_wakeup.bits.fflags.bits.uop.ldst_is_rs1 invalidate fast_wakeup.bits.fflags.bits.uop.flush_on_commit invalidate fast_wakeup.bits.fflags.bits.uop.is_unique invalidate fast_wakeup.bits.fflags.bits.uop.is_sys_pc2epc invalidate fast_wakeup.bits.fflags.bits.uop.uses_stq invalidate fast_wakeup.bits.fflags.bits.uop.uses_ldq invalidate fast_wakeup.bits.fflags.bits.uop.is_amo invalidate fast_wakeup.bits.fflags.bits.uop.is_fencei invalidate fast_wakeup.bits.fflags.bits.uop.is_fence invalidate fast_wakeup.bits.fflags.bits.uop.mem_signed invalidate fast_wakeup.bits.fflags.bits.uop.mem_size invalidate fast_wakeup.bits.fflags.bits.uop.mem_cmd invalidate fast_wakeup.bits.fflags.bits.uop.bypassable invalidate fast_wakeup.bits.fflags.bits.uop.exc_cause invalidate fast_wakeup.bits.fflags.bits.uop.exception invalidate fast_wakeup.bits.fflags.bits.uop.stale_pdst invalidate fast_wakeup.bits.fflags.bits.uop.ppred_busy invalidate fast_wakeup.bits.fflags.bits.uop.prs3_busy invalidate fast_wakeup.bits.fflags.bits.uop.prs2_busy invalidate fast_wakeup.bits.fflags.bits.uop.prs1_busy invalidate fast_wakeup.bits.fflags.bits.uop.ppred invalidate fast_wakeup.bits.fflags.bits.uop.prs3 invalidate fast_wakeup.bits.fflags.bits.uop.prs2 invalidate fast_wakeup.bits.fflags.bits.uop.prs1 invalidate fast_wakeup.bits.fflags.bits.uop.pdst invalidate fast_wakeup.bits.fflags.bits.uop.rxq_idx invalidate fast_wakeup.bits.fflags.bits.uop.stq_idx invalidate fast_wakeup.bits.fflags.bits.uop.ldq_idx invalidate fast_wakeup.bits.fflags.bits.uop.rob_idx invalidate fast_wakeup.bits.fflags.bits.uop.csr_addr invalidate fast_wakeup.bits.fflags.bits.uop.imm_packed invalidate fast_wakeup.bits.fflags.bits.uop.taken invalidate fast_wakeup.bits.fflags.bits.uop.pc_lob invalidate fast_wakeup.bits.fflags.bits.uop.edge_inst invalidate fast_wakeup.bits.fflags.bits.uop.ftq_idx invalidate fast_wakeup.bits.fflags.bits.uop.br_tag invalidate fast_wakeup.bits.fflags.bits.uop.br_mask invalidate fast_wakeup.bits.fflags.bits.uop.is_sfb invalidate fast_wakeup.bits.fflags.bits.uop.is_jal invalidate fast_wakeup.bits.fflags.bits.uop.is_jalr invalidate fast_wakeup.bits.fflags.bits.uop.is_br invalidate fast_wakeup.bits.fflags.bits.uop.iw_p2_poisoned invalidate fast_wakeup.bits.fflags.bits.uop.iw_p1_poisoned invalidate fast_wakeup.bits.fflags.bits.uop.iw_state invalidate fast_wakeup.bits.fflags.bits.uop.ctrl.is_std invalidate fast_wakeup.bits.fflags.bits.uop.ctrl.is_sta invalidate fast_wakeup.bits.fflags.bits.uop.ctrl.is_load invalidate fast_wakeup.bits.fflags.bits.uop.ctrl.csr_cmd invalidate fast_wakeup.bits.fflags.bits.uop.ctrl.fcn_dw invalidate fast_wakeup.bits.fflags.bits.uop.ctrl.op_fcn invalidate fast_wakeup.bits.fflags.bits.uop.ctrl.imm_sel invalidate fast_wakeup.bits.fflags.bits.uop.ctrl.op2_sel invalidate fast_wakeup.bits.fflags.bits.uop.ctrl.op1_sel invalidate fast_wakeup.bits.fflags.bits.uop.ctrl.br_type invalidate fast_wakeup.bits.fflags.bits.uop.fu_code invalidate fast_wakeup.bits.fflags.bits.uop.iq_type invalidate fast_wakeup.bits.fflags.bits.uop.debug_pc invalidate fast_wakeup.bits.fflags.bits.uop.is_rvc invalidate fast_wakeup.bits.fflags.bits.uop.debug_inst invalidate fast_wakeup.bits.fflags.bits.uop.inst invalidate fast_wakeup.bits.fflags.bits.uop.uopc invalidate fast_wakeup.bits.fflags.valid invalidate fast_wakeup.bits.predicated invalidate fast_wakeup.bits.data invalidate fast_wakeup.bits.uop.debug_tsrc invalidate fast_wakeup.bits.uop.debug_fsrc invalidate fast_wakeup.bits.uop.bp_xcpt_if invalidate fast_wakeup.bits.uop.bp_debug_if invalidate fast_wakeup.bits.uop.xcpt_ma_if invalidate fast_wakeup.bits.uop.xcpt_ae_if invalidate fast_wakeup.bits.uop.xcpt_pf_if invalidate fast_wakeup.bits.uop.fp_single invalidate fast_wakeup.bits.uop.fp_val invalidate fast_wakeup.bits.uop.frs3_en invalidate fast_wakeup.bits.uop.lrs2_rtype invalidate fast_wakeup.bits.uop.lrs1_rtype invalidate fast_wakeup.bits.uop.dst_rtype invalidate fast_wakeup.bits.uop.ldst_val invalidate fast_wakeup.bits.uop.lrs3 invalidate fast_wakeup.bits.uop.lrs2 invalidate fast_wakeup.bits.uop.lrs1 invalidate fast_wakeup.bits.uop.ldst invalidate fast_wakeup.bits.uop.ldst_is_rs1 invalidate fast_wakeup.bits.uop.flush_on_commit invalidate fast_wakeup.bits.uop.is_unique invalidate fast_wakeup.bits.uop.is_sys_pc2epc invalidate fast_wakeup.bits.uop.uses_stq invalidate fast_wakeup.bits.uop.uses_ldq invalidate fast_wakeup.bits.uop.is_amo invalidate fast_wakeup.bits.uop.is_fencei invalidate fast_wakeup.bits.uop.is_fence invalidate fast_wakeup.bits.uop.mem_signed invalidate fast_wakeup.bits.uop.mem_size invalidate fast_wakeup.bits.uop.mem_cmd invalidate fast_wakeup.bits.uop.bypassable invalidate fast_wakeup.bits.uop.exc_cause invalidate fast_wakeup.bits.uop.exception invalidate fast_wakeup.bits.uop.stale_pdst invalidate fast_wakeup.bits.uop.ppred_busy invalidate fast_wakeup.bits.uop.prs3_busy invalidate fast_wakeup.bits.uop.prs2_busy invalidate fast_wakeup.bits.uop.prs1_busy invalidate fast_wakeup.bits.uop.ppred invalidate fast_wakeup.bits.uop.prs3 invalidate fast_wakeup.bits.uop.prs2 invalidate fast_wakeup.bits.uop.prs1 invalidate fast_wakeup.bits.uop.pdst invalidate fast_wakeup.bits.uop.rxq_idx invalidate fast_wakeup.bits.uop.stq_idx invalidate fast_wakeup.bits.uop.ldq_idx invalidate fast_wakeup.bits.uop.rob_idx invalidate fast_wakeup.bits.uop.csr_addr invalidate fast_wakeup.bits.uop.imm_packed invalidate fast_wakeup.bits.uop.taken invalidate fast_wakeup.bits.uop.pc_lob invalidate fast_wakeup.bits.uop.edge_inst invalidate fast_wakeup.bits.uop.ftq_idx invalidate fast_wakeup.bits.uop.br_tag invalidate fast_wakeup.bits.uop.br_mask invalidate fast_wakeup.bits.uop.is_sfb invalidate fast_wakeup.bits.uop.is_jal invalidate fast_wakeup.bits.uop.is_jalr invalidate fast_wakeup.bits.uop.is_br invalidate fast_wakeup.bits.uop.iw_p2_poisoned invalidate fast_wakeup.bits.uop.iw_p1_poisoned invalidate fast_wakeup.bits.uop.iw_state invalidate fast_wakeup.bits.uop.ctrl.is_std invalidate fast_wakeup.bits.uop.ctrl.is_sta invalidate fast_wakeup.bits.uop.ctrl.is_load invalidate fast_wakeup.bits.uop.ctrl.csr_cmd invalidate fast_wakeup.bits.uop.ctrl.fcn_dw invalidate fast_wakeup.bits.uop.ctrl.op_fcn invalidate fast_wakeup.bits.uop.ctrl.imm_sel invalidate fast_wakeup.bits.uop.ctrl.op2_sel invalidate fast_wakeup.bits.uop.ctrl.op1_sel invalidate fast_wakeup.bits.uop.ctrl.br_type invalidate fast_wakeup.bits.uop.fu_code invalidate fast_wakeup.bits.uop.iq_type invalidate fast_wakeup.bits.uop.debug_pc invalidate fast_wakeup.bits.uop.is_rvc invalidate fast_wakeup.bits.uop.debug_inst invalidate fast_wakeup.bits.uop.inst invalidate fast_wakeup.bits.uop.uopc invalidate fast_wakeup.valid invalidate slow_wakeup.bits.fflags.bits.flags invalidate slow_wakeup.bits.fflags.bits.uop.debug_tsrc invalidate slow_wakeup.bits.fflags.bits.uop.debug_fsrc invalidate slow_wakeup.bits.fflags.bits.uop.bp_xcpt_if invalidate slow_wakeup.bits.fflags.bits.uop.bp_debug_if invalidate slow_wakeup.bits.fflags.bits.uop.xcpt_ma_if invalidate slow_wakeup.bits.fflags.bits.uop.xcpt_ae_if invalidate slow_wakeup.bits.fflags.bits.uop.xcpt_pf_if invalidate slow_wakeup.bits.fflags.bits.uop.fp_single invalidate slow_wakeup.bits.fflags.bits.uop.fp_val invalidate slow_wakeup.bits.fflags.bits.uop.frs3_en invalidate slow_wakeup.bits.fflags.bits.uop.lrs2_rtype invalidate slow_wakeup.bits.fflags.bits.uop.lrs1_rtype invalidate slow_wakeup.bits.fflags.bits.uop.dst_rtype invalidate slow_wakeup.bits.fflags.bits.uop.ldst_val invalidate slow_wakeup.bits.fflags.bits.uop.lrs3 invalidate slow_wakeup.bits.fflags.bits.uop.lrs2 invalidate slow_wakeup.bits.fflags.bits.uop.lrs1 invalidate slow_wakeup.bits.fflags.bits.uop.ldst invalidate slow_wakeup.bits.fflags.bits.uop.ldst_is_rs1 invalidate slow_wakeup.bits.fflags.bits.uop.flush_on_commit invalidate slow_wakeup.bits.fflags.bits.uop.is_unique invalidate slow_wakeup.bits.fflags.bits.uop.is_sys_pc2epc invalidate slow_wakeup.bits.fflags.bits.uop.uses_stq invalidate slow_wakeup.bits.fflags.bits.uop.uses_ldq invalidate slow_wakeup.bits.fflags.bits.uop.is_amo invalidate slow_wakeup.bits.fflags.bits.uop.is_fencei invalidate slow_wakeup.bits.fflags.bits.uop.is_fence invalidate slow_wakeup.bits.fflags.bits.uop.mem_signed invalidate slow_wakeup.bits.fflags.bits.uop.mem_size invalidate slow_wakeup.bits.fflags.bits.uop.mem_cmd invalidate slow_wakeup.bits.fflags.bits.uop.bypassable invalidate slow_wakeup.bits.fflags.bits.uop.exc_cause invalidate slow_wakeup.bits.fflags.bits.uop.exception invalidate slow_wakeup.bits.fflags.bits.uop.stale_pdst invalidate slow_wakeup.bits.fflags.bits.uop.ppred_busy invalidate slow_wakeup.bits.fflags.bits.uop.prs3_busy invalidate slow_wakeup.bits.fflags.bits.uop.prs2_busy invalidate slow_wakeup.bits.fflags.bits.uop.prs1_busy invalidate slow_wakeup.bits.fflags.bits.uop.ppred invalidate slow_wakeup.bits.fflags.bits.uop.prs3 invalidate slow_wakeup.bits.fflags.bits.uop.prs2 invalidate slow_wakeup.bits.fflags.bits.uop.prs1 invalidate slow_wakeup.bits.fflags.bits.uop.pdst invalidate slow_wakeup.bits.fflags.bits.uop.rxq_idx invalidate slow_wakeup.bits.fflags.bits.uop.stq_idx invalidate slow_wakeup.bits.fflags.bits.uop.ldq_idx invalidate slow_wakeup.bits.fflags.bits.uop.rob_idx invalidate slow_wakeup.bits.fflags.bits.uop.csr_addr invalidate slow_wakeup.bits.fflags.bits.uop.imm_packed invalidate slow_wakeup.bits.fflags.bits.uop.taken invalidate slow_wakeup.bits.fflags.bits.uop.pc_lob invalidate slow_wakeup.bits.fflags.bits.uop.edge_inst invalidate slow_wakeup.bits.fflags.bits.uop.ftq_idx invalidate slow_wakeup.bits.fflags.bits.uop.br_tag invalidate slow_wakeup.bits.fflags.bits.uop.br_mask invalidate slow_wakeup.bits.fflags.bits.uop.is_sfb invalidate slow_wakeup.bits.fflags.bits.uop.is_jal invalidate slow_wakeup.bits.fflags.bits.uop.is_jalr invalidate slow_wakeup.bits.fflags.bits.uop.is_br invalidate slow_wakeup.bits.fflags.bits.uop.iw_p2_poisoned invalidate slow_wakeup.bits.fflags.bits.uop.iw_p1_poisoned invalidate slow_wakeup.bits.fflags.bits.uop.iw_state invalidate slow_wakeup.bits.fflags.bits.uop.ctrl.is_std invalidate slow_wakeup.bits.fflags.bits.uop.ctrl.is_sta invalidate slow_wakeup.bits.fflags.bits.uop.ctrl.is_load invalidate slow_wakeup.bits.fflags.bits.uop.ctrl.csr_cmd invalidate slow_wakeup.bits.fflags.bits.uop.ctrl.fcn_dw invalidate slow_wakeup.bits.fflags.bits.uop.ctrl.op_fcn invalidate slow_wakeup.bits.fflags.bits.uop.ctrl.imm_sel invalidate slow_wakeup.bits.fflags.bits.uop.ctrl.op2_sel invalidate slow_wakeup.bits.fflags.bits.uop.ctrl.op1_sel invalidate slow_wakeup.bits.fflags.bits.uop.ctrl.br_type invalidate slow_wakeup.bits.fflags.bits.uop.fu_code invalidate slow_wakeup.bits.fflags.bits.uop.iq_type invalidate slow_wakeup.bits.fflags.bits.uop.debug_pc invalidate slow_wakeup.bits.fflags.bits.uop.is_rvc invalidate slow_wakeup.bits.fflags.bits.uop.debug_inst invalidate slow_wakeup.bits.fflags.bits.uop.inst invalidate slow_wakeup.bits.fflags.bits.uop.uopc invalidate slow_wakeup.bits.fflags.valid invalidate slow_wakeup.bits.predicated invalidate slow_wakeup.bits.data invalidate slow_wakeup.bits.uop.debug_tsrc invalidate slow_wakeup.bits.uop.debug_fsrc invalidate slow_wakeup.bits.uop.bp_xcpt_if invalidate slow_wakeup.bits.uop.bp_debug_if invalidate slow_wakeup.bits.uop.xcpt_ma_if invalidate slow_wakeup.bits.uop.xcpt_ae_if invalidate slow_wakeup.bits.uop.xcpt_pf_if invalidate slow_wakeup.bits.uop.fp_single invalidate slow_wakeup.bits.uop.fp_val invalidate slow_wakeup.bits.uop.frs3_en invalidate slow_wakeup.bits.uop.lrs2_rtype invalidate slow_wakeup.bits.uop.lrs1_rtype invalidate slow_wakeup.bits.uop.dst_rtype invalidate slow_wakeup.bits.uop.ldst_val invalidate slow_wakeup.bits.uop.lrs3 invalidate slow_wakeup.bits.uop.lrs2 invalidate slow_wakeup.bits.uop.lrs1 invalidate slow_wakeup.bits.uop.ldst invalidate slow_wakeup.bits.uop.ldst_is_rs1 invalidate slow_wakeup.bits.uop.flush_on_commit invalidate slow_wakeup.bits.uop.is_unique invalidate slow_wakeup.bits.uop.is_sys_pc2epc invalidate slow_wakeup.bits.uop.uses_stq invalidate slow_wakeup.bits.uop.uses_ldq invalidate slow_wakeup.bits.uop.is_amo invalidate slow_wakeup.bits.uop.is_fencei invalidate slow_wakeup.bits.uop.is_fence invalidate slow_wakeup.bits.uop.mem_signed invalidate slow_wakeup.bits.uop.mem_size invalidate slow_wakeup.bits.uop.mem_cmd invalidate slow_wakeup.bits.uop.bypassable invalidate slow_wakeup.bits.uop.exc_cause invalidate slow_wakeup.bits.uop.exception invalidate slow_wakeup.bits.uop.stale_pdst invalidate slow_wakeup.bits.uop.ppred_busy invalidate slow_wakeup.bits.uop.prs3_busy invalidate slow_wakeup.bits.uop.prs2_busy invalidate slow_wakeup.bits.uop.prs1_busy invalidate slow_wakeup.bits.uop.ppred invalidate slow_wakeup.bits.uop.prs3 invalidate slow_wakeup.bits.uop.prs2 invalidate slow_wakeup.bits.uop.prs1 invalidate slow_wakeup.bits.uop.pdst invalidate slow_wakeup.bits.uop.rxq_idx invalidate slow_wakeup.bits.uop.stq_idx invalidate slow_wakeup.bits.uop.ldq_idx invalidate slow_wakeup.bits.uop.rob_idx invalidate slow_wakeup.bits.uop.csr_addr invalidate slow_wakeup.bits.uop.imm_packed invalidate slow_wakeup.bits.uop.taken invalidate slow_wakeup.bits.uop.pc_lob invalidate slow_wakeup.bits.uop.edge_inst invalidate slow_wakeup.bits.uop.ftq_idx invalidate slow_wakeup.bits.uop.br_tag invalidate slow_wakeup.bits.uop.br_mask invalidate slow_wakeup.bits.uop.is_sfb invalidate slow_wakeup.bits.uop.is_jal invalidate slow_wakeup.bits.uop.is_jalr invalidate slow_wakeup.bits.uop.is_br invalidate slow_wakeup.bits.uop.iw_p2_poisoned invalidate slow_wakeup.bits.uop.iw_p1_poisoned invalidate slow_wakeup.bits.uop.iw_state invalidate slow_wakeup.bits.uop.ctrl.is_std invalidate slow_wakeup.bits.uop.ctrl.is_sta invalidate slow_wakeup.bits.uop.ctrl.is_load invalidate slow_wakeup.bits.uop.ctrl.csr_cmd invalidate slow_wakeup.bits.uop.ctrl.fcn_dw invalidate slow_wakeup.bits.uop.ctrl.op_fcn invalidate slow_wakeup.bits.uop.ctrl.imm_sel invalidate slow_wakeup.bits.uop.ctrl.op2_sel invalidate slow_wakeup.bits.uop.ctrl.op1_sel invalidate slow_wakeup.bits.uop.ctrl.br_type invalidate slow_wakeup.bits.uop.fu_code invalidate slow_wakeup.bits.uop.iq_type invalidate slow_wakeup.bits.uop.debug_pc invalidate slow_wakeup.bits.uop.is_rvc invalidate slow_wakeup.bits.uop.debug_inst invalidate slow_wakeup.bits.uop.inst invalidate slow_wakeup.bits.uop.uopc invalidate slow_wakeup.valid node _T_49 = neq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _T_50 = and(alu_exe_unit.io.iresp.valid, _T_49) node _T_51 = neq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _T_52 = and(_T_50, _T_51) node _T_53 = eq(_T_52, UInt<1>(0h0)) node _T_54 = asUInt(reset) node _T_55 = eq(_T_54, UInt<1>(0h0)) when _T_55 : node _T_56 = eq(_T_53, UInt<1>(0h0)) when _T_56 : printf(clock, UInt<1>(0h1), "Assertion failed\n at core.scala:820 assert(!(resp.valid && resp.bits.uop.rf_wen && resp.bits.uop.dst_rtype =/= RT_FIX))\n") : printf_2 assert(clock, _T_53, UInt<1>(0h1), "") : assert_2 connect fast_wakeup.bits.uop, iss_uops[1] node _fast_wakeup_valid_T = and(iss_valids[1], iss_uops[1].bypassable) node _fast_wakeup_valid_T_1 = eq(iss_uops[1].dst_rtype, UInt<2>(0h0)) node _fast_wakeup_valid_T_2 = and(_fast_wakeup_valid_T, _fast_wakeup_valid_T_1) node _fast_wakeup_valid_T_3 = and(_fast_wakeup_valid_T_2, iss_uops[1].ldst_val) node _fast_wakeup_valid_T_4 = or(iss_uops[1].iw_p1_poisoned, iss_uops[1].iw_p2_poisoned) node _fast_wakeup_valid_T_5 = and(io.lsu.ld_miss, _fast_wakeup_valid_T_4) node _fast_wakeup_valid_T_6 = eq(_fast_wakeup_valid_T_5, UInt<1>(0h0)) node _fast_wakeup_valid_T_7 = and(_fast_wakeup_valid_T_3, _fast_wakeup_valid_T_6) connect fast_wakeup.valid, _fast_wakeup_valid_T_7 connect slow_wakeup.bits.uop, alu_exe_unit.io.iresp.bits.uop node _slow_wakeup_valid_T = neq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _slow_wakeup_valid_T_1 = and(alu_exe_unit.io.iresp.valid, _slow_wakeup_valid_T) node _slow_wakeup_valid_T_2 = eq(alu_exe_unit.io.iresp.bits.uop.bypassable, UInt<1>(0h0)) node _slow_wakeup_valid_T_3 = and(_slow_wakeup_valid_T_1, _slow_wakeup_valid_T_2) node _slow_wakeup_valid_T_4 = eq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _slow_wakeup_valid_T_5 = and(_slow_wakeup_valid_T_3, _slow_wakeup_valid_T_4) connect slow_wakeup.valid, _slow_wakeup_valid_T_5 connect int_iss_wakeups[1], fast_wakeup connect int_iss_wakeups[2], slow_wakeup connect int_ren_wakeups[1], fast_wakeup connect int_ren_wakeups[2], slow_wakeup wire fast_wakeup_1 : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}} wire slow_wakeup_1 : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}} invalidate fast_wakeup_1.bits.fflags.bits.flags invalidate fast_wakeup_1.bits.fflags.bits.uop.debug_tsrc invalidate fast_wakeup_1.bits.fflags.bits.uop.debug_fsrc invalidate fast_wakeup_1.bits.fflags.bits.uop.bp_xcpt_if invalidate fast_wakeup_1.bits.fflags.bits.uop.bp_debug_if invalidate fast_wakeup_1.bits.fflags.bits.uop.xcpt_ma_if invalidate fast_wakeup_1.bits.fflags.bits.uop.xcpt_ae_if invalidate fast_wakeup_1.bits.fflags.bits.uop.xcpt_pf_if invalidate fast_wakeup_1.bits.fflags.bits.uop.fp_single invalidate fast_wakeup_1.bits.fflags.bits.uop.fp_val invalidate fast_wakeup_1.bits.fflags.bits.uop.frs3_en invalidate fast_wakeup_1.bits.fflags.bits.uop.lrs2_rtype invalidate fast_wakeup_1.bits.fflags.bits.uop.lrs1_rtype invalidate fast_wakeup_1.bits.fflags.bits.uop.dst_rtype invalidate fast_wakeup_1.bits.fflags.bits.uop.ldst_val invalidate fast_wakeup_1.bits.fflags.bits.uop.lrs3 invalidate fast_wakeup_1.bits.fflags.bits.uop.lrs2 invalidate fast_wakeup_1.bits.fflags.bits.uop.lrs1 invalidate fast_wakeup_1.bits.fflags.bits.uop.ldst invalidate fast_wakeup_1.bits.fflags.bits.uop.ldst_is_rs1 invalidate fast_wakeup_1.bits.fflags.bits.uop.flush_on_commit invalidate fast_wakeup_1.bits.fflags.bits.uop.is_unique invalidate fast_wakeup_1.bits.fflags.bits.uop.is_sys_pc2epc invalidate fast_wakeup_1.bits.fflags.bits.uop.uses_stq invalidate fast_wakeup_1.bits.fflags.bits.uop.uses_ldq invalidate fast_wakeup_1.bits.fflags.bits.uop.is_amo invalidate fast_wakeup_1.bits.fflags.bits.uop.is_fencei invalidate fast_wakeup_1.bits.fflags.bits.uop.is_fence invalidate fast_wakeup_1.bits.fflags.bits.uop.mem_signed invalidate fast_wakeup_1.bits.fflags.bits.uop.mem_size invalidate fast_wakeup_1.bits.fflags.bits.uop.mem_cmd invalidate fast_wakeup_1.bits.fflags.bits.uop.bypassable invalidate fast_wakeup_1.bits.fflags.bits.uop.exc_cause invalidate fast_wakeup_1.bits.fflags.bits.uop.exception invalidate fast_wakeup_1.bits.fflags.bits.uop.stale_pdst invalidate fast_wakeup_1.bits.fflags.bits.uop.ppred_busy invalidate fast_wakeup_1.bits.fflags.bits.uop.prs3_busy invalidate fast_wakeup_1.bits.fflags.bits.uop.prs2_busy invalidate fast_wakeup_1.bits.fflags.bits.uop.prs1_busy invalidate fast_wakeup_1.bits.fflags.bits.uop.ppred invalidate fast_wakeup_1.bits.fflags.bits.uop.prs3 invalidate fast_wakeup_1.bits.fflags.bits.uop.prs2 invalidate fast_wakeup_1.bits.fflags.bits.uop.prs1 invalidate fast_wakeup_1.bits.fflags.bits.uop.pdst invalidate fast_wakeup_1.bits.fflags.bits.uop.rxq_idx invalidate fast_wakeup_1.bits.fflags.bits.uop.stq_idx invalidate fast_wakeup_1.bits.fflags.bits.uop.ldq_idx invalidate fast_wakeup_1.bits.fflags.bits.uop.rob_idx invalidate fast_wakeup_1.bits.fflags.bits.uop.csr_addr invalidate fast_wakeup_1.bits.fflags.bits.uop.imm_packed invalidate fast_wakeup_1.bits.fflags.bits.uop.taken invalidate fast_wakeup_1.bits.fflags.bits.uop.pc_lob invalidate fast_wakeup_1.bits.fflags.bits.uop.edge_inst invalidate fast_wakeup_1.bits.fflags.bits.uop.ftq_idx invalidate fast_wakeup_1.bits.fflags.bits.uop.br_tag invalidate fast_wakeup_1.bits.fflags.bits.uop.br_mask invalidate fast_wakeup_1.bits.fflags.bits.uop.is_sfb invalidate fast_wakeup_1.bits.fflags.bits.uop.is_jal invalidate fast_wakeup_1.bits.fflags.bits.uop.is_jalr invalidate fast_wakeup_1.bits.fflags.bits.uop.is_br invalidate fast_wakeup_1.bits.fflags.bits.uop.iw_p2_poisoned invalidate fast_wakeup_1.bits.fflags.bits.uop.iw_p1_poisoned invalidate fast_wakeup_1.bits.fflags.bits.uop.iw_state invalidate fast_wakeup_1.bits.fflags.bits.uop.ctrl.is_std invalidate fast_wakeup_1.bits.fflags.bits.uop.ctrl.is_sta invalidate fast_wakeup_1.bits.fflags.bits.uop.ctrl.is_load invalidate fast_wakeup_1.bits.fflags.bits.uop.ctrl.csr_cmd invalidate fast_wakeup_1.bits.fflags.bits.uop.ctrl.fcn_dw invalidate fast_wakeup_1.bits.fflags.bits.uop.ctrl.op_fcn invalidate fast_wakeup_1.bits.fflags.bits.uop.ctrl.imm_sel invalidate fast_wakeup_1.bits.fflags.bits.uop.ctrl.op2_sel invalidate fast_wakeup_1.bits.fflags.bits.uop.ctrl.op1_sel invalidate fast_wakeup_1.bits.fflags.bits.uop.ctrl.br_type invalidate fast_wakeup_1.bits.fflags.bits.uop.fu_code invalidate fast_wakeup_1.bits.fflags.bits.uop.iq_type invalidate fast_wakeup_1.bits.fflags.bits.uop.debug_pc invalidate fast_wakeup_1.bits.fflags.bits.uop.is_rvc invalidate fast_wakeup_1.bits.fflags.bits.uop.debug_inst invalidate fast_wakeup_1.bits.fflags.bits.uop.inst invalidate fast_wakeup_1.bits.fflags.bits.uop.uopc invalidate fast_wakeup_1.bits.fflags.valid invalidate fast_wakeup_1.bits.predicated invalidate fast_wakeup_1.bits.data invalidate fast_wakeup_1.bits.uop.debug_tsrc invalidate fast_wakeup_1.bits.uop.debug_fsrc invalidate fast_wakeup_1.bits.uop.bp_xcpt_if invalidate fast_wakeup_1.bits.uop.bp_debug_if invalidate fast_wakeup_1.bits.uop.xcpt_ma_if invalidate fast_wakeup_1.bits.uop.xcpt_ae_if invalidate fast_wakeup_1.bits.uop.xcpt_pf_if invalidate fast_wakeup_1.bits.uop.fp_single invalidate fast_wakeup_1.bits.uop.fp_val invalidate fast_wakeup_1.bits.uop.frs3_en invalidate fast_wakeup_1.bits.uop.lrs2_rtype invalidate fast_wakeup_1.bits.uop.lrs1_rtype invalidate fast_wakeup_1.bits.uop.dst_rtype invalidate fast_wakeup_1.bits.uop.ldst_val invalidate fast_wakeup_1.bits.uop.lrs3 invalidate fast_wakeup_1.bits.uop.lrs2 invalidate fast_wakeup_1.bits.uop.lrs1 invalidate fast_wakeup_1.bits.uop.ldst invalidate fast_wakeup_1.bits.uop.ldst_is_rs1 invalidate fast_wakeup_1.bits.uop.flush_on_commit invalidate fast_wakeup_1.bits.uop.is_unique invalidate fast_wakeup_1.bits.uop.is_sys_pc2epc invalidate fast_wakeup_1.bits.uop.uses_stq invalidate fast_wakeup_1.bits.uop.uses_ldq invalidate fast_wakeup_1.bits.uop.is_amo invalidate fast_wakeup_1.bits.uop.is_fencei invalidate fast_wakeup_1.bits.uop.is_fence invalidate fast_wakeup_1.bits.uop.mem_signed invalidate fast_wakeup_1.bits.uop.mem_size invalidate fast_wakeup_1.bits.uop.mem_cmd invalidate fast_wakeup_1.bits.uop.bypassable invalidate fast_wakeup_1.bits.uop.exc_cause invalidate fast_wakeup_1.bits.uop.exception invalidate fast_wakeup_1.bits.uop.stale_pdst invalidate fast_wakeup_1.bits.uop.ppred_busy invalidate fast_wakeup_1.bits.uop.prs3_busy invalidate fast_wakeup_1.bits.uop.prs2_busy invalidate fast_wakeup_1.bits.uop.prs1_busy invalidate fast_wakeup_1.bits.uop.ppred invalidate fast_wakeup_1.bits.uop.prs3 invalidate fast_wakeup_1.bits.uop.prs2 invalidate fast_wakeup_1.bits.uop.prs1 invalidate fast_wakeup_1.bits.uop.pdst invalidate fast_wakeup_1.bits.uop.rxq_idx invalidate fast_wakeup_1.bits.uop.stq_idx invalidate fast_wakeup_1.bits.uop.ldq_idx invalidate fast_wakeup_1.bits.uop.rob_idx invalidate fast_wakeup_1.bits.uop.csr_addr invalidate fast_wakeup_1.bits.uop.imm_packed invalidate fast_wakeup_1.bits.uop.taken invalidate fast_wakeup_1.bits.uop.pc_lob invalidate fast_wakeup_1.bits.uop.edge_inst invalidate fast_wakeup_1.bits.uop.ftq_idx invalidate fast_wakeup_1.bits.uop.br_tag invalidate fast_wakeup_1.bits.uop.br_mask invalidate fast_wakeup_1.bits.uop.is_sfb invalidate fast_wakeup_1.bits.uop.is_jal invalidate fast_wakeup_1.bits.uop.is_jalr invalidate fast_wakeup_1.bits.uop.is_br invalidate fast_wakeup_1.bits.uop.iw_p2_poisoned invalidate fast_wakeup_1.bits.uop.iw_p1_poisoned invalidate fast_wakeup_1.bits.uop.iw_state invalidate fast_wakeup_1.bits.uop.ctrl.is_std invalidate fast_wakeup_1.bits.uop.ctrl.is_sta invalidate fast_wakeup_1.bits.uop.ctrl.is_load invalidate fast_wakeup_1.bits.uop.ctrl.csr_cmd invalidate fast_wakeup_1.bits.uop.ctrl.fcn_dw invalidate fast_wakeup_1.bits.uop.ctrl.op_fcn invalidate fast_wakeup_1.bits.uop.ctrl.imm_sel invalidate fast_wakeup_1.bits.uop.ctrl.op2_sel invalidate fast_wakeup_1.bits.uop.ctrl.op1_sel invalidate fast_wakeup_1.bits.uop.ctrl.br_type invalidate fast_wakeup_1.bits.uop.fu_code invalidate fast_wakeup_1.bits.uop.iq_type invalidate fast_wakeup_1.bits.uop.debug_pc invalidate fast_wakeup_1.bits.uop.is_rvc invalidate fast_wakeup_1.bits.uop.debug_inst invalidate fast_wakeup_1.bits.uop.inst invalidate fast_wakeup_1.bits.uop.uopc invalidate fast_wakeup_1.valid invalidate slow_wakeup_1.bits.fflags.bits.flags invalidate slow_wakeup_1.bits.fflags.bits.uop.debug_tsrc invalidate slow_wakeup_1.bits.fflags.bits.uop.debug_fsrc invalidate slow_wakeup_1.bits.fflags.bits.uop.bp_xcpt_if invalidate slow_wakeup_1.bits.fflags.bits.uop.bp_debug_if invalidate slow_wakeup_1.bits.fflags.bits.uop.xcpt_ma_if invalidate slow_wakeup_1.bits.fflags.bits.uop.xcpt_ae_if invalidate slow_wakeup_1.bits.fflags.bits.uop.xcpt_pf_if invalidate slow_wakeup_1.bits.fflags.bits.uop.fp_single invalidate slow_wakeup_1.bits.fflags.bits.uop.fp_val invalidate slow_wakeup_1.bits.fflags.bits.uop.frs3_en invalidate slow_wakeup_1.bits.fflags.bits.uop.lrs2_rtype invalidate slow_wakeup_1.bits.fflags.bits.uop.lrs1_rtype invalidate slow_wakeup_1.bits.fflags.bits.uop.dst_rtype invalidate slow_wakeup_1.bits.fflags.bits.uop.ldst_val invalidate slow_wakeup_1.bits.fflags.bits.uop.lrs3 invalidate slow_wakeup_1.bits.fflags.bits.uop.lrs2 invalidate slow_wakeup_1.bits.fflags.bits.uop.lrs1 invalidate slow_wakeup_1.bits.fflags.bits.uop.ldst invalidate slow_wakeup_1.bits.fflags.bits.uop.ldst_is_rs1 invalidate slow_wakeup_1.bits.fflags.bits.uop.flush_on_commit invalidate slow_wakeup_1.bits.fflags.bits.uop.is_unique invalidate slow_wakeup_1.bits.fflags.bits.uop.is_sys_pc2epc invalidate slow_wakeup_1.bits.fflags.bits.uop.uses_stq invalidate slow_wakeup_1.bits.fflags.bits.uop.uses_ldq invalidate slow_wakeup_1.bits.fflags.bits.uop.is_amo invalidate slow_wakeup_1.bits.fflags.bits.uop.is_fencei invalidate slow_wakeup_1.bits.fflags.bits.uop.is_fence invalidate slow_wakeup_1.bits.fflags.bits.uop.mem_signed invalidate slow_wakeup_1.bits.fflags.bits.uop.mem_size invalidate slow_wakeup_1.bits.fflags.bits.uop.mem_cmd invalidate slow_wakeup_1.bits.fflags.bits.uop.bypassable invalidate slow_wakeup_1.bits.fflags.bits.uop.exc_cause invalidate slow_wakeup_1.bits.fflags.bits.uop.exception invalidate slow_wakeup_1.bits.fflags.bits.uop.stale_pdst invalidate slow_wakeup_1.bits.fflags.bits.uop.ppred_busy invalidate slow_wakeup_1.bits.fflags.bits.uop.prs3_busy invalidate slow_wakeup_1.bits.fflags.bits.uop.prs2_busy invalidate slow_wakeup_1.bits.fflags.bits.uop.prs1_busy invalidate slow_wakeup_1.bits.fflags.bits.uop.ppred invalidate slow_wakeup_1.bits.fflags.bits.uop.prs3 invalidate slow_wakeup_1.bits.fflags.bits.uop.prs2 invalidate slow_wakeup_1.bits.fflags.bits.uop.prs1 invalidate slow_wakeup_1.bits.fflags.bits.uop.pdst invalidate slow_wakeup_1.bits.fflags.bits.uop.rxq_idx invalidate slow_wakeup_1.bits.fflags.bits.uop.stq_idx invalidate slow_wakeup_1.bits.fflags.bits.uop.ldq_idx invalidate slow_wakeup_1.bits.fflags.bits.uop.rob_idx invalidate slow_wakeup_1.bits.fflags.bits.uop.csr_addr invalidate slow_wakeup_1.bits.fflags.bits.uop.imm_packed invalidate slow_wakeup_1.bits.fflags.bits.uop.taken invalidate slow_wakeup_1.bits.fflags.bits.uop.pc_lob invalidate slow_wakeup_1.bits.fflags.bits.uop.edge_inst invalidate slow_wakeup_1.bits.fflags.bits.uop.ftq_idx invalidate slow_wakeup_1.bits.fflags.bits.uop.br_tag invalidate slow_wakeup_1.bits.fflags.bits.uop.br_mask invalidate slow_wakeup_1.bits.fflags.bits.uop.is_sfb invalidate slow_wakeup_1.bits.fflags.bits.uop.is_jal invalidate slow_wakeup_1.bits.fflags.bits.uop.is_jalr invalidate slow_wakeup_1.bits.fflags.bits.uop.is_br invalidate slow_wakeup_1.bits.fflags.bits.uop.iw_p2_poisoned invalidate slow_wakeup_1.bits.fflags.bits.uop.iw_p1_poisoned invalidate slow_wakeup_1.bits.fflags.bits.uop.iw_state invalidate slow_wakeup_1.bits.fflags.bits.uop.ctrl.is_std invalidate slow_wakeup_1.bits.fflags.bits.uop.ctrl.is_sta invalidate slow_wakeup_1.bits.fflags.bits.uop.ctrl.is_load invalidate slow_wakeup_1.bits.fflags.bits.uop.ctrl.csr_cmd invalidate slow_wakeup_1.bits.fflags.bits.uop.ctrl.fcn_dw invalidate slow_wakeup_1.bits.fflags.bits.uop.ctrl.op_fcn invalidate slow_wakeup_1.bits.fflags.bits.uop.ctrl.imm_sel invalidate slow_wakeup_1.bits.fflags.bits.uop.ctrl.op2_sel invalidate slow_wakeup_1.bits.fflags.bits.uop.ctrl.op1_sel invalidate slow_wakeup_1.bits.fflags.bits.uop.ctrl.br_type invalidate slow_wakeup_1.bits.fflags.bits.uop.fu_code invalidate slow_wakeup_1.bits.fflags.bits.uop.iq_type invalidate slow_wakeup_1.bits.fflags.bits.uop.debug_pc invalidate slow_wakeup_1.bits.fflags.bits.uop.is_rvc invalidate slow_wakeup_1.bits.fflags.bits.uop.debug_inst invalidate slow_wakeup_1.bits.fflags.bits.uop.inst invalidate slow_wakeup_1.bits.fflags.bits.uop.uopc invalidate slow_wakeup_1.bits.fflags.valid invalidate slow_wakeup_1.bits.predicated invalidate slow_wakeup_1.bits.data invalidate slow_wakeup_1.bits.uop.debug_tsrc invalidate slow_wakeup_1.bits.uop.debug_fsrc invalidate slow_wakeup_1.bits.uop.bp_xcpt_if invalidate slow_wakeup_1.bits.uop.bp_debug_if invalidate slow_wakeup_1.bits.uop.xcpt_ma_if invalidate slow_wakeup_1.bits.uop.xcpt_ae_if invalidate slow_wakeup_1.bits.uop.xcpt_pf_if invalidate slow_wakeup_1.bits.uop.fp_single invalidate slow_wakeup_1.bits.uop.fp_val invalidate slow_wakeup_1.bits.uop.frs3_en invalidate slow_wakeup_1.bits.uop.lrs2_rtype invalidate slow_wakeup_1.bits.uop.lrs1_rtype invalidate slow_wakeup_1.bits.uop.dst_rtype invalidate slow_wakeup_1.bits.uop.ldst_val invalidate slow_wakeup_1.bits.uop.lrs3 invalidate slow_wakeup_1.bits.uop.lrs2 invalidate slow_wakeup_1.bits.uop.lrs1 invalidate slow_wakeup_1.bits.uop.ldst invalidate slow_wakeup_1.bits.uop.ldst_is_rs1 invalidate slow_wakeup_1.bits.uop.flush_on_commit invalidate slow_wakeup_1.bits.uop.is_unique invalidate slow_wakeup_1.bits.uop.is_sys_pc2epc invalidate slow_wakeup_1.bits.uop.uses_stq invalidate slow_wakeup_1.bits.uop.uses_ldq invalidate slow_wakeup_1.bits.uop.is_amo invalidate slow_wakeup_1.bits.uop.is_fencei invalidate slow_wakeup_1.bits.uop.is_fence invalidate slow_wakeup_1.bits.uop.mem_signed invalidate slow_wakeup_1.bits.uop.mem_size invalidate slow_wakeup_1.bits.uop.mem_cmd invalidate slow_wakeup_1.bits.uop.bypassable invalidate slow_wakeup_1.bits.uop.exc_cause invalidate slow_wakeup_1.bits.uop.exception invalidate slow_wakeup_1.bits.uop.stale_pdst invalidate slow_wakeup_1.bits.uop.ppred_busy invalidate slow_wakeup_1.bits.uop.prs3_busy invalidate slow_wakeup_1.bits.uop.prs2_busy invalidate slow_wakeup_1.bits.uop.prs1_busy invalidate slow_wakeup_1.bits.uop.ppred invalidate slow_wakeup_1.bits.uop.prs3 invalidate slow_wakeup_1.bits.uop.prs2 invalidate slow_wakeup_1.bits.uop.prs1 invalidate slow_wakeup_1.bits.uop.pdst invalidate slow_wakeup_1.bits.uop.rxq_idx invalidate slow_wakeup_1.bits.uop.stq_idx invalidate slow_wakeup_1.bits.uop.ldq_idx invalidate slow_wakeup_1.bits.uop.rob_idx invalidate slow_wakeup_1.bits.uop.csr_addr invalidate slow_wakeup_1.bits.uop.imm_packed invalidate slow_wakeup_1.bits.uop.taken invalidate slow_wakeup_1.bits.uop.pc_lob invalidate slow_wakeup_1.bits.uop.edge_inst invalidate slow_wakeup_1.bits.uop.ftq_idx invalidate slow_wakeup_1.bits.uop.br_tag invalidate slow_wakeup_1.bits.uop.br_mask invalidate slow_wakeup_1.bits.uop.is_sfb invalidate slow_wakeup_1.bits.uop.is_jal invalidate slow_wakeup_1.bits.uop.is_jalr invalidate slow_wakeup_1.bits.uop.is_br invalidate slow_wakeup_1.bits.uop.iw_p2_poisoned invalidate slow_wakeup_1.bits.uop.iw_p1_poisoned invalidate slow_wakeup_1.bits.uop.iw_state invalidate slow_wakeup_1.bits.uop.ctrl.is_std invalidate slow_wakeup_1.bits.uop.ctrl.is_sta invalidate slow_wakeup_1.bits.uop.ctrl.is_load invalidate slow_wakeup_1.bits.uop.ctrl.csr_cmd invalidate slow_wakeup_1.bits.uop.ctrl.fcn_dw invalidate slow_wakeup_1.bits.uop.ctrl.op_fcn invalidate slow_wakeup_1.bits.uop.ctrl.imm_sel invalidate slow_wakeup_1.bits.uop.ctrl.op2_sel invalidate slow_wakeup_1.bits.uop.ctrl.op1_sel invalidate slow_wakeup_1.bits.uop.ctrl.br_type invalidate slow_wakeup_1.bits.uop.fu_code invalidate slow_wakeup_1.bits.uop.iq_type invalidate slow_wakeup_1.bits.uop.debug_pc invalidate slow_wakeup_1.bits.uop.is_rvc invalidate slow_wakeup_1.bits.uop.debug_inst invalidate slow_wakeup_1.bits.uop.inst invalidate slow_wakeup_1.bits.uop.uopc invalidate slow_wakeup_1.valid node _T_57 = neq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _T_58 = and(alu_exe_unit_1.io.iresp.valid, _T_57) node _T_59 = neq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(_T_60, UInt<1>(0h0)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed\n at core.scala:820 assert(!(resp.valid && resp.bits.uop.rf_wen && resp.bits.uop.dst_rtype =/= RT_FIX))\n") : printf_3 assert(clock, _T_61, UInt<1>(0h1), "") : assert_3 connect fast_wakeup_1.bits.uop, iss_uops[2] node _fast_wakeup_valid_T_8 = and(iss_valids[2], iss_uops[2].bypassable) node _fast_wakeup_valid_T_9 = eq(iss_uops[2].dst_rtype, UInt<2>(0h0)) node _fast_wakeup_valid_T_10 = and(_fast_wakeup_valid_T_8, _fast_wakeup_valid_T_9) node _fast_wakeup_valid_T_11 = and(_fast_wakeup_valid_T_10, iss_uops[2].ldst_val) node _fast_wakeup_valid_T_12 = or(iss_uops[2].iw_p1_poisoned, iss_uops[2].iw_p2_poisoned) node _fast_wakeup_valid_T_13 = and(io.lsu.ld_miss, _fast_wakeup_valid_T_12) node _fast_wakeup_valid_T_14 = eq(_fast_wakeup_valid_T_13, UInt<1>(0h0)) node _fast_wakeup_valid_T_15 = and(_fast_wakeup_valid_T_11, _fast_wakeup_valid_T_14) connect fast_wakeup_1.valid, _fast_wakeup_valid_T_15 connect slow_wakeup_1.bits.uop, alu_exe_unit_1.io.iresp.bits.uop node _slow_wakeup_valid_T_6 = neq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _slow_wakeup_valid_T_7 = and(alu_exe_unit_1.io.iresp.valid, _slow_wakeup_valid_T_6) node _slow_wakeup_valid_T_8 = eq(alu_exe_unit_1.io.iresp.bits.uop.bypassable, UInt<1>(0h0)) node _slow_wakeup_valid_T_9 = and(_slow_wakeup_valid_T_7, _slow_wakeup_valid_T_8) node _slow_wakeup_valid_T_10 = eq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _slow_wakeup_valid_T_11 = and(_slow_wakeup_valid_T_9, _slow_wakeup_valid_T_10) connect slow_wakeup_1.valid, _slow_wakeup_valid_T_11 connect int_iss_wakeups[3], fast_wakeup_1 connect int_iss_wakeups[4], slow_wakeup_1 connect int_ren_wakeups[3], fast_wakeup_1 connect int_ren_wakeups[4], slow_wakeup_1 wire fast_wakeup_2 : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}} wire slow_wakeup_2 : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}} invalidate fast_wakeup_2.bits.fflags.bits.flags invalidate fast_wakeup_2.bits.fflags.bits.uop.debug_tsrc invalidate fast_wakeup_2.bits.fflags.bits.uop.debug_fsrc invalidate fast_wakeup_2.bits.fflags.bits.uop.bp_xcpt_if invalidate fast_wakeup_2.bits.fflags.bits.uop.bp_debug_if invalidate fast_wakeup_2.bits.fflags.bits.uop.xcpt_ma_if invalidate fast_wakeup_2.bits.fflags.bits.uop.xcpt_ae_if invalidate fast_wakeup_2.bits.fflags.bits.uop.xcpt_pf_if invalidate fast_wakeup_2.bits.fflags.bits.uop.fp_single invalidate fast_wakeup_2.bits.fflags.bits.uop.fp_val invalidate fast_wakeup_2.bits.fflags.bits.uop.frs3_en invalidate fast_wakeup_2.bits.fflags.bits.uop.lrs2_rtype invalidate fast_wakeup_2.bits.fflags.bits.uop.lrs1_rtype invalidate fast_wakeup_2.bits.fflags.bits.uop.dst_rtype invalidate fast_wakeup_2.bits.fflags.bits.uop.ldst_val invalidate fast_wakeup_2.bits.fflags.bits.uop.lrs3 invalidate fast_wakeup_2.bits.fflags.bits.uop.lrs2 invalidate fast_wakeup_2.bits.fflags.bits.uop.lrs1 invalidate fast_wakeup_2.bits.fflags.bits.uop.ldst invalidate fast_wakeup_2.bits.fflags.bits.uop.ldst_is_rs1 invalidate fast_wakeup_2.bits.fflags.bits.uop.flush_on_commit invalidate fast_wakeup_2.bits.fflags.bits.uop.is_unique invalidate fast_wakeup_2.bits.fflags.bits.uop.is_sys_pc2epc invalidate fast_wakeup_2.bits.fflags.bits.uop.uses_stq invalidate fast_wakeup_2.bits.fflags.bits.uop.uses_ldq invalidate fast_wakeup_2.bits.fflags.bits.uop.is_amo invalidate fast_wakeup_2.bits.fflags.bits.uop.is_fencei invalidate fast_wakeup_2.bits.fflags.bits.uop.is_fence invalidate fast_wakeup_2.bits.fflags.bits.uop.mem_signed invalidate fast_wakeup_2.bits.fflags.bits.uop.mem_size invalidate fast_wakeup_2.bits.fflags.bits.uop.mem_cmd invalidate fast_wakeup_2.bits.fflags.bits.uop.bypassable invalidate fast_wakeup_2.bits.fflags.bits.uop.exc_cause invalidate fast_wakeup_2.bits.fflags.bits.uop.exception invalidate fast_wakeup_2.bits.fflags.bits.uop.stale_pdst invalidate fast_wakeup_2.bits.fflags.bits.uop.ppred_busy invalidate fast_wakeup_2.bits.fflags.bits.uop.prs3_busy invalidate fast_wakeup_2.bits.fflags.bits.uop.prs2_busy invalidate fast_wakeup_2.bits.fflags.bits.uop.prs1_busy invalidate fast_wakeup_2.bits.fflags.bits.uop.ppred invalidate fast_wakeup_2.bits.fflags.bits.uop.prs3 invalidate fast_wakeup_2.bits.fflags.bits.uop.prs2 invalidate fast_wakeup_2.bits.fflags.bits.uop.prs1 invalidate fast_wakeup_2.bits.fflags.bits.uop.pdst invalidate fast_wakeup_2.bits.fflags.bits.uop.rxq_idx invalidate fast_wakeup_2.bits.fflags.bits.uop.stq_idx invalidate fast_wakeup_2.bits.fflags.bits.uop.ldq_idx invalidate fast_wakeup_2.bits.fflags.bits.uop.rob_idx invalidate fast_wakeup_2.bits.fflags.bits.uop.csr_addr invalidate fast_wakeup_2.bits.fflags.bits.uop.imm_packed invalidate fast_wakeup_2.bits.fflags.bits.uop.taken invalidate fast_wakeup_2.bits.fflags.bits.uop.pc_lob invalidate fast_wakeup_2.bits.fflags.bits.uop.edge_inst invalidate fast_wakeup_2.bits.fflags.bits.uop.ftq_idx invalidate fast_wakeup_2.bits.fflags.bits.uop.br_tag invalidate fast_wakeup_2.bits.fflags.bits.uop.br_mask invalidate fast_wakeup_2.bits.fflags.bits.uop.is_sfb invalidate fast_wakeup_2.bits.fflags.bits.uop.is_jal invalidate fast_wakeup_2.bits.fflags.bits.uop.is_jalr invalidate fast_wakeup_2.bits.fflags.bits.uop.is_br invalidate fast_wakeup_2.bits.fflags.bits.uop.iw_p2_poisoned invalidate fast_wakeup_2.bits.fflags.bits.uop.iw_p1_poisoned invalidate fast_wakeup_2.bits.fflags.bits.uop.iw_state invalidate fast_wakeup_2.bits.fflags.bits.uop.ctrl.is_std invalidate fast_wakeup_2.bits.fflags.bits.uop.ctrl.is_sta invalidate fast_wakeup_2.bits.fflags.bits.uop.ctrl.is_load invalidate fast_wakeup_2.bits.fflags.bits.uop.ctrl.csr_cmd invalidate fast_wakeup_2.bits.fflags.bits.uop.ctrl.fcn_dw invalidate fast_wakeup_2.bits.fflags.bits.uop.ctrl.op_fcn invalidate fast_wakeup_2.bits.fflags.bits.uop.ctrl.imm_sel invalidate fast_wakeup_2.bits.fflags.bits.uop.ctrl.op2_sel invalidate fast_wakeup_2.bits.fflags.bits.uop.ctrl.op1_sel invalidate fast_wakeup_2.bits.fflags.bits.uop.ctrl.br_type invalidate fast_wakeup_2.bits.fflags.bits.uop.fu_code invalidate fast_wakeup_2.bits.fflags.bits.uop.iq_type invalidate fast_wakeup_2.bits.fflags.bits.uop.debug_pc invalidate fast_wakeup_2.bits.fflags.bits.uop.is_rvc invalidate fast_wakeup_2.bits.fflags.bits.uop.debug_inst invalidate fast_wakeup_2.bits.fflags.bits.uop.inst invalidate fast_wakeup_2.bits.fflags.bits.uop.uopc invalidate fast_wakeup_2.bits.fflags.valid invalidate fast_wakeup_2.bits.predicated invalidate fast_wakeup_2.bits.data invalidate fast_wakeup_2.bits.uop.debug_tsrc invalidate fast_wakeup_2.bits.uop.debug_fsrc invalidate fast_wakeup_2.bits.uop.bp_xcpt_if invalidate fast_wakeup_2.bits.uop.bp_debug_if invalidate fast_wakeup_2.bits.uop.xcpt_ma_if invalidate fast_wakeup_2.bits.uop.xcpt_ae_if invalidate fast_wakeup_2.bits.uop.xcpt_pf_if invalidate fast_wakeup_2.bits.uop.fp_single invalidate fast_wakeup_2.bits.uop.fp_val invalidate fast_wakeup_2.bits.uop.frs3_en invalidate fast_wakeup_2.bits.uop.lrs2_rtype invalidate fast_wakeup_2.bits.uop.lrs1_rtype invalidate fast_wakeup_2.bits.uop.dst_rtype invalidate fast_wakeup_2.bits.uop.ldst_val invalidate fast_wakeup_2.bits.uop.lrs3 invalidate fast_wakeup_2.bits.uop.lrs2 invalidate fast_wakeup_2.bits.uop.lrs1 invalidate fast_wakeup_2.bits.uop.ldst invalidate fast_wakeup_2.bits.uop.ldst_is_rs1 invalidate fast_wakeup_2.bits.uop.flush_on_commit invalidate fast_wakeup_2.bits.uop.is_unique invalidate fast_wakeup_2.bits.uop.is_sys_pc2epc invalidate fast_wakeup_2.bits.uop.uses_stq invalidate fast_wakeup_2.bits.uop.uses_ldq invalidate fast_wakeup_2.bits.uop.is_amo invalidate fast_wakeup_2.bits.uop.is_fencei invalidate fast_wakeup_2.bits.uop.is_fence invalidate fast_wakeup_2.bits.uop.mem_signed invalidate fast_wakeup_2.bits.uop.mem_size invalidate fast_wakeup_2.bits.uop.mem_cmd invalidate fast_wakeup_2.bits.uop.bypassable invalidate fast_wakeup_2.bits.uop.exc_cause invalidate fast_wakeup_2.bits.uop.exception invalidate fast_wakeup_2.bits.uop.stale_pdst invalidate fast_wakeup_2.bits.uop.ppred_busy invalidate fast_wakeup_2.bits.uop.prs3_busy invalidate fast_wakeup_2.bits.uop.prs2_busy invalidate fast_wakeup_2.bits.uop.prs1_busy invalidate fast_wakeup_2.bits.uop.ppred invalidate fast_wakeup_2.bits.uop.prs3 invalidate fast_wakeup_2.bits.uop.prs2 invalidate fast_wakeup_2.bits.uop.prs1 invalidate fast_wakeup_2.bits.uop.pdst invalidate fast_wakeup_2.bits.uop.rxq_idx invalidate fast_wakeup_2.bits.uop.stq_idx invalidate fast_wakeup_2.bits.uop.ldq_idx invalidate fast_wakeup_2.bits.uop.rob_idx invalidate fast_wakeup_2.bits.uop.csr_addr invalidate fast_wakeup_2.bits.uop.imm_packed invalidate fast_wakeup_2.bits.uop.taken invalidate fast_wakeup_2.bits.uop.pc_lob invalidate fast_wakeup_2.bits.uop.edge_inst invalidate fast_wakeup_2.bits.uop.ftq_idx invalidate fast_wakeup_2.bits.uop.br_tag invalidate fast_wakeup_2.bits.uop.br_mask invalidate fast_wakeup_2.bits.uop.is_sfb invalidate fast_wakeup_2.bits.uop.is_jal invalidate fast_wakeup_2.bits.uop.is_jalr invalidate fast_wakeup_2.bits.uop.is_br invalidate fast_wakeup_2.bits.uop.iw_p2_poisoned invalidate fast_wakeup_2.bits.uop.iw_p1_poisoned invalidate fast_wakeup_2.bits.uop.iw_state invalidate fast_wakeup_2.bits.uop.ctrl.is_std invalidate fast_wakeup_2.bits.uop.ctrl.is_sta invalidate fast_wakeup_2.bits.uop.ctrl.is_load invalidate fast_wakeup_2.bits.uop.ctrl.csr_cmd invalidate fast_wakeup_2.bits.uop.ctrl.fcn_dw invalidate fast_wakeup_2.bits.uop.ctrl.op_fcn invalidate fast_wakeup_2.bits.uop.ctrl.imm_sel invalidate fast_wakeup_2.bits.uop.ctrl.op2_sel invalidate fast_wakeup_2.bits.uop.ctrl.op1_sel invalidate fast_wakeup_2.bits.uop.ctrl.br_type invalidate fast_wakeup_2.bits.uop.fu_code invalidate fast_wakeup_2.bits.uop.iq_type invalidate fast_wakeup_2.bits.uop.debug_pc invalidate fast_wakeup_2.bits.uop.is_rvc invalidate fast_wakeup_2.bits.uop.debug_inst invalidate fast_wakeup_2.bits.uop.inst invalidate fast_wakeup_2.bits.uop.uopc invalidate fast_wakeup_2.valid invalidate slow_wakeup_2.bits.fflags.bits.flags invalidate slow_wakeup_2.bits.fflags.bits.uop.debug_tsrc invalidate slow_wakeup_2.bits.fflags.bits.uop.debug_fsrc invalidate slow_wakeup_2.bits.fflags.bits.uop.bp_xcpt_if invalidate slow_wakeup_2.bits.fflags.bits.uop.bp_debug_if invalidate slow_wakeup_2.bits.fflags.bits.uop.xcpt_ma_if invalidate slow_wakeup_2.bits.fflags.bits.uop.xcpt_ae_if invalidate slow_wakeup_2.bits.fflags.bits.uop.xcpt_pf_if invalidate slow_wakeup_2.bits.fflags.bits.uop.fp_single invalidate slow_wakeup_2.bits.fflags.bits.uop.fp_val invalidate slow_wakeup_2.bits.fflags.bits.uop.frs3_en invalidate slow_wakeup_2.bits.fflags.bits.uop.lrs2_rtype invalidate slow_wakeup_2.bits.fflags.bits.uop.lrs1_rtype invalidate slow_wakeup_2.bits.fflags.bits.uop.dst_rtype invalidate slow_wakeup_2.bits.fflags.bits.uop.ldst_val invalidate slow_wakeup_2.bits.fflags.bits.uop.lrs3 invalidate slow_wakeup_2.bits.fflags.bits.uop.lrs2 invalidate slow_wakeup_2.bits.fflags.bits.uop.lrs1 invalidate slow_wakeup_2.bits.fflags.bits.uop.ldst invalidate slow_wakeup_2.bits.fflags.bits.uop.ldst_is_rs1 invalidate slow_wakeup_2.bits.fflags.bits.uop.flush_on_commit invalidate slow_wakeup_2.bits.fflags.bits.uop.is_unique invalidate slow_wakeup_2.bits.fflags.bits.uop.is_sys_pc2epc invalidate slow_wakeup_2.bits.fflags.bits.uop.uses_stq invalidate slow_wakeup_2.bits.fflags.bits.uop.uses_ldq invalidate slow_wakeup_2.bits.fflags.bits.uop.is_amo invalidate slow_wakeup_2.bits.fflags.bits.uop.is_fencei invalidate slow_wakeup_2.bits.fflags.bits.uop.is_fence invalidate slow_wakeup_2.bits.fflags.bits.uop.mem_signed invalidate slow_wakeup_2.bits.fflags.bits.uop.mem_size invalidate slow_wakeup_2.bits.fflags.bits.uop.mem_cmd invalidate slow_wakeup_2.bits.fflags.bits.uop.bypassable invalidate slow_wakeup_2.bits.fflags.bits.uop.exc_cause invalidate slow_wakeup_2.bits.fflags.bits.uop.exception invalidate slow_wakeup_2.bits.fflags.bits.uop.stale_pdst invalidate slow_wakeup_2.bits.fflags.bits.uop.ppred_busy invalidate slow_wakeup_2.bits.fflags.bits.uop.prs3_busy invalidate slow_wakeup_2.bits.fflags.bits.uop.prs2_busy invalidate slow_wakeup_2.bits.fflags.bits.uop.prs1_busy invalidate slow_wakeup_2.bits.fflags.bits.uop.ppred invalidate slow_wakeup_2.bits.fflags.bits.uop.prs3 invalidate slow_wakeup_2.bits.fflags.bits.uop.prs2 invalidate slow_wakeup_2.bits.fflags.bits.uop.prs1 invalidate slow_wakeup_2.bits.fflags.bits.uop.pdst invalidate slow_wakeup_2.bits.fflags.bits.uop.rxq_idx invalidate slow_wakeup_2.bits.fflags.bits.uop.stq_idx invalidate slow_wakeup_2.bits.fflags.bits.uop.ldq_idx invalidate slow_wakeup_2.bits.fflags.bits.uop.rob_idx invalidate slow_wakeup_2.bits.fflags.bits.uop.csr_addr invalidate slow_wakeup_2.bits.fflags.bits.uop.imm_packed invalidate slow_wakeup_2.bits.fflags.bits.uop.taken invalidate slow_wakeup_2.bits.fflags.bits.uop.pc_lob invalidate slow_wakeup_2.bits.fflags.bits.uop.edge_inst invalidate slow_wakeup_2.bits.fflags.bits.uop.ftq_idx invalidate slow_wakeup_2.bits.fflags.bits.uop.br_tag invalidate slow_wakeup_2.bits.fflags.bits.uop.br_mask invalidate slow_wakeup_2.bits.fflags.bits.uop.is_sfb invalidate slow_wakeup_2.bits.fflags.bits.uop.is_jal invalidate slow_wakeup_2.bits.fflags.bits.uop.is_jalr invalidate slow_wakeup_2.bits.fflags.bits.uop.is_br invalidate slow_wakeup_2.bits.fflags.bits.uop.iw_p2_poisoned invalidate slow_wakeup_2.bits.fflags.bits.uop.iw_p1_poisoned invalidate slow_wakeup_2.bits.fflags.bits.uop.iw_state invalidate slow_wakeup_2.bits.fflags.bits.uop.ctrl.is_std invalidate slow_wakeup_2.bits.fflags.bits.uop.ctrl.is_sta invalidate slow_wakeup_2.bits.fflags.bits.uop.ctrl.is_load invalidate slow_wakeup_2.bits.fflags.bits.uop.ctrl.csr_cmd invalidate slow_wakeup_2.bits.fflags.bits.uop.ctrl.fcn_dw invalidate slow_wakeup_2.bits.fflags.bits.uop.ctrl.op_fcn invalidate slow_wakeup_2.bits.fflags.bits.uop.ctrl.imm_sel invalidate slow_wakeup_2.bits.fflags.bits.uop.ctrl.op2_sel invalidate slow_wakeup_2.bits.fflags.bits.uop.ctrl.op1_sel invalidate slow_wakeup_2.bits.fflags.bits.uop.ctrl.br_type invalidate slow_wakeup_2.bits.fflags.bits.uop.fu_code invalidate slow_wakeup_2.bits.fflags.bits.uop.iq_type invalidate slow_wakeup_2.bits.fflags.bits.uop.debug_pc invalidate slow_wakeup_2.bits.fflags.bits.uop.is_rvc invalidate slow_wakeup_2.bits.fflags.bits.uop.debug_inst invalidate slow_wakeup_2.bits.fflags.bits.uop.inst invalidate slow_wakeup_2.bits.fflags.bits.uop.uopc invalidate slow_wakeup_2.bits.fflags.valid invalidate slow_wakeup_2.bits.predicated invalidate slow_wakeup_2.bits.data invalidate slow_wakeup_2.bits.uop.debug_tsrc invalidate slow_wakeup_2.bits.uop.debug_fsrc invalidate slow_wakeup_2.bits.uop.bp_xcpt_if invalidate slow_wakeup_2.bits.uop.bp_debug_if invalidate slow_wakeup_2.bits.uop.xcpt_ma_if invalidate slow_wakeup_2.bits.uop.xcpt_ae_if invalidate slow_wakeup_2.bits.uop.xcpt_pf_if invalidate slow_wakeup_2.bits.uop.fp_single invalidate slow_wakeup_2.bits.uop.fp_val invalidate slow_wakeup_2.bits.uop.frs3_en invalidate slow_wakeup_2.bits.uop.lrs2_rtype invalidate slow_wakeup_2.bits.uop.lrs1_rtype invalidate slow_wakeup_2.bits.uop.dst_rtype invalidate slow_wakeup_2.bits.uop.ldst_val invalidate slow_wakeup_2.bits.uop.lrs3 invalidate slow_wakeup_2.bits.uop.lrs2 invalidate slow_wakeup_2.bits.uop.lrs1 invalidate slow_wakeup_2.bits.uop.ldst invalidate slow_wakeup_2.bits.uop.ldst_is_rs1 invalidate slow_wakeup_2.bits.uop.flush_on_commit invalidate slow_wakeup_2.bits.uop.is_unique invalidate slow_wakeup_2.bits.uop.is_sys_pc2epc invalidate slow_wakeup_2.bits.uop.uses_stq invalidate slow_wakeup_2.bits.uop.uses_ldq invalidate slow_wakeup_2.bits.uop.is_amo invalidate slow_wakeup_2.bits.uop.is_fencei invalidate slow_wakeup_2.bits.uop.is_fence invalidate slow_wakeup_2.bits.uop.mem_signed invalidate slow_wakeup_2.bits.uop.mem_size invalidate slow_wakeup_2.bits.uop.mem_cmd invalidate slow_wakeup_2.bits.uop.bypassable invalidate slow_wakeup_2.bits.uop.exc_cause invalidate slow_wakeup_2.bits.uop.exception invalidate slow_wakeup_2.bits.uop.stale_pdst invalidate slow_wakeup_2.bits.uop.ppred_busy invalidate slow_wakeup_2.bits.uop.prs3_busy invalidate slow_wakeup_2.bits.uop.prs2_busy invalidate slow_wakeup_2.bits.uop.prs1_busy invalidate slow_wakeup_2.bits.uop.ppred invalidate slow_wakeup_2.bits.uop.prs3 invalidate slow_wakeup_2.bits.uop.prs2 invalidate slow_wakeup_2.bits.uop.prs1 invalidate slow_wakeup_2.bits.uop.pdst invalidate slow_wakeup_2.bits.uop.rxq_idx invalidate slow_wakeup_2.bits.uop.stq_idx invalidate slow_wakeup_2.bits.uop.ldq_idx invalidate slow_wakeup_2.bits.uop.rob_idx invalidate slow_wakeup_2.bits.uop.csr_addr invalidate slow_wakeup_2.bits.uop.imm_packed invalidate slow_wakeup_2.bits.uop.taken invalidate slow_wakeup_2.bits.uop.pc_lob invalidate slow_wakeup_2.bits.uop.edge_inst invalidate slow_wakeup_2.bits.uop.ftq_idx invalidate slow_wakeup_2.bits.uop.br_tag invalidate slow_wakeup_2.bits.uop.br_mask invalidate slow_wakeup_2.bits.uop.is_sfb invalidate slow_wakeup_2.bits.uop.is_jal invalidate slow_wakeup_2.bits.uop.is_jalr invalidate slow_wakeup_2.bits.uop.is_br invalidate slow_wakeup_2.bits.uop.iw_p2_poisoned invalidate slow_wakeup_2.bits.uop.iw_p1_poisoned invalidate slow_wakeup_2.bits.uop.iw_state invalidate slow_wakeup_2.bits.uop.ctrl.is_std invalidate slow_wakeup_2.bits.uop.ctrl.is_sta invalidate slow_wakeup_2.bits.uop.ctrl.is_load invalidate slow_wakeup_2.bits.uop.ctrl.csr_cmd invalidate slow_wakeup_2.bits.uop.ctrl.fcn_dw invalidate slow_wakeup_2.bits.uop.ctrl.op_fcn invalidate slow_wakeup_2.bits.uop.ctrl.imm_sel invalidate slow_wakeup_2.bits.uop.ctrl.op2_sel invalidate slow_wakeup_2.bits.uop.ctrl.op1_sel invalidate slow_wakeup_2.bits.uop.ctrl.br_type invalidate slow_wakeup_2.bits.uop.fu_code invalidate slow_wakeup_2.bits.uop.iq_type invalidate slow_wakeup_2.bits.uop.debug_pc invalidate slow_wakeup_2.bits.uop.is_rvc invalidate slow_wakeup_2.bits.uop.debug_inst invalidate slow_wakeup_2.bits.uop.inst invalidate slow_wakeup_2.bits.uop.uopc invalidate slow_wakeup_2.valid node _T_65 = neq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _T_66 = and(alu_exe_unit_2.io.iresp.valid, _T_65) node _T_67 = neq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _T_68 = and(_T_66, _T_67) node _T_69 = eq(_T_68, UInt<1>(0h0)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed\n at core.scala:820 assert(!(resp.valid && resp.bits.uop.rf_wen && resp.bits.uop.dst_rtype =/= RT_FIX))\n") : printf_4 assert(clock, _T_69, UInt<1>(0h1), "") : assert_4 connect fast_wakeup_2.bits.uop, iss_uops[3] node _fast_wakeup_valid_T_16 = and(iss_valids[3], iss_uops[3].bypassable) node _fast_wakeup_valid_T_17 = eq(iss_uops[3].dst_rtype, UInt<2>(0h0)) node _fast_wakeup_valid_T_18 = and(_fast_wakeup_valid_T_16, _fast_wakeup_valid_T_17) node _fast_wakeup_valid_T_19 = and(_fast_wakeup_valid_T_18, iss_uops[3].ldst_val) node _fast_wakeup_valid_T_20 = or(iss_uops[3].iw_p1_poisoned, iss_uops[3].iw_p2_poisoned) node _fast_wakeup_valid_T_21 = and(io.lsu.ld_miss, _fast_wakeup_valid_T_20) node _fast_wakeup_valid_T_22 = eq(_fast_wakeup_valid_T_21, UInt<1>(0h0)) node _fast_wakeup_valid_T_23 = and(_fast_wakeup_valid_T_19, _fast_wakeup_valid_T_22) connect fast_wakeup_2.valid, _fast_wakeup_valid_T_23 connect slow_wakeup_2.bits.uop, alu_exe_unit_2.io.iresp.bits.uop node _slow_wakeup_valid_T_12 = neq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _slow_wakeup_valid_T_13 = and(alu_exe_unit_2.io.iresp.valid, _slow_wakeup_valid_T_12) node _slow_wakeup_valid_T_14 = eq(alu_exe_unit_2.io.iresp.bits.uop.bypassable, UInt<1>(0h0)) node _slow_wakeup_valid_T_15 = and(_slow_wakeup_valid_T_13, _slow_wakeup_valid_T_14) node _slow_wakeup_valid_T_16 = eq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _slow_wakeup_valid_T_17 = and(_slow_wakeup_valid_T_15, _slow_wakeup_valid_T_16) connect slow_wakeup_2.valid, _slow_wakeup_valid_T_17 connect int_iss_wakeups[5], fast_wakeup_2 connect int_iss_wakeups[6], slow_wakeup_2 connect int_ren_wakeups[5], fast_wakeup_2 connect int_ren_wakeups[6], slow_wakeup_2 node _pred_wakeup_valid_T = and(iss_uops[1].is_br, iss_uops[1].is_sfb) node _pred_wakeup_valid_T_1 = and(_pred_wakeup_valid_T, UInt<1>(0h0)) node _pred_wakeup_valid_T_2 = and(iss_valids[1], _pred_wakeup_valid_T_1) node _pred_wakeup_valid_T_3 = or(iss_uops[1].iw_p1_poisoned, iss_uops[1].iw_p2_poisoned) node _pred_wakeup_valid_T_4 = and(io.lsu.ld_miss, _pred_wakeup_valid_T_3) node _pred_wakeup_valid_T_5 = eq(_pred_wakeup_valid_T_4, UInt<1>(0h0)) node _pred_wakeup_valid_T_6 = and(_pred_wakeup_valid_T_2, _pred_wakeup_valid_T_5) connect pred_wakeup.valid, _pred_wakeup_valid_T_6 connect pred_wakeup.bits.uop, iss_uops[1] invalidate pred_wakeup.bits.fflags.bits.flags invalidate pred_wakeup.bits.fflags.bits.uop.debug_tsrc invalidate pred_wakeup.bits.fflags.bits.uop.debug_fsrc invalidate pred_wakeup.bits.fflags.bits.uop.bp_xcpt_if invalidate pred_wakeup.bits.fflags.bits.uop.bp_debug_if invalidate pred_wakeup.bits.fflags.bits.uop.xcpt_ma_if invalidate pred_wakeup.bits.fflags.bits.uop.xcpt_ae_if invalidate pred_wakeup.bits.fflags.bits.uop.xcpt_pf_if invalidate pred_wakeup.bits.fflags.bits.uop.fp_single invalidate pred_wakeup.bits.fflags.bits.uop.fp_val invalidate pred_wakeup.bits.fflags.bits.uop.frs3_en invalidate pred_wakeup.bits.fflags.bits.uop.lrs2_rtype invalidate pred_wakeup.bits.fflags.bits.uop.lrs1_rtype invalidate pred_wakeup.bits.fflags.bits.uop.dst_rtype invalidate pred_wakeup.bits.fflags.bits.uop.ldst_val invalidate pred_wakeup.bits.fflags.bits.uop.lrs3 invalidate pred_wakeup.bits.fflags.bits.uop.lrs2 invalidate pred_wakeup.bits.fflags.bits.uop.lrs1 invalidate pred_wakeup.bits.fflags.bits.uop.ldst invalidate pred_wakeup.bits.fflags.bits.uop.ldst_is_rs1 invalidate pred_wakeup.bits.fflags.bits.uop.flush_on_commit invalidate pred_wakeup.bits.fflags.bits.uop.is_unique invalidate pred_wakeup.bits.fflags.bits.uop.is_sys_pc2epc invalidate pred_wakeup.bits.fflags.bits.uop.uses_stq invalidate pred_wakeup.bits.fflags.bits.uop.uses_ldq invalidate pred_wakeup.bits.fflags.bits.uop.is_amo invalidate pred_wakeup.bits.fflags.bits.uop.is_fencei invalidate pred_wakeup.bits.fflags.bits.uop.is_fence invalidate pred_wakeup.bits.fflags.bits.uop.mem_signed invalidate pred_wakeup.bits.fflags.bits.uop.mem_size invalidate pred_wakeup.bits.fflags.bits.uop.mem_cmd invalidate pred_wakeup.bits.fflags.bits.uop.bypassable invalidate pred_wakeup.bits.fflags.bits.uop.exc_cause invalidate pred_wakeup.bits.fflags.bits.uop.exception invalidate pred_wakeup.bits.fflags.bits.uop.stale_pdst invalidate pred_wakeup.bits.fflags.bits.uop.ppred_busy invalidate pred_wakeup.bits.fflags.bits.uop.prs3_busy invalidate pred_wakeup.bits.fflags.bits.uop.prs2_busy invalidate pred_wakeup.bits.fflags.bits.uop.prs1_busy invalidate pred_wakeup.bits.fflags.bits.uop.ppred invalidate pred_wakeup.bits.fflags.bits.uop.prs3 invalidate pred_wakeup.bits.fflags.bits.uop.prs2 invalidate pred_wakeup.bits.fflags.bits.uop.prs1 invalidate pred_wakeup.bits.fflags.bits.uop.pdst invalidate pred_wakeup.bits.fflags.bits.uop.rxq_idx invalidate pred_wakeup.bits.fflags.bits.uop.stq_idx invalidate pred_wakeup.bits.fflags.bits.uop.ldq_idx invalidate pred_wakeup.bits.fflags.bits.uop.rob_idx invalidate pred_wakeup.bits.fflags.bits.uop.csr_addr invalidate pred_wakeup.bits.fflags.bits.uop.imm_packed invalidate pred_wakeup.bits.fflags.bits.uop.taken invalidate pred_wakeup.bits.fflags.bits.uop.pc_lob invalidate pred_wakeup.bits.fflags.bits.uop.edge_inst invalidate pred_wakeup.bits.fflags.bits.uop.ftq_idx invalidate pred_wakeup.bits.fflags.bits.uop.br_tag invalidate pred_wakeup.bits.fflags.bits.uop.br_mask invalidate pred_wakeup.bits.fflags.bits.uop.is_sfb invalidate pred_wakeup.bits.fflags.bits.uop.is_jal invalidate pred_wakeup.bits.fflags.bits.uop.is_jalr invalidate pred_wakeup.bits.fflags.bits.uop.is_br invalidate pred_wakeup.bits.fflags.bits.uop.iw_p2_poisoned invalidate pred_wakeup.bits.fflags.bits.uop.iw_p1_poisoned invalidate pred_wakeup.bits.fflags.bits.uop.iw_state invalidate pred_wakeup.bits.fflags.bits.uop.ctrl.is_std invalidate pred_wakeup.bits.fflags.bits.uop.ctrl.is_sta invalidate pred_wakeup.bits.fflags.bits.uop.ctrl.is_load invalidate pred_wakeup.bits.fflags.bits.uop.ctrl.csr_cmd invalidate pred_wakeup.bits.fflags.bits.uop.ctrl.fcn_dw invalidate pred_wakeup.bits.fflags.bits.uop.ctrl.op_fcn invalidate pred_wakeup.bits.fflags.bits.uop.ctrl.imm_sel invalidate pred_wakeup.bits.fflags.bits.uop.ctrl.op2_sel invalidate pred_wakeup.bits.fflags.bits.uop.ctrl.op1_sel invalidate pred_wakeup.bits.fflags.bits.uop.ctrl.br_type invalidate pred_wakeup.bits.fflags.bits.uop.fu_code invalidate pred_wakeup.bits.fflags.bits.uop.iq_type invalidate pred_wakeup.bits.fflags.bits.uop.debug_pc invalidate pred_wakeup.bits.fflags.bits.uop.is_rvc invalidate pred_wakeup.bits.fflags.bits.uop.debug_inst invalidate pred_wakeup.bits.fflags.bits.uop.inst invalidate pred_wakeup.bits.fflags.bits.uop.uopc invalidate pred_wakeup.bits.fflags.valid invalidate pred_wakeup.bits.data invalidate pred_wakeup.bits.predicated connect mem_issue_unit.io.spec_ld_wakeup[0].bits, io.lsu.spec_ld_wakeup[0].bits connect mem_issue_unit.io.spec_ld_wakeup[0].valid, io.lsu.spec_ld_wakeup[0].valid connect int_issue_unit.io.spec_ld_wakeup[0].bits, io.lsu.spec_ld_wakeup[0].bits connect int_issue_unit.io.spec_ld_wakeup[0].valid, io.lsu.spec_ld_wakeup[0].valid connect mem_issue_unit.io.pred_wakeup_port.valid, UInt<1>(0h0) invalidate mem_issue_unit.io.pred_wakeup_port.bits connect int_issue_unit.io.pred_wakeup_port.valid, UInt<1>(0h0) invalidate int_issue_unit.io.pred_wakeup_port.bits connect rename_stage.io.wakeups[0], int_ren_wakeups[0] connect rename_stage.io.wakeups[1], int_ren_wakeups[1] connect rename_stage.io.wakeups[2], int_ren_wakeups[2] connect rename_stage.io.wakeups[3], int_ren_wakeups[3] connect rename_stage.io.wakeups[4], int_ren_wakeups[4] connect rename_stage.io.wakeups[5], int_ren_wakeups[5] connect rename_stage.io.wakeups[6], int_ren_wakeups[6] connect fp_rename_stage.io.wakeups[0], FpPipeline.io.wakeups[0] connect fp_rename_stage.io.wakeups[1], FpPipeline.io.wakeups[1] invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.flags invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.debug_tsrc invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.debug_fsrc invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.bp_xcpt_if invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.bp_debug_if invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.xcpt_ma_if invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.xcpt_ae_if invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.xcpt_pf_if invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.fp_single invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.fp_val invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.frs3_en invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.lrs2_rtype invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.lrs1_rtype invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.dst_rtype invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ldst_val invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.lrs3 invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.lrs2 invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.lrs1 invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ldst invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ldst_is_rs1 invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.flush_on_commit invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.is_unique invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.is_sys_pc2epc invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.uses_stq invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.uses_ldq invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.is_amo invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.is_fencei invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.is_fence invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.mem_signed invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.mem_size invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.mem_cmd invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.bypassable invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.exc_cause invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.exception invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.stale_pdst invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ppred_busy invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.prs3_busy invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.prs2_busy invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.prs1_busy invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ppred invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.prs3 invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.prs2 invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.prs1 invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.pdst invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.rxq_idx invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.stq_idx invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ldq_idx invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.rob_idx invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.csr_addr invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.imm_packed invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.taken invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.pc_lob invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.edge_inst invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ftq_idx invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.br_tag invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.br_mask invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.is_sfb invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.is_jal invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.is_jalr invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.is_br invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.iw_p2_poisoned invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.iw_p1_poisoned invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.iw_state invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ctrl.is_std invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ctrl.is_sta invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ctrl.is_load invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ctrl.csr_cmd invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ctrl.fcn_dw invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ctrl.op_fcn invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ctrl.imm_sel invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ctrl.op2_sel invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ctrl.op1_sel invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.ctrl.br_type invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.fu_code invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.iq_type invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.debug_pc invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.is_rvc invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.debug_inst invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.inst invalidate pred_rename_stage.io.wakeups[0].bits.fflags.bits.uop.uopc invalidate pred_rename_stage.io.wakeups[0].bits.fflags.valid invalidate pred_rename_stage.io.wakeups[0].bits.predicated invalidate pred_rename_stage.io.wakeups[0].bits.data invalidate pred_rename_stage.io.wakeups[0].bits.uop.debug_tsrc invalidate pred_rename_stage.io.wakeups[0].bits.uop.debug_fsrc invalidate pred_rename_stage.io.wakeups[0].bits.uop.bp_xcpt_if invalidate pred_rename_stage.io.wakeups[0].bits.uop.bp_debug_if invalidate pred_rename_stage.io.wakeups[0].bits.uop.xcpt_ma_if invalidate pred_rename_stage.io.wakeups[0].bits.uop.xcpt_ae_if invalidate pred_rename_stage.io.wakeups[0].bits.uop.xcpt_pf_if invalidate pred_rename_stage.io.wakeups[0].bits.uop.fp_single invalidate pred_rename_stage.io.wakeups[0].bits.uop.fp_val invalidate pred_rename_stage.io.wakeups[0].bits.uop.frs3_en invalidate pred_rename_stage.io.wakeups[0].bits.uop.lrs2_rtype invalidate pred_rename_stage.io.wakeups[0].bits.uop.lrs1_rtype invalidate pred_rename_stage.io.wakeups[0].bits.uop.dst_rtype invalidate pred_rename_stage.io.wakeups[0].bits.uop.ldst_val invalidate pred_rename_stage.io.wakeups[0].bits.uop.lrs3 invalidate pred_rename_stage.io.wakeups[0].bits.uop.lrs2 invalidate pred_rename_stage.io.wakeups[0].bits.uop.lrs1 invalidate pred_rename_stage.io.wakeups[0].bits.uop.ldst invalidate pred_rename_stage.io.wakeups[0].bits.uop.ldst_is_rs1 invalidate pred_rename_stage.io.wakeups[0].bits.uop.flush_on_commit invalidate pred_rename_stage.io.wakeups[0].bits.uop.is_unique invalidate pred_rename_stage.io.wakeups[0].bits.uop.is_sys_pc2epc invalidate pred_rename_stage.io.wakeups[0].bits.uop.uses_stq invalidate pred_rename_stage.io.wakeups[0].bits.uop.uses_ldq invalidate pred_rename_stage.io.wakeups[0].bits.uop.is_amo invalidate pred_rename_stage.io.wakeups[0].bits.uop.is_fencei invalidate pred_rename_stage.io.wakeups[0].bits.uop.is_fence invalidate pred_rename_stage.io.wakeups[0].bits.uop.mem_signed invalidate pred_rename_stage.io.wakeups[0].bits.uop.mem_size invalidate pred_rename_stage.io.wakeups[0].bits.uop.mem_cmd invalidate pred_rename_stage.io.wakeups[0].bits.uop.bypassable invalidate pred_rename_stage.io.wakeups[0].bits.uop.exc_cause invalidate pred_rename_stage.io.wakeups[0].bits.uop.exception invalidate pred_rename_stage.io.wakeups[0].bits.uop.stale_pdst invalidate pred_rename_stage.io.wakeups[0].bits.uop.ppred_busy invalidate pred_rename_stage.io.wakeups[0].bits.uop.prs3_busy invalidate pred_rename_stage.io.wakeups[0].bits.uop.prs2_busy invalidate pred_rename_stage.io.wakeups[0].bits.uop.prs1_busy invalidate pred_rename_stage.io.wakeups[0].bits.uop.ppred invalidate pred_rename_stage.io.wakeups[0].bits.uop.prs3 invalidate pred_rename_stage.io.wakeups[0].bits.uop.prs2 invalidate pred_rename_stage.io.wakeups[0].bits.uop.prs1 invalidate pred_rename_stage.io.wakeups[0].bits.uop.pdst invalidate pred_rename_stage.io.wakeups[0].bits.uop.rxq_idx invalidate pred_rename_stage.io.wakeups[0].bits.uop.stq_idx invalidate pred_rename_stage.io.wakeups[0].bits.uop.ldq_idx invalidate pred_rename_stage.io.wakeups[0].bits.uop.rob_idx invalidate pred_rename_stage.io.wakeups[0].bits.uop.csr_addr invalidate pred_rename_stage.io.wakeups[0].bits.uop.imm_packed invalidate pred_rename_stage.io.wakeups[0].bits.uop.taken invalidate pred_rename_stage.io.wakeups[0].bits.uop.pc_lob invalidate pred_rename_stage.io.wakeups[0].bits.uop.edge_inst invalidate pred_rename_stage.io.wakeups[0].bits.uop.ftq_idx invalidate pred_rename_stage.io.wakeups[0].bits.uop.br_tag invalidate pred_rename_stage.io.wakeups[0].bits.uop.br_mask invalidate pred_rename_stage.io.wakeups[0].bits.uop.is_sfb invalidate pred_rename_stage.io.wakeups[0].bits.uop.is_jal invalidate pred_rename_stage.io.wakeups[0].bits.uop.is_jalr invalidate pred_rename_stage.io.wakeups[0].bits.uop.is_br invalidate pred_rename_stage.io.wakeups[0].bits.uop.iw_p2_poisoned invalidate pred_rename_stage.io.wakeups[0].bits.uop.iw_p1_poisoned invalidate pred_rename_stage.io.wakeups[0].bits.uop.iw_state invalidate pred_rename_stage.io.wakeups[0].bits.uop.ctrl.is_std invalidate pred_rename_stage.io.wakeups[0].bits.uop.ctrl.is_sta invalidate pred_rename_stage.io.wakeups[0].bits.uop.ctrl.is_load invalidate pred_rename_stage.io.wakeups[0].bits.uop.ctrl.csr_cmd invalidate pred_rename_stage.io.wakeups[0].bits.uop.ctrl.fcn_dw invalidate pred_rename_stage.io.wakeups[0].bits.uop.ctrl.op_fcn invalidate pred_rename_stage.io.wakeups[0].bits.uop.ctrl.imm_sel invalidate pred_rename_stage.io.wakeups[0].bits.uop.ctrl.op2_sel invalidate pred_rename_stage.io.wakeups[0].bits.uop.ctrl.op1_sel invalidate pred_rename_stage.io.wakeups[0].bits.uop.ctrl.br_type invalidate pred_rename_stage.io.wakeups[0].bits.uop.fu_code invalidate pred_rename_stage.io.wakeups[0].bits.uop.iq_type invalidate pred_rename_stage.io.wakeups[0].bits.uop.debug_pc invalidate pred_rename_stage.io.wakeups[0].bits.uop.is_rvc invalidate pred_rename_stage.io.wakeups[0].bits.uop.debug_inst invalidate pred_rename_stage.io.wakeups[0].bits.uop.inst invalidate pred_rename_stage.io.wakeups[0].bits.uop.uopc invalidate pred_rename_stage.io.wakeups[0].valid node loads_saturating = and(mem_issue_unit.io.iss_valids[0], mem_issue_unit.io.iss_uops[0].uses_ldq) regreset saturating_loads_counter : UInt<5>, clock, reset, UInt<5>(0h0) when loads_saturating : node _saturating_loads_counter_T = add(saturating_loads_counter, UInt<1>(0h1)) node _saturating_loads_counter_T_1 = tail(_saturating_loads_counter_T, 1) connect saturating_loads_counter, _saturating_loads_counter_T_1 else : connect saturating_loads_counter, UInt<1>(0h0) reg pause_mem_REG : UInt<1>, clock connect pause_mem_REG, loads_saturating node _pause_mem_T = not(UInt<5>(0h0)) node _pause_mem_T_1 = eq(saturating_loads_counter, _pause_mem_T) node pause_mem = and(pause_mem_REG, _pause_mem_T_1) connect iss_valids[0], mem_issue_unit.io.iss_valids[0] connect iss_uops[0], mem_issue_unit.io.iss_uops[0] node _mem_issue_unit_io_fu_types_0_T = mux(pause_mem, UInt<1>(0h0), memExeUnit.io.fu_types) connect mem_issue_unit.io.fu_types[0], _mem_issue_unit_io_fu_types_0_T node _idiv_issued_T = and(iss_uops[1].fu_code, UInt<10>(0h10)) node _idiv_issued_T_1 = neq(_idiv_issued_T, UInt<1>(0h0)) node idiv_issued = and(iss_valids[1], _idiv_issued_T_1) node _T_73 = mux(idiv_issued, UInt<10>(0h10), UInt<1>(0h0)) node _T_74 = not(_T_73) reg REG_4 : UInt, clock connect REG_4, _T_74 node _T_75 = and(alu_exe_unit.io.fu_types, REG_4) connect iss_valids[1], int_issue_unit.io.iss_valids[0] connect iss_uops[1], int_issue_unit.io.iss_uops[0] connect int_issue_unit.io.fu_types[0], _T_75 connect iss_valids[2], int_issue_unit.io.iss_valids[1] connect iss_uops[2], int_issue_unit.io.iss_uops[1] connect int_issue_unit.io.fu_types[1], alu_exe_unit_1.io.fu_types node _idiv_issued_T_2 = and(iss_uops[3].fu_code, UInt<10>(0h10)) node _idiv_issued_T_3 = neq(_idiv_issued_T_2, UInt<1>(0h0)) node idiv_issued_1 = and(iss_valids[3], _idiv_issued_T_3) node _T_76 = mux(idiv_issued_1, UInt<10>(0h10), UInt<1>(0h0)) node _T_77 = not(_T_76) reg REG_5 : UInt, clock connect REG_5, _T_77 node _T_78 = and(alu_exe_unit_2.io.fu_types, REG_5) connect iss_valids[3], int_issue_unit.io.iss_valids[2] connect iss_uops[3], int_issue_unit.io.iss_uops[2] connect int_issue_unit.io.fu_types[2], _T_78 connect mem_issue_unit.io.tsc_reg, debug_tsc_reg connect int_issue_unit.io.tsc_reg, debug_tsc_reg connect mem_issue_unit.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect mem_issue_unit.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect mem_issue_unit.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect mem_issue_unit.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect mem_issue_unit.io.brupdate.b2.taken, brupdate.b2.taken connect mem_issue_unit.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect mem_issue_unit.io.brupdate.b2.valid, brupdate.b2.valid connect mem_issue_unit.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect mem_issue_unit.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect mem_issue_unit.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect mem_issue_unit.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect mem_issue_unit.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect mem_issue_unit.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect mem_issue_unit.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect mem_issue_unit.io.brupdate.b2.uop.fp_single, brupdate.b2.uop.fp_single connect mem_issue_unit.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect mem_issue_unit.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect mem_issue_unit.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect mem_issue_unit.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect mem_issue_unit.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect mem_issue_unit.io.brupdate.b2.uop.ldst_val, brupdate.b2.uop.ldst_val connect mem_issue_unit.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect mem_issue_unit.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect mem_issue_unit.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect mem_issue_unit.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect mem_issue_unit.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect mem_issue_unit.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect mem_issue_unit.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect mem_issue_unit.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect mem_issue_unit.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect mem_issue_unit.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect mem_issue_unit.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect mem_issue_unit.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect mem_issue_unit.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect mem_issue_unit.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect mem_issue_unit.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect mem_issue_unit.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect mem_issue_unit.io.brupdate.b2.uop.bypassable, brupdate.b2.uop.bypassable connect mem_issue_unit.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect mem_issue_unit.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect mem_issue_unit.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect mem_issue_unit.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect mem_issue_unit.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect mem_issue_unit.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect mem_issue_unit.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect mem_issue_unit.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect mem_issue_unit.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect mem_issue_unit.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect mem_issue_unit.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect mem_issue_unit.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect mem_issue_unit.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect mem_issue_unit.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect mem_issue_unit.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect mem_issue_unit.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect mem_issue_unit.io.brupdate.b2.uop.csr_addr, brupdate.b2.uop.csr_addr connect mem_issue_unit.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect mem_issue_unit.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect mem_issue_unit.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect mem_issue_unit.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect mem_issue_unit.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect mem_issue_unit.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect mem_issue_unit.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect mem_issue_unit.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect mem_issue_unit.io.brupdate.b2.uop.is_jal, brupdate.b2.uop.is_jal connect mem_issue_unit.io.brupdate.b2.uop.is_jalr, brupdate.b2.uop.is_jalr connect mem_issue_unit.io.brupdate.b2.uop.is_br, brupdate.b2.uop.is_br connect mem_issue_unit.io.brupdate.b2.uop.iw_p2_poisoned, brupdate.b2.uop.iw_p2_poisoned connect mem_issue_unit.io.brupdate.b2.uop.iw_p1_poisoned, brupdate.b2.uop.iw_p1_poisoned connect mem_issue_unit.io.brupdate.b2.uop.iw_state, brupdate.b2.uop.iw_state connect mem_issue_unit.io.brupdate.b2.uop.ctrl.is_std, brupdate.b2.uop.ctrl.is_std connect mem_issue_unit.io.brupdate.b2.uop.ctrl.is_sta, brupdate.b2.uop.ctrl.is_sta connect mem_issue_unit.io.brupdate.b2.uop.ctrl.is_load, brupdate.b2.uop.ctrl.is_load connect mem_issue_unit.io.brupdate.b2.uop.ctrl.csr_cmd, brupdate.b2.uop.ctrl.csr_cmd connect mem_issue_unit.io.brupdate.b2.uop.ctrl.fcn_dw, brupdate.b2.uop.ctrl.fcn_dw connect mem_issue_unit.io.brupdate.b2.uop.ctrl.op_fcn, brupdate.b2.uop.ctrl.op_fcn connect mem_issue_unit.io.brupdate.b2.uop.ctrl.imm_sel, brupdate.b2.uop.ctrl.imm_sel connect mem_issue_unit.io.brupdate.b2.uop.ctrl.op2_sel, brupdate.b2.uop.ctrl.op2_sel connect mem_issue_unit.io.brupdate.b2.uop.ctrl.op1_sel, brupdate.b2.uop.ctrl.op1_sel connect mem_issue_unit.io.brupdate.b2.uop.ctrl.br_type, brupdate.b2.uop.ctrl.br_type connect mem_issue_unit.io.brupdate.b2.uop.fu_code, brupdate.b2.uop.fu_code connect mem_issue_unit.io.brupdate.b2.uop.iq_type, brupdate.b2.uop.iq_type connect mem_issue_unit.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect mem_issue_unit.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect mem_issue_unit.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect mem_issue_unit.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect mem_issue_unit.io.brupdate.b2.uop.uopc, brupdate.b2.uop.uopc connect mem_issue_unit.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect mem_issue_unit.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect int_issue_unit.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect int_issue_unit.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect int_issue_unit.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect int_issue_unit.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect int_issue_unit.io.brupdate.b2.taken, brupdate.b2.taken connect int_issue_unit.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect int_issue_unit.io.brupdate.b2.valid, brupdate.b2.valid connect int_issue_unit.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect int_issue_unit.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect int_issue_unit.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect int_issue_unit.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect int_issue_unit.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect int_issue_unit.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect int_issue_unit.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect int_issue_unit.io.brupdate.b2.uop.fp_single, brupdate.b2.uop.fp_single connect int_issue_unit.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect int_issue_unit.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect int_issue_unit.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect int_issue_unit.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect int_issue_unit.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect int_issue_unit.io.brupdate.b2.uop.ldst_val, brupdate.b2.uop.ldst_val connect int_issue_unit.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect int_issue_unit.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect int_issue_unit.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect int_issue_unit.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect int_issue_unit.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect int_issue_unit.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect int_issue_unit.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect int_issue_unit.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect int_issue_unit.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect int_issue_unit.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect int_issue_unit.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect int_issue_unit.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect int_issue_unit.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect int_issue_unit.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect int_issue_unit.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect int_issue_unit.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect int_issue_unit.io.brupdate.b2.uop.bypassable, brupdate.b2.uop.bypassable connect int_issue_unit.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect int_issue_unit.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect int_issue_unit.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect int_issue_unit.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect int_issue_unit.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect int_issue_unit.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect int_issue_unit.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect int_issue_unit.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect int_issue_unit.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect int_issue_unit.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect int_issue_unit.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect int_issue_unit.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect int_issue_unit.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect int_issue_unit.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect int_issue_unit.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect int_issue_unit.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect int_issue_unit.io.brupdate.b2.uop.csr_addr, brupdate.b2.uop.csr_addr connect int_issue_unit.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect int_issue_unit.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect int_issue_unit.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect int_issue_unit.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect int_issue_unit.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect int_issue_unit.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect int_issue_unit.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect int_issue_unit.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect int_issue_unit.io.brupdate.b2.uop.is_jal, brupdate.b2.uop.is_jal connect int_issue_unit.io.brupdate.b2.uop.is_jalr, brupdate.b2.uop.is_jalr connect int_issue_unit.io.brupdate.b2.uop.is_br, brupdate.b2.uop.is_br connect int_issue_unit.io.brupdate.b2.uop.iw_p2_poisoned, brupdate.b2.uop.iw_p2_poisoned connect int_issue_unit.io.brupdate.b2.uop.iw_p1_poisoned, brupdate.b2.uop.iw_p1_poisoned connect int_issue_unit.io.brupdate.b2.uop.iw_state, brupdate.b2.uop.iw_state connect int_issue_unit.io.brupdate.b2.uop.ctrl.is_std, brupdate.b2.uop.ctrl.is_std connect int_issue_unit.io.brupdate.b2.uop.ctrl.is_sta, brupdate.b2.uop.ctrl.is_sta connect int_issue_unit.io.brupdate.b2.uop.ctrl.is_load, brupdate.b2.uop.ctrl.is_load connect int_issue_unit.io.brupdate.b2.uop.ctrl.csr_cmd, brupdate.b2.uop.ctrl.csr_cmd connect int_issue_unit.io.brupdate.b2.uop.ctrl.fcn_dw, brupdate.b2.uop.ctrl.fcn_dw connect int_issue_unit.io.brupdate.b2.uop.ctrl.op_fcn, brupdate.b2.uop.ctrl.op_fcn connect int_issue_unit.io.brupdate.b2.uop.ctrl.imm_sel, brupdate.b2.uop.ctrl.imm_sel connect int_issue_unit.io.brupdate.b2.uop.ctrl.op2_sel, brupdate.b2.uop.ctrl.op2_sel connect int_issue_unit.io.brupdate.b2.uop.ctrl.op1_sel, brupdate.b2.uop.ctrl.op1_sel connect int_issue_unit.io.brupdate.b2.uop.ctrl.br_type, brupdate.b2.uop.ctrl.br_type connect int_issue_unit.io.brupdate.b2.uop.fu_code, brupdate.b2.uop.fu_code connect int_issue_unit.io.brupdate.b2.uop.iq_type, brupdate.b2.uop.iq_type connect int_issue_unit.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect int_issue_unit.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect int_issue_unit.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect int_issue_unit.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect int_issue_unit.io.brupdate.b2.uop.uopc, brupdate.b2.uop.uopc connect int_issue_unit.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect int_issue_unit.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask reg mem_issue_unit_io_flush_pipeline_REG : UInt<1>, clock connect mem_issue_unit_io_flush_pipeline_REG, rob.io.flush.valid connect mem_issue_unit.io.flush_pipeline, mem_issue_unit_io_flush_pipeline_REG reg int_issue_unit_io_flush_pipeline_REG : UInt<1>, clock connect int_issue_unit_io_flush_pipeline_REG, rob.io.flush.valid connect int_issue_unit.io.flush_pipeline, int_issue_unit_io_flush_pipeline_REG connect mem_issue_unit.io.ld_miss, io.lsu.ld_miss connect int_issue_unit.io.ld_miss, io.lsu.ld_miss reg memExeUnit_io_com_exception_REG : UInt<1>, clock connect memExeUnit_io_com_exception_REG, rob.io.flush.valid connect memExeUnit.io.com_exception, memExeUnit_io_com_exception_REG connect mem_issue_unit.io.wakeup_ports[0].valid, int_iss_wakeups[0].valid connect mem_issue_unit.io.wakeup_ports[0].bits.pdst, int_iss_wakeups[0].bits.uop.pdst node _mem_issue_unit_io_wakeup_ports_0_bits_poisoned_T = or(int_iss_wakeups[0].bits.uop.iw_p1_poisoned, int_iss_wakeups[0].bits.uop.iw_p2_poisoned) connect mem_issue_unit.io.wakeup_ports[0].bits.poisoned, _mem_issue_unit_io_wakeup_ports_0_bits_poisoned_T connect mem_issue_unit.io.wakeup_ports[1].valid, int_iss_wakeups[1].valid connect mem_issue_unit.io.wakeup_ports[1].bits.pdst, int_iss_wakeups[1].bits.uop.pdst node _mem_issue_unit_io_wakeup_ports_1_bits_poisoned_T = or(int_iss_wakeups[1].bits.uop.iw_p1_poisoned, int_iss_wakeups[1].bits.uop.iw_p2_poisoned) connect mem_issue_unit.io.wakeup_ports[1].bits.poisoned, _mem_issue_unit_io_wakeup_ports_1_bits_poisoned_T connect mem_issue_unit.io.wakeup_ports[2].valid, int_iss_wakeups[2].valid connect mem_issue_unit.io.wakeup_ports[2].bits.pdst, int_iss_wakeups[2].bits.uop.pdst node _mem_issue_unit_io_wakeup_ports_2_bits_poisoned_T = or(int_iss_wakeups[2].bits.uop.iw_p1_poisoned, int_iss_wakeups[2].bits.uop.iw_p2_poisoned) connect mem_issue_unit.io.wakeup_ports[2].bits.poisoned, _mem_issue_unit_io_wakeup_ports_2_bits_poisoned_T connect mem_issue_unit.io.wakeup_ports[3].valid, int_iss_wakeups[3].valid connect mem_issue_unit.io.wakeup_ports[3].bits.pdst, int_iss_wakeups[3].bits.uop.pdst node _mem_issue_unit_io_wakeup_ports_3_bits_poisoned_T = or(int_iss_wakeups[3].bits.uop.iw_p1_poisoned, int_iss_wakeups[3].bits.uop.iw_p2_poisoned) connect mem_issue_unit.io.wakeup_ports[3].bits.poisoned, _mem_issue_unit_io_wakeup_ports_3_bits_poisoned_T connect mem_issue_unit.io.wakeup_ports[4].valid, int_iss_wakeups[4].valid connect mem_issue_unit.io.wakeup_ports[4].bits.pdst, int_iss_wakeups[4].bits.uop.pdst node _mem_issue_unit_io_wakeup_ports_4_bits_poisoned_T = or(int_iss_wakeups[4].bits.uop.iw_p1_poisoned, int_iss_wakeups[4].bits.uop.iw_p2_poisoned) connect mem_issue_unit.io.wakeup_ports[4].bits.poisoned, _mem_issue_unit_io_wakeup_ports_4_bits_poisoned_T connect mem_issue_unit.io.wakeup_ports[5].valid, int_iss_wakeups[5].valid connect mem_issue_unit.io.wakeup_ports[5].bits.pdst, int_iss_wakeups[5].bits.uop.pdst node _mem_issue_unit_io_wakeup_ports_5_bits_poisoned_T = or(int_iss_wakeups[5].bits.uop.iw_p1_poisoned, int_iss_wakeups[5].bits.uop.iw_p2_poisoned) connect mem_issue_unit.io.wakeup_ports[5].bits.poisoned, _mem_issue_unit_io_wakeup_ports_5_bits_poisoned_T connect mem_issue_unit.io.wakeup_ports[6].valid, int_iss_wakeups[6].valid connect mem_issue_unit.io.wakeup_ports[6].bits.pdst, int_iss_wakeups[6].bits.uop.pdst node _mem_issue_unit_io_wakeup_ports_6_bits_poisoned_T = or(int_iss_wakeups[6].bits.uop.iw_p1_poisoned, int_iss_wakeups[6].bits.uop.iw_p2_poisoned) connect mem_issue_unit.io.wakeup_ports[6].bits.poisoned, _mem_issue_unit_io_wakeup_ports_6_bits_poisoned_T connect int_issue_unit.io.wakeup_ports[0].valid, int_iss_wakeups[0].valid connect int_issue_unit.io.wakeup_ports[0].bits.pdst, int_iss_wakeups[0].bits.uop.pdst node _int_issue_unit_io_wakeup_ports_0_bits_poisoned_T = or(int_iss_wakeups[0].bits.uop.iw_p1_poisoned, int_iss_wakeups[0].bits.uop.iw_p2_poisoned) connect int_issue_unit.io.wakeup_ports[0].bits.poisoned, _int_issue_unit_io_wakeup_ports_0_bits_poisoned_T connect int_issue_unit.io.wakeup_ports[1].valid, int_iss_wakeups[1].valid connect int_issue_unit.io.wakeup_ports[1].bits.pdst, int_iss_wakeups[1].bits.uop.pdst node _int_issue_unit_io_wakeup_ports_1_bits_poisoned_T = or(int_iss_wakeups[1].bits.uop.iw_p1_poisoned, int_iss_wakeups[1].bits.uop.iw_p2_poisoned) connect int_issue_unit.io.wakeup_ports[1].bits.poisoned, _int_issue_unit_io_wakeup_ports_1_bits_poisoned_T connect int_issue_unit.io.wakeup_ports[2].valid, int_iss_wakeups[2].valid connect int_issue_unit.io.wakeup_ports[2].bits.pdst, int_iss_wakeups[2].bits.uop.pdst node _int_issue_unit_io_wakeup_ports_2_bits_poisoned_T = or(int_iss_wakeups[2].bits.uop.iw_p1_poisoned, int_iss_wakeups[2].bits.uop.iw_p2_poisoned) connect int_issue_unit.io.wakeup_ports[2].bits.poisoned, _int_issue_unit_io_wakeup_ports_2_bits_poisoned_T connect int_issue_unit.io.wakeup_ports[3].valid, int_iss_wakeups[3].valid connect int_issue_unit.io.wakeup_ports[3].bits.pdst, int_iss_wakeups[3].bits.uop.pdst node _int_issue_unit_io_wakeup_ports_3_bits_poisoned_T = or(int_iss_wakeups[3].bits.uop.iw_p1_poisoned, int_iss_wakeups[3].bits.uop.iw_p2_poisoned) connect int_issue_unit.io.wakeup_ports[3].bits.poisoned, _int_issue_unit_io_wakeup_ports_3_bits_poisoned_T connect int_issue_unit.io.wakeup_ports[4].valid, int_iss_wakeups[4].valid connect int_issue_unit.io.wakeup_ports[4].bits.pdst, int_iss_wakeups[4].bits.uop.pdst node _int_issue_unit_io_wakeup_ports_4_bits_poisoned_T = or(int_iss_wakeups[4].bits.uop.iw_p1_poisoned, int_iss_wakeups[4].bits.uop.iw_p2_poisoned) connect int_issue_unit.io.wakeup_ports[4].bits.poisoned, _int_issue_unit_io_wakeup_ports_4_bits_poisoned_T connect int_issue_unit.io.wakeup_ports[5].valid, int_iss_wakeups[5].valid connect int_issue_unit.io.wakeup_ports[5].bits.pdst, int_iss_wakeups[5].bits.uop.pdst node _int_issue_unit_io_wakeup_ports_5_bits_poisoned_T = or(int_iss_wakeups[5].bits.uop.iw_p1_poisoned, int_iss_wakeups[5].bits.uop.iw_p2_poisoned) connect int_issue_unit.io.wakeup_ports[5].bits.poisoned, _int_issue_unit_io_wakeup_ports_5_bits_poisoned_T connect int_issue_unit.io.wakeup_ports[6].valid, int_iss_wakeups[6].valid connect int_issue_unit.io.wakeup_ports[6].bits.pdst, int_iss_wakeups[6].bits.uop.pdst node _int_issue_unit_io_wakeup_ports_6_bits_poisoned_T = or(int_iss_wakeups[6].bits.uop.iw_p1_poisoned, int_iss_wakeups[6].bits.uop.iw_p2_poisoned) connect int_issue_unit.io.wakeup_ports[6].bits.poisoned, _int_issue_unit_io_wakeup_ports_6_bits_poisoned_T connect iregister_read.io.rf_read_ports, iregfile.io.read_ports invalidate iregister_read.io.prf_read_ports[0].data invalidate iregister_read.io.prf_read_ports[0].addr invalidate iregister_read.io.prf_read_ports[1].data invalidate iregister_read.io.prf_read_ports[1].addr invalidate iregister_read.io.prf_read_ports[2].data invalidate iregister_read.io.prf_read_ports[2].addr invalidate iregister_read.io.prf_read_ports[3].data invalidate iregister_read.io.prf_read_ports[3].addr node _iregister_read_io_iss_valids_0_T = or(iss_uops[0].iw_p1_poisoned, iss_uops[0].iw_p2_poisoned) node _iregister_read_io_iss_valids_0_T_1 = and(io.lsu.ld_miss, _iregister_read_io_iss_valids_0_T) node _iregister_read_io_iss_valids_0_T_2 = eq(_iregister_read_io_iss_valids_0_T_1, UInt<1>(0h0)) node _iregister_read_io_iss_valids_0_T_3 = and(iss_valids[0], _iregister_read_io_iss_valids_0_T_2) connect iregister_read.io.iss_valids[0], _iregister_read_io_iss_valids_0_T_3 node _iregister_read_io_iss_valids_1_T = or(iss_uops[1].iw_p1_poisoned, iss_uops[1].iw_p2_poisoned) node _iregister_read_io_iss_valids_1_T_1 = and(io.lsu.ld_miss, _iregister_read_io_iss_valids_1_T) node _iregister_read_io_iss_valids_1_T_2 = eq(_iregister_read_io_iss_valids_1_T_1, UInt<1>(0h0)) node _iregister_read_io_iss_valids_1_T_3 = and(iss_valids[1], _iregister_read_io_iss_valids_1_T_2) connect iregister_read.io.iss_valids[1], _iregister_read_io_iss_valids_1_T_3 node _iregister_read_io_iss_valids_2_T = or(iss_uops[2].iw_p1_poisoned, iss_uops[2].iw_p2_poisoned) node _iregister_read_io_iss_valids_2_T_1 = and(io.lsu.ld_miss, _iregister_read_io_iss_valids_2_T) node _iregister_read_io_iss_valids_2_T_2 = eq(_iregister_read_io_iss_valids_2_T_1, UInt<1>(0h0)) node _iregister_read_io_iss_valids_2_T_3 = and(iss_valids[2], _iregister_read_io_iss_valids_2_T_2) connect iregister_read.io.iss_valids[2], _iregister_read_io_iss_valids_2_T_3 node _iregister_read_io_iss_valids_3_T = or(iss_uops[3].iw_p1_poisoned, iss_uops[3].iw_p2_poisoned) node _iregister_read_io_iss_valids_3_T_1 = and(io.lsu.ld_miss, _iregister_read_io_iss_valids_3_T) node _iregister_read_io_iss_valids_3_T_2 = eq(_iregister_read_io_iss_valids_3_T_1, UInt<1>(0h0)) node _iregister_read_io_iss_valids_3_T_3 = and(iss_valids[3], _iregister_read_io_iss_valids_3_T_2) connect iregister_read.io.iss_valids[3], _iregister_read_io_iss_valids_3_T_3 connect iregister_read.io.iss_uops[0].debug_tsrc, iss_uops[0].debug_tsrc connect iregister_read.io.iss_uops[0].debug_fsrc, iss_uops[0].debug_fsrc connect iregister_read.io.iss_uops[0].bp_xcpt_if, iss_uops[0].bp_xcpt_if connect iregister_read.io.iss_uops[0].bp_debug_if, iss_uops[0].bp_debug_if connect iregister_read.io.iss_uops[0].xcpt_ma_if, iss_uops[0].xcpt_ma_if connect iregister_read.io.iss_uops[0].xcpt_ae_if, iss_uops[0].xcpt_ae_if connect iregister_read.io.iss_uops[0].xcpt_pf_if, iss_uops[0].xcpt_pf_if connect iregister_read.io.iss_uops[0].fp_single, iss_uops[0].fp_single connect iregister_read.io.iss_uops[0].fp_val, iss_uops[0].fp_val connect iregister_read.io.iss_uops[0].frs3_en, iss_uops[0].frs3_en connect iregister_read.io.iss_uops[0].lrs2_rtype, iss_uops[0].lrs2_rtype connect iregister_read.io.iss_uops[0].lrs1_rtype, iss_uops[0].lrs1_rtype connect iregister_read.io.iss_uops[0].dst_rtype, iss_uops[0].dst_rtype connect iregister_read.io.iss_uops[0].ldst_val, iss_uops[0].ldst_val connect iregister_read.io.iss_uops[0].lrs3, iss_uops[0].lrs3 connect iregister_read.io.iss_uops[0].lrs2, iss_uops[0].lrs2 connect iregister_read.io.iss_uops[0].lrs1, iss_uops[0].lrs1 connect iregister_read.io.iss_uops[0].ldst, iss_uops[0].ldst connect iregister_read.io.iss_uops[0].ldst_is_rs1, iss_uops[0].ldst_is_rs1 connect iregister_read.io.iss_uops[0].flush_on_commit, iss_uops[0].flush_on_commit connect iregister_read.io.iss_uops[0].is_unique, iss_uops[0].is_unique connect iregister_read.io.iss_uops[0].is_sys_pc2epc, iss_uops[0].is_sys_pc2epc connect iregister_read.io.iss_uops[0].uses_stq, iss_uops[0].uses_stq connect iregister_read.io.iss_uops[0].uses_ldq, iss_uops[0].uses_ldq connect iregister_read.io.iss_uops[0].is_amo, iss_uops[0].is_amo connect iregister_read.io.iss_uops[0].is_fencei, iss_uops[0].is_fencei connect iregister_read.io.iss_uops[0].is_fence, iss_uops[0].is_fence connect iregister_read.io.iss_uops[0].mem_signed, iss_uops[0].mem_signed connect iregister_read.io.iss_uops[0].mem_size, iss_uops[0].mem_size connect iregister_read.io.iss_uops[0].mem_cmd, iss_uops[0].mem_cmd connect iregister_read.io.iss_uops[0].bypassable, iss_uops[0].bypassable connect iregister_read.io.iss_uops[0].exc_cause, iss_uops[0].exc_cause connect iregister_read.io.iss_uops[0].exception, iss_uops[0].exception connect iregister_read.io.iss_uops[0].stale_pdst, iss_uops[0].stale_pdst connect iregister_read.io.iss_uops[0].ppred_busy, iss_uops[0].ppred_busy connect iregister_read.io.iss_uops[0].prs3_busy, iss_uops[0].prs3_busy connect iregister_read.io.iss_uops[0].prs2_busy, iss_uops[0].prs2_busy connect iregister_read.io.iss_uops[0].prs1_busy, iss_uops[0].prs1_busy connect iregister_read.io.iss_uops[0].ppred, iss_uops[0].ppred connect iregister_read.io.iss_uops[0].prs3, iss_uops[0].prs3 connect iregister_read.io.iss_uops[0].prs2, iss_uops[0].prs2 connect iregister_read.io.iss_uops[0].prs1, iss_uops[0].prs1 connect iregister_read.io.iss_uops[0].pdst, iss_uops[0].pdst connect iregister_read.io.iss_uops[0].rxq_idx, iss_uops[0].rxq_idx connect iregister_read.io.iss_uops[0].stq_idx, iss_uops[0].stq_idx connect iregister_read.io.iss_uops[0].ldq_idx, iss_uops[0].ldq_idx connect iregister_read.io.iss_uops[0].rob_idx, iss_uops[0].rob_idx connect iregister_read.io.iss_uops[0].csr_addr, iss_uops[0].csr_addr connect iregister_read.io.iss_uops[0].imm_packed, iss_uops[0].imm_packed connect iregister_read.io.iss_uops[0].taken, iss_uops[0].taken connect iregister_read.io.iss_uops[0].pc_lob, iss_uops[0].pc_lob connect iregister_read.io.iss_uops[0].edge_inst, iss_uops[0].edge_inst connect iregister_read.io.iss_uops[0].ftq_idx, iss_uops[0].ftq_idx connect iregister_read.io.iss_uops[0].br_tag, iss_uops[0].br_tag connect iregister_read.io.iss_uops[0].br_mask, iss_uops[0].br_mask connect iregister_read.io.iss_uops[0].is_sfb, iss_uops[0].is_sfb connect iregister_read.io.iss_uops[0].is_jal, iss_uops[0].is_jal connect iregister_read.io.iss_uops[0].is_jalr, iss_uops[0].is_jalr connect iregister_read.io.iss_uops[0].is_br, iss_uops[0].is_br connect iregister_read.io.iss_uops[0].iw_p2_poisoned, iss_uops[0].iw_p2_poisoned connect iregister_read.io.iss_uops[0].iw_p1_poisoned, iss_uops[0].iw_p1_poisoned connect iregister_read.io.iss_uops[0].iw_state, iss_uops[0].iw_state connect iregister_read.io.iss_uops[0].ctrl.is_std, iss_uops[0].ctrl.is_std connect iregister_read.io.iss_uops[0].ctrl.is_sta, iss_uops[0].ctrl.is_sta connect iregister_read.io.iss_uops[0].ctrl.is_load, iss_uops[0].ctrl.is_load connect iregister_read.io.iss_uops[0].ctrl.csr_cmd, iss_uops[0].ctrl.csr_cmd connect iregister_read.io.iss_uops[0].ctrl.fcn_dw, iss_uops[0].ctrl.fcn_dw connect iregister_read.io.iss_uops[0].ctrl.op_fcn, iss_uops[0].ctrl.op_fcn connect iregister_read.io.iss_uops[0].ctrl.imm_sel, iss_uops[0].ctrl.imm_sel connect iregister_read.io.iss_uops[0].ctrl.op2_sel, iss_uops[0].ctrl.op2_sel connect iregister_read.io.iss_uops[0].ctrl.op1_sel, iss_uops[0].ctrl.op1_sel connect iregister_read.io.iss_uops[0].ctrl.br_type, iss_uops[0].ctrl.br_type connect iregister_read.io.iss_uops[0].fu_code, iss_uops[0].fu_code connect iregister_read.io.iss_uops[0].iq_type, iss_uops[0].iq_type connect iregister_read.io.iss_uops[0].debug_pc, iss_uops[0].debug_pc connect iregister_read.io.iss_uops[0].is_rvc, iss_uops[0].is_rvc connect iregister_read.io.iss_uops[0].debug_inst, iss_uops[0].debug_inst connect iregister_read.io.iss_uops[0].inst, iss_uops[0].inst connect iregister_read.io.iss_uops[0].uopc, iss_uops[0].uopc connect iregister_read.io.iss_uops[1].debug_tsrc, iss_uops[1].debug_tsrc connect iregister_read.io.iss_uops[1].debug_fsrc, iss_uops[1].debug_fsrc connect iregister_read.io.iss_uops[1].bp_xcpt_if, iss_uops[1].bp_xcpt_if connect iregister_read.io.iss_uops[1].bp_debug_if, iss_uops[1].bp_debug_if connect iregister_read.io.iss_uops[1].xcpt_ma_if, iss_uops[1].xcpt_ma_if connect iregister_read.io.iss_uops[1].xcpt_ae_if, iss_uops[1].xcpt_ae_if connect iregister_read.io.iss_uops[1].xcpt_pf_if, iss_uops[1].xcpt_pf_if connect iregister_read.io.iss_uops[1].fp_single, iss_uops[1].fp_single connect iregister_read.io.iss_uops[1].fp_val, iss_uops[1].fp_val connect iregister_read.io.iss_uops[1].frs3_en, iss_uops[1].frs3_en connect iregister_read.io.iss_uops[1].lrs2_rtype, iss_uops[1].lrs2_rtype connect iregister_read.io.iss_uops[1].lrs1_rtype, iss_uops[1].lrs1_rtype connect iregister_read.io.iss_uops[1].dst_rtype, iss_uops[1].dst_rtype connect iregister_read.io.iss_uops[1].ldst_val, iss_uops[1].ldst_val connect iregister_read.io.iss_uops[1].lrs3, iss_uops[1].lrs3 connect iregister_read.io.iss_uops[1].lrs2, iss_uops[1].lrs2 connect iregister_read.io.iss_uops[1].lrs1, iss_uops[1].lrs1 connect iregister_read.io.iss_uops[1].ldst, iss_uops[1].ldst connect iregister_read.io.iss_uops[1].ldst_is_rs1, iss_uops[1].ldst_is_rs1 connect iregister_read.io.iss_uops[1].flush_on_commit, iss_uops[1].flush_on_commit connect iregister_read.io.iss_uops[1].is_unique, iss_uops[1].is_unique connect iregister_read.io.iss_uops[1].is_sys_pc2epc, iss_uops[1].is_sys_pc2epc connect iregister_read.io.iss_uops[1].uses_stq, iss_uops[1].uses_stq connect iregister_read.io.iss_uops[1].uses_ldq, iss_uops[1].uses_ldq connect iregister_read.io.iss_uops[1].is_amo, iss_uops[1].is_amo connect iregister_read.io.iss_uops[1].is_fencei, iss_uops[1].is_fencei connect iregister_read.io.iss_uops[1].is_fence, iss_uops[1].is_fence connect iregister_read.io.iss_uops[1].mem_signed, iss_uops[1].mem_signed connect iregister_read.io.iss_uops[1].mem_size, iss_uops[1].mem_size connect iregister_read.io.iss_uops[1].mem_cmd, iss_uops[1].mem_cmd connect iregister_read.io.iss_uops[1].bypassable, iss_uops[1].bypassable connect iregister_read.io.iss_uops[1].exc_cause, iss_uops[1].exc_cause connect iregister_read.io.iss_uops[1].exception, iss_uops[1].exception connect iregister_read.io.iss_uops[1].stale_pdst, iss_uops[1].stale_pdst connect iregister_read.io.iss_uops[1].ppred_busy, iss_uops[1].ppred_busy connect iregister_read.io.iss_uops[1].prs3_busy, iss_uops[1].prs3_busy connect iregister_read.io.iss_uops[1].prs2_busy, iss_uops[1].prs2_busy connect iregister_read.io.iss_uops[1].prs1_busy, iss_uops[1].prs1_busy connect iregister_read.io.iss_uops[1].ppred, iss_uops[1].ppred connect iregister_read.io.iss_uops[1].prs3, iss_uops[1].prs3 connect iregister_read.io.iss_uops[1].prs2, iss_uops[1].prs2 connect iregister_read.io.iss_uops[1].prs1, iss_uops[1].prs1 connect iregister_read.io.iss_uops[1].pdst, iss_uops[1].pdst connect iregister_read.io.iss_uops[1].rxq_idx, iss_uops[1].rxq_idx connect iregister_read.io.iss_uops[1].stq_idx, iss_uops[1].stq_idx connect iregister_read.io.iss_uops[1].ldq_idx, iss_uops[1].ldq_idx connect iregister_read.io.iss_uops[1].rob_idx, iss_uops[1].rob_idx connect iregister_read.io.iss_uops[1].csr_addr, iss_uops[1].csr_addr connect iregister_read.io.iss_uops[1].imm_packed, iss_uops[1].imm_packed connect iregister_read.io.iss_uops[1].taken, iss_uops[1].taken connect iregister_read.io.iss_uops[1].pc_lob, iss_uops[1].pc_lob connect iregister_read.io.iss_uops[1].edge_inst, iss_uops[1].edge_inst connect iregister_read.io.iss_uops[1].ftq_idx, iss_uops[1].ftq_idx connect iregister_read.io.iss_uops[1].br_tag, iss_uops[1].br_tag connect iregister_read.io.iss_uops[1].br_mask, iss_uops[1].br_mask connect iregister_read.io.iss_uops[1].is_sfb, iss_uops[1].is_sfb connect iregister_read.io.iss_uops[1].is_jal, iss_uops[1].is_jal connect iregister_read.io.iss_uops[1].is_jalr, iss_uops[1].is_jalr connect iregister_read.io.iss_uops[1].is_br, iss_uops[1].is_br connect iregister_read.io.iss_uops[1].iw_p2_poisoned, iss_uops[1].iw_p2_poisoned connect iregister_read.io.iss_uops[1].iw_p1_poisoned, iss_uops[1].iw_p1_poisoned connect iregister_read.io.iss_uops[1].iw_state, iss_uops[1].iw_state connect iregister_read.io.iss_uops[1].ctrl.is_std, iss_uops[1].ctrl.is_std connect iregister_read.io.iss_uops[1].ctrl.is_sta, iss_uops[1].ctrl.is_sta connect iregister_read.io.iss_uops[1].ctrl.is_load, iss_uops[1].ctrl.is_load connect iregister_read.io.iss_uops[1].ctrl.csr_cmd, iss_uops[1].ctrl.csr_cmd connect iregister_read.io.iss_uops[1].ctrl.fcn_dw, iss_uops[1].ctrl.fcn_dw connect iregister_read.io.iss_uops[1].ctrl.op_fcn, iss_uops[1].ctrl.op_fcn connect iregister_read.io.iss_uops[1].ctrl.imm_sel, iss_uops[1].ctrl.imm_sel connect iregister_read.io.iss_uops[1].ctrl.op2_sel, iss_uops[1].ctrl.op2_sel connect iregister_read.io.iss_uops[1].ctrl.op1_sel, iss_uops[1].ctrl.op1_sel connect iregister_read.io.iss_uops[1].ctrl.br_type, iss_uops[1].ctrl.br_type connect iregister_read.io.iss_uops[1].fu_code, iss_uops[1].fu_code connect iregister_read.io.iss_uops[1].iq_type, iss_uops[1].iq_type connect iregister_read.io.iss_uops[1].debug_pc, iss_uops[1].debug_pc connect iregister_read.io.iss_uops[1].is_rvc, iss_uops[1].is_rvc connect iregister_read.io.iss_uops[1].debug_inst, iss_uops[1].debug_inst connect iregister_read.io.iss_uops[1].inst, iss_uops[1].inst connect iregister_read.io.iss_uops[1].uopc, iss_uops[1].uopc connect iregister_read.io.iss_uops[2].debug_tsrc, iss_uops[2].debug_tsrc connect iregister_read.io.iss_uops[2].debug_fsrc, iss_uops[2].debug_fsrc connect iregister_read.io.iss_uops[2].bp_xcpt_if, iss_uops[2].bp_xcpt_if connect iregister_read.io.iss_uops[2].bp_debug_if, iss_uops[2].bp_debug_if connect iregister_read.io.iss_uops[2].xcpt_ma_if, iss_uops[2].xcpt_ma_if connect iregister_read.io.iss_uops[2].xcpt_ae_if, iss_uops[2].xcpt_ae_if connect iregister_read.io.iss_uops[2].xcpt_pf_if, iss_uops[2].xcpt_pf_if connect iregister_read.io.iss_uops[2].fp_single, iss_uops[2].fp_single connect iregister_read.io.iss_uops[2].fp_val, iss_uops[2].fp_val connect iregister_read.io.iss_uops[2].frs3_en, iss_uops[2].frs3_en connect iregister_read.io.iss_uops[2].lrs2_rtype, iss_uops[2].lrs2_rtype connect iregister_read.io.iss_uops[2].lrs1_rtype, iss_uops[2].lrs1_rtype connect iregister_read.io.iss_uops[2].dst_rtype, iss_uops[2].dst_rtype connect iregister_read.io.iss_uops[2].ldst_val, iss_uops[2].ldst_val connect iregister_read.io.iss_uops[2].lrs3, iss_uops[2].lrs3 connect iregister_read.io.iss_uops[2].lrs2, iss_uops[2].lrs2 connect iregister_read.io.iss_uops[2].lrs1, iss_uops[2].lrs1 connect iregister_read.io.iss_uops[2].ldst, iss_uops[2].ldst connect iregister_read.io.iss_uops[2].ldst_is_rs1, iss_uops[2].ldst_is_rs1 connect iregister_read.io.iss_uops[2].flush_on_commit, iss_uops[2].flush_on_commit connect iregister_read.io.iss_uops[2].is_unique, iss_uops[2].is_unique connect iregister_read.io.iss_uops[2].is_sys_pc2epc, iss_uops[2].is_sys_pc2epc connect iregister_read.io.iss_uops[2].uses_stq, iss_uops[2].uses_stq connect iregister_read.io.iss_uops[2].uses_ldq, iss_uops[2].uses_ldq connect iregister_read.io.iss_uops[2].is_amo, iss_uops[2].is_amo connect iregister_read.io.iss_uops[2].is_fencei, iss_uops[2].is_fencei connect iregister_read.io.iss_uops[2].is_fence, iss_uops[2].is_fence connect iregister_read.io.iss_uops[2].mem_signed, iss_uops[2].mem_signed connect iregister_read.io.iss_uops[2].mem_size, iss_uops[2].mem_size connect iregister_read.io.iss_uops[2].mem_cmd, iss_uops[2].mem_cmd connect iregister_read.io.iss_uops[2].bypassable, iss_uops[2].bypassable connect iregister_read.io.iss_uops[2].exc_cause, iss_uops[2].exc_cause connect iregister_read.io.iss_uops[2].exception, iss_uops[2].exception connect iregister_read.io.iss_uops[2].stale_pdst, iss_uops[2].stale_pdst connect iregister_read.io.iss_uops[2].ppred_busy, iss_uops[2].ppred_busy connect iregister_read.io.iss_uops[2].prs3_busy, iss_uops[2].prs3_busy connect iregister_read.io.iss_uops[2].prs2_busy, iss_uops[2].prs2_busy connect iregister_read.io.iss_uops[2].prs1_busy, iss_uops[2].prs1_busy connect iregister_read.io.iss_uops[2].ppred, iss_uops[2].ppred connect iregister_read.io.iss_uops[2].prs3, iss_uops[2].prs3 connect iregister_read.io.iss_uops[2].prs2, iss_uops[2].prs2 connect iregister_read.io.iss_uops[2].prs1, iss_uops[2].prs1 connect iregister_read.io.iss_uops[2].pdst, iss_uops[2].pdst connect iregister_read.io.iss_uops[2].rxq_idx, iss_uops[2].rxq_idx connect iregister_read.io.iss_uops[2].stq_idx, iss_uops[2].stq_idx connect iregister_read.io.iss_uops[2].ldq_idx, iss_uops[2].ldq_idx connect iregister_read.io.iss_uops[2].rob_idx, iss_uops[2].rob_idx connect iregister_read.io.iss_uops[2].csr_addr, iss_uops[2].csr_addr connect iregister_read.io.iss_uops[2].imm_packed, iss_uops[2].imm_packed connect iregister_read.io.iss_uops[2].taken, iss_uops[2].taken connect iregister_read.io.iss_uops[2].pc_lob, iss_uops[2].pc_lob connect iregister_read.io.iss_uops[2].edge_inst, iss_uops[2].edge_inst connect iregister_read.io.iss_uops[2].ftq_idx, iss_uops[2].ftq_idx connect iregister_read.io.iss_uops[2].br_tag, iss_uops[2].br_tag connect iregister_read.io.iss_uops[2].br_mask, iss_uops[2].br_mask connect iregister_read.io.iss_uops[2].is_sfb, iss_uops[2].is_sfb connect iregister_read.io.iss_uops[2].is_jal, iss_uops[2].is_jal connect iregister_read.io.iss_uops[2].is_jalr, iss_uops[2].is_jalr connect iregister_read.io.iss_uops[2].is_br, iss_uops[2].is_br connect iregister_read.io.iss_uops[2].iw_p2_poisoned, iss_uops[2].iw_p2_poisoned connect iregister_read.io.iss_uops[2].iw_p1_poisoned, iss_uops[2].iw_p1_poisoned connect iregister_read.io.iss_uops[2].iw_state, iss_uops[2].iw_state connect iregister_read.io.iss_uops[2].ctrl.is_std, iss_uops[2].ctrl.is_std connect iregister_read.io.iss_uops[2].ctrl.is_sta, iss_uops[2].ctrl.is_sta connect iregister_read.io.iss_uops[2].ctrl.is_load, iss_uops[2].ctrl.is_load connect iregister_read.io.iss_uops[2].ctrl.csr_cmd, iss_uops[2].ctrl.csr_cmd connect iregister_read.io.iss_uops[2].ctrl.fcn_dw, iss_uops[2].ctrl.fcn_dw connect iregister_read.io.iss_uops[2].ctrl.op_fcn, iss_uops[2].ctrl.op_fcn connect iregister_read.io.iss_uops[2].ctrl.imm_sel, iss_uops[2].ctrl.imm_sel connect iregister_read.io.iss_uops[2].ctrl.op2_sel, iss_uops[2].ctrl.op2_sel connect iregister_read.io.iss_uops[2].ctrl.op1_sel, iss_uops[2].ctrl.op1_sel connect iregister_read.io.iss_uops[2].ctrl.br_type, iss_uops[2].ctrl.br_type connect iregister_read.io.iss_uops[2].fu_code, iss_uops[2].fu_code connect iregister_read.io.iss_uops[2].iq_type, iss_uops[2].iq_type connect iregister_read.io.iss_uops[2].debug_pc, iss_uops[2].debug_pc connect iregister_read.io.iss_uops[2].is_rvc, iss_uops[2].is_rvc connect iregister_read.io.iss_uops[2].debug_inst, iss_uops[2].debug_inst connect iregister_read.io.iss_uops[2].inst, iss_uops[2].inst connect iregister_read.io.iss_uops[2].uopc, iss_uops[2].uopc connect iregister_read.io.iss_uops[3].debug_tsrc, iss_uops[3].debug_tsrc connect iregister_read.io.iss_uops[3].debug_fsrc, iss_uops[3].debug_fsrc connect iregister_read.io.iss_uops[3].bp_xcpt_if, iss_uops[3].bp_xcpt_if connect iregister_read.io.iss_uops[3].bp_debug_if, iss_uops[3].bp_debug_if connect iregister_read.io.iss_uops[3].xcpt_ma_if, iss_uops[3].xcpt_ma_if connect iregister_read.io.iss_uops[3].xcpt_ae_if, iss_uops[3].xcpt_ae_if connect iregister_read.io.iss_uops[3].xcpt_pf_if, iss_uops[3].xcpt_pf_if connect iregister_read.io.iss_uops[3].fp_single, iss_uops[3].fp_single connect iregister_read.io.iss_uops[3].fp_val, iss_uops[3].fp_val connect iregister_read.io.iss_uops[3].frs3_en, iss_uops[3].frs3_en connect iregister_read.io.iss_uops[3].lrs2_rtype, iss_uops[3].lrs2_rtype connect iregister_read.io.iss_uops[3].lrs1_rtype, iss_uops[3].lrs1_rtype connect iregister_read.io.iss_uops[3].dst_rtype, iss_uops[3].dst_rtype connect iregister_read.io.iss_uops[3].ldst_val, iss_uops[3].ldst_val connect iregister_read.io.iss_uops[3].lrs3, iss_uops[3].lrs3 connect iregister_read.io.iss_uops[3].lrs2, iss_uops[3].lrs2 connect iregister_read.io.iss_uops[3].lrs1, iss_uops[3].lrs1 connect iregister_read.io.iss_uops[3].ldst, iss_uops[3].ldst connect iregister_read.io.iss_uops[3].ldst_is_rs1, iss_uops[3].ldst_is_rs1 connect iregister_read.io.iss_uops[3].flush_on_commit, iss_uops[3].flush_on_commit connect iregister_read.io.iss_uops[3].is_unique, iss_uops[3].is_unique connect iregister_read.io.iss_uops[3].is_sys_pc2epc, iss_uops[3].is_sys_pc2epc connect iregister_read.io.iss_uops[3].uses_stq, iss_uops[3].uses_stq connect iregister_read.io.iss_uops[3].uses_ldq, iss_uops[3].uses_ldq connect iregister_read.io.iss_uops[3].is_amo, iss_uops[3].is_amo connect iregister_read.io.iss_uops[3].is_fencei, iss_uops[3].is_fencei connect iregister_read.io.iss_uops[3].is_fence, iss_uops[3].is_fence connect iregister_read.io.iss_uops[3].mem_signed, iss_uops[3].mem_signed connect iregister_read.io.iss_uops[3].mem_size, iss_uops[3].mem_size connect iregister_read.io.iss_uops[3].mem_cmd, iss_uops[3].mem_cmd connect iregister_read.io.iss_uops[3].bypassable, iss_uops[3].bypassable connect iregister_read.io.iss_uops[3].exc_cause, iss_uops[3].exc_cause connect iregister_read.io.iss_uops[3].exception, iss_uops[3].exception connect iregister_read.io.iss_uops[3].stale_pdst, iss_uops[3].stale_pdst connect iregister_read.io.iss_uops[3].ppred_busy, iss_uops[3].ppred_busy connect iregister_read.io.iss_uops[3].prs3_busy, iss_uops[3].prs3_busy connect iregister_read.io.iss_uops[3].prs2_busy, iss_uops[3].prs2_busy connect iregister_read.io.iss_uops[3].prs1_busy, iss_uops[3].prs1_busy connect iregister_read.io.iss_uops[3].ppred, iss_uops[3].ppred connect iregister_read.io.iss_uops[3].prs3, iss_uops[3].prs3 connect iregister_read.io.iss_uops[3].prs2, iss_uops[3].prs2 connect iregister_read.io.iss_uops[3].prs1, iss_uops[3].prs1 connect iregister_read.io.iss_uops[3].pdst, iss_uops[3].pdst connect iregister_read.io.iss_uops[3].rxq_idx, iss_uops[3].rxq_idx connect iregister_read.io.iss_uops[3].stq_idx, iss_uops[3].stq_idx connect iregister_read.io.iss_uops[3].ldq_idx, iss_uops[3].ldq_idx connect iregister_read.io.iss_uops[3].rob_idx, iss_uops[3].rob_idx connect iregister_read.io.iss_uops[3].csr_addr, iss_uops[3].csr_addr connect iregister_read.io.iss_uops[3].imm_packed, iss_uops[3].imm_packed connect iregister_read.io.iss_uops[3].taken, iss_uops[3].taken connect iregister_read.io.iss_uops[3].pc_lob, iss_uops[3].pc_lob connect iregister_read.io.iss_uops[3].edge_inst, iss_uops[3].edge_inst connect iregister_read.io.iss_uops[3].ftq_idx, iss_uops[3].ftq_idx connect iregister_read.io.iss_uops[3].br_tag, iss_uops[3].br_tag connect iregister_read.io.iss_uops[3].br_mask, iss_uops[3].br_mask connect iregister_read.io.iss_uops[3].is_sfb, iss_uops[3].is_sfb connect iregister_read.io.iss_uops[3].is_jal, iss_uops[3].is_jal connect iregister_read.io.iss_uops[3].is_jalr, iss_uops[3].is_jalr connect iregister_read.io.iss_uops[3].is_br, iss_uops[3].is_br connect iregister_read.io.iss_uops[3].iw_p2_poisoned, iss_uops[3].iw_p2_poisoned connect iregister_read.io.iss_uops[3].iw_p1_poisoned, iss_uops[3].iw_p1_poisoned connect iregister_read.io.iss_uops[3].iw_state, iss_uops[3].iw_state connect iregister_read.io.iss_uops[3].ctrl.is_std, iss_uops[3].ctrl.is_std connect iregister_read.io.iss_uops[3].ctrl.is_sta, iss_uops[3].ctrl.is_sta connect iregister_read.io.iss_uops[3].ctrl.is_load, iss_uops[3].ctrl.is_load connect iregister_read.io.iss_uops[3].ctrl.csr_cmd, iss_uops[3].ctrl.csr_cmd connect iregister_read.io.iss_uops[3].ctrl.fcn_dw, iss_uops[3].ctrl.fcn_dw connect iregister_read.io.iss_uops[3].ctrl.op_fcn, iss_uops[3].ctrl.op_fcn connect iregister_read.io.iss_uops[3].ctrl.imm_sel, iss_uops[3].ctrl.imm_sel connect iregister_read.io.iss_uops[3].ctrl.op2_sel, iss_uops[3].ctrl.op2_sel connect iregister_read.io.iss_uops[3].ctrl.op1_sel, iss_uops[3].ctrl.op1_sel connect iregister_read.io.iss_uops[3].ctrl.br_type, iss_uops[3].ctrl.br_type connect iregister_read.io.iss_uops[3].fu_code, iss_uops[3].fu_code connect iregister_read.io.iss_uops[3].iq_type, iss_uops[3].iq_type connect iregister_read.io.iss_uops[3].debug_pc, iss_uops[3].debug_pc connect iregister_read.io.iss_uops[3].is_rvc, iss_uops[3].is_rvc connect iregister_read.io.iss_uops[3].debug_inst, iss_uops[3].debug_inst connect iregister_read.io.iss_uops[3].inst, iss_uops[3].inst connect iregister_read.io.iss_uops[3].uopc, iss_uops[3].uopc connect iregister_read.io.iss_uops[0].iw_p1_poisoned, UInt<1>(0h0) connect iregister_read.io.iss_uops[0].iw_p2_poisoned, UInt<1>(0h0) connect iregister_read.io.iss_uops[1].iw_p1_poisoned, UInt<1>(0h0) connect iregister_read.io.iss_uops[1].iw_p2_poisoned, UInt<1>(0h0) connect iregister_read.io.iss_uops[2].iw_p1_poisoned, UInt<1>(0h0) connect iregister_read.io.iss_uops[2].iw_p2_poisoned, UInt<1>(0h0) connect iregister_read.io.iss_uops[3].iw_p1_poisoned, UInt<1>(0h0) connect iregister_read.io.iss_uops[3].iw_p2_poisoned, UInt<1>(0h0) connect iregister_read.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect iregister_read.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect iregister_read.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect iregister_read.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect iregister_read.io.brupdate.b2.taken, brupdate.b2.taken connect iregister_read.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect iregister_read.io.brupdate.b2.valid, brupdate.b2.valid connect iregister_read.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect iregister_read.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect iregister_read.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect iregister_read.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect iregister_read.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect iregister_read.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect iregister_read.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect iregister_read.io.brupdate.b2.uop.fp_single, brupdate.b2.uop.fp_single connect iregister_read.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect iregister_read.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect iregister_read.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect iregister_read.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect iregister_read.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect iregister_read.io.brupdate.b2.uop.ldst_val, brupdate.b2.uop.ldst_val connect iregister_read.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect iregister_read.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect iregister_read.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect iregister_read.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect iregister_read.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect iregister_read.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect iregister_read.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect iregister_read.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect iregister_read.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect iregister_read.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect iregister_read.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect iregister_read.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect iregister_read.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect iregister_read.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect iregister_read.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect iregister_read.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect iregister_read.io.brupdate.b2.uop.bypassable, brupdate.b2.uop.bypassable connect iregister_read.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect iregister_read.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect iregister_read.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect iregister_read.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect iregister_read.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect iregister_read.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect iregister_read.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect iregister_read.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect iregister_read.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect iregister_read.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect iregister_read.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect iregister_read.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect iregister_read.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect iregister_read.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect iregister_read.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect iregister_read.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect iregister_read.io.brupdate.b2.uop.csr_addr, brupdate.b2.uop.csr_addr connect iregister_read.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect iregister_read.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect iregister_read.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect iregister_read.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect iregister_read.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect iregister_read.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect iregister_read.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect iregister_read.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect iregister_read.io.brupdate.b2.uop.is_jal, brupdate.b2.uop.is_jal connect iregister_read.io.brupdate.b2.uop.is_jalr, brupdate.b2.uop.is_jalr connect iregister_read.io.brupdate.b2.uop.is_br, brupdate.b2.uop.is_br connect iregister_read.io.brupdate.b2.uop.iw_p2_poisoned, brupdate.b2.uop.iw_p2_poisoned connect iregister_read.io.brupdate.b2.uop.iw_p1_poisoned, brupdate.b2.uop.iw_p1_poisoned connect iregister_read.io.brupdate.b2.uop.iw_state, brupdate.b2.uop.iw_state connect iregister_read.io.brupdate.b2.uop.ctrl.is_std, brupdate.b2.uop.ctrl.is_std connect iregister_read.io.brupdate.b2.uop.ctrl.is_sta, brupdate.b2.uop.ctrl.is_sta connect iregister_read.io.brupdate.b2.uop.ctrl.is_load, brupdate.b2.uop.ctrl.is_load connect iregister_read.io.brupdate.b2.uop.ctrl.csr_cmd, brupdate.b2.uop.ctrl.csr_cmd connect iregister_read.io.brupdate.b2.uop.ctrl.fcn_dw, brupdate.b2.uop.ctrl.fcn_dw connect iregister_read.io.brupdate.b2.uop.ctrl.op_fcn, brupdate.b2.uop.ctrl.op_fcn connect iregister_read.io.brupdate.b2.uop.ctrl.imm_sel, brupdate.b2.uop.ctrl.imm_sel connect iregister_read.io.brupdate.b2.uop.ctrl.op2_sel, brupdate.b2.uop.ctrl.op2_sel connect iregister_read.io.brupdate.b2.uop.ctrl.op1_sel, brupdate.b2.uop.ctrl.op1_sel connect iregister_read.io.brupdate.b2.uop.ctrl.br_type, brupdate.b2.uop.ctrl.br_type connect iregister_read.io.brupdate.b2.uop.fu_code, brupdate.b2.uop.fu_code connect iregister_read.io.brupdate.b2.uop.iq_type, brupdate.b2.uop.iq_type connect iregister_read.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect iregister_read.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect iregister_read.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect iregister_read.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect iregister_read.io.brupdate.b2.uop.uopc, brupdate.b2.uop.uopc connect iregister_read.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect iregister_read.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask reg iregister_read_io_kill_REG : UInt<1>, clock connect iregister_read_io_kill_REG, rob.io.flush.valid connect iregister_read.io.kill, iregister_read_io_kill_REG connect iregister_read.io.bypass[0].bits.fflags.bits.flags, bypasses[0].bits.fflags.bits.flags connect iregister_read.io.bypass[0].bits.fflags.bits.uop.debug_tsrc, bypasses[0].bits.fflags.bits.uop.debug_tsrc connect iregister_read.io.bypass[0].bits.fflags.bits.uop.debug_fsrc, bypasses[0].bits.fflags.bits.uop.debug_fsrc connect iregister_read.io.bypass[0].bits.fflags.bits.uop.bp_xcpt_if, bypasses[0].bits.fflags.bits.uop.bp_xcpt_if connect iregister_read.io.bypass[0].bits.fflags.bits.uop.bp_debug_if, bypasses[0].bits.fflags.bits.uop.bp_debug_if connect iregister_read.io.bypass[0].bits.fflags.bits.uop.xcpt_ma_if, bypasses[0].bits.fflags.bits.uop.xcpt_ma_if connect iregister_read.io.bypass[0].bits.fflags.bits.uop.xcpt_ae_if, bypasses[0].bits.fflags.bits.uop.xcpt_ae_if connect iregister_read.io.bypass[0].bits.fflags.bits.uop.xcpt_pf_if, bypasses[0].bits.fflags.bits.uop.xcpt_pf_if connect iregister_read.io.bypass[0].bits.fflags.bits.uop.fp_single, bypasses[0].bits.fflags.bits.uop.fp_single connect iregister_read.io.bypass[0].bits.fflags.bits.uop.fp_val, bypasses[0].bits.fflags.bits.uop.fp_val connect iregister_read.io.bypass[0].bits.fflags.bits.uop.frs3_en, bypasses[0].bits.fflags.bits.uop.frs3_en connect iregister_read.io.bypass[0].bits.fflags.bits.uop.lrs2_rtype, bypasses[0].bits.fflags.bits.uop.lrs2_rtype connect iregister_read.io.bypass[0].bits.fflags.bits.uop.lrs1_rtype, bypasses[0].bits.fflags.bits.uop.lrs1_rtype connect iregister_read.io.bypass[0].bits.fflags.bits.uop.dst_rtype, bypasses[0].bits.fflags.bits.uop.dst_rtype connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ldst_val, bypasses[0].bits.fflags.bits.uop.ldst_val connect iregister_read.io.bypass[0].bits.fflags.bits.uop.lrs3, bypasses[0].bits.fflags.bits.uop.lrs3 connect iregister_read.io.bypass[0].bits.fflags.bits.uop.lrs2, bypasses[0].bits.fflags.bits.uop.lrs2 connect iregister_read.io.bypass[0].bits.fflags.bits.uop.lrs1, bypasses[0].bits.fflags.bits.uop.lrs1 connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ldst, bypasses[0].bits.fflags.bits.uop.ldst connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ldst_is_rs1, bypasses[0].bits.fflags.bits.uop.ldst_is_rs1 connect iregister_read.io.bypass[0].bits.fflags.bits.uop.flush_on_commit, bypasses[0].bits.fflags.bits.uop.flush_on_commit connect iregister_read.io.bypass[0].bits.fflags.bits.uop.is_unique, bypasses[0].bits.fflags.bits.uop.is_unique connect iregister_read.io.bypass[0].bits.fflags.bits.uop.is_sys_pc2epc, bypasses[0].bits.fflags.bits.uop.is_sys_pc2epc connect iregister_read.io.bypass[0].bits.fflags.bits.uop.uses_stq, bypasses[0].bits.fflags.bits.uop.uses_stq connect iregister_read.io.bypass[0].bits.fflags.bits.uop.uses_ldq, bypasses[0].bits.fflags.bits.uop.uses_ldq connect iregister_read.io.bypass[0].bits.fflags.bits.uop.is_amo, bypasses[0].bits.fflags.bits.uop.is_amo connect iregister_read.io.bypass[0].bits.fflags.bits.uop.is_fencei, bypasses[0].bits.fflags.bits.uop.is_fencei connect iregister_read.io.bypass[0].bits.fflags.bits.uop.is_fence, bypasses[0].bits.fflags.bits.uop.is_fence connect iregister_read.io.bypass[0].bits.fflags.bits.uop.mem_signed, bypasses[0].bits.fflags.bits.uop.mem_signed connect iregister_read.io.bypass[0].bits.fflags.bits.uop.mem_size, bypasses[0].bits.fflags.bits.uop.mem_size connect iregister_read.io.bypass[0].bits.fflags.bits.uop.mem_cmd, bypasses[0].bits.fflags.bits.uop.mem_cmd connect iregister_read.io.bypass[0].bits.fflags.bits.uop.bypassable, bypasses[0].bits.fflags.bits.uop.bypassable connect iregister_read.io.bypass[0].bits.fflags.bits.uop.exc_cause, bypasses[0].bits.fflags.bits.uop.exc_cause connect iregister_read.io.bypass[0].bits.fflags.bits.uop.exception, bypasses[0].bits.fflags.bits.uop.exception connect iregister_read.io.bypass[0].bits.fflags.bits.uop.stale_pdst, bypasses[0].bits.fflags.bits.uop.stale_pdst connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ppred_busy, bypasses[0].bits.fflags.bits.uop.ppred_busy connect iregister_read.io.bypass[0].bits.fflags.bits.uop.prs3_busy, bypasses[0].bits.fflags.bits.uop.prs3_busy connect iregister_read.io.bypass[0].bits.fflags.bits.uop.prs2_busy, bypasses[0].bits.fflags.bits.uop.prs2_busy connect iregister_read.io.bypass[0].bits.fflags.bits.uop.prs1_busy, bypasses[0].bits.fflags.bits.uop.prs1_busy connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ppred, bypasses[0].bits.fflags.bits.uop.ppred connect iregister_read.io.bypass[0].bits.fflags.bits.uop.prs3, bypasses[0].bits.fflags.bits.uop.prs3 connect iregister_read.io.bypass[0].bits.fflags.bits.uop.prs2, bypasses[0].bits.fflags.bits.uop.prs2 connect iregister_read.io.bypass[0].bits.fflags.bits.uop.prs1, bypasses[0].bits.fflags.bits.uop.prs1 connect iregister_read.io.bypass[0].bits.fflags.bits.uop.pdst, bypasses[0].bits.fflags.bits.uop.pdst connect iregister_read.io.bypass[0].bits.fflags.bits.uop.rxq_idx, bypasses[0].bits.fflags.bits.uop.rxq_idx connect iregister_read.io.bypass[0].bits.fflags.bits.uop.stq_idx, bypasses[0].bits.fflags.bits.uop.stq_idx connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ldq_idx, bypasses[0].bits.fflags.bits.uop.ldq_idx connect iregister_read.io.bypass[0].bits.fflags.bits.uop.rob_idx, bypasses[0].bits.fflags.bits.uop.rob_idx connect iregister_read.io.bypass[0].bits.fflags.bits.uop.csr_addr, bypasses[0].bits.fflags.bits.uop.csr_addr connect iregister_read.io.bypass[0].bits.fflags.bits.uop.imm_packed, bypasses[0].bits.fflags.bits.uop.imm_packed connect iregister_read.io.bypass[0].bits.fflags.bits.uop.taken, bypasses[0].bits.fflags.bits.uop.taken connect iregister_read.io.bypass[0].bits.fflags.bits.uop.pc_lob, bypasses[0].bits.fflags.bits.uop.pc_lob connect iregister_read.io.bypass[0].bits.fflags.bits.uop.edge_inst, bypasses[0].bits.fflags.bits.uop.edge_inst connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ftq_idx, bypasses[0].bits.fflags.bits.uop.ftq_idx connect iregister_read.io.bypass[0].bits.fflags.bits.uop.br_tag, bypasses[0].bits.fflags.bits.uop.br_tag connect iregister_read.io.bypass[0].bits.fflags.bits.uop.br_mask, bypasses[0].bits.fflags.bits.uop.br_mask connect iregister_read.io.bypass[0].bits.fflags.bits.uop.is_sfb, bypasses[0].bits.fflags.bits.uop.is_sfb connect iregister_read.io.bypass[0].bits.fflags.bits.uop.is_jal, bypasses[0].bits.fflags.bits.uop.is_jal connect iregister_read.io.bypass[0].bits.fflags.bits.uop.is_jalr, bypasses[0].bits.fflags.bits.uop.is_jalr connect iregister_read.io.bypass[0].bits.fflags.bits.uop.is_br, bypasses[0].bits.fflags.bits.uop.is_br connect iregister_read.io.bypass[0].bits.fflags.bits.uop.iw_p2_poisoned, bypasses[0].bits.fflags.bits.uop.iw_p2_poisoned connect iregister_read.io.bypass[0].bits.fflags.bits.uop.iw_p1_poisoned, bypasses[0].bits.fflags.bits.uop.iw_p1_poisoned connect iregister_read.io.bypass[0].bits.fflags.bits.uop.iw_state, bypasses[0].bits.fflags.bits.uop.iw_state connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ctrl.is_std, bypasses[0].bits.fflags.bits.uop.ctrl.is_std connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ctrl.is_sta, bypasses[0].bits.fflags.bits.uop.ctrl.is_sta connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ctrl.is_load, bypasses[0].bits.fflags.bits.uop.ctrl.is_load connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ctrl.csr_cmd, bypasses[0].bits.fflags.bits.uop.ctrl.csr_cmd connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ctrl.fcn_dw, bypasses[0].bits.fflags.bits.uop.ctrl.fcn_dw connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ctrl.op_fcn, bypasses[0].bits.fflags.bits.uop.ctrl.op_fcn connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ctrl.imm_sel, bypasses[0].bits.fflags.bits.uop.ctrl.imm_sel connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ctrl.op2_sel, bypasses[0].bits.fflags.bits.uop.ctrl.op2_sel connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ctrl.op1_sel, bypasses[0].bits.fflags.bits.uop.ctrl.op1_sel connect iregister_read.io.bypass[0].bits.fflags.bits.uop.ctrl.br_type, bypasses[0].bits.fflags.bits.uop.ctrl.br_type connect iregister_read.io.bypass[0].bits.fflags.bits.uop.fu_code, bypasses[0].bits.fflags.bits.uop.fu_code connect iregister_read.io.bypass[0].bits.fflags.bits.uop.iq_type, bypasses[0].bits.fflags.bits.uop.iq_type connect iregister_read.io.bypass[0].bits.fflags.bits.uop.debug_pc, bypasses[0].bits.fflags.bits.uop.debug_pc connect iregister_read.io.bypass[0].bits.fflags.bits.uop.is_rvc, bypasses[0].bits.fflags.bits.uop.is_rvc connect iregister_read.io.bypass[0].bits.fflags.bits.uop.debug_inst, bypasses[0].bits.fflags.bits.uop.debug_inst connect iregister_read.io.bypass[0].bits.fflags.bits.uop.inst, bypasses[0].bits.fflags.bits.uop.inst connect iregister_read.io.bypass[0].bits.fflags.bits.uop.uopc, bypasses[0].bits.fflags.bits.uop.uopc connect iregister_read.io.bypass[0].bits.fflags.valid, bypasses[0].bits.fflags.valid connect iregister_read.io.bypass[0].bits.predicated, bypasses[0].bits.predicated connect iregister_read.io.bypass[0].bits.data, bypasses[0].bits.data connect iregister_read.io.bypass[0].bits.uop.debug_tsrc, bypasses[0].bits.uop.debug_tsrc connect iregister_read.io.bypass[0].bits.uop.debug_fsrc, bypasses[0].bits.uop.debug_fsrc connect iregister_read.io.bypass[0].bits.uop.bp_xcpt_if, bypasses[0].bits.uop.bp_xcpt_if connect iregister_read.io.bypass[0].bits.uop.bp_debug_if, bypasses[0].bits.uop.bp_debug_if connect iregister_read.io.bypass[0].bits.uop.xcpt_ma_if, bypasses[0].bits.uop.xcpt_ma_if connect iregister_read.io.bypass[0].bits.uop.xcpt_ae_if, bypasses[0].bits.uop.xcpt_ae_if connect iregister_read.io.bypass[0].bits.uop.xcpt_pf_if, bypasses[0].bits.uop.xcpt_pf_if connect iregister_read.io.bypass[0].bits.uop.fp_single, bypasses[0].bits.uop.fp_single connect iregister_read.io.bypass[0].bits.uop.fp_val, bypasses[0].bits.uop.fp_val connect iregister_read.io.bypass[0].bits.uop.frs3_en, bypasses[0].bits.uop.frs3_en connect iregister_read.io.bypass[0].bits.uop.lrs2_rtype, bypasses[0].bits.uop.lrs2_rtype connect iregister_read.io.bypass[0].bits.uop.lrs1_rtype, bypasses[0].bits.uop.lrs1_rtype connect iregister_read.io.bypass[0].bits.uop.dst_rtype, bypasses[0].bits.uop.dst_rtype connect iregister_read.io.bypass[0].bits.uop.ldst_val, bypasses[0].bits.uop.ldst_val connect iregister_read.io.bypass[0].bits.uop.lrs3, bypasses[0].bits.uop.lrs3 connect iregister_read.io.bypass[0].bits.uop.lrs2, bypasses[0].bits.uop.lrs2 connect iregister_read.io.bypass[0].bits.uop.lrs1, bypasses[0].bits.uop.lrs1 connect iregister_read.io.bypass[0].bits.uop.ldst, bypasses[0].bits.uop.ldst connect iregister_read.io.bypass[0].bits.uop.ldst_is_rs1, bypasses[0].bits.uop.ldst_is_rs1 connect iregister_read.io.bypass[0].bits.uop.flush_on_commit, bypasses[0].bits.uop.flush_on_commit connect iregister_read.io.bypass[0].bits.uop.is_unique, bypasses[0].bits.uop.is_unique connect iregister_read.io.bypass[0].bits.uop.is_sys_pc2epc, bypasses[0].bits.uop.is_sys_pc2epc connect iregister_read.io.bypass[0].bits.uop.uses_stq, bypasses[0].bits.uop.uses_stq connect iregister_read.io.bypass[0].bits.uop.uses_ldq, bypasses[0].bits.uop.uses_ldq connect iregister_read.io.bypass[0].bits.uop.is_amo, bypasses[0].bits.uop.is_amo connect iregister_read.io.bypass[0].bits.uop.is_fencei, bypasses[0].bits.uop.is_fencei connect iregister_read.io.bypass[0].bits.uop.is_fence, bypasses[0].bits.uop.is_fence connect iregister_read.io.bypass[0].bits.uop.mem_signed, bypasses[0].bits.uop.mem_signed connect iregister_read.io.bypass[0].bits.uop.mem_size, bypasses[0].bits.uop.mem_size connect iregister_read.io.bypass[0].bits.uop.mem_cmd, bypasses[0].bits.uop.mem_cmd connect iregister_read.io.bypass[0].bits.uop.bypassable, bypasses[0].bits.uop.bypassable connect iregister_read.io.bypass[0].bits.uop.exc_cause, bypasses[0].bits.uop.exc_cause connect iregister_read.io.bypass[0].bits.uop.exception, bypasses[0].bits.uop.exception connect iregister_read.io.bypass[0].bits.uop.stale_pdst, bypasses[0].bits.uop.stale_pdst connect iregister_read.io.bypass[0].bits.uop.ppred_busy, bypasses[0].bits.uop.ppred_busy connect iregister_read.io.bypass[0].bits.uop.prs3_busy, bypasses[0].bits.uop.prs3_busy connect iregister_read.io.bypass[0].bits.uop.prs2_busy, bypasses[0].bits.uop.prs2_busy connect iregister_read.io.bypass[0].bits.uop.prs1_busy, bypasses[0].bits.uop.prs1_busy connect iregister_read.io.bypass[0].bits.uop.ppred, bypasses[0].bits.uop.ppred connect iregister_read.io.bypass[0].bits.uop.prs3, bypasses[0].bits.uop.prs3 connect iregister_read.io.bypass[0].bits.uop.prs2, bypasses[0].bits.uop.prs2 connect iregister_read.io.bypass[0].bits.uop.prs1, bypasses[0].bits.uop.prs1 connect iregister_read.io.bypass[0].bits.uop.pdst, bypasses[0].bits.uop.pdst connect iregister_read.io.bypass[0].bits.uop.rxq_idx, bypasses[0].bits.uop.rxq_idx connect iregister_read.io.bypass[0].bits.uop.stq_idx, bypasses[0].bits.uop.stq_idx connect iregister_read.io.bypass[0].bits.uop.ldq_idx, bypasses[0].bits.uop.ldq_idx connect iregister_read.io.bypass[0].bits.uop.rob_idx, bypasses[0].bits.uop.rob_idx connect iregister_read.io.bypass[0].bits.uop.csr_addr, bypasses[0].bits.uop.csr_addr connect iregister_read.io.bypass[0].bits.uop.imm_packed, bypasses[0].bits.uop.imm_packed connect iregister_read.io.bypass[0].bits.uop.taken, bypasses[0].bits.uop.taken connect iregister_read.io.bypass[0].bits.uop.pc_lob, bypasses[0].bits.uop.pc_lob connect iregister_read.io.bypass[0].bits.uop.edge_inst, bypasses[0].bits.uop.edge_inst connect iregister_read.io.bypass[0].bits.uop.ftq_idx, bypasses[0].bits.uop.ftq_idx connect iregister_read.io.bypass[0].bits.uop.br_tag, bypasses[0].bits.uop.br_tag connect iregister_read.io.bypass[0].bits.uop.br_mask, bypasses[0].bits.uop.br_mask connect iregister_read.io.bypass[0].bits.uop.is_sfb, bypasses[0].bits.uop.is_sfb connect iregister_read.io.bypass[0].bits.uop.is_jal, bypasses[0].bits.uop.is_jal connect iregister_read.io.bypass[0].bits.uop.is_jalr, bypasses[0].bits.uop.is_jalr connect iregister_read.io.bypass[0].bits.uop.is_br, bypasses[0].bits.uop.is_br connect iregister_read.io.bypass[0].bits.uop.iw_p2_poisoned, bypasses[0].bits.uop.iw_p2_poisoned connect iregister_read.io.bypass[0].bits.uop.iw_p1_poisoned, bypasses[0].bits.uop.iw_p1_poisoned connect iregister_read.io.bypass[0].bits.uop.iw_state, bypasses[0].bits.uop.iw_state connect iregister_read.io.bypass[0].bits.uop.ctrl.is_std, bypasses[0].bits.uop.ctrl.is_std connect iregister_read.io.bypass[0].bits.uop.ctrl.is_sta, bypasses[0].bits.uop.ctrl.is_sta connect iregister_read.io.bypass[0].bits.uop.ctrl.is_load, bypasses[0].bits.uop.ctrl.is_load connect iregister_read.io.bypass[0].bits.uop.ctrl.csr_cmd, bypasses[0].bits.uop.ctrl.csr_cmd connect iregister_read.io.bypass[0].bits.uop.ctrl.fcn_dw, bypasses[0].bits.uop.ctrl.fcn_dw connect iregister_read.io.bypass[0].bits.uop.ctrl.op_fcn, bypasses[0].bits.uop.ctrl.op_fcn connect iregister_read.io.bypass[0].bits.uop.ctrl.imm_sel, bypasses[0].bits.uop.ctrl.imm_sel connect iregister_read.io.bypass[0].bits.uop.ctrl.op2_sel, bypasses[0].bits.uop.ctrl.op2_sel connect iregister_read.io.bypass[0].bits.uop.ctrl.op1_sel, bypasses[0].bits.uop.ctrl.op1_sel connect iregister_read.io.bypass[0].bits.uop.ctrl.br_type, bypasses[0].bits.uop.ctrl.br_type connect iregister_read.io.bypass[0].bits.uop.fu_code, bypasses[0].bits.uop.fu_code connect iregister_read.io.bypass[0].bits.uop.iq_type, bypasses[0].bits.uop.iq_type connect iregister_read.io.bypass[0].bits.uop.debug_pc, bypasses[0].bits.uop.debug_pc connect iregister_read.io.bypass[0].bits.uop.is_rvc, bypasses[0].bits.uop.is_rvc connect iregister_read.io.bypass[0].bits.uop.debug_inst, bypasses[0].bits.uop.debug_inst connect iregister_read.io.bypass[0].bits.uop.inst, bypasses[0].bits.uop.inst connect iregister_read.io.bypass[0].bits.uop.uopc, bypasses[0].bits.uop.uopc connect iregister_read.io.bypass[0].valid, bypasses[0].valid connect iregister_read.io.bypass[1].bits.fflags.bits.flags, bypasses[1].bits.fflags.bits.flags connect iregister_read.io.bypass[1].bits.fflags.bits.uop.debug_tsrc, bypasses[1].bits.fflags.bits.uop.debug_tsrc connect iregister_read.io.bypass[1].bits.fflags.bits.uop.debug_fsrc, bypasses[1].bits.fflags.bits.uop.debug_fsrc connect iregister_read.io.bypass[1].bits.fflags.bits.uop.bp_xcpt_if, bypasses[1].bits.fflags.bits.uop.bp_xcpt_if connect iregister_read.io.bypass[1].bits.fflags.bits.uop.bp_debug_if, bypasses[1].bits.fflags.bits.uop.bp_debug_if connect iregister_read.io.bypass[1].bits.fflags.bits.uop.xcpt_ma_if, bypasses[1].bits.fflags.bits.uop.xcpt_ma_if connect iregister_read.io.bypass[1].bits.fflags.bits.uop.xcpt_ae_if, bypasses[1].bits.fflags.bits.uop.xcpt_ae_if connect iregister_read.io.bypass[1].bits.fflags.bits.uop.xcpt_pf_if, bypasses[1].bits.fflags.bits.uop.xcpt_pf_if connect iregister_read.io.bypass[1].bits.fflags.bits.uop.fp_single, bypasses[1].bits.fflags.bits.uop.fp_single connect iregister_read.io.bypass[1].bits.fflags.bits.uop.fp_val, bypasses[1].bits.fflags.bits.uop.fp_val connect iregister_read.io.bypass[1].bits.fflags.bits.uop.frs3_en, bypasses[1].bits.fflags.bits.uop.frs3_en connect iregister_read.io.bypass[1].bits.fflags.bits.uop.lrs2_rtype, bypasses[1].bits.fflags.bits.uop.lrs2_rtype connect iregister_read.io.bypass[1].bits.fflags.bits.uop.lrs1_rtype, bypasses[1].bits.fflags.bits.uop.lrs1_rtype connect iregister_read.io.bypass[1].bits.fflags.bits.uop.dst_rtype, bypasses[1].bits.fflags.bits.uop.dst_rtype connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ldst_val, bypasses[1].bits.fflags.bits.uop.ldst_val connect iregister_read.io.bypass[1].bits.fflags.bits.uop.lrs3, bypasses[1].bits.fflags.bits.uop.lrs3 connect iregister_read.io.bypass[1].bits.fflags.bits.uop.lrs2, bypasses[1].bits.fflags.bits.uop.lrs2 connect iregister_read.io.bypass[1].bits.fflags.bits.uop.lrs1, bypasses[1].bits.fflags.bits.uop.lrs1 connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ldst, bypasses[1].bits.fflags.bits.uop.ldst connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ldst_is_rs1, bypasses[1].bits.fflags.bits.uop.ldst_is_rs1 connect iregister_read.io.bypass[1].bits.fflags.bits.uop.flush_on_commit, bypasses[1].bits.fflags.bits.uop.flush_on_commit connect iregister_read.io.bypass[1].bits.fflags.bits.uop.is_unique, bypasses[1].bits.fflags.bits.uop.is_unique connect iregister_read.io.bypass[1].bits.fflags.bits.uop.is_sys_pc2epc, bypasses[1].bits.fflags.bits.uop.is_sys_pc2epc connect iregister_read.io.bypass[1].bits.fflags.bits.uop.uses_stq, bypasses[1].bits.fflags.bits.uop.uses_stq connect iregister_read.io.bypass[1].bits.fflags.bits.uop.uses_ldq, bypasses[1].bits.fflags.bits.uop.uses_ldq connect iregister_read.io.bypass[1].bits.fflags.bits.uop.is_amo, bypasses[1].bits.fflags.bits.uop.is_amo connect iregister_read.io.bypass[1].bits.fflags.bits.uop.is_fencei, bypasses[1].bits.fflags.bits.uop.is_fencei connect iregister_read.io.bypass[1].bits.fflags.bits.uop.is_fence, bypasses[1].bits.fflags.bits.uop.is_fence connect iregister_read.io.bypass[1].bits.fflags.bits.uop.mem_signed, bypasses[1].bits.fflags.bits.uop.mem_signed connect iregister_read.io.bypass[1].bits.fflags.bits.uop.mem_size, bypasses[1].bits.fflags.bits.uop.mem_size connect iregister_read.io.bypass[1].bits.fflags.bits.uop.mem_cmd, bypasses[1].bits.fflags.bits.uop.mem_cmd connect iregister_read.io.bypass[1].bits.fflags.bits.uop.bypassable, bypasses[1].bits.fflags.bits.uop.bypassable connect iregister_read.io.bypass[1].bits.fflags.bits.uop.exc_cause, bypasses[1].bits.fflags.bits.uop.exc_cause connect iregister_read.io.bypass[1].bits.fflags.bits.uop.exception, bypasses[1].bits.fflags.bits.uop.exception connect iregister_read.io.bypass[1].bits.fflags.bits.uop.stale_pdst, bypasses[1].bits.fflags.bits.uop.stale_pdst connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ppred_busy, bypasses[1].bits.fflags.bits.uop.ppred_busy connect iregister_read.io.bypass[1].bits.fflags.bits.uop.prs3_busy, bypasses[1].bits.fflags.bits.uop.prs3_busy connect iregister_read.io.bypass[1].bits.fflags.bits.uop.prs2_busy, bypasses[1].bits.fflags.bits.uop.prs2_busy connect iregister_read.io.bypass[1].bits.fflags.bits.uop.prs1_busy, bypasses[1].bits.fflags.bits.uop.prs1_busy connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ppred, bypasses[1].bits.fflags.bits.uop.ppred connect iregister_read.io.bypass[1].bits.fflags.bits.uop.prs3, bypasses[1].bits.fflags.bits.uop.prs3 connect iregister_read.io.bypass[1].bits.fflags.bits.uop.prs2, bypasses[1].bits.fflags.bits.uop.prs2 connect iregister_read.io.bypass[1].bits.fflags.bits.uop.prs1, bypasses[1].bits.fflags.bits.uop.prs1 connect iregister_read.io.bypass[1].bits.fflags.bits.uop.pdst, bypasses[1].bits.fflags.bits.uop.pdst connect iregister_read.io.bypass[1].bits.fflags.bits.uop.rxq_idx, bypasses[1].bits.fflags.bits.uop.rxq_idx connect iregister_read.io.bypass[1].bits.fflags.bits.uop.stq_idx, bypasses[1].bits.fflags.bits.uop.stq_idx connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ldq_idx, bypasses[1].bits.fflags.bits.uop.ldq_idx connect iregister_read.io.bypass[1].bits.fflags.bits.uop.rob_idx, bypasses[1].bits.fflags.bits.uop.rob_idx connect iregister_read.io.bypass[1].bits.fflags.bits.uop.csr_addr, bypasses[1].bits.fflags.bits.uop.csr_addr connect iregister_read.io.bypass[1].bits.fflags.bits.uop.imm_packed, bypasses[1].bits.fflags.bits.uop.imm_packed connect iregister_read.io.bypass[1].bits.fflags.bits.uop.taken, bypasses[1].bits.fflags.bits.uop.taken connect iregister_read.io.bypass[1].bits.fflags.bits.uop.pc_lob, bypasses[1].bits.fflags.bits.uop.pc_lob connect iregister_read.io.bypass[1].bits.fflags.bits.uop.edge_inst, bypasses[1].bits.fflags.bits.uop.edge_inst connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ftq_idx, bypasses[1].bits.fflags.bits.uop.ftq_idx connect iregister_read.io.bypass[1].bits.fflags.bits.uop.br_tag, bypasses[1].bits.fflags.bits.uop.br_tag connect iregister_read.io.bypass[1].bits.fflags.bits.uop.br_mask, bypasses[1].bits.fflags.bits.uop.br_mask connect iregister_read.io.bypass[1].bits.fflags.bits.uop.is_sfb, bypasses[1].bits.fflags.bits.uop.is_sfb connect iregister_read.io.bypass[1].bits.fflags.bits.uop.is_jal, bypasses[1].bits.fflags.bits.uop.is_jal connect iregister_read.io.bypass[1].bits.fflags.bits.uop.is_jalr, bypasses[1].bits.fflags.bits.uop.is_jalr connect iregister_read.io.bypass[1].bits.fflags.bits.uop.is_br, bypasses[1].bits.fflags.bits.uop.is_br connect iregister_read.io.bypass[1].bits.fflags.bits.uop.iw_p2_poisoned, bypasses[1].bits.fflags.bits.uop.iw_p2_poisoned connect iregister_read.io.bypass[1].bits.fflags.bits.uop.iw_p1_poisoned, bypasses[1].bits.fflags.bits.uop.iw_p1_poisoned connect iregister_read.io.bypass[1].bits.fflags.bits.uop.iw_state, bypasses[1].bits.fflags.bits.uop.iw_state connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ctrl.is_std, bypasses[1].bits.fflags.bits.uop.ctrl.is_std connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ctrl.is_sta, bypasses[1].bits.fflags.bits.uop.ctrl.is_sta connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ctrl.is_load, bypasses[1].bits.fflags.bits.uop.ctrl.is_load connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ctrl.csr_cmd, bypasses[1].bits.fflags.bits.uop.ctrl.csr_cmd connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ctrl.fcn_dw, bypasses[1].bits.fflags.bits.uop.ctrl.fcn_dw connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ctrl.op_fcn, bypasses[1].bits.fflags.bits.uop.ctrl.op_fcn connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ctrl.imm_sel, bypasses[1].bits.fflags.bits.uop.ctrl.imm_sel connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ctrl.op2_sel, bypasses[1].bits.fflags.bits.uop.ctrl.op2_sel connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ctrl.op1_sel, bypasses[1].bits.fflags.bits.uop.ctrl.op1_sel connect iregister_read.io.bypass[1].bits.fflags.bits.uop.ctrl.br_type, bypasses[1].bits.fflags.bits.uop.ctrl.br_type connect iregister_read.io.bypass[1].bits.fflags.bits.uop.fu_code, bypasses[1].bits.fflags.bits.uop.fu_code connect iregister_read.io.bypass[1].bits.fflags.bits.uop.iq_type, bypasses[1].bits.fflags.bits.uop.iq_type connect iregister_read.io.bypass[1].bits.fflags.bits.uop.debug_pc, bypasses[1].bits.fflags.bits.uop.debug_pc connect iregister_read.io.bypass[1].bits.fflags.bits.uop.is_rvc, bypasses[1].bits.fflags.bits.uop.is_rvc connect iregister_read.io.bypass[1].bits.fflags.bits.uop.debug_inst, bypasses[1].bits.fflags.bits.uop.debug_inst connect iregister_read.io.bypass[1].bits.fflags.bits.uop.inst, bypasses[1].bits.fflags.bits.uop.inst connect iregister_read.io.bypass[1].bits.fflags.bits.uop.uopc, bypasses[1].bits.fflags.bits.uop.uopc connect iregister_read.io.bypass[1].bits.fflags.valid, bypasses[1].bits.fflags.valid connect iregister_read.io.bypass[1].bits.predicated, bypasses[1].bits.predicated connect iregister_read.io.bypass[1].bits.data, bypasses[1].bits.data connect iregister_read.io.bypass[1].bits.uop.debug_tsrc, bypasses[1].bits.uop.debug_tsrc connect iregister_read.io.bypass[1].bits.uop.debug_fsrc, bypasses[1].bits.uop.debug_fsrc connect iregister_read.io.bypass[1].bits.uop.bp_xcpt_if, bypasses[1].bits.uop.bp_xcpt_if connect iregister_read.io.bypass[1].bits.uop.bp_debug_if, bypasses[1].bits.uop.bp_debug_if connect iregister_read.io.bypass[1].bits.uop.xcpt_ma_if, bypasses[1].bits.uop.xcpt_ma_if connect iregister_read.io.bypass[1].bits.uop.xcpt_ae_if, bypasses[1].bits.uop.xcpt_ae_if connect iregister_read.io.bypass[1].bits.uop.xcpt_pf_if, bypasses[1].bits.uop.xcpt_pf_if connect iregister_read.io.bypass[1].bits.uop.fp_single, bypasses[1].bits.uop.fp_single connect iregister_read.io.bypass[1].bits.uop.fp_val, bypasses[1].bits.uop.fp_val connect iregister_read.io.bypass[1].bits.uop.frs3_en, bypasses[1].bits.uop.frs3_en connect iregister_read.io.bypass[1].bits.uop.lrs2_rtype, bypasses[1].bits.uop.lrs2_rtype connect iregister_read.io.bypass[1].bits.uop.lrs1_rtype, bypasses[1].bits.uop.lrs1_rtype connect iregister_read.io.bypass[1].bits.uop.dst_rtype, bypasses[1].bits.uop.dst_rtype connect iregister_read.io.bypass[1].bits.uop.ldst_val, bypasses[1].bits.uop.ldst_val connect iregister_read.io.bypass[1].bits.uop.lrs3, bypasses[1].bits.uop.lrs3 connect iregister_read.io.bypass[1].bits.uop.lrs2, bypasses[1].bits.uop.lrs2 connect iregister_read.io.bypass[1].bits.uop.lrs1, bypasses[1].bits.uop.lrs1 connect iregister_read.io.bypass[1].bits.uop.ldst, bypasses[1].bits.uop.ldst connect iregister_read.io.bypass[1].bits.uop.ldst_is_rs1, bypasses[1].bits.uop.ldst_is_rs1 connect iregister_read.io.bypass[1].bits.uop.flush_on_commit, bypasses[1].bits.uop.flush_on_commit connect iregister_read.io.bypass[1].bits.uop.is_unique, bypasses[1].bits.uop.is_unique connect iregister_read.io.bypass[1].bits.uop.is_sys_pc2epc, bypasses[1].bits.uop.is_sys_pc2epc connect iregister_read.io.bypass[1].bits.uop.uses_stq, bypasses[1].bits.uop.uses_stq connect iregister_read.io.bypass[1].bits.uop.uses_ldq, bypasses[1].bits.uop.uses_ldq connect iregister_read.io.bypass[1].bits.uop.is_amo, bypasses[1].bits.uop.is_amo connect iregister_read.io.bypass[1].bits.uop.is_fencei, bypasses[1].bits.uop.is_fencei connect iregister_read.io.bypass[1].bits.uop.is_fence, bypasses[1].bits.uop.is_fence connect iregister_read.io.bypass[1].bits.uop.mem_signed, bypasses[1].bits.uop.mem_signed connect iregister_read.io.bypass[1].bits.uop.mem_size, bypasses[1].bits.uop.mem_size connect iregister_read.io.bypass[1].bits.uop.mem_cmd, bypasses[1].bits.uop.mem_cmd connect iregister_read.io.bypass[1].bits.uop.bypassable, bypasses[1].bits.uop.bypassable connect iregister_read.io.bypass[1].bits.uop.exc_cause, bypasses[1].bits.uop.exc_cause connect iregister_read.io.bypass[1].bits.uop.exception, bypasses[1].bits.uop.exception connect iregister_read.io.bypass[1].bits.uop.stale_pdst, bypasses[1].bits.uop.stale_pdst connect iregister_read.io.bypass[1].bits.uop.ppred_busy, bypasses[1].bits.uop.ppred_busy connect iregister_read.io.bypass[1].bits.uop.prs3_busy, bypasses[1].bits.uop.prs3_busy connect iregister_read.io.bypass[1].bits.uop.prs2_busy, bypasses[1].bits.uop.prs2_busy connect iregister_read.io.bypass[1].bits.uop.prs1_busy, bypasses[1].bits.uop.prs1_busy connect iregister_read.io.bypass[1].bits.uop.ppred, bypasses[1].bits.uop.ppred connect iregister_read.io.bypass[1].bits.uop.prs3, bypasses[1].bits.uop.prs3 connect iregister_read.io.bypass[1].bits.uop.prs2, bypasses[1].bits.uop.prs2 connect iregister_read.io.bypass[1].bits.uop.prs1, bypasses[1].bits.uop.prs1 connect iregister_read.io.bypass[1].bits.uop.pdst, bypasses[1].bits.uop.pdst connect iregister_read.io.bypass[1].bits.uop.rxq_idx, bypasses[1].bits.uop.rxq_idx connect iregister_read.io.bypass[1].bits.uop.stq_idx, bypasses[1].bits.uop.stq_idx connect iregister_read.io.bypass[1].bits.uop.ldq_idx, bypasses[1].bits.uop.ldq_idx connect iregister_read.io.bypass[1].bits.uop.rob_idx, bypasses[1].bits.uop.rob_idx connect iregister_read.io.bypass[1].bits.uop.csr_addr, bypasses[1].bits.uop.csr_addr connect iregister_read.io.bypass[1].bits.uop.imm_packed, bypasses[1].bits.uop.imm_packed connect iregister_read.io.bypass[1].bits.uop.taken, bypasses[1].bits.uop.taken connect iregister_read.io.bypass[1].bits.uop.pc_lob, bypasses[1].bits.uop.pc_lob connect iregister_read.io.bypass[1].bits.uop.edge_inst, bypasses[1].bits.uop.edge_inst connect iregister_read.io.bypass[1].bits.uop.ftq_idx, bypasses[1].bits.uop.ftq_idx connect iregister_read.io.bypass[1].bits.uop.br_tag, bypasses[1].bits.uop.br_tag connect iregister_read.io.bypass[1].bits.uop.br_mask, bypasses[1].bits.uop.br_mask connect iregister_read.io.bypass[1].bits.uop.is_sfb, bypasses[1].bits.uop.is_sfb connect iregister_read.io.bypass[1].bits.uop.is_jal, bypasses[1].bits.uop.is_jal connect iregister_read.io.bypass[1].bits.uop.is_jalr, bypasses[1].bits.uop.is_jalr connect iregister_read.io.bypass[1].bits.uop.is_br, bypasses[1].bits.uop.is_br connect iregister_read.io.bypass[1].bits.uop.iw_p2_poisoned, bypasses[1].bits.uop.iw_p2_poisoned connect iregister_read.io.bypass[1].bits.uop.iw_p1_poisoned, bypasses[1].bits.uop.iw_p1_poisoned connect iregister_read.io.bypass[1].bits.uop.iw_state, bypasses[1].bits.uop.iw_state connect iregister_read.io.bypass[1].bits.uop.ctrl.is_std, bypasses[1].bits.uop.ctrl.is_std connect iregister_read.io.bypass[1].bits.uop.ctrl.is_sta, bypasses[1].bits.uop.ctrl.is_sta connect iregister_read.io.bypass[1].bits.uop.ctrl.is_load, bypasses[1].bits.uop.ctrl.is_load connect iregister_read.io.bypass[1].bits.uop.ctrl.csr_cmd, bypasses[1].bits.uop.ctrl.csr_cmd connect iregister_read.io.bypass[1].bits.uop.ctrl.fcn_dw, bypasses[1].bits.uop.ctrl.fcn_dw connect iregister_read.io.bypass[1].bits.uop.ctrl.op_fcn, bypasses[1].bits.uop.ctrl.op_fcn connect iregister_read.io.bypass[1].bits.uop.ctrl.imm_sel, bypasses[1].bits.uop.ctrl.imm_sel connect iregister_read.io.bypass[1].bits.uop.ctrl.op2_sel, bypasses[1].bits.uop.ctrl.op2_sel connect iregister_read.io.bypass[1].bits.uop.ctrl.op1_sel, bypasses[1].bits.uop.ctrl.op1_sel connect iregister_read.io.bypass[1].bits.uop.ctrl.br_type, bypasses[1].bits.uop.ctrl.br_type connect iregister_read.io.bypass[1].bits.uop.fu_code, bypasses[1].bits.uop.fu_code connect iregister_read.io.bypass[1].bits.uop.iq_type, bypasses[1].bits.uop.iq_type connect iregister_read.io.bypass[1].bits.uop.debug_pc, bypasses[1].bits.uop.debug_pc connect iregister_read.io.bypass[1].bits.uop.is_rvc, bypasses[1].bits.uop.is_rvc connect iregister_read.io.bypass[1].bits.uop.debug_inst, bypasses[1].bits.uop.debug_inst connect iregister_read.io.bypass[1].bits.uop.inst, bypasses[1].bits.uop.inst connect iregister_read.io.bypass[1].bits.uop.uopc, bypasses[1].bits.uop.uopc connect iregister_read.io.bypass[1].valid, bypasses[1].valid connect iregister_read.io.bypass[2].bits.fflags.bits.flags, bypasses[2].bits.fflags.bits.flags connect iregister_read.io.bypass[2].bits.fflags.bits.uop.debug_tsrc, bypasses[2].bits.fflags.bits.uop.debug_tsrc connect iregister_read.io.bypass[2].bits.fflags.bits.uop.debug_fsrc, bypasses[2].bits.fflags.bits.uop.debug_fsrc connect iregister_read.io.bypass[2].bits.fflags.bits.uop.bp_xcpt_if, bypasses[2].bits.fflags.bits.uop.bp_xcpt_if connect iregister_read.io.bypass[2].bits.fflags.bits.uop.bp_debug_if, bypasses[2].bits.fflags.bits.uop.bp_debug_if connect iregister_read.io.bypass[2].bits.fflags.bits.uop.xcpt_ma_if, bypasses[2].bits.fflags.bits.uop.xcpt_ma_if connect iregister_read.io.bypass[2].bits.fflags.bits.uop.xcpt_ae_if, bypasses[2].bits.fflags.bits.uop.xcpt_ae_if connect iregister_read.io.bypass[2].bits.fflags.bits.uop.xcpt_pf_if, bypasses[2].bits.fflags.bits.uop.xcpt_pf_if connect iregister_read.io.bypass[2].bits.fflags.bits.uop.fp_single, bypasses[2].bits.fflags.bits.uop.fp_single connect iregister_read.io.bypass[2].bits.fflags.bits.uop.fp_val, bypasses[2].bits.fflags.bits.uop.fp_val connect iregister_read.io.bypass[2].bits.fflags.bits.uop.frs3_en, bypasses[2].bits.fflags.bits.uop.frs3_en connect iregister_read.io.bypass[2].bits.fflags.bits.uop.lrs2_rtype, bypasses[2].bits.fflags.bits.uop.lrs2_rtype connect iregister_read.io.bypass[2].bits.fflags.bits.uop.lrs1_rtype, bypasses[2].bits.fflags.bits.uop.lrs1_rtype connect iregister_read.io.bypass[2].bits.fflags.bits.uop.dst_rtype, bypasses[2].bits.fflags.bits.uop.dst_rtype connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ldst_val, bypasses[2].bits.fflags.bits.uop.ldst_val connect iregister_read.io.bypass[2].bits.fflags.bits.uop.lrs3, bypasses[2].bits.fflags.bits.uop.lrs3 connect iregister_read.io.bypass[2].bits.fflags.bits.uop.lrs2, bypasses[2].bits.fflags.bits.uop.lrs2 connect iregister_read.io.bypass[2].bits.fflags.bits.uop.lrs1, bypasses[2].bits.fflags.bits.uop.lrs1 connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ldst, bypasses[2].bits.fflags.bits.uop.ldst connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ldst_is_rs1, bypasses[2].bits.fflags.bits.uop.ldst_is_rs1 connect iregister_read.io.bypass[2].bits.fflags.bits.uop.flush_on_commit, bypasses[2].bits.fflags.bits.uop.flush_on_commit connect iregister_read.io.bypass[2].bits.fflags.bits.uop.is_unique, bypasses[2].bits.fflags.bits.uop.is_unique connect iregister_read.io.bypass[2].bits.fflags.bits.uop.is_sys_pc2epc, bypasses[2].bits.fflags.bits.uop.is_sys_pc2epc connect iregister_read.io.bypass[2].bits.fflags.bits.uop.uses_stq, bypasses[2].bits.fflags.bits.uop.uses_stq connect iregister_read.io.bypass[2].bits.fflags.bits.uop.uses_ldq, bypasses[2].bits.fflags.bits.uop.uses_ldq connect iregister_read.io.bypass[2].bits.fflags.bits.uop.is_amo, bypasses[2].bits.fflags.bits.uop.is_amo connect iregister_read.io.bypass[2].bits.fflags.bits.uop.is_fencei, bypasses[2].bits.fflags.bits.uop.is_fencei connect iregister_read.io.bypass[2].bits.fflags.bits.uop.is_fence, bypasses[2].bits.fflags.bits.uop.is_fence connect iregister_read.io.bypass[2].bits.fflags.bits.uop.mem_signed, bypasses[2].bits.fflags.bits.uop.mem_signed connect iregister_read.io.bypass[2].bits.fflags.bits.uop.mem_size, bypasses[2].bits.fflags.bits.uop.mem_size connect iregister_read.io.bypass[2].bits.fflags.bits.uop.mem_cmd, bypasses[2].bits.fflags.bits.uop.mem_cmd connect iregister_read.io.bypass[2].bits.fflags.bits.uop.bypassable, bypasses[2].bits.fflags.bits.uop.bypassable connect iregister_read.io.bypass[2].bits.fflags.bits.uop.exc_cause, bypasses[2].bits.fflags.bits.uop.exc_cause connect iregister_read.io.bypass[2].bits.fflags.bits.uop.exception, bypasses[2].bits.fflags.bits.uop.exception connect iregister_read.io.bypass[2].bits.fflags.bits.uop.stale_pdst, bypasses[2].bits.fflags.bits.uop.stale_pdst connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ppred_busy, bypasses[2].bits.fflags.bits.uop.ppred_busy connect iregister_read.io.bypass[2].bits.fflags.bits.uop.prs3_busy, bypasses[2].bits.fflags.bits.uop.prs3_busy connect iregister_read.io.bypass[2].bits.fflags.bits.uop.prs2_busy, bypasses[2].bits.fflags.bits.uop.prs2_busy connect iregister_read.io.bypass[2].bits.fflags.bits.uop.prs1_busy, bypasses[2].bits.fflags.bits.uop.prs1_busy connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ppred, bypasses[2].bits.fflags.bits.uop.ppred connect iregister_read.io.bypass[2].bits.fflags.bits.uop.prs3, bypasses[2].bits.fflags.bits.uop.prs3 connect iregister_read.io.bypass[2].bits.fflags.bits.uop.prs2, bypasses[2].bits.fflags.bits.uop.prs2 connect iregister_read.io.bypass[2].bits.fflags.bits.uop.prs1, bypasses[2].bits.fflags.bits.uop.prs1 connect iregister_read.io.bypass[2].bits.fflags.bits.uop.pdst, bypasses[2].bits.fflags.bits.uop.pdst connect iregister_read.io.bypass[2].bits.fflags.bits.uop.rxq_idx, bypasses[2].bits.fflags.bits.uop.rxq_idx connect iregister_read.io.bypass[2].bits.fflags.bits.uop.stq_idx, bypasses[2].bits.fflags.bits.uop.stq_idx connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ldq_idx, bypasses[2].bits.fflags.bits.uop.ldq_idx connect iregister_read.io.bypass[2].bits.fflags.bits.uop.rob_idx, bypasses[2].bits.fflags.bits.uop.rob_idx connect iregister_read.io.bypass[2].bits.fflags.bits.uop.csr_addr, bypasses[2].bits.fflags.bits.uop.csr_addr connect iregister_read.io.bypass[2].bits.fflags.bits.uop.imm_packed, bypasses[2].bits.fflags.bits.uop.imm_packed connect iregister_read.io.bypass[2].bits.fflags.bits.uop.taken, bypasses[2].bits.fflags.bits.uop.taken connect iregister_read.io.bypass[2].bits.fflags.bits.uop.pc_lob, bypasses[2].bits.fflags.bits.uop.pc_lob connect iregister_read.io.bypass[2].bits.fflags.bits.uop.edge_inst, bypasses[2].bits.fflags.bits.uop.edge_inst connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ftq_idx, bypasses[2].bits.fflags.bits.uop.ftq_idx connect iregister_read.io.bypass[2].bits.fflags.bits.uop.br_tag, bypasses[2].bits.fflags.bits.uop.br_tag connect iregister_read.io.bypass[2].bits.fflags.bits.uop.br_mask, bypasses[2].bits.fflags.bits.uop.br_mask connect iregister_read.io.bypass[2].bits.fflags.bits.uop.is_sfb, bypasses[2].bits.fflags.bits.uop.is_sfb connect iregister_read.io.bypass[2].bits.fflags.bits.uop.is_jal, bypasses[2].bits.fflags.bits.uop.is_jal connect iregister_read.io.bypass[2].bits.fflags.bits.uop.is_jalr, bypasses[2].bits.fflags.bits.uop.is_jalr connect iregister_read.io.bypass[2].bits.fflags.bits.uop.is_br, bypasses[2].bits.fflags.bits.uop.is_br connect iregister_read.io.bypass[2].bits.fflags.bits.uop.iw_p2_poisoned, bypasses[2].bits.fflags.bits.uop.iw_p2_poisoned connect iregister_read.io.bypass[2].bits.fflags.bits.uop.iw_p1_poisoned, bypasses[2].bits.fflags.bits.uop.iw_p1_poisoned connect iregister_read.io.bypass[2].bits.fflags.bits.uop.iw_state, bypasses[2].bits.fflags.bits.uop.iw_state connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ctrl.is_std, bypasses[2].bits.fflags.bits.uop.ctrl.is_std connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ctrl.is_sta, bypasses[2].bits.fflags.bits.uop.ctrl.is_sta connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ctrl.is_load, bypasses[2].bits.fflags.bits.uop.ctrl.is_load connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ctrl.csr_cmd, bypasses[2].bits.fflags.bits.uop.ctrl.csr_cmd connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ctrl.fcn_dw, bypasses[2].bits.fflags.bits.uop.ctrl.fcn_dw connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ctrl.op_fcn, bypasses[2].bits.fflags.bits.uop.ctrl.op_fcn connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ctrl.imm_sel, bypasses[2].bits.fflags.bits.uop.ctrl.imm_sel connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ctrl.op2_sel, bypasses[2].bits.fflags.bits.uop.ctrl.op2_sel connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ctrl.op1_sel, bypasses[2].bits.fflags.bits.uop.ctrl.op1_sel connect iregister_read.io.bypass[2].bits.fflags.bits.uop.ctrl.br_type, bypasses[2].bits.fflags.bits.uop.ctrl.br_type connect iregister_read.io.bypass[2].bits.fflags.bits.uop.fu_code, bypasses[2].bits.fflags.bits.uop.fu_code connect iregister_read.io.bypass[2].bits.fflags.bits.uop.iq_type, bypasses[2].bits.fflags.bits.uop.iq_type connect iregister_read.io.bypass[2].bits.fflags.bits.uop.debug_pc, bypasses[2].bits.fflags.bits.uop.debug_pc connect iregister_read.io.bypass[2].bits.fflags.bits.uop.is_rvc, bypasses[2].bits.fflags.bits.uop.is_rvc connect iregister_read.io.bypass[2].bits.fflags.bits.uop.debug_inst, bypasses[2].bits.fflags.bits.uop.debug_inst connect iregister_read.io.bypass[2].bits.fflags.bits.uop.inst, bypasses[2].bits.fflags.bits.uop.inst connect iregister_read.io.bypass[2].bits.fflags.bits.uop.uopc, bypasses[2].bits.fflags.bits.uop.uopc connect iregister_read.io.bypass[2].bits.fflags.valid, bypasses[2].bits.fflags.valid connect iregister_read.io.bypass[2].bits.predicated, bypasses[2].bits.predicated connect iregister_read.io.bypass[2].bits.data, bypasses[2].bits.data connect iregister_read.io.bypass[2].bits.uop.debug_tsrc, bypasses[2].bits.uop.debug_tsrc connect iregister_read.io.bypass[2].bits.uop.debug_fsrc, bypasses[2].bits.uop.debug_fsrc connect iregister_read.io.bypass[2].bits.uop.bp_xcpt_if, bypasses[2].bits.uop.bp_xcpt_if connect iregister_read.io.bypass[2].bits.uop.bp_debug_if, bypasses[2].bits.uop.bp_debug_if connect iregister_read.io.bypass[2].bits.uop.xcpt_ma_if, bypasses[2].bits.uop.xcpt_ma_if connect iregister_read.io.bypass[2].bits.uop.xcpt_ae_if, bypasses[2].bits.uop.xcpt_ae_if connect iregister_read.io.bypass[2].bits.uop.xcpt_pf_if, bypasses[2].bits.uop.xcpt_pf_if connect iregister_read.io.bypass[2].bits.uop.fp_single, bypasses[2].bits.uop.fp_single connect iregister_read.io.bypass[2].bits.uop.fp_val, bypasses[2].bits.uop.fp_val connect iregister_read.io.bypass[2].bits.uop.frs3_en, bypasses[2].bits.uop.frs3_en connect iregister_read.io.bypass[2].bits.uop.lrs2_rtype, bypasses[2].bits.uop.lrs2_rtype connect iregister_read.io.bypass[2].bits.uop.lrs1_rtype, bypasses[2].bits.uop.lrs1_rtype connect iregister_read.io.bypass[2].bits.uop.dst_rtype, bypasses[2].bits.uop.dst_rtype connect iregister_read.io.bypass[2].bits.uop.ldst_val, bypasses[2].bits.uop.ldst_val connect iregister_read.io.bypass[2].bits.uop.lrs3, bypasses[2].bits.uop.lrs3 connect iregister_read.io.bypass[2].bits.uop.lrs2, bypasses[2].bits.uop.lrs2 connect iregister_read.io.bypass[2].bits.uop.lrs1, bypasses[2].bits.uop.lrs1 connect iregister_read.io.bypass[2].bits.uop.ldst, bypasses[2].bits.uop.ldst connect iregister_read.io.bypass[2].bits.uop.ldst_is_rs1, bypasses[2].bits.uop.ldst_is_rs1 connect iregister_read.io.bypass[2].bits.uop.flush_on_commit, bypasses[2].bits.uop.flush_on_commit connect iregister_read.io.bypass[2].bits.uop.is_unique, bypasses[2].bits.uop.is_unique connect iregister_read.io.bypass[2].bits.uop.is_sys_pc2epc, bypasses[2].bits.uop.is_sys_pc2epc connect iregister_read.io.bypass[2].bits.uop.uses_stq, bypasses[2].bits.uop.uses_stq connect iregister_read.io.bypass[2].bits.uop.uses_ldq, bypasses[2].bits.uop.uses_ldq connect iregister_read.io.bypass[2].bits.uop.is_amo, bypasses[2].bits.uop.is_amo connect iregister_read.io.bypass[2].bits.uop.is_fencei, bypasses[2].bits.uop.is_fencei connect iregister_read.io.bypass[2].bits.uop.is_fence, bypasses[2].bits.uop.is_fence connect iregister_read.io.bypass[2].bits.uop.mem_signed, bypasses[2].bits.uop.mem_signed connect iregister_read.io.bypass[2].bits.uop.mem_size, bypasses[2].bits.uop.mem_size connect iregister_read.io.bypass[2].bits.uop.mem_cmd, bypasses[2].bits.uop.mem_cmd connect iregister_read.io.bypass[2].bits.uop.bypassable, bypasses[2].bits.uop.bypassable connect iregister_read.io.bypass[2].bits.uop.exc_cause, bypasses[2].bits.uop.exc_cause connect iregister_read.io.bypass[2].bits.uop.exception, bypasses[2].bits.uop.exception connect iregister_read.io.bypass[2].bits.uop.stale_pdst, bypasses[2].bits.uop.stale_pdst connect iregister_read.io.bypass[2].bits.uop.ppred_busy, bypasses[2].bits.uop.ppred_busy connect iregister_read.io.bypass[2].bits.uop.prs3_busy, bypasses[2].bits.uop.prs3_busy connect iregister_read.io.bypass[2].bits.uop.prs2_busy, bypasses[2].bits.uop.prs2_busy connect iregister_read.io.bypass[2].bits.uop.prs1_busy, bypasses[2].bits.uop.prs1_busy connect iregister_read.io.bypass[2].bits.uop.ppred, bypasses[2].bits.uop.ppred connect iregister_read.io.bypass[2].bits.uop.prs3, bypasses[2].bits.uop.prs3 connect iregister_read.io.bypass[2].bits.uop.prs2, bypasses[2].bits.uop.prs2 connect iregister_read.io.bypass[2].bits.uop.prs1, bypasses[2].bits.uop.prs1 connect iregister_read.io.bypass[2].bits.uop.pdst, bypasses[2].bits.uop.pdst connect iregister_read.io.bypass[2].bits.uop.rxq_idx, bypasses[2].bits.uop.rxq_idx connect iregister_read.io.bypass[2].bits.uop.stq_idx, bypasses[2].bits.uop.stq_idx connect iregister_read.io.bypass[2].bits.uop.ldq_idx, bypasses[2].bits.uop.ldq_idx connect iregister_read.io.bypass[2].bits.uop.rob_idx, bypasses[2].bits.uop.rob_idx connect iregister_read.io.bypass[2].bits.uop.csr_addr, bypasses[2].bits.uop.csr_addr connect iregister_read.io.bypass[2].bits.uop.imm_packed, bypasses[2].bits.uop.imm_packed connect iregister_read.io.bypass[2].bits.uop.taken, bypasses[2].bits.uop.taken connect iregister_read.io.bypass[2].bits.uop.pc_lob, bypasses[2].bits.uop.pc_lob connect iregister_read.io.bypass[2].bits.uop.edge_inst, bypasses[2].bits.uop.edge_inst connect iregister_read.io.bypass[2].bits.uop.ftq_idx, bypasses[2].bits.uop.ftq_idx connect iregister_read.io.bypass[2].bits.uop.br_tag, bypasses[2].bits.uop.br_tag connect iregister_read.io.bypass[2].bits.uop.br_mask, bypasses[2].bits.uop.br_mask connect iregister_read.io.bypass[2].bits.uop.is_sfb, bypasses[2].bits.uop.is_sfb connect iregister_read.io.bypass[2].bits.uop.is_jal, bypasses[2].bits.uop.is_jal connect iregister_read.io.bypass[2].bits.uop.is_jalr, bypasses[2].bits.uop.is_jalr connect iregister_read.io.bypass[2].bits.uop.is_br, bypasses[2].bits.uop.is_br connect iregister_read.io.bypass[2].bits.uop.iw_p2_poisoned, bypasses[2].bits.uop.iw_p2_poisoned connect iregister_read.io.bypass[2].bits.uop.iw_p1_poisoned, bypasses[2].bits.uop.iw_p1_poisoned connect iregister_read.io.bypass[2].bits.uop.iw_state, bypasses[2].bits.uop.iw_state connect iregister_read.io.bypass[2].bits.uop.ctrl.is_std, bypasses[2].bits.uop.ctrl.is_std connect iregister_read.io.bypass[2].bits.uop.ctrl.is_sta, bypasses[2].bits.uop.ctrl.is_sta connect iregister_read.io.bypass[2].bits.uop.ctrl.is_load, bypasses[2].bits.uop.ctrl.is_load connect iregister_read.io.bypass[2].bits.uop.ctrl.csr_cmd, bypasses[2].bits.uop.ctrl.csr_cmd connect iregister_read.io.bypass[2].bits.uop.ctrl.fcn_dw, bypasses[2].bits.uop.ctrl.fcn_dw connect iregister_read.io.bypass[2].bits.uop.ctrl.op_fcn, bypasses[2].bits.uop.ctrl.op_fcn connect iregister_read.io.bypass[2].bits.uop.ctrl.imm_sel, bypasses[2].bits.uop.ctrl.imm_sel connect iregister_read.io.bypass[2].bits.uop.ctrl.op2_sel, bypasses[2].bits.uop.ctrl.op2_sel connect iregister_read.io.bypass[2].bits.uop.ctrl.op1_sel, bypasses[2].bits.uop.ctrl.op1_sel connect iregister_read.io.bypass[2].bits.uop.ctrl.br_type, bypasses[2].bits.uop.ctrl.br_type connect iregister_read.io.bypass[2].bits.uop.fu_code, bypasses[2].bits.uop.fu_code connect iregister_read.io.bypass[2].bits.uop.iq_type, bypasses[2].bits.uop.iq_type connect iregister_read.io.bypass[2].bits.uop.debug_pc, bypasses[2].bits.uop.debug_pc connect iregister_read.io.bypass[2].bits.uop.is_rvc, bypasses[2].bits.uop.is_rvc connect iregister_read.io.bypass[2].bits.uop.debug_inst, bypasses[2].bits.uop.debug_inst connect iregister_read.io.bypass[2].bits.uop.inst, bypasses[2].bits.uop.inst connect iregister_read.io.bypass[2].bits.uop.uopc, bypasses[2].bits.uop.uopc connect iregister_read.io.bypass[2].valid, bypasses[2].valid connect iregister_read.io.bypass[3].bits.fflags.bits.flags, bypasses[3].bits.fflags.bits.flags connect iregister_read.io.bypass[3].bits.fflags.bits.uop.debug_tsrc, bypasses[3].bits.fflags.bits.uop.debug_tsrc connect iregister_read.io.bypass[3].bits.fflags.bits.uop.debug_fsrc, bypasses[3].bits.fflags.bits.uop.debug_fsrc connect iregister_read.io.bypass[3].bits.fflags.bits.uop.bp_xcpt_if, bypasses[3].bits.fflags.bits.uop.bp_xcpt_if connect iregister_read.io.bypass[3].bits.fflags.bits.uop.bp_debug_if, bypasses[3].bits.fflags.bits.uop.bp_debug_if connect iregister_read.io.bypass[3].bits.fflags.bits.uop.xcpt_ma_if, bypasses[3].bits.fflags.bits.uop.xcpt_ma_if connect iregister_read.io.bypass[3].bits.fflags.bits.uop.xcpt_ae_if, bypasses[3].bits.fflags.bits.uop.xcpt_ae_if connect iregister_read.io.bypass[3].bits.fflags.bits.uop.xcpt_pf_if, bypasses[3].bits.fflags.bits.uop.xcpt_pf_if connect iregister_read.io.bypass[3].bits.fflags.bits.uop.fp_single, bypasses[3].bits.fflags.bits.uop.fp_single connect iregister_read.io.bypass[3].bits.fflags.bits.uop.fp_val, bypasses[3].bits.fflags.bits.uop.fp_val connect iregister_read.io.bypass[3].bits.fflags.bits.uop.frs3_en, bypasses[3].bits.fflags.bits.uop.frs3_en connect iregister_read.io.bypass[3].bits.fflags.bits.uop.lrs2_rtype, bypasses[3].bits.fflags.bits.uop.lrs2_rtype connect iregister_read.io.bypass[3].bits.fflags.bits.uop.lrs1_rtype, bypasses[3].bits.fflags.bits.uop.lrs1_rtype connect iregister_read.io.bypass[3].bits.fflags.bits.uop.dst_rtype, bypasses[3].bits.fflags.bits.uop.dst_rtype connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ldst_val, bypasses[3].bits.fflags.bits.uop.ldst_val connect iregister_read.io.bypass[3].bits.fflags.bits.uop.lrs3, bypasses[3].bits.fflags.bits.uop.lrs3 connect iregister_read.io.bypass[3].bits.fflags.bits.uop.lrs2, bypasses[3].bits.fflags.bits.uop.lrs2 connect iregister_read.io.bypass[3].bits.fflags.bits.uop.lrs1, bypasses[3].bits.fflags.bits.uop.lrs1 connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ldst, bypasses[3].bits.fflags.bits.uop.ldst connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ldst_is_rs1, bypasses[3].bits.fflags.bits.uop.ldst_is_rs1 connect iregister_read.io.bypass[3].bits.fflags.bits.uop.flush_on_commit, bypasses[3].bits.fflags.bits.uop.flush_on_commit connect iregister_read.io.bypass[3].bits.fflags.bits.uop.is_unique, bypasses[3].bits.fflags.bits.uop.is_unique connect iregister_read.io.bypass[3].bits.fflags.bits.uop.is_sys_pc2epc, bypasses[3].bits.fflags.bits.uop.is_sys_pc2epc connect iregister_read.io.bypass[3].bits.fflags.bits.uop.uses_stq, bypasses[3].bits.fflags.bits.uop.uses_stq connect iregister_read.io.bypass[3].bits.fflags.bits.uop.uses_ldq, bypasses[3].bits.fflags.bits.uop.uses_ldq connect iregister_read.io.bypass[3].bits.fflags.bits.uop.is_amo, bypasses[3].bits.fflags.bits.uop.is_amo connect iregister_read.io.bypass[3].bits.fflags.bits.uop.is_fencei, bypasses[3].bits.fflags.bits.uop.is_fencei connect iregister_read.io.bypass[3].bits.fflags.bits.uop.is_fence, bypasses[3].bits.fflags.bits.uop.is_fence connect iregister_read.io.bypass[3].bits.fflags.bits.uop.mem_signed, bypasses[3].bits.fflags.bits.uop.mem_signed connect iregister_read.io.bypass[3].bits.fflags.bits.uop.mem_size, bypasses[3].bits.fflags.bits.uop.mem_size connect iregister_read.io.bypass[3].bits.fflags.bits.uop.mem_cmd, bypasses[3].bits.fflags.bits.uop.mem_cmd connect iregister_read.io.bypass[3].bits.fflags.bits.uop.bypassable, bypasses[3].bits.fflags.bits.uop.bypassable connect iregister_read.io.bypass[3].bits.fflags.bits.uop.exc_cause, bypasses[3].bits.fflags.bits.uop.exc_cause connect iregister_read.io.bypass[3].bits.fflags.bits.uop.exception, bypasses[3].bits.fflags.bits.uop.exception connect iregister_read.io.bypass[3].bits.fflags.bits.uop.stale_pdst, bypasses[3].bits.fflags.bits.uop.stale_pdst connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ppred_busy, bypasses[3].bits.fflags.bits.uop.ppred_busy connect iregister_read.io.bypass[3].bits.fflags.bits.uop.prs3_busy, bypasses[3].bits.fflags.bits.uop.prs3_busy connect iregister_read.io.bypass[3].bits.fflags.bits.uop.prs2_busy, bypasses[3].bits.fflags.bits.uop.prs2_busy connect iregister_read.io.bypass[3].bits.fflags.bits.uop.prs1_busy, bypasses[3].bits.fflags.bits.uop.prs1_busy connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ppred, bypasses[3].bits.fflags.bits.uop.ppred connect iregister_read.io.bypass[3].bits.fflags.bits.uop.prs3, bypasses[3].bits.fflags.bits.uop.prs3 connect iregister_read.io.bypass[3].bits.fflags.bits.uop.prs2, bypasses[3].bits.fflags.bits.uop.prs2 connect iregister_read.io.bypass[3].bits.fflags.bits.uop.prs1, bypasses[3].bits.fflags.bits.uop.prs1 connect iregister_read.io.bypass[3].bits.fflags.bits.uop.pdst, bypasses[3].bits.fflags.bits.uop.pdst connect iregister_read.io.bypass[3].bits.fflags.bits.uop.rxq_idx, bypasses[3].bits.fflags.bits.uop.rxq_idx connect iregister_read.io.bypass[3].bits.fflags.bits.uop.stq_idx, bypasses[3].bits.fflags.bits.uop.stq_idx connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ldq_idx, bypasses[3].bits.fflags.bits.uop.ldq_idx connect iregister_read.io.bypass[3].bits.fflags.bits.uop.rob_idx, bypasses[3].bits.fflags.bits.uop.rob_idx connect iregister_read.io.bypass[3].bits.fflags.bits.uop.csr_addr, bypasses[3].bits.fflags.bits.uop.csr_addr connect iregister_read.io.bypass[3].bits.fflags.bits.uop.imm_packed, bypasses[3].bits.fflags.bits.uop.imm_packed connect iregister_read.io.bypass[3].bits.fflags.bits.uop.taken, bypasses[3].bits.fflags.bits.uop.taken connect iregister_read.io.bypass[3].bits.fflags.bits.uop.pc_lob, bypasses[3].bits.fflags.bits.uop.pc_lob connect iregister_read.io.bypass[3].bits.fflags.bits.uop.edge_inst, bypasses[3].bits.fflags.bits.uop.edge_inst connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ftq_idx, bypasses[3].bits.fflags.bits.uop.ftq_idx connect iregister_read.io.bypass[3].bits.fflags.bits.uop.br_tag, bypasses[3].bits.fflags.bits.uop.br_tag connect iregister_read.io.bypass[3].bits.fflags.bits.uop.br_mask, bypasses[3].bits.fflags.bits.uop.br_mask connect iregister_read.io.bypass[3].bits.fflags.bits.uop.is_sfb, bypasses[3].bits.fflags.bits.uop.is_sfb connect iregister_read.io.bypass[3].bits.fflags.bits.uop.is_jal, bypasses[3].bits.fflags.bits.uop.is_jal connect iregister_read.io.bypass[3].bits.fflags.bits.uop.is_jalr, bypasses[3].bits.fflags.bits.uop.is_jalr connect iregister_read.io.bypass[3].bits.fflags.bits.uop.is_br, bypasses[3].bits.fflags.bits.uop.is_br connect iregister_read.io.bypass[3].bits.fflags.bits.uop.iw_p2_poisoned, bypasses[3].bits.fflags.bits.uop.iw_p2_poisoned connect iregister_read.io.bypass[3].bits.fflags.bits.uop.iw_p1_poisoned, bypasses[3].bits.fflags.bits.uop.iw_p1_poisoned connect iregister_read.io.bypass[3].bits.fflags.bits.uop.iw_state, bypasses[3].bits.fflags.bits.uop.iw_state connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ctrl.is_std, bypasses[3].bits.fflags.bits.uop.ctrl.is_std connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ctrl.is_sta, bypasses[3].bits.fflags.bits.uop.ctrl.is_sta connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ctrl.is_load, bypasses[3].bits.fflags.bits.uop.ctrl.is_load connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ctrl.csr_cmd, bypasses[3].bits.fflags.bits.uop.ctrl.csr_cmd connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ctrl.fcn_dw, bypasses[3].bits.fflags.bits.uop.ctrl.fcn_dw connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ctrl.op_fcn, bypasses[3].bits.fflags.bits.uop.ctrl.op_fcn connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ctrl.imm_sel, bypasses[3].bits.fflags.bits.uop.ctrl.imm_sel connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ctrl.op2_sel, bypasses[3].bits.fflags.bits.uop.ctrl.op2_sel connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ctrl.op1_sel, bypasses[3].bits.fflags.bits.uop.ctrl.op1_sel connect iregister_read.io.bypass[3].bits.fflags.bits.uop.ctrl.br_type, bypasses[3].bits.fflags.bits.uop.ctrl.br_type connect iregister_read.io.bypass[3].bits.fflags.bits.uop.fu_code, bypasses[3].bits.fflags.bits.uop.fu_code connect iregister_read.io.bypass[3].bits.fflags.bits.uop.iq_type, bypasses[3].bits.fflags.bits.uop.iq_type connect iregister_read.io.bypass[3].bits.fflags.bits.uop.debug_pc, bypasses[3].bits.fflags.bits.uop.debug_pc connect iregister_read.io.bypass[3].bits.fflags.bits.uop.is_rvc, bypasses[3].bits.fflags.bits.uop.is_rvc connect iregister_read.io.bypass[3].bits.fflags.bits.uop.debug_inst, bypasses[3].bits.fflags.bits.uop.debug_inst connect iregister_read.io.bypass[3].bits.fflags.bits.uop.inst, bypasses[3].bits.fflags.bits.uop.inst connect iregister_read.io.bypass[3].bits.fflags.bits.uop.uopc, bypasses[3].bits.fflags.bits.uop.uopc connect iregister_read.io.bypass[3].bits.fflags.valid, bypasses[3].bits.fflags.valid connect iregister_read.io.bypass[3].bits.predicated, bypasses[3].bits.predicated connect iregister_read.io.bypass[3].bits.data, bypasses[3].bits.data connect iregister_read.io.bypass[3].bits.uop.debug_tsrc, bypasses[3].bits.uop.debug_tsrc connect iregister_read.io.bypass[3].bits.uop.debug_fsrc, bypasses[3].bits.uop.debug_fsrc connect iregister_read.io.bypass[3].bits.uop.bp_xcpt_if, bypasses[3].bits.uop.bp_xcpt_if connect iregister_read.io.bypass[3].bits.uop.bp_debug_if, bypasses[3].bits.uop.bp_debug_if connect iregister_read.io.bypass[3].bits.uop.xcpt_ma_if, bypasses[3].bits.uop.xcpt_ma_if connect iregister_read.io.bypass[3].bits.uop.xcpt_ae_if, bypasses[3].bits.uop.xcpt_ae_if connect iregister_read.io.bypass[3].bits.uop.xcpt_pf_if, bypasses[3].bits.uop.xcpt_pf_if connect iregister_read.io.bypass[3].bits.uop.fp_single, bypasses[3].bits.uop.fp_single connect iregister_read.io.bypass[3].bits.uop.fp_val, bypasses[3].bits.uop.fp_val connect iregister_read.io.bypass[3].bits.uop.frs3_en, bypasses[3].bits.uop.frs3_en connect iregister_read.io.bypass[3].bits.uop.lrs2_rtype, bypasses[3].bits.uop.lrs2_rtype connect iregister_read.io.bypass[3].bits.uop.lrs1_rtype, bypasses[3].bits.uop.lrs1_rtype connect iregister_read.io.bypass[3].bits.uop.dst_rtype, bypasses[3].bits.uop.dst_rtype connect iregister_read.io.bypass[3].bits.uop.ldst_val, bypasses[3].bits.uop.ldst_val connect iregister_read.io.bypass[3].bits.uop.lrs3, bypasses[3].bits.uop.lrs3 connect iregister_read.io.bypass[3].bits.uop.lrs2, bypasses[3].bits.uop.lrs2 connect iregister_read.io.bypass[3].bits.uop.lrs1, bypasses[3].bits.uop.lrs1 connect iregister_read.io.bypass[3].bits.uop.ldst, bypasses[3].bits.uop.ldst connect iregister_read.io.bypass[3].bits.uop.ldst_is_rs1, bypasses[3].bits.uop.ldst_is_rs1 connect iregister_read.io.bypass[3].bits.uop.flush_on_commit, bypasses[3].bits.uop.flush_on_commit connect iregister_read.io.bypass[3].bits.uop.is_unique, bypasses[3].bits.uop.is_unique connect iregister_read.io.bypass[3].bits.uop.is_sys_pc2epc, bypasses[3].bits.uop.is_sys_pc2epc connect iregister_read.io.bypass[3].bits.uop.uses_stq, bypasses[3].bits.uop.uses_stq connect iregister_read.io.bypass[3].bits.uop.uses_ldq, bypasses[3].bits.uop.uses_ldq connect iregister_read.io.bypass[3].bits.uop.is_amo, bypasses[3].bits.uop.is_amo connect iregister_read.io.bypass[3].bits.uop.is_fencei, bypasses[3].bits.uop.is_fencei connect iregister_read.io.bypass[3].bits.uop.is_fence, bypasses[3].bits.uop.is_fence connect iregister_read.io.bypass[3].bits.uop.mem_signed, bypasses[3].bits.uop.mem_signed connect iregister_read.io.bypass[3].bits.uop.mem_size, bypasses[3].bits.uop.mem_size connect iregister_read.io.bypass[3].bits.uop.mem_cmd, bypasses[3].bits.uop.mem_cmd connect iregister_read.io.bypass[3].bits.uop.bypassable, bypasses[3].bits.uop.bypassable connect iregister_read.io.bypass[3].bits.uop.exc_cause, bypasses[3].bits.uop.exc_cause connect iregister_read.io.bypass[3].bits.uop.exception, bypasses[3].bits.uop.exception connect iregister_read.io.bypass[3].bits.uop.stale_pdst, bypasses[3].bits.uop.stale_pdst connect iregister_read.io.bypass[3].bits.uop.ppred_busy, bypasses[3].bits.uop.ppred_busy connect iregister_read.io.bypass[3].bits.uop.prs3_busy, bypasses[3].bits.uop.prs3_busy connect iregister_read.io.bypass[3].bits.uop.prs2_busy, bypasses[3].bits.uop.prs2_busy connect iregister_read.io.bypass[3].bits.uop.prs1_busy, bypasses[3].bits.uop.prs1_busy connect iregister_read.io.bypass[3].bits.uop.ppred, bypasses[3].bits.uop.ppred connect iregister_read.io.bypass[3].bits.uop.prs3, bypasses[3].bits.uop.prs3 connect iregister_read.io.bypass[3].bits.uop.prs2, bypasses[3].bits.uop.prs2 connect iregister_read.io.bypass[3].bits.uop.prs1, bypasses[3].bits.uop.prs1 connect iregister_read.io.bypass[3].bits.uop.pdst, bypasses[3].bits.uop.pdst connect iregister_read.io.bypass[3].bits.uop.rxq_idx, bypasses[3].bits.uop.rxq_idx connect iregister_read.io.bypass[3].bits.uop.stq_idx, bypasses[3].bits.uop.stq_idx connect iregister_read.io.bypass[3].bits.uop.ldq_idx, bypasses[3].bits.uop.ldq_idx connect iregister_read.io.bypass[3].bits.uop.rob_idx, bypasses[3].bits.uop.rob_idx connect iregister_read.io.bypass[3].bits.uop.csr_addr, bypasses[3].bits.uop.csr_addr connect iregister_read.io.bypass[3].bits.uop.imm_packed, bypasses[3].bits.uop.imm_packed connect iregister_read.io.bypass[3].bits.uop.taken, bypasses[3].bits.uop.taken connect iregister_read.io.bypass[3].bits.uop.pc_lob, bypasses[3].bits.uop.pc_lob connect iregister_read.io.bypass[3].bits.uop.edge_inst, bypasses[3].bits.uop.edge_inst connect iregister_read.io.bypass[3].bits.uop.ftq_idx, bypasses[3].bits.uop.ftq_idx connect iregister_read.io.bypass[3].bits.uop.br_tag, bypasses[3].bits.uop.br_tag connect iregister_read.io.bypass[3].bits.uop.br_mask, bypasses[3].bits.uop.br_mask connect iregister_read.io.bypass[3].bits.uop.is_sfb, bypasses[3].bits.uop.is_sfb connect iregister_read.io.bypass[3].bits.uop.is_jal, bypasses[3].bits.uop.is_jal connect iregister_read.io.bypass[3].bits.uop.is_jalr, bypasses[3].bits.uop.is_jalr connect iregister_read.io.bypass[3].bits.uop.is_br, bypasses[3].bits.uop.is_br connect iregister_read.io.bypass[3].bits.uop.iw_p2_poisoned, bypasses[3].bits.uop.iw_p2_poisoned connect iregister_read.io.bypass[3].bits.uop.iw_p1_poisoned, bypasses[3].bits.uop.iw_p1_poisoned connect iregister_read.io.bypass[3].bits.uop.iw_state, bypasses[3].bits.uop.iw_state connect iregister_read.io.bypass[3].bits.uop.ctrl.is_std, bypasses[3].bits.uop.ctrl.is_std connect iregister_read.io.bypass[3].bits.uop.ctrl.is_sta, bypasses[3].bits.uop.ctrl.is_sta connect iregister_read.io.bypass[3].bits.uop.ctrl.is_load, bypasses[3].bits.uop.ctrl.is_load connect iregister_read.io.bypass[3].bits.uop.ctrl.csr_cmd, bypasses[3].bits.uop.ctrl.csr_cmd connect iregister_read.io.bypass[3].bits.uop.ctrl.fcn_dw, bypasses[3].bits.uop.ctrl.fcn_dw connect iregister_read.io.bypass[3].bits.uop.ctrl.op_fcn, bypasses[3].bits.uop.ctrl.op_fcn connect iregister_read.io.bypass[3].bits.uop.ctrl.imm_sel, bypasses[3].bits.uop.ctrl.imm_sel connect iregister_read.io.bypass[3].bits.uop.ctrl.op2_sel, bypasses[3].bits.uop.ctrl.op2_sel connect iregister_read.io.bypass[3].bits.uop.ctrl.op1_sel, bypasses[3].bits.uop.ctrl.op1_sel connect iregister_read.io.bypass[3].bits.uop.ctrl.br_type, bypasses[3].bits.uop.ctrl.br_type connect iregister_read.io.bypass[3].bits.uop.fu_code, bypasses[3].bits.uop.fu_code connect iregister_read.io.bypass[3].bits.uop.iq_type, bypasses[3].bits.uop.iq_type connect iregister_read.io.bypass[3].bits.uop.debug_pc, bypasses[3].bits.uop.debug_pc connect iregister_read.io.bypass[3].bits.uop.is_rvc, bypasses[3].bits.uop.is_rvc connect iregister_read.io.bypass[3].bits.uop.debug_inst, bypasses[3].bits.uop.debug_inst connect iregister_read.io.bypass[3].bits.uop.inst, bypasses[3].bits.uop.inst connect iregister_read.io.bypass[3].bits.uop.uopc, bypasses[3].bits.uop.uopc connect iregister_read.io.bypass[3].valid, bypasses[3].valid connect iregister_read.io.bypass[4].bits.fflags.bits.flags, bypasses[4].bits.fflags.bits.flags connect iregister_read.io.bypass[4].bits.fflags.bits.uop.debug_tsrc, bypasses[4].bits.fflags.bits.uop.debug_tsrc connect iregister_read.io.bypass[4].bits.fflags.bits.uop.debug_fsrc, bypasses[4].bits.fflags.bits.uop.debug_fsrc connect iregister_read.io.bypass[4].bits.fflags.bits.uop.bp_xcpt_if, bypasses[4].bits.fflags.bits.uop.bp_xcpt_if connect iregister_read.io.bypass[4].bits.fflags.bits.uop.bp_debug_if, bypasses[4].bits.fflags.bits.uop.bp_debug_if connect iregister_read.io.bypass[4].bits.fflags.bits.uop.xcpt_ma_if, bypasses[4].bits.fflags.bits.uop.xcpt_ma_if connect iregister_read.io.bypass[4].bits.fflags.bits.uop.xcpt_ae_if, bypasses[4].bits.fflags.bits.uop.xcpt_ae_if connect iregister_read.io.bypass[4].bits.fflags.bits.uop.xcpt_pf_if, bypasses[4].bits.fflags.bits.uop.xcpt_pf_if connect iregister_read.io.bypass[4].bits.fflags.bits.uop.fp_single, bypasses[4].bits.fflags.bits.uop.fp_single connect iregister_read.io.bypass[4].bits.fflags.bits.uop.fp_val, bypasses[4].bits.fflags.bits.uop.fp_val connect iregister_read.io.bypass[4].bits.fflags.bits.uop.frs3_en, bypasses[4].bits.fflags.bits.uop.frs3_en connect iregister_read.io.bypass[4].bits.fflags.bits.uop.lrs2_rtype, bypasses[4].bits.fflags.bits.uop.lrs2_rtype connect iregister_read.io.bypass[4].bits.fflags.bits.uop.lrs1_rtype, bypasses[4].bits.fflags.bits.uop.lrs1_rtype connect iregister_read.io.bypass[4].bits.fflags.bits.uop.dst_rtype, bypasses[4].bits.fflags.bits.uop.dst_rtype connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ldst_val, bypasses[4].bits.fflags.bits.uop.ldst_val connect iregister_read.io.bypass[4].bits.fflags.bits.uop.lrs3, bypasses[4].bits.fflags.bits.uop.lrs3 connect iregister_read.io.bypass[4].bits.fflags.bits.uop.lrs2, bypasses[4].bits.fflags.bits.uop.lrs2 connect iregister_read.io.bypass[4].bits.fflags.bits.uop.lrs1, bypasses[4].bits.fflags.bits.uop.lrs1 connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ldst, bypasses[4].bits.fflags.bits.uop.ldst connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ldst_is_rs1, bypasses[4].bits.fflags.bits.uop.ldst_is_rs1 connect iregister_read.io.bypass[4].bits.fflags.bits.uop.flush_on_commit, bypasses[4].bits.fflags.bits.uop.flush_on_commit connect iregister_read.io.bypass[4].bits.fflags.bits.uop.is_unique, bypasses[4].bits.fflags.bits.uop.is_unique connect iregister_read.io.bypass[4].bits.fflags.bits.uop.is_sys_pc2epc, bypasses[4].bits.fflags.bits.uop.is_sys_pc2epc connect iregister_read.io.bypass[4].bits.fflags.bits.uop.uses_stq, bypasses[4].bits.fflags.bits.uop.uses_stq connect iregister_read.io.bypass[4].bits.fflags.bits.uop.uses_ldq, bypasses[4].bits.fflags.bits.uop.uses_ldq connect iregister_read.io.bypass[4].bits.fflags.bits.uop.is_amo, bypasses[4].bits.fflags.bits.uop.is_amo connect iregister_read.io.bypass[4].bits.fflags.bits.uop.is_fencei, bypasses[4].bits.fflags.bits.uop.is_fencei connect iregister_read.io.bypass[4].bits.fflags.bits.uop.is_fence, bypasses[4].bits.fflags.bits.uop.is_fence connect iregister_read.io.bypass[4].bits.fflags.bits.uop.mem_signed, bypasses[4].bits.fflags.bits.uop.mem_signed connect iregister_read.io.bypass[4].bits.fflags.bits.uop.mem_size, bypasses[4].bits.fflags.bits.uop.mem_size connect iregister_read.io.bypass[4].bits.fflags.bits.uop.mem_cmd, bypasses[4].bits.fflags.bits.uop.mem_cmd connect iregister_read.io.bypass[4].bits.fflags.bits.uop.bypassable, bypasses[4].bits.fflags.bits.uop.bypassable connect iregister_read.io.bypass[4].bits.fflags.bits.uop.exc_cause, bypasses[4].bits.fflags.bits.uop.exc_cause connect iregister_read.io.bypass[4].bits.fflags.bits.uop.exception, bypasses[4].bits.fflags.bits.uop.exception connect iregister_read.io.bypass[4].bits.fflags.bits.uop.stale_pdst, bypasses[4].bits.fflags.bits.uop.stale_pdst connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ppred_busy, bypasses[4].bits.fflags.bits.uop.ppred_busy connect iregister_read.io.bypass[4].bits.fflags.bits.uop.prs3_busy, bypasses[4].bits.fflags.bits.uop.prs3_busy connect iregister_read.io.bypass[4].bits.fflags.bits.uop.prs2_busy, bypasses[4].bits.fflags.bits.uop.prs2_busy connect iregister_read.io.bypass[4].bits.fflags.bits.uop.prs1_busy, bypasses[4].bits.fflags.bits.uop.prs1_busy connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ppred, bypasses[4].bits.fflags.bits.uop.ppred connect iregister_read.io.bypass[4].bits.fflags.bits.uop.prs3, bypasses[4].bits.fflags.bits.uop.prs3 connect iregister_read.io.bypass[4].bits.fflags.bits.uop.prs2, bypasses[4].bits.fflags.bits.uop.prs2 connect iregister_read.io.bypass[4].bits.fflags.bits.uop.prs1, bypasses[4].bits.fflags.bits.uop.prs1 connect iregister_read.io.bypass[4].bits.fflags.bits.uop.pdst, bypasses[4].bits.fflags.bits.uop.pdst connect iregister_read.io.bypass[4].bits.fflags.bits.uop.rxq_idx, bypasses[4].bits.fflags.bits.uop.rxq_idx connect iregister_read.io.bypass[4].bits.fflags.bits.uop.stq_idx, bypasses[4].bits.fflags.bits.uop.stq_idx connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ldq_idx, bypasses[4].bits.fflags.bits.uop.ldq_idx connect iregister_read.io.bypass[4].bits.fflags.bits.uop.rob_idx, bypasses[4].bits.fflags.bits.uop.rob_idx connect iregister_read.io.bypass[4].bits.fflags.bits.uop.csr_addr, bypasses[4].bits.fflags.bits.uop.csr_addr connect iregister_read.io.bypass[4].bits.fflags.bits.uop.imm_packed, bypasses[4].bits.fflags.bits.uop.imm_packed connect iregister_read.io.bypass[4].bits.fflags.bits.uop.taken, bypasses[4].bits.fflags.bits.uop.taken connect iregister_read.io.bypass[4].bits.fflags.bits.uop.pc_lob, bypasses[4].bits.fflags.bits.uop.pc_lob connect iregister_read.io.bypass[4].bits.fflags.bits.uop.edge_inst, bypasses[4].bits.fflags.bits.uop.edge_inst connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ftq_idx, bypasses[4].bits.fflags.bits.uop.ftq_idx connect iregister_read.io.bypass[4].bits.fflags.bits.uop.br_tag, bypasses[4].bits.fflags.bits.uop.br_tag connect iregister_read.io.bypass[4].bits.fflags.bits.uop.br_mask, bypasses[4].bits.fflags.bits.uop.br_mask connect iregister_read.io.bypass[4].bits.fflags.bits.uop.is_sfb, bypasses[4].bits.fflags.bits.uop.is_sfb connect iregister_read.io.bypass[4].bits.fflags.bits.uop.is_jal, bypasses[4].bits.fflags.bits.uop.is_jal connect iregister_read.io.bypass[4].bits.fflags.bits.uop.is_jalr, bypasses[4].bits.fflags.bits.uop.is_jalr connect iregister_read.io.bypass[4].bits.fflags.bits.uop.is_br, bypasses[4].bits.fflags.bits.uop.is_br connect iregister_read.io.bypass[4].bits.fflags.bits.uop.iw_p2_poisoned, bypasses[4].bits.fflags.bits.uop.iw_p2_poisoned connect iregister_read.io.bypass[4].bits.fflags.bits.uop.iw_p1_poisoned, bypasses[4].bits.fflags.bits.uop.iw_p1_poisoned connect iregister_read.io.bypass[4].bits.fflags.bits.uop.iw_state, bypasses[4].bits.fflags.bits.uop.iw_state connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ctrl.is_std, bypasses[4].bits.fflags.bits.uop.ctrl.is_std connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ctrl.is_sta, bypasses[4].bits.fflags.bits.uop.ctrl.is_sta connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ctrl.is_load, bypasses[4].bits.fflags.bits.uop.ctrl.is_load connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ctrl.csr_cmd, bypasses[4].bits.fflags.bits.uop.ctrl.csr_cmd connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ctrl.fcn_dw, bypasses[4].bits.fflags.bits.uop.ctrl.fcn_dw connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ctrl.op_fcn, bypasses[4].bits.fflags.bits.uop.ctrl.op_fcn connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ctrl.imm_sel, bypasses[4].bits.fflags.bits.uop.ctrl.imm_sel connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ctrl.op2_sel, bypasses[4].bits.fflags.bits.uop.ctrl.op2_sel connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ctrl.op1_sel, bypasses[4].bits.fflags.bits.uop.ctrl.op1_sel connect iregister_read.io.bypass[4].bits.fflags.bits.uop.ctrl.br_type, bypasses[4].bits.fflags.bits.uop.ctrl.br_type connect iregister_read.io.bypass[4].bits.fflags.bits.uop.fu_code, bypasses[4].bits.fflags.bits.uop.fu_code connect iregister_read.io.bypass[4].bits.fflags.bits.uop.iq_type, bypasses[4].bits.fflags.bits.uop.iq_type connect iregister_read.io.bypass[4].bits.fflags.bits.uop.debug_pc, bypasses[4].bits.fflags.bits.uop.debug_pc connect iregister_read.io.bypass[4].bits.fflags.bits.uop.is_rvc, bypasses[4].bits.fflags.bits.uop.is_rvc connect iregister_read.io.bypass[4].bits.fflags.bits.uop.debug_inst, bypasses[4].bits.fflags.bits.uop.debug_inst connect iregister_read.io.bypass[4].bits.fflags.bits.uop.inst, bypasses[4].bits.fflags.bits.uop.inst connect iregister_read.io.bypass[4].bits.fflags.bits.uop.uopc, bypasses[4].bits.fflags.bits.uop.uopc connect iregister_read.io.bypass[4].bits.fflags.valid, bypasses[4].bits.fflags.valid connect iregister_read.io.bypass[4].bits.predicated, bypasses[4].bits.predicated connect iregister_read.io.bypass[4].bits.data, bypasses[4].bits.data connect iregister_read.io.bypass[4].bits.uop.debug_tsrc, bypasses[4].bits.uop.debug_tsrc connect iregister_read.io.bypass[4].bits.uop.debug_fsrc, bypasses[4].bits.uop.debug_fsrc connect iregister_read.io.bypass[4].bits.uop.bp_xcpt_if, bypasses[4].bits.uop.bp_xcpt_if connect iregister_read.io.bypass[4].bits.uop.bp_debug_if, bypasses[4].bits.uop.bp_debug_if connect iregister_read.io.bypass[4].bits.uop.xcpt_ma_if, bypasses[4].bits.uop.xcpt_ma_if connect iregister_read.io.bypass[4].bits.uop.xcpt_ae_if, bypasses[4].bits.uop.xcpt_ae_if connect iregister_read.io.bypass[4].bits.uop.xcpt_pf_if, bypasses[4].bits.uop.xcpt_pf_if connect iregister_read.io.bypass[4].bits.uop.fp_single, bypasses[4].bits.uop.fp_single connect iregister_read.io.bypass[4].bits.uop.fp_val, bypasses[4].bits.uop.fp_val connect iregister_read.io.bypass[4].bits.uop.frs3_en, bypasses[4].bits.uop.frs3_en connect iregister_read.io.bypass[4].bits.uop.lrs2_rtype, bypasses[4].bits.uop.lrs2_rtype connect iregister_read.io.bypass[4].bits.uop.lrs1_rtype, bypasses[4].bits.uop.lrs1_rtype connect iregister_read.io.bypass[4].bits.uop.dst_rtype, bypasses[4].bits.uop.dst_rtype connect iregister_read.io.bypass[4].bits.uop.ldst_val, bypasses[4].bits.uop.ldst_val connect iregister_read.io.bypass[4].bits.uop.lrs3, bypasses[4].bits.uop.lrs3 connect iregister_read.io.bypass[4].bits.uop.lrs2, bypasses[4].bits.uop.lrs2 connect iregister_read.io.bypass[4].bits.uop.lrs1, bypasses[4].bits.uop.lrs1 connect iregister_read.io.bypass[4].bits.uop.ldst, bypasses[4].bits.uop.ldst connect iregister_read.io.bypass[4].bits.uop.ldst_is_rs1, bypasses[4].bits.uop.ldst_is_rs1 connect iregister_read.io.bypass[4].bits.uop.flush_on_commit, bypasses[4].bits.uop.flush_on_commit connect iregister_read.io.bypass[4].bits.uop.is_unique, bypasses[4].bits.uop.is_unique connect iregister_read.io.bypass[4].bits.uop.is_sys_pc2epc, bypasses[4].bits.uop.is_sys_pc2epc connect iregister_read.io.bypass[4].bits.uop.uses_stq, bypasses[4].bits.uop.uses_stq connect iregister_read.io.bypass[4].bits.uop.uses_ldq, bypasses[4].bits.uop.uses_ldq connect iregister_read.io.bypass[4].bits.uop.is_amo, bypasses[4].bits.uop.is_amo connect iregister_read.io.bypass[4].bits.uop.is_fencei, bypasses[4].bits.uop.is_fencei connect iregister_read.io.bypass[4].bits.uop.is_fence, bypasses[4].bits.uop.is_fence connect iregister_read.io.bypass[4].bits.uop.mem_signed, bypasses[4].bits.uop.mem_signed connect iregister_read.io.bypass[4].bits.uop.mem_size, bypasses[4].bits.uop.mem_size connect iregister_read.io.bypass[4].bits.uop.mem_cmd, bypasses[4].bits.uop.mem_cmd connect iregister_read.io.bypass[4].bits.uop.bypassable, bypasses[4].bits.uop.bypassable connect iregister_read.io.bypass[4].bits.uop.exc_cause, bypasses[4].bits.uop.exc_cause connect iregister_read.io.bypass[4].bits.uop.exception, bypasses[4].bits.uop.exception connect iregister_read.io.bypass[4].bits.uop.stale_pdst, bypasses[4].bits.uop.stale_pdst connect iregister_read.io.bypass[4].bits.uop.ppred_busy, bypasses[4].bits.uop.ppred_busy connect iregister_read.io.bypass[4].bits.uop.prs3_busy, bypasses[4].bits.uop.prs3_busy connect iregister_read.io.bypass[4].bits.uop.prs2_busy, bypasses[4].bits.uop.prs2_busy connect iregister_read.io.bypass[4].bits.uop.prs1_busy, bypasses[4].bits.uop.prs1_busy connect iregister_read.io.bypass[4].bits.uop.ppred, bypasses[4].bits.uop.ppred connect iregister_read.io.bypass[4].bits.uop.prs3, bypasses[4].bits.uop.prs3 connect iregister_read.io.bypass[4].bits.uop.prs2, bypasses[4].bits.uop.prs2 connect iregister_read.io.bypass[4].bits.uop.prs1, bypasses[4].bits.uop.prs1 connect iregister_read.io.bypass[4].bits.uop.pdst, bypasses[4].bits.uop.pdst connect iregister_read.io.bypass[4].bits.uop.rxq_idx, bypasses[4].bits.uop.rxq_idx connect iregister_read.io.bypass[4].bits.uop.stq_idx, bypasses[4].bits.uop.stq_idx connect iregister_read.io.bypass[4].bits.uop.ldq_idx, bypasses[4].bits.uop.ldq_idx connect iregister_read.io.bypass[4].bits.uop.rob_idx, bypasses[4].bits.uop.rob_idx connect iregister_read.io.bypass[4].bits.uop.csr_addr, bypasses[4].bits.uop.csr_addr connect iregister_read.io.bypass[4].bits.uop.imm_packed, bypasses[4].bits.uop.imm_packed connect iregister_read.io.bypass[4].bits.uop.taken, bypasses[4].bits.uop.taken connect iregister_read.io.bypass[4].bits.uop.pc_lob, bypasses[4].bits.uop.pc_lob connect iregister_read.io.bypass[4].bits.uop.edge_inst, bypasses[4].bits.uop.edge_inst connect iregister_read.io.bypass[4].bits.uop.ftq_idx, bypasses[4].bits.uop.ftq_idx connect iregister_read.io.bypass[4].bits.uop.br_tag, bypasses[4].bits.uop.br_tag connect iregister_read.io.bypass[4].bits.uop.br_mask, bypasses[4].bits.uop.br_mask connect iregister_read.io.bypass[4].bits.uop.is_sfb, bypasses[4].bits.uop.is_sfb connect iregister_read.io.bypass[4].bits.uop.is_jal, bypasses[4].bits.uop.is_jal connect iregister_read.io.bypass[4].bits.uop.is_jalr, bypasses[4].bits.uop.is_jalr connect iregister_read.io.bypass[4].bits.uop.is_br, bypasses[4].bits.uop.is_br connect iregister_read.io.bypass[4].bits.uop.iw_p2_poisoned, bypasses[4].bits.uop.iw_p2_poisoned connect iregister_read.io.bypass[4].bits.uop.iw_p1_poisoned, bypasses[4].bits.uop.iw_p1_poisoned connect iregister_read.io.bypass[4].bits.uop.iw_state, bypasses[4].bits.uop.iw_state connect iregister_read.io.bypass[4].bits.uop.ctrl.is_std, bypasses[4].bits.uop.ctrl.is_std connect iregister_read.io.bypass[4].bits.uop.ctrl.is_sta, bypasses[4].bits.uop.ctrl.is_sta connect iregister_read.io.bypass[4].bits.uop.ctrl.is_load, bypasses[4].bits.uop.ctrl.is_load connect iregister_read.io.bypass[4].bits.uop.ctrl.csr_cmd, bypasses[4].bits.uop.ctrl.csr_cmd connect iregister_read.io.bypass[4].bits.uop.ctrl.fcn_dw, bypasses[4].bits.uop.ctrl.fcn_dw connect iregister_read.io.bypass[4].bits.uop.ctrl.op_fcn, bypasses[4].bits.uop.ctrl.op_fcn connect iregister_read.io.bypass[4].bits.uop.ctrl.imm_sel, bypasses[4].bits.uop.ctrl.imm_sel connect iregister_read.io.bypass[4].bits.uop.ctrl.op2_sel, bypasses[4].bits.uop.ctrl.op2_sel connect iregister_read.io.bypass[4].bits.uop.ctrl.op1_sel, bypasses[4].bits.uop.ctrl.op1_sel connect iregister_read.io.bypass[4].bits.uop.ctrl.br_type, bypasses[4].bits.uop.ctrl.br_type connect iregister_read.io.bypass[4].bits.uop.fu_code, bypasses[4].bits.uop.fu_code connect iregister_read.io.bypass[4].bits.uop.iq_type, bypasses[4].bits.uop.iq_type connect iregister_read.io.bypass[4].bits.uop.debug_pc, bypasses[4].bits.uop.debug_pc connect iregister_read.io.bypass[4].bits.uop.is_rvc, bypasses[4].bits.uop.is_rvc connect iregister_read.io.bypass[4].bits.uop.debug_inst, bypasses[4].bits.uop.debug_inst connect iregister_read.io.bypass[4].bits.uop.inst, bypasses[4].bits.uop.inst connect iregister_read.io.bypass[4].bits.uop.uopc, bypasses[4].bits.uop.uopc connect iregister_read.io.bypass[4].valid, bypasses[4].valid connect iregister_read.io.pred_bypass[0].bits.fflags.bits.flags, pred_bypasses[0].bits.fflags.bits.flags connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.debug_tsrc, pred_bypasses[0].bits.fflags.bits.uop.debug_tsrc connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.debug_fsrc, pred_bypasses[0].bits.fflags.bits.uop.debug_fsrc connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.bp_xcpt_if, pred_bypasses[0].bits.fflags.bits.uop.bp_xcpt_if connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.bp_debug_if, pred_bypasses[0].bits.fflags.bits.uop.bp_debug_if connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.xcpt_ma_if, pred_bypasses[0].bits.fflags.bits.uop.xcpt_ma_if connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.xcpt_ae_if, pred_bypasses[0].bits.fflags.bits.uop.xcpt_ae_if connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.xcpt_pf_if, pred_bypasses[0].bits.fflags.bits.uop.xcpt_pf_if connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.fp_single, pred_bypasses[0].bits.fflags.bits.uop.fp_single connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.fp_val, pred_bypasses[0].bits.fflags.bits.uop.fp_val connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.frs3_en, pred_bypasses[0].bits.fflags.bits.uop.frs3_en connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.lrs2_rtype, pred_bypasses[0].bits.fflags.bits.uop.lrs2_rtype connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.lrs1_rtype, pred_bypasses[0].bits.fflags.bits.uop.lrs1_rtype connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.dst_rtype, pred_bypasses[0].bits.fflags.bits.uop.dst_rtype connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ldst_val, pred_bypasses[0].bits.fflags.bits.uop.ldst_val connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.lrs3, pred_bypasses[0].bits.fflags.bits.uop.lrs3 connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.lrs2, pred_bypasses[0].bits.fflags.bits.uop.lrs2 connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.lrs1, pred_bypasses[0].bits.fflags.bits.uop.lrs1 connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ldst, pred_bypasses[0].bits.fflags.bits.uop.ldst connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ldst_is_rs1, pred_bypasses[0].bits.fflags.bits.uop.ldst_is_rs1 connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.flush_on_commit, pred_bypasses[0].bits.fflags.bits.uop.flush_on_commit connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.is_unique, pred_bypasses[0].bits.fflags.bits.uop.is_unique connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.is_sys_pc2epc, pred_bypasses[0].bits.fflags.bits.uop.is_sys_pc2epc connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.uses_stq, pred_bypasses[0].bits.fflags.bits.uop.uses_stq connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.uses_ldq, pred_bypasses[0].bits.fflags.bits.uop.uses_ldq connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.is_amo, pred_bypasses[0].bits.fflags.bits.uop.is_amo connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.is_fencei, pred_bypasses[0].bits.fflags.bits.uop.is_fencei connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.is_fence, pred_bypasses[0].bits.fflags.bits.uop.is_fence connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.mem_signed, pred_bypasses[0].bits.fflags.bits.uop.mem_signed connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.mem_size, pred_bypasses[0].bits.fflags.bits.uop.mem_size connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.mem_cmd, pred_bypasses[0].bits.fflags.bits.uop.mem_cmd connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.bypassable, pred_bypasses[0].bits.fflags.bits.uop.bypassable connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.exc_cause, pred_bypasses[0].bits.fflags.bits.uop.exc_cause connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.exception, pred_bypasses[0].bits.fflags.bits.uop.exception connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.stale_pdst, pred_bypasses[0].bits.fflags.bits.uop.stale_pdst connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ppred_busy, pred_bypasses[0].bits.fflags.bits.uop.ppred_busy connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.prs3_busy, pred_bypasses[0].bits.fflags.bits.uop.prs3_busy connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.prs2_busy, pred_bypasses[0].bits.fflags.bits.uop.prs2_busy connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.prs1_busy, pred_bypasses[0].bits.fflags.bits.uop.prs1_busy connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ppred, pred_bypasses[0].bits.fflags.bits.uop.ppred connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.prs3, pred_bypasses[0].bits.fflags.bits.uop.prs3 connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.prs2, pred_bypasses[0].bits.fflags.bits.uop.prs2 connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.prs1, pred_bypasses[0].bits.fflags.bits.uop.prs1 connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.pdst, pred_bypasses[0].bits.fflags.bits.uop.pdst connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.rxq_idx, pred_bypasses[0].bits.fflags.bits.uop.rxq_idx connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.stq_idx, pred_bypasses[0].bits.fflags.bits.uop.stq_idx connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ldq_idx, pred_bypasses[0].bits.fflags.bits.uop.ldq_idx connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.rob_idx, pred_bypasses[0].bits.fflags.bits.uop.rob_idx connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.csr_addr, pred_bypasses[0].bits.fflags.bits.uop.csr_addr connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.imm_packed, pred_bypasses[0].bits.fflags.bits.uop.imm_packed connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.taken, pred_bypasses[0].bits.fflags.bits.uop.taken connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.pc_lob, pred_bypasses[0].bits.fflags.bits.uop.pc_lob connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.edge_inst, pred_bypasses[0].bits.fflags.bits.uop.edge_inst connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ftq_idx, pred_bypasses[0].bits.fflags.bits.uop.ftq_idx connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.br_tag, pred_bypasses[0].bits.fflags.bits.uop.br_tag connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.br_mask, pred_bypasses[0].bits.fflags.bits.uop.br_mask connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.is_sfb, pred_bypasses[0].bits.fflags.bits.uop.is_sfb connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.is_jal, pred_bypasses[0].bits.fflags.bits.uop.is_jal connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.is_jalr, pred_bypasses[0].bits.fflags.bits.uop.is_jalr connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.is_br, pred_bypasses[0].bits.fflags.bits.uop.is_br connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.iw_p2_poisoned, pred_bypasses[0].bits.fflags.bits.uop.iw_p2_poisoned connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.iw_p1_poisoned, pred_bypasses[0].bits.fflags.bits.uop.iw_p1_poisoned connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.iw_state, pred_bypasses[0].bits.fflags.bits.uop.iw_state connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ctrl.is_std, pred_bypasses[0].bits.fflags.bits.uop.ctrl.is_std connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ctrl.is_sta, pred_bypasses[0].bits.fflags.bits.uop.ctrl.is_sta connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ctrl.is_load, pred_bypasses[0].bits.fflags.bits.uop.ctrl.is_load connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ctrl.csr_cmd, pred_bypasses[0].bits.fflags.bits.uop.ctrl.csr_cmd connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ctrl.fcn_dw, pred_bypasses[0].bits.fflags.bits.uop.ctrl.fcn_dw connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ctrl.op_fcn, pred_bypasses[0].bits.fflags.bits.uop.ctrl.op_fcn connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ctrl.imm_sel, pred_bypasses[0].bits.fflags.bits.uop.ctrl.imm_sel connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ctrl.op2_sel, pred_bypasses[0].bits.fflags.bits.uop.ctrl.op2_sel connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ctrl.op1_sel, pred_bypasses[0].bits.fflags.bits.uop.ctrl.op1_sel connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.ctrl.br_type, pred_bypasses[0].bits.fflags.bits.uop.ctrl.br_type connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.fu_code, pred_bypasses[0].bits.fflags.bits.uop.fu_code connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.iq_type, pred_bypasses[0].bits.fflags.bits.uop.iq_type connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.debug_pc, pred_bypasses[0].bits.fflags.bits.uop.debug_pc connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.is_rvc, pred_bypasses[0].bits.fflags.bits.uop.is_rvc connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.debug_inst, pred_bypasses[0].bits.fflags.bits.uop.debug_inst connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.inst, pred_bypasses[0].bits.fflags.bits.uop.inst connect iregister_read.io.pred_bypass[0].bits.fflags.bits.uop.uopc, pred_bypasses[0].bits.fflags.bits.uop.uopc connect iregister_read.io.pred_bypass[0].bits.fflags.valid, pred_bypasses[0].bits.fflags.valid connect iregister_read.io.pred_bypass[0].bits.predicated, pred_bypasses[0].bits.predicated connect iregister_read.io.pred_bypass[0].bits.data, pred_bypasses[0].bits.data connect iregister_read.io.pred_bypass[0].bits.uop.debug_tsrc, pred_bypasses[0].bits.uop.debug_tsrc connect iregister_read.io.pred_bypass[0].bits.uop.debug_fsrc, pred_bypasses[0].bits.uop.debug_fsrc connect iregister_read.io.pred_bypass[0].bits.uop.bp_xcpt_if, pred_bypasses[0].bits.uop.bp_xcpt_if connect iregister_read.io.pred_bypass[0].bits.uop.bp_debug_if, pred_bypasses[0].bits.uop.bp_debug_if connect iregister_read.io.pred_bypass[0].bits.uop.xcpt_ma_if, pred_bypasses[0].bits.uop.xcpt_ma_if connect iregister_read.io.pred_bypass[0].bits.uop.xcpt_ae_if, pred_bypasses[0].bits.uop.xcpt_ae_if connect iregister_read.io.pred_bypass[0].bits.uop.xcpt_pf_if, pred_bypasses[0].bits.uop.xcpt_pf_if connect iregister_read.io.pred_bypass[0].bits.uop.fp_single, pred_bypasses[0].bits.uop.fp_single connect iregister_read.io.pred_bypass[0].bits.uop.fp_val, pred_bypasses[0].bits.uop.fp_val connect iregister_read.io.pred_bypass[0].bits.uop.frs3_en, pred_bypasses[0].bits.uop.frs3_en connect iregister_read.io.pred_bypass[0].bits.uop.lrs2_rtype, pred_bypasses[0].bits.uop.lrs2_rtype connect iregister_read.io.pred_bypass[0].bits.uop.lrs1_rtype, pred_bypasses[0].bits.uop.lrs1_rtype connect iregister_read.io.pred_bypass[0].bits.uop.dst_rtype, pred_bypasses[0].bits.uop.dst_rtype connect iregister_read.io.pred_bypass[0].bits.uop.ldst_val, pred_bypasses[0].bits.uop.ldst_val connect iregister_read.io.pred_bypass[0].bits.uop.lrs3, pred_bypasses[0].bits.uop.lrs3 connect iregister_read.io.pred_bypass[0].bits.uop.lrs2, pred_bypasses[0].bits.uop.lrs2 connect iregister_read.io.pred_bypass[0].bits.uop.lrs1, pred_bypasses[0].bits.uop.lrs1 connect iregister_read.io.pred_bypass[0].bits.uop.ldst, pred_bypasses[0].bits.uop.ldst connect iregister_read.io.pred_bypass[0].bits.uop.ldst_is_rs1, pred_bypasses[0].bits.uop.ldst_is_rs1 connect iregister_read.io.pred_bypass[0].bits.uop.flush_on_commit, pred_bypasses[0].bits.uop.flush_on_commit connect iregister_read.io.pred_bypass[0].bits.uop.is_unique, pred_bypasses[0].bits.uop.is_unique connect iregister_read.io.pred_bypass[0].bits.uop.is_sys_pc2epc, pred_bypasses[0].bits.uop.is_sys_pc2epc connect iregister_read.io.pred_bypass[0].bits.uop.uses_stq, pred_bypasses[0].bits.uop.uses_stq connect iregister_read.io.pred_bypass[0].bits.uop.uses_ldq, pred_bypasses[0].bits.uop.uses_ldq connect iregister_read.io.pred_bypass[0].bits.uop.is_amo, pred_bypasses[0].bits.uop.is_amo connect iregister_read.io.pred_bypass[0].bits.uop.is_fencei, pred_bypasses[0].bits.uop.is_fencei connect iregister_read.io.pred_bypass[0].bits.uop.is_fence, pred_bypasses[0].bits.uop.is_fence connect iregister_read.io.pred_bypass[0].bits.uop.mem_signed, pred_bypasses[0].bits.uop.mem_signed connect iregister_read.io.pred_bypass[0].bits.uop.mem_size, pred_bypasses[0].bits.uop.mem_size connect iregister_read.io.pred_bypass[0].bits.uop.mem_cmd, pred_bypasses[0].bits.uop.mem_cmd connect iregister_read.io.pred_bypass[0].bits.uop.bypassable, pred_bypasses[0].bits.uop.bypassable connect iregister_read.io.pred_bypass[0].bits.uop.exc_cause, pred_bypasses[0].bits.uop.exc_cause connect iregister_read.io.pred_bypass[0].bits.uop.exception, pred_bypasses[0].bits.uop.exception connect iregister_read.io.pred_bypass[0].bits.uop.stale_pdst, pred_bypasses[0].bits.uop.stale_pdst connect iregister_read.io.pred_bypass[0].bits.uop.ppred_busy, pred_bypasses[0].bits.uop.ppred_busy connect iregister_read.io.pred_bypass[0].bits.uop.prs3_busy, pred_bypasses[0].bits.uop.prs3_busy connect iregister_read.io.pred_bypass[0].bits.uop.prs2_busy, pred_bypasses[0].bits.uop.prs2_busy connect iregister_read.io.pred_bypass[0].bits.uop.prs1_busy, pred_bypasses[0].bits.uop.prs1_busy connect iregister_read.io.pred_bypass[0].bits.uop.ppred, pred_bypasses[0].bits.uop.ppred connect iregister_read.io.pred_bypass[0].bits.uop.prs3, pred_bypasses[0].bits.uop.prs3 connect iregister_read.io.pred_bypass[0].bits.uop.prs2, pred_bypasses[0].bits.uop.prs2 connect iregister_read.io.pred_bypass[0].bits.uop.prs1, pred_bypasses[0].bits.uop.prs1 connect iregister_read.io.pred_bypass[0].bits.uop.pdst, pred_bypasses[0].bits.uop.pdst connect iregister_read.io.pred_bypass[0].bits.uop.rxq_idx, pred_bypasses[0].bits.uop.rxq_idx connect iregister_read.io.pred_bypass[0].bits.uop.stq_idx, pred_bypasses[0].bits.uop.stq_idx connect iregister_read.io.pred_bypass[0].bits.uop.ldq_idx, pred_bypasses[0].bits.uop.ldq_idx connect iregister_read.io.pred_bypass[0].bits.uop.rob_idx, pred_bypasses[0].bits.uop.rob_idx connect iregister_read.io.pred_bypass[0].bits.uop.csr_addr, pred_bypasses[0].bits.uop.csr_addr connect iregister_read.io.pred_bypass[0].bits.uop.imm_packed, pred_bypasses[0].bits.uop.imm_packed connect iregister_read.io.pred_bypass[0].bits.uop.taken, pred_bypasses[0].bits.uop.taken connect iregister_read.io.pred_bypass[0].bits.uop.pc_lob, pred_bypasses[0].bits.uop.pc_lob connect iregister_read.io.pred_bypass[0].bits.uop.edge_inst, pred_bypasses[0].bits.uop.edge_inst connect iregister_read.io.pred_bypass[0].bits.uop.ftq_idx, pred_bypasses[0].bits.uop.ftq_idx connect iregister_read.io.pred_bypass[0].bits.uop.br_tag, pred_bypasses[0].bits.uop.br_tag connect iregister_read.io.pred_bypass[0].bits.uop.br_mask, pred_bypasses[0].bits.uop.br_mask connect iregister_read.io.pred_bypass[0].bits.uop.is_sfb, pred_bypasses[0].bits.uop.is_sfb connect iregister_read.io.pred_bypass[0].bits.uop.is_jal, pred_bypasses[0].bits.uop.is_jal connect iregister_read.io.pred_bypass[0].bits.uop.is_jalr, pred_bypasses[0].bits.uop.is_jalr connect iregister_read.io.pred_bypass[0].bits.uop.is_br, pred_bypasses[0].bits.uop.is_br connect iregister_read.io.pred_bypass[0].bits.uop.iw_p2_poisoned, pred_bypasses[0].bits.uop.iw_p2_poisoned connect iregister_read.io.pred_bypass[0].bits.uop.iw_p1_poisoned, pred_bypasses[0].bits.uop.iw_p1_poisoned connect iregister_read.io.pred_bypass[0].bits.uop.iw_state, pred_bypasses[0].bits.uop.iw_state connect iregister_read.io.pred_bypass[0].bits.uop.ctrl.is_std, pred_bypasses[0].bits.uop.ctrl.is_std connect iregister_read.io.pred_bypass[0].bits.uop.ctrl.is_sta, pred_bypasses[0].bits.uop.ctrl.is_sta connect iregister_read.io.pred_bypass[0].bits.uop.ctrl.is_load, pred_bypasses[0].bits.uop.ctrl.is_load connect iregister_read.io.pred_bypass[0].bits.uop.ctrl.csr_cmd, pred_bypasses[0].bits.uop.ctrl.csr_cmd connect iregister_read.io.pred_bypass[0].bits.uop.ctrl.fcn_dw, pred_bypasses[0].bits.uop.ctrl.fcn_dw connect iregister_read.io.pred_bypass[0].bits.uop.ctrl.op_fcn, pred_bypasses[0].bits.uop.ctrl.op_fcn connect iregister_read.io.pred_bypass[0].bits.uop.ctrl.imm_sel, pred_bypasses[0].bits.uop.ctrl.imm_sel connect iregister_read.io.pred_bypass[0].bits.uop.ctrl.op2_sel, pred_bypasses[0].bits.uop.ctrl.op2_sel connect iregister_read.io.pred_bypass[0].bits.uop.ctrl.op1_sel, pred_bypasses[0].bits.uop.ctrl.op1_sel connect iregister_read.io.pred_bypass[0].bits.uop.ctrl.br_type, pred_bypasses[0].bits.uop.ctrl.br_type connect iregister_read.io.pred_bypass[0].bits.uop.fu_code, pred_bypasses[0].bits.uop.fu_code connect iregister_read.io.pred_bypass[0].bits.uop.iq_type, pred_bypasses[0].bits.uop.iq_type connect iregister_read.io.pred_bypass[0].bits.uop.debug_pc, pred_bypasses[0].bits.uop.debug_pc connect iregister_read.io.pred_bypass[0].bits.uop.is_rvc, pred_bypasses[0].bits.uop.is_rvc connect iregister_read.io.pred_bypass[0].bits.uop.debug_inst, pred_bypasses[0].bits.uop.debug_inst connect iregister_read.io.pred_bypass[0].bits.uop.inst, pred_bypasses[0].bits.uop.inst connect iregister_read.io.pred_bypass[0].bits.uop.uopc, pred_bypasses[0].bits.uop.uopc connect iregister_read.io.pred_bypass[0].valid, pred_bypasses[0].valid connect csr.io.rw.addr, alu_exe_unit_1.io.iresp.bits.uop.csr_addr node _csr_io_rw_cmd_T = mux(alu_exe_unit_1.io.iresp.valid, UInt<1>(0h0), UInt<3>(0h4)) node _csr_io_rw_cmd_T_1 = not(_csr_io_rw_cmd_T) node _csr_io_rw_cmd_T_2 = and(alu_exe_unit_1.io.iresp.bits.uop.ctrl.csr_cmd, _csr_io_rw_cmd_T_1) connect csr.io.rw.cmd, _csr_io_rw_cmd_T_2 connect csr.io.rw.wdata, alu_exe_unit_1.io.iresp.bits.data node _rob_io_csr_replay_valid_T = and(alu_exe_unit_1.io.iresp.valid, csr.io.rw_stall) connect rob.io.csr_replay.valid, _rob_io_csr_replay_valid_T connect rob.io.csr_replay.bits.uop.debug_tsrc, alu_exe_unit_1.io.iresp.bits.uop.debug_tsrc connect rob.io.csr_replay.bits.uop.debug_fsrc, alu_exe_unit_1.io.iresp.bits.uop.debug_fsrc connect rob.io.csr_replay.bits.uop.bp_xcpt_if, alu_exe_unit_1.io.iresp.bits.uop.bp_xcpt_if connect rob.io.csr_replay.bits.uop.bp_debug_if, alu_exe_unit_1.io.iresp.bits.uop.bp_debug_if connect rob.io.csr_replay.bits.uop.xcpt_ma_if, alu_exe_unit_1.io.iresp.bits.uop.xcpt_ma_if connect rob.io.csr_replay.bits.uop.xcpt_ae_if, alu_exe_unit_1.io.iresp.bits.uop.xcpt_ae_if connect rob.io.csr_replay.bits.uop.xcpt_pf_if, alu_exe_unit_1.io.iresp.bits.uop.xcpt_pf_if connect rob.io.csr_replay.bits.uop.fp_single, alu_exe_unit_1.io.iresp.bits.uop.fp_single connect rob.io.csr_replay.bits.uop.fp_val, alu_exe_unit_1.io.iresp.bits.uop.fp_val connect rob.io.csr_replay.bits.uop.frs3_en, alu_exe_unit_1.io.iresp.bits.uop.frs3_en connect rob.io.csr_replay.bits.uop.lrs2_rtype, alu_exe_unit_1.io.iresp.bits.uop.lrs2_rtype connect rob.io.csr_replay.bits.uop.lrs1_rtype, alu_exe_unit_1.io.iresp.bits.uop.lrs1_rtype connect rob.io.csr_replay.bits.uop.dst_rtype, alu_exe_unit_1.io.iresp.bits.uop.dst_rtype connect rob.io.csr_replay.bits.uop.ldst_val, alu_exe_unit_1.io.iresp.bits.uop.ldst_val connect rob.io.csr_replay.bits.uop.lrs3, alu_exe_unit_1.io.iresp.bits.uop.lrs3 connect rob.io.csr_replay.bits.uop.lrs2, alu_exe_unit_1.io.iresp.bits.uop.lrs2 connect rob.io.csr_replay.bits.uop.lrs1, alu_exe_unit_1.io.iresp.bits.uop.lrs1 connect rob.io.csr_replay.bits.uop.ldst, alu_exe_unit_1.io.iresp.bits.uop.ldst connect rob.io.csr_replay.bits.uop.ldst_is_rs1, alu_exe_unit_1.io.iresp.bits.uop.ldst_is_rs1 connect rob.io.csr_replay.bits.uop.flush_on_commit, alu_exe_unit_1.io.iresp.bits.uop.flush_on_commit connect rob.io.csr_replay.bits.uop.is_unique, alu_exe_unit_1.io.iresp.bits.uop.is_unique connect rob.io.csr_replay.bits.uop.is_sys_pc2epc, alu_exe_unit_1.io.iresp.bits.uop.is_sys_pc2epc connect rob.io.csr_replay.bits.uop.uses_stq, alu_exe_unit_1.io.iresp.bits.uop.uses_stq connect rob.io.csr_replay.bits.uop.uses_ldq, alu_exe_unit_1.io.iresp.bits.uop.uses_ldq connect rob.io.csr_replay.bits.uop.is_amo, alu_exe_unit_1.io.iresp.bits.uop.is_amo connect rob.io.csr_replay.bits.uop.is_fencei, alu_exe_unit_1.io.iresp.bits.uop.is_fencei connect rob.io.csr_replay.bits.uop.is_fence, alu_exe_unit_1.io.iresp.bits.uop.is_fence connect rob.io.csr_replay.bits.uop.mem_signed, alu_exe_unit_1.io.iresp.bits.uop.mem_signed connect rob.io.csr_replay.bits.uop.mem_size, alu_exe_unit_1.io.iresp.bits.uop.mem_size connect rob.io.csr_replay.bits.uop.mem_cmd, alu_exe_unit_1.io.iresp.bits.uop.mem_cmd connect rob.io.csr_replay.bits.uop.bypassable, alu_exe_unit_1.io.iresp.bits.uop.bypassable connect rob.io.csr_replay.bits.uop.exc_cause, alu_exe_unit_1.io.iresp.bits.uop.exc_cause connect rob.io.csr_replay.bits.uop.exception, alu_exe_unit_1.io.iresp.bits.uop.exception connect rob.io.csr_replay.bits.uop.stale_pdst, alu_exe_unit_1.io.iresp.bits.uop.stale_pdst connect rob.io.csr_replay.bits.uop.ppred_busy, alu_exe_unit_1.io.iresp.bits.uop.ppred_busy connect rob.io.csr_replay.bits.uop.prs3_busy, alu_exe_unit_1.io.iresp.bits.uop.prs3_busy connect rob.io.csr_replay.bits.uop.prs2_busy, alu_exe_unit_1.io.iresp.bits.uop.prs2_busy connect rob.io.csr_replay.bits.uop.prs1_busy, alu_exe_unit_1.io.iresp.bits.uop.prs1_busy connect rob.io.csr_replay.bits.uop.ppred, alu_exe_unit_1.io.iresp.bits.uop.ppred connect rob.io.csr_replay.bits.uop.prs3, alu_exe_unit_1.io.iresp.bits.uop.prs3 connect rob.io.csr_replay.bits.uop.prs2, alu_exe_unit_1.io.iresp.bits.uop.prs2 connect rob.io.csr_replay.bits.uop.prs1, alu_exe_unit_1.io.iresp.bits.uop.prs1 connect rob.io.csr_replay.bits.uop.pdst, alu_exe_unit_1.io.iresp.bits.uop.pdst connect rob.io.csr_replay.bits.uop.rxq_idx, alu_exe_unit_1.io.iresp.bits.uop.rxq_idx connect rob.io.csr_replay.bits.uop.stq_idx, alu_exe_unit_1.io.iresp.bits.uop.stq_idx connect rob.io.csr_replay.bits.uop.ldq_idx, alu_exe_unit_1.io.iresp.bits.uop.ldq_idx connect rob.io.csr_replay.bits.uop.rob_idx, alu_exe_unit_1.io.iresp.bits.uop.rob_idx connect rob.io.csr_replay.bits.uop.csr_addr, alu_exe_unit_1.io.iresp.bits.uop.csr_addr connect rob.io.csr_replay.bits.uop.imm_packed, alu_exe_unit_1.io.iresp.bits.uop.imm_packed connect rob.io.csr_replay.bits.uop.taken, alu_exe_unit_1.io.iresp.bits.uop.taken connect rob.io.csr_replay.bits.uop.pc_lob, alu_exe_unit_1.io.iresp.bits.uop.pc_lob connect rob.io.csr_replay.bits.uop.edge_inst, alu_exe_unit_1.io.iresp.bits.uop.edge_inst connect rob.io.csr_replay.bits.uop.ftq_idx, alu_exe_unit_1.io.iresp.bits.uop.ftq_idx connect rob.io.csr_replay.bits.uop.br_tag, alu_exe_unit_1.io.iresp.bits.uop.br_tag connect rob.io.csr_replay.bits.uop.br_mask, alu_exe_unit_1.io.iresp.bits.uop.br_mask connect rob.io.csr_replay.bits.uop.is_sfb, alu_exe_unit_1.io.iresp.bits.uop.is_sfb connect rob.io.csr_replay.bits.uop.is_jal, alu_exe_unit_1.io.iresp.bits.uop.is_jal connect rob.io.csr_replay.bits.uop.is_jalr, alu_exe_unit_1.io.iresp.bits.uop.is_jalr connect rob.io.csr_replay.bits.uop.is_br, alu_exe_unit_1.io.iresp.bits.uop.is_br connect rob.io.csr_replay.bits.uop.iw_p2_poisoned, alu_exe_unit_1.io.iresp.bits.uop.iw_p2_poisoned connect rob.io.csr_replay.bits.uop.iw_p1_poisoned, alu_exe_unit_1.io.iresp.bits.uop.iw_p1_poisoned connect rob.io.csr_replay.bits.uop.iw_state, alu_exe_unit_1.io.iresp.bits.uop.iw_state connect rob.io.csr_replay.bits.uop.ctrl.is_std, alu_exe_unit_1.io.iresp.bits.uop.ctrl.is_std connect rob.io.csr_replay.bits.uop.ctrl.is_sta, alu_exe_unit_1.io.iresp.bits.uop.ctrl.is_sta connect rob.io.csr_replay.bits.uop.ctrl.is_load, alu_exe_unit_1.io.iresp.bits.uop.ctrl.is_load connect rob.io.csr_replay.bits.uop.ctrl.csr_cmd, alu_exe_unit_1.io.iresp.bits.uop.ctrl.csr_cmd connect rob.io.csr_replay.bits.uop.ctrl.fcn_dw, alu_exe_unit_1.io.iresp.bits.uop.ctrl.fcn_dw connect rob.io.csr_replay.bits.uop.ctrl.op_fcn, alu_exe_unit_1.io.iresp.bits.uop.ctrl.op_fcn connect rob.io.csr_replay.bits.uop.ctrl.imm_sel, alu_exe_unit_1.io.iresp.bits.uop.ctrl.imm_sel connect rob.io.csr_replay.bits.uop.ctrl.op2_sel, alu_exe_unit_1.io.iresp.bits.uop.ctrl.op2_sel connect rob.io.csr_replay.bits.uop.ctrl.op1_sel, alu_exe_unit_1.io.iresp.bits.uop.ctrl.op1_sel connect rob.io.csr_replay.bits.uop.ctrl.br_type, alu_exe_unit_1.io.iresp.bits.uop.ctrl.br_type connect rob.io.csr_replay.bits.uop.fu_code, alu_exe_unit_1.io.iresp.bits.uop.fu_code connect rob.io.csr_replay.bits.uop.iq_type, alu_exe_unit_1.io.iresp.bits.uop.iq_type connect rob.io.csr_replay.bits.uop.debug_pc, alu_exe_unit_1.io.iresp.bits.uop.debug_pc connect rob.io.csr_replay.bits.uop.is_rvc, alu_exe_unit_1.io.iresp.bits.uop.is_rvc connect rob.io.csr_replay.bits.uop.debug_inst, alu_exe_unit_1.io.iresp.bits.uop.debug_inst connect rob.io.csr_replay.bits.uop.inst, alu_exe_unit_1.io.iresp.bits.uop.inst connect rob.io.csr_replay.bits.uop.uopc, alu_exe_unit_1.io.iresp.bits.uop.uopc connect rob.io.csr_replay.bits.cause, UInt<5>(0h11) invalidate rob.io.csr_replay.bits.badvaddr node csr_io_retire_hi = cat(rob.io.commit.arch_valids[2], rob.io.commit.arch_valids[1]) node _csr_io_retire_T = cat(csr_io_retire_hi, rob.io.commit.arch_valids[0]) node _csr_io_retire_T_1 = bits(_csr_io_retire_T, 0, 0) node _csr_io_retire_T_2 = bits(_csr_io_retire_T, 1, 1) node _csr_io_retire_T_3 = bits(_csr_io_retire_T, 2, 2) node _csr_io_retire_T_4 = add(_csr_io_retire_T_2, _csr_io_retire_T_3) node _csr_io_retire_T_5 = bits(_csr_io_retire_T_4, 1, 0) node _csr_io_retire_T_6 = add(_csr_io_retire_T_1, _csr_io_retire_T_5) node _csr_io_retire_T_7 = bits(_csr_io_retire_T_6, 1, 0) reg csr_io_retire_REG : UInt, clock connect csr_io_retire_REG, _csr_io_retire_T_7 connect csr.io.retire, csr_io_retire_REG reg csr_io_exception_REG : UInt<1>, clock connect csr_io_exception_REG, rob.io.com_xcpt.valid connect csr.io.exception, csr_io_exception_REG node _csr_io_pc_T = not(io.ifu.get_pc[0].com_pc) node _csr_io_pc_T_1 = or(_csr_io_pc_T, UInt<6>(0h3f)) node _csr_io_pc_T_2 = not(_csr_io_pc_T_1) reg csr_io_pc_REG : UInt, clock connect csr_io_pc_REG, rob.io.com_xcpt.bits.pc_lob node _csr_io_pc_T_3 = add(_csr_io_pc_T_2, csr_io_pc_REG) node _csr_io_pc_T_4 = tail(_csr_io_pc_T_3, 1) reg csr_io_pc_REG_1 : UInt<1>, clock connect csr_io_pc_REG_1, rob.io.com_xcpt.bits.edge_inst node _csr_io_pc_T_5 = mux(csr_io_pc_REG_1, UInt<2>(0h2), UInt<1>(0h0)) node _csr_io_pc_T_6 = sub(_csr_io_pc_T_4, _csr_io_pc_T_5) node _csr_io_pc_T_7 = tail(_csr_io_pc_T_6, 1) connect csr.io.pc, _csr_io_pc_T_7 reg csr_io_cause_REG : UInt, clock connect csr_io_cause_REG, rob.io.com_xcpt.bits.cause connect csr.io.cause, csr_io_cause_REG connect csr.io.ungated_clock, clock node _tval_valid_T = eq(csr.io.cause, UInt<2>(0h3)) node _tval_valid_T_1 = eq(csr.io.cause, UInt<3>(0h4)) node _tval_valid_T_2 = eq(csr.io.cause, UInt<3>(0h6)) node _tval_valid_T_3 = eq(csr.io.cause, UInt<3>(0h5)) node _tval_valid_T_4 = eq(csr.io.cause, UInt<3>(0h7)) node _tval_valid_T_5 = eq(csr.io.cause, UInt<1>(0h1)) node _tval_valid_T_6 = eq(csr.io.cause, UInt<4>(0hd)) node _tval_valid_T_7 = eq(csr.io.cause, UInt<4>(0hf)) node _tval_valid_T_8 = eq(csr.io.cause, UInt<4>(0hc)) node _tval_valid_T_9 = or(_tval_valid_T, _tval_valid_T_1) node _tval_valid_T_10 = or(_tval_valid_T_9, _tval_valid_T_2) node _tval_valid_T_11 = or(_tval_valid_T_10, _tval_valid_T_3) node _tval_valid_T_12 = or(_tval_valid_T_11, _tval_valid_T_4) node _tval_valid_T_13 = or(_tval_valid_T_12, _tval_valid_T_5) node _tval_valid_T_14 = or(_tval_valid_T_13, _tval_valid_T_6) node _tval_valid_T_15 = or(_tval_valid_T_14, _tval_valid_T_7) node _tval_valid_T_16 = or(_tval_valid_T_15, _tval_valid_T_8) node tval_valid = and(csr.io.exception, _tval_valid_T_16) node _csr_io_tval_a_T = asSInt(rob.io.com_xcpt.bits.badvaddr) node csr_io_tval_a = shr(_csr_io_tval_a_T, 39) node _csr_io_tval_msb_T = eq(csr_io_tval_a, asSInt(UInt<1>(0h0))) node _csr_io_tval_msb_T_1 = eq(csr_io_tval_a, asSInt(UInt<1>(0h1))) node _csr_io_tval_msb_T_2 = or(_csr_io_tval_msb_T, _csr_io_tval_msb_T_1) node _csr_io_tval_msb_T_3 = bits(rob.io.com_xcpt.bits.badvaddr, 39, 39) node _csr_io_tval_msb_T_4 = bits(rob.io.com_xcpt.bits.badvaddr, 38, 38) node _csr_io_tval_msb_T_5 = eq(_csr_io_tval_msb_T_4, UInt<1>(0h0)) node csr_io_tval_msb = mux(_csr_io_tval_msb_T_2, _csr_io_tval_msb_T_3, _csr_io_tval_msb_T_5) node _csr_io_tval_T = bits(rob.io.com_xcpt.bits.badvaddr, 38, 0) node _csr_io_tval_T_1 = cat(csr_io_tval_msb, _csr_io_tval_T) reg csr_io_tval_REG : UInt, clock connect csr_io_tval_REG, _csr_io_tval_T_1 node _csr_io_tval_T_2 = mux(tval_valid, csr_io_tval_REG, UInt<1>(0h0)) connect csr.io.tval, _csr_io_tval_T_2 connect csr.io.fcsr_flags.valid, rob.io.commit.fflags.valid connect csr.io.fcsr_flags.bits, rob.io.commit.fflags.bits connect csr.io.set_fs_dirty, rob.io.commit.fflags.valid connect alu_exe_unit_1.io.fcsr_rm, csr.io.fcsr_rm connect io.fcsr_rm, csr.io.fcsr_rm connect FpPipeline.io.fcsr_rm, csr.io.fcsr_rm connect csr.io.hartid, io.hartid connect csr.io.interrupts.seip, io.interrupts.seip connect csr.io.interrupts.meip, io.interrupts.meip connect csr.io.interrupts.msip, io.interrupts.msip connect csr.io.interrupts.mtip, io.interrupts.mtip connect csr.io.interrupts.debug, io.interrupts.debug invalidate csr.io.htval invalidate csr.io.gva connect memExeUnit.io.req, iregister_read.io.exe_reqs[0] connect alu_exe_unit.io.req, iregister_read.io.exe_reqs[1] connect bypasses[0], alu_exe_unit.io.bypass[0] connect alu_exe_unit_1.io.req, iregister_read.io.exe_reqs[2] connect bypasses[1], alu_exe_unit_1.io.bypass[0] connect alu_exe_unit_2.io.req, iregister_read.io.exe_reqs[3] connect bypasses[2], alu_exe_unit_2.io.bypass[0] connect bypasses[3], alu_exe_unit_2.io.bypass[1] connect bypasses[4], alu_exe_unit_2.io.bypass[2] connect pred_bypasses[0], alu_exe_unit.io.bypass[0] connect io.lsu.dis_uops[0].valid, dis_fire[0] connect io.lsu.dis_uops[0].bits, dis_uops[0] connect io.lsu.dis_uops[1].valid, dis_fire[1] connect io.lsu.dis_uops[1].bits, dis_uops[1] connect io.lsu.dis_uops[2].valid, dis_fire[2] connect io.lsu.dis_uops[2].bits, dis_uops[2] connect io.lsu.commit, rob.io.commit connect io.lsu.commit_load_at_rob_head, rob.io.com_load_is_at_rob_head reg io_lsu_exception_REG : UInt<1>, clock connect io_lsu_exception_REG, rob.io.flush.valid connect io.lsu.exception, io_lsu_exception_REG connect io.lsu.brupdate, brupdate connect io.lsu.rob_head_idx, rob.io.rob_head_idx connect io.lsu.rob_pnr_idx, rob.io.rob_pnr_idx connect io.lsu.tsc_reg, debug_tsc_reg connect io.lsu.fp_stdata.bits, FpPipeline.io.to_sdq.bits connect io.lsu.fp_stdata.valid, FpPipeline.io.to_sdq.valid connect FpPipeline.io.to_sdq.ready, io.lsu.fp_stdata.ready wire iregfile_io_write_ports_0_wport : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<64>}} node _iregfile_io_write_ports_0_wport_valid_T = eq(ll_wbarb.io.out.bits.uop.dst_rtype, UInt<2>(0h0)) node _iregfile_io_write_ports_0_wport_valid_T_1 = and(ll_wbarb.io.out.valid, _iregfile_io_write_ports_0_wport_valid_T) connect iregfile_io_write_ports_0_wport.valid, _iregfile_io_write_ports_0_wport_valid_T_1 connect iregfile_io_write_ports_0_wport.bits.addr, ll_wbarb.io.out.bits.uop.pdst connect iregfile_io_write_ports_0_wport.bits.data, ll_wbarb.io.out.bits.data connect ll_wbarb.io.out.ready, UInt<1>(0h1) connect iregfile.io.write_ports[0].bits.data, iregfile_io_write_ports_0_wport.bits.data connect iregfile.io.write_ports[0].bits.addr, iregfile_io_write_ports_0_wport.bits.addr connect iregfile.io.write_ports[0].valid, iregfile_io_write_ports_0_wport.valid connect ll_wbarb.io.in[0], memExeUnit.io.ll_iresp node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(ll_wbarb.io.in[0].ready, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed\n at core.scala:1147 assert (ll_wbarb.io.in(0).ready) // never backpressure the memory unit.\n") : printf_5 assert(clock, ll_wbarb.io.in[0].ready, UInt<1>(0h1), "") : assert_5 node wbReadsCSR = neq(alu_exe_unit.io.iresp.bits.uop.ctrl.csr_cmd, UInt<3>(0h0)) node _iregfile_io_write_ports_1_valid_T = neq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _iregfile_io_write_ports_1_valid_T_1 = and(alu_exe_unit.io.iresp.valid, _iregfile_io_write_ports_1_valid_T) node _iregfile_io_write_ports_1_valid_T_2 = eq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _iregfile_io_write_ports_1_valid_T_3 = and(_iregfile_io_write_ports_1_valid_T_1, _iregfile_io_write_ports_1_valid_T_2) connect iregfile.io.write_ports[1].valid, _iregfile_io_write_ports_1_valid_T_3 connect iregfile.io.write_ports[1].bits.addr, alu_exe_unit.io.iresp.bits.uop.pdst connect alu_exe_unit.io.iresp.ready, UInt<1>(0h1) connect iregfile.io.write_ports[1].bits.data, alu_exe_unit.io.iresp.bits.data node _T_82 = neq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _T_83 = and(alu_exe_unit.io.iresp.valid, _T_82) node _T_84 = eq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h1)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = asUInt(reset) node _T_88 = eq(_T_87, UInt<1>(0h0)) when _T_88 : node _T_89 = eq(_T_86, UInt<1>(0h0)) when _T_89 : printf(clock, UInt<1>(0h1), "Assertion failed: [fppipeline] An FP writeback is being attempted to the Int Regfile.\n at core.scala:1172 assert (!wbIsValid(RT_FLT), \"[fppipeline] An FP writeback is being attempted to the Int Regfile.\")\n") : printf_6 assert(clock, _T_86, UInt<1>(0h1), "") : assert_6 node _T_90 = neq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _T_91 = eq(_T_90, UInt<1>(0h0)) node _T_92 = and(alu_exe_unit.io.iresp.valid, _T_91) node _T_93 = eq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(_T_94, UInt<1>(0h0)) node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : node _T_98 = eq(_T_95, UInt<1>(0h0)) when _T_98 : printf(clock, UInt<1>(0h1), "Assertion failed: [fppipeline] An Int writeback is being attempted with rf_wen disabled.\n at core.scala:1174 assert (!(wbresp.valid &&\n") : printf_7 assert(clock, _T_95, UInt<1>(0h1), "") : assert_7 node _T_99 = neq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _T_100 = and(alu_exe_unit.io.iresp.valid, _T_99) node _T_101 = neq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _T_102 = and(_T_100, _T_101) node _T_103 = eq(_T_102, UInt<1>(0h0)) node _T_104 = asUInt(reset) node _T_105 = eq(_T_104, UInt<1>(0h0)) when _T_105 : node _T_106 = eq(_T_103, UInt<1>(0h0)) when _T_106 : printf(clock, UInt<1>(0h1), "Assertion failed: [fppipeline] writeback being attempted to Int RF with dst != Int type exe_units(1).iresp\n at core.scala:1179 assert (!(wbresp.valid &&\n") : printf_8 assert(clock, _T_103, UInt<1>(0h1), "") : assert_8 node wbReadsCSR_1 = neq(alu_exe_unit_1.io.iresp.bits.uop.ctrl.csr_cmd, UInt<3>(0h0)) node _iregfile_io_write_ports_2_valid_T = neq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _iregfile_io_write_ports_2_valid_T_1 = and(alu_exe_unit_1.io.iresp.valid, _iregfile_io_write_ports_2_valid_T) node _iregfile_io_write_ports_2_valid_T_2 = eq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _iregfile_io_write_ports_2_valid_T_3 = and(_iregfile_io_write_ports_2_valid_T_1, _iregfile_io_write_ports_2_valid_T_2) connect iregfile.io.write_ports[2].valid, _iregfile_io_write_ports_2_valid_T_3 connect iregfile.io.write_ports[2].bits.addr, alu_exe_unit_1.io.iresp.bits.uop.pdst connect alu_exe_unit_1.io.iresp.ready, UInt<1>(0h1) node _iregfile_io_write_ports_2_bits_data_T = mux(wbReadsCSR_1, csr.io.rw.rdata, alu_exe_unit_1.io.iresp.bits.data) connect iregfile.io.write_ports[2].bits.data, _iregfile_io_write_ports_2_bits_data_T node _T_107 = neq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _T_108 = and(alu_exe_unit_1.io.iresp.valid, _T_107) node _T_109 = eq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h1)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(_T_110, UInt<1>(0h0)) node _T_112 = asUInt(reset) node _T_113 = eq(_T_112, UInt<1>(0h0)) when _T_113 : node _T_114 = eq(_T_111, UInt<1>(0h0)) when _T_114 : printf(clock, UInt<1>(0h1), "Assertion failed: [fppipeline] An FP writeback is being attempted to the Int Regfile.\n at core.scala:1172 assert (!wbIsValid(RT_FLT), \"[fppipeline] An FP writeback is being attempted to the Int Regfile.\")\n") : printf_9 assert(clock, _T_111, UInt<1>(0h1), "") : assert_9 node _T_115 = neq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _T_116 = eq(_T_115, UInt<1>(0h0)) node _T_117 = and(alu_exe_unit_1.io.iresp.valid, _T_116) node _T_118 = eq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: [fppipeline] An Int writeback is being attempted with rf_wen disabled.\n at core.scala:1174 assert (!(wbresp.valid &&\n") : printf_10 assert(clock, _T_120, UInt<1>(0h1), "") : assert_10 node _T_124 = neq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _T_125 = and(alu_exe_unit_1.io.iresp.valid, _T_124) node _T_126 = neq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(_T_127, UInt<1>(0h0)) node _T_129 = asUInt(reset) node _T_130 = eq(_T_129, UInt<1>(0h0)) when _T_130 : node _T_131 = eq(_T_128, UInt<1>(0h0)) when _T_131 : printf(clock, UInt<1>(0h1), "Assertion failed: [fppipeline] writeback being attempted to Int RF with dst != Int type exe_units(2).iresp\n at core.scala:1179 assert (!(wbresp.valid &&\n") : printf_11 assert(clock, _T_128, UInt<1>(0h1), "") : assert_11 node wbReadsCSR_2 = neq(alu_exe_unit_2.io.iresp.bits.uop.ctrl.csr_cmd, UInt<3>(0h0)) node _iregfile_io_write_ports_3_valid_T = neq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _iregfile_io_write_ports_3_valid_T_1 = and(alu_exe_unit_2.io.iresp.valid, _iregfile_io_write_ports_3_valid_T) node _iregfile_io_write_ports_3_valid_T_2 = eq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _iregfile_io_write_ports_3_valid_T_3 = and(_iregfile_io_write_ports_3_valid_T_1, _iregfile_io_write_ports_3_valid_T_2) connect iregfile.io.write_ports[3].valid, _iregfile_io_write_ports_3_valid_T_3 connect iregfile.io.write_ports[3].bits.addr, alu_exe_unit_2.io.iresp.bits.uop.pdst connect alu_exe_unit_2.io.iresp.ready, UInt<1>(0h1) connect iregfile.io.write_ports[3].bits.data, alu_exe_unit_2.io.iresp.bits.data node _T_132 = neq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _T_133 = and(alu_exe_unit_2.io.iresp.valid, _T_132) node _T_134 = eq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h1)) node _T_135 = and(_T_133, _T_134) node _T_136 = eq(_T_135, UInt<1>(0h0)) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: [fppipeline] An FP writeback is being attempted to the Int Regfile.\n at core.scala:1172 assert (!wbIsValid(RT_FLT), \"[fppipeline] An FP writeback is being attempted to the Int Regfile.\")\n") : printf_12 assert(clock, _T_136, UInt<1>(0h1), "") : assert_12 node _T_140 = neq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = and(alu_exe_unit_2.io.iresp.valid, _T_141) node _T_143 = eq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _T_144 = and(_T_142, _T_143) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = asUInt(reset) node _T_147 = eq(_T_146, UInt<1>(0h0)) when _T_147 : node _T_148 = eq(_T_145, UInt<1>(0h0)) when _T_148 : printf(clock, UInt<1>(0h1), "Assertion failed: [fppipeline] An Int writeback is being attempted with rf_wen disabled.\n at core.scala:1174 assert (!(wbresp.valid &&\n") : printf_13 assert(clock, _T_145, UInt<1>(0h1), "") : assert_13 node _T_149 = neq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _T_150 = and(alu_exe_unit_2.io.iresp.valid, _T_149) node _T_151 = neq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _T_152 = and(_T_150, _T_151) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = asUInt(reset) node _T_155 = eq(_T_154, UInt<1>(0h0)) when _T_155 : node _T_156 = eq(_T_153, UInt<1>(0h0)) when _T_156 : printf(clock, UInt<1>(0h1), "Assertion failed: [fppipeline] writeback being attempted to Int RF with dst != Int type exe_units(3).iresp\n at core.scala:1179 assert (!(wbresp.valid &&\n") : printf_14 assert(clock, _T_153, UInt<1>(0h1), "") : assert_14 connect FpPipeline.io.from_int, alu_exe_unit_1.io.ll_fresp connect ll_wbarb.io.in[1], FpPipeline.io.to_int connect FpPipeline.io.ll_wports[0], memExeUnit.io.ll_fresp node _rob_io_wb_resps_0_valid_T = eq(ll_wbarb.io.out.bits.uop.is_amo, UInt<1>(0h0)) node _rob_io_wb_resps_0_valid_T_1 = and(ll_wbarb.io.out.bits.uop.uses_stq, _rob_io_wb_resps_0_valid_T) node _rob_io_wb_resps_0_valid_T_2 = eq(_rob_io_wb_resps_0_valid_T_1, UInt<1>(0h0)) node _rob_io_wb_resps_0_valid_T_3 = and(ll_wbarb.io.out.valid, _rob_io_wb_resps_0_valid_T_2) connect rob.io.wb_resps[0].valid, _rob_io_wb_resps_0_valid_T_3 connect rob.io.wb_resps[0].bits, ll_wbarb.io.out.bits node _rob_io_debug_wb_valids_0_T = neq(ll_wbarb.io.out.bits.uop.dst_rtype, UInt<2>(0h2)) node _rob_io_debug_wb_valids_0_T_1 = and(ll_wbarb.io.out.valid, _rob_io_debug_wb_valids_0_T) connect rob.io.debug_wb_valids[0], _rob_io_debug_wb_valids_0_T_1 connect rob.io.debug_wb_wdata[0], ll_wbarb.io.out.bits.data node _rob_io_wb_resps_1_valid_T = eq(alu_exe_unit.io.iresp.bits.uop.is_amo, UInt<1>(0h0)) node _rob_io_wb_resps_1_valid_T_1 = and(alu_exe_unit.io.iresp.bits.uop.uses_stq, _rob_io_wb_resps_1_valid_T) node _rob_io_wb_resps_1_valid_T_2 = eq(_rob_io_wb_resps_1_valid_T_1, UInt<1>(0h0)) node _rob_io_wb_resps_1_valid_T_3 = and(alu_exe_unit.io.iresp.valid, _rob_io_wb_resps_1_valid_T_2) connect rob.io.wb_resps[1].valid, _rob_io_wb_resps_1_valid_T_3 connect rob.io.wb_resps[1].bits, alu_exe_unit.io.iresp.bits node _rob_io_debug_wb_valids_1_T = neq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _rob_io_debug_wb_valids_1_T_1 = and(alu_exe_unit.io.iresp.valid, _rob_io_debug_wb_valids_1_T) node _rob_io_debug_wb_valids_1_T_2 = eq(alu_exe_unit.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _rob_io_debug_wb_valids_1_T_3 = and(_rob_io_debug_wb_valids_1_T_1, _rob_io_debug_wb_valids_1_T_2) connect rob.io.debug_wb_valids[1], _rob_io_debug_wb_valids_1_T_3 connect rob.io.debug_wb_wdata[1], alu_exe_unit.io.iresp.bits.data node _rob_io_wb_resps_2_valid_T = eq(alu_exe_unit_1.io.iresp.bits.uop.is_amo, UInt<1>(0h0)) node _rob_io_wb_resps_2_valid_T_1 = and(alu_exe_unit_1.io.iresp.bits.uop.uses_stq, _rob_io_wb_resps_2_valid_T) node _rob_io_wb_resps_2_valid_T_2 = eq(_rob_io_wb_resps_2_valid_T_1, UInt<1>(0h0)) node _rob_io_wb_resps_2_valid_T_3 = and(alu_exe_unit_1.io.iresp.valid, _rob_io_wb_resps_2_valid_T_2) connect rob.io.wb_resps[2].valid, _rob_io_wb_resps_2_valid_T_3 connect rob.io.wb_resps[2].bits, alu_exe_unit_1.io.iresp.bits node _rob_io_debug_wb_valids_2_T = neq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _rob_io_debug_wb_valids_2_T_1 = and(alu_exe_unit_1.io.iresp.valid, _rob_io_debug_wb_valids_2_T) node _rob_io_debug_wb_valids_2_T_2 = eq(alu_exe_unit_1.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _rob_io_debug_wb_valids_2_T_3 = and(_rob_io_debug_wb_valids_2_T_1, _rob_io_debug_wb_valids_2_T_2) connect rob.io.debug_wb_valids[2], _rob_io_debug_wb_valids_2_T_3 node _rob_io_debug_wb_wdata_2_T = neq(alu_exe_unit_1.io.iresp.bits.uop.ctrl.csr_cmd, UInt<3>(0h0)) node _rob_io_debug_wb_wdata_2_T_1 = mux(_rob_io_debug_wb_wdata_2_T, csr.io.rw.rdata, alu_exe_unit_1.io.iresp.bits.data) connect rob.io.debug_wb_wdata[2], _rob_io_debug_wb_wdata_2_T_1 node _rob_io_wb_resps_3_valid_T = eq(alu_exe_unit_2.io.iresp.bits.uop.is_amo, UInt<1>(0h0)) node _rob_io_wb_resps_3_valid_T_1 = and(alu_exe_unit_2.io.iresp.bits.uop.uses_stq, _rob_io_wb_resps_3_valid_T) node _rob_io_wb_resps_3_valid_T_2 = eq(_rob_io_wb_resps_3_valid_T_1, UInt<1>(0h0)) node _rob_io_wb_resps_3_valid_T_3 = and(alu_exe_unit_2.io.iresp.valid, _rob_io_wb_resps_3_valid_T_2) connect rob.io.wb_resps[3].valid, _rob_io_wb_resps_3_valid_T_3 connect rob.io.wb_resps[3].bits, alu_exe_unit_2.io.iresp.bits node _rob_io_debug_wb_valids_3_T = neq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h2)) node _rob_io_debug_wb_valids_3_T_1 = and(alu_exe_unit_2.io.iresp.valid, _rob_io_debug_wb_valids_3_T) node _rob_io_debug_wb_valids_3_T_2 = eq(alu_exe_unit_2.io.iresp.bits.uop.dst_rtype, UInt<2>(0h0)) node _rob_io_debug_wb_valids_3_T_3 = and(_rob_io_debug_wb_valids_3_T_1, _rob_io_debug_wb_valids_3_T_2) connect rob.io.debug_wb_valids[3], _rob_io_debug_wb_valids_3_T_3 connect rob.io.debug_wb_wdata[3], alu_exe_unit_2.io.iresp.bits.data connect rob.io.wb_resps[4], FpPipeline.io.wakeups[0] connect rob.io.fflags[0], FpPipeline.io.wakeups[0].bits.fflags connect rob.io.debug_wb_valids[4], FpPipeline.io.wakeups[0].valid connect rob.io.debug_wb_wdata[4], FpPipeline.io.debug_wb_wdata[0] node _T_157 = neq(FpPipeline.io.wakeups[0].bits.uop.dst_rtype, UInt<2>(0h1)) node _T_158 = and(FpPipeline.io.wakeups[0].valid, _T_157) node _T_159 = eq(_T_158, UInt<1>(0h0)) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: [core] FP wakeup does not write back to a FP register.\n at core.scala:1266 assert (!(wakeup.valid && wakeup.bits.uop.dst_rtype =/= RT_FLT),\n") : printf_15 assert(clock, _T_159, UInt<1>(0h1), "") : assert_15 node _T_163 = eq(FpPipeline.io.wakeups[0].bits.uop.fp_val, UInt<1>(0h0)) node _T_164 = and(FpPipeline.io.wakeups[0].valid, _T_163) node _T_165 = eq(_T_164, UInt<1>(0h0)) node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(_T_165, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: [core] FP wakeup does not involve an FP instruction.\n at core.scala:1269 assert (!(wakeup.valid && !wakeup.bits.uop.fp_val),\n") : printf_16 assert(clock, _T_165, UInt<1>(0h1), "") : assert_16 connect rob.io.wb_resps[5], FpPipeline.io.wakeups[1] connect rob.io.fflags[1], FpPipeline.io.wakeups[1].bits.fflags connect rob.io.debug_wb_valids[5], FpPipeline.io.wakeups[1].valid connect rob.io.debug_wb_wdata[5], FpPipeline.io.debug_wb_wdata[1] node _T_169 = neq(FpPipeline.io.wakeups[1].bits.uop.dst_rtype, UInt<2>(0h1)) node _T_170 = and(FpPipeline.io.wakeups[1].valid, _T_169) node _T_171 = eq(_T_170, UInt<1>(0h0)) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: [core] FP wakeup does not write back to a FP register.\n at core.scala:1266 assert (!(wakeup.valid && wakeup.bits.uop.dst_rtype =/= RT_FLT),\n") : printf_17 assert(clock, _T_171, UInt<1>(0h1), "") : assert_17 node _T_175 = eq(FpPipeline.io.wakeups[1].bits.uop.fp_val, UInt<1>(0h0)) node _T_176 = and(FpPipeline.io.wakeups[1].valid, _T_175) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = asUInt(reset) node _T_179 = eq(_T_178, UInt<1>(0h0)) when _T_179 : node _T_180 = eq(_T_177, UInt<1>(0h0)) when _T_180 : printf(clock, UInt<1>(0h1), "Assertion failed: [core] FP wakeup does not involve an FP instruction.\n at core.scala:1269 assert (!(wakeup.valid && !wakeup.bits.uop.fp_val),\n") : printf_18 assert(clock, _T_177, UInt<1>(0h1), "") : assert_18 connect rob.io.brupdate, brupdate connect memExeUnit.io.status.uie, csr.io.status.uie connect memExeUnit.io.status.sie, csr.io.status.sie connect memExeUnit.io.status.hie, csr.io.status.hie connect memExeUnit.io.status.mie, csr.io.status.mie connect memExeUnit.io.status.upie, csr.io.status.upie connect memExeUnit.io.status.spie, csr.io.status.spie connect memExeUnit.io.status.ube, csr.io.status.ube connect memExeUnit.io.status.mpie, csr.io.status.mpie connect memExeUnit.io.status.spp, csr.io.status.spp connect memExeUnit.io.status.vs, csr.io.status.vs connect memExeUnit.io.status.mpp, csr.io.status.mpp connect memExeUnit.io.status.fs, csr.io.status.fs connect memExeUnit.io.status.xs, csr.io.status.xs connect memExeUnit.io.status.mprv, csr.io.status.mprv connect memExeUnit.io.status.sum, csr.io.status.sum connect memExeUnit.io.status.mxr, csr.io.status.mxr connect memExeUnit.io.status.tvm, csr.io.status.tvm connect memExeUnit.io.status.tw, csr.io.status.tw connect memExeUnit.io.status.tsr, csr.io.status.tsr connect memExeUnit.io.status.zero1, csr.io.status.zero1 connect memExeUnit.io.status.sd_rv32, csr.io.status.sd_rv32 connect memExeUnit.io.status.uxl, csr.io.status.uxl connect memExeUnit.io.status.sxl, csr.io.status.sxl connect memExeUnit.io.status.sbe, csr.io.status.sbe connect memExeUnit.io.status.mbe, csr.io.status.mbe connect memExeUnit.io.status.gva, csr.io.status.gva connect memExeUnit.io.status.mpv, csr.io.status.mpv connect memExeUnit.io.status.zero2, csr.io.status.zero2 connect memExeUnit.io.status.sd, csr.io.status.sd connect memExeUnit.io.status.v, csr.io.status.v connect memExeUnit.io.status.prv, csr.io.status.prv connect memExeUnit.io.status.dv, csr.io.status.dv connect memExeUnit.io.status.dprv, csr.io.status.dprv connect memExeUnit.io.status.isa, csr.io.status.isa connect memExeUnit.io.status.wfi, csr.io.status.wfi connect memExeUnit.io.status.cease, csr.io.status.cease connect memExeUnit.io.status.debug, csr.io.status.debug connect alu_exe_unit.io.status.uie, csr.io.status.uie connect alu_exe_unit.io.status.sie, csr.io.status.sie connect alu_exe_unit.io.status.hie, csr.io.status.hie connect alu_exe_unit.io.status.mie, csr.io.status.mie connect alu_exe_unit.io.status.upie, csr.io.status.upie connect alu_exe_unit.io.status.spie, csr.io.status.spie connect alu_exe_unit.io.status.ube, csr.io.status.ube connect alu_exe_unit.io.status.mpie, csr.io.status.mpie connect alu_exe_unit.io.status.spp, csr.io.status.spp connect alu_exe_unit.io.status.vs, csr.io.status.vs connect alu_exe_unit.io.status.mpp, csr.io.status.mpp connect alu_exe_unit.io.status.fs, csr.io.status.fs connect alu_exe_unit.io.status.xs, csr.io.status.xs connect alu_exe_unit.io.status.mprv, csr.io.status.mprv connect alu_exe_unit.io.status.sum, csr.io.status.sum connect alu_exe_unit.io.status.mxr, csr.io.status.mxr connect alu_exe_unit.io.status.tvm, csr.io.status.tvm connect alu_exe_unit.io.status.tw, csr.io.status.tw connect alu_exe_unit.io.status.tsr, csr.io.status.tsr connect alu_exe_unit.io.status.zero1, csr.io.status.zero1 connect alu_exe_unit.io.status.sd_rv32, csr.io.status.sd_rv32 connect alu_exe_unit.io.status.uxl, csr.io.status.uxl connect alu_exe_unit.io.status.sxl, csr.io.status.sxl connect alu_exe_unit.io.status.sbe, csr.io.status.sbe connect alu_exe_unit.io.status.mbe, csr.io.status.mbe connect alu_exe_unit.io.status.gva, csr.io.status.gva connect alu_exe_unit.io.status.mpv, csr.io.status.mpv connect alu_exe_unit.io.status.zero2, csr.io.status.zero2 connect alu_exe_unit.io.status.sd, csr.io.status.sd connect alu_exe_unit.io.status.v, csr.io.status.v connect alu_exe_unit.io.status.prv, csr.io.status.prv connect alu_exe_unit.io.status.dv, csr.io.status.dv connect alu_exe_unit.io.status.dprv, csr.io.status.dprv connect alu_exe_unit.io.status.isa, csr.io.status.isa connect alu_exe_unit.io.status.wfi, csr.io.status.wfi connect alu_exe_unit.io.status.cease, csr.io.status.cease connect alu_exe_unit.io.status.debug, csr.io.status.debug connect alu_exe_unit_1.io.status.uie, csr.io.status.uie connect alu_exe_unit_1.io.status.sie, csr.io.status.sie connect alu_exe_unit_1.io.status.hie, csr.io.status.hie connect alu_exe_unit_1.io.status.mie, csr.io.status.mie connect alu_exe_unit_1.io.status.upie, csr.io.status.upie connect alu_exe_unit_1.io.status.spie, csr.io.status.spie connect alu_exe_unit_1.io.status.ube, csr.io.status.ube connect alu_exe_unit_1.io.status.mpie, csr.io.status.mpie connect alu_exe_unit_1.io.status.spp, csr.io.status.spp connect alu_exe_unit_1.io.status.vs, csr.io.status.vs connect alu_exe_unit_1.io.status.mpp, csr.io.status.mpp connect alu_exe_unit_1.io.status.fs, csr.io.status.fs connect alu_exe_unit_1.io.status.xs, csr.io.status.xs connect alu_exe_unit_1.io.status.mprv, csr.io.status.mprv connect alu_exe_unit_1.io.status.sum, csr.io.status.sum connect alu_exe_unit_1.io.status.mxr, csr.io.status.mxr connect alu_exe_unit_1.io.status.tvm, csr.io.status.tvm connect alu_exe_unit_1.io.status.tw, csr.io.status.tw connect alu_exe_unit_1.io.status.tsr, csr.io.status.tsr connect alu_exe_unit_1.io.status.zero1, csr.io.status.zero1 connect alu_exe_unit_1.io.status.sd_rv32, csr.io.status.sd_rv32 connect alu_exe_unit_1.io.status.uxl, csr.io.status.uxl connect alu_exe_unit_1.io.status.sxl, csr.io.status.sxl connect alu_exe_unit_1.io.status.sbe, csr.io.status.sbe connect alu_exe_unit_1.io.status.mbe, csr.io.status.mbe connect alu_exe_unit_1.io.status.gva, csr.io.status.gva connect alu_exe_unit_1.io.status.mpv, csr.io.status.mpv connect alu_exe_unit_1.io.status.zero2, csr.io.status.zero2 connect alu_exe_unit_1.io.status.sd, csr.io.status.sd connect alu_exe_unit_1.io.status.v, csr.io.status.v connect alu_exe_unit_1.io.status.prv, csr.io.status.prv connect alu_exe_unit_1.io.status.dv, csr.io.status.dv connect alu_exe_unit_1.io.status.dprv, csr.io.status.dprv connect alu_exe_unit_1.io.status.isa, csr.io.status.isa connect alu_exe_unit_1.io.status.wfi, csr.io.status.wfi connect alu_exe_unit_1.io.status.cease, csr.io.status.cease connect alu_exe_unit_1.io.status.debug, csr.io.status.debug connect alu_exe_unit_2.io.status.uie, csr.io.status.uie connect alu_exe_unit_2.io.status.sie, csr.io.status.sie connect alu_exe_unit_2.io.status.hie, csr.io.status.hie connect alu_exe_unit_2.io.status.mie, csr.io.status.mie connect alu_exe_unit_2.io.status.upie, csr.io.status.upie connect alu_exe_unit_2.io.status.spie, csr.io.status.spie connect alu_exe_unit_2.io.status.ube, csr.io.status.ube connect alu_exe_unit_2.io.status.mpie, csr.io.status.mpie connect alu_exe_unit_2.io.status.spp, csr.io.status.spp connect alu_exe_unit_2.io.status.vs, csr.io.status.vs connect alu_exe_unit_2.io.status.mpp, csr.io.status.mpp connect alu_exe_unit_2.io.status.fs, csr.io.status.fs connect alu_exe_unit_2.io.status.xs, csr.io.status.xs connect alu_exe_unit_2.io.status.mprv, csr.io.status.mprv connect alu_exe_unit_2.io.status.sum, csr.io.status.sum connect alu_exe_unit_2.io.status.mxr, csr.io.status.mxr connect alu_exe_unit_2.io.status.tvm, csr.io.status.tvm connect alu_exe_unit_2.io.status.tw, csr.io.status.tw connect alu_exe_unit_2.io.status.tsr, csr.io.status.tsr connect alu_exe_unit_2.io.status.zero1, csr.io.status.zero1 connect alu_exe_unit_2.io.status.sd_rv32, csr.io.status.sd_rv32 connect alu_exe_unit_2.io.status.uxl, csr.io.status.uxl connect alu_exe_unit_2.io.status.sxl, csr.io.status.sxl connect alu_exe_unit_2.io.status.sbe, csr.io.status.sbe connect alu_exe_unit_2.io.status.mbe, csr.io.status.mbe connect alu_exe_unit_2.io.status.gva, csr.io.status.gva connect alu_exe_unit_2.io.status.mpv, csr.io.status.mpv connect alu_exe_unit_2.io.status.zero2, csr.io.status.zero2 connect alu_exe_unit_2.io.status.sd, csr.io.status.sd connect alu_exe_unit_2.io.status.v, csr.io.status.v connect alu_exe_unit_2.io.status.prv, csr.io.status.prv connect alu_exe_unit_2.io.status.dv, csr.io.status.dv connect alu_exe_unit_2.io.status.dprv, csr.io.status.dprv connect alu_exe_unit_2.io.status.isa, csr.io.status.isa connect alu_exe_unit_2.io.status.wfi, csr.io.status.wfi connect alu_exe_unit_2.io.status.cease, csr.io.status.cease connect alu_exe_unit_2.io.status.debug, csr.io.status.debug connect FpPipeline.io.status.uie, csr.io.status.uie connect FpPipeline.io.status.sie, csr.io.status.sie connect FpPipeline.io.status.hie, csr.io.status.hie connect FpPipeline.io.status.mie, csr.io.status.mie connect FpPipeline.io.status.upie, csr.io.status.upie connect FpPipeline.io.status.spie, csr.io.status.spie connect FpPipeline.io.status.ube, csr.io.status.ube connect FpPipeline.io.status.mpie, csr.io.status.mpie connect FpPipeline.io.status.spp, csr.io.status.spp connect FpPipeline.io.status.vs, csr.io.status.vs connect FpPipeline.io.status.mpp, csr.io.status.mpp connect FpPipeline.io.status.fs, csr.io.status.fs connect FpPipeline.io.status.xs, csr.io.status.xs connect FpPipeline.io.status.mprv, csr.io.status.mprv connect FpPipeline.io.status.sum, csr.io.status.sum connect FpPipeline.io.status.mxr, csr.io.status.mxr connect FpPipeline.io.status.tvm, csr.io.status.tvm connect FpPipeline.io.status.tw, csr.io.status.tw connect FpPipeline.io.status.tsr, csr.io.status.tsr connect FpPipeline.io.status.zero1, csr.io.status.zero1 connect FpPipeline.io.status.sd_rv32, csr.io.status.sd_rv32 connect FpPipeline.io.status.uxl, csr.io.status.uxl connect FpPipeline.io.status.sxl, csr.io.status.sxl connect FpPipeline.io.status.sbe, csr.io.status.sbe connect FpPipeline.io.status.mbe, csr.io.status.mbe connect FpPipeline.io.status.gva, csr.io.status.gva connect FpPipeline.io.status.mpv, csr.io.status.mpv connect FpPipeline.io.status.zero2, csr.io.status.zero2 connect FpPipeline.io.status.sd, csr.io.status.sd connect FpPipeline.io.status.v, csr.io.status.v connect FpPipeline.io.status.prv, csr.io.status.prv connect FpPipeline.io.status.dv, csr.io.status.dv connect FpPipeline.io.status.dprv, csr.io.status.dprv connect FpPipeline.io.status.isa, csr.io.status.isa connect FpPipeline.io.status.wfi, csr.io.status.wfi connect FpPipeline.io.status.cease, csr.io.status.cease connect FpPipeline.io.status.debug, csr.io.status.debug connect memExeUnit.io.status.uie, csr.io.status.uie connect memExeUnit.io.status.sie, csr.io.status.sie connect memExeUnit.io.status.hie, csr.io.status.hie connect memExeUnit.io.status.mie, csr.io.status.mie connect memExeUnit.io.status.upie, csr.io.status.upie connect memExeUnit.io.status.spie, csr.io.status.spie connect memExeUnit.io.status.ube, csr.io.status.ube connect memExeUnit.io.status.mpie, csr.io.status.mpie connect memExeUnit.io.status.spp, csr.io.status.spp connect memExeUnit.io.status.vs, csr.io.status.vs connect memExeUnit.io.status.mpp, csr.io.status.mpp connect memExeUnit.io.status.fs, csr.io.status.fs connect memExeUnit.io.status.xs, csr.io.status.xs connect memExeUnit.io.status.mprv, csr.io.status.mprv connect memExeUnit.io.status.sum, csr.io.status.sum connect memExeUnit.io.status.mxr, csr.io.status.mxr connect memExeUnit.io.status.tvm, csr.io.status.tvm connect memExeUnit.io.status.tw, csr.io.status.tw connect memExeUnit.io.status.tsr, csr.io.status.tsr connect memExeUnit.io.status.zero1, csr.io.status.zero1 connect memExeUnit.io.status.sd_rv32, csr.io.status.sd_rv32 connect memExeUnit.io.status.uxl, csr.io.status.uxl connect memExeUnit.io.status.sxl, csr.io.status.sxl connect memExeUnit.io.status.sbe, csr.io.status.sbe connect memExeUnit.io.status.mbe, csr.io.status.mbe connect memExeUnit.io.status.gva, csr.io.status.gva connect memExeUnit.io.status.mpv, csr.io.status.mpv connect memExeUnit.io.status.zero2, csr.io.status.zero2 connect memExeUnit.io.status.sd, csr.io.status.sd connect memExeUnit.io.status.v, csr.io.status.v connect memExeUnit.io.status.prv, csr.io.status.prv connect memExeUnit.io.status.dv, csr.io.status.dv connect memExeUnit.io.status.dprv, csr.io.status.dprv connect memExeUnit.io.status.isa, csr.io.status.isa connect memExeUnit.io.status.wfi, csr.io.status.wfi connect memExeUnit.io.status.cease, csr.io.status.cease connect memExeUnit.io.status.debug, csr.io.status.debug connect memExeUnit.io.mcontext, csr.io.mcontext connect memExeUnit.io.scontext, csr.io.scontext connect rob.io.lsu_clr_bsy[0].bits, io.lsu.clr_bsy[0].bits connect rob.io.lsu_clr_bsy[0].valid, io.lsu.clr_bsy[0].valid connect rob.io.lsu_clr_bsy[1].bits, io.lsu.clr_bsy[1].bits connect rob.io.lsu_clr_bsy[1].valid, io.lsu.clr_bsy[1].valid connect rob.io.lsu_clr_unsafe[0].bits, io.lsu.clr_unsafe[0].bits connect rob.io.lsu_clr_unsafe[0].valid, io.lsu.clr_unsafe[0].valid connect rob.io.lxcpt, io.lsu.lxcpt node _T_181 = eq(csr.io.singleStep, UInt<1>(0h0)) node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(_T_181, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: [core] single-step is unsupported.\n at core.scala:1297 assert (!(csr.io.singleStep), \"[core] single-step is unsupported.\")\n") : printf_19 assert(clock, _T_181, UInt<1>(0h1), "") : assert_19 reg REG_6 : UInt<1>, clock connect REG_6, rob.io.flush.valid connect FpPipeline.io.flush_pipeline, REG_6 reg memExeUnit_io_req_bits_kill_REG : UInt<1>, clock connect memExeUnit_io_req_bits_kill_REG, rob.io.flush.valid connect memExeUnit.io.req.bits.kill, memExeUnit_io_req_bits_kill_REG reg alu_exe_unit_io_req_bits_kill_REG : UInt<1>, clock connect alu_exe_unit_io_req_bits_kill_REG, rob.io.flush.valid connect alu_exe_unit.io.req.bits.kill, alu_exe_unit_io_req_bits_kill_REG reg alu_exe_unit_io_req_bits_kill_REG_1 : UInt<1>, clock connect alu_exe_unit_io_req_bits_kill_REG_1, rob.io.flush.valid connect alu_exe_unit_1.io.req.bits.kill, alu_exe_unit_io_req_bits_kill_REG_1 reg alu_exe_unit_io_req_bits_kill_REG_2 : UInt<1>, clock connect alu_exe_unit_io_req_bits_kill_REG_2, rob.io.flush.valid connect alu_exe_unit_2.io.req.bits.kill, alu_exe_unit_io_req_bits_kill_REG_2 node _T_185 = eq(rob.io.flush.valid, UInt<1>(0h0)) node _T_186 = and(rob.io.com_xcpt.valid, _T_185) node _T_187 = eq(_T_186, UInt<1>(0h0)) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: [core] exception occurred, but pipeline flush signal not set!\n at core.scala:1313 assert (!(rob.io.com_xcpt.valid && !rob.io.flush.valid),\n") : printf_20 assert(clock, _T_187, UInt<1>(0h1), "") : assert_20 regreset small : UInt<5>, clock, reset, UInt<5>(0h0) node nextSmall = add(small, UInt<1>(0h1)) node _T_191 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_191 : connect small, nextSmall regreset large : UInt<27>, clock, reset, UInt<27>(0h0) node _large_T = bits(nextSmall, 5, 5) node _large_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _large_T_2 = and(_large_T, _large_T_1) when _large_T_2 : node _large_r_T = add(large, UInt<1>(0h1)) node _large_r_T_1 = tail(_large_r_T, 1) connect large, _large_r_T_1 node value = cat(large, small) node hi = cat(rob.io.commit.valids[2], rob.io.commit.valids[1]) node _T_192 = cat(hi, rob.io.commit.valids[0]) node _T_193 = orr(_T_192) node _T_194 = or(_T_193, csr.io.csr_stall) node _T_195 = or(_T_194, io.rocc.busy) node _T_196 = asUInt(reset) node _T_197 = or(_T_195, _T_196) when _T_197 : connect small, UInt<1>(0h0) node _large_T_3 = shr(UInt<1>(0h0), 5) connect large, _large_T_3 node _T_198 = bits(value, 13, 13) node _T_199 = eq(_T_198, UInt<1>(0h0)) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: Pipeline has hung.\n at core.scala:1330 assert (!(idle_cycles.value(13)), \"Pipeline has hung.\")\n") : printf_21 assert(clock, _T_199, UInt<1>(0h1), "") : assert_21 connect FpPipeline.io.debug_tsc_reg, debug_tsc_reg wire coreMonitorBundle : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>} invalidate coreMonitorBundle.inst invalidate coreMonitorBundle.rd1val invalidate coreMonitorBundle.rd1src invalidate coreMonitorBundle.rd0val invalidate coreMonitorBundle.rd0src invalidate coreMonitorBundle.wrenf invalidate coreMonitorBundle.wrenx invalidate coreMonitorBundle.wrdata invalidate coreMonitorBundle.wrdst invalidate coreMonitorBundle.pc invalidate coreMonitorBundle.valid invalidate coreMonitorBundle.timer invalidate coreMonitorBundle.hartid invalidate coreMonitorBundle.priv_mode invalidate coreMonitorBundle.excpt invalidate coreMonitorBundle.reset invalidate coreMonitorBundle.clock connect coreMonitorBundle.clock, clock connect coreMonitorBundle.reset, reset connect io.ptw.ptbr, csr.io.ptbr connect io.ptw.status, csr.io.status connect io.ptw.pmp, csr.io.pmp connect io.ptw.sfence.bits.hg, io.ifu.sfence.bits.hg connect io.ptw.sfence.bits.hv, io.ifu.sfence.bits.hv connect io.ptw.sfence.bits.asid, io.ifu.sfence.bits.asid connect io.ptw.sfence.bits.addr, io.ifu.sfence.bits.addr connect io.ptw.sfence.bits.rs2, io.ifu.sfence.bits.rs2 connect io.ptw.sfence.bits.rs1, io.ifu.sfence.bits.rs1 connect io.ptw.sfence.valid, io.ifu.sfence.valid invalidate io.rocc.exception invalidate io.rocc.interrupt invalidate io.rocc.busy invalidate io.rocc.mem.clock_enabled invalidate io.rocc.mem.keep_clock_enabled invalidate io.rocc.mem.perf.storeBufferEmptyAfterStore invalidate io.rocc.mem.perf.storeBufferEmptyAfterLoad invalidate io.rocc.mem.perf.canAcceptLoadThenLoad invalidate io.rocc.mem.perf.canAcceptStoreThenRMW invalidate io.rocc.mem.perf.canAcceptStoreThenLoad invalidate io.rocc.mem.perf.blocked invalidate io.rocc.mem.perf.tlbMiss invalidate io.rocc.mem.perf.grant invalidate io.rocc.mem.perf.release invalidate io.rocc.mem.perf.acquire invalidate io.rocc.mem.store_pending invalidate io.rocc.mem.ordered invalidate io.rocc.mem.s2_gpa_is_pte invalidate io.rocc.mem.s2_gpa invalidate io.rocc.mem.s2_xcpt.ae.st invalidate io.rocc.mem.s2_xcpt.ae.ld invalidate io.rocc.mem.s2_xcpt.gf.st invalidate io.rocc.mem.s2_xcpt.gf.ld invalidate io.rocc.mem.s2_xcpt.pf.st invalidate io.rocc.mem.s2_xcpt.pf.ld invalidate io.rocc.mem.s2_xcpt.ma.st invalidate io.rocc.mem.s2_xcpt.ma.ld invalidate io.rocc.mem.replay_next invalidate io.rocc.mem.resp.bits.store_data invalidate io.rocc.mem.resp.bits.data_raw invalidate io.rocc.mem.resp.bits.data_word_bypass invalidate io.rocc.mem.resp.bits.has_data invalidate io.rocc.mem.resp.bits.replay invalidate io.rocc.mem.resp.bits.mask invalidate io.rocc.mem.resp.bits.data invalidate io.rocc.mem.resp.bits.dv invalidate io.rocc.mem.resp.bits.dprv invalidate io.rocc.mem.resp.bits.signed invalidate io.rocc.mem.resp.bits.size invalidate io.rocc.mem.resp.bits.cmd invalidate io.rocc.mem.resp.bits.tag invalidate io.rocc.mem.resp.bits.addr invalidate io.rocc.mem.resp.valid invalidate io.rocc.mem.s2_paddr invalidate io.rocc.mem.s2_uncached invalidate io.rocc.mem.s2_kill invalidate io.rocc.mem.s2_nack_cause_raw invalidate io.rocc.mem.s2_nack invalidate io.rocc.mem.s1_data.mask invalidate io.rocc.mem.s1_data.data invalidate io.rocc.mem.s1_kill invalidate io.rocc.mem.req.bits.mask invalidate io.rocc.mem.req.bits.data invalidate io.rocc.mem.req.bits.no_xcpt invalidate io.rocc.mem.req.bits.no_alloc invalidate io.rocc.mem.req.bits.no_resp invalidate io.rocc.mem.req.bits.phys invalidate io.rocc.mem.req.bits.dv invalidate io.rocc.mem.req.bits.dprv invalidate io.rocc.mem.req.bits.signed invalidate io.rocc.mem.req.bits.size invalidate io.rocc.mem.req.bits.cmd invalidate io.rocc.mem.req.bits.tag invalidate io.rocc.mem.req.bits.addr invalidate io.rocc.mem.req.valid invalidate io.rocc.mem.req.ready invalidate io.rocc.resp.bits.data invalidate io.rocc.resp.bits.rd invalidate io.rocc.resp.valid invalidate io.rocc.resp.ready invalidate io.rocc.cmd.bits.status.uie invalidate io.rocc.cmd.bits.status.sie invalidate io.rocc.cmd.bits.status.hie invalidate io.rocc.cmd.bits.status.mie invalidate io.rocc.cmd.bits.status.upie invalidate io.rocc.cmd.bits.status.spie invalidate io.rocc.cmd.bits.status.ube invalidate io.rocc.cmd.bits.status.mpie invalidate io.rocc.cmd.bits.status.spp invalidate io.rocc.cmd.bits.status.vs invalidate io.rocc.cmd.bits.status.mpp invalidate io.rocc.cmd.bits.status.fs invalidate io.rocc.cmd.bits.status.xs invalidate io.rocc.cmd.bits.status.mprv invalidate io.rocc.cmd.bits.status.sum invalidate io.rocc.cmd.bits.status.mxr invalidate io.rocc.cmd.bits.status.tvm invalidate io.rocc.cmd.bits.status.tw invalidate io.rocc.cmd.bits.status.tsr invalidate io.rocc.cmd.bits.status.zero1 invalidate io.rocc.cmd.bits.status.sd_rv32 invalidate io.rocc.cmd.bits.status.uxl invalidate io.rocc.cmd.bits.status.sxl invalidate io.rocc.cmd.bits.status.sbe invalidate io.rocc.cmd.bits.status.mbe invalidate io.rocc.cmd.bits.status.gva invalidate io.rocc.cmd.bits.status.mpv invalidate io.rocc.cmd.bits.status.zero2 invalidate io.rocc.cmd.bits.status.sd invalidate io.rocc.cmd.bits.status.v invalidate io.rocc.cmd.bits.status.prv invalidate io.rocc.cmd.bits.status.dv invalidate io.rocc.cmd.bits.status.dprv invalidate io.rocc.cmd.bits.status.isa invalidate io.rocc.cmd.bits.status.wfi invalidate io.rocc.cmd.bits.status.cease invalidate io.rocc.cmd.bits.status.debug invalidate io.rocc.cmd.bits.rs2 invalidate io.rocc.cmd.bits.rs1 invalidate io.rocc.cmd.bits.inst.opcode invalidate io.rocc.cmd.bits.inst.rd invalidate io.rocc.cmd.bits.inst.xs2 invalidate io.rocc.cmd.bits.inst.xs1 invalidate io.rocc.cmd.bits.inst.xd invalidate io.rocc.cmd.bits.inst.rs1 invalidate io.rocc.cmd.bits.inst.rs2 invalidate io.rocc.cmd.bits.inst.funct invalidate io.rocc.cmd.valid invalidate io.rocc.cmd.ready node _io_rocc_exception_T = orr(csr.io.status.xs) node _io_rocc_exception_T_1 = and(csr.io.exception, _io_rocc_exception_T) connect io.rocc.exception, _io_rocc_exception_T_1 invalidate io.trace.custom.rob_empty invalidate io.trace.time invalidate io.trace.insns[0].tval invalidate io.trace.insns[0].cause invalidate io.trace.insns[0].interrupt invalidate io.trace.insns[0].exception invalidate io.trace.insns[0].priv invalidate io.trace.insns[0].insn invalidate io.trace.insns[0].iaddr invalidate io.trace.insns[0].valid invalidate io.trace.insns[1].tval invalidate io.trace.insns[1].cause invalidate io.trace.insns[1].interrupt invalidate io.trace.insns[1].exception invalidate io.trace.insns[1].priv invalidate io.trace.insns[1].insn invalidate io.trace.insns[1].iaddr invalidate io.trace.insns[1].valid invalidate io.trace.insns[2].tval invalidate io.trace.insns[2].cause invalidate io.trace.insns[2].interrupt invalidate io.trace.insns[2].exception invalidate io.trace.insns[2].priv invalidate io.trace.insns[2].insn invalidate io.trace.insns[2].iaddr invalidate io.trace.insns[2].valid connect io.trace.time, csr.io.time connect io.trace.insns[0].valid, UInt<1>(0h0) connect io.trace.insns[1].valid, UInt<1>(0h0) connect io.trace.insns[2].valid, UInt<1>(0h0) connect io.trace.custom.rob_empty, rob.io.empty invalidate io.ifu.debug_ftq_idx[0] invalidate io.ifu.debug_ftq_idx[1] invalidate io.ifu.debug_ftq_idx[2]	module BoomCore_1( // @[core.scala:51:7] input clock, // @[core.scala:51:7] input reset, // @[core.scala:51:7] input [1:0] io_hartid, // @[core.scala:54:14] input io_interrupts_debug, // @[core.scala:54:14] input io_interrupts_mtip, // @[core.scala:54:14] input io_interrupts_msip, // @[core.scala:54:14] input io_interrupts_meip, // @[core.scala:54:14] input io_interrupts_seip, // @[core.scala:54:14] output io_ifu_fetchpacket_ready, // @[core.scala:54:14] input io_ifu_fetchpacket_valid, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_valid, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_0_bits_inst, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_inst, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_is_rvc, // @[core.scala:54:14] input [39:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_pc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_is_sfb, // @[core.scala:54:14] input [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_edge_inst, // @[core.scala:54:14] input [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pc_lob, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_taken, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if, // @[core.scala:54:14] input [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_valid, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_1_bits_inst, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_inst, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_is_rvc, // @[core.scala:54:14] input [39:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_pc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_is_sfb, // @[core.scala:54:14] input [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_edge_inst, // @[core.scala:54:14] input [5:0] io_ifu_fetchpacket_bits_uops_1_bits_pc_lob, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_taken, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if, // @[core.scala:54:14] input [1:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_valid, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_2_bits_inst, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_inst, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_is_rvc, // @[core.scala:54:14] input [39:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_pc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_is_sfb, // @[core.scala:54:14] input [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_edge_inst, // @[core.scala:54:14] input [5:0] io_ifu_fetchpacket_bits_uops_2_bits_pc_lob, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_taken, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if, // @[core.scala:54:14] input [1:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc, // @[core.scala:54:14] output [4:0] io_ifu_get_pc_0_ftq_idx, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_cfi_idx_valid, // @[core.scala:54:14] input [2:0] io_ifu_get_pc_0_entry_cfi_idx_bits, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_cfi_taken, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_cfi_mispredicted, // @[core.scala:54:14] input [2:0] io_ifu_get_pc_0_entry_cfi_type, // @[core.scala:54:14] input [7:0] io_ifu_get_pc_0_entry_br_mask, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_cfi_is_call, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_cfi_is_ret, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_cfi_npc_plus4, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_0_entry_ras_top, // @[core.scala:54:14] input [4:0] io_ifu_get_pc_0_entry_ras_idx, // @[core.scala:54:14] input io_ifu_get_pc_0_entry_start_bank, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_0_pc, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_0_com_pc, // @[core.scala:54:14] input io_ifu_get_pc_0_next_val, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_0_next_pc, // @[core.scala:54:14] output [4:0] io_ifu_get_pc_1_ftq_idx, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_cfi_idx_valid, // @[core.scala:54:14] input [2:0] io_ifu_get_pc_1_entry_cfi_idx_bits, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_cfi_taken, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_cfi_mispredicted, // @[core.scala:54:14] input [2:0] io_ifu_get_pc_1_entry_cfi_type, // @[core.scala:54:14] input [7:0] io_ifu_get_pc_1_entry_br_mask, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_cfi_is_call, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_cfi_is_ret, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_cfi_npc_plus4, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_1_entry_ras_top, // @[core.scala:54:14] input [4:0] io_ifu_get_pc_1_entry_ras_idx, // @[core.scala:54:14] input io_ifu_get_pc_1_entry_start_bank, // @[core.scala:54:14] input [63:0] io_ifu_get_pc_1_ghist_old_history, // @[core.scala:54:14] input io_ifu_get_pc_1_ghist_current_saw_branch_not_taken, // @[core.scala:54:14] input io_ifu_get_pc_1_ghist_new_saw_branch_not_taken, // @[core.scala:54:14] input io_ifu_get_pc_1_ghist_new_saw_branch_taken, // @[core.scala:54:14] input [4:0] io_ifu_get_pc_1_ghist_ras_idx, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_1_pc, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_1_com_pc, // @[core.scala:54:14] input io_ifu_get_pc_1_next_val, // @[core.scala:54:14] input [39:0] io_ifu_get_pc_1_next_pc, // @[core.scala:54:14] input [39:0] io_ifu_debug_fetch_pc_0, // @[core.scala:54:14] input [39:0] io_ifu_debug_fetch_pc_1, // @[core.scala:54:14] input [39:0] io_ifu_debug_fetch_pc_2, // @[core.scala:54:14] output io_ifu_status_debug, // @[core.scala:54:14] output io_ifu_status_cease, // @[core.scala:54:14] output io_ifu_status_wfi, // @[core.scala:54:14] output [1:0] io_ifu_status_dprv, // @[core.scala:54:14] output io_ifu_status_dv, // @[core.scala:54:14] output [1:0] io_ifu_status_prv, // @[core.scala:54:14] output io_ifu_status_v, // @[core.scala:54:14] output io_ifu_status_sd, // @[core.scala:54:14] output io_ifu_status_mpv, // @[core.scala:54:14] output io_ifu_status_gva, // @[core.scala:54:14] output io_ifu_status_tsr, // @[core.scala:54:14] output io_ifu_status_tw, // @[core.scala:54:14] output io_ifu_status_tvm, // @[core.scala:54:14] output io_ifu_status_mxr, // @[core.scala:54:14] output io_ifu_status_sum, // @[core.scala:54:14] output io_ifu_status_mprv, // @[core.scala:54:14] output [1:0] io_ifu_status_fs, // @[core.scala:54:14] output [1:0] io_ifu_status_mpp, // @[core.scala:54:14] output io_ifu_status_spp, // @[core.scala:54:14] output io_ifu_status_mpie, // @[core.scala:54:14] output io_ifu_status_spie, // @[core.scala:54:14] output io_ifu_status_mie, // @[core.scala:54:14] output io_ifu_status_sie, // @[core.scala:54:14] output io_ifu_sfence_valid, // @[core.scala:54:14] output io_ifu_sfence_bits_rs1, // @[core.scala:54:14] output io_ifu_sfence_bits_rs2, // @[core.scala:54:14] output [38:0] io_ifu_sfence_bits_addr, // @[core.scala:54:14] output io_ifu_sfence_bits_asid, // @[core.scala:54:14] output [15:0] io_ifu_brupdate_b1_resolve_mask, // @[core.scala:54:14] output [15:0] io_ifu_brupdate_b1_mispredict_mask, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_uopc, // @[core.scala:54:14] output [31:0] io_ifu_brupdate_b2_uop_inst, // @[core.scala:54:14] output [31:0] io_ifu_brupdate_b2_uop_debug_inst, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_ifu_brupdate_b2_uop_debug_pc, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_iq_type, // @[core.scala:54:14] output [9:0] io_ifu_brupdate_b2_uop_fu_code, // @[core.scala:54:14] output [3:0] io_ifu_brupdate_b2_uop_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_ctrl_op_fcn, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_ctrl_csr_cmd, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ctrl_is_load, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ctrl_is_sta, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_iw_state, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iw_p1_poisoned, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iw_p2_poisoned, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_br, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_jalr, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_jal, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_sfb, // @[core.scala:54:14] output [15:0] io_ifu_brupdate_b2_uop_br_mask, // @[core.scala:54:14] output [3:0] io_ifu_brupdate_b2_uop_br_tag, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_ftq_idx, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_pc_lob, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_taken, // @[core.scala:54:14] output [19:0] io_ifu_brupdate_b2_uop_imm_packed, // @[core.scala:54:14] output [11:0] io_ifu_brupdate_b2_uop_csr_addr, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_rob_idx, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_ldq_idx, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_pdst, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_prs1, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_prs2, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_prs3, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_ppred, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_prs1_busy, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_prs2_busy, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_prs3_busy, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_stale_pdst, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_exception, // @[core.scala:54:14] output [63:0] io_ifu_brupdate_b2_uop_exc_cause, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_bypassable, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_mem_size, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_mem_signed, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_fence, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_fencei, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_amo, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_uses_ldq, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_uses_stq, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_unique, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_flush_on_commit, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_ldst, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_lrs1, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_lrs2, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_lrs3, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ldst_val, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_lrs2_rtype, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_frs3_en, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_val, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_single, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_xcpt_pf_if, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_xcpt_ae_if, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_xcpt_ma_if, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_bp_debug_if, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_debug_fsrc, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_debug_tsrc, // @[core.scala:54:14] output io_ifu_brupdate_b2_valid, // @[core.scala:54:14] output io_ifu_brupdate_b2_mispredict, // @[core.scala:54:14] output io_ifu_brupdate_b2_taken, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_cfi_type, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_pc_sel, // @[core.scala:54:14] output [39:0] io_ifu_brupdate_b2_jalr_target, // @[core.scala:54:14] output [20:0] io_ifu_brupdate_b2_target_offset, // @[core.scala:54:14] output io_ifu_redirect_flush, // @[core.scala:54:14] output io_ifu_redirect_val, // @[core.scala:54:14] output [39:0] io_ifu_redirect_pc, // @[core.scala:54:14] output [4:0] io_ifu_redirect_ftq_idx, // @[core.scala:54:14] output [63:0] io_ifu_redirect_ghist_old_history, // @[core.scala:54:14] output io_ifu_redirect_ghist_current_saw_branch_not_taken, // @[core.scala:54:14] output io_ifu_redirect_ghist_new_saw_branch_not_taken, // @[core.scala:54:14] output io_ifu_redirect_ghist_new_saw_branch_taken, // @[core.scala:54:14] output [4:0] io_ifu_redirect_ghist_ras_idx, // @[core.scala:54:14] output io_ifu_commit_valid, // @[core.scala:54:14] output [31:0] io_ifu_commit_bits, // @[core.scala:54:14] output io_ifu_flush_icache, // @[core.scala:54:14] input io_ifu_perf_acquire, // @[core.scala:54:14] input io_ifu_perf_tlbMiss, // @[core.scala:54:14] output [3:0] io_ptw_ptbr_mode, // @[core.scala:54:14] output [43:0] io_ptw_ptbr_ppn, // @[core.scala:54:14] output io_ptw_sfence_valid, // @[core.scala:54:14] output io_ptw_sfence_bits_rs1, // @[core.scala:54:14] output io_ptw_sfence_bits_rs2, // @[core.scala:54:14] output [38:0] io_ptw_sfence_bits_addr, // @[core.scala:54:14] output io_ptw_sfence_bits_asid, // @[core.scala:54:14] output io_ptw_status_debug, // @[core.scala:54:14] output io_ptw_status_cease, // @[core.scala:54:14] output io_ptw_status_wfi, // @[core.scala:54:14] output [1:0] io_ptw_status_dprv, // @[core.scala:54:14] output io_ptw_status_dv, // @[core.scala:54:14] output [1:0] io_ptw_status_prv, // @[core.scala:54:14] output io_ptw_status_v, // @[core.scala:54:14] output io_ptw_status_sd, // @[core.scala:54:14] output io_ptw_status_mpv, // @[core.scala:54:14] output io_ptw_status_gva, // @[core.scala:54:14] output io_ptw_status_tsr, // @[core.scala:54:14] output io_ptw_status_tw, // @[core.scala:54:14] output io_ptw_status_tvm, // @[core.scala:54:14] output io_ptw_status_mxr, // @[core.scala:54:14] output io_ptw_status_sum, // @[core.scala:54:14] output io_ptw_status_mprv, // @[core.scala:54:14] output [1:0] io_ptw_status_fs, // @[core.scala:54:14] output [1:0] io_ptw_status_mpp, // @[core.scala:54:14] output io_ptw_status_spp, // @[core.scala:54:14] output io_ptw_status_mpie, // @[core.scala:54:14] output io_ptw_status_spie, // @[core.scala:54:14] output io_ptw_status_mie, // @[core.scala:54:14] output io_ptw_status_sie, // @[core.scala:54:14] output io_ptw_pmp_0_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_0_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_0_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_0_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_0_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_0_mask, // @[core.scala:54:14] output io_ptw_pmp_1_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_1_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_1_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_1_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_1_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_1_mask, // @[core.scala:54:14] output io_ptw_pmp_2_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_2_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_2_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_2_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_2_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_2_mask, // @[core.scala:54:14] output io_ptw_pmp_3_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_3_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_3_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_3_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_3_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_3_mask, // @[core.scala:54:14] output io_ptw_pmp_4_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_4_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_4_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_4_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_4_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_4_mask, // @[core.scala:54:14] output io_ptw_pmp_5_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_5_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_5_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_5_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_5_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_5_mask, // @[core.scala:54:14] output io_ptw_pmp_6_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_6_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_6_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_6_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_6_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_6_mask, // @[core.scala:54:14] output io_ptw_pmp_7_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_7_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_7_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_7_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_7_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_7_mask, // @[core.scala:54:14] input io_ptw_perf_l2miss, // @[core.scala:54:14] input io_ptw_perf_l2hit, // @[core.scala:54:14] input io_ptw_perf_pte_miss, // @[core.scala:54:14] input io_ptw_perf_pte_hit, // @[core.scala:54:14] input io_ptw_clock_enabled, // @[core.scala:54:14] output io_lsu_exe_0_req_valid, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_uopc, // @[core.scala:54:14] output [31:0] io_lsu_exe_0_req_bits_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_exe_0_req_bits_uop_debug_inst, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_exe_0_req_bits_uop_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_exe_0_req_bits_uop_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_exe_0_req_bits_uop_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ctrl_is_load, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_iw_state, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_br, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_jalr, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_jal, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_exe_0_req_bits_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_exe_0_req_bits_uop_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_exe_0_req_bits_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_exe_0_req_bits_uop_pc_lob, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_taken, // @[core.scala:54:14] output [19:0] io_lsu_exe_0_req_bits_uop_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_exe_0_req_bits_uop_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_exe_0_req_bits_uop_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_exe_0_req_bits_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_exe_0_req_bits_uop_ppred, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_exe_0_req_bits_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_exe_0_req_bits_uop_exc_cause, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_mem_size, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_mem_signed, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_fence, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_fencei, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_amo, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_uses_stq, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_is_unique, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_flush_on_commit, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_exe_0_req_bits_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_exe_0_req_bits_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_exe_0_req_bits_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_exe_0_req_bits_uop_lrs3, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_frs3_en, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_fp_val, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_fp_single, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_uop_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc, // @[core.scala:54:14] output [63:0] io_lsu_exe_0_req_bits_data, // @[core.scala:54:14] output [39:0] io_lsu_exe_0_req_bits_addr, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_mxcpt_valid, // @[core.scala:54:14] output [24:0] io_lsu_exe_0_req_bits_mxcpt_bits, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_sfence_valid, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_sfence_bits_rs1, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_sfence_bits_rs2, // @[core.scala:54:14] output [38:0] io_lsu_exe_0_req_bits_sfence_bits_addr, // @[core.scala:54:14] output io_lsu_exe_0_req_bits_sfence_bits_asid, // @[core.scala:54:14] input io_lsu_exe_0_iresp_valid, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_uopc, // @[core.scala:54:14] input [31:0] io_lsu_exe_0_iresp_bits_uop_inst, // @[core.scala:54:14] input [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_rvc, // @[core.scala:54:14] input [39:0] io_lsu_exe_0_iresp_bits_uop_debug_pc, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type, // @[core.scala:54:14] input [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code, // @[core.scala:54:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_is_load, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ctrl_is_std, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_br, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_jalr, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_jal, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_sfb, // @[core.scala:54:14] input [15:0] io_lsu_exe_0_iresp_bits_uop_br_mask, // @[core.scala:54:14] input [3:0] io_lsu_exe_0_iresp_bits_uop_br_tag, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_edge_inst, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_taken, // @[core.scala:54:14] input [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed, // @[core.scala:54:14] input [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_rob_idx, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_stq_idx, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_pdst, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_prs1, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_prs2, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_prs3, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_ppred, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_prs1_busy, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_prs2_busy, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_prs3_busy, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ppred_busy, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_exception, // @[core.scala:54:14] input [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_bypassable, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_mem_signed, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_fence, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_fencei, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_amo, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_uses_ldq, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_uses_stq, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_is_unique, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_flush_on_commit, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_ldst, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_ldst_val, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_frs3_en, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_fp_val, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_fp_single, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_bp_debug_if, // @[core.scala:54:14] input io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc, // @[core.scala:54:14] input [63:0] io_lsu_exe_0_iresp_bits_data, // @[core.scala:54:14] input io_lsu_exe_0_fresp_valid, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_uopc, // @[core.scala:54:14] input [31:0] io_lsu_exe_0_fresp_bits_uop_inst, // @[core.scala:54:14] input [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_rvc, // @[core.scala:54:14] input [39:0] io_lsu_exe_0_fresp_bits_uop_debug_pc, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type, // @[core.scala:54:14] input [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code, // @[core.scala:54:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14] input [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_is_load, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ctrl_is_std, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_br, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_jalr, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_jal, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_sfb, // @[core.scala:54:14] input [15:0] io_lsu_exe_0_fresp_bits_uop_br_mask, // @[core.scala:54:14] input [3:0] io_lsu_exe_0_fresp_bits_uop_br_tag, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_edge_inst, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_taken, // @[core.scala:54:14] input [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed, // @[core.scala:54:14] input [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_rob_idx, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_stq_idx, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_pdst, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_prs1, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_prs2, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_prs3, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_ppred, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_prs1_busy, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_prs2_busy, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_prs3_busy, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ppred_busy, // @[core.scala:54:14] input [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_exception, // @[core.scala:54:14] input [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_bypassable, // @[core.scala:54:14] input [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_mem_signed, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_fence, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_fencei, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_amo, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_uses_ldq, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_uses_stq, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_is_unique, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_flush_on_commit, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_ldst, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2, // @[core.scala:54:14] input [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_ldst_val, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_frs3_en, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_fp_val, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_fp_single, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_bp_debug_if, // @[core.scala:54:14] input io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc, // @[core.scala:54:14] input [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc, // @[core.scala:54:14] input [64:0] io_lsu_exe_0_fresp_bits_data, // @[core.scala:54:14] output io_lsu_dis_uops_0_valid, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_uopc, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_0_bits_inst, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_0_bits_debug_inst, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_dis_uops_0_bits_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_dis_uops_0_bits_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ctrl_is_load, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_iw_state, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_br, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_jalr, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_jal, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_dis_uops_0_bits_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_0_bits_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_ftq_idx, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_pc_lob, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_taken, // @[core.scala:54:14] output [19:0] io_lsu_dis_uops_0_bits_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_dis_uops_0_bits_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_pdst, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_prs1, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_prs2, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_prs3, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_prs1_busy, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_prs2_busy, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_prs3_busy, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_stale_pdst, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_exception, // @[core.scala:54:14] output [63:0] io_lsu_dis_uops_0_bits_exc_cause, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_mem_size, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_mem_signed, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_fence, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_fencei, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_amo, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_uses_ldq, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_uses_stq, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_unique, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_flush_on_commit, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_ldst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_lrs3, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_frs3_en, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_val, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_single, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_bp_debug_if, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_debug_tsrc, // @[core.scala:54:14] output io_lsu_dis_uops_1_valid, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_uopc, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_1_bits_inst, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_1_bits_debug_inst, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_dis_uops_1_bits_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_dis_uops_1_bits_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_1_bits_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ctrl_is_load, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_iw_state, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_br, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_jalr, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_jal, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_dis_uops_1_bits_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_1_bits_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_ftq_idx, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_pc_lob, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_taken, // @[core.scala:54:14] output [19:0] io_lsu_dis_uops_1_bits_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_dis_uops_1_bits_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_pdst, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_prs1, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_prs2, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_prs3, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_prs1_busy, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_prs2_busy, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_prs3_busy, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_stale_pdst, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_exception, // @[core.scala:54:14] output [63:0] io_lsu_dis_uops_1_bits_exc_cause, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_mem_size, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_mem_signed, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_fence, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_fencei, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_amo, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_uses_ldq, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_uses_stq, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_unique, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_flush_on_commit, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_ldst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_lrs3, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_lrs2_rtype, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_frs3_en, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_val, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_single, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_bp_debug_if, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_debug_tsrc, // @[core.scala:54:14] output io_lsu_dis_uops_2_valid, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_uopc, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_2_bits_inst, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_2_bits_debug_inst, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_dis_uops_2_bits_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_2_bits_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_dis_uops_2_bits_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_2_bits_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_2_bits_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_2_bits_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_2_bits_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_2_bits_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_ctrl_is_load, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_iw_state, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_br, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_jalr, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_jal, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_dis_uops_2_bits_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_2_bits_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_2_bits_ftq_idx, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_2_bits_pc_lob, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_taken, // @[core.scala:54:14] output [19:0] io_lsu_dis_uops_2_bits_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_dis_uops_2_bits_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_2_bits_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_2_bits_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_pdst, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_prs1, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_prs2, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_prs3, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_prs1_busy, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_prs2_busy, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_prs3_busy, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_2_bits_stale_pdst, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_exception, // @[core.scala:54:14] output [63:0] io_lsu_dis_uops_2_bits_exc_cause, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_2_bits_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_mem_size, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_mem_signed, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_fence, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_fencei, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_amo, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_uses_ldq, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_uses_stq, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_is_unique, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_flush_on_commit, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_2_bits_ldst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_2_bits_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_2_bits_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_2_bits_lrs3, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_lrs2_rtype, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_frs3_en, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_fp_val, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_fp_single, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_bp_debug_if, // @[core.scala:54:14] output io_lsu_dis_uops_2_bits_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_2_bits_debug_tsrc, // @[core.scala:54:14] input [4:0] io_lsu_dis_ldq_idx_0, // @[core.scala:54:14] input [4:0] io_lsu_dis_ldq_idx_1, // @[core.scala:54:14] input [4:0] io_lsu_dis_ldq_idx_2, // @[core.scala:54:14] input [4:0] io_lsu_dis_stq_idx_0, // @[core.scala:54:14] input [4:0] io_lsu_dis_stq_idx_1, // @[core.scala:54:14] input [4:0] io_lsu_dis_stq_idx_2, // @[core.scala:54:14] input io_lsu_ldq_full_0, // @[core.scala:54:14] input io_lsu_ldq_full_1, // @[core.scala:54:14] input io_lsu_ldq_full_2, // @[core.scala:54:14] input io_lsu_stq_full_0, // @[core.scala:54:14] input io_lsu_stq_full_1, // @[core.scala:54:14] input io_lsu_stq_full_2, // @[core.scala:54:14] input io_lsu_fp_stdata_ready, // @[core.scala:54:14] output io_lsu_fp_stdata_valid, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_uopc, // @[core.scala:54:14] output [31:0] io_lsu_fp_stdata_bits_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_fp_stdata_bits_uop_debug_inst, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_fp_stdata_bits_uop_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_uop_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_fp_stdata_bits_uop_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ctrl_is_load, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_iw_state, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_br, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_jalr, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_jal, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_fp_stdata_bits_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_fp_stdata_bits_uop_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_uop_pc_lob, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_taken, // @[core.scala:54:14] output [19:0] io_lsu_fp_stdata_bits_uop_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_fp_stdata_bits_uop_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_uop_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_uop_ppred, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_fp_stdata_bits_uop_exc_cause, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_mem_size, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_mem_signed, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_fence, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_fencei, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_amo, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_uses_stq, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_is_unique, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_flush_on_commit, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_uop_lrs3, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_frs3_en, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_fp_val, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_fp_single, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_uop_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc, // @[core.scala:54:14] output [63:0] io_lsu_fp_stdata_bits_data, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_predicated, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_valid, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc, // @[core.scala:54:14] output [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_br, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_taken, // @[core.scala:54:14] output [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc, // @[core.scala:54:14] output [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags, // @[core.scala:54:14] output io_lsu_commit_valids_0, // @[core.scala:54:14] output io_lsu_commit_valids_1, // @[core.scala:54:14] output io_lsu_commit_valids_2, // @[core.scala:54:14] output io_lsu_commit_arch_valids_0, // @[core.scala:54:14] output io_lsu_commit_arch_valids_1, // @[core.scala:54:14] output io_lsu_commit_arch_valids_2, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_uopc, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_0_inst, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_0_debug_inst, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_commit_uops_0_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_commit_uops_0_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_0_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_commit_uops_0_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_commit_uops_0_ctrl_is_load, // @[core.scala:54:14] output io_lsu_commit_uops_0_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_commit_uops_0_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_iw_state, // @[core.scala:54:14] output io_lsu_commit_uops_0_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_commit_uops_0_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_br, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_jalr, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_jal, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_commit_uops_0_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_0_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_ftq_idx, // @[core.scala:54:14] output io_lsu_commit_uops_0_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_pc_lob, // @[core.scala:54:14] output io_lsu_commit_uops_0_taken, // @[core.scala:54:14] output [19:0] io_lsu_commit_uops_0_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_commit_uops_0_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_pdst, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_prs1, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_prs2, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_prs3, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_ppred, // @[core.scala:54:14] output io_lsu_commit_uops_0_prs1_busy, // @[core.scala:54:14] output io_lsu_commit_uops_0_prs2_busy, // @[core.scala:54:14] output io_lsu_commit_uops_0_prs3_busy, // @[core.scala:54:14] output io_lsu_commit_uops_0_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_stale_pdst, // @[core.scala:54:14] output io_lsu_commit_uops_0_exception, // @[core.scala:54:14] output [63:0] io_lsu_commit_uops_0_exc_cause, // @[core.scala:54:14] output io_lsu_commit_uops_0_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_mem_size, // @[core.scala:54:14] output io_lsu_commit_uops_0_mem_signed, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_fence, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_fencei, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_amo, // @[core.scala:54:14] output io_lsu_commit_uops_0_uses_ldq, // @[core.scala:54:14] output io_lsu_commit_uops_0_uses_stq, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_unique, // @[core.scala:54:14] output io_lsu_commit_uops_0_flush_on_commit, // @[core.scala:54:14] output io_lsu_commit_uops_0_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_ldst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_lrs3, // @[core.scala:54:14] output io_lsu_commit_uops_0_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_lrs2_rtype, // @[core.scala:54:14] output io_lsu_commit_uops_0_frs3_en, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_val, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_single, // @[core.scala:54:14] output io_lsu_commit_uops_0_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_commit_uops_0_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_commit_uops_0_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_commit_uops_0_bp_debug_if, // @[core.scala:54:14] output io_lsu_commit_uops_0_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_debug_tsrc, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_uopc, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_1_inst, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_1_debug_inst, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_commit_uops_1_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_commit_uops_1_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_1_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_commit_uops_1_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_commit_uops_1_ctrl_is_load, // @[core.scala:54:14] output io_lsu_commit_uops_1_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_commit_uops_1_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_iw_state, // @[core.scala:54:14] output io_lsu_commit_uops_1_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_commit_uops_1_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_br, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_jalr, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_jal, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_commit_uops_1_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_1_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_ftq_idx, // @[core.scala:54:14] output io_lsu_commit_uops_1_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_pc_lob, // @[core.scala:54:14] output io_lsu_commit_uops_1_taken, // @[core.scala:54:14] output [19:0] io_lsu_commit_uops_1_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_commit_uops_1_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_pdst, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_prs1, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_prs2, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_prs3, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_ppred, // @[core.scala:54:14] output io_lsu_commit_uops_1_prs1_busy, // @[core.scala:54:14] output io_lsu_commit_uops_1_prs2_busy, // @[core.scala:54:14] output io_lsu_commit_uops_1_prs3_busy, // @[core.scala:54:14] output io_lsu_commit_uops_1_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_stale_pdst, // @[core.scala:54:14] output io_lsu_commit_uops_1_exception, // @[core.scala:54:14] output [63:0] io_lsu_commit_uops_1_exc_cause, // @[core.scala:54:14] output io_lsu_commit_uops_1_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_mem_size, // @[core.scala:54:14] output io_lsu_commit_uops_1_mem_signed, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_fence, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_fencei, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_amo, // @[core.scala:54:14] output io_lsu_commit_uops_1_uses_ldq, // @[core.scala:54:14] output io_lsu_commit_uops_1_uses_stq, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_unique, // @[core.scala:54:14] output io_lsu_commit_uops_1_flush_on_commit, // @[core.scala:54:14] output io_lsu_commit_uops_1_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_ldst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_lrs3, // @[core.scala:54:14] output io_lsu_commit_uops_1_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_lrs2_rtype, // @[core.scala:54:14] output io_lsu_commit_uops_1_frs3_en, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_val, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_single, // @[core.scala:54:14] output io_lsu_commit_uops_1_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_commit_uops_1_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_commit_uops_1_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_commit_uops_1_bp_debug_if, // @[core.scala:54:14] output io_lsu_commit_uops_1_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_debug_tsrc, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_uopc, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_2_inst, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_2_debug_inst, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_commit_uops_2_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_2_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_commit_uops_2_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_2_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_2_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_2_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_2_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_commit_uops_2_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_2_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_commit_uops_2_ctrl_is_load, // @[core.scala:54:14] output io_lsu_commit_uops_2_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_commit_uops_2_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_iw_state, // @[core.scala:54:14] output io_lsu_commit_uops_2_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_commit_uops_2_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_br, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_jalr, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_jal, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_commit_uops_2_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_2_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_2_ftq_idx, // @[core.scala:54:14] output io_lsu_commit_uops_2_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_2_pc_lob, // @[core.scala:54:14] output io_lsu_commit_uops_2_taken, // @[core.scala:54:14] output [19:0] io_lsu_commit_uops_2_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_commit_uops_2_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_2_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_2_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_pdst, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_prs1, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_prs2, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_prs3, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_2_ppred, // @[core.scala:54:14] output io_lsu_commit_uops_2_prs1_busy, // @[core.scala:54:14] output io_lsu_commit_uops_2_prs2_busy, // @[core.scala:54:14] output io_lsu_commit_uops_2_prs3_busy, // @[core.scala:54:14] output io_lsu_commit_uops_2_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_2_stale_pdst, // @[core.scala:54:14] output io_lsu_commit_uops_2_exception, // @[core.scala:54:14] output [63:0] io_lsu_commit_uops_2_exc_cause, // @[core.scala:54:14] output io_lsu_commit_uops_2_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_2_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_mem_size, // @[core.scala:54:14] output io_lsu_commit_uops_2_mem_signed, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_fence, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_fencei, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_amo, // @[core.scala:54:14] output io_lsu_commit_uops_2_uses_ldq, // @[core.scala:54:14] output io_lsu_commit_uops_2_uses_stq, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_commit_uops_2_is_unique, // @[core.scala:54:14] output io_lsu_commit_uops_2_flush_on_commit, // @[core.scala:54:14] output io_lsu_commit_uops_2_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_2_ldst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_2_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_2_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_2_lrs3, // @[core.scala:54:14] output io_lsu_commit_uops_2_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_lrs2_rtype, // @[core.scala:54:14] output io_lsu_commit_uops_2_frs3_en, // @[core.scala:54:14] output io_lsu_commit_uops_2_fp_val, // @[core.scala:54:14] output io_lsu_commit_uops_2_fp_single, // @[core.scala:54:14] output io_lsu_commit_uops_2_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_commit_uops_2_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_commit_uops_2_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_commit_uops_2_bp_debug_if, // @[core.scala:54:14] output io_lsu_commit_uops_2_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_2_debug_tsrc, // @[core.scala:54:14] output io_lsu_commit_fflags_valid, // @[core.scala:54:14] output [4:0] io_lsu_commit_fflags_bits, // @[core.scala:54:14] output [31:0] io_lsu_commit_debug_insts_0, // @[core.scala:54:14] output [31:0] io_lsu_commit_debug_insts_1, // @[core.scala:54:14] output [31:0] io_lsu_commit_debug_insts_2, // @[core.scala:54:14] output io_lsu_commit_rbk_valids_0, // @[core.scala:54:14] output io_lsu_commit_rbk_valids_1, // @[core.scala:54:14] output io_lsu_commit_rbk_valids_2, // @[core.scala:54:14] output io_lsu_commit_rollback, // @[core.scala:54:14] output [63:0] io_lsu_commit_debug_wdata_0, // @[core.scala:54:14] output [63:0] io_lsu_commit_debug_wdata_1, // @[core.scala:54:14] output [63:0] io_lsu_commit_debug_wdata_2, // @[core.scala:54:14] output io_lsu_commit_load_at_rob_head, // @[core.scala:54:14] input io_lsu_clr_bsy_0_valid, // @[core.scala:54:14] input [6:0] io_lsu_clr_bsy_0_bits, // @[core.scala:54:14] input io_lsu_clr_bsy_1_valid, // @[core.scala:54:14] input [6:0] io_lsu_clr_bsy_1_bits, // @[core.scala:54:14] input [6:0] io_lsu_clr_unsafe_0_bits, // @[core.scala:54:14] output io_lsu_fence_dmem, // @[core.scala:54:14] input io_lsu_spec_ld_wakeup_0_valid, // @[core.scala:54:14] input [6:0] io_lsu_spec_ld_wakeup_0_bits, // @[core.scala:54:14] input io_lsu_ld_miss, // @[core.scala:54:14] output [15:0] io_lsu_brupdate_b1_resolve_mask, // @[core.scala:54:14] output [15:0] io_lsu_brupdate_b1_mispredict_mask, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_uopc, // @[core.scala:54:14] output [31:0] io_lsu_brupdate_b2_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_brupdate_b2_uop_debug_inst, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_brupdate_b2_uop_debug_pc, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_iq_type, // @[core.scala:54:14] output [9:0] io_lsu_brupdate_b2_uop_fu_code, // @[core.scala:54:14] output [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ctrl_fcn_dw, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ctrl_is_load, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ctrl_is_sta, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ctrl_is_std, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_iw_state, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iw_p1_poisoned, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iw_p2_poisoned, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_br, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_jalr, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_jal, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_sfb, // @[core.scala:54:14] output [15:0] io_lsu_brupdate_b2_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_brupdate_b2_uop_br_tag, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_pc_lob, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_taken, // @[core.scala:54:14] output [19:0] io_lsu_brupdate_b2_uop_imm_packed, // @[core.scala:54:14] output [11:0] io_lsu_brupdate_b2_uop_csr_addr, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_rob_idx, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_ldq_idx, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_ppred, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_brupdate_b2_uop_exc_cause, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_bypassable, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_mem_size, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_mem_signed, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_fence, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_fencei, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_amo, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_uses_stq, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_unique, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_flush_on_commit, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_lrs3, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ldst_val, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_frs3_en, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_val, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_single, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_bp_xcpt_if, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_debug_fsrc, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_debug_tsrc, // @[core.scala:54:14] output io_lsu_brupdate_b2_valid, // @[core.scala:54:14] output io_lsu_brupdate_b2_mispredict, // @[core.scala:54:14] output io_lsu_brupdate_b2_taken, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_cfi_type, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_pc_sel, // @[core.scala:54:14] output [39:0] io_lsu_brupdate_b2_jalr_target, // @[core.scala:54:14] output [20:0] io_lsu_brupdate_b2_target_offset, // @[core.scala:54:14] output [6:0] io_lsu_rob_pnr_idx, // @[core.scala:54:14] output [6:0] io_lsu_rob_head_idx, // @[core.scala:54:14] output io_lsu_exception, // @[core.scala:54:14] input io_lsu_fencei_rdy, // @[core.scala:54:14] input io_lsu_lxcpt_valid, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_uopc, // @[core.scala:54:14] input [31:0] io_lsu_lxcpt_bits_uop_inst, // @[core.scala:54:14] input [31:0] io_lsu_lxcpt_bits_uop_debug_inst, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_rvc, // @[core.scala:54:14] input [39:0] io_lsu_lxcpt_bits_uop_debug_pc, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_iq_type, // @[core.scala:54:14] input [9:0] io_lsu_lxcpt_bits_uop_fu_code, // @[core.scala:54:14] input [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ctrl_fcn_dw, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ctrl_is_load, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ctrl_is_sta, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ctrl_is_std, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_iw_state, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iw_p1_poisoned, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iw_p2_poisoned, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_br, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_jalr, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_jal, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_sfb, // @[core.scala:54:14] input [15:0] io_lsu_lxcpt_bits_uop_br_mask, // @[core.scala:54:14] input [3:0] io_lsu_lxcpt_bits_uop_br_tag, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_ftq_idx, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_edge_inst, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_pc_lob, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_taken, // @[core.scala:54:14] input [19:0] io_lsu_lxcpt_bits_uop_imm_packed, // @[core.scala:54:14] input [11:0] io_lsu_lxcpt_bits_uop_csr_addr, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_rob_idx, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_ldq_idx, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_stq_idx, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_rxq_idx, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_pdst, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_prs1, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_prs2, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_prs3, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_ppred, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_prs1_busy, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_prs2_busy, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_prs3_busy, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ppred_busy, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_stale_pdst, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_exception, // @[core.scala:54:14] input [63:0] io_lsu_lxcpt_bits_uop_exc_cause, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_bypassable, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_mem_cmd, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_mem_size, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_mem_signed, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_fence, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_fencei, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_amo, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_uses_ldq, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_uses_stq, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_unique, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_flush_on_commit, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ldst_is_rs1, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_ldst, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs1, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs2, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs3, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ldst_val, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_dst_rtype, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_frs3_en, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_val, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_single, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_xcpt_pf_if, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_xcpt_ae_if, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_xcpt_ma_if, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_bp_debug_if, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_bp_xcpt_if, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_cause, // @[core.scala:54:14] input [39:0] io_lsu_lxcpt_bits_badvaddr, // @[core.scala:54:14] output [63:0] io_lsu_tsc_reg, // @[core.scala:54:14] input io_lsu_perf_acquire, // @[core.scala:54:14] input io_lsu_perf_release, // @[core.scala:54:14] input io_lsu_perf_tlbMiss, // @[core.scala:54:14] input io_ptw_tlb_req_ready, // @[core.scala:54:14] input io_ptw_tlb_resp_valid, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_ae_ptw, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_ae_final, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pf, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_gf, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_hr, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_hw, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_hx, // @[core.scala:54:14] input [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future, // @[core.scala:54:14] input [43:0] io_ptw_tlb_resp_bits_pte_ppn, // @[core.scala:54:14] input [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_d, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_a, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_g, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_u, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_x, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_w, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_r, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_v, // @[core.scala:54:14] input [1:0] io_ptw_tlb_resp_bits_level, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_homogeneous, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_gpa_valid, // @[core.scala:54:14] input [38:0] io_ptw_tlb_resp_bits_gpa_bits, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_gpa_is_pte, // @[core.scala:54:14] input [3:0] io_ptw_tlb_ptbr_mode, // @[core.scala:54:14] input [43:0] io_ptw_tlb_ptbr_ppn, // @[core.scala:54:14] input io_ptw_tlb_status_debug, // @[core.scala:54:14] input io_ptw_tlb_status_cease, // @[core.scala:54:14] input io_ptw_tlb_status_wfi, // @[core.scala:54:14] input [1:0] io_ptw_tlb_status_dprv, // @[core.scala:54:14] input io_ptw_tlb_status_dv, // @[core.scala:54:14] input [1:0] io_ptw_tlb_status_prv, // @[core.scala:54:14] input io_ptw_tlb_status_v, // @[core.scala:54:14] input io_ptw_tlb_status_sd, // @[core.scala:54:14] input io_ptw_tlb_status_mpv, // @[core.scala:54:14] input io_ptw_tlb_status_gva, // @[core.scala:54:14] input io_ptw_tlb_status_tsr, // @[core.scala:54:14] input io_ptw_tlb_status_tw, // @[core.scala:54:14] input io_ptw_tlb_status_tvm, // @[core.scala:54:14] input io_ptw_tlb_status_mxr, // @[core.scala:54:14] input io_ptw_tlb_status_sum, // @[core.scala:54:14] input io_ptw_tlb_status_mprv, // @[core.scala:54:14] input [1:0] io_ptw_tlb_status_fs, // @[core.scala:54:14] input [1:0] io_ptw_tlb_status_mpp, // @[core.scala:54:14] input io_ptw_tlb_status_spp, // @[core.scala:54:14] input io_ptw_tlb_status_mpie, // @[core.scala:54:14] input io_ptw_tlb_status_spie, // @[core.scala:54:14] input io_ptw_tlb_status_mie, // @[core.scala:54:14] input io_ptw_tlb_status_sie, // @[core.scala:54:14] input io_ptw_tlb_pmp_0_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_0_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_0_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_0_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_0_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_0_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_0_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_1_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_1_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_1_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_1_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_1_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_1_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_1_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_2_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_2_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_2_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_2_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_2_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_2_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_2_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_3_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_3_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_3_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_3_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_3_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_3_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_3_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_4_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_4_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_4_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_4_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_4_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_4_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_4_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_5_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_5_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_5_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_5_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_5_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_5_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_5_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_6_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_6_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_6_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_6_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_6_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_6_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_6_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_7_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_7_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_7_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_7_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_7_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_7_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_7_mask, // @[core.scala:54:14] output [63:0] io_trace_time, // @[core.scala:54:14] output io_trace_custom_rob_empty // @[core.scala:54:14] ); wire [1:0] iss_uops_3_debug_tsrc; // @[core.scala:173:24] wire [1:0] iss_uops_3_debug_fsrc; // @[core.scala:173:24] wire iss_uops_3_bp_xcpt_if; // @[core.scala:173:24] wire iss_uops_3_bp_debug_if; // @[core.scala:173:24] wire iss_uops_3_xcpt_ma_if; // @[core.scala:173:24] wire iss_uops_3_xcpt_ae_if; // @[core.scala:173:24] wire iss_uops_3_xcpt_pf_if; // @[core.scala:173:24] wire iss_uops_3_fp_single; // @[core.scala:173:24] wire iss_uops_3_fp_val; // @[core.scala:173:24] wire iss_uops_3_frs3_en; // @[core.scala:173:24] wire [1:0] iss_uops_3_lrs2_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_3_lrs1_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_3_dst_rtype; // @[core.scala:173:24] wire iss_uops_3_ldst_val; // @[core.scala:173:24] wire [5:0] iss_uops_3_lrs3; // @[core.scala:173:24] wire [5:0] iss_uops_3_lrs2; // @[core.scala:173:24] wire [5:0] iss_uops_3_lrs1; // @[core.scala:173:24] wire [5:0] iss_uops_3_ldst; // @[core.scala:173:24] wire iss_uops_3_ldst_is_rs1; // @[core.scala:173:24] wire iss_uops_3_flush_on_commit; // @[core.scala:173:24] wire iss_uops_3_is_unique; // @[core.scala:173:24] wire iss_uops_3_is_sys_pc2epc; // @[core.scala:173:24] wire iss_uops_3_uses_stq; // @[core.scala:173:24] wire iss_uops_3_uses_ldq; // @[core.scala:173:24] wire iss_uops_3_is_amo; // @[core.scala:173:24] wire iss_uops_3_is_fencei; // @[core.scala:173:24] wire iss_uops_3_is_fence; // @[core.scala:173:24] wire iss_uops_3_mem_signed; // @[core.scala:173:24] wire [1:0] iss_uops_3_mem_size; // @[core.scala:173:24] wire [4:0] iss_uops_3_mem_cmd; // @[core.scala:173:24] wire iss_uops_3_bypassable; // @[core.scala:173:24] wire [63:0] iss_uops_3_exc_cause; // @[core.scala:173:24] wire iss_uops_3_exception; // @[core.scala:173:24] wire [6:0] iss_uops_3_stale_pdst; // @[core.scala:173:24] wire iss_uops_3_ppred_busy; // @[core.scala:173:24] wire iss_uops_3_prs3_busy; // @[core.scala:173:24] wire iss_uops_3_prs2_busy; // @[core.scala:173:24] wire iss_uops_3_prs1_busy; // @[core.scala:173:24] wire [4:0] iss_uops_3_ppred; // @[core.scala:173:24] wire [6:0] iss_uops_3_prs3; // @[core.scala:173:24] wire [6:0] iss_uops_3_prs2; // @[core.scala:173:24] wire [6:0] iss_uops_3_prs1; // @[core.scala:173:24] wire [6:0] iss_uops_3_pdst; // @[core.scala:173:24] wire [1:0] iss_uops_3_rxq_idx; // @[core.scala:173:24] wire [4:0] iss_uops_3_stq_idx; // @[core.scala:173:24] wire [4:0] iss_uops_3_ldq_idx; // @[core.scala:173:24] wire [6:0] iss_uops_3_rob_idx; // @[core.scala:173:24] wire [11:0] iss_uops_3_csr_addr; // @[core.scala:173:24] wire [19:0] iss_uops_3_imm_packed; // @[core.scala:173:24] wire iss_uops_3_taken; // @[core.scala:173:24] wire [5:0] iss_uops_3_pc_lob; // @[core.scala:173:24] wire iss_uops_3_edge_inst; // @[core.scala:173:24] wire [4:0] iss_uops_3_ftq_idx; // @[core.scala:173:24] wire [3:0] iss_uops_3_br_tag; // @[core.scala:173:24] wire [15:0] iss_uops_3_br_mask; // @[core.scala:173:24] wire iss_uops_3_is_sfb; // @[core.scala:173:24] wire iss_uops_3_is_jal; // @[core.scala:173:24] wire iss_uops_3_is_jalr; // @[core.scala:173:24] wire iss_uops_3_is_br; // @[core.scala:173:24] wire iss_uops_3_iw_p2_poisoned; // @[core.scala:173:24] wire iss_uops_3_iw_p1_poisoned; // @[core.scala:173:24] wire [1:0] iss_uops_3_iw_state; // @[core.scala:173:24] wire [9:0] iss_uops_3_fu_code; // @[core.scala:173:24] wire [2:0] iss_uops_3_iq_type; // @[core.scala:173:24] wire [39:0] iss_uops_3_debug_pc; // @[core.scala:173:24] wire iss_uops_3_is_rvc; // @[core.scala:173:24] wire [31:0] iss_uops_3_debug_inst; // @[core.scala:173:24] wire [31:0] iss_uops_3_inst; // @[core.scala:173:24] wire [6:0] iss_uops_3_uopc; // @[core.scala:173:24] wire iss_uops_3_ctrl_is_std; // @[core.scala:173:24] wire iss_uops_3_ctrl_is_sta; // @[core.scala:173:24] wire iss_uops_3_ctrl_is_load; // @[core.scala:173:24] wire [2:0] iss_uops_3_ctrl_csr_cmd; // @[core.scala:173:24] wire iss_uops_3_ctrl_fcn_dw; // @[core.scala:173:24] wire [4:0] iss_uops_3_ctrl_op_fcn; // @[core.scala:173:24] wire [2:0] iss_uops_3_ctrl_imm_sel; // @[core.scala:173:24] wire [2:0] iss_uops_3_ctrl_op2_sel; // @[core.scala:173:24] wire [1:0] iss_uops_3_ctrl_op1_sel; // @[core.scala:173:24] wire [3:0] iss_uops_3_ctrl_br_type; // @[core.scala:173:24] wire [1:0] iss_uops_2_debug_tsrc; // @[core.scala:173:24] wire [1:0] iss_uops_2_debug_fsrc; // @[core.scala:173:24] wire iss_uops_2_bp_xcpt_if; // @[core.scala:173:24] wire iss_uops_2_bp_debug_if; // @[core.scala:173:24] wire iss_uops_2_xcpt_ma_if; // @[core.scala:173:24] wire iss_uops_2_xcpt_ae_if; // @[core.scala:173:24] wire iss_uops_2_xcpt_pf_if; // @[core.scala:173:24] wire iss_uops_2_fp_single; // @[core.scala:173:24] wire iss_uops_2_fp_val; // @[core.scala:173:24] wire iss_uops_2_frs3_en; // @[core.scala:173:24] wire [1:0] iss_uops_2_lrs2_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_2_lrs1_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_2_dst_rtype; // @[core.scala:173:24] wire iss_uops_2_ldst_val; // @[core.scala:173:24] wire [5:0] iss_uops_2_lrs3; // @[core.scala:173:24] wire [5:0] iss_uops_2_lrs2; // @[core.scala:173:24] wire [5:0] iss_uops_2_lrs1; // @[core.scala:173:24] wire [5:0] iss_uops_2_ldst; // @[core.scala:173:24] wire iss_uops_2_ldst_is_rs1; // @[core.scala:173:24] wire iss_uops_2_flush_on_commit; // @[core.scala:173:24] wire iss_uops_2_is_unique; // @[core.scala:173:24] wire iss_uops_2_is_sys_pc2epc; // @[core.scala:173:24] wire iss_uops_2_uses_stq; // @[core.scala:173:24] wire iss_uops_2_uses_ldq; // @[core.scala:173:24] wire iss_uops_2_is_amo; // @[core.scala:173:24] wire iss_uops_2_is_fencei; // @[core.scala:173:24] wire iss_uops_2_is_fence; // @[core.scala:173:24] wire iss_uops_2_mem_signed; // @[core.scala:173:24] wire [1:0] iss_uops_2_mem_size; // @[core.scala:173:24] wire [4:0] iss_uops_2_mem_cmd; // @[core.scala:173:24] wire iss_uops_2_bypassable; // @[core.scala:173:24] wire [63:0] iss_uops_2_exc_cause; // @[core.scala:173:24] wire iss_uops_2_exception; // @[core.scala:173:24] wire [6:0] iss_uops_2_stale_pdst; // @[core.scala:173:24] wire iss_uops_2_ppred_busy; // @[core.scala:173:24] wire iss_uops_2_prs3_busy; // @[core.scala:173:24] wire iss_uops_2_prs2_busy; // @[core.scala:173:24] wire iss_uops_2_prs1_busy; // @[core.scala:173:24] wire [4:0] iss_uops_2_ppred; // @[core.scala:173:24] wire [6:0] iss_uops_2_prs3; // @[core.scala:173:24] wire [6:0] iss_uops_2_prs2; // @[core.scala:173:24] wire [6:0] iss_uops_2_prs1; // @[core.scala:173:24] wire [6:0] iss_uops_2_pdst; // @[core.scala:173:24] wire [1:0] iss_uops_2_rxq_idx; // @[core.scala:173:24] wire [4:0] iss_uops_2_stq_idx; // @[core.scala:173:24] wire [4:0] iss_uops_2_ldq_idx; // @[core.scala:173:24] wire [6:0] iss_uops_2_rob_idx; // @[core.scala:173:24] wire [11:0] iss_uops_2_csr_addr; // @[core.scala:173:24] wire [19:0] iss_uops_2_imm_packed; // @[core.scala:173:24] wire iss_uops_2_taken; // @[core.scala:173:24] wire [5:0] iss_uops_2_pc_lob; // @[core.scala:173:24] wire iss_uops_2_edge_inst; // @[core.scala:173:24] wire [4:0] iss_uops_2_ftq_idx; // @[core.scala:173:24] wire [3:0] iss_uops_2_br_tag; // @[core.scala:173:24] wire [15:0] iss_uops_2_br_mask; // @[core.scala:173:24] wire iss_uops_2_is_sfb; // @[core.scala:173:24] wire iss_uops_2_is_jal; // @[core.scala:173:24] wire iss_uops_2_is_jalr; // @[core.scala:173:24] wire iss_uops_2_is_br; // @[core.scala:173:24] wire iss_uops_2_iw_p2_poisoned; // @[core.scala:173:24] wire iss_uops_2_iw_p1_poisoned; // @[core.scala:173:24] wire [1:0] iss_uops_2_iw_state; // @[core.scala:173:24] wire [9:0] iss_uops_2_fu_code; // @[core.scala:173:24] wire [2:0] iss_uops_2_iq_type; // @[core.scala:173:24] wire [39:0] iss_uops_2_debug_pc; // @[core.scala:173:24] wire iss_uops_2_is_rvc; // @[core.scala:173:24] wire [31:0] iss_uops_2_debug_inst; // @[core.scala:173:24] wire [31:0] iss_uops_2_inst; // @[core.scala:173:24] wire [6:0] iss_uops_2_uopc; // @[core.scala:173:24] wire iss_uops_2_ctrl_is_std; // @[core.scala:173:24] wire iss_uops_2_ctrl_is_sta; // @[core.scala:173:24] wire iss_uops_2_ctrl_is_load; // @[core.scala:173:24] wire [2:0] iss_uops_2_ctrl_csr_cmd; // @[core.scala:173:24] wire iss_uops_2_ctrl_fcn_dw; // @[core.scala:173:24] wire [4:0] iss_uops_2_ctrl_op_fcn; // @[core.scala:173:24] wire [2:0] iss_uops_2_ctrl_imm_sel; // @[core.scala:173:24] wire [2:0] iss_uops_2_ctrl_op2_sel; // @[core.scala:173:24] wire [1:0] iss_uops_2_ctrl_op1_sel; // @[core.scala:173:24] wire [3:0] iss_uops_2_ctrl_br_type; // @[core.scala:173:24] wire dis_valids_0; // @[core.scala:166:24] wire io_ifu_sfence_bits_asid_0; // @[core.scala:51:7] wire [38:0] io_ifu_sfence_bits_addr_0; // @[core.scala:51:7] wire io_ifu_sfence_bits_rs2_0; // @[core.scala:51:7] wire io_ifu_sfence_bits_rs1_0; // @[core.scala:51:7] wire io_ifu_sfence_valid_0; // @[core.scala:51:7] wire [63:0] _csr_io_rw_rdata; // @[core.scala:271:19] wire _csr_io_decode_0_fp_illegal; // @[core.scala:271:19] wire _csr_io_decode_0_fp_csr; // @[core.scala:271:19] wire _csr_io_decode_0_read_illegal; // @[core.scala:271:19] wire _csr_io_decode_0_write_illegal; // @[core.scala:271:19] wire _csr_io_decode_0_write_flush; // @[core.scala:271:19] wire _csr_io_decode_0_system_illegal; // @[core.scala:271:19] wire _csr_io_decode_0_virtual_access_illegal; // @[core.scala:271:19] wire _csr_io_decode_0_virtual_system_illegal; // @[core.scala:271:19] wire _csr_io_decode_1_fp_illegal; // @[core.scala:271:19] wire _csr_io_decode_1_fp_csr; // @[core.scala:271:19] wire _csr_io_decode_1_read_illegal; // @[core.scala:271:19] wire _csr_io_decode_1_write_illegal; // @[core.scala:271:19] wire _csr_io_decode_1_write_flush; // @[core.scala:271:19] wire _csr_io_decode_1_system_illegal; // @[core.scala:271:19] wire _csr_io_decode_1_virtual_access_illegal; // @[core.scala:271:19] wire _csr_io_decode_1_virtual_system_illegal; // @[core.scala:271:19] wire _csr_io_decode_2_fp_illegal; // @[core.scala:271:19] wire _csr_io_decode_2_fp_csr; // @[core.scala:271:19] wire _csr_io_decode_2_read_illegal; // @[core.scala:271:19] wire _csr_io_decode_2_write_illegal; // @[core.scala:271:19] wire _csr_io_decode_2_write_flush; // @[core.scala:271:19] wire _csr_io_decode_2_system_illegal; // @[core.scala:271:19] wire _csr_io_decode_2_virtual_access_illegal; // @[core.scala:271:19] wire _csr_io_decode_2_virtual_system_illegal; // @[core.scala:271:19] wire _csr_io_csr_stall; // @[core.scala:271:19] wire _csr_io_singleStep; // @[core.scala:271:19] wire _csr_io_status_debug; // @[core.scala:271:19] wire _csr_io_status_cease; // @[core.scala:271:19] wire _csr_io_status_wfi; // @[core.scala:271:19] wire [1:0] _csr_io_status_dprv; // @[core.scala:271:19] wire _csr_io_status_dv; // @[core.scala:271:19] wire [1:0] _csr_io_status_prv; // @[core.scala:271:19] wire _csr_io_status_v; // @[core.scala:271:19] wire _csr_io_status_sd; // @[core.scala:271:19] wire _csr_io_status_mpv; // @[core.scala:271:19] wire _csr_io_status_gva; // @[core.scala:271:19] wire _csr_io_status_tsr; // @[core.scala:271:19] wire _csr_io_status_tw; // @[core.scala:271:19] wire _csr_io_status_tvm; // @[core.scala:271:19] wire _csr_io_status_mxr; // @[core.scala:271:19] wire _csr_io_status_sum; // @[core.scala:271:19] wire _csr_io_status_mprv; // @[core.scala:271:19] wire [1:0] _csr_io_status_fs; // @[core.scala:271:19] wire [1:0] _csr_io_status_mpp; // @[core.scala:271:19] wire _csr_io_status_spp; // @[core.scala:271:19] wire _csr_io_status_mpie; // @[core.scala:271:19] wire _csr_io_status_spie; // @[core.scala:271:19] wire _csr_io_status_mie; // @[core.scala:271:19] wire _csr_io_status_sie; // @[core.scala:271:19] wire [39:0] _csr_io_evec; // @[core.scala:271:19] wire [2:0] _csr_io_fcsr_rm; // @[core.scala:271:19] wire _csr_io_interrupt; // @[core.scala:271:19] wire [63:0] _csr_io_interrupt_cause; // @[core.scala:271:19] wire [6:0] _rob_io_rob_tail_idx; // @[core.scala:143:32] wire [6:0] _rob_io_rob_head_idx; // @[core.scala:143:32] wire _rob_io_commit_valids_0; // @[core.scala:143:32] wire _rob_io_commit_valids_1; // @[core.scala:143:32] wire _rob_io_commit_valids_2; // @[core.scala:143:32] wire _rob_io_commit_arch_valids_0; // @[core.scala:143:32] wire _rob_io_commit_arch_valids_1; // @[core.scala:143:32] wire _rob_io_commit_arch_valids_2; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_uopc; // @[core.scala:143:32] wire [31:0] _rob_io_commit_uops_0_inst; // @[core.scala:143:32] wire [31:0] _rob_io_commit_uops_0_debug_inst; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_rvc; // @[core.scala:143:32] wire [39:0] _rob_io_commit_uops_0_debug_pc; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_0_iq_type; // @[core.scala:143:32] wire [9:0] _rob_io_commit_uops_0_fu_code; // @[core.scala:143:32] wire [3:0] _rob_io_commit_uops_0_ctrl_br_type; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_ctrl_op1_sel; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_0_ctrl_op2_sel; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_0_ctrl_imm_sel; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_0_ctrl_op_fcn; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ctrl_fcn_dw; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_0_ctrl_csr_cmd; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ctrl_is_load; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ctrl_is_sta; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ctrl_is_std; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_iw_state; // @[core.scala:143:32] wire _rob_io_commit_uops_0_iw_p1_poisoned; // @[core.scala:143:32] wire _rob_io_commit_uops_0_iw_p2_poisoned; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_br; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_sfb; // @[core.scala:143:32] wire [15:0] _rob_io_commit_uops_0_br_mask; // @[core.scala:143:32] wire [3:0] _rob_io_commit_uops_0_br_tag; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_0_ftq_idx; // @[core.scala:143:32] wire _rob_io_commit_uops_0_edge_inst; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_0_pc_lob; // @[core.scala:143:32] wire _rob_io_commit_uops_0_taken; // @[core.scala:143:32] wire [19:0] _rob_io_commit_uops_0_imm_packed; // @[core.scala:143:32] wire [11:0] _rob_io_commit_uops_0_csr_addr; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_rob_idx; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_0_ldq_idx; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_0_stq_idx; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_rxq_idx; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_pdst; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_prs1; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_prs2; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_prs3; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_0_ppred; // @[core.scala:143:32] wire _rob_io_commit_uops_0_prs1_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_0_prs2_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_0_prs3_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ppred_busy; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_0_stale_pdst; // @[core.scala:143:32] wire _rob_io_commit_uops_0_exception; // @[core.scala:143:32] wire [63:0] _rob_io_commit_uops_0_exc_cause; // @[core.scala:143:32] wire _rob_io_commit_uops_0_bypassable; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_0_mem_cmd; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_mem_size; // @[core.scala:143:32] wire _rob_io_commit_uops_0_mem_signed; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_fence; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_fencei; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_amo; // @[core.scala:143:32] wire _rob_io_commit_uops_0_uses_ldq; // @[core.scala:143:32] wire _rob_io_commit_uops_0_uses_stq; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_sys_pc2epc; // @[core.scala:143:32] wire _rob_io_commit_uops_0_is_unique; // @[core.scala:143:32] wire _rob_io_commit_uops_0_flush_on_commit; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ldst_is_rs1; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_0_ldst; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_0_lrs1; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_0_lrs2; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_0_lrs3; // @[core.scala:143:32] wire _rob_io_commit_uops_0_ldst_val; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_dst_rtype; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_lrs1_rtype; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_lrs2_rtype; // @[core.scala:143:32] wire _rob_io_commit_uops_0_frs3_en; // @[core.scala:143:32] wire _rob_io_commit_uops_0_fp_val; // @[core.scala:143:32] wire _rob_io_commit_uops_0_fp_single; // @[core.scala:143:32] wire _rob_io_commit_uops_0_xcpt_pf_if; // @[core.scala:143:32] wire _rob_io_commit_uops_0_xcpt_ae_if; // @[core.scala:143:32] wire _rob_io_commit_uops_0_xcpt_ma_if; // @[core.scala:143:32] wire _rob_io_commit_uops_0_bp_debug_if; // @[core.scala:143:32] wire _rob_io_commit_uops_0_bp_xcpt_if; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_0_debug_tsrc; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_uopc; // @[core.scala:143:32] wire [31:0] _rob_io_commit_uops_1_inst; // @[core.scala:143:32] wire [31:0] _rob_io_commit_uops_1_debug_inst; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_rvc; // @[core.scala:143:32] wire [39:0] _rob_io_commit_uops_1_debug_pc; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_1_iq_type; // @[core.scala:143:32] wire [9:0] _rob_io_commit_uops_1_fu_code; // @[core.scala:143:32] wire [3:0] _rob_io_commit_uops_1_ctrl_br_type; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_ctrl_op1_sel; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_1_ctrl_op2_sel; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_1_ctrl_imm_sel; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_1_ctrl_op_fcn; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ctrl_fcn_dw; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_1_ctrl_csr_cmd; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ctrl_is_load; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ctrl_is_sta; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ctrl_is_std; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_iw_state; // @[core.scala:143:32] wire _rob_io_commit_uops_1_iw_p1_poisoned; // @[core.scala:143:32] wire _rob_io_commit_uops_1_iw_p2_poisoned; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_br; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_sfb; // @[core.scala:143:32] wire [15:0] _rob_io_commit_uops_1_br_mask; // @[core.scala:143:32] wire [3:0] _rob_io_commit_uops_1_br_tag; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_1_ftq_idx; // @[core.scala:143:32] wire _rob_io_commit_uops_1_edge_inst; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_1_pc_lob; // @[core.scala:143:32] wire _rob_io_commit_uops_1_taken; // @[core.scala:143:32] wire [19:0] _rob_io_commit_uops_1_imm_packed; // @[core.scala:143:32] wire [11:0] _rob_io_commit_uops_1_csr_addr; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_rob_idx; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_1_ldq_idx; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_1_stq_idx; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_rxq_idx; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_pdst; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_prs1; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_prs2; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_prs3; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_1_ppred; // @[core.scala:143:32] wire _rob_io_commit_uops_1_prs1_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_1_prs2_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_1_prs3_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ppred_busy; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_1_stale_pdst; // @[core.scala:143:32] wire _rob_io_commit_uops_1_exception; // @[core.scala:143:32] wire [63:0] _rob_io_commit_uops_1_exc_cause; // @[core.scala:143:32] wire _rob_io_commit_uops_1_bypassable; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_1_mem_cmd; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_mem_size; // @[core.scala:143:32] wire _rob_io_commit_uops_1_mem_signed; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_fence; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_fencei; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_amo; // @[core.scala:143:32] wire _rob_io_commit_uops_1_uses_ldq; // @[core.scala:143:32] wire _rob_io_commit_uops_1_uses_stq; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_sys_pc2epc; // @[core.scala:143:32] wire _rob_io_commit_uops_1_is_unique; // @[core.scala:143:32] wire _rob_io_commit_uops_1_flush_on_commit; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ldst_is_rs1; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_1_ldst; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_1_lrs1; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_1_lrs2; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_1_lrs3; // @[core.scala:143:32] wire _rob_io_commit_uops_1_ldst_val; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_dst_rtype; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_lrs1_rtype; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_lrs2_rtype; // @[core.scala:143:32] wire _rob_io_commit_uops_1_frs3_en; // @[core.scala:143:32] wire _rob_io_commit_uops_1_fp_val; // @[core.scala:143:32] wire _rob_io_commit_uops_1_fp_single; // @[core.scala:143:32] wire _rob_io_commit_uops_1_xcpt_pf_if; // @[core.scala:143:32] wire _rob_io_commit_uops_1_xcpt_ae_if; // @[core.scala:143:32] wire _rob_io_commit_uops_1_xcpt_ma_if; // @[core.scala:143:32] wire _rob_io_commit_uops_1_bp_debug_if; // @[core.scala:143:32] wire _rob_io_commit_uops_1_bp_xcpt_if; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_debug_fsrc; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_1_debug_tsrc; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_uopc; // @[core.scala:143:32] wire [31:0] _rob_io_commit_uops_2_inst; // @[core.scala:143:32] wire [31:0] _rob_io_commit_uops_2_debug_inst; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_rvc; // @[core.scala:143:32] wire [39:0] _rob_io_commit_uops_2_debug_pc; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_2_iq_type; // @[core.scala:143:32] wire [9:0] _rob_io_commit_uops_2_fu_code; // @[core.scala:143:32] wire [3:0] _rob_io_commit_uops_2_ctrl_br_type; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_ctrl_op1_sel; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_2_ctrl_op2_sel; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_2_ctrl_imm_sel; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_2_ctrl_op_fcn; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ctrl_fcn_dw; // @[core.scala:143:32] wire [2:0] _rob_io_commit_uops_2_ctrl_csr_cmd; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ctrl_is_load; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ctrl_is_sta; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ctrl_is_std; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_iw_state; // @[core.scala:143:32] wire _rob_io_commit_uops_2_iw_p1_poisoned; // @[core.scala:143:32] wire _rob_io_commit_uops_2_iw_p2_poisoned; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_br; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_sfb; // @[core.scala:143:32] wire [15:0] _rob_io_commit_uops_2_br_mask; // @[core.scala:143:32] wire [3:0] _rob_io_commit_uops_2_br_tag; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_2_ftq_idx; // @[core.scala:143:32] wire _rob_io_commit_uops_2_edge_inst; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_2_pc_lob; // @[core.scala:143:32] wire _rob_io_commit_uops_2_taken; // @[core.scala:143:32] wire [19:0] _rob_io_commit_uops_2_imm_packed; // @[core.scala:143:32] wire [11:0] _rob_io_commit_uops_2_csr_addr; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_rob_idx; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_2_ldq_idx; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_2_stq_idx; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_rxq_idx; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_pdst; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_prs1; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_prs2; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_prs3; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_2_ppred; // @[core.scala:143:32] wire _rob_io_commit_uops_2_prs1_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_2_prs2_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_2_prs3_busy; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ppred_busy; // @[core.scala:143:32] wire [6:0] _rob_io_commit_uops_2_stale_pdst; // @[core.scala:143:32] wire _rob_io_commit_uops_2_exception; // @[core.scala:143:32] wire [63:0] _rob_io_commit_uops_2_exc_cause; // @[core.scala:143:32] wire _rob_io_commit_uops_2_bypassable; // @[core.scala:143:32] wire [4:0] _rob_io_commit_uops_2_mem_cmd; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_mem_size; // @[core.scala:143:32] wire _rob_io_commit_uops_2_mem_signed; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_fence; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_fencei; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_amo; // @[core.scala:143:32] wire _rob_io_commit_uops_2_uses_ldq; // @[core.scala:143:32] wire _rob_io_commit_uops_2_uses_stq; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_sys_pc2epc; // @[core.scala:143:32] wire _rob_io_commit_uops_2_is_unique; // @[core.scala:143:32] wire _rob_io_commit_uops_2_flush_on_commit; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ldst_is_rs1; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_2_ldst; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_2_lrs1; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_2_lrs2; // @[core.scala:143:32] wire [5:0] _rob_io_commit_uops_2_lrs3; // @[core.scala:143:32] wire _rob_io_commit_uops_2_ldst_val; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_dst_rtype; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_lrs1_rtype; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_lrs2_rtype; // @[core.scala:143:32] wire _rob_io_commit_uops_2_frs3_en; // @[core.scala:143:32] wire _rob_io_commit_uops_2_fp_val; // @[core.scala:143:32] wire _rob_io_commit_uops_2_fp_single; // @[core.scala:143:32] wire _rob_io_commit_uops_2_xcpt_pf_if; // @[core.scala:143:32] wire _rob_io_commit_uops_2_xcpt_ae_if; // @[core.scala:143:32] wire _rob_io_commit_uops_2_xcpt_ma_if; // @[core.scala:143:32] wire _rob_io_commit_uops_2_bp_debug_if; // @[core.scala:143:32] wire _rob_io_commit_uops_2_bp_xcpt_if; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_debug_fsrc; // @[core.scala:143:32] wire [1:0] _rob_io_commit_uops_2_debug_tsrc; // @[core.scala:143:32] wire _rob_io_commit_fflags_valid; // @[core.scala:143:32] wire [4:0] _rob_io_commit_fflags_bits; // @[core.scala:143:32] wire _rob_io_commit_rbk_valids_0; // @[core.scala:143:32] wire _rob_io_commit_rbk_valids_1; // @[core.scala:143:32] wire _rob_io_commit_rbk_valids_2; // @[core.scala:143:32] wire _rob_io_commit_rollback; // @[core.scala:143:32] wire _rob_io_com_xcpt_valid; // @[core.scala:143:32] wire [4:0] _rob_io_com_xcpt_bits_ftq_idx; // @[core.scala:143:32] wire _rob_io_com_xcpt_bits_edge_inst; // @[core.scala:143:32] wire [5:0] _rob_io_com_xcpt_bits_pc_lob; // @[core.scala:143:32] wire [63:0] _rob_io_com_xcpt_bits_cause; // @[core.scala:143:32] wire [63:0] _rob_io_com_xcpt_bits_badvaddr; // @[core.scala:143:32] wire _rob_io_flush_valid; // @[core.scala:143:32] wire [4:0] _rob_io_flush_bits_ftq_idx; // @[core.scala:143:32] wire _rob_io_flush_bits_edge_inst; // @[core.scala:143:32] wire _rob_io_flush_bits_is_rvc; // @[core.scala:143:32] wire [5:0] _rob_io_flush_bits_pc_lob; // @[core.scala:143:32] wire [2:0] _rob_io_flush_bits_flush_typ; // @[core.scala:143:32] wire _rob_io_empty; // @[core.scala:143:32] wire _rob_io_ready; // @[core.scala:143:32] wire _rob_io_flush_frontend; // @[core.scala:143:32] wire [6:0] _iregister_read_io_rf_read_ports_0_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_1_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_2_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_3_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_4_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_5_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_6_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_rf_read_ports_7_addr; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_valid; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_uopc; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_0_bits_uop_inst; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_inst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_rvc; // @[core.scala:135:32] wire [39:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_pc; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_iq_type; // @[core.scala:135:32] wire [9:0] _iregister_read_io_exe_reqs_0_bits_uop_fu_code; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_br_type; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op1_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op2_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_imm_sel; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_op_fcn; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_0_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_load; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_sta; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ctrl_is_std; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_iw_state; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_iw_p1_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_iw_p2_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_br; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_jalr; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_jal; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_sfb; // @[core.scala:135:32] wire [15:0] _iregister_read_io_exe_reqs_0_bits_uop_br_mask; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_0_bits_uop_br_tag; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ftq_idx; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_edge_inst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_pc_lob; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_taken; // @[core.scala:135:32] wire [19:0] _iregister_read_io_exe_reqs_0_bits_uop_imm_packed; // @[core.scala:135:32] wire [11:0] _iregister_read_io_exe_reqs_0_bits_uop_csr_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_rob_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ldq_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_stq_idx; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_rxq_idx; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_pdst; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_prs1; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_prs2; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_prs3; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_ppred; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_prs1_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_prs2_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_prs3_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ppred_busy; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_0_bits_uop_stale_pdst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_exception; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_0_bits_uop_exc_cause; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_bypassable; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_0_bits_uop_mem_cmd; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_mem_size; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_mem_signed; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_fence; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_fencei; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_amo; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_uses_ldq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_uses_stq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_sys_pc2epc; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_is_unique; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_flush_on_commit; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ldst_is_rs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_ldst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs2; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs3; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_ldst_val; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_dst_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs1_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_lrs2_rtype; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_frs3_en; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_fp_val; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_fp_single; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_pf_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_ae_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_xcpt_ma_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_bp_debug_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_0_bits_uop_bp_xcpt_if; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_fsrc; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_0_bits_uop_debug_tsrc; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_0_bits_rs1_data; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_0_bits_rs2_data; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_valid; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_uopc; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_1_bits_uop_inst; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_inst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_rvc; // @[core.scala:135:32] wire [39:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_pc; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_iq_type; // @[core.scala:135:32] wire [9:0] _iregister_read_io_exe_reqs_1_bits_uop_fu_code; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_br_type; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op1_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op2_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_imm_sel; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_op_fcn; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_1_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_load; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_sta; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ctrl_is_std; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_iw_state; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_iw_p1_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_iw_p2_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_br; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_jalr; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_jal; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_sfb; // @[core.scala:135:32] wire [15:0] _iregister_read_io_exe_reqs_1_bits_uop_br_mask; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_1_bits_uop_br_tag; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ftq_idx; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_edge_inst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_pc_lob; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_taken; // @[core.scala:135:32] wire [19:0] _iregister_read_io_exe_reqs_1_bits_uop_imm_packed; // @[core.scala:135:32] wire [11:0] _iregister_read_io_exe_reqs_1_bits_uop_csr_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_rob_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ldq_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_stq_idx; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_rxq_idx; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_pdst; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_prs1; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_prs2; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_prs3; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_ppred; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_prs1_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_prs2_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_prs3_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ppred_busy; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_1_bits_uop_stale_pdst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_exception; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_1_bits_uop_exc_cause; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_bypassable; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_1_bits_uop_mem_cmd; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_mem_size; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_mem_signed; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_fence; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_fencei; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_amo; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_uses_ldq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_uses_stq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_sys_pc2epc; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_is_unique; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_flush_on_commit; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ldst_is_rs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_ldst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs2; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs3; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_ldst_val; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_dst_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs1_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_lrs2_rtype; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_frs3_en; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_fp_val; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_fp_single; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_pf_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_ae_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_xcpt_ma_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_bp_debug_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_1_bits_uop_bp_xcpt_if; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_fsrc; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_1_bits_uop_debug_tsrc; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_1_bits_rs1_data; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_1_bits_rs2_data; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_valid; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_uopc; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_2_bits_uop_inst; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_inst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_rvc; // @[core.scala:135:32] wire [39:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_pc; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_iq_type; // @[core.scala:135:32] wire [9:0] _iregister_read_io_exe_reqs_2_bits_uop_fu_code; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_br_type; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_op1_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_op2_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_imm_sel; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_op_fcn; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_2_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_is_load; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_is_sta; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ctrl_is_std; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_iw_state; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_iw_p1_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_iw_p2_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_br; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_jalr; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_jal; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_sfb; // @[core.scala:135:32] wire [15:0] _iregister_read_io_exe_reqs_2_bits_uop_br_mask; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_2_bits_uop_br_tag; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ftq_idx; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_edge_inst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_pc_lob; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_taken; // @[core.scala:135:32] wire [19:0] _iregister_read_io_exe_reqs_2_bits_uop_imm_packed; // @[core.scala:135:32] wire [11:0] _iregister_read_io_exe_reqs_2_bits_uop_csr_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_rob_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ldq_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_stq_idx; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_rxq_idx; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_pdst; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_prs1; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_prs2; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_prs3; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_ppred; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_prs1_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_prs2_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_prs3_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ppred_busy; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_2_bits_uop_stale_pdst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_exception; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_2_bits_uop_exc_cause; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_bypassable; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_2_bits_uop_mem_cmd; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_mem_size; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_mem_signed; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_fence; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_fencei; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_amo; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_uses_ldq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_uses_stq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_sys_pc2epc; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_is_unique; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_flush_on_commit; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ldst_is_rs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_ldst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs2; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs3; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_ldst_val; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_dst_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs1_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_lrs2_rtype; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_frs3_en; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_fp_val; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_fp_single; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_xcpt_pf_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_xcpt_ae_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_xcpt_ma_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_bp_debug_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_2_bits_uop_bp_xcpt_if; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_fsrc; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_2_bits_uop_debug_tsrc; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_2_bits_rs1_data; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_2_bits_rs2_data; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_valid; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_uopc; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_3_bits_uop_inst; // @[core.scala:135:32] wire [31:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_inst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_rvc; // @[core.scala:135:32] wire [39:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_pc; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_iq_type; // @[core.scala:135:32] wire [9:0] _iregister_read_io_exe_reqs_3_bits_uop_fu_code; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_br_type; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_op1_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_op2_sel; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_imm_sel; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_op_fcn; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_fcn_dw; // @[core.scala:135:32] wire [2:0] _iregister_read_io_exe_reqs_3_bits_uop_ctrl_csr_cmd; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_is_load; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_is_sta; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ctrl_is_std; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_iw_state; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_iw_p1_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_iw_p2_poisoned; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_br; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_jalr; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_jal; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_sfb; // @[core.scala:135:32] wire [15:0] _iregister_read_io_exe_reqs_3_bits_uop_br_mask; // @[core.scala:135:32] wire [3:0] _iregister_read_io_exe_reqs_3_bits_uop_br_tag; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ftq_idx; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_edge_inst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_pc_lob; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_taken; // @[core.scala:135:32] wire [19:0] _iregister_read_io_exe_reqs_3_bits_uop_imm_packed; // @[core.scala:135:32] wire [11:0] _iregister_read_io_exe_reqs_3_bits_uop_csr_addr; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_rob_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ldq_idx; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_stq_idx; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_rxq_idx; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_pdst; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_prs1; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_prs2; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_prs3; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_ppred; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_prs1_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_prs2_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_prs3_busy; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ppred_busy; // @[core.scala:135:32] wire [6:0] _iregister_read_io_exe_reqs_3_bits_uop_stale_pdst; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_exception; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_3_bits_uop_exc_cause; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_bypassable; // @[core.scala:135:32] wire [4:0] _iregister_read_io_exe_reqs_3_bits_uop_mem_cmd; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_mem_size; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_mem_signed; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_fence; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_fencei; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_amo; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_uses_ldq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_uses_stq; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_sys_pc2epc; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_is_unique; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_flush_on_commit; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ldst_is_rs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_ldst; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs1; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs2; // @[core.scala:135:32] wire [5:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs3; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_ldst_val; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_dst_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs1_rtype; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_lrs2_rtype; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_frs3_en; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_fp_val; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_fp_single; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_xcpt_pf_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_xcpt_ae_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_xcpt_ma_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_bp_debug_if; // @[core.scala:135:32] wire _iregister_read_io_exe_reqs_3_bits_uop_bp_xcpt_if; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_fsrc; // @[core.scala:135:32] wire [1:0] _iregister_read_io_exe_reqs_3_bits_uop_debug_tsrc; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_3_bits_rs1_data; // @[core.scala:135:32] wire [63:0] _iregister_read_io_exe_reqs_3_bits_rs2_data; // @[core.scala:135:32] wire _ll_wbarb_io_in_1_ready; // @[core.scala:132:32] wire _ll_wbarb_io_out_valid; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_uopc; // @[core.scala:132:32] wire [31:0] _ll_wbarb_io_out_bits_uop_inst; // @[core.scala:132:32] wire [31:0] _ll_wbarb_io_out_bits_uop_debug_inst; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_rvc; // @[core.scala:132:32] wire [39:0] _ll_wbarb_io_out_bits_uop_debug_pc; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_uop_iq_type; // @[core.scala:132:32] wire [9:0] _ll_wbarb_io_out_bits_uop_fu_code; // @[core.scala:132:32] wire [3:0] _ll_wbarb_io_out_bits_uop_ctrl_br_type; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_ctrl_op1_sel; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_op2_sel; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_imm_sel; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_uop_ctrl_op_fcn; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ctrl_fcn_dw; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_uop_ctrl_csr_cmd; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ctrl_is_load; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ctrl_is_sta; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ctrl_is_std; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_iw_state; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_iw_p1_poisoned; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_iw_p2_poisoned; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_br; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_jalr; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_jal; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_sfb; // @[core.scala:132:32] wire [15:0] _ll_wbarb_io_out_bits_uop_br_mask; // @[core.scala:132:32] wire [3:0] _ll_wbarb_io_out_bits_uop_br_tag; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_uop_ftq_idx; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_edge_inst; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_uop_pc_lob; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_taken; // @[core.scala:132:32] wire [19:0] _ll_wbarb_io_out_bits_uop_imm_packed; // @[core.scala:132:32] wire [11:0] _ll_wbarb_io_out_bits_uop_csr_addr; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_rob_idx; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_uop_ldq_idx; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_uop_stq_idx; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_rxq_idx; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_pdst; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_prs1; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_prs2; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_prs3; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_uop_ppred; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_prs1_busy; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_prs2_busy; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_prs3_busy; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ppred_busy; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_uop_stale_pdst; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_exception; // @[core.scala:132:32] wire [63:0] _ll_wbarb_io_out_bits_uop_exc_cause; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_bypassable; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_uop_mem_cmd; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_mem_size; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_mem_signed; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_fence; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_fencei; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_amo; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_uses_ldq; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_uses_stq; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_sys_pc2epc; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_is_unique; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_flush_on_commit; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ldst_is_rs1; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_uop_ldst; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_uop_lrs1; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_uop_lrs2; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_uop_lrs3; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_ldst_val; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_dst_rtype; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_lrs1_rtype; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_lrs2_rtype; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_frs3_en; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_fp_val; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_fp_single; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_xcpt_pf_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_xcpt_ae_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_xcpt_ma_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_bp_debug_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_uop_bp_xcpt_if; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_debug_fsrc; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_uop_debug_tsrc; // @[core.scala:132:32] wire [63:0] _ll_wbarb_io_out_bits_data; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_predicated; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_valid; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_uopc; // @[core.scala:132:32] wire [31:0] _ll_wbarb_io_out_bits_fflags_bits_uop_inst; // @[core.scala:132:32] wire [31:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_inst; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_rvc; // @[core.scala:132:32] wire [39:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_pc; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_iq_type; // @[core.scala:132:32] wire [9:0] _ll_wbarb_io_out_bits_fflags_bits_uop_fu_code; // @[core.scala:132:32] wire [3:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:132:32] wire [2:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_iw_state; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_br; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_jalr; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_jal; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_sfb; // @[core.scala:132:32] wire [15:0] _ll_wbarb_io_out_bits_fflags_bits_uop_br_mask; // @[core.scala:132:32] wire [3:0] _ll_wbarb_io_out_bits_fflags_bits_uop_br_tag; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ftq_idx; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_edge_inst; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_pc_lob; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_taken; // @[core.scala:132:32] wire [19:0] _ll_wbarb_io_out_bits_fflags_bits_uop_imm_packed; // @[core.scala:132:32] wire [11:0] _ll_wbarb_io_out_bits_fflags_bits_uop_csr_addr; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_rob_idx; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ldq_idx; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_stq_idx; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_rxq_idx; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_pdst; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs1; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs2; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_prs3; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ppred; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs1_busy; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs2_busy; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_prs3_busy; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ppred_busy; // @[core.scala:132:32] wire [6:0] _ll_wbarb_io_out_bits_fflags_bits_uop_stale_pdst; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_exception; // @[core.scala:132:32] wire [63:0] _ll_wbarb_io_out_bits_fflags_bits_uop_exc_cause; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_bypassable; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_uop_mem_cmd; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_mem_size; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_mem_signed; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_fence; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_fencei; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_amo; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_uses_ldq; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_uses_stq; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_is_unique; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_ldst; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs1; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs2; // @[core.scala:132:32] wire [5:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs3; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_ldst_val; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_dst_rtype; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_frs3_en; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_fp_val; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_fp_single; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:132:32] wire _ll_wbarb_io_out_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:132:32] wire [1:0] _ll_wbarb_io_out_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:132:32] wire [4:0] _ll_wbarb_io_out_bits_fflags_bits_flags; // @[core.scala:132:32] wire [63:0] _iregfile_io_read_ports_0_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_1_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_2_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_3_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_4_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_5_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_6_data; // @[core.scala:116:32] wire [63:0] _iregfile_io_read_ports_7_data; // @[core.scala:116:32] wire _dispatcher_io_ren_uops_0_ready; // @[core.scala:114:32] wire _dispatcher_io_ren_uops_1_ready; // @[core.scala:114:32] wire _dispatcher_io_ren_uops_2_ready; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_2_0_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_2_0_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_2_0_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_2_0_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_2_0_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_2_0_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_2_0_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_2_0_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_2_0_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_0_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_2_1_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_2_1_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_2_1_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_2_1_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_2_1_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_2_1_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_2_1_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_2_1_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_2_1_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_1_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_2_2_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_2_2_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_2_2_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_2_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_2_2_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_2_2_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_2_2_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_2_2_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_2_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_2_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_2_2_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_2_2_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_2_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_2_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_2_2_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_2_2_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_2_2_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_2_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_2_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_2_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_2_2_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_2_2_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_2_2_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_1_0_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_1_0_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_1_0_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_1_0_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_1_0_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_1_0_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_1_0_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_1_0_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_1_0_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_0_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_1_1_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_1_1_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_1_1_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_1_1_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_1_1_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_1_1_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_1_1_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_1_1_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_1_1_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_1_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_1_2_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_1_2_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_1_2_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_2_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_1_2_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_1_2_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_1_2_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_1_2_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_2_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_2_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_1_2_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_1_2_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_2_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_2_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_1_2_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_1_2_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_1_2_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_2_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_2_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_2_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_1_2_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_1_2_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_1_2_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_0_0_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_0_0_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_0_0_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_0_0_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_0_0_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_0_0_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_0_0_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_0_0_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_0_0_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_0_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_0_1_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_0_1_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_0_1_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_0_1_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_0_1_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_0_1_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_0_1_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_0_1_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_0_1_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_1_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_debug_tsrc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_valid; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_uopc; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_0_2_bits_inst; // @[core.scala:114:32] wire [31:0] _dispatcher_io_dis_uops_0_2_bits_debug_inst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_rvc; // @[core.scala:114:32] wire [39:0] _dispatcher_io_dis_uops_0_2_bits_debug_pc; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_2_bits_iq_type; // @[core.scala:114:32] wire [9:0] _dispatcher_io_dis_uops_0_2_bits_fu_code; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_br_type; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_op1_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_op2_sel; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_imm_sel; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_op_fcn; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_ctrl_fcn_dw; // @[core.scala:114:32] wire [2:0] _dispatcher_io_dis_uops_0_2_bits_ctrl_csr_cmd; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_ctrl_is_load; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_ctrl_is_sta; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_ctrl_is_std; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_iw_state; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_iw_p1_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_iw_p2_poisoned; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_br; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_jalr; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_jal; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_sfb; // @[core.scala:114:32] wire [15:0] _dispatcher_io_dis_uops_0_2_bits_br_mask; // @[core.scala:114:32] wire [3:0] _dispatcher_io_dis_uops_0_2_bits_br_tag; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_2_bits_ftq_idx; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_edge_inst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_2_bits_pc_lob; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_taken; // @[core.scala:114:32] wire [19:0] _dispatcher_io_dis_uops_0_2_bits_imm_packed; // @[core.scala:114:32] wire [11:0] _dispatcher_io_dis_uops_0_2_bits_csr_addr; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_rob_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_2_bits_ldq_idx; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_2_bits_stq_idx; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_rxq_idx; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_pdst; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_prs1; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_prs2; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_prs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_prs1_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_prs2_busy; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_prs3_busy; // @[core.scala:114:32] wire [6:0] _dispatcher_io_dis_uops_0_2_bits_stale_pdst; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_exception; // @[core.scala:114:32] wire [63:0] _dispatcher_io_dis_uops_0_2_bits_exc_cause; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_bypassable; // @[core.scala:114:32] wire [4:0] _dispatcher_io_dis_uops_0_2_bits_mem_cmd; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_mem_size; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_mem_signed; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_fence; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_fencei; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_amo; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_uses_ldq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_uses_stq; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_sys_pc2epc; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_is_unique; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_flush_on_commit; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_ldst_is_rs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_2_bits_ldst; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_2_bits_lrs1; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_2_bits_lrs2; // @[core.scala:114:32] wire [5:0] _dispatcher_io_dis_uops_0_2_bits_lrs3; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_ldst_val; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_dst_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_lrs1_rtype; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_lrs2_rtype; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_frs3_en; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_fp_val; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_fp_single; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_xcpt_pf_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_xcpt_ae_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_xcpt_ma_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_bp_debug_if; // @[core.scala:114:32] wire _dispatcher_io_dis_uops_0_2_bits_bp_xcpt_if; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_debug_fsrc; // @[core.scala:114:32] wire [1:0] _dispatcher_io_dis_uops_0_2_bits_debug_tsrc; // @[core.scala:114:32] wire _int_issue_unit_io_dis_uops_0_ready; // @[core.scala:110:32] wire _int_issue_unit_io_dis_uops_1_ready; // @[core.scala:110:32] wire _int_issue_unit_io_dis_uops_2_ready; // @[core.scala:110:32] wire _mem_issue_unit_io_dis_uops_0_ready; // @[core.scala:108:32] wire _mem_issue_unit_io_dis_uops_1_ready; // @[core.scala:108:32] wire _mem_issue_unit_io_dis_uops_2_ready; // @[core.scala:108:32] wire _mem_issue_unit_io_iss_valids_0; // @[core.scala:108:32] wire _mem_issue_unit_io_iss_uops_0_uses_ldq; // @[core.scala:108:32] wire _fp_rename_stage_io_ren_stalls_0; // @[core.scala:104:46] wire _fp_rename_stage_io_ren_stalls_1; // @[core.scala:104:46] wire _fp_rename_stage_io_ren_stalls_2; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_0_pdst; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_0_prs1; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_0_prs2; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_0_prs1_busy; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_0_prs2_busy; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_0_prs3_busy; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_1_pdst; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_1_prs1; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_1_prs2; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_1_prs1_busy; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_1_prs2_busy; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_1_prs3_busy; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_1_stale_pdst; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_2_pdst; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_2_prs1; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_2_prs2; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_2_prs1_busy; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_2_prs2_busy; // @[core.scala:104:46] wire _fp_rename_stage_io_ren2_uops_2_prs3_busy; // @[core.scala:104:46] wire [6:0] _fp_rename_stage_io_ren2_uops_2_stale_pdst; // @[core.scala:104:46] wire _rename_stage_io_ren_stalls_0; // @[core.scala:103:32] wire _rename_stage_io_ren_stalls_1; // @[core.scala:103:32] wire _rename_stage_io_ren_stalls_2; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_0_pdst; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_0_prs1; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_0_prs2; // @[core.scala:103:32] wire _rename_stage_io_ren2_uops_0_prs1_busy; // @[core.scala:103:32] wire _rename_stage_io_ren2_uops_0_prs2_busy; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_1_pdst; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_1_prs1; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_1_prs2; // @[core.scala:103:32] wire _rename_stage_io_ren2_uops_1_prs1_busy; // @[core.scala:103:32] wire _rename_stage_io_ren2_uops_1_prs2_busy; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_1_stale_pdst; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_2_pdst; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_2_prs1; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_2_prs2; // @[core.scala:103:32] wire _rename_stage_io_ren2_uops_2_prs1_busy; // @[core.scala:103:32] wire _rename_stage_io_ren2_uops_2_prs2_busy; // @[core.scala:103:32] wire [6:0] _rename_stage_io_ren2_uops_2_stale_pdst; // @[core.scala:103:32] wire [31:0] _decode_units_2_io_csr_decode_inst; // @[core.scala:101:79] wire [31:0] _decode_units_1_io_csr_decode_inst; // @[core.scala:101:79] wire [31:0] _decode_units_0_io_csr_decode_inst; // @[core.scala:101:79] wire _FpPipeline_io_dis_uops_0_ready; // @[core.scala:80:37] wire _FpPipeline_io_dis_uops_1_ready; // @[core.scala:80:37] wire _FpPipeline_io_dis_uops_2_ready; // @[core.scala:80:37] wire _FpPipeline_io_from_int_ready; // @[core.scala:80:37] wire _FpPipeline_io_to_int_valid; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_uopc; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_to_int_bits_uop_inst; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_to_int_bits_uop_debug_inst; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_rvc; // @[core.scala:80:37] wire [39:0] _FpPipeline_io_to_int_bits_uop_debug_pc; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_uop_iq_type; // @[core.scala:80:37] wire [9:0] _FpPipeline_io_to_int_bits_uop_fu_code; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_to_int_bits_uop_ctrl_br_type; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_ctrl_op1_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_op2_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_imm_sel; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_uop_ctrl_op_fcn; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ctrl_is_load; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ctrl_is_sta; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ctrl_is_std; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_iw_state; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_iw_p1_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_iw_p2_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_br; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_jalr; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_jal; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_sfb; // @[core.scala:80:37] wire [15:0] _FpPipeline_io_to_int_bits_uop_br_mask; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_to_int_bits_uop_br_tag; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_uop_ftq_idx; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_edge_inst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_uop_pc_lob; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_taken; // @[core.scala:80:37] wire [19:0] _FpPipeline_io_to_int_bits_uop_imm_packed; // @[core.scala:80:37] wire [11:0] _FpPipeline_io_to_int_bits_uop_csr_addr; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_rob_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_uop_ldq_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_uop_stq_idx; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_rxq_idx; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_pdst; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_prs1; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_prs2; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_prs3; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_uop_ppred; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_prs1_busy; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_prs2_busy; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_prs3_busy; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ppred_busy; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_uop_stale_pdst; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_exception; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_to_int_bits_uop_exc_cause; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_bypassable; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_uop_mem_cmd; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_mem_size; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_mem_signed; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_fence; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_fencei; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_amo; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_uses_ldq; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_uses_stq; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_sys_pc2epc; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_is_unique; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_flush_on_commit; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ldst_is_rs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_uop_ldst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs2; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_uop_lrs3; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_ldst_val; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_dst_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_lrs1_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_lrs2_rtype; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_frs3_en; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_fp_val; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_fp_single; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_xcpt_pf_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_xcpt_ae_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_xcpt_ma_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_bp_debug_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_uop_bp_xcpt_if; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_debug_fsrc; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_uop_debug_tsrc; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_to_int_bits_data; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_predicated; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_valid; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_uopc; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_inst; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_inst; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_rvc; // @[core.scala:80:37] wire [39:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_pc; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_iq_type; // @[core.scala:80:37] wire [9:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_fu_code; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_state; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_br; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_jalr; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_jal; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_sfb; // @[core.scala:80:37] wire [15:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_br_mask; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_br_tag; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ftq_idx; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_edge_inst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_pc_lob; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_taken; // @[core.scala:80:37] wire [19:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_imm_packed; // @[core.scala:80:37] wire [11:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_csr_addr; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_rob_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ldq_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_stq_idx; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_rxq_idx; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_pdst; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs1; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs2; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_prs3; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ppred; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs1_busy; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs2_busy; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_prs3_busy; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ppred_busy; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_stale_pdst; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_exception; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_exc_cause; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bypassable; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_cmd; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_size; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_mem_signed; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_fence; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_fencei; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_amo; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_uses_ldq; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_uses_stq; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_is_unique; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs2; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs3; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_ldst_val; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_dst_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_frs3_en; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_fp_val; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_fp_single; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:80:37] wire _FpPipeline_io_to_int_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_to_int_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_to_int_bits_fflags_bits_flags; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_valid; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_uopc; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_0_bits_uop_inst; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_0_bits_uop_debug_inst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_rvc; // @[core.scala:80:37] wire [39:0] _FpPipeline_io_wakeups_0_bits_uop_debug_pc; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_iq_type; // @[core.scala:80:37] wire [9:0] _FpPipeline_io_wakeups_0_bits_uop_fu_code; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_br_type; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op1_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op2_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_imm_sel; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_op_fcn; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_load; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_sta; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ctrl_is_std; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_iw_state; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_iw_p1_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_br; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_jalr; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_jal; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_sfb; // @[core.scala:80:37] wire [15:0] _FpPipeline_io_wakeups_0_bits_uop_br_mask; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_0_bits_uop_br_tag; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ftq_idx; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_edge_inst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_pc_lob; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_taken; // @[core.scala:80:37] wire [19:0] _FpPipeline_io_wakeups_0_bits_uop_imm_packed; // @[core.scala:80:37] wire [11:0] _FpPipeline_io_wakeups_0_bits_uop_csr_addr; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_rob_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ldq_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_stq_idx; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_rxq_idx; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_pdst; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_prs1; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_prs2; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_prs3; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_ppred; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_prs1_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_prs2_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_prs3_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ppred_busy; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_uop_stale_pdst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_exception; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_wakeups_0_bits_uop_exc_cause; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_bypassable; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_uop_mem_cmd; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_mem_size; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_mem_signed; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_fence; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_fencei; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_amo; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_uses_ldq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_uses_stq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_is_unique; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_ldst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs2; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_uop_lrs3; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_ldst_val; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_dst_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_frs3_en; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_fp_val; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_fp_single; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:80:37] wire [64:0] _FpPipeline_io_wakeups_0_bits_data; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_predicated; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_valid; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uopc; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_inst; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[core.scala:80:37] wire [39:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iq_type; // @[core.scala:80:37] wire [9:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fu_code; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_state; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_br; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_jal; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[core.scala:80:37] wire [15:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_br_mask; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_br_tag; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_taken; // @[core.scala:80:37] wire [19:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[core.scala:80:37] wire [11:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_pdst; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs1; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs2; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs3; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ppred; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_exception; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bypassable; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_size; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_fence; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_amo; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_is_unique; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs2; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs3; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fp_val; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_fp_single; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_0_bits_fflags_bits_flags; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_valid; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_uopc; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_1_bits_uop_inst; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_1_bits_uop_debug_inst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_rvc; // @[core.scala:80:37] wire [39:0] _FpPipeline_io_wakeups_1_bits_uop_debug_pc; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_iq_type; // @[core.scala:80:37] wire [9:0] _FpPipeline_io_wakeups_1_bits_uop_fu_code; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_br_type; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op1_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op2_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_imm_sel; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_op_fcn; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_load; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_sta; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ctrl_is_std; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_iw_state; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_iw_p1_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_br; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_jalr; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_jal; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_sfb; // @[core.scala:80:37] wire [15:0] _FpPipeline_io_wakeups_1_bits_uop_br_mask; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_1_bits_uop_br_tag; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ftq_idx; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_edge_inst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_pc_lob; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_taken; // @[core.scala:80:37] wire [19:0] _FpPipeline_io_wakeups_1_bits_uop_imm_packed; // @[core.scala:80:37] wire [11:0] _FpPipeline_io_wakeups_1_bits_uop_csr_addr; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_rob_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ldq_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_stq_idx; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_rxq_idx; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_pdst; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_prs1; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_prs2; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_prs3; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_ppred; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_prs1_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_prs2_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_prs3_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ppred_busy; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_uop_stale_pdst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_exception; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_wakeups_1_bits_uop_exc_cause; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_bypassable; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_uop_mem_cmd; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_mem_size; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_mem_signed; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_fence; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_fencei; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_amo; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_uses_ldq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_uses_stq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_is_unique; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_ldst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs2; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_uop_lrs3; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_ldst_val; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_dst_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_frs3_en; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_fp_val; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_fp_single; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:80:37] wire [64:0] _FpPipeline_io_wakeups_1_bits_data; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_valid; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uopc; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_inst; // @[core.scala:80:37] wire [31:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_inst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_rvc; // @[core.scala:80:37] wire [39:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_pc; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iq_type; // @[core.scala:80:37] wire [9:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fu_code; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:80:37] wire [2:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_state; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_br; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_jalr; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_jal; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_sfb; // @[core.scala:80:37] wire [15:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_br_mask; // @[core.scala:80:37] wire [3:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_br_tag; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ftq_idx; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_edge_inst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_pc_lob; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_taken; // @[core.scala:80:37] wire [19:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_imm_packed; // @[core.scala:80:37] wire [11:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_csr_addr; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_rob_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldq_idx; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_stq_idx; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_rxq_idx; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_pdst; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs1; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs2; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs3; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ppred; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs1_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs2_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_prs3_busy; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ppred_busy; // @[core.scala:80:37] wire [6:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_stale_pdst; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_exception; // @[core.scala:80:37] wire [63:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_exc_cause; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bypassable; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_cmd; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_size; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_mem_signed; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_fence; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_fencei; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_amo; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uses_ldq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_uses_stq; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_is_unique; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs1; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs2; // @[core.scala:80:37] wire [5:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs3; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_ldst_val; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_dst_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_frs3_en; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fp_val; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_fp_single; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:80:37] wire _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:80:37] wire [1:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:80:37] wire [4:0] _FpPipeline_io_wakeups_1_bits_fflags_bits_flags; // @[core.scala:80:37] wire [64:0] _FpPipeline_io_debug_wb_wdata_0; // @[core.scala:80:37] wire [64:0] _FpPipeline_io_debug_wb_wdata_1; // @[core.scala:80:37] wire _alu_exe_unit_2_io_iresp_valid; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_2_io_iresp_bits_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_2_io_iresp_bits_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_2_io_iresp_bits_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_2_io_iresp_bits_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_2_io_iresp_bits_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_2_io_iresp_bits_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_iresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_2_io_iresp_bits_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_iresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_2_io_iresp_bits_data; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_2_io_bypass_0_bits_data; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_2_io_bypass_1_bits_data; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_2_io_bypass_2_bits_data; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_2_io_brinfo_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_2_io_brinfo_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_2_io_brinfo_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_brinfo_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_2_io_brinfo_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_brinfo_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_2_io_brinfo_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_2_io_brinfo_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_brinfo_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_2_io_brinfo_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_2_io_brinfo_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_brinfo_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_brinfo_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_2_io_brinfo_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_2_io_brinfo_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_2_io_brinfo_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_brinfo_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_brinfo_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_brinfo_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_2_io_brinfo_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_uop_debug_tsrc; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_valid; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_mispredict; // @[execution-units.scala:119:32] wire _alu_exe_unit_2_io_brinfo_taken; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_2_io_brinfo_cfi_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_2_io_brinfo_pc_sel; // @[execution-units.scala:119:32] wire [20:0] _alu_exe_unit_2_io_brinfo_target_offset; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_1_io_fu_types; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_valid; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_iresp_bits_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_1_io_iresp_bits_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_1_io_iresp_bits_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_iresp_bits_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_1_io_iresp_bits_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_1_io_iresp_bits_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_iresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_1_io_iresp_bits_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_iresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_1_io_iresp_bits_data; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_valid; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_1_io_ll_fresp_bits_data; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_predicated; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_valid; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_uop_debug_tsrc; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_ll_fresp_bits_fflags_bits_flags; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_1_io_bypass_0_bits_data; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_brinfo_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_1_io_brinfo_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_1_io_brinfo_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_brinfo_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_1_io_brinfo_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_brinfo_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_1_io_brinfo_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_1_io_brinfo_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_brinfo_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_1_io_brinfo_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_1_io_brinfo_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_brinfo_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_brinfo_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_1_io_brinfo_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_1_io_brinfo_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_1_io_brinfo_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_brinfo_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_brinfo_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_brinfo_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_1_io_brinfo_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_uop_debug_tsrc; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_valid; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_mispredict; // @[execution-units.scala:119:32] wire _alu_exe_unit_1_io_brinfo_taken; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_1_io_brinfo_cfi_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_1_io_brinfo_pc_sel; // @[execution-units.scala:119:32] wire [20:0] _alu_exe_unit_1_io_brinfo_target_offset; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_io_fu_types; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_valid; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_io_iresp_bits_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_io_iresp_bits_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_io_iresp_bits_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_iresp_bits_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_io_iresp_bits_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_io_iresp_bits_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_io_iresp_bits_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_iresp_bits_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_io_iresp_bits_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_io_iresp_bits_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_iresp_bits_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_iresp_bits_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_iresp_bits_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_io_iresp_bits_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_iresp_bits_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_iresp_bits_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_iresp_bits_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_io_iresp_bits_data; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_valid; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_io_bypass_0_bits_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_io_bypass_0_bits_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_bypass_0_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_io_bypass_0_bits_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_io_bypass_0_bits_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_io_bypass_0_bits_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_io_bypass_0_bits_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_bypass_0_bits_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_io_bypass_0_bits_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_bypass_0_bits_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_bypass_0_bits_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_bypass_0_bits_uop_debug_tsrc; // @[execution-units.scala:119:32] wire [64:0] _alu_exe_unit_io_bypass_0_bits_data; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_uopc; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_io_brinfo_uop_inst; // @[execution-units.scala:119:32] wire [31:0] _alu_exe_unit_io_brinfo_uop_debug_inst; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_rvc; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_io_brinfo_uop_debug_pc; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_brinfo_uop_iq_type; // @[execution-units.scala:119:32] wire [9:0] _alu_exe_unit_io_brinfo_uop_fu_code; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_io_brinfo_uop_ctrl_br_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_ctrl_op1_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_op2_sel; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_imm_sel; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_brinfo_uop_ctrl_op_fcn; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ctrl_fcn_dw; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_brinfo_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ctrl_is_load; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ctrl_is_sta; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ctrl_is_std; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_iw_state; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_iw_p1_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_iw_p2_poisoned; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_br; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_jalr; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_jal; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_sfb; // @[execution-units.scala:119:32] wire [15:0] _alu_exe_unit_io_brinfo_uop_br_mask; // @[execution-units.scala:119:32] wire [3:0] _alu_exe_unit_io_brinfo_uop_br_tag; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_brinfo_uop_ftq_idx; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_edge_inst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_brinfo_uop_pc_lob; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_taken; // @[execution-units.scala:119:32] wire [19:0] _alu_exe_unit_io_brinfo_uop_imm_packed; // @[execution-units.scala:119:32] wire [11:0] _alu_exe_unit_io_brinfo_uop_csr_addr; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_rob_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_brinfo_uop_ldq_idx; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_brinfo_uop_stq_idx; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_rxq_idx; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_pdst; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_prs1; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_prs2; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_prs3; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_brinfo_uop_ppred; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_prs1_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_prs2_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_prs3_busy; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ppred_busy; // @[execution-units.scala:119:32] wire [6:0] _alu_exe_unit_io_brinfo_uop_stale_pdst; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_exception; // @[execution-units.scala:119:32] wire [63:0] _alu_exe_unit_io_brinfo_uop_exc_cause; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_bypassable; // @[execution-units.scala:119:32] wire [4:0] _alu_exe_unit_io_brinfo_uop_mem_cmd; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_mem_size; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_mem_signed; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_fence; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_fencei; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_amo; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_uses_ldq; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_uses_stq; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_sys_pc2epc; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_is_unique; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_flush_on_commit; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ldst_is_rs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_brinfo_uop_ldst; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs1; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs2; // @[execution-units.scala:119:32] wire [5:0] _alu_exe_unit_io_brinfo_uop_lrs3; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_ldst_val; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_dst_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_lrs1_rtype; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_lrs2_rtype; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_frs3_en; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_fp_val; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_fp_single; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_xcpt_pf_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_xcpt_ae_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_xcpt_ma_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_bp_debug_if; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_uop_bp_xcpt_if; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_debug_fsrc; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_uop_debug_tsrc; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_valid; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_mispredict; // @[execution-units.scala:119:32] wire _alu_exe_unit_io_brinfo_taken; // @[execution-units.scala:119:32] wire [2:0] _alu_exe_unit_io_brinfo_cfi_type; // @[execution-units.scala:119:32] wire [1:0] _alu_exe_unit_io_brinfo_pc_sel; // @[execution-units.scala:119:32] wire [39:0] _alu_exe_unit_io_brinfo_jalr_target; // @[execution-units.scala:119:32] wire [20:0] _alu_exe_unit_io_brinfo_target_offset; // @[execution-units.scala:119:32] wire _memExeUnit_io_ll_iresp_valid; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_uopc; // @[execution-units.scala:108:30] wire [31:0] _memExeUnit_io_ll_iresp_bits_uop_inst; // @[execution-units.scala:108:30] wire [31:0] _memExeUnit_io_ll_iresp_bits_uop_debug_inst; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_rvc; // @[execution-units.scala:108:30] wire [39:0] _memExeUnit_io_ll_iresp_bits_uop_debug_pc; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_iq_type; // @[execution-units.scala:108:30] wire [9:0] _memExeUnit_io_ll_iresp_bits_uop_fu_code; // @[execution-units.scala:108:30] wire [3:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_br_type; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_load; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ctrl_is_std; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_iw_state; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_br; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_jalr; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_jal; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_sfb; // @[execution-units.scala:108:30] wire [15:0] _memExeUnit_io_ll_iresp_bits_uop_br_mask; // @[execution-units.scala:108:30] wire [3:0] _memExeUnit_io_ll_iresp_bits_uop_br_tag; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ftq_idx; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_edge_inst; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_pc_lob; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_taken; // @[execution-units.scala:108:30] wire [19:0] _memExeUnit_io_ll_iresp_bits_uop_imm_packed; // @[execution-units.scala:108:30] wire [11:0] _memExeUnit_io_ll_iresp_bits_uop_csr_addr; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_rob_idx; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ldq_idx; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_stq_idx; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_rxq_idx; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_pdst; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_prs1; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_prs2; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_prs3; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_ppred; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_prs1_busy; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_prs2_busy; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_prs3_busy; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ppred_busy; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_iresp_bits_uop_stale_pdst; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_exception; // @[execution-units.scala:108:30] wire [63:0] _memExeUnit_io_ll_iresp_bits_uop_exc_cause; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_bypassable; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_iresp_bits_uop_mem_cmd; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_mem_size; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_mem_signed; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_fence; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_fencei; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_amo; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_uses_ldq; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_uses_stq; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_is_unique; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_flush_on_commit; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_ldst; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs1; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs2; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_iresp_bits_uop_lrs3; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_ldst_val; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_dst_rtype; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_lrs1_rtype; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_lrs2_rtype; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_frs3_en; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_fp_val; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_fp_single; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_bp_debug_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_iresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_debug_fsrc; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_iresp_bits_uop_debug_tsrc; // @[execution-units.scala:108:30] wire [64:0] _memExeUnit_io_ll_iresp_bits_data; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_valid; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_uopc; // @[execution-units.scala:108:30] wire [31:0] _memExeUnit_io_ll_fresp_bits_uop_inst; // @[execution-units.scala:108:30] wire [31:0] _memExeUnit_io_ll_fresp_bits_uop_debug_inst; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_rvc; // @[execution-units.scala:108:30] wire [39:0] _memExeUnit_io_ll_fresp_bits_uop_debug_pc; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_iq_type; // @[execution-units.scala:108:30] wire [9:0] _memExeUnit_io_ll_fresp_bits_uop_fu_code; // @[execution-units.scala:108:30] wire [3:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_br_type; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op1_sel; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op2_sel; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_imm_sel; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_op_fcn; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_fcn_dw; // @[execution-units.scala:108:30] wire [2:0] _memExeUnit_io_ll_fresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_load; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_sta; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ctrl_is_std; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_iw_state; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_iw_p1_poisoned; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_iw_p2_poisoned; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_br; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_jalr; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_jal; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_sfb; // @[execution-units.scala:108:30] wire [15:0] _memExeUnit_io_ll_fresp_bits_uop_br_mask; // @[execution-units.scala:108:30] wire [3:0] _memExeUnit_io_ll_fresp_bits_uop_br_tag; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ftq_idx; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_edge_inst; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_pc_lob; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_taken; // @[execution-units.scala:108:30] wire [19:0] _memExeUnit_io_ll_fresp_bits_uop_imm_packed; // @[execution-units.scala:108:30] wire [11:0] _memExeUnit_io_ll_fresp_bits_uop_csr_addr; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_rob_idx; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ldq_idx; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_stq_idx; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_rxq_idx; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_pdst; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_prs1; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_prs2; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_prs3; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_ppred; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_prs1_busy; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_prs2_busy; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_prs3_busy; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ppred_busy; // @[execution-units.scala:108:30] wire [6:0] _memExeUnit_io_ll_fresp_bits_uop_stale_pdst; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_exception; // @[execution-units.scala:108:30] wire [63:0] _memExeUnit_io_ll_fresp_bits_uop_exc_cause; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_bypassable; // @[execution-units.scala:108:30] wire [4:0] _memExeUnit_io_ll_fresp_bits_uop_mem_cmd; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_mem_size; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_mem_signed; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_fence; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_fencei; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_amo; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_uses_ldq; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_uses_stq; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_sys_pc2epc; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_is_unique; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_flush_on_commit; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ldst_is_rs1; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_ldst; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs1; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs2; // @[execution-units.scala:108:30] wire [5:0] _memExeUnit_io_ll_fresp_bits_uop_lrs3; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_ldst_val; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_dst_rtype; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_lrs1_rtype; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_lrs2_rtype; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_frs3_en; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_fp_val; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_fp_single; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_pf_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_ae_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_xcpt_ma_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_bp_debug_if; // @[execution-units.scala:108:30] wire _memExeUnit_io_ll_fresp_bits_uop_bp_xcpt_if; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_debug_fsrc; // @[execution-units.scala:108:30] wire [1:0] _memExeUnit_io_ll_fresp_bits_uop_debug_tsrc; // @[execution-units.scala:108:30] wire [64:0] _memExeUnit_io_ll_fresp_bits_data; // @[execution-units.scala:108:30] wire [1:0] io_hartid_0 = io_hartid; // @[core.scala:51:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[core.scala:51:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[core.scala:51:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[core.scala:51:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[core.scala:51:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[core.scala:51:7] wire io_ifu_fetchpacket_valid_0 = io_ifu_fetchpacket_valid; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_valid_0 = io_ifu_fetchpacket_bits_uops_0_valid; // @[core.scala:51:7] wire [31:0] io_ifu_fetchpacket_bits_uops_0_bits_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_inst; // @[core.scala:51:7] wire [31:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_inst; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_0_bits_is_rvc; // @[core.scala:51:7] wire [39:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_pc; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_0_bits_is_sfb; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_edge_inst; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_0_bits_pc_lob; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_taken_0 = io_ifu_fetchpacket_bits_uops_0_bits_taken; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_valid_0 = io_ifu_fetchpacket_bits_uops_1_valid; // @[core.scala:51:7] wire [31:0] io_ifu_fetchpacket_bits_uops_1_bits_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_inst; // @[core.scala:51:7] wire [31:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_inst; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_1_bits_is_rvc; // @[core.scala:51:7] wire [39:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_pc; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_1_bits_is_sfb; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_edge_inst; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_1_bits_pc_lob; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_taken_0 = io_ifu_fetchpacket_bits_uops_1_bits_taken; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_valid_0 = io_ifu_fetchpacket_bits_uops_2_valid; // @[core.scala:51:7] wire [31:0] io_ifu_fetchpacket_bits_uops_2_bits_inst_0 = io_ifu_fetchpacket_bits_uops_2_bits_inst; // @[core.scala:51:7] wire [31:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_2_bits_debug_inst; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_2_bits_is_rvc; // @[core.scala:51:7] wire [39:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_2_bits_debug_pc; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_2_bits_is_sfb; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_2_bits_edge_inst; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_2_bits_pc_lob; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_taken_0 = io_ifu_fetchpacket_bits_uops_2_bits_taken; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_cfi_idx_valid_0 = io_ifu_get_pc_0_entry_cfi_idx_valid; // @[core.scala:51:7] wire [2:0] io_ifu_get_pc_0_entry_cfi_idx_bits_0 = io_ifu_get_pc_0_entry_cfi_idx_bits; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_cfi_taken_0 = io_ifu_get_pc_0_entry_cfi_taken; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_cfi_mispredicted_0 = io_ifu_get_pc_0_entry_cfi_mispredicted; // @[core.scala:51:7] wire [2:0] io_ifu_get_pc_0_entry_cfi_type_0 = io_ifu_get_pc_0_entry_cfi_type; // @[core.scala:51:7] wire [7:0] io_ifu_get_pc_0_entry_br_mask_0 = io_ifu_get_pc_0_entry_br_mask; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_cfi_is_call_0 = io_ifu_get_pc_0_entry_cfi_is_call; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_cfi_is_ret_0 = io_ifu_get_pc_0_entry_cfi_is_ret; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_cfi_npc_plus4_0 = io_ifu_get_pc_0_entry_cfi_npc_plus4; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_0_entry_ras_top_0 = io_ifu_get_pc_0_entry_ras_top; // @[core.scala:51:7] wire [4:0] io_ifu_get_pc_0_entry_ras_idx_0 = io_ifu_get_pc_0_entry_ras_idx; // @[core.scala:51:7] wire io_ifu_get_pc_0_entry_start_bank_0 = io_ifu_get_pc_0_entry_start_bank; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_0_pc_0 = io_ifu_get_pc_0_pc; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_0_com_pc_0 = io_ifu_get_pc_0_com_pc; // @[core.scala:51:7] wire io_ifu_get_pc_0_next_val_0 = io_ifu_get_pc_0_next_val; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_0_next_pc_0 = io_ifu_get_pc_0_next_pc; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_cfi_idx_valid_0 = io_ifu_get_pc_1_entry_cfi_idx_valid; // @[core.scala:51:7] wire [2:0] io_ifu_get_pc_1_entry_cfi_idx_bits_0 = io_ifu_get_pc_1_entry_cfi_idx_bits; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_cfi_taken_0 = io_ifu_get_pc_1_entry_cfi_taken; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_cfi_mispredicted_0 = io_ifu_get_pc_1_entry_cfi_mispredicted; // @[core.scala:51:7] wire [2:0] io_ifu_get_pc_1_entry_cfi_type_0 = io_ifu_get_pc_1_entry_cfi_type; // @[core.scala:51:7] wire [7:0] io_ifu_get_pc_1_entry_br_mask_0 = io_ifu_get_pc_1_entry_br_mask; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_cfi_is_call_0 = io_ifu_get_pc_1_entry_cfi_is_call; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_cfi_is_ret_0 = io_ifu_get_pc_1_entry_cfi_is_ret; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_cfi_npc_plus4_0 = io_ifu_get_pc_1_entry_cfi_npc_plus4; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_1_entry_ras_top_0 = io_ifu_get_pc_1_entry_ras_top; // @[core.scala:51:7] wire [4:0] io_ifu_get_pc_1_entry_ras_idx_0 = io_ifu_get_pc_1_entry_ras_idx; // @[core.scala:51:7] wire io_ifu_get_pc_1_entry_start_bank_0 = io_ifu_get_pc_1_entry_start_bank; // @[core.scala:51:7] wire [63:0] io_ifu_get_pc_1_ghist_old_history_0 = io_ifu_get_pc_1_ghist_old_history; // @[core.scala:51:7] wire io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0 = io_ifu_get_pc_1_ghist_current_saw_branch_not_taken; // @[core.scala:51:7] wire io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken; // @[core.scala:51:7] wire io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 = io_ifu_get_pc_1_ghist_new_saw_branch_taken; // @[core.scala:51:7] wire [4:0] io_ifu_get_pc_1_ghist_ras_idx_0 = io_ifu_get_pc_1_ghist_ras_idx; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_1_pc_0 = io_ifu_get_pc_1_pc; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_1_com_pc_0 = io_ifu_get_pc_1_com_pc; // @[core.scala:51:7] wire io_ifu_get_pc_1_next_val_0 = io_ifu_get_pc_1_next_val; // @[core.scala:51:7] wire [39:0] io_ifu_get_pc_1_next_pc_0 = io_ifu_get_pc_1_next_pc; // @[core.scala:51:7] wire [39:0] io_ifu_debug_fetch_pc_0_0 = io_ifu_debug_fetch_pc_0; // @[core.scala:51:7] wire [39:0] io_ifu_debug_fetch_pc_1_0 = io_ifu_debug_fetch_pc_1; // @[core.scala:51:7] wire [39:0] io_ifu_debug_fetch_pc_2_0 = io_ifu_debug_fetch_pc_2; // @[core.scala:51:7] wire io_ifu_perf_acquire_0 = io_ifu_perf_acquire; // @[core.scala:51:7] wire io_ifu_perf_tlbMiss_0 = io_ifu_perf_tlbMiss; // @[core.scala:51:7] wire io_ptw_perf_l2miss_0 = io_ptw_perf_l2miss; // @[core.scala:51:7] wire io_ptw_perf_l2hit_0 = io_ptw_perf_l2hit; // @[core.scala:51:7] wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[core.scala:51:7] wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[core.scala:51:7] wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_valid_0 = io_lsu_exe_0_iresp_valid; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_uopc_0 = io_lsu_exe_0_iresp_bits_uop_uopc; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_iresp_bits_uop_inst_0 = io_lsu_exe_0_iresp_bits_uop_inst; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_iresp_bits_uop_debug_inst_0 = io_lsu_exe_0_iresp_bits_uop_debug_inst; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_rvc_0 = io_lsu_exe_0_iresp_bits_uop_is_rvc; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_iresp_bits_uop_debug_pc_0 = io_lsu_exe_0_iresp_bits_uop_debug_pc; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_iq_type_0 = io_lsu_exe_0_iresp_bits_uop_iq_type; // @[core.scala:51:7] wire [9:0] io_lsu_exe_0_iresp_bits_uop_fu_code_0 = io_lsu_exe_0_iresp_bits_uop_fu_code; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_br_type; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_load; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_iresp_bits_uop_ctrl_is_std; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_iw_state_0 = io_lsu_exe_0_iresp_bits_uop_iw_state; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_br_0 = io_lsu_exe_0_iresp_bits_uop_is_br; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_jalr_0 = io_lsu_exe_0_iresp_bits_uop_is_jalr; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_jal_0 = io_lsu_exe_0_iresp_bits_uop_is_jal; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_sfb_0 = io_lsu_exe_0_iresp_bits_uop_is_sfb; // @[core.scala:51:7] wire [15:0] io_lsu_exe_0_iresp_bits_uop_br_mask_0 = io_lsu_exe_0_iresp_bits_uop_br_mask; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_iresp_bits_uop_br_tag_0 = io_lsu_exe_0_iresp_bits_uop_br_tag; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ftq_idx; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_edge_inst_0 = io_lsu_exe_0_iresp_bits_uop_edge_inst; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_pc_lob_0 = io_lsu_exe_0_iresp_bits_uop_pc_lob; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_taken_0 = io_lsu_exe_0_iresp_bits_uop_taken; // @[core.scala:51:7] wire [19:0] io_lsu_exe_0_iresp_bits_uop_imm_packed_0 = io_lsu_exe_0_iresp_bits_uop_imm_packed; // @[core.scala:51:7] wire [11:0] io_lsu_exe_0_iresp_bits_uop_csr_addr_0 = io_lsu_exe_0_iresp_bits_uop_csr_addr; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_rob_idx_0 = io_lsu_exe_0_iresp_bits_uop_rob_idx; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_iresp_bits_uop_ldq_idx; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_stq_idx_0 = io_lsu_exe_0_iresp_bits_uop_stq_idx; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_iresp_bits_uop_rxq_idx; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_pdst_0 = io_lsu_exe_0_iresp_bits_uop_pdst; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs1_0 = io_lsu_exe_0_iresp_bits_uop_prs1; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs2_0 = io_lsu_exe_0_iresp_bits_uop_prs2; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_prs3_0 = io_lsu_exe_0_iresp_bits_uop_prs3; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_ppred_0 = io_lsu_exe_0_iresp_bits_uop_ppred; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs1_busy; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs2_busy; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_iresp_bits_uop_prs3_busy; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_iresp_bits_uop_ppred_busy; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_iresp_bits_uop_stale_pdst; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_exception_0 = io_lsu_exe_0_iresp_bits_uop_exception; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_iresp_bits_uop_exc_cause_0 = io_lsu_exe_0_iresp_bits_uop_exc_cause; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_bypassable_0 = io_lsu_exe_0_iresp_bits_uop_bypassable; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_iresp_bits_uop_mem_cmd; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_mem_size_0 = io_lsu_exe_0_iresp_bits_uop_mem_size; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_mem_signed_0 = io_lsu_exe_0_iresp_bits_uop_mem_signed; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_fence_0 = io_lsu_exe_0_iresp_bits_uop_is_fence; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_fencei_0 = io_lsu_exe_0_iresp_bits_uop_is_fencei; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_amo_0 = io_lsu_exe_0_iresp_bits_uop_is_amo; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_iresp_bits_uop_uses_ldq; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_uses_stq_0 = io_lsu_exe_0_iresp_bits_uop_uses_stq; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_is_unique_0 = io_lsu_exe_0_iresp_bits_uop_is_unique; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_iresp_bits_uop_flush_on_commit; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_ldst_0 = io_lsu_exe_0_iresp_bits_uop_ldst; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs1_0 = io_lsu_exe_0_iresp_bits_uop_lrs1; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs2_0 = io_lsu_exe_0_iresp_bits_uop_lrs2; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_uop_lrs3_0 = io_lsu_exe_0_iresp_bits_uop_lrs3; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_ldst_val_0 = io_lsu_exe_0_iresp_bits_uop_ldst_val; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_iresp_bits_uop_dst_rtype; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs1_rtype; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_iresp_bits_uop_lrs2_rtype; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_frs3_en_0 = io_lsu_exe_0_iresp_bits_uop_frs3_en; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_fp_val_0 = io_lsu_exe_0_iresp_bits_uop_fp_val; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_fp_single_0 = io_lsu_exe_0_iresp_bits_uop_fp_single; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_debug_if; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_fsrc; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_iresp_bits_uop_debug_tsrc; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_iresp_bits_data_0 = io_lsu_exe_0_iresp_bits_data; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_valid_0 = io_lsu_exe_0_fresp_valid; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_uopc_0 = io_lsu_exe_0_fresp_bits_uop_uopc; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_fresp_bits_uop_inst_0 = io_lsu_exe_0_fresp_bits_uop_inst; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_fresp_bits_uop_debug_inst_0 = io_lsu_exe_0_fresp_bits_uop_debug_inst; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_rvc_0 = io_lsu_exe_0_fresp_bits_uop_is_rvc; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_fresp_bits_uop_debug_pc_0 = io_lsu_exe_0_fresp_bits_uop_debug_pc; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_iq_type_0 = io_lsu_exe_0_fresp_bits_uop_iq_type; // @[core.scala:51:7] wire [9:0] io_lsu_exe_0_fresp_bits_uop_fu_code_0 = io_lsu_exe_0_fresp_bits_uop_fu_code; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_ctrl_br_type_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_br_type; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_load_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_load; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ctrl_is_std_0 = io_lsu_exe_0_fresp_bits_uop_ctrl_is_std; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_iw_state_0 = io_lsu_exe_0_fresp_bits_uop_iw_state; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned_0 = io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_br_0 = io_lsu_exe_0_fresp_bits_uop_is_br; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_jalr_0 = io_lsu_exe_0_fresp_bits_uop_is_jalr; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_jal_0 = io_lsu_exe_0_fresp_bits_uop_is_jal; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_sfb_0 = io_lsu_exe_0_fresp_bits_uop_is_sfb; // @[core.scala:51:7] wire [15:0] io_lsu_exe_0_fresp_bits_uop_br_mask_0 = io_lsu_exe_0_fresp_bits_uop_br_mask; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_fresp_bits_uop_br_tag_0 = io_lsu_exe_0_fresp_bits_uop_br_tag; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_ftq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ftq_idx; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_edge_inst_0 = io_lsu_exe_0_fresp_bits_uop_edge_inst; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_pc_lob_0 = io_lsu_exe_0_fresp_bits_uop_pc_lob; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_taken_0 = io_lsu_exe_0_fresp_bits_uop_taken; // @[core.scala:51:7] wire [19:0] io_lsu_exe_0_fresp_bits_uop_imm_packed_0 = io_lsu_exe_0_fresp_bits_uop_imm_packed; // @[core.scala:51:7] wire [11:0] io_lsu_exe_0_fresp_bits_uop_csr_addr_0 = io_lsu_exe_0_fresp_bits_uop_csr_addr; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_rob_idx_0 = io_lsu_exe_0_fresp_bits_uop_rob_idx; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_ldq_idx_0 = io_lsu_exe_0_fresp_bits_uop_ldq_idx; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_stq_idx_0 = io_lsu_exe_0_fresp_bits_uop_stq_idx; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_rxq_idx_0 = io_lsu_exe_0_fresp_bits_uop_rxq_idx; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_pdst_0 = io_lsu_exe_0_fresp_bits_uop_pdst; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs1_0 = io_lsu_exe_0_fresp_bits_uop_prs1; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs2_0 = io_lsu_exe_0_fresp_bits_uop_prs2; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_prs3_0 = io_lsu_exe_0_fresp_bits_uop_prs3; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_ppred_0 = io_lsu_exe_0_fresp_bits_uop_ppred; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_prs1_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs1_busy; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_prs2_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs2_busy; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_prs3_busy_0 = io_lsu_exe_0_fresp_bits_uop_prs3_busy; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ppred_busy_0 = io_lsu_exe_0_fresp_bits_uop_ppred_busy; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_uop_stale_pdst_0 = io_lsu_exe_0_fresp_bits_uop_stale_pdst; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_exception_0 = io_lsu_exe_0_fresp_bits_uop_exception; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_fresp_bits_uop_exc_cause_0 = io_lsu_exe_0_fresp_bits_uop_exc_cause; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_bypassable_0 = io_lsu_exe_0_fresp_bits_uop_bypassable; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_uop_mem_cmd_0 = io_lsu_exe_0_fresp_bits_uop_mem_cmd; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_mem_size_0 = io_lsu_exe_0_fresp_bits_uop_mem_size; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_mem_signed_0 = io_lsu_exe_0_fresp_bits_uop_mem_signed; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_fence_0 = io_lsu_exe_0_fresp_bits_uop_is_fence; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_fencei_0 = io_lsu_exe_0_fresp_bits_uop_is_fencei; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_amo_0 = io_lsu_exe_0_fresp_bits_uop_is_amo; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_uses_ldq_0 = io_lsu_exe_0_fresp_bits_uop_uses_ldq; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_uses_stq_0 = io_lsu_exe_0_fresp_bits_uop_uses_stq; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc_0 = io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_is_unique_0 = io_lsu_exe_0_fresp_bits_uop_is_unique; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_flush_on_commit_0 = io_lsu_exe_0_fresp_bits_uop_flush_on_commit; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1_0 = io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_ldst_0 = io_lsu_exe_0_fresp_bits_uop_ldst; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs1_0 = io_lsu_exe_0_fresp_bits_uop_lrs1; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs2_0 = io_lsu_exe_0_fresp_bits_uop_lrs2; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_uop_lrs3_0 = io_lsu_exe_0_fresp_bits_uop_lrs3; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_ldst_val_0 = io_lsu_exe_0_fresp_bits_uop_ldst_val; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_dst_rtype_0 = io_lsu_exe_0_fresp_bits_uop_dst_rtype; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs1_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs1_rtype; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_lrs2_rtype_0 = io_lsu_exe_0_fresp_bits_uop_lrs2_rtype; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_frs3_en_0 = io_lsu_exe_0_fresp_bits_uop_frs3_en; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_fp_val_0 = io_lsu_exe_0_fresp_bits_uop_fp_val; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_fp_single_0 = io_lsu_exe_0_fresp_bits_uop_fp_single; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if_0 = io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_bp_debug_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_debug_if; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if_0 = io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_fsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_fsrc; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_uop_debug_tsrc_0 = io_lsu_exe_0_fresp_bits_uop_debug_tsrc; // @[core.scala:51:7] wire [64:0] io_lsu_exe_0_fresp_bits_data_0 = io_lsu_exe_0_fresp_bits_data; // @[core.scala:51:7] wire [4:0] io_lsu_dis_ldq_idx_0_0 = io_lsu_dis_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_ldq_idx_1_0 = io_lsu_dis_ldq_idx_1; // @[core.scala:51:7] wire [4:0] io_lsu_dis_ldq_idx_2_0 = io_lsu_dis_ldq_idx_2; // @[core.scala:51:7] wire [4:0] io_lsu_dis_stq_idx_0_0 = io_lsu_dis_stq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_stq_idx_1_0 = io_lsu_dis_stq_idx_1; // @[core.scala:51:7] wire [4:0] io_lsu_dis_stq_idx_2_0 = io_lsu_dis_stq_idx_2; // @[core.scala:51:7] wire io_lsu_ldq_full_0_0 = io_lsu_ldq_full_0; // @[core.scala:51:7] wire io_lsu_ldq_full_1_0 = io_lsu_ldq_full_1; // @[core.scala:51:7] wire io_lsu_ldq_full_2_0 = io_lsu_ldq_full_2; // @[core.scala:51:7] wire io_lsu_stq_full_0_0 = io_lsu_stq_full_0; // @[core.scala:51:7] wire io_lsu_stq_full_1_0 = io_lsu_stq_full_1; // @[core.scala:51:7] wire io_lsu_stq_full_2_0 = io_lsu_stq_full_2; // @[core.scala:51:7] wire io_lsu_fp_stdata_ready_0 = io_lsu_fp_stdata_ready; // @[core.scala:51:7] wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[core.scala:51:7] wire [6:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[core.scala:51:7] wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid; // @[core.scala:51:7] wire [6:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits; // @[core.scala:51:7] wire [6:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[core.scala:51:7] wire io_lsu_spec_ld_wakeup_0_valid_0 = io_lsu_spec_ld_wakeup_0_valid; // @[core.scala:51:7] wire [6:0] io_lsu_spec_ld_wakeup_0_bits_0 = io_lsu_spec_ld_wakeup_0_bits; // @[core.scala:51:7] wire io_lsu_ld_miss_0 = io_lsu_ld_miss; // @[core.scala:51:7] wire io_lsu_fencei_rdy_0 = io_lsu_fencei_rdy; // @[core.scala:51:7] wire io_lsu_lxcpt_valid_0 = io_lsu_lxcpt_valid; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_uopc_0 = io_lsu_lxcpt_bits_uop_uopc; // @[core.scala:51:7] wire [31:0] io_lsu_lxcpt_bits_uop_inst_0 = io_lsu_lxcpt_bits_uop_inst; // @[core.scala:51:7] wire [31:0] io_lsu_lxcpt_bits_uop_debug_inst_0 = io_lsu_lxcpt_bits_uop_debug_inst; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_rvc_0 = io_lsu_lxcpt_bits_uop_is_rvc; // @[core.scala:51:7] wire [39:0] io_lsu_lxcpt_bits_uop_debug_pc_0 = io_lsu_lxcpt_bits_uop_debug_pc; // @[core.scala:51:7] wire [2:0] io_lsu_lxcpt_bits_uop_iq_type_0 = io_lsu_lxcpt_bits_uop_iq_type; // @[core.scala:51:7] wire [9:0] io_lsu_lxcpt_bits_uop_fu_code_0 = io_lsu_lxcpt_bits_uop_fu_code; // @[core.scala:51:7] wire [3:0] io_lsu_lxcpt_bits_uop_ctrl_br_type_0 = io_lsu_lxcpt_bits_uop_ctrl_br_type; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_ctrl_op1_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op1_sel; // @[core.scala:51:7] wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_op2_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_op2_sel; // @[core.scala:51:7] wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_imm_sel_0 = io_lsu_lxcpt_bits_uop_ctrl_imm_sel; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_uop_ctrl_op_fcn_0 = io_lsu_lxcpt_bits_uop_ctrl_op_fcn; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ctrl_fcn_dw_0 = io_lsu_lxcpt_bits_uop_ctrl_fcn_dw; // @[core.scala:51:7] wire [2:0] io_lsu_lxcpt_bits_uop_ctrl_csr_cmd_0 = io_lsu_lxcpt_bits_uop_ctrl_csr_cmd; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ctrl_is_load_0 = io_lsu_lxcpt_bits_uop_ctrl_is_load; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ctrl_is_sta_0 = io_lsu_lxcpt_bits_uop_ctrl_is_sta; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ctrl_is_std_0 = io_lsu_lxcpt_bits_uop_ctrl_is_std; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_iw_state_0 = io_lsu_lxcpt_bits_uop_iw_state; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_iw_p1_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p1_poisoned; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_iw_p2_poisoned_0 = io_lsu_lxcpt_bits_uop_iw_p2_poisoned; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_br_0 = io_lsu_lxcpt_bits_uop_is_br; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_jalr_0 = io_lsu_lxcpt_bits_uop_is_jalr; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_jal_0 = io_lsu_lxcpt_bits_uop_is_jal; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_sfb_0 = io_lsu_lxcpt_bits_uop_is_sfb; // @[core.scala:51:7] wire [15:0] io_lsu_lxcpt_bits_uop_br_mask_0 = io_lsu_lxcpt_bits_uop_br_mask; // @[core.scala:51:7] wire [3:0] io_lsu_lxcpt_bits_uop_br_tag_0 = io_lsu_lxcpt_bits_uop_br_tag; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_uop_ftq_idx_0 = io_lsu_lxcpt_bits_uop_ftq_idx; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_edge_inst_0 = io_lsu_lxcpt_bits_uop_edge_inst; // @[core.scala:51:7] wire [5:0] io_lsu_lxcpt_bits_uop_pc_lob_0 = io_lsu_lxcpt_bits_uop_pc_lob; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_taken_0 = io_lsu_lxcpt_bits_uop_taken; // @[core.scala:51:7] wire [19:0] io_lsu_lxcpt_bits_uop_imm_packed_0 = io_lsu_lxcpt_bits_uop_imm_packed; // @[core.scala:51:7] wire [11:0] io_lsu_lxcpt_bits_uop_csr_addr_0 = io_lsu_lxcpt_bits_uop_csr_addr; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_rob_idx_0 = io_lsu_lxcpt_bits_uop_rob_idx; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_uop_ldq_idx_0 = io_lsu_lxcpt_bits_uop_ldq_idx; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_uop_stq_idx_0 = io_lsu_lxcpt_bits_uop_stq_idx; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_rxq_idx_0 = io_lsu_lxcpt_bits_uop_rxq_idx; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_pdst_0 = io_lsu_lxcpt_bits_uop_pdst; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs1_0 = io_lsu_lxcpt_bits_uop_prs1; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs2_0 = io_lsu_lxcpt_bits_uop_prs2; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs3_0 = io_lsu_lxcpt_bits_uop_prs3; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_uop_ppred_0 = io_lsu_lxcpt_bits_uop_ppred; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_prs1_busy_0 = io_lsu_lxcpt_bits_uop_prs1_busy; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_prs2_busy_0 = io_lsu_lxcpt_bits_uop_prs2_busy; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_prs3_busy_0 = io_lsu_lxcpt_bits_uop_prs3_busy; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ppred_busy_0 = io_lsu_lxcpt_bits_uop_ppred_busy; // @[core.scala:51:7] wire [6:0] io_lsu_lxcpt_bits_uop_stale_pdst_0 = io_lsu_lxcpt_bits_uop_stale_pdst; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_exception_0 = io_lsu_lxcpt_bits_uop_exception; // @[core.scala:51:7] wire [63:0] io_lsu_lxcpt_bits_uop_exc_cause_0 = io_lsu_lxcpt_bits_uop_exc_cause; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_bypassable_0 = io_lsu_lxcpt_bits_uop_bypassable; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_uop_mem_cmd_0 = io_lsu_lxcpt_bits_uop_mem_cmd; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_mem_size_0 = io_lsu_lxcpt_bits_uop_mem_size; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_mem_signed_0 = io_lsu_lxcpt_bits_uop_mem_signed; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_fence_0 = io_lsu_lxcpt_bits_uop_is_fence; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_fencei_0 = io_lsu_lxcpt_bits_uop_is_fencei; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_amo_0 = io_lsu_lxcpt_bits_uop_is_amo; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_uses_ldq_0 = io_lsu_lxcpt_bits_uop_uses_ldq; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_uses_stq_0 = io_lsu_lxcpt_bits_uop_uses_stq; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lsu_lxcpt_bits_uop_is_sys_pc2epc; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_is_unique_0 = io_lsu_lxcpt_bits_uop_is_unique; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_flush_on_commit_0 = io_lsu_lxcpt_bits_uop_flush_on_commit; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ldst_is_rs1_0 = io_lsu_lxcpt_bits_uop_ldst_is_rs1; // @[core.scala:51:7] wire [5:0] io_lsu_lxcpt_bits_uop_ldst_0 = io_lsu_lxcpt_bits_uop_ldst; // @[core.scala:51:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs1_0 = io_lsu_lxcpt_bits_uop_lrs1; // @[core.scala:51:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs2_0 = io_lsu_lxcpt_bits_uop_lrs2; // @[core.scala:51:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs3_0 = io_lsu_lxcpt_bits_uop_lrs3; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_ldst_val_0 = io_lsu_lxcpt_bits_uop_ldst_val; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_dst_rtype_0 = io_lsu_lxcpt_bits_uop_dst_rtype; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype_0 = io_lsu_lxcpt_bits_uop_lrs1_rtype; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype_0 = io_lsu_lxcpt_bits_uop_lrs2_rtype; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_frs3_en_0 = io_lsu_lxcpt_bits_uop_frs3_en; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_fp_val_0 = io_lsu_lxcpt_bits_uop_fp_val; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_fp_single_0 = io_lsu_lxcpt_bits_uop_fp_single; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_xcpt_pf_if_0 = io_lsu_lxcpt_bits_uop_xcpt_pf_if; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_xcpt_ae_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ae_if; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_xcpt_ma_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ma_if; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_bp_debug_if_0 = io_lsu_lxcpt_bits_uop_bp_debug_if; // @[core.scala:51:7] wire io_lsu_lxcpt_bits_uop_bp_xcpt_if_0 = io_lsu_lxcpt_bits_uop_bp_xcpt_if; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_debug_fsrc_0 = io_lsu_lxcpt_bits_uop_debug_fsrc; // @[core.scala:51:7] wire [1:0] io_lsu_lxcpt_bits_uop_debug_tsrc_0 = io_lsu_lxcpt_bits_uop_debug_tsrc; // @[core.scala:51:7] wire [4:0] io_lsu_lxcpt_bits_cause_0 = io_lsu_lxcpt_bits_cause; // @[core.scala:51:7] wire [39:0] io_lsu_lxcpt_bits_badvaddr_0 = io_lsu_lxcpt_bits_badvaddr; // @[core.scala:51:7] wire io_lsu_perf_acquire_0 = io_lsu_perf_acquire; // @[core.scala:51:7] wire io_lsu_perf_release_0 = io_lsu_perf_release; // @[core.scala:51:7] wire io_lsu_perf_tlbMiss_0 = io_lsu_perf_tlbMiss; // @[core.scala:51:7] wire io_ptw_tlb_req_ready_0 = io_ptw_tlb_req_ready; // @[core.scala:51:7] wire io_ptw_tlb_resp_valid_0 = io_ptw_tlb_resp_valid; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_ae_ptw_0 = io_ptw_tlb_resp_bits_ae_ptw; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_ae_final_0 = io_ptw_tlb_resp_bits_ae_final; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pf_0 = io_ptw_tlb_resp_bits_pf; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_gf_0 = io_ptw_tlb_resp_bits_gf; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_hr_0 = io_ptw_tlb_resp_bits_hr; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_hw_0 = io_ptw_tlb_resp_bits_hw; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_hx_0 = io_ptw_tlb_resp_bits_hx; // @[core.scala:51:7] wire [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future_0 = io_ptw_tlb_resp_bits_pte_reserved_for_future; // @[core.scala:51:7] wire [43:0] io_ptw_tlb_resp_bits_pte_ppn_0 = io_ptw_tlb_resp_bits_pte_ppn; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software_0 = io_ptw_tlb_resp_bits_pte_reserved_for_software; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_d_0 = io_ptw_tlb_resp_bits_pte_d; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_a_0 = io_ptw_tlb_resp_bits_pte_a; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_g_0 = io_ptw_tlb_resp_bits_pte_g; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_u_0 = io_ptw_tlb_resp_bits_pte_u; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_x_0 = io_ptw_tlb_resp_bits_pte_x; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_w_0 = io_ptw_tlb_resp_bits_pte_w; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_r_0 = io_ptw_tlb_resp_bits_pte_r; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_pte_v_0 = io_ptw_tlb_resp_bits_pte_v; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_resp_bits_level_0 = io_ptw_tlb_resp_bits_level; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_homogeneous_0 = io_ptw_tlb_resp_bits_homogeneous; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_gpa_valid_0 = io_ptw_tlb_resp_bits_gpa_valid; // @[core.scala:51:7] wire [38:0] io_ptw_tlb_resp_bits_gpa_bits_0 = io_ptw_tlb_resp_bits_gpa_bits; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_gpa_is_pte_0 = io_ptw_tlb_resp_bits_gpa_is_pte; // @[core.scala:51:7] wire [3:0] io_ptw_tlb_ptbr_mode_0 = io_ptw_tlb_ptbr_mode; // @[core.scala:51:7] wire [43:0] io_ptw_tlb_ptbr_ppn_0 = io_ptw_tlb_ptbr_ppn; // @[core.scala:51:7] wire io_ptw_tlb_status_debug_0 = io_ptw_tlb_status_debug; // @[core.scala:51:7] wire io_ptw_tlb_status_cease_0 = io_ptw_tlb_status_cease; // @[core.scala:51:7] wire io_ptw_tlb_status_wfi_0 = io_ptw_tlb_status_wfi; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_dprv_0 = io_ptw_tlb_status_dprv; // @[core.scala:51:7] wire io_ptw_tlb_status_dv_0 = io_ptw_tlb_status_dv; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_prv_0 = io_ptw_tlb_status_prv; // @[core.scala:51:7] wire io_ptw_tlb_status_v_0 = io_ptw_tlb_status_v; // @[core.scala:51:7] wire io_ptw_tlb_status_sd_0 = io_ptw_tlb_status_sd; // @[core.scala:51:7] wire io_ptw_tlb_status_mpv_0 = io_ptw_tlb_status_mpv; // @[core.scala:51:7] wire io_ptw_tlb_status_gva_0 = io_ptw_tlb_status_gva; // @[core.scala:51:7] wire io_ptw_tlb_status_tsr_0 = io_ptw_tlb_status_tsr; // @[core.scala:51:7] wire io_ptw_tlb_status_tw_0 = io_ptw_tlb_status_tw; // @[core.scala:51:7] wire io_ptw_tlb_status_tvm_0 = io_ptw_tlb_status_tvm; // @[core.scala:51:7] wire io_ptw_tlb_status_mxr_0 = io_ptw_tlb_status_mxr; // @[core.scala:51:7] wire io_ptw_tlb_status_sum_0 = io_ptw_tlb_status_sum; // @[core.scala:51:7] wire io_ptw_tlb_status_mprv_0 = io_ptw_tlb_status_mprv; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_fs_0 = io_ptw_tlb_status_fs; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_mpp_0 = io_ptw_tlb_status_mpp; // @[core.scala:51:7] wire io_ptw_tlb_status_spp_0 = io_ptw_tlb_status_spp; // @[core.scala:51:7] wire io_ptw_tlb_status_mpie_0 = io_ptw_tlb_status_mpie; // @[core.scala:51:7] wire io_ptw_tlb_status_spie_0 = io_ptw_tlb_status_spie; // @[core.scala:51:7] wire io_ptw_tlb_status_mie_0 = io_ptw_tlb_status_mie; // @[core.scala:51:7] wire io_ptw_tlb_status_sie_0 = io_ptw_tlb_status_sie; // @[core.scala:51:7] wire io_ptw_tlb_pmp_0_cfg_l_0 = io_ptw_tlb_pmp_0_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_0_cfg_a_0 = io_ptw_tlb_pmp_0_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_0_cfg_x_0 = io_ptw_tlb_pmp_0_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_0_cfg_w_0 = io_ptw_tlb_pmp_0_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_0_cfg_r_0 = io_ptw_tlb_pmp_0_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_0_addr_0 = io_ptw_tlb_pmp_0_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_0_mask_0 = io_ptw_tlb_pmp_0_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_1_cfg_l_0 = io_ptw_tlb_pmp_1_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_1_cfg_a_0 = io_ptw_tlb_pmp_1_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_1_cfg_x_0 = io_ptw_tlb_pmp_1_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_1_cfg_w_0 = io_ptw_tlb_pmp_1_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_1_cfg_r_0 = io_ptw_tlb_pmp_1_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_1_addr_0 = io_ptw_tlb_pmp_1_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_1_mask_0 = io_ptw_tlb_pmp_1_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_2_cfg_l_0 = io_ptw_tlb_pmp_2_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_2_cfg_a_0 = io_ptw_tlb_pmp_2_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_2_cfg_x_0 = io_ptw_tlb_pmp_2_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_2_cfg_w_0 = io_ptw_tlb_pmp_2_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_2_cfg_r_0 = io_ptw_tlb_pmp_2_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_2_addr_0 = io_ptw_tlb_pmp_2_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_2_mask_0 = io_ptw_tlb_pmp_2_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_3_cfg_l_0 = io_ptw_tlb_pmp_3_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_3_cfg_a_0 = io_ptw_tlb_pmp_3_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_3_cfg_x_0 = io_ptw_tlb_pmp_3_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_3_cfg_w_0 = io_ptw_tlb_pmp_3_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_3_cfg_r_0 = io_ptw_tlb_pmp_3_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_3_addr_0 = io_ptw_tlb_pmp_3_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_3_mask_0 = io_ptw_tlb_pmp_3_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_4_cfg_l_0 = io_ptw_tlb_pmp_4_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_4_cfg_a_0 = io_ptw_tlb_pmp_4_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_4_cfg_x_0 = io_ptw_tlb_pmp_4_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_4_cfg_w_0 = io_ptw_tlb_pmp_4_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_4_cfg_r_0 = io_ptw_tlb_pmp_4_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_4_addr_0 = io_ptw_tlb_pmp_4_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_4_mask_0 = io_ptw_tlb_pmp_4_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_5_cfg_l_0 = io_ptw_tlb_pmp_5_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_5_cfg_a_0 = io_ptw_tlb_pmp_5_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_5_cfg_x_0 = io_ptw_tlb_pmp_5_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_5_cfg_w_0 = io_ptw_tlb_pmp_5_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_5_cfg_r_0 = io_ptw_tlb_pmp_5_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_5_addr_0 = io_ptw_tlb_pmp_5_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_5_mask_0 = io_ptw_tlb_pmp_5_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_6_cfg_l_0 = io_ptw_tlb_pmp_6_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_6_cfg_a_0 = io_ptw_tlb_pmp_6_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_6_cfg_x_0 = io_ptw_tlb_pmp_6_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_6_cfg_w_0 = io_ptw_tlb_pmp_6_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_6_cfg_r_0 = io_ptw_tlb_pmp_6_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_6_addr_0 = io_ptw_tlb_pmp_6_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_6_mask_0 = io_ptw_tlb_pmp_6_mask; // @[core.scala:51:7] wire io_ptw_tlb_pmp_7_cfg_l_0 = io_ptw_tlb_pmp_7_cfg_l; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_7_cfg_a_0 = io_ptw_tlb_pmp_7_cfg_a; // @[core.scala:51:7] wire io_ptw_tlb_pmp_7_cfg_x_0 = io_ptw_tlb_pmp_7_cfg_x; // @[core.scala:51:7] wire io_ptw_tlb_pmp_7_cfg_w_0 = io_ptw_tlb_pmp_7_cfg_w; // @[core.scala:51:7] wire io_ptw_tlb_pmp_7_cfg_r_0 = io_ptw_tlb_pmp_7_cfg_r; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_pmp_7_addr_0 = io_ptw_tlb_pmp_7_addr; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_pmp_7_mask_0 = io_ptw_tlb_pmp_7_mask; // @[core.scala:51:7] wire coreMonitorBundle_clock = clock; // @[core.scala:1405:31] wire coreMonitorBundle_reset = reset; // @[core.scala:1405:31] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_uopc = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_rob_idx = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs1 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs2 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs3 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_stale_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_uopc = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_rob_idx = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs1 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs2 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs3 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_stale_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_uopc = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_rob_idx = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_prs1 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_prs2 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_prs3 = 7'h0; // @[core.scala:51:7] wire [6:0] io_ifu_fetchpacket_bits_uops_2_bits_stale_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_rocc_cmd_bits_inst_funct = 7'h0; // @[core.scala:51:7] wire [6:0] io_rocc_cmd_bits_inst_opcode = 7'h0; // @[core.scala:51:7] wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[core.scala:51:7] wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:51:7] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:147:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:148:30] wire [6:0] pred_wakeup_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:149:26] wire [6:0] dec_uops_0_rob_idx = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_0_pdst = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_0_prs1 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_0_prs2 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_0_prs3 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_0_stale_pdst = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_1_rob_idx = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_1_pdst = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_1_prs1 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_1_prs2 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_1_prs3 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_1_stale_pdst = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_2_rob_idx = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_2_pdst = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_2_prs1 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_2_prs2 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_2_prs3 = 7'h0; // @[core.scala:158:24] wire [6:0] dec_uops_2_stale_pdst = 7'h0; // @[core.scala:158:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:174:24] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:175:27] wire [6:0] p_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_1_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] p_uop_2_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] fast_wakeup_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:814:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:815:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:814:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:815:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:814:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_uopc = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_pdst = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[core.scala:815:29] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_iq_type = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op2_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_imm_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_iq_type = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_op2_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_imm_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_iq_type = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_op2_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_imm_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:51:7] wire [2:0] io_trace_insns_0_priv = 3'h0; // @[core.scala:51:7] wire [2:0] io_trace_insns_1_priv = 3'h0; // @[core.scala:51:7] wire [2:0] io_trace_insns_2_priv = 3'h0; // @[core.scala:51:7] wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:147:30] wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:148:30] wire [2:0] pred_wakeup_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:149:26] wire [2:0] dec_uops_0_ctrl_op2_sel = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_0_ctrl_imm_sel = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_0_ctrl_csr_cmd = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_1_ctrl_op2_sel = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_1_ctrl_imm_sel = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_1_ctrl_csr_cmd = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_2_ctrl_op2_sel = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_2_ctrl_imm_sel = 3'h0; // @[core.scala:158:24] wire [2:0] dec_uops_2_ctrl_csr_cmd = 3'h0; // @[core.scala:158:24] wire [2:0] bypasses_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:174:24] wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:175:27] wire [2:0] p_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_1_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_1_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_1_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_1_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_cs_1_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_cs_1_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_cs_1_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_2_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_2_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_2_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_2_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] p_uop_cs_2_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_cs_2_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] p_uop_cs_2_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [2:0] fast_wakeup_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:814:29] wire [2:0] slow_wakeup_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:815:29] wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:814:29] wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:815:29] wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:814:29] wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[core.scala:815:29] wire [2:0] coreMonitorBundle_priv_mode = 3'h0; // @[core.scala:1405:31] wire [9:0] io_ifu_fetchpacket_bits_uops_0_bits_fu_code = 10'h0; // @[core.scala:51:7] wire [9:0] io_ifu_fetchpacket_bits_uops_1_bits_fu_code = 10'h0; // @[core.scala:51:7] wire [9:0] io_ifu_fetchpacket_bits_uops_2_bits_fu_code = 10'h0; // @[core.scala:51:7] wire [9:0] io_lsu_exe_0_req_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:51:7] wire [9:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:51:7] wire [9:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:51:7] wire [9:0] int_iss_wakeups_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_3_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_4_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_5_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_6_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:147:30] wire [9:0] int_ren_wakeups_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_3_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_4_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_5_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_6_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:148:30] wire [9:0] pred_wakeup_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:149:26] wire [9:0] bypasses_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24] wire [9:0] bypasses_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24] wire [9:0] bypasses_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24] wire [9:0] bypasses_3_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24] wire [9:0] bypasses_4_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:174:24] wire [9:0] pred_bypasses_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:175:27] wire [9:0] p_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] p_uop_1_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] p_uop_2_fu_code = 10'h0; // @[consts.scala:269:19] wire [9:0] fast_wakeup_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:814:29] wire [9:0] slow_wakeup_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:815:29] wire [9:0] fast_wakeup_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:814:29] wire [9:0] slow_wakeup_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:815:29] wire [9:0] fast_wakeup_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:814:29] wire [9:0] slow_wakeup_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[core.scala:815:29] wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_br_type = 4'h0; // @[core.scala:51:7] wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_br_tag = 4'h0; // @[core.scala:51:7] wire [3:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_br_type = 4'h0; // @[core.scala:51:7] wire [3:0] io_ifu_fetchpacket_bits_uops_1_bits_br_tag = 4'h0; // @[core.scala:51:7] wire [3:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_br_type = 4'h0; // @[core.scala:51:7] wire [3:0] io_ifu_fetchpacket_bits_uops_2_bits_br_tag = 4'h0; // @[core.scala:51:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[core.scala:51:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:51:7] wire [3:0] io_ptw_tlb_hgatp_mode = 4'h0; // @[core.scala:51:7] wire [3:0] io_ptw_tlb_vsatp_mode = 4'h0; // @[core.scala:51:7] wire [3:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_3_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_4_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_5_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_6_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:147:30] wire [3:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_3_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_4_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_5_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_6_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:148:30] wire [3:0] pred_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:149:26] wire [3:0] pred_wakeup_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:149:26] wire [3:0] dec_uops_0_ctrl_br_type = 4'h0; // @[core.scala:158:24] wire [3:0] dec_uops_1_ctrl_br_type = 4'h0; // @[core.scala:158:24] wire [3:0] dec_uops_2_ctrl_br_type = 4'h0; // @[core.scala:158:24] wire [3:0] bypasses_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_3_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_3_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_4_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:174:24] wire [3:0] bypasses_4_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:174:24] wire [3:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:175:27] wire [3:0] pred_bypasses_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:175:27] wire [3:0] p_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] p_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] p_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] p_uop_1_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] p_uop_1_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] p_uop_cs_1_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] p_uop_2_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] p_uop_2_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] p_uop_cs_2_br_type = 4'h0; // @[consts.scala:279:18] wire [3:0] fast_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:814:29] wire [3:0] fast_wakeup_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:814:29] wire [3:0] slow_wakeup_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:815:29] wire [3:0] slow_wakeup_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:815:29] wire [3:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:814:29] wire [3:0] fast_wakeup_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:814:29] wire [3:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:815:29] wire [3:0] slow_wakeup_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:815:29] wire [3:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:814:29] wire [3:0] fast_wakeup_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:814:29] wire [3:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[core.scala:815:29] wire [3:0] slow_wakeup_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[core.scala:815:29] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op1_sel = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_iw_state = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_rxq_idx = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_mem_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_dst_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs1_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs2_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_tsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_op1_sel = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_iw_state = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_rxq_idx = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_mem_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_dst_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs1_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs2_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_tsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_op1_sel = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_iw_state = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_rxq_idx = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_mem_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_dst_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs1_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs2_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_fetchpacket_bits_uops_2_bits_debug_tsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_status_xs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ifu_status_vs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_dprv = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_prv = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_fs = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_mpp = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_xs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_vs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_hstatus_vsxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_hstatus_zero3 = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_hstatus_zero2 = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_dprv = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_prv = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_sxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_uxl = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_xs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_fs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_mpp = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_gstatus_vs = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_0_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_1_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_2_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_3_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_4_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_5_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_6_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_pmp_7_cfg_res = 2'h0; // @[core.scala:51:7] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:147:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:148:30] wire [1:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:149:26] wire [1:0] dec_uops_0_ctrl_op1_sel = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_0_iw_state = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_0_rxq_idx = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_0_debug_tsrc = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_1_ctrl_op1_sel = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_1_iw_state = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_1_rxq_idx = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_1_debug_tsrc = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_2_ctrl_op1_sel = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_2_iw_state = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_2_rxq_idx = 2'h0; // @[core.scala:158:24] wire [1:0] dec_uops_2_debug_tsrc = 2'h0; // @[core.scala:158:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:174:24] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:175:27] wire [1:0] p_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] p_uop_1_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_1_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_cs_1_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] p_uop_2_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_2_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] p_uop_cs_2_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:814:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:815:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:814:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:815:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:814:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[core.scala:815:29] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ctrl_op_fcn = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ldq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_stq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_mem_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ctrl_op_fcn = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ldq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_stq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_mem_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ctrl_op_fcn = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ldq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_stq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_fetchpacket_bits_uops_2_bits_mem_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_get_pc_0_ghist_ras_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_debug_ftq_idx_0 = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_debug_ftq_idx_1 = 5'h0; // @[core.scala:51:7] wire [4:0] io_ifu_debug_ftq_idx_2 = 5'h0; // @[core.scala:51:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[core.scala:51:7] wire [4:0] io_rocc_cmd_bits_inst_rs2 = 5'h0; // @[core.scala:51:7] wire [4:0] io_rocc_cmd_bits_inst_rs1 = 5'h0; // @[core.scala:51:7] wire [4:0] io_rocc_cmd_bits_inst_rd = 5'h0; // @[core.scala:51:7] wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[core.scala:51:7] wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_fflags_bits_flags = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_iresp_bits_fflags_bits_flags = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_fresp_bits_fflags_bits_flags = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_0_bits_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_1_bits_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_2_bits_ppred = 5'h0; // @[core.scala:51:7] wire [4:0] io_ptw_tlb_hstatus_zero1 = 5'h0; // @[core.scala:51:7] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_fflags_bits_flags = 5'h0; // @[core.scala:147:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_fflags_bits_flags = 5'h0; // @[core.scala:148:30] wire [4:0] pred_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_fflags_bits_flags = 5'h0; // @[core.scala:149:26] wire [4:0] dec_uops_0_ctrl_op_fcn = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_0_ldq_idx = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_0_stq_idx = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_0_ppred = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_1_ctrl_op_fcn = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_1_ldq_idx = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_1_stq_idx = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_1_ppred = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_2_ctrl_op_fcn = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_2_ldq_idx = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_2_stq_idx = 5'h0; // @[core.scala:158:24] wire [4:0] dec_uops_2_ppred = 5'h0; // @[core.scala:158:24] wire [4:0] dis_uops_0_ppred = 5'h0; // @[core.scala:167:24] wire [4:0] dis_uops_1_ppred = 5'h0; // @[core.scala:167:24] wire [4:0] dis_uops_2_ppred = 5'h0; // @[core.scala:167:24] wire [4:0] bypasses_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_fflags_bits_flags = 5'h0; // @[core.scala:174:24] wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_fflags_bits_flags = 5'h0; // @[core.scala:175:27] wire [4:0] _new_ghist_WIRE_ras_idx = 5'h0; // @[core.scala:406:44] wire [4:0] p_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] p_uop_1_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_1_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_1_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_1_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_1_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_1_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_cs_1_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] p_uop_2_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_2_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_2_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_2_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_2_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_2_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] p_uop_cs_2_op_fcn = 5'h0; // @[consts.scala:279:18] wire [4:0] fast_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_fflags_bits_flags = 5'h0; // @[core.scala:814:29] wire [4:0] slow_wakeup_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_fflags_bits_flags = 5'h0; // @[core.scala:815:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:814:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_fflags_bits_flags = 5'h0; // @[core.scala:815:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:814:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_ppred = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_fflags_bits_flags = 5'h0; // @[core.scala:815:29] wire [4:0] coreMonitorBundle_wrdst = 5'h0; // @[core.scala:1405:31] wire [4:0] coreMonitorBundle_rd0src = 5'h0; // @[core.scala:1405:31] wire [4:0] coreMonitorBundle_rd1src = 5'h0; // @[core.scala:1405:31] wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_load = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_sta = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ctrl_is_std = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p1_poisoned = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p2_poisoned = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_br = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_jalr = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_jal = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_prs1_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_prs2_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_prs3_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_exception = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_bypassable = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_mem_signed = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_fence = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_fencei = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_amo = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_uses_ldq = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_uses_stq = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_sys_pc2epc = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_unique = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_flush_on_commit = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ldst_is_rs1 = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ldst_val = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_frs3_en = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_val = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_single = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ma_if = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_is_load = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_is_sta = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ctrl_is_std = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iw_p1_poisoned = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iw_p2_poisoned = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_br = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_jalr = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_jal = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_prs1_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_prs2_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_prs3_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_exception = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_bypassable = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_mem_signed = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_fence = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_fencei = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_amo = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_uses_ldq = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_uses_stq = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_sys_pc2epc = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_unique = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_flush_on_commit = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ldst_is_rs1 = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ldst_val = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_frs3_en = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_val = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_single = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ma_if = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_is_load = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_is_sta = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ctrl_is_std = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_iw_p1_poisoned = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_iw_p2_poisoned = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_br = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_jalr = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_jal = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_prs1_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_prs2_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_prs3_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_exception = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_bypassable = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_mem_signed = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_fence = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_fencei = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_amo = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_uses_ldq = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_uses_stq = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_sys_pc2epc = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_is_unique = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_flush_on_commit = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ldst_is_rs1 = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_ldst_val = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_frs3_en = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_fp_val = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_fp_single = 1'h0; // @[core.scala:51:7] wire io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ma_if = 1'h0; // @[core.scala:51:7] wire io_ifu_get_pc_0_ghist_current_saw_branch_not_taken = 1'h0; // @[core.scala:51:7] wire io_ifu_get_pc_0_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:51:7] wire io_ifu_get_pc_0_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:51:7] wire io_ifu_status_mbe = 1'h0; // @[core.scala:51:7] wire io_ifu_status_sbe = 1'h0; // @[core.scala:51:7] wire io_ifu_status_sd_rv32 = 1'h0; // @[core.scala:51:7] wire io_ifu_status_ube = 1'h0; // @[core.scala:51:7] wire io_ifu_status_upie = 1'h0; // @[core.scala:51:7] wire io_ifu_status_hie = 1'h0; // @[core.scala:51:7] wire io_ifu_status_uie = 1'h0; // @[core.scala:51:7] wire io_ifu_sfence_bits_hv = 1'h0; // @[core.scala:51:7] wire io_ifu_sfence_bits_hg = 1'h0; // @[core.scala:51:7] wire io_ptw_sfence_bits_hv = 1'h0; // @[core.scala:51:7] wire io_ptw_sfence_bits_hg = 1'h0; // @[core.scala:51:7] wire io_ptw_status_mbe = 1'h0; // @[core.scala:51:7] wire io_ptw_status_sbe = 1'h0; // @[core.scala:51:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[core.scala:51:7] wire io_ptw_status_ube = 1'h0; // @[core.scala:51:7] wire io_ptw_status_upie = 1'h0; // @[core.scala:51:7] wire io_ptw_status_hie = 1'h0; // @[core.scala:51:7] wire io_ptw_status_uie = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_vtw = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_hu = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_spvp = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_spv = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_gva = 1'h0; // @[core.scala:51:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_debug = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_cease = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_wfi = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_dv = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_v = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_sd = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_mpv = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_gva = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_mbe = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_sbe = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_tsr = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_tw = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_tvm = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_mxr = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_sum = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_mprv = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_spp = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_mpie = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_ube = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_spie = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_upie = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_mie = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_hie = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_sie = 1'h0; // @[core.scala:51:7] wire io_ptw_gstatus_uie = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[core.scala:51:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_ready = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_valid = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_inst_xd = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_inst_xs1 = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_inst_xs2 = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_debug = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_cease = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_wfi = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_dv = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_v = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_sd = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_mpv = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_gva = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_tsr = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_tw = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_tvm = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_mxr = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_sum = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_mprv = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_spp = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_mpie = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_ube = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_spie = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_upie = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_mie = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_hie = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_sie = 1'h0; // @[core.scala:51:7] wire io_rocc_cmd_bits_status_uie = 1'h0; // @[core.scala:51:7] wire io_rocc_resp_ready = 1'h0; // @[core.scala:51:7] wire io_rocc_resp_valid = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_ready = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_valid = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_bits_signed = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_bits_dv = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_bits_phys = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s1_kill = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_nack = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_kill = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_uncached = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_resp_valid = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_resp_bits_signed = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_resp_bits_dv = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_resp_bits_replay = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_replay_next = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_ordered = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_store_pending = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_acquire = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_release = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_grant = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_blocked = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[core.scala:51:7] wire io_rocc_mem_clock_enabled = 1'h0; // @[core.scala:51:7] wire io_rocc_busy = 1'h0; // @[core.scala:51:7] wire io_rocc_interrupt = 1'h0; // @[core.scala:51:7] wire io_rocc_exception = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_predicated = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_valid = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_sfence_bits_hv = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_sfence_bits_hg = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_predicated = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_valid = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_predicated = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_valid = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ppred_busy = 1'h0; // @[core.scala:51:7] wire io_lsu_clr_unsafe_0_valid = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_req_valid = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_req_bits_valid = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_req_bits_bits_need_gpa = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_req_bits_bits_vstage1 = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_req_bits_bits_stage2 = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_resp_bits_fragmented_superpage = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_mbe = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_sbe = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_sd_rv32 = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_ube = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_upie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_hie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_status_uie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_vtsr = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_vtw = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_vtvm = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_hu = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_spvp = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_spv = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_gva = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_hstatus_vsbe = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_debug = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_cease = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_wfi = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_dv = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_v = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_sd = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_mpv = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_gva = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_mbe = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_sbe = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_sd_rv32 = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_tsr = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_tw = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_tvm = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_mxr = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_sum = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_mprv = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_spp = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_mpie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_ube = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_spie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_upie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_mie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_hie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_sie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_gstatus_uie = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_0_ren = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_0_wen = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_0_stall = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_0_set = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_1_ren = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_1_wen = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_1_stall = 1'h0; // @[core.scala:51:7] wire io_ptw_tlb_customCSRs_csrs_1_set = 1'h0; // @[core.scala:51:7] wire io_trace_insns_0_valid = 1'h0; // @[core.scala:51:7] wire io_trace_insns_0_exception = 1'h0; // @[core.scala:51:7] wire io_trace_insns_0_interrupt = 1'h0; // @[core.scala:51:7] wire io_trace_insns_1_valid = 1'h0; // @[core.scala:51:7] wire io_trace_insns_1_exception = 1'h0; // @[core.scala:51:7] wire io_trace_insns_1_interrupt = 1'h0; // @[core.scala:51:7] wire io_trace_insns_2_valid = 1'h0; // @[core.scala:51:7] wire io_trace_insns_2_exception = 1'h0; // @[core.scala:51:7] wire io_trace_insns_2_interrupt = 1'h0; // @[core.scala:51:7] wire int_iss_wakeups_1_bits_predicated = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_valid = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_predicated = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_valid = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_predicated = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_valid = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_predicated = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_valid = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_predicated = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_valid = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_predicated = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_valid = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:147:30] wire int_ren_wakeups_1_bits_predicated = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_valid = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_predicated = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_valid = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_predicated = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_valid = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_predicated = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_valid = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_predicated = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_valid = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_predicated = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_valid = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:148:30] wire pred_wakeup_valid = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_data = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_predicated = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_valid = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:149:26] wire pred_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:149:26] wire dec_uops_0_ctrl_fcn_dw = 1'h0; // @[core.scala:158:24] wire dec_uops_0_ctrl_is_load = 1'h0; // @[core.scala:158:24] wire dec_uops_0_ctrl_is_sta = 1'h0; // @[core.scala:158:24] wire dec_uops_0_ctrl_is_std = 1'h0; // @[core.scala:158:24] wire dec_uops_0_iw_p1_poisoned = 1'h0; // @[core.scala:158:24] wire dec_uops_0_iw_p2_poisoned = 1'h0; // @[core.scala:158:24] wire dec_uops_0_prs1_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_0_prs2_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_0_prs3_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_0_ppred_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_0_ldst_is_rs1 = 1'h0; // @[core.scala:158:24] wire dec_uops_0_xcpt_ma_if = 1'h0; // @[core.scala:158:24] wire dec_uops_1_ctrl_fcn_dw = 1'h0; // @[core.scala:158:24] wire dec_uops_1_ctrl_is_load = 1'h0; // @[core.scala:158:24] wire dec_uops_1_ctrl_is_sta = 1'h0; // @[core.scala:158:24] wire dec_uops_1_ctrl_is_std = 1'h0; // @[core.scala:158:24] wire dec_uops_1_iw_p1_poisoned = 1'h0; // @[core.scala:158:24] wire dec_uops_1_iw_p2_poisoned = 1'h0; // @[core.scala:158:24] wire dec_uops_1_prs1_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_1_prs2_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_1_prs3_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_1_ppred_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_1_ldst_is_rs1 = 1'h0; // @[core.scala:158:24] wire dec_uops_1_xcpt_ma_if = 1'h0; // @[core.scala:158:24] wire dec_uops_2_ctrl_fcn_dw = 1'h0; // @[core.scala:158:24] wire dec_uops_2_ctrl_is_load = 1'h0; // @[core.scala:158:24] wire dec_uops_2_ctrl_is_sta = 1'h0; // @[core.scala:158:24] wire dec_uops_2_ctrl_is_std = 1'h0; // @[core.scala:158:24] wire dec_uops_2_iw_p1_poisoned = 1'h0; // @[core.scala:158:24] wire dec_uops_2_iw_p2_poisoned = 1'h0; // @[core.scala:158:24] wire dec_uops_2_prs1_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_2_prs2_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_2_prs3_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_2_ppred_busy = 1'h0; // @[core.scala:158:24] wire dec_uops_2_ldst_is_rs1 = 1'h0; // @[core.scala:158:24] wire dec_uops_2_xcpt_ma_if = 1'h0; // @[core.scala:158:24] wire dis_uops_0_ppred_busy = 1'h0; // @[core.scala:167:24] wire dis_uops_1_ppred_busy = 1'h0; // @[core.scala:167:24] wire dis_uops_2_ppred_busy = 1'h0; // @[core.scala:167:24] wire bypasses_0_bits_predicated = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_valid = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24] wire bypasses_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_predicated = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_valid = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24] wire bypasses_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_predicated = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_valid = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24] wire bypasses_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_predicated = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_valid = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24] wire bypasses_3_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_predicated = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_valid = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:174:24] wire bypasses_4_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:174:24] wire pred_bypasses_0_bits_predicated = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_valid = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:175:27] wire pred_bypasses_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:175:27] wire brupdate_b2_valid = 1'h0; // @[core.scala:188:23] wire _use_this_mispredict_T_2 = 1'h0; // @[util.scala:363:52] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire hits_1 = 1'h0; // @[Events.scala:13:25] wire hits_2 = 1'h0; // @[Events.scala:13:25] wire hits_3 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33] wire hits_1_0 = 1'h0; // @[Events.scala:13:25] wire hits_1_1 = 1'h0; // @[Events.scala:13:25] wire hits_1_2 = 1'h0; // @[Events.scala:13:25] wire hits_1_3 = 1'h0; // @[Events.scala:13:25] wire hits_1_4 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33] wire hits_2_0 = 1'h0; // @[Events.scala:13:25] wire hits_2_1 = 1'h0; // @[Events.scala:13:25] wire hits_2_2 = 1'h0; // @[Events.scala:13:25] wire hits_2_3 = 1'h0; // @[Events.scala:13:25] wire hits_2_4 = 1'h0; // @[Events.scala:13:25] wire hits_2_5 = 1'h0; // @[Events.scala:13:25] wire custom_csrs_csrs_0_stall = 1'h0; // @[core.scala:276:25] wire custom_csrs_csrs_0_set = 1'h0; // @[core.scala:276:25] wire custom_csrs_csrs_1_stall = 1'h0; // @[core.scala:276:25] wire custom_csrs_csrs_1_set = 1'h0; // @[core.scala:276:25] wire _new_ghist_WIRE_current_saw_branch_not_taken = 1'h0; // @[core.scala:406:44] wire _new_ghist_WIRE_new_saw_branch_not_taken = 1'h0; // @[core.scala:406:44] wire _new_ghist_WIRE_new_saw_branch_taken = 1'h0; // @[core.scala:406:44] wire new_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:406:29] wire new_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:406:29] wire next_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:87:27] wire p_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire p_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire p_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire p_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire p_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire p_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire p_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire p_uop_is_br = 1'h0; // @[consts.scala:269:19] wire p_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire p_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire p_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire p_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire p_uop_taken = 1'h0; // @[consts.scala:269:19] wire p_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_exception = 1'h0; // @[consts.scala:269:19] wire p_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire p_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire p_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire p_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire p_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire p_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire p_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire p_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire p_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire p_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire p_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire p_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire p_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire p_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire p_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire p_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire p_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire p_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire p_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire p_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire p_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _dis_uops_0_ppred_busy_T_2 = 1'h0; // @[micro-op.scala:110:43] wire _dis_uops_0_ppred_busy_T_3 = 1'h0; // @[core.scala:669:48] wire p_uop_1_is_rvc = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire p_uop_1_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire p_uop_1_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_br = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_jalr = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_jal = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_sfb = 1'h0; // @[consts.scala:269:19] wire p_uop_1_edge_inst = 1'h0; // @[consts.scala:269:19] wire p_uop_1_taken = 1'h0; // @[consts.scala:269:19] wire p_uop_1_prs1_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_1_prs2_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_1_prs3_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ppred_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_1_exception = 1'h0; // @[consts.scala:269:19] wire p_uop_1_bypassable = 1'h0; // @[consts.scala:269:19] wire p_uop_1_mem_signed = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_fence = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_fencei = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_amo = 1'h0; // @[consts.scala:269:19] wire p_uop_1_uses_ldq = 1'h0; // @[consts.scala:269:19] wire p_uop_1_uses_stq = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire p_uop_1_is_unique = 1'h0; // @[consts.scala:269:19] wire p_uop_1_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire p_uop_1_ldst_val = 1'h0; // @[consts.scala:269:19] wire p_uop_1_frs3_en = 1'h0; // @[consts.scala:269:19] wire p_uop_1_fp_val = 1'h0; // @[consts.scala:269:19] wire p_uop_1_fp_single = 1'h0; // @[consts.scala:269:19] wire p_uop_1_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire p_uop_1_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire p_uop_1_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire p_uop_1_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire p_uop_1_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire p_uop_cs_1_fcn_dw = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_1_is_load = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_1_is_sta = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_1_is_std = 1'h0; // @[consts.scala:279:18] wire _dis_uops_1_ppred_busy_T_2 = 1'h0; // @[micro-op.scala:110:43] wire _dis_uops_1_ppred_busy_T_3 = 1'h0; // @[core.scala:669:48] wire p_uop_2_is_rvc = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire p_uop_2_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire p_uop_2_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_br = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_jalr = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_jal = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_sfb = 1'h0; // @[consts.scala:269:19] wire p_uop_2_edge_inst = 1'h0; // @[consts.scala:269:19] wire p_uop_2_taken = 1'h0; // @[consts.scala:269:19] wire p_uop_2_prs1_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_2_prs2_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_2_prs3_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ppred_busy = 1'h0; // @[consts.scala:269:19] wire p_uop_2_exception = 1'h0; // @[consts.scala:269:19] wire p_uop_2_bypassable = 1'h0; // @[consts.scala:269:19] wire p_uop_2_mem_signed = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_fence = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_fencei = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_amo = 1'h0; // @[consts.scala:269:19] wire p_uop_2_uses_ldq = 1'h0; // @[consts.scala:269:19] wire p_uop_2_uses_stq = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire p_uop_2_is_unique = 1'h0; // @[consts.scala:269:19] wire p_uop_2_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire p_uop_2_ldst_val = 1'h0; // @[consts.scala:269:19] wire p_uop_2_frs3_en = 1'h0; // @[consts.scala:269:19] wire p_uop_2_fp_val = 1'h0; // @[consts.scala:269:19] wire p_uop_2_fp_single = 1'h0; // @[consts.scala:269:19] wire p_uop_2_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire p_uop_2_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire p_uop_2_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire p_uop_2_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire p_uop_2_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire p_uop_cs_2_fcn_dw = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_2_is_load = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_2_is_sta = 1'h0; // @[consts.scala:279:18] wire p_uop_cs_2_is_std = 1'h0; // @[consts.scala:279:18] wire _dis_uops_2_ppred_busy_T_2 = 1'h0; // @[micro-op.scala:110:43] wire _dis_uops_2_ppred_busy_T_3 = 1'h0; // @[core.scala:669:48] wire _wait_for_rocc_T_1 = 1'h0; // @[core.scala:689:90] wire wait_for_rocc_0 = 1'h0; // @[core.scala:689:73] wire _wait_for_rocc_T_3 = 1'h0; // @[core.scala:689:90] wire wait_for_rocc_1 = 1'h0; // @[core.scala:689:73] wire _wait_for_rocc_T_5 = 1'h0; // @[core.scala:689:90] wire wait_for_rocc_2 = 1'h0; // @[core.scala:689:73] wire fast_wakeup_bits_predicated = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_valid = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:814:29] wire slow_wakeup_bits_predicated = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_valid = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:815:29] wire fast_wakeup_1_bits_predicated = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_valid = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:814:29] wire slow_wakeup_1_bits_predicated = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_valid = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:815:29] wire fast_wakeup_2_bits_predicated = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_valid = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:814:29] wire fast_wakeup_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:814:29] wire slow_wakeup_2_bits_predicated = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_valid = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_br = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_taken = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_exception = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[core.scala:815:29] wire slow_wakeup_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:815:29] wire _pred_wakeup_valid_T_1 = 1'h0; // @[micro-op.scala:109:42] wire _pred_wakeup_valid_T_2 = 1'h0; // @[core.scala:862:50] wire _pred_wakeup_valid_T_6 = 1'h0; // @[core.scala:863:58] wire _rob_io_csr_replay_valid_T = 1'h0; // @[core.scala:1008:58] wire _large_T_3 = 1'h0; // @[Counters.scala:68:28] wire coreMonitorBundle_excpt = 1'h0; // @[core.scala:1405:31] wire coreMonitorBundle_valid = 1'h0; // @[core.scala:1405:31] wire coreMonitorBundle_wrenx = 1'h0; // @[core.scala:1405:31] wire coreMonitorBundle_wrenf = 1'h0; // @[core.scala:1405:31] wire _io_rocc_exception_T = 1'h0; // @[core.scala:1424:61] wire _io_rocc_exception_T_1 = 1'h0; // @[core.scala:1424:41] wire [15:0] io_ifu_fetchpacket_bits_uops_0_bits_br_mask = 16'h0; // @[core.scala:51:7] wire [15:0] io_ifu_fetchpacket_bits_uops_1_bits_br_mask = 16'h0; // @[core.scala:51:7] wire [15:0] io_ifu_fetchpacket_bits_uops_2_bits_br_mask = 16'h0; // @[core.scala:51:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[core.scala:51:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[core.scala:51:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[core.scala:51:7] wire [15:0] io_lsu_exe_0_req_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:51:7] wire [15:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:51:7] wire [15:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:51:7] wire [15:0] io_ptw_tlb_ptbr_asid = 16'h0; // @[core.scala:51:7] wire [15:0] io_ptw_tlb_hgatp_asid = 16'h0; // @[core.scala:51:7] wire [15:0] io_ptw_tlb_vsatp_asid = 16'h0; // @[core.scala:51:7] wire [15:0] int_iss_wakeups_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_3_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_4_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_5_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_6_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:147:30] wire [15:0] int_ren_wakeups_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_3_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_4_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_5_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_6_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:148:30] wire [15:0] pred_wakeup_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:149:26] wire [15:0] bypasses_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24] wire [15:0] bypasses_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24] wire [15:0] bypasses_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24] wire [15:0] bypasses_3_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24] wire [15:0] bypasses_4_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:174:24] wire [15:0] pred_bypasses_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:175:27] wire [15:0] p_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] p_uop_1_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] p_uop_2_br_mask = 16'h0; // @[consts.scala:269:19] wire [15:0] fast_wakeup_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:814:29] wire [15:0] slow_wakeup_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:815:29] wire [15:0] fast_wakeup_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:814:29] wire [15:0] slow_wakeup_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:815:29] wire [15:0] fast_wakeup_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:814:29] wire [15:0] slow_wakeup_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[core.scala:815:29] wire [19:0] io_ifu_fetchpacket_bits_uops_0_bits_imm_packed = 20'h0; // @[core.scala:51:7] wire [19:0] io_ifu_fetchpacket_bits_uops_1_bits_imm_packed = 20'h0; // @[core.scala:51:7] wire [19:0] io_ifu_fetchpacket_bits_uops_2_bits_imm_packed = 20'h0; // @[core.scala:51:7] wire [19:0] io_lsu_exe_0_req_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:51:7] wire [19:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:51:7] wire [19:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:51:7] wire [19:0] int_iss_wakeups_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_3_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_4_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_5_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_6_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:147:30] wire [19:0] int_ren_wakeups_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_3_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_4_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_5_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_6_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:148:30] wire [19:0] pred_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:149:26] wire [19:0] bypasses_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24] wire [19:0] bypasses_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24] wire [19:0] bypasses_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24] wire [19:0] bypasses_3_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24] wire [19:0] bypasses_4_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:174:24] wire [19:0] pred_bypasses_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:175:27] wire [19:0] p_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] p_uop_1_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] p_uop_2_imm_packed = 20'h0; // @[consts.scala:269:19] wire [19:0] fast_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:814:29] wire [19:0] slow_wakeup_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:815:29] wire [19:0] fast_wakeup_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:814:29] wire [19:0] slow_wakeup_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:815:29] wire [19:0] fast_wakeup_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:814:29] wire [19:0] slow_wakeup_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[core.scala:815:29] wire [11:0] io_ifu_fetchpacket_bits_uops_0_bits_csr_addr = 12'h0; // @[core.scala:51:7] wire [11:0] io_ifu_fetchpacket_bits_uops_1_bits_csr_addr = 12'h0; // @[core.scala:51:7] wire [11:0] io_ifu_fetchpacket_bits_uops_2_bits_csr_addr = 12'h0; // @[core.scala:51:7] wire [11:0] io_lsu_exe_0_req_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:51:7] wire [11:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:51:7] wire [11:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:51:7] wire [11:0] int_iss_wakeups_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_3_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_4_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_5_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_6_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:147:30] wire [11:0] int_ren_wakeups_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_3_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_4_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_5_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_6_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:148:30] wire [11:0] pred_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:149:26] wire [11:0] dec_uops_0_csr_addr = 12'h0; // @[core.scala:158:24] wire [11:0] dec_uops_1_csr_addr = 12'h0; // @[core.scala:158:24] wire [11:0] dec_uops_2_csr_addr = 12'h0; // @[core.scala:158:24] wire [11:0] bypasses_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24] wire [11:0] bypasses_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24] wire [11:0] bypasses_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24] wire [11:0] bypasses_3_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24] wire [11:0] bypasses_4_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:174:24] wire [11:0] pred_bypasses_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:175:27] wire [11:0] p_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] p_uop_1_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] p_uop_2_csr_addr = 12'h0; // @[consts.scala:269:19] wire [11:0] fast_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:814:29] wire [11:0] slow_wakeup_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:815:29] wire [11:0] fast_wakeup_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:814:29] wire [11:0] slow_wakeup_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:815:29] wire [11:0] fast_wakeup_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:814:29] wire [11:0] slow_wakeup_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[core.scala:815:29] wire [63:0] io_ifu_fetchpacket_bits_uops_0_bits_exc_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_ifu_fetchpacket_bits_uops_1_bits_exc_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_ifu_fetchpacket_bits_uops_2_bits_exc_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_ifu_get_pc_0_ghist_old_history = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_cmd_bits_rs1 = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_cmd_bits_rs2 = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[core.scala:51:7] wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_req_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_0_wdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_0_value = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_0_sdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_1_wdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_1_value = 64'h0; // @[core.scala:51:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_1_sdata = 64'h0; // @[core.scala:51:7] wire [63:0] io_trace_insns_0_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_trace_insns_1_cause = 64'h0; // @[core.scala:51:7] wire [63:0] io_trace_insns_2_cause = 64'h0; // @[core.scala:51:7] wire [63:0] int_iss_wakeups_1_bits_data = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_2_bits_data = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_3_bits_data = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_3_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_4_bits_data = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_4_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_5_bits_data = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_5_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_6_bits_data = 64'h0; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_6_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:147:30] wire [63:0] int_ren_wakeups_1_bits_data = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_2_bits_data = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_3_bits_data = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_3_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_4_bits_data = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_4_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_5_bits_data = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_5_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_6_bits_data = 64'h0; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_6_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:148:30] wire [63:0] pred_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:149:26] wire [63:0] bypasses_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24] wire [63:0] bypasses_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24] wire [63:0] bypasses_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24] wire [63:0] bypasses_3_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24] wire [63:0] bypasses_4_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:174:24] wire [63:0] pred_bypasses_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:175:27] wire [63:0] custom_csrs_csrs_0_sdata = 64'h0; // @[core.scala:276:25] wire [63:0] custom_csrs_csrs_1_sdata = 64'h0; // @[core.scala:276:25] wire [63:0] _new_ghist_WIRE_old_history = 64'h0; // @[core.scala:406:44] wire [63:0] new_ghist_old_history = 64'h0; // @[core.scala:406:29] wire [63:0] p_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] p_uop_1_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] p_uop_2_exc_cause = 64'h0; // @[consts.scala:269:19] wire [63:0] fast_wakeup_bits_data = 64'h0; // @[core.scala:814:29] wire [63:0] fast_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:814:29] wire [63:0] slow_wakeup_bits_data = 64'h0; // @[core.scala:815:29] wire [63:0] slow_wakeup_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:815:29] wire [63:0] fast_wakeup_1_bits_data = 64'h0; // @[core.scala:814:29] wire [63:0] fast_wakeup_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:814:29] wire [63:0] slow_wakeup_1_bits_data = 64'h0; // @[core.scala:815:29] wire [63:0] slow_wakeup_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:815:29] wire [63:0] fast_wakeup_2_bits_data = 64'h0; // @[core.scala:814:29] wire [63:0] fast_wakeup_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:814:29] wire [63:0] slow_wakeup_2_bits_data = 64'h0; // @[core.scala:815:29] wire [63:0] slow_wakeup_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[core.scala:815:29] wire [63:0] coreMonitorBundle_hartid = 64'h0; // @[core.scala:1405:31] wire [63:0] coreMonitorBundle_pc = 64'h0; // @[core.scala:1405:31] wire [63:0] coreMonitorBundle_wrdata = 64'h0; // @[core.scala:1405:31] wire [63:0] coreMonitorBundle_rd0val = 64'h0; // @[core.scala:1405:31] wire [63:0] coreMonitorBundle_rd1val = 64'h0; // @[core.scala:1405:31] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_ldst = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs1 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs2 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs3 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_ldst = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs1 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs2 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs3 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_ldst = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs1 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs2 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ifu_fetchpacket_bits_uops_2_bits_lrs3 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:51:7] wire [5:0] io_ptw_tlb_hstatus_vgein = 6'h0; // @[core.scala:51:7] wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:147:30] wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:148:30] wire [5:0] pred_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:149:26] wire [5:0] bypasses_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:174:24] wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:175:27] wire [5:0] p_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_1_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_1_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_1_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_1_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_1_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_2_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_2_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_2_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_2_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] p_uop_2_lrs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] fast_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:814:29] wire [5:0] slow_wakeup_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:815:29] wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:814:29] wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:815:29] wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:814:29] wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_ldst = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[core.scala:815:29] wire [31:0] io_ifu_status_isa = 32'h14112D; // @[core.scala:51:7] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_status_isa = 32'h14112D; // @[core.scala:51:7] wire [22:0] io_ifu_status_zero2 = 23'h0; // @[core.scala:51:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[core.scala:51:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[core.scala:51:7] wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[core.scala:51:7] wire [22:0] io_ptw_tlb_status_zero2 = 23'h0; // @[core.scala:51:7] wire [22:0] io_ptw_tlb_gstatus_zero2 = 23'h0; // @[core.scala:51:7] wire [7:0] io_ifu_status_zero1 = 8'h0; // @[core.scala:51:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[core.scala:51:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[core.scala:51:7] wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[core.scala:51:7] wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[core.scala:51:7] wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[core.scala:51:7] wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[core.scala:51:7] wire [7:0] io_ptw_tlb_status_zero1 = 8'h0; // @[core.scala:51:7] wire [7:0] io_ptw_tlb_gstatus_zero1 = 8'h0; // @[core.scala:51:7] wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[core.scala:51:7] wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[core.scala:51:7] wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:51:7] wire [39:0] io_trace_insns_0_iaddr = 40'h0; // @[core.scala:51:7] wire [39:0] io_trace_insns_0_tval = 40'h0; // @[core.scala:51:7] wire [39:0] io_trace_insns_1_iaddr = 40'h0; // @[core.scala:51:7] wire [39:0] io_trace_insns_1_tval = 40'h0; // @[core.scala:51:7] wire [39:0] io_trace_insns_2_iaddr = 40'h0; // @[core.scala:51:7] wire [39:0] io_trace_insns_2_tval = 40'h0; // @[core.scala:51:7] wire [39:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:147:30] wire [39:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:148:30] wire [39:0] pred_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:149:26] wire [39:0] bypasses_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24] wire [39:0] bypasses_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24] wire [39:0] bypasses_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24] wire [39:0] bypasses_3_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24] wire [39:0] bypasses_4_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:174:24] wire [39:0] pred_bypasses_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:175:27] wire [39:0] p_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] p_uop_1_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] p_uop_2_debug_pc = 40'h0; // @[consts.scala:269:19] wire [39:0] fast_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:814:29] wire [39:0] slow_wakeup_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:815:29] wire [39:0] fast_wakeup_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:814:29] wire [39:0] slow_wakeup_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:815:29] wire [39:0] fast_wakeup_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:814:29] wire [39:0] slow_wakeup_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[core.scala:815:29] wire [1:0] io_ifu_status_sxl = 2'h2; // @[core.scala:51:7] wire [1:0] io_ifu_status_uxl = 2'h2; // @[core.scala:51:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[core.scala:51:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_sxl = 2'h2; // @[core.scala:51:7] wire [1:0] io_ptw_tlb_status_uxl = 2'h2; // @[core.scala:51:7] wire [1:0] p_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] p_uop_1_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [1:0] p_uop_2_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[core.scala:51:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[core.scala:51:7] wire [43:0] io_ptw_tlb_hgatp_ppn = 44'h0; // @[core.scala:51:7] wire [43:0] io_ptw_tlb_vsatp_ppn = 44'h0; // @[core.scala:51:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[core.scala:51:7] wire [29:0] io_ptw_tlb_hstatus_zero6 = 30'h0; // @[core.scala:51:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[core.scala:51:7] wire [8:0] io_ptw_tlb_hstatus_zero5 = 9'h0; // @[core.scala:51:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[core.scala:51:7] wire [31:0] io_rocc_cmd_bits_status_isa = 32'h0; // @[core.scala:51:7] wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_req_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:51:7] wire [31:0] io_ptw_tlb_gstatus_isa = 32'h0; // @[core.scala:51:7] wire [31:0] io_trace_insns_0_insn = 32'h0; // @[core.scala:51:7] wire [31:0] io_trace_insns_1_insn = 32'h0; // @[core.scala:51:7] wire [31:0] io_trace_insns_2_insn = 32'h0; // @[core.scala:51:7] wire [31:0] int_iss_wakeups_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_3_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_3_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_4_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_4_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_5_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_5_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_6_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_6_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:147:30] wire [31:0] int_ren_wakeups_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_3_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_3_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_4_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_4_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_5_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_5_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_6_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_6_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:148:30] wire [31:0] pred_wakeup_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:149:26] wire [31:0] pred_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:149:26] wire [31:0] bypasses_0_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_3_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_3_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_4_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:174:24] wire [31:0] bypasses_4_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:174:24] wire [31:0] pred_bypasses_0_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:175:27] wire [31:0] pred_bypasses_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:175:27] wire [31:0] p_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] p_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] p_uop_1_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] p_uop_1_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] p_uop_2_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] p_uop_2_debug_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] fast_wakeup_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:814:29] wire [31:0] fast_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:814:29] wire [31:0] slow_wakeup_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:815:29] wire [31:0] slow_wakeup_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:815:29] wire [31:0] fast_wakeup_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:814:29] wire [31:0] fast_wakeup_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:814:29] wire [31:0] slow_wakeup_1_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:815:29] wire [31:0] slow_wakeup_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:815:29] wire [31:0] fast_wakeup_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:814:29] wire [31:0] fast_wakeup_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:814:29] wire [31:0] slow_wakeup_2_bits_fflags_bits_uop_inst = 32'h0; // @[core.scala:815:29] wire [31:0] slow_wakeup_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[core.scala:815:29] wire [31:0] coreMonitorBundle_timer = 32'h0; // @[core.scala:1405:31] wire [31:0] coreMonitorBundle_inst = 32'h0; // @[core.scala:1405:31] wire io_lsu_exe_0_iresp_ready = 1'h1; // @[core.scala:51:7] wire io_lsu_exe_0_fresp_ready = 1'h1; // @[core.scala:51:7] wire _use_this_mispredict_T = 1'h1; // @[core.scala:206:31] wire use_this_mispredict = 1'h1; // @[core.scala:206:47] wire new_ghist_current_saw_branch_not_taken = 1'h1; // @[core.scala:406:29] wire flush_pc_req_ready = 1'h1; // @[core.scala:524:26] wire _large_T_1 = 1'h1; // @[Counters.scala:51:36] wire [26:0] io_ptw_tlb_req_bits_bits_addr = 27'h0; // @[core.scala:51:7] wire [4:0] _pause_mem_T = 5'h1F; // @[core.scala:912:77] wire [3:0] _cfi_idx_T_1 = 4'h8; // @[core.scala:442:45] wire [7:0] _next_ghist_not_taken_branches_T_19 = 8'hFF; // @[frontend.scala:91:45] wire dec_ready; // @[core.scala:161:24] wire [4:0] new_ghist_ras_idx = io_ifu_get_pc_0_entry_ras_idx_0; // @[core.scala:51:7, :406:29] wire _cfi_idx_T = io_ifu_get_pc_1_entry_start_bank_0; // @[core.scala:51:7, :442:32] wire io_ptw_sfence_valid_0 = io_ifu_sfence_valid_0; // @[core.scala:51:7] wire io_ptw_sfence_bits_rs1_0 = io_ifu_sfence_bits_rs1_0; // @[core.scala:51:7] wire io_ptw_sfence_bits_rs2_0 = io_ifu_sfence_bits_rs2_0; // @[core.scala:51:7] wire [38:0] io_ptw_sfence_bits_addr_0 = io_ifu_sfence_bits_addr_0; // @[core.scala:51:7] wire io_ptw_sfence_bits_asid_0 = io_ifu_sfence_bits_asid_0; // @[core.scala:51:7] wire [15:0] brupdate_b1_resolve_mask; // @[core.scala:188:23] wire [15:0] brupdate_b1_mispredict_mask; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_uopc; // @[core.scala:188:23] wire [31:0] brupdate_b2_uop_inst; // @[core.scala:188:23] wire [31:0] brupdate_b2_uop_debug_inst; // @[core.scala:188:23] wire brupdate_b2_uop_is_rvc; // @[core.scala:188:23] wire [39:0] brupdate_b2_uop_debug_pc; // @[core.scala:188:23] wire [2:0] brupdate_b2_uop_iq_type; // @[core.scala:188:23] wire [9:0] brupdate_b2_uop_fu_code; // @[core.scala:188:23] wire [3:0] brupdate_b2_uop_ctrl_br_type; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_ctrl_op1_sel; // @[core.scala:188:23] wire [2:0] brupdate_b2_uop_ctrl_op2_sel; // @[core.scala:188:23] wire [2:0] brupdate_b2_uop_ctrl_imm_sel; // @[core.scala:188:23] wire [4:0] brupdate_b2_uop_ctrl_op_fcn; // @[core.scala:188:23] wire brupdate_b2_uop_ctrl_fcn_dw; // @[core.scala:188:23] wire [2:0] brupdate_b2_uop_ctrl_csr_cmd; // @[core.scala:188:23] wire brupdate_b2_uop_ctrl_is_load; // @[core.scala:188:23] wire brupdate_b2_uop_ctrl_is_sta; // @[core.scala:188:23] wire brupdate_b2_uop_ctrl_is_std; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_iw_state; // @[core.scala:188:23] wire brupdate_b2_uop_iw_p1_poisoned; // @[core.scala:188:23] wire brupdate_b2_uop_iw_p2_poisoned; // @[core.scala:188:23] wire brupdate_b2_uop_is_br; // @[core.scala:188:23] wire brupdate_b2_uop_is_jalr; // @[core.scala:188:23] wire brupdate_b2_uop_is_jal; // @[core.scala:188:23] wire brupdate_b2_uop_is_sfb; // @[core.scala:188:23] wire [15:0] brupdate_b2_uop_br_mask; // @[core.scala:188:23] wire [3:0] brupdate_b2_uop_br_tag; // @[core.scala:188:23] wire [4:0] brupdate_b2_uop_ftq_idx; // @[core.scala:188:23] wire brupdate_b2_uop_edge_inst; // @[core.scala:188:23] wire [5:0] brupdate_b2_uop_pc_lob; // @[core.scala:188:23] wire brupdate_b2_uop_taken; // @[core.scala:188:23] wire [19:0] brupdate_b2_uop_imm_packed; // @[core.scala:188:23] wire [11:0] brupdate_b2_uop_csr_addr; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_rob_idx; // @[core.scala:188:23] wire [4:0] brupdate_b2_uop_ldq_idx; // @[core.scala:188:23] wire [4:0] brupdate_b2_uop_stq_idx; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_rxq_idx; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_pdst; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_prs1; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_prs2; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_prs3; // @[core.scala:188:23] wire [4:0] brupdate_b2_uop_ppred; // @[core.scala:188:23] wire brupdate_b2_uop_prs1_busy; // @[core.scala:188:23] wire brupdate_b2_uop_prs2_busy; // @[core.scala:188:23] wire brupdate_b2_uop_prs3_busy; // @[core.scala:188:23] wire brupdate_b2_uop_ppred_busy; // @[core.scala:188:23] wire [6:0] brupdate_b2_uop_stale_pdst; // @[core.scala:188:23] wire brupdate_b2_uop_exception; // @[core.scala:188:23] wire [63:0] brupdate_b2_uop_exc_cause; // @[core.scala:188:23] wire brupdate_b2_uop_bypassable; // @[core.scala:188:23] wire [4:0] brupdate_b2_uop_mem_cmd; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_mem_size; // @[core.scala:188:23] wire brupdate_b2_uop_mem_signed; // @[core.scala:188:23] wire brupdate_b2_uop_is_fence; // @[core.scala:188:23] wire brupdate_b2_uop_is_fencei; // @[core.scala:188:23] wire brupdate_b2_uop_is_amo; // @[core.scala:188:23] wire brupdate_b2_uop_uses_ldq; // @[core.scala:188:23] wire brupdate_b2_uop_uses_stq; // @[core.scala:188:23] wire brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:188:23] wire brupdate_b2_uop_is_unique; // @[core.scala:188:23] wire brupdate_b2_uop_flush_on_commit; // @[core.scala:188:23] wire brupdate_b2_uop_ldst_is_rs1; // @[core.scala:188:23] wire [5:0] brupdate_b2_uop_ldst; // @[core.scala:188:23] wire [5:0] brupdate_b2_uop_lrs1; // @[core.scala:188:23] wire [5:0] brupdate_b2_uop_lrs2; // @[core.scala:188:23] wire [5:0] brupdate_b2_uop_lrs3; // @[core.scala:188:23] wire brupdate_b2_uop_ldst_val; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_dst_rtype; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_lrs1_rtype; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_lrs2_rtype; // @[core.scala:188:23] wire brupdate_b2_uop_frs3_en; // @[core.scala:188:23] wire brupdate_b2_uop_fp_val; // @[core.scala:188:23] wire brupdate_b2_uop_fp_single; // @[core.scala:188:23] wire brupdate_b2_uop_xcpt_pf_if; // @[core.scala:188:23] wire brupdate_b2_uop_xcpt_ae_if; // @[core.scala:188:23] wire brupdate_b2_uop_xcpt_ma_if; // @[core.scala:188:23] wire brupdate_b2_uop_bp_debug_if; // @[core.scala:188:23] wire brupdate_b2_uop_bp_xcpt_if; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_debug_fsrc; // @[core.scala:188:23] wire [1:0] brupdate_b2_uop_debug_tsrc; // @[core.scala:188:23] wire brupdate_b2_mispredict; // @[core.scala:188:23] wire brupdate_b2_taken; // @[core.scala:188:23] wire [2:0] brupdate_b2_cfi_type; // @[core.scala:188:23] wire [1:0] brupdate_b2_pc_sel; // @[core.scala:188:23] wire [39:0] brupdate_b2_jalr_target; // @[core.scala:188:23] wire [20:0] brupdate_b2_target_offset; // @[core.scala:188:23] wire _io_ifu_flush_icache_T_13; // @[core.scala:390:13] wire dis_fire_0; // @[core.scala:168:24] wire [6:0] dis_uops_0_uopc; // @[core.scala:167:24] wire [31:0] dis_uops_0_inst; // @[core.scala:167:24] wire [31:0] dis_uops_0_debug_inst; // @[core.scala:167:24] wire dis_uops_0_is_rvc; // @[core.scala:167:24] wire [39:0] dis_uops_0_debug_pc; // @[core.scala:167:24] wire [2:0] dis_uops_0_iq_type; // @[core.scala:167:24] wire [9:0] dis_uops_0_fu_code; // @[core.scala:167:24] wire [3:0] dis_uops_0_ctrl_br_type; // @[core.scala:167:24] wire [1:0] dis_uops_0_ctrl_op1_sel; // @[core.scala:167:24] wire [2:0] dis_uops_0_ctrl_op2_sel; // @[core.scala:167:24] wire [2:0] dis_uops_0_ctrl_imm_sel; // @[core.scala:167:24] wire [4:0] dis_uops_0_ctrl_op_fcn; // @[core.scala:167:24] wire dis_uops_0_ctrl_fcn_dw; // @[core.scala:167:24] wire [2:0] dis_uops_0_ctrl_csr_cmd; // @[core.scala:167:24] wire dis_uops_0_ctrl_is_load; // @[core.scala:167:24] wire dis_uops_0_ctrl_is_sta; // @[core.scala:167:24] wire dis_uops_0_ctrl_is_std; // @[core.scala:167:24] wire [1:0] dis_uops_0_iw_state; // @[core.scala:167:24] wire dis_uops_0_iw_p1_poisoned; // @[core.scala:167:24] wire dis_uops_0_iw_p2_poisoned; // @[core.scala:167:24] wire dis_uops_0_is_br; // @[core.scala:167:24] wire dis_uops_0_is_jalr; // @[core.scala:167:24] wire dis_uops_0_is_jal; // @[core.scala:167:24] wire dis_uops_0_is_sfb; // @[core.scala:167:24] wire [15:0] dis_uops_0_br_mask; // @[core.scala:167:24] wire [3:0] dis_uops_0_br_tag; // @[core.scala:167:24] wire [4:0] dis_uops_0_ftq_idx; // @[core.scala:167:24] wire dis_uops_0_edge_inst; // @[core.scala:167:24] wire [5:0] dis_uops_0_pc_lob; // @[core.scala:167:24] wire dis_uops_0_taken; // @[core.scala:167:24] wire [19:0] dis_uops_0_imm_packed; // @[core.scala:167:24] wire [11:0] dis_uops_0_csr_addr; // @[core.scala:167:24] wire [6:0] dis_uops_0_rob_idx; // @[core.scala:167:24] wire [4:0] dis_uops_0_ldq_idx; // @[core.scala:167:24] wire [4:0] dis_uops_0_stq_idx; // @[core.scala:167:24] wire [1:0] dis_uops_0_rxq_idx; // @[core.scala:167:24] wire [6:0] dis_uops_0_pdst; // @[core.scala:167:24] wire [6:0] dis_uops_0_prs1; // @[core.scala:167:24] wire [6:0] dis_uops_0_prs2; // @[core.scala:167:24] wire [6:0] dis_uops_0_prs3; // @[core.scala:167:24] wire dis_uops_0_prs1_busy; // @[core.scala:167:24] wire dis_uops_0_prs2_busy; // @[core.scala:167:24] wire dis_uops_0_prs3_busy; // @[core.scala:167:24] wire [6:0] dis_uops_0_stale_pdst; // @[core.scala:167:24] wire dis_uops_0_exception; // @[core.scala:167:24] wire [63:0] dis_uops_0_exc_cause; // @[core.scala:167:24] wire dis_uops_0_bypassable; // @[core.scala:167:24] wire [4:0] dis_uops_0_mem_cmd; // @[core.scala:167:24] wire [1:0] dis_uops_0_mem_size; // @[core.scala:167:24] wire dis_uops_0_mem_signed; // @[core.scala:167:24] wire dis_uops_0_is_fence; // @[core.scala:167:24] wire dis_uops_0_is_fencei; // @[core.scala:167:24] wire dis_uops_0_is_amo; // @[core.scala:167:24] wire dis_uops_0_uses_ldq; // @[core.scala:167:24] wire dis_uops_0_uses_stq; // @[core.scala:167:24] wire dis_uops_0_is_sys_pc2epc; // @[core.scala:167:24] wire dis_uops_0_is_unique; // @[core.scala:167:24] wire dis_uops_0_flush_on_commit; // @[core.scala:167:24] wire dis_uops_0_ldst_is_rs1; // @[core.scala:167:24] wire [5:0] dis_uops_0_ldst; // @[core.scala:167:24] wire [5:0] dis_uops_0_lrs1; // @[core.scala:167:24] wire [5:0] dis_uops_0_lrs2; // @[core.scala:167:24] wire [5:0] dis_uops_0_lrs3; // @[core.scala:167:24] wire dis_uops_0_ldst_val; // @[core.scala:167:24] wire [1:0] dis_uops_0_dst_rtype; // @[core.scala:167:24] wire [1:0] dis_uops_0_lrs1_rtype; // @[core.scala:167:24] wire [1:0] dis_uops_0_lrs2_rtype; // @[core.scala:167:24] wire dis_uops_0_frs3_en; // @[core.scala:167:24] wire dis_uops_0_fp_val; // @[core.scala:167:24] wire dis_uops_0_fp_single; // @[core.scala:167:24] wire dis_uops_0_xcpt_pf_if; // @[core.scala:167:24] wire dis_uops_0_xcpt_ae_if; // @[core.scala:167:24] wire dis_uops_0_xcpt_ma_if; // @[core.scala:167:24] wire dis_uops_0_bp_debug_if; // @[core.scala:167:24] wire dis_uops_0_bp_xcpt_if; // @[core.scala:167:24] wire [1:0] dis_uops_0_debug_fsrc; // @[core.scala:167:24] wire [1:0] dis_uops_0_debug_tsrc; // @[core.scala:167:24] wire dis_fire_1; // @[core.scala:168:24] wire [6:0] dis_uops_1_uopc; // @[core.scala:167:24] wire [31:0] dis_uops_1_inst; // @[core.scala:167:24] wire [31:0] dis_uops_1_debug_inst; // @[core.scala:167:24] wire dis_uops_1_is_rvc; // @[core.scala:167:24] wire [39:0] dis_uops_1_debug_pc; // @[core.scala:167:24] wire [2:0] dis_uops_1_iq_type; // @[core.scala:167:24] wire [9:0] dis_uops_1_fu_code; // @[core.scala:167:24] wire [3:0] dis_uops_1_ctrl_br_type; // @[core.scala:167:24] wire [1:0] dis_uops_1_ctrl_op1_sel; // @[core.scala:167:24] wire [2:0] dis_uops_1_ctrl_op2_sel; // @[core.scala:167:24] wire [2:0] dis_uops_1_ctrl_imm_sel; // @[core.scala:167:24] wire [4:0] dis_uops_1_ctrl_op_fcn; // @[core.scala:167:24] wire dis_uops_1_ctrl_fcn_dw; // @[core.scala:167:24] wire [2:0] dis_uops_1_ctrl_csr_cmd; // @[core.scala:167:24] wire dis_uops_1_ctrl_is_load; // @[core.scala:167:24] wire dis_uops_1_ctrl_is_sta; // @[core.scala:167:24] wire dis_uops_1_ctrl_is_std; // @[core.scala:167:24] wire [1:0] dis_uops_1_iw_state; // @[core.scala:167:24] wire dis_uops_1_iw_p1_poisoned; // @[core.scala:167:24] wire dis_uops_1_iw_p2_poisoned; // @[core.scala:167:24] wire dis_uops_1_is_br; // @[core.scala:167:24] wire dis_uops_1_is_jalr; // @[core.scala:167:24] wire dis_uops_1_is_jal; // @[core.scala:167:24] wire dis_uops_1_is_sfb; // @[core.scala:167:24] wire [15:0] dis_uops_1_br_mask; // @[core.scala:167:24] wire [3:0] dis_uops_1_br_tag; // @[core.scala:167:24] wire [4:0] dis_uops_1_ftq_idx; // @[core.scala:167:24] wire dis_uops_1_edge_inst; // @[core.scala:167:24] wire [5:0] dis_uops_1_pc_lob; // @[core.scala:167:24] wire dis_uops_1_taken; // @[core.scala:167:24] wire [19:0] dis_uops_1_imm_packed; // @[core.scala:167:24] wire [11:0] dis_uops_1_csr_addr; // @[core.scala:167:24] wire [6:0] dis_uops_1_rob_idx; // @[core.scala:167:24] wire [4:0] dis_uops_1_ldq_idx; // @[core.scala:167:24] wire [4:0] dis_uops_1_stq_idx; // @[core.scala:167:24] wire [1:0] dis_uops_1_rxq_idx; // @[core.scala:167:24] wire [6:0] dis_uops_1_pdst; // @[core.scala:167:24] wire [6:0] dis_uops_1_prs1; // @[core.scala:167:24] wire [6:0] dis_uops_1_prs2; // @[core.scala:167:24] wire [6:0] dis_uops_1_prs3; // @[core.scala:167:24] wire dis_uops_1_prs1_busy; // @[core.scala:167:24] wire dis_uops_1_prs2_busy; // @[core.scala:167:24] wire dis_uops_1_prs3_busy; // @[core.scala:167:24] wire [6:0] dis_uops_1_stale_pdst; // @[core.scala:167:24] wire dis_uops_1_exception; // @[core.scala:167:24] wire [63:0] dis_uops_1_exc_cause; // @[core.scala:167:24] wire dis_uops_1_bypassable; // @[core.scala:167:24] wire [4:0] dis_uops_1_mem_cmd; // @[core.scala:167:24] wire [1:0] dis_uops_1_mem_size; // @[core.scala:167:24] wire dis_uops_1_mem_signed; // @[core.scala:167:24] wire dis_uops_1_is_fence; // @[core.scala:167:24] wire dis_uops_1_is_fencei; // @[core.scala:167:24] wire dis_uops_1_is_amo; // @[core.scala:167:24] wire dis_uops_1_uses_ldq; // @[core.scala:167:24] wire dis_uops_1_uses_stq; // @[core.scala:167:24] wire dis_uops_1_is_sys_pc2epc; // @[core.scala:167:24] wire dis_uops_1_is_unique; // @[core.scala:167:24] wire dis_uops_1_flush_on_commit; // @[core.scala:167:24] wire dis_uops_1_ldst_is_rs1; // @[core.scala:167:24] wire [5:0] dis_uops_1_ldst; // @[core.scala:167:24] wire [5:0] dis_uops_1_lrs1; // @[core.scala:167:24] wire [5:0] dis_uops_1_lrs2; // @[core.scala:167:24] wire [5:0] dis_uops_1_lrs3; // @[core.scala:167:24] wire dis_uops_1_ldst_val; // @[core.scala:167:24] wire [1:0] dis_uops_1_dst_rtype; // @[core.scala:167:24] wire [1:0] dis_uops_1_lrs1_rtype; // @[core.scala:167:24] wire [1:0] dis_uops_1_lrs2_rtype; // @[core.scala:167:24] wire dis_uops_1_frs3_en; // @[core.scala:167:24] wire dis_uops_1_fp_val; // @[core.scala:167:24] wire dis_uops_1_fp_single; // @[core.scala:167:24] wire dis_uops_1_xcpt_pf_if; // @[core.scala:167:24] wire dis_uops_1_xcpt_ae_if; // @[core.scala:167:24] wire dis_uops_1_xcpt_ma_if; // @[core.scala:167:24] wire dis_uops_1_bp_debug_if; // @[core.scala:167:24] wire dis_uops_1_bp_xcpt_if; // @[core.scala:167:24] wire [1:0] dis_uops_1_debug_fsrc; // @[core.scala:167:24] wire [1:0] dis_uops_1_debug_tsrc; // @[core.scala:167:24] wire dis_fire_2; // @[core.scala:168:24] wire [6:0] dis_uops_2_uopc; // @[core.scala:167:24] wire [31:0] dis_uops_2_inst; // @[core.scala:167:24] wire [31:0] dis_uops_2_debug_inst; // @[core.scala:167:24] wire dis_uops_2_is_rvc; // @[core.scala:167:24] wire [39:0] dis_uops_2_debug_pc; // @[core.scala:167:24] wire [2:0] dis_uops_2_iq_type; // @[core.scala:167:24] wire [9:0] dis_uops_2_fu_code; // @[core.scala:167:24] wire [3:0] dis_uops_2_ctrl_br_type; // @[core.scala:167:24] wire [1:0] dis_uops_2_ctrl_op1_sel; // @[core.scala:167:24] wire [2:0] dis_uops_2_ctrl_op2_sel; // @[core.scala:167:24] wire [2:0] dis_uops_2_ctrl_imm_sel; // @[core.scala:167:24] wire [4:0] dis_uops_2_ctrl_op_fcn; // @[core.scala:167:24] wire dis_uops_2_ctrl_fcn_dw; // @[core.scala:167:24] wire [2:0] dis_uops_2_ctrl_csr_cmd; // @[core.scala:167:24] wire dis_uops_2_ctrl_is_load; // @[core.scala:167:24] wire dis_uops_2_ctrl_is_sta; // @[core.scala:167:24] wire dis_uops_2_ctrl_is_std; // @[core.scala:167:24] wire [1:0] dis_uops_2_iw_state; // @[core.scala:167:24] wire dis_uops_2_iw_p1_poisoned; // @[core.scala:167:24] wire dis_uops_2_iw_p2_poisoned; // @[core.scala:167:24] wire dis_uops_2_is_br; // @[core.scala:167:24] wire dis_uops_2_is_jalr; // @[core.scala:167:24] wire dis_uops_2_is_jal; // @[core.scala:167:24] wire dis_uops_2_is_sfb; // @[core.scala:167:24] wire [15:0] dis_uops_2_br_mask; // @[core.scala:167:24] wire [3:0] dis_uops_2_br_tag; // @[core.scala:167:24] wire [4:0] dis_uops_2_ftq_idx; // @[core.scala:167:24] wire dis_uops_2_edge_inst; // @[core.scala:167:24] wire [5:0] dis_uops_2_pc_lob; // @[core.scala:167:24] wire dis_uops_2_taken; // @[core.scala:167:24] wire [19:0] dis_uops_2_imm_packed; // @[core.scala:167:24] wire [11:0] dis_uops_2_csr_addr; // @[core.scala:167:24] wire [6:0] dis_uops_2_rob_idx; // @[core.scala:167:24] wire [4:0] dis_uops_2_ldq_idx; // @[core.scala:167:24] wire [4:0] dis_uops_2_stq_idx; // @[core.scala:167:24] wire [1:0] dis_uops_2_rxq_idx; // @[core.scala:167:24] wire [6:0] dis_uops_2_pdst; // @[core.scala:167:24] wire [6:0] dis_uops_2_prs1; // @[core.scala:167:24] wire [6:0] dis_uops_2_prs2; // @[core.scala:167:24] wire [6:0] dis_uops_2_prs3; // @[core.scala:167:24] wire dis_uops_2_prs1_busy; // @[core.scala:167:24] wire dis_uops_2_prs2_busy; // @[core.scala:167:24] wire dis_uops_2_prs3_busy; // @[core.scala:167:24] wire [6:0] dis_uops_2_stale_pdst; // @[core.scala:167:24] wire dis_uops_2_exception; // @[core.scala:167:24] wire [63:0] dis_uops_2_exc_cause; // @[core.scala:167:24] wire dis_uops_2_bypassable; // @[core.scala:167:24] wire [4:0] dis_uops_2_mem_cmd; // @[core.scala:167:24] wire [1:0] dis_uops_2_mem_size; // @[core.scala:167:24] wire dis_uops_2_mem_signed; // @[core.scala:167:24] wire dis_uops_2_is_fence; // @[core.scala:167:24] wire dis_uops_2_is_fencei; // @[core.scala:167:24] wire dis_uops_2_is_amo; // @[core.scala:167:24] wire dis_uops_2_uses_ldq; // @[core.scala:167:24] wire dis_uops_2_uses_stq; // @[core.scala:167:24] wire dis_uops_2_is_sys_pc2epc; // @[core.scala:167:24] wire dis_uops_2_is_unique; // @[core.scala:167:24] wire dis_uops_2_flush_on_commit; // @[core.scala:167:24] wire dis_uops_2_ldst_is_rs1; // @[core.scala:167:24] wire [5:0] dis_uops_2_ldst; // @[core.scala:167:24] wire [5:0] dis_uops_2_lrs1; // @[core.scala:167:24] wire [5:0] dis_uops_2_lrs2; // @[core.scala:167:24] wire [5:0] dis_uops_2_lrs3; // @[core.scala:167:24] wire dis_uops_2_ldst_val; // @[core.scala:167:24] wire [1:0] dis_uops_2_dst_rtype; // @[core.scala:167:24] wire [1:0] dis_uops_2_lrs1_rtype; // @[core.scala:167:24] wire [1:0] dis_uops_2_lrs2_rtype; // @[core.scala:167:24] wire dis_uops_2_frs3_en; // @[core.scala:167:24] wire dis_uops_2_fp_val; // @[core.scala:167:24] wire dis_uops_2_fp_single; // @[core.scala:167:24] wire dis_uops_2_xcpt_pf_if; // @[core.scala:167:24] wire dis_uops_2_xcpt_ae_if; // @[core.scala:167:24] wire dis_uops_2_xcpt_ma_if; // @[core.scala:167:24] wire dis_uops_2_bp_debug_if; // @[core.scala:167:24] wire dis_uops_2_bp_xcpt_if; // @[core.scala:167:24] wire [1:0] dis_uops_2_debug_fsrc; // @[core.scala:167:24] wire [1:0] dis_uops_2_debug_tsrc; // @[core.scala:167:24] assign dis_uops_0_ldq_idx = io_lsu_dis_ldq_idx_0_0; // @[core.scala:51:7, :167:24] assign dis_uops_1_ldq_idx = io_lsu_dis_ldq_idx_1_0; // @[core.scala:51:7, :167:24] assign dis_uops_2_ldq_idx = io_lsu_dis_ldq_idx_2_0; // @[core.scala:51:7, :167:24] assign dis_uops_0_stq_idx = io_lsu_dis_stq_idx_0_0; // @[core.scala:51:7, :167:24] assign dis_uops_1_stq_idx = io_lsu_dis_stq_idx_1_0; // @[core.scala:51:7, :167:24] assign dis_uops_2_stq_idx = io_lsu_dis_stq_idx_2_0; // @[core.scala:51:7, :167:24] wire _io_lsu_fence_dmem_T_4; // @[core.scala:711:101] wire io_ifu_fetchpacket_ready_0; // @[core.scala:51:7] wire [4:0] io_ifu_get_pc_0_ftq_idx_0; // @[core.scala:51:7] wire [4:0] io_ifu_get_pc_1_ftq_idx_0; // @[core.scala:51:7] wire io_ifu_status_debug_0; // @[core.scala:51:7] wire io_ifu_status_cease_0; // @[core.scala:51:7] wire io_ifu_status_wfi_0; // @[core.scala:51:7] wire [1:0] io_ifu_status_dprv_0; // @[core.scala:51:7] wire io_ifu_status_dv_0; // @[core.scala:51:7] wire [1:0] io_ifu_status_prv_0; // @[core.scala:51:7] wire io_ifu_status_v_0; // @[core.scala:51:7] wire io_ifu_status_sd_0; // @[core.scala:51:7] wire io_ifu_status_mpv_0; // @[core.scala:51:7] wire io_ifu_status_gva_0; // @[core.scala:51:7] wire io_ifu_status_tsr_0; // @[core.scala:51:7] wire io_ifu_status_tw_0; // @[core.scala:51:7] wire io_ifu_status_tvm_0; // @[core.scala:51:7] wire io_ifu_status_mxr_0; // @[core.scala:51:7] wire io_ifu_status_sum_0; // @[core.scala:51:7] wire io_ifu_status_mprv_0; // @[core.scala:51:7] wire [1:0] io_ifu_status_fs_0; // @[core.scala:51:7] wire [1:0] io_ifu_status_mpp_0; // @[core.scala:51:7] wire io_ifu_status_spp_0; // @[core.scala:51:7] wire io_ifu_status_mpie_0; // @[core.scala:51:7] wire io_ifu_status_spie_0; // @[core.scala:51:7] wire io_ifu_status_mie_0; // @[core.scala:51:7] wire io_ifu_status_sie_0; // @[core.scala:51:7] wire [15:0] io_ifu_brupdate_b1_resolve_mask_0; // @[core.scala:51:7] wire [15:0] io_ifu_brupdate_b1_mispredict_mask_0; // @[core.scala:51:7] wire [3:0] io_ifu_brupdate_b2_uop_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_ifu_brupdate_b2_uop_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_ifu_brupdate_b2_uop_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_ifu_brupdate_b2_uop_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_ifu_brupdate_b2_uop_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ctrl_is_load_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ctrl_is_sta_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_uopc_0; // @[core.scala:51:7] wire [31:0] io_ifu_brupdate_b2_uop_inst_0; // @[core.scala:51:7] wire [31:0] io_ifu_brupdate_b2_uop_debug_inst_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_ifu_brupdate_b2_uop_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_ifu_brupdate_b2_uop_iq_type_0; // @[core.scala:51:7] wire [9:0] io_ifu_brupdate_b2_uop_fu_code_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_iw_state_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_br_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_jalr_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_jal_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_ifu_brupdate_b2_uop_br_mask_0; // @[core.scala:51:7] wire [3:0] io_ifu_brupdate_b2_uop_br_tag_0; // @[core.scala:51:7] wire [4:0] io_ifu_brupdate_b2_uop_ftq_idx_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_ifu_brupdate_b2_uop_pc_lob_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_taken_0; // @[core.scala:51:7] wire [19:0] io_ifu_brupdate_b2_uop_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_ifu_brupdate_b2_uop_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_ifu_brupdate_b2_uop_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_ifu_brupdate_b2_uop_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_pdst_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_prs1_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_prs2_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_prs3_0; // @[core.scala:51:7] wire [4:0] io_ifu_brupdate_b2_uop_ppred_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_prs1_busy_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_prs2_busy_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_prs3_busy_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_ifu_brupdate_b2_uop_stale_pdst_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_exception_0; // @[core.scala:51:7] wire [63:0] io_ifu_brupdate_b2_uop_exc_cause_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_bypassable_0; // @[core.scala:51:7] wire [4:0] io_ifu_brupdate_b2_uop_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_mem_size_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_mem_signed_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_fence_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_fencei_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_amo_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_uses_ldq_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_uses_stq_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_is_unique_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_flush_on_commit_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_ifu_brupdate_b2_uop_ldst_0; // @[core.scala:51:7] wire [5:0] io_ifu_brupdate_b2_uop_lrs1_0; // @[core.scala:51:7] wire [5:0] io_ifu_brupdate_b2_uop_lrs2_0; // @[core.scala:51:7] wire [5:0] io_ifu_brupdate_b2_uop_lrs3_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_lrs2_rtype_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_frs3_en_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_fp_val_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_fp_single_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_xcpt_pf_if_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_xcpt_ae_if_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_xcpt_ma_if_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_bp_debug_if_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_uop_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_uop_debug_tsrc_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_valid_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_mispredict_0; // @[core.scala:51:7] wire io_ifu_brupdate_b2_taken_0; // @[core.scala:51:7] wire [2:0] io_ifu_brupdate_b2_cfi_type_0; // @[core.scala:51:7] wire [1:0] io_ifu_brupdate_b2_pc_sel_0; // @[core.scala:51:7] wire [39:0] io_ifu_brupdate_b2_jalr_target_0; // @[core.scala:51:7] wire [20:0] io_ifu_brupdate_b2_target_offset_0; // @[core.scala:51:7] wire [63:0] io_ifu_redirect_ghist_old_history_0; // @[core.scala:51:7] wire io_ifu_redirect_ghist_current_saw_branch_not_taken_0; // @[core.scala:51:7] wire io_ifu_redirect_ghist_new_saw_branch_not_taken_0; // @[core.scala:51:7] wire io_ifu_redirect_ghist_new_saw_branch_taken_0; // @[core.scala:51:7] wire [4:0] io_ifu_redirect_ghist_ras_idx_0; // @[core.scala:51:7] wire io_ifu_commit_valid_0; // @[core.scala:51:7] wire [31:0] io_ifu_commit_bits_0; // @[core.scala:51:7] wire io_ifu_redirect_flush_0; // @[core.scala:51:7] wire io_ifu_redirect_val_0; // @[core.scala:51:7] wire [39:0] io_ifu_redirect_pc_0; // @[core.scala:51:7] wire [4:0] io_ifu_redirect_ftq_idx_0; // @[core.scala:51:7] wire io_ifu_flush_icache_0; // @[core.scala:51:7] wire [3:0] io_ptw_ptbr_mode_0; // @[core.scala:51:7] wire [43:0] io_ptw_ptbr_ppn_0; // @[core.scala:51:7] wire io_ptw_status_debug_0; // @[core.scala:51:7] wire io_ptw_status_cease_0; // @[core.scala:51:7] wire io_ptw_status_wfi_0; // @[core.scala:51:7] wire [1:0] io_ptw_status_dprv_0; // @[core.scala:51:7] wire io_ptw_status_dv_0; // @[core.scala:51:7] wire [1:0] io_ptw_status_prv_0; // @[core.scala:51:7] wire io_ptw_status_v_0; // @[core.scala:51:7] wire io_ptw_status_sd_0; // @[core.scala:51:7] wire io_ptw_status_mpv_0; // @[core.scala:51:7] wire io_ptw_status_gva_0; // @[core.scala:51:7] wire io_ptw_status_tsr_0; // @[core.scala:51:7] wire io_ptw_status_tw_0; // @[core.scala:51:7] wire io_ptw_status_tvm_0; // @[core.scala:51:7] wire io_ptw_status_mxr_0; // @[core.scala:51:7] wire io_ptw_status_sum_0; // @[core.scala:51:7] wire io_ptw_status_mprv_0; // @[core.scala:51:7] wire [1:0] io_ptw_status_fs_0; // @[core.scala:51:7] wire [1:0] io_ptw_status_mpp_0; // @[core.scala:51:7] wire io_ptw_status_spp_0; // @[core.scala:51:7] wire io_ptw_status_mpie_0; // @[core.scala:51:7] wire io_ptw_status_spie_0; // @[core.scala:51:7] wire io_ptw_status_mie_0; // @[core.scala:51:7] wire io_ptw_status_sie_0; // @[core.scala:51:7] wire io_ptw_pmp_0_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_0_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_0_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_0_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_0_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_0_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_1_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_1_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_1_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_1_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_1_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_1_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_2_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_2_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_2_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_2_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_2_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_2_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_3_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_3_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_3_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_3_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_3_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_3_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_4_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_4_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_4_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_4_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_4_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_4_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_5_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_5_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_5_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_5_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_5_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_5_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_6_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_6_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_6_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_6_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_6_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_6_mask_0; // @[core.scala:51:7] wire io_ptw_pmp_7_cfg_l_0; // @[core.scala:51:7] wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[core.scala:51:7] wire io_ptw_pmp_7_cfg_x_0; // @[core.scala:51:7] wire io_ptw_pmp_7_cfg_w_0; // @[core.scala:51:7] wire io_ptw_pmp_7_cfg_r_0; // @[core.scala:51:7] wire [29:0] io_ptw_pmp_7_addr_0; // @[core.scala:51:7] wire [31:0] io_ptw_pmp_7_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_req_bits_uop_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_uop_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_req_bits_uop_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_exe_0_req_bits_uop_debug_inst_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_req_bits_uop_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_exe_0_req_bits_uop_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_exe_0_req_bits_uop_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_iw_state_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_br_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_jalr_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_jal_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_exe_0_req_bits_uop_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_exe_0_req_bits_uop_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_uop_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_uop_pc_lob_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_exe_0_req_bits_uop_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_exe_0_req_bits_uop_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_uop_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_uop_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_uop_ppred_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_exe_0_req_bits_uop_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_req_bits_uop_exc_cause_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_exe_0_req_bits_uop_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_mem_size_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_mem_signed_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_fence_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_fencei_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_amo_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_uses_stq_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_is_unique_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_uop_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_uop_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_uop_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_exe_0_req_bits_uop_lrs3_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_frs3_en_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_fp_val_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_fp_single_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_uop_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_exe_0_req_bits_uop_debug_tsrc_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_mxcpt_valid_0; // @[core.scala:51:7] wire [24:0] io_lsu_exe_0_req_bits_mxcpt_bits_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_sfence_bits_rs1_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_sfence_bits_rs2_0; // @[core.scala:51:7] wire [38:0] io_lsu_exe_0_req_bits_sfence_bits_addr_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_sfence_bits_asid_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_bits_sfence_valid_0; // @[core.scala:51:7] wire [63:0] io_lsu_exe_0_req_bits_data_0; // @[core.scala:51:7] wire [39:0] io_lsu_exe_0_req_bits_addr_0; // @[core.scala:51:7] wire io_lsu_exe_0_req_valid_0; // @[core.scala:51:7] wire [3:0] io_lsu_dis_uops_0_bits_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_0_bits_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_0_bits_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_0_bits_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_0_bits_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_dis_uops_0_bits_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_dis_uops_0_bits_debug_inst_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_dis_uops_0_bits_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_0_bits_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_dis_uops_0_bits_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_iw_state_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_br_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_jalr_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_jal_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_dis_uops_0_bits_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_dis_uops_0_bits_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_0_bits_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_0_bits_pc_lob_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_dis_uops_0_bits_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_dis_uops_0_bits_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_0_bits_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_0_bits_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_prs3_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_prs3_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_0_bits_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_dis_uops_0_bits_exc_cause_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_0_bits_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_mem_size_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_mem_signed_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_fence_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_fencei_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_amo_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_uses_stq_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_is_unique_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_0_bits_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs3_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_frs3_en_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_fp_val_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_fp_single_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_bits_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_0_bits_debug_tsrc_0; // @[core.scala:51:7] wire io_lsu_dis_uops_0_valid_0; // @[core.scala:51:7] wire [3:0] io_lsu_dis_uops_1_bits_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_1_bits_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_1_bits_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_1_bits_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_1_bits_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_dis_uops_1_bits_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_dis_uops_1_bits_debug_inst_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_dis_uops_1_bits_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_1_bits_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_dis_uops_1_bits_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_iw_state_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_br_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_jalr_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_jal_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_dis_uops_1_bits_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_dis_uops_1_bits_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_1_bits_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_1_bits_pc_lob_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_dis_uops_1_bits_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_dis_uops_1_bits_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_1_bits_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_1_bits_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_prs3_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_prs3_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_1_bits_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_dis_uops_1_bits_exc_cause_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_1_bits_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_mem_size_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_mem_signed_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_fence_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_fencei_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_amo_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_uses_stq_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_is_unique_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_1_bits_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_1_bits_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_1_bits_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_1_bits_lrs3_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_frs3_en_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_fp_val_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_fp_single_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_bits_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_1_bits_debug_tsrc_0; // @[core.scala:51:7] wire io_lsu_dis_uops_1_valid_0; // @[core.scala:51:7] wire [3:0] io_lsu_dis_uops_2_bits_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_2_bits_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_2_bits_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_2_bits_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_2_bits_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_dis_uops_2_bits_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_dis_uops_2_bits_debug_inst_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_dis_uops_2_bits_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_dis_uops_2_bits_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_dis_uops_2_bits_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_iw_state_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_br_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_jalr_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_jal_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_dis_uops_2_bits_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_dis_uops_2_bits_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_2_bits_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_2_bits_pc_lob_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_dis_uops_2_bits_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_dis_uops_2_bits_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_2_bits_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_2_bits_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_prs3_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_prs3_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_dis_uops_2_bits_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_dis_uops_2_bits_exc_cause_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_dis_uops_2_bits_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_mem_size_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_mem_signed_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_fence_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_fencei_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_amo_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_uses_stq_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_is_unique_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_2_bits_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_2_bits_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_2_bits_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_dis_uops_2_bits_lrs3_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_frs3_en_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_fp_val_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_fp_single_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_bits_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_dis_uops_2_bits_debug_tsrc_0; // @[core.scala:51:7] wire io_lsu_dis_uops_2_valid_0; // @[core.scala:51:7] wire [3:0] io_lsu_fp_stdata_bits_uop_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_uop_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_fp_stdata_bits_uop_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_fp_stdata_bits_uop_debug_inst_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_fp_stdata_bits_uop_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_uop_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_fp_stdata_bits_uop_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_iw_state_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_br_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_jalr_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_jal_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_fp_stdata_bits_uop_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_fp_stdata_bits_uop_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_uop_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_uop_pc_lob_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_fp_stdata_bits_uop_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_fp_stdata_bits_uop_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_uop_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_uop_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_uop_ppred_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_uop_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_fp_stdata_bits_uop_exc_cause_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_uop_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_mem_size_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_mem_signed_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_fence_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_fencei_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_amo_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_uses_stq_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_is_unique_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_uop_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_uop_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_uop_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_uop_lrs3_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_frs3_en_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_fp_val_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_fp_single_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_uop_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_uop_debug_tsrc_0; // @[core.scala:51:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_br_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc_0; // @[core.scala:51:7] wire [4:0] io_lsu_fp_stdata_bits_fflags_bits_flags_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_fflags_valid_0; // @[core.scala:51:7] wire [63:0] io_lsu_fp_stdata_bits_data_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_bits_predicated_0; // @[core.scala:51:7] wire io_lsu_fp_stdata_valid_0; // @[core.scala:51:7] wire io_lsu_commit_valids_0_0; // @[core.scala:51:7] wire io_lsu_commit_valids_1_0; // @[core.scala:51:7] wire io_lsu_commit_valids_2_0; // @[core.scala:51:7] wire io_lsu_commit_arch_valids_0_0; // @[core.scala:51:7] wire io_lsu_commit_arch_valids_1_0; // @[core.scala:51:7] wire io_lsu_commit_arch_valids_2_0; // @[core.scala:51:7] wire [3:0] io_lsu_commit_uops_0_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_0_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_0_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_0_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_0_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_uops_0_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_uops_0_debug_inst_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_commit_uops_0_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_0_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_commit_uops_0_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_iw_state_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_br_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_jalr_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_jal_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_commit_uops_0_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_commit_uops_0_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_0_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_0_pc_lob_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_commit_uops_0_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_commit_uops_0_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_0_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_0_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_0_ppred_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_0_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_commit_uops_0_exc_cause_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_0_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_mem_size_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_mem_signed_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_fence_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_fencei_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_amo_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_uses_stq_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_is_unique_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_0_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_0_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_0_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_0_lrs3_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_frs3_en_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_fp_val_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_fp_single_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_0_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_0_debug_tsrc_0; // @[core.scala:51:7] wire [3:0] io_lsu_commit_uops_1_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_1_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_1_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_1_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_1_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_uops_1_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_uops_1_debug_inst_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_commit_uops_1_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_1_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_commit_uops_1_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_iw_state_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_br_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_jalr_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_jal_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_commit_uops_1_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_commit_uops_1_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_1_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_1_pc_lob_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_commit_uops_1_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_commit_uops_1_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_1_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_1_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_1_ppred_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_1_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_commit_uops_1_exc_cause_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_1_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_mem_size_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_mem_signed_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_fence_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_fencei_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_amo_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_uses_stq_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_is_unique_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_1_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_1_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_1_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_1_lrs3_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_frs3_en_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_fp_val_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_fp_single_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_1_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_1_debug_tsrc_0; // @[core.scala:51:7] wire [3:0] io_lsu_commit_uops_2_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_2_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_2_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_2_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_2_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_uops_2_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_uops_2_debug_inst_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_commit_uops_2_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_commit_uops_2_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_commit_uops_2_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_iw_state_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_br_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_jalr_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_jal_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_commit_uops_2_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_commit_uops_2_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_2_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_2_pc_lob_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_commit_uops_2_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_commit_uops_2_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_2_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_2_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_2_ppred_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_commit_uops_2_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_commit_uops_2_exc_cause_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_uops_2_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_mem_size_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_mem_signed_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_fence_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_fencei_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_amo_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_uses_stq_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_is_unique_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_2_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_2_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_2_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_commit_uops_2_lrs3_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_frs3_en_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_fp_val_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_fp_single_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_commit_uops_2_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_commit_uops_2_debug_tsrc_0; // @[core.scala:51:7] wire io_lsu_commit_fflags_valid_0; // @[core.scala:51:7] wire [4:0] io_lsu_commit_fflags_bits_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_debug_insts_0_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_debug_insts_1_0; // @[core.scala:51:7] wire [31:0] io_lsu_commit_debug_insts_2_0; // @[core.scala:51:7] wire io_lsu_commit_rbk_valids_0_0; // @[core.scala:51:7] wire io_lsu_commit_rbk_valids_1_0; // @[core.scala:51:7] wire io_lsu_commit_rbk_valids_2_0; // @[core.scala:51:7] wire [63:0] io_lsu_commit_debug_wdata_0_0; // @[core.scala:51:7] wire [63:0] io_lsu_commit_debug_wdata_1_0; // @[core.scala:51:7] wire [63:0] io_lsu_commit_debug_wdata_2_0; // @[core.scala:51:7] wire io_lsu_commit_rollback_0; // @[core.scala:51:7] wire [15:0] io_lsu_brupdate_b1_resolve_mask_0; // @[core.scala:51:7] wire [15:0] io_lsu_brupdate_b1_mispredict_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_brupdate_b2_uop_ctrl_br_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_ctrl_op1_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_brupdate_b2_uop_ctrl_op2_sel_0; // @[core.scala:51:7] wire [2:0] io_lsu_brupdate_b2_uop_ctrl_imm_sel_0; // @[core.scala:51:7] wire [4:0] io_lsu_brupdate_b2_uop_ctrl_op_fcn_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ctrl_fcn_dw_0; // @[core.scala:51:7] wire [2:0] io_lsu_brupdate_b2_uop_ctrl_csr_cmd_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ctrl_is_load_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ctrl_is_sta_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ctrl_is_std_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_uopc_0; // @[core.scala:51:7] wire [31:0] io_lsu_brupdate_b2_uop_inst_0; // @[core.scala:51:7] wire [31:0] io_lsu_brupdate_b2_uop_debug_inst_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_rvc_0; // @[core.scala:51:7] wire [39:0] io_lsu_brupdate_b2_uop_debug_pc_0; // @[core.scala:51:7] wire [2:0] io_lsu_brupdate_b2_uop_iq_type_0; // @[core.scala:51:7] wire [9:0] io_lsu_brupdate_b2_uop_fu_code_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_iw_state_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_iw_p1_poisoned_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_iw_p2_poisoned_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_br_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_jalr_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_jal_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_sfb_0; // @[core.scala:51:7] wire [15:0] io_lsu_brupdate_b2_uop_br_mask_0; // @[core.scala:51:7] wire [3:0] io_lsu_brupdate_b2_uop_br_tag_0; // @[core.scala:51:7] wire [4:0] io_lsu_brupdate_b2_uop_ftq_idx_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_edge_inst_0; // @[core.scala:51:7] wire [5:0] io_lsu_brupdate_b2_uop_pc_lob_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_taken_0; // @[core.scala:51:7] wire [19:0] io_lsu_brupdate_b2_uop_imm_packed_0; // @[core.scala:51:7] wire [11:0] io_lsu_brupdate_b2_uop_csr_addr_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_rob_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_brupdate_b2_uop_ldq_idx_0; // @[core.scala:51:7] wire [4:0] io_lsu_brupdate_b2_uop_stq_idx_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_pdst_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_prs1_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_prs2_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_prs3_0; // @[core.scala:51:7] wire [4:0] io_lsu_brupdate_b2_uop_ppred_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_prs1_busy_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_prs2_busy_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_prs3_busy_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ppred_busy_0; // @[core.scala:51:7] wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_brupdate_b2_uop_exc_cause_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_bypassable_0; // @[core.scala:51:7] wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_mem_size_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_mem_signed_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_fence_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_fencei_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_amo_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_uses_ldq_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_uses_stq_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_sys_pc2epc_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_is_unique_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_flush_on_commit_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ldst_is_rs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_brupdate_b2_uop_ldst_0; // @[core.scala:51:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs1_0; // @[core.scala:51:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs2_0; // @[core.scala:51:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs3_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_ldst_val_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_frs3_en_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_fp_val_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_fp_single_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_xcpt_pf_if_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_xcpt_ae_if_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_xcpt_ma_if_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_bp_debug_if_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_uop_bp_xcpt_if_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_debug_fsrc_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_uop_debug_tsrc_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_valid_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_mispredict_0; // @[core.scala:51:7] wire io_lsu_brupdate_b2_taken_0; // @[core.scala:51:7] wire [2:0] io_lsu_brupdate_b2_cfi_type_0; // @[core.scala:51:7] wire [1:0] io_lsu_brupdate_b2_pc_sel_0; // @[core.scala:51:7] wire [39:0] io_lsu_brupdate_b2_jalr_target_0; // @[core.scala:51:7] wire [20:0] io_lsu_brupdate_b2_target_offset_0; // @[core.scala:51:7] wire io_lsu_commit_load_at_rob_head_0; // @[core.scala:51:7] wire io_lsu_fence_dmem_0; // @[core.scala:51:7] wire [6:0] io_lsu_rob_pnr_idx_0; // @[core.scala:51:7] wire [6:0] io_lsu_rob_head_idx_0; // @[core.scala:51:7] wire io_lsu_exception_0; // @[core.scala:51:7] wire [63:0] io_lsu_tsc_reg_0; // @[core.scala:51:7] wire io_trace_custom_rob_empty_0; // @[core.scala:51:7] wire [63:0] io_trace_time_0; // @[core.scala:51:7] wire [2:0] io_fcsr_rm; // @[core.scala:51:7] wire _int_iss_wakeups_0_valid_T_2; // @[core.scala:795:52] wire fast_wakeup_valid; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_uopc; // @[core.scala:814:29] wire [31:0] fast_wakeup_bits_uop_inst; // @[core.scala:814:29] wire [31:0] fast_wakeup_bits_uop_debug_inst; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_rvc; // @[core.scala:814:29] wire [39:0] fast_wakeup_bits_uop_debug_pc; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_uop_iq_type; // @[core.scala:814:29] wire [9:0] fast_wakeup_bits_uop_fu_code; // @[core.scala:814:29] wire [3:0] fast_wakeup_bits_uop_ctrl_br_type; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:814:29] wire [2:0] fast_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ctrl_is_load; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ctrl_is_std; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_iw_state; // @[core.scala:814:29] wire fast_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:814:29] wire fast_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_br; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_jalr; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_jal; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_sfb; // @[core.scala:814:29] wire [15:0] fast_wakeup_bits_uop_br_mask; // @[core.scala:814:29] wire [3:0] fast_wakeup_bits_uop_br_tag; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_uop_ftq_idx; // @[core.scala:814:29] wire fast_wakeup_bits_uop_edge_inst; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_uop_pc_lob; // @[core.scala:814:29] wire fast_wakeup_bits_uop_taken; // @[core.scala:814:29] wire [19:0] fast_wakeup_bits_uop_imm_packed; // @[core.scala:814:29] wire [11:0] fast_wakeup_bits_uop_csr_addr; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_rob_idx; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_uop_ldq_idx; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_uop_stq_idx; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_rxq_idx; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_pdst; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_prs1; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_prs2; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_prs3; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_uop_ppred; // @[core.scala:814:29] wire fast_wakeup_bits_uop_prs1_busy; // @[core.scala:814:29] wire fast_wakeup_bits_uop_prs2_busy; // @[core.scala:814:29] wire fast_wakeup_bits_uop_prs3_busy; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ppred_busy; // @[core.scala:814:29] wire [6:0] fast_wakeup_bits_uop_stale_pdst; // @[core.scala:814:29] wire fast_wakeup_bits_uop_exception; // @[core.scala:814:29] wire [63:0] fast_wakeup_bits_uop_exc_cause; // @[core.scala:814:29] wire fast_wakeup_bits_uop_bypassable; // @[core.scala:814:29] wire [4:0] fast_wakeup_bits_uop_mem_cmd; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_mem_size; // @[core.scala:814:29] wire fast_wakeup_bits_uop_mem_signed; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_fence; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_fencei; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_amo; // @[core.scala:814:29] wire fast_wakeup_bits_uop_uses_ldq; // @[core.scala:814:29] wire fast_wakeup_bits_uop_uses_stq; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:814:29] wire fast_wakeup_bits_uop_is_unique; // @[core.scala:814:29] wire fast_wakeup_bits_uop_flush_on_commit; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_uop_ldst; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_uop_lrs1; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_uop_lrs2; // @[core.scala:814:29] wire [5:0] fast_wakeup_bits_uop_lrs3; // @[core.scala:814:29] wire fast_wakeup_bits_uop_ldst_val; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_dst_rtype; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_lrs1_rtype; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_lrs2_rtype; // @[core.scala:814:29] wire fast_wakeup_bits_uop_frs3_en; // @[core.scala:814:29] wire fast_wakeup_bits_uop_fp_val; // @[core.scala:814:29] wire fast_wakeup_bits_uop_fp_single; // @[core.scala:814:29] wire fast_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:814:29] wire fast_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:814:29] wire fast_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:814:29] wire fast_wakeup_bits_uop_bp_debug_if; // @[core.scala:814:29] wire fast_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_debug_fsrc; // @[core.scala:814:29] wire [1:0] fast_wakeup_bits_uop_debug_tsrc; // @[core.scala:814:29] wire slow_wakeup_valid; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_uopc; // @[core.scala:815:29] wire [31:0] slow_wakeup_bits_uop_inst; // @[core.scala:815:29] wire [31:0] slow_wakeup_bits_uop_debug_inst; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_rvc; // @[core.scala:815:29] wire [39:0] slow_wakeup_bits_uop_debug_pc; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_uop_iq_type; // @[core.scala:815:29] wire [9:0] slow_wakeup_bits_uop_fu_code; // @[core.scala:815:29] wire [3:0] slow_wakeup_bits_uop_ctrl_br_type; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:815:29] wire [2:0] slow_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ctrl_is_load; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ctrl_is_std; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_iw_state; // @[core.scala:815:29] wire slow_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:815:29] wire slow_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_br; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_jalr; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_jal; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_sfb; // @[core.scala:815:29] wire [15:0] slow_wakeup_bits_uop_br_mask; // @[core.scala:815:29] wire [3:0] slow_wakeup_bits_uop_br_tag; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_uop_ftq_idx; // @[core.scala:815:29] wire slow_wakeup_bits_uop_edge_inst; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_uop_pc_lob; // @[core.scala:815:29] wire slow_wakeup_bits_uop_taken; // @[core.scala:815:29] wire [19:0] slow_wakeup_bits_uop_imm_packed; // @[core.scala:815:29] wire [11:0] slow_wakeup_bits_uop_csr_addr; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_rob_idx; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_uop_ldq_idx; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_uop_stq_idx; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_rxq_idx; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_pdst; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_prs1; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_prs2; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_prs3; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_uop_ppred; // @[core.scala:815:29] wire slow_wakeup_bits_uop_prs1_busy; // @[core.scala:815:29] wire slow_wakeup_bits_uop_prs2_busy; // @[core.scala:815:29] wire slow_wakeup_bits_uop_prs3_busy; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ppred_busy; // @[core.scala:815:29] wire [6:0] slow_wakeup_bits_uop_stale_pdst; // @[core.scala:815:29] wire slow_wakeup_bits_uop_exception; // @[core.scala:815:29] wire [63:0] slow_wakeup_bits_uop_exc_cause; // @[core.scala:815:29] wire slow_wakeup_bits_uop_bypassable; // @[core.scala:815:29] wire [4:0] slow_wakeup_bits_uop_mem_cmd; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_mem_size; // @[core.scala:815:29] wire slow_wakeup_bits_uop_mem_signed; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_fence; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_fencei; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_amo; // @[core.scala:815:29] wire slow_wakeup_bits_uop_uses_ldq; // @[core.scala:815:29] wire slow_wakeup_bits_uop_uses_stq; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:815:29] wire slow_wakeup_bits_uop_is_unique; // @[core.scala:815:29] wire slow_wakeup_bits_uop_flush_on_commit; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_uop_ldst; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_uop_lrs1; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_uop_lrs2; // @[core.scala:815:29] wire [5:0] slow_wakeup_bits_uop_lrs3; // @[core.scala:815:29] wire slow_wakeup_bits_uop_ldst_val; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_dst_rtype; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_lrs1_rtype; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_lrs2_rtype; // @[core.scala:815:29] wire slow_wakeup_bits_uop_frs3_en; // @[core.scala:815:29] wire slow_wakeup_bits_uop_fp_val; // @[core.scala:815:29] wire slow_wakeup_bits_uop_fp_single; // @[core.scala:815:29] wire slow_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:815:29] wire slow_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:815:29] wire slow_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:815:29] wire slow_wakeup_bits_uop_bp_debug_if; // @[core.scala:815:29] wire slow_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_debug_fsrc; // @[core.scala:815:29] wire [1:0] slow_wakeup_bits_uop_debug_tsrc; // @[core.scala:815:29] wire fast_wakeup_1_valid; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_uopc; // @[core.scala:814:29] wire [31:0] fast_wakeup_1_bits_uop_inst; // @[core.scala:814:29] wire [31:0] fast_wakeup_1_bits_uop_debug_inst; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_rvc; // @[core.scala:814:29] wire [39:0] fast_wakeup_1_bits_uop_debug_pc; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_uop_iq_type; // @[core.scala:814:29] wire [9:0] fast_wakeup_1_bits_uop_fu_code; // @[core.scala:814:29] wire [3:0] fast_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:814:29] wire [2:0] fast_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_iw_state; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_br; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_jalr; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_jal; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_sfb; // @[core.scala:814:29] wire [15:0] fast_wakeup_1_bits_uop_br_mask; // @[core.scala:814:29] wire [3:0] fast_wakeup_1_bits_uop_br_tag; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_uop_ftq_idx; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_edge_inst; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_uop_pc_lob; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_taken; // @[core.scala:814:29] wire [19:0] fast_wakeup_1_bits_uop_imm_packed; // @[core.scala:814:29] wire [11:0] fast_wakeup_1_bits_uop_csr_addr; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_rob_idx; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_uop_ldq_idx; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_uop_stq_idx; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_rxq_idx; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_pdst; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_prs1; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_prs2; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_prs3; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_uop_ppred; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_prs1_busy; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_prs2_busy; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_prs3_busy; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ppred_busy; // @[core.scala:814:29] wire [6:0] fast_wakeup_1_bits_uop_stale_pdst; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_exception; // @[core.scala:814:29] wire [63:0] fast_wakeup_1_bits_uop_exc_cause; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_bypassable; // @[core.scala:814:29] wire [4:0] fast_wakeup_1_bits_uop_mem_cmd; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_mem_size; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_mem_signed; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_fence; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_fencei; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_amo; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_uses_ldq; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_uses_stq; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_is_unique; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_uop_ldst; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_uop_lrs1; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_uop_lrs2; // @[core.scala:814:29] wire [5:0] fast_wakeup_1_bits_uop_lrs3; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_ldst_val; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_dst_rtype; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_frs3_en; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_fp_val; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_fp_single; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:814:29] wire fast_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:814:29] wire [1:0] fast_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:814:29] wire slow_wakeup_1_valid; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_uopc; // @[core.scala:815:29] wire [31:0] slow_wakeup_1_bits_uop_inst; // @[core.scala:815:29] wire [31:0] slow_wakeup_1_bits_uop_debug_inst; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_rvc; // @[core.scala:815:29] wire [39:0] slow_wakeup_1_bits_uop_debug_pc; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_uop_iq_type; // @[core.scala:815:29] wire [9:0] slow_wakeup_1_bits_uop_fu_code; // @[core.scala:815:29] wire [3:0] slow_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:815:29] wire [2:0] slow_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_iw_state; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_br; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_jalr; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_jal; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_sfb; // @[core.scala:815:29] wire [15:0] slow_wakeup_1_bits_uop_br_mask; // @[core.scala:815:29] wire [3:0] slow_wakeup_1_bits_uop_br_tag; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_uop_ftq_idx; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_edge_inst; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_uop_pc_lob; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_taken; // @[core.scala:815:29] wire [19:0] slow_wakeup_1_bits_uop_imm_packed; // @[core.scala:815:29] wire [11:0] slow_wakeup_1_bits_uop_csr_addr; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_rob_idx; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_uop_ldq_idx; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_uop_stq_idx; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_rxq_idx; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_pdst; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_prs1; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_prs2; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_prs3; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_uop_ppred; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_prs1_busy; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_prs2_busy; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_prs3_busy; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ppred_busy; // @[core.scala:815:29] wire [6:0] slow_wakeup_1_bits_uop_stale_pdst; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_exception; // @[core.scala:815:29] wire [63:0] slow_wakeup_1_bits_uop_exc_cause; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_bypassable; // @[core.scala:815:29] wire [4:0] slow_wakeup_1_bits_uop_mem_cmd; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_mem_size; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_mem_signed; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_fence; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_fencei; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_amo; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_uses_ldq; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_uses_stq; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_is_unique; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_uop_ldst; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_uop_lrs1; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_uop_lrs2; // @[core.scala:815:29] wire [5:0] slow_wakeup_1_bits_uop_lrs3; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_ldst_val; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_dst_rtype; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_frs3_en; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_fp_val; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_fp_single; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:815:29] wire slow_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:815:29] wire [1:0] slow_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:815:29] wire fast_wakeup_2_valid; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_uopc; // @[core.scala:814:29] wire [31:0] fast_wakeup_2_bits_uop_inst; // @[core.scala:814:29] wire [31:0] fast_wakeup_2_bits_uop_debug_inst; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_rvc; // @[core.scala:814:29] wire [39:0] fast_wakeup_2_bits_uop_debug_pc; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_uop_iq_type; // @[core.scala:814:29] wire [9:0] fast_wakeup_2_bits_uop_fu_code; // @[core.scala:814:29] wire [3:0] fast_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:814:29] wire [2:0] fast_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_iw_state; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_br; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_jalr; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_jal; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_sfb; // @[core.scala:814:29] wire [15:0] fast_wakeup_2_bits_uop_br_mask; // @[core.scala:814:29] wire [3:0] fast_wakeup_2_bits_uop_br_tag; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_uop_ftq_idx; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_edge_inst; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_uop_pc_lob; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_taken; // @[core.scala:814:29] wire [19:0] fast_wakeup_2_bits_uop_imm_packed; // @[core.scala:814:29] wire [11:0] fast_wakeup_2_bits_uop_csr_addr; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_rob_idx; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_uop_ldq_idx; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_uop_stq_idx; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_rxq_idx; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_pdst; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_prs1; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_prs2; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_prs3; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_uop_ppred; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_prs1_busy; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_prs2_busy; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_prs3_busy; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ppred_busy; // @[core.scala:814:29] wire [6:0] fast_wakeup_2_bits_uop_stale_pdst; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_exception; // @[core.scala:814:29] wire [63:0] fast_wakeup_2_bits_uop_exc_cause; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_bypassable; // @[core.scala:814:29] wire [4:0] fast_wakeup_2_bits_uop_mem_cmd; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_mem_size; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_mem_signed; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_fence; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_fencei; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_amo; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_uses_ldq; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_uses_stq; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_is_unique; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_uop_ldst; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_uop_lrs1; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_uop_lrs2; // @[core.scala:814:29] wire [5:0] fast_wakeup_2_bits_uop_lrs3; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_ldst_val; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_dst_rtype; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_frs3_en; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_fp_val; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_fp_single; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:814:29] wire fast_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:814:29] wire [1:0] fast_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:814:29] wire slow_wakeup_2_valid; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_uopc; // @[core.scala:815:29] wire [31:0] slow_wakeup_2_bits_uop_inst; // @[core.scala:815:29] wire [31:0] slow_wakeup_2_bits_uop_debug_inst; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_rvc; // @[core.scala:815:29] wire [39:0] slow_wakeup_2_bits_uop_debug_pc; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_uop_iq_type; // @[core.scala:815:29] wire [9:0] slow_wakeup_2_bits_uop_fu_code; // @[core.scala:815:29] wire [3:0] slow_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:815:29] wire [2:0] slow_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_iw_state; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_br; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_jalr; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_jal; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_sfb; // @[core.scala:815:29] wire [15:0] slow_wakeup_2_bits_uop_br_mask; // @[core.scala:815:29] wire [3:0] slow_wakeup_2_bits_uop_br_tag; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_uop_ftq_idx; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_edge_inst; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_uop_pc_lob; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_taken; // @[core.scala:815:29] wire [19:0] slow_wakeup_2_bits_uop_imm_packed; // @[core.scala:815:29] wire [11:0] slow_wakeup_2_bits_uop_csr_addr; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_rob_idx; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_uop_ldq_idx; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_uop_stq_idx; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_rxq_idx; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_pdst; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_prs1; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_prs2; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_prs3; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_uop_ppred; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_prs1_busy; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_prs2_busy; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_prs3_busy; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ppred_busy; // @[core.scala:815:29] wire [6:0] slow_wakeup_2_bits_uop_stale_pdst; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_exception; // @[core.scala:815:29] wire [63:0] slow_wakeup_2_bits_uop_exc_cause; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_bypassable; // @[core.scala:815:29] wire [4:0] slow_wakeup_2_bits_uop_mem_cmd; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_mem_size; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_mem_signed; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_fence; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_fencei; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_amo; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_uses_ldq; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_uses_stq; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_is_unique; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_uop_ldst; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_uop_lrs1; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_uop_lrs2; // @[core.scala:815:29] wire [5:0] slow_wakeup_2_bits_uop_lrs3; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_ldst_val; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_dst_rtype; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_frs3_en; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_fp_val; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_fp_single; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:815:29] wire slow_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:815:29] wire [1:0] slow_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:815:29] wire [3:0] int_iss_wakeups_0_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_0_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_0_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_0_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_0_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_0_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_0_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_0_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_0_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_0_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_0_bits_fflags_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_0_bits_fflags_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_0_bits_fflags_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_0_bits_fflags_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_0_bits_fflags_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_0_bits_fflags_bits_flags; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_fflags_valid; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_0_bits_data; // @[core.scala:147:30] wire int_iss_wakeups_0_bits_predicated; // @[core.scala:147:30] wire int_iss_wakeups_0_valid; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_1_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_1_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_1_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_1_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_1_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_1_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_1_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_1_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_1_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_1_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_1_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_1_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_1_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_1_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:147:30] wire int_iss_wakeups_1_valid; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_2_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_2_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_2_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_2_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_2_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_2_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_2_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_2_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_2_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_2_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_2_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_2_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_2_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_2_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_2_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_2_bits_uop_debug_tsrc; // @[core.scala:147:30] wire int_iss_wakeups_2_valid; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_3_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_3_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_3_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_3_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_3_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_3_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_3_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_3_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_3_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_3_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_3_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_3_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_3_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_3_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_3_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_3_bits_uop_debug_tsrc; // @[core.scala:147:30] wire int_iss_wakeups_3_valid; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_4_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_4_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_4_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_4_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_4_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_4_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_4_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_4_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_4_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_4_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_4_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_4_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_4_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_4_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_4_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_4_bits_uop_debug_tsrc; // @[core.scala:147:30] wire int_iss_wakeups_4_valid; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_5_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_5_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_5_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_5_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_5_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_5_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_5_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_5_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_5_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_5_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_5_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_5_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_5_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_5_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_5_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_5_bits_uop_debug_tsrc; // @[core.scala:147:30] wire int_iss_wakeups_5_valid; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_6_bits_uop_ctrl_br_type; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_ctrl_op1_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_uop_ctrl_op2_sel; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_uop_ctrl_imm_sel; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_uop_ctrl_op_fcn; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ctrl_is_load; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ctrl_is_sta; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ctrl_is_std; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_uopc; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_6_bits_uop_inst; // @[core.scala:147:30] wire [31:0] int_iss_wakeups_6_bits_uop_debug_inst; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_rvc; // @[core.scala:147:30] wire [39:0] int_iss_wakeups_6_bits_uop_debug_pc; // @[core.scala:147:30] wire [2:0] int_iss_wakeups_6_bits_uop_iq_type; // @[core.scala:147:30] wire [9:0] int_iss_wakeups_6_bits_uop_fu_code; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_iw_state; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_iw_p1_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_iw_p2_poisoned; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_br; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_jalr; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_jal; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_sfb; // @[core.scala:147:30] wire [15:0] int_iss_wakeups_6_bits_uop_br_mask; // @[core.scala:147:30] wire [3:0] int_iss_wakeups_6_bits_uop_br_tag; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_uop_ftq_idx; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_edge_inst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_uop_pc_lob; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_taken; // @[core.scala:147:30] wire [19:0] int_iss_wakeups_6_bits_uop_imm_packed; // @[core.scala:147:30] wire [11:0] int_iss_wakeups_6_bits_uop_csr_addr; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_rob_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_uop_ldq_idx; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_uop_stq_idx; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_rxq_idx; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_pdst; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_prs1; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_prs2; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_prs3; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_uop_ppred; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_prs1_busy; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_prs2_busy; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_prs3_busy; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ppred_busy; // @[core.scala:147:30] wire [6:0] int_iss_wakeups_6_bits_uop_stale_pdst; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_exception; // @[core.scala:147:30] wire [63:0] int_iss_wakeups_6_bits_uop_exc_cause; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_bypassable; // @[core.scala:147:30] wire [4:0] int_iss_wakeups_6_bits_uop_mem_cmd; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_mem_size; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_mem_signed; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_fence; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_fencei; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_amo; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_uses_ldq; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_uses_stq; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_sys_pc2epc; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_is_unique; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_flush_on_commit; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ldst_is_rs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_uop_ldst; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_uop_lrs1; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_uop_lrs2; // @[core.scala:147:30] wire [5:0] int_iss_wakeups_6_bits_uop_lrs3; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_ldst_val; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_dst_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_lrs1_rtype; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_lrs2_rtype; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_frs3_en; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_fp_val; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_fp_single; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_xcpt_pf_if; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_xcpt_ae_if; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_xcpt_ma_if; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_bp_debug_if; // @[core.scala:147:30] wire int_iss_wakeups_6_bits_uop_bp_xcpt_if; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_debug_fsrc; // @[core.scala:147:30] wire [1:0] int_iss_wakeups_6_bits_uop_debug_tsrc; // @[core.scala:147:30] wire int_iss_wakeups_6_valid; // @[core.scala:147:30] wire _int_ren_wakeups_0_valid_T_2; // @[core.scala:798:52] wire [3:0] int_ren_wakeups_0_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_0_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_0_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_0_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_0_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_0_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_0_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_0_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_0_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_0_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_0_bits_fflags_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_0_bits_fflags_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_0_bits_fflags_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_0_bits_fflags_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_0_bits_fflags_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_0_bits_fflags_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_0_bits_fflags_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_0_bits_fflags_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_0_bits_fflags_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_0_bits_fflags_bits_uop_debug_tsrc; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_0_bits_fflags_bits_flags; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_fflags_valid; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_0_bits_data; // @[core.scala:148:30] wire int_ren_wakeups_0_bits_predicated; // @[core.scala:148:30] wire int_ren_wakeups_0_valid; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_1_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_1_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_1_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_1_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_1_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_1_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_1_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_1_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_1_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_1_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_1_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_1_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_1_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_1_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:148:30] wire int_ren_wakeups_1_valid; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_2_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_2_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_2_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_2_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_2_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_2_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_2_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_2_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_2_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_2_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_2_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_2_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_2_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_2_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_2_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_2_bits_uop_debug_tsrc; // @[core.scala:148:30] wire int_ren_wakeups_2_valid; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_3_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_3_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_3_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_3_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_3_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_3_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_3_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_3_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_3_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_3_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_3_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_3_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_3_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_3_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_3_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_3_bits_uop_debug_tsrc; // @[core.scala:148:30] wire int_ren_wakeups_3_valid; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_4_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_4_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_4_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_4_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_4_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_4_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_4_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_4_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_4_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_4_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_4_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_4_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_4_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_4_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_4_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_4_bits_uop_debug_tsrc; // @[core.scala:148:30] wire int_ren_wakeups_4_valid; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_5_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_5_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_5_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_5_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_5_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_5_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_5_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_5_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_5_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_5_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_5_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_5_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_5_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_5_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_5_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_5_bits_uop_debug_tsrc; // @[core.scala:148:30] wire int_ren_wakeups_5_valid; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_6_bits_uop_ctrl_br_type; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_ctrl_op1_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_uop_ctrl_op2_sel; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_uop_ctrl_imm_sel; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_uop_ctrl_op_fcn; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ctrl_is_load; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ctrl_is_sta; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ctrl_is_std; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_uopc; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_6_bits_uop_inst; // @[core.scala:148:30] wire [31:0] int_ren_wakeups_6_bits_uop_debug_inst; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_rvc; // @[core.scala:148:30] wire [39:0] int_ren_wakeups_6_bits_uop_debug_pc; // @[core.scala:148:30] wire [2:0] int_ren_wakeups_6_bits_uop_iq_type; // @[core.scala:148:30] wire [9:0] int_ren_wakeups_6_bits_uop_fu_code; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_iw_state; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_iw_p1_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_iw_p2_poisoned; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_br; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_jalr; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_jal; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_sfb; // @[core.scala:148:30] wire [15:0] int_ren_wakeups_6_bits_uop_br_mask; // @[core.scala:148:30] wire [3:0] int_ren_wakeups_6_bits_uop_br_tag; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_uop_ftq_idx; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_edge_inst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_uop_pc_lob; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_taken; // @[core.scala:148:30] wire [19:0] int_ren_wakeups_6_bits_uop_imm_packed; // @[core.scala:148:30] wire [11:0] int_ren_wakeups_6_bits_uop_csr_addr; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_rob_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_uop_ldq_idx; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_uop_stq_idx; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_rxq_idx; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_pdst; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_prs1; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_prs2; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_prs3; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_uop_ppred; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_prs1_busy; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_prs2_busy; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_prs3_busy; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ppred_busy; // @[core.scala:148:30] wire [6:0] int_ren_wakeups_6_bits_uop_stale_pdst; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_exception; // @[core.scala:148:30] wire [63:0] int_ren_wakeups_6_bits_uop_exc_cause; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_bypassable; // @[core.scala:148:30] wire [4:0] int_ren_wakeups_6_bits_uop_mem_cmd; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_mem_size; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_mem_signed; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_fence; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_fencei; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_amo; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_uses_ldq; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_uses_stq; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_sys_pc2epc; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_is_unique; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_flush_on_commit; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ldst_is_rs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_uop_ldst; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_uop_lrs1; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_uop_lrs2; // @[core.scala:148:30] wire [5:0] int_ren_wakeups_6_bits_uop_lrs3; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_ldst_val; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_dst_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_lrs1_rtype; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_lrs2_rtype; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_frs3_en; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_fp_val; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_fp_single; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_xcpt_pf_if; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_xcpt_ae_if; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_xcpt_ma_if; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_bp_debug_if; // @[core.scala:148:30] wire int_ren_wakeups_6_bits_uop_bp_xcpt_if; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_debug_fsrc; // @[core.scala:148:30] wire [1:0] int_ren_wakeups_6_bits_uop_debug_tsrc; // @[core.scala:148:30] wire int_ren_wakeups_6_valid; // @[core.scala:148:30] wire [6:0] iss_uops_1_uopc; // @[core.scala:173:24] wire [31:0] iss_uops_1_inst; // @[core.scala:173:24] wire [31:0] iss_uops_1_debug_inst; // @[core.scala:173:24] wire iss_uops_1_is_rvc; // @[core.scala:173:24] wire [39:0] iss_uops_1_debug_pc; // @[core.scala:173:24] wire [2:0] iss_uops_1_iq_type; // @[core.scala:173:24] wire [9:0] iss_uops_1_fu_code; // @[core.scala:173:24] wire [3:0] iss_uops_1_ctrl_br_type; // @[core.scala:173:24] wire [1:0] iss_uops_1_ctrl_op1_sel; // @[core.scala:173:24] wire [2:0] iss_uops_1_ctrl_op2_sel; // @[core.scala:173:24] wire [2:0] iss_uops_1_ctrl_imm_sel; // @[core.scala:173:24] wire [4:0] iss_uops_1_ctrl_op_fcn; // @[core.scala:173:24] wire iss_uops_1_ctrl_fcn_dw; // @[core.scala:173:24] wire [2:0] iss_uops_1_ctrl_csr_cmd; // @[core.scala:173:24] wire iss_uops_1_ctrl_is_load; // @[core.scala:173:24] wire iss_uops_1_ctrl_is_sta; // @[core.scala:173:24] wire iss_uops_1_ctrl_is_std; // @[core.scala:173:24] wire [1:0] iss_uops_1_iw_state; // @[core.scala:173:24] wire iss_uops_1_iw_p1_poisoned; // @[core.scala:173:24] wire iss_uops_1_iw_p2_poisoned; // @[core.scala:173:24] wire iss_uops_1_is_br; // @[core.scala:173:24] wire iss_uops_1_is_jalr; // @[core.scala:173:24] wire iss_uops_1_is_jal; // @[core.scala:173:24] wire iss_uops_1_is_sfb; // @[core.scala:173:24] wire [15:0] iss_uops_1_br_mask; // @[core.scala:173:24] wire [3:0] iss_uops_1_br_tag; // @[core.scala:173:24] wire [4:0] iss_uops_1_ftq_idx; // @[core.scala:173:24] wire iss_uops_1_edge_inst; // @[core.scala:173:24] wire [5:0] iss_uops_1_pc_lob; // @[core.scala:173:24] wire iss_uops_1_taken; // @[core.scala:173:24] wire [19:0] iss_uops_1_imm_packed; // @[core.scala:173:24] wire [11:0] iss_uops_1_csr_addr; // @[core.scala:173:24] wire [6:0] iss_uops_1_rob_idx; // @[core.scala:173:24] wire [4:0] iss_uops_1_ldq_idx; // @[core.scala:173:24] wire [4:0] iss_uops_1_stq_idx; // @[core.scala:173:24] wire [1:0] iss_uops_1_rxq_idx; // @[core.scala:173:24] wire [6:0] iss_uops_1_pdst; // @[core.scala:173:24] wire [6:0] iss_uops_1_prs1; // @[core.scala:173:24] wire [6:0] iss_uops_1_prs2; // @[core.scala:173:24] wire [6:0] iss_uops_1_prs3; // @[core.scala:173:24] wire [4:0] iss_uops_1_ppred; // @[core.scala:173:24] wire iss_uops_1_prs1_busy; // @[core.scala:173:24] wire iss_uops_1_prs2_busy; // @[core.scala:173:24] wire iss_uops_1_prs3_busy; // @[core.scala:173:24] wire iss_uops_1_ppred_busy; // @[core.scala:173:24] wire [6:0] iss_uops_1_stale_pdst; // @[core.scala:173:24] wire iss_uops_1_exception; // @[core.scala:173:24] wire [63:0] iss_uops_1_exc_cause; // @[core.scala:173:24] wire iss_uops_1_bypassable; // @[core.scala:173:24] wire [4:0] iss_uops_1_mem_cmd; // @[core.scala:173:24] wire [1:0] iss_uops_1_mem_size; // @[core.scala:173:24] wire iss_uops_1_mem_signed; // @[core.scala:173:24] wire iss_uops_1_is_fence; // @[core.scala:173:24] wire iss_uops_1_is_fencei; // @[core.scala:173:24] wire iss_uops_1_is_amo; // @[core.scala:173:24] wire iss_uops_1_uses_ldq; // @[core.scala:173:24] wire iss_uops_1_uses_stq; // @[core.scala:173:24] wire iss_uops_1_is_sys_pc2epc; // @[core.scala:173:24] wire iss_uops_1_is_unique; // @[core.scala:173:24] wire iss_uops_1_flush_on_commit; // @[core.scala:173:24] wire iss_uops_1_ldst_is_rs1; // @[core.scala:173:24] wire [5:0] iss_uops_1_ldst; // @[core.scala:173:24] wire [5:0] iss_uops_1_lrs1; // @[core.scala:173:24] wire [5:0] iss_uops_1_lrs2; // @[core.scala:173:24] wire [5:0] iss_uops_1_lrs3; // @[core.scala:173:24] wire iss_uops_1_ldst_val; // @[core.scala:173:24] wire [1:0] iss_uops_1_dst_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_1_lrs1_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_1_lrs2_rtype; // @[core.scala:173:24] wire iss_uops_1_frs3_en; // @[core.scala:173:24] wire iss_uops_1_fp_val; // @[core.scala:173:24] wire iss_uops_1_fp_single; // @[core.scala:173:24] wire iss_uops_1_xcpt_pf_if; // @[core.scala:173:24] wire iss_uops_1_xcpt_ae_if; // @[core.scala:173:24] wire iss_uops_1_xcpt_ma_if; // @[core.scala:173:24] wire iss_uops_1_bp_debug_if; // @[core.scala:173:24] wire iss_uops_1_bp_xcpt_if; // @[core.scala:173:24] wire [1:0] iss_uops_1_debug_fsrc; // @[core.scala:173:24] wire [1:0] iss_uops_1_debug_tsrc; // @[core.scala:173:24] wire [3:0] pred_wakeup_bits_uop_ctrl_br_type; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ctrl_is_load; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ctrl_is_std; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_uopc; // @[core.scala:149:26] wire [31:0] pred_wakeup_bits_uop_inst; // @[core.scala:149:26] wire [31:0] pred_wakeup_bits_uop_debug_inst; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_rvc; // @[core.scala:149:26] wire [39:0] pred_wakeup_bits_uop_debug_pc; // @[core.scala:149:26] wire [2:0] pred_wakeup_bits_uop_iq_type; // @[core.scala:149:26] wire [9:0] pred_wakeup_bits_uop_fu_code; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_iw_state; // @[core.scala:149:26] wire pred_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:149:26] wire pred_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_br; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_jalr; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_jal; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_sfb; // @[core.scala:149:26] wire [15:0] pred_wakeup_bits_uop_br_mask; // @[core.scala:149:26] wire [3:0] pred_wakeup_bits_uop_br_tag; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_uop_ftq_idx; // @[core.scala:149:26] wire pred_wakeup_bits_uop_edge_inst; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_uop_pc_lob; // @[core.scala:149:26] wire pred_wakeup_bits_uop_taken; // @[core.scala:149:26] wire [19:0] pred_wakeup_bits_uop_imm_packed; // @[core.scala:149:26] wire [11:0] pred_wakeup_bits_uop_csr_addr; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_rob_idx; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_uop_ldq_idx; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_uop_stq_idx; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_rxq_idx; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_pdst; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_prs1; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_prs2; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_prs3; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_uop_ppred; // @[core.scala:149:26] wire pred_wakeup_bits_uop_prs1_busy; // @[core.scala:149:26] wire pred_wakeup_bits_uop_prs2_busy; // @[core.scala:149:26] wire pred_wakeup_bits_uop_prs3_busy; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ppred_busy; // @[core.scala:149:26] wire [6:0] pred_wakeup_bits_uop_stale_pdst; // @[core.scala:149:26] wire pred_wakeup_bits_uop_exception; // @[core.scala:149:26] wire [63:0] pred_wakeup_bits_uop_exc_cause; // @[core.scala:149:26] wire pred_wakeup_bits_uop_bypassable; // @[core.scala:149:26] wire [4:0] pred_wakeup_bits_uop_mem_cmd; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_mem_size; // @[core.scala:149:26] wire pred_wakeup_bits_uop_mem_signed; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_fence; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_fencei; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_amo; // @[core.scala:149:26] wire pred_wakeup_bits_uop_uses_ldq; // @[core.scala:149:26] wire pred_wakeup_bits_uop_uses_stq; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:149:26] wire pred_wakeup_bits_uop_is_unique; // @[core.scala:149:26] wire pred_wakeup_bits_uop_flush_on_commit; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_uop_ldst; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_uop_lrs1; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_uop_lrs2; // @[core.scala:149:26] wire [5:0] pred_wakeup_bits_uop_lrs3; // @[core.scala:149:26] wire pred_wakeup_bits_uop_ldst_val; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_dst_rtype; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_lrs1_rtype; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_lrs2_rtype; // @[core.scala:149:26] wire pred_wakeup_bits_uop_frs3_en; // @[core.scala:149:26] wire pred_wakeup_bits_uop_fp_val; // @[core.scala:149:26] wire pred_wakeup_bits_uop_fp_single; // @[core.scala:149:26] wire pred_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:149:26] wire pred_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:149:26] wire pred_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:149:26] wire pred_wakeup_bits_uop_bp_debug_if; // @[core.scala:149:26] wire pred_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_debug_fsrc; // @[core.scala:149:26] wire [1:0] pred_wakeup_bits_uop_debug_tsrc; // @[core.scala:149:26] wire _dec_valids_0_T_3; // @[core.scala:508:97] wire _dec_valids_1_T_3; // @[core.scala:508:97] wire _dec_valids_2_T_3; // @[core.scala:508:97] wire dec_valids_0; // @[core.scala:157:24] wire dec_valids_1; // @[core.scala:157:24] wire dec_valids_2; // @[core.scala:157:24] wire [6:0] dec_uops_0_uopc; // @[core.scala:158:24] wire [31:0] dec_uops_0_inst; // @[core.scala:158:24] wire [31:0] dec_uops_0_debug_inst; // @[core.scala:158:24] wire dec_uops_0_is_rvc; // @[core.scala:158:24] wire [39:0] dec_uops_0_debug_pc; // @[core.scala:158:24] wire [2:0] dec_uops_0_iq_type; // @[core.scala:158:24] wire [9:0] dec_uops_0_fu_code; // @[core.scala:158:24] wire dec_uops_0_is_br; // @[core.scala:158:24] wire dec_uops_0_is_jalr; // @[core.scala:158:24] wire dec_uops_0_is_jal; // @[core.scala:158:24] wire dec_uops_0_is_sfb; // @[core.scala:158:24] wire [15:0] dec_uops_0_br_mask; // @[core.scala:158:24] wire [3:0] dec_uops_0_br_tag; // @[core.scala:158:24] wire [4:0] dec_uops_0_ftq_idx; // @[core.scala:158:24] wire dec_uops_0_edge_inst; // @[core.scala:158:24] wire [5:0] dec_uops_0_pc_lob; // @[core.scala:158:24] wire dec_uops_0_taken; // @[core.scala:158:24] wire [19:0] dec_uops_0_imm_packed; // @[core.scala:158:24] wire dec_uops_0_exception; // @[core.scala:158:24] wire [63:0] dec_uops_0_exc_cause; // @[core.scala:158:24] wire dec_uops_0_bypassable; // @[core.scala:158:24] wire [4:0] dec_uops_0_mem_cmd; // @[core.scala:158:24] wire [1:0] dec_uops_0_mem_size; // @[core.scala:158:24] wire dec_uops_0_mem_signed; // @[core.scala:158:24] wire dec_uops_0_is_fence; // @[core.scala:158:24] wire dec_uops_0_is_fencei; // @[core.scala:158:24] wire dec_uops_0_is_amo; // @[core.scala:158:24] wire dec_uops_0_uses_ldq; // @[core.scala:158:24] wire dec_uops_0_uses_stq; // @[core.scala:158:24] wire dec_uops_0_is_sys_pc2epc; // @[core.scala:158:24] wire dec_uops_0_is_unique; // @[core.scala:158:24] wire dec_uops_0_flush_on_commit; // @[core.scala:158:24] wire [5:0] dec_uops_0_ldst; // @[core.scala:158:24] wire [5:0] dec_uops_0_lrs1; // @[core.scala:158:24] wire [5:0] dec_uops_0_lrs2; // @[core.scala:158:24] wire [5:0] dec_uops_0_lrs3; // @[core.scala:158:24] wire dec_uops_0_ldst_val; // @[core.scala:158:24] wire [1:0] dec_uops_0_dst_rtype; // @[core.scala:158:24] wire [1:0] dec_uops_0_lrs1_rtype; // @[core.scala:158:24] wire [1:0] dec_uops_0_lrs2_rtype; // @[core.scala:158:24] wire dec_uops_0_frs3_en; // @[core.scala:158:24] wire dec_uops_0_fp_val; // @[core.scala:158:24] wire dec_uops_0_fp_single; // @[core.scala:158:24] wire dec_uops_0_xcpt_pf_if; // @[core.scala:158:24] wire dec_uops_0_xcpt_ae_if; // @[core.scala:158:24] wire dec_uops_0_bp_debug_if; // @[core.scala:158:24] wire dec_uops_0_bp_xcpt_if; // @[core.scala:158:24] wire [1:0] dec_uops_0_debug_fsrc; // @[core.scala:158:24] wire [6:0] dec_uops_1_uopc; // @[core.scala:158:24] wire [31:0] dec_uops_1_inst; // @[core.scala:158:24] wire [31:0] dec_uops_1_debug_inst; // @[core.scala:158:24] wire dec_uops_1_is_rvc; // @[core.scala:158:24] wire [39:0] dec_uops_1_debug_pc; // @[core.scala:158:24] wire [2:0] dec_uops_1_iq_type; // @[core.scala:158:24] wire [9:0] dec_uops_1_fu_code; // @[core.scala:158:24] wire dec_uops_1_is_br; // @[core.scala:158:24] wire dec_uops_1_is_jalr; // @[core.scala:158:24] wire dec_uops_1_is_jal; // @[core.scala:158:24] wire dec_uops_1_is_sfb; // @[core.scala:158:24] wire [15:0] dec_uops_1_br_mask; // @[core.scala:158:24] wire [3:0] dec_uops_1_br_tag; // @[core.scala:158:24] wire [4:0] dec_uops_1_ftq_idx; // @[core.scala:158:24] wire dec_uops_1_edge_inst; // @[core.scala:158:24] wire [5:0] dec_uops_1_pc_lob; // @[core.scala:158:24] wire dec_uops_1_taken; // @[core.scala:158:24] wire [19:0] dec_uops_1_imm_packed; // @[core.scala:158:24] wire dec_uops_1_exception; // @[core.scala:158:24] wire [63:0] dec_uops_1_exc_cause; // @[core.scala:158:24] wire dec_uops_1_bypassable; // @[core.scala:158:24] wire [4:0] dec_uops_1_mem_cmd; // @[core.scala:158:24] wire [1:0] dec_uops_1_mem_size; // @[core.scala:158:24] wire dec_uops_1_mem_signed; // @[core.scala:158:24] wire dec_uops_1_is_fence; // @[core.scala:158:24] wire dec_uops_1_is_fencei; // @[core.scala:158:24] wire dec_uops_1_is_amo; // @[core.scala:158:24] wire dec_uops_1_uses_ldq; // @[core.scala:158:24] wire dec_uops_1_uses_stq; // @[core.scala:158:24] wire dec_uops_1_is_sys_pc2epc; // @[core.scala:158:24] wire dec_uops_1_is_unique; // @[core.scala:158:24] wire dec_uops_1_flush_on_commit; // @[core.scala:158:24] wire [5:0] dec_uops_1_ldst; // @[core.scala:158:24] wire [5:0] dec_uops_1_lrs1; // @[core.scala:158:24] wire [5:0] dec_uops_1_lrs2; // @[core.scala:158:24] wire [5:0] dec_uops_1_lrs3; // @[core.scala:158:24] wire dec_uops_1_ldst_val; // @[core.scala:158:24] wire [1:0] dec_uops_1_dst_rtype; // @[core.scala:158:24] wire [1:0] dec_uops_1_lrs1_rtype; // @[core.scala:158:24] wire [1:0] dec_uops_1_lrs2_rtype; // @[core.scala:158:24] wire dec_uops_1_frs3_en; // @[core.scala:158:24] wire dec_uops_1_fp_val; // @[core.scala:158:24] wire dec_uops_1_fp_single; // @[core.scala:158:24] wire dec_uops_1_xcpt_pf_if; // @[core.scala:158:24] wire dec_uops_1_xcpt_ae_if; // @[core.scala:158:24] wire dec_uops_1_bp_debug_if; // @[core.scala:158:24] wire dec_uops_1_bp_xcpt_if; // @[core.scala:158:24] wire [1:0] dec_uops_1_debug_fsrc; // @[core.scala:158:24] wire [6:0] dec_uops_2_uopc; // @[core.scala:158:24] wire [31:0] dec_uops_2_inst; // @[core.scala:158:24] wire [31:0] dec_uops_2_debug_inst; // @[core.scala:158:24] wire dec_uops_2_is_rvc; // @[core.scala:158:24] wire [39:0] dec_uops_2_debug_pc; // @[core.scala:158:24] wire [2:0] dec_uops_2_iq_type; // @[core.scala:158:24] wire [9:0] dec_uops_2_fu_code; // @[core.scala:158:24] wire dec_uops_2_is_br; // @[core.scala:158:24] wire dec_uops_2_is_jalr; // @[core.scala:158:24] wire dec_uops_2_is_jal; // @[core.scala:158:24] wire dec_uops_2_is_sfb; // @[core.scala:158:24] wire [15:0] dec_uops_2_br_mask; // @[core.scala:158:24] wire [3:0] dec_uops_2_br_tag; // @[core.scala:158:24] wire [4:0] dec_uops_2_ftq_idx; // @[core.scala:158:24] wire dec_uops_2_edge_inst; // @[core.scala:158:24] wire [5:0] dec_uops_2_pc_lob; // @[core.scala:158:24] wire dec_uops_2_taken; // @[core.scala:158:24] wire [19:0] dec_uops_2_imm_packed; // @[core.scala:158:24] wire dec_uops_2_exception; // @[core.scala:158:24] wire [63:0] dec_uops_2_exc_cause; // @[core.scala:158:24] wire dec_uops_2_bypassable; // @[core.scala:158:24] wire [4:0] dec_uops_2_mem_cmd; // @[core.scala:158:24] wire [1:0] dec_uops_2_mem_size; // @[core.scala:158:24] wire dec_uops_2_mem_signed; // @[core.scala:158:24] wire dec_uops_2_is_fence; // @[core.scala:158:24] wire dec_uops_2_is_fencei; // @[core.scala:158:24] wire dec_uops_2_is_amo; // @[core.scala:158:24] wire dec_uops_2_uses_ldq; // @[core.scala:158:24] wire dec_uops_2_uses_stq; // @[core.scala:158:24] wire dec_uops_2_is_sys_pc2epc; // @[core.scala:158:24] wire dec_uops_2_is_unique; // @[core.scala:158:24] wire dec_uops_2_flush_on_commit; // @[core.scala:158:24] wire [5:0] dec_uops_2_ldst; // @[core.scala:158:24] wire [5:0] dec_uops_2_lrs1; // @[core.scala:158:24] wire [5:0] dec_uops_2_lrs2; // @[core.scala:158:24] wire [5:0] dec_uops_2_lrs3; // @[core.scala:158:24] wire dec_uops_2_ldst_val; // @[core.scala:158:24] wire [1:0] dec_uops_2_dst_rtype; // @[core.scala:158:24] wire [1:0] dec_uops_2_lrs1_rtype; // @[core.scala:158:24] wire [1:0] dec_uops_2_lrs2_rtype; // @[core.scala:158:24] wire dec_uops_2_frs3_en; // @[core.scala:158:24] wire dec_uops_2_fp_val; // @[core.scala:158:24] wire dec_uops_2_fp_single; // @[core.scala:158:24] wire dec_uops_2_xcpt_pf_if; // @[core.scala:158:24] wire dec_uops_2_xcpt_ae_if; // @[core.scala:158:24] wire dec_uops_2_bp_debug_if; // @[core.scala:158:24] wire dec_uops_2_bp_xcpt_if; // @[core.scala:158:24] wire [1:0] dec_uops_2_debug_fsrc; // @[core.scala:158:24] wire dec_fire_0; // @[core.scala:159:24] wire dec_fire_1; // @[core.scala:159:24] wire dec_fire_2; // @[core.scala:159:24] assign dec_ready = dec_fire_2; // @[core.scala:159:24, :161:24] assign io_ifu_fetchpacket_ready_0 = dec_ready; // @[core.scala:51:7, :161:24] wire dec_xcpts_0; // @[core.scala:162:24] wire dec_xcpts_1; // @[core.scala:162:24] wire dec_xcpts_2; // @[core.scala:162:24] wire _ren_stalls_0_T_1; // @[core.scala:671:63] wire _ren_stalls_1_T_1; // @[core.scala:671:63] wire _ren_stalls_2_T_1; // @[core.scala:671:63] wire ren_stalls_0; // @[core.scala:163:24] wire ren_stalls_1; // @[core.scala:163:24] wire ren_stalls_2; // @[core.scala:163:24] wire dis_prior_slot_valid_1 = dis_valids_0; // @[core.scala:166:24, :683:71] wire dis_valids_1; // @[core.scala:166:24] wire dis_valids_2; // @[core.scala:166:24] assign io_lsu_dis_uops_0_bits_uopc_0 = dis_uops_0_uopc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_inst_0 = dis_uops_0_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_debug_inst_0 = dis_uops_0_debug_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_rvc_0 = dis_uops_0_is_rvc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_debug_pc_0 = dis_uops_0_debug_pc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_iq_type_0 = dis_uops_0_iq_type; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_fu_code_0 = dis_uops_0_fu_code; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_br_type_0 = dis_uops_0_ctrl_br_type; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_op1_sel_0 = dis_uops_0_ctrl_op1_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_op2_sel_0 = dis_uops_0_ctrl_op2_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_imm_sel_0 = dis_uops_0_ctrl_imm_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_op_fcn_0 = dis_uops_0_ctrl_op_fcn; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_fcn_dw_0 = dis_uops_0_ctrl_fcn_dw; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_csr_cmd_0 = dis_uops_0_ctrl_csr_cmd; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_is_load_0 = dis_uops_0_ctrl_is_load; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_is_sta_0 = dis_uops_0_ctrl_is_sta; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ctrl_is_std_0 = dis_uops_0_ctrl_is_std; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_iw_state_0 = dis_uops_0_iw_state; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_iw_p1_poisoned_0 = dis_uops_0_iw_p1_poisoned; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_iw_p2_poisoned_0 = dis_uops_0_iw_p2_poisoned; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_br_0 = dis_uops_0_is_br; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_jalr_0 = dis_uops_0_is_jalr; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_jal_0 = dis_uops_0_is_jal; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_sfb_0 = dis_uops_0_is_sfb; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_br_mask_0 = dis_uops_0_br_mask; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_br_tag_0 = dis_uops_0_br_tag; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ftq_idx_0 = dis_uops_0_ftq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_edge_inst_0 = dis_uops_0_edge_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_pc_lob_0 = dis_uops_0_pc_lob; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_taken_0 = dis_uops_0_taken; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_imm_packed_0 = dis_uops_0_imm_packed; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_csr_addr_0 = dis_uops_0_csr_addr; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_rob_idx_0 = dis_uops_0_rob_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ldq_idx_0 = dis_uops_0_ldq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_stq_idx_0 = dis_uops_0_stq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_rxq_idx_0 = dis_uops_0_rxq_idx; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_0_pdst_T_3; // @[core.scala:659:28] assign io_lsu_dis_uops_0_bits_pdst_0 = dis_uops_0_pdst; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_0_prs1_T_3; // @[core.scala:654:28] assign io_lsu_dis_uops_0_bits_prs1_0 = dis_uops_0_prs1; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_0_prs2_T_1; // @[core.scala:656:28] assign io_lsu_dis_uops_0_bits_prs2_0 = dis_uops_0_prs2; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_prs3_0 = dis_uops_0_prs3; // @[core.scala:51:7, :167:24] wire _dis_uops_0_prs1_busy_T_4; // @[core.scala:664:85] assign io_lsu_dis_uops_0_bits_prs1_busy_0 = dis_uops_0_prs1_busy; // @[core.scala:51:7, :167:24] wire _dis_uops_0_prs2_busy_T_4; // @[core.scala:666:85] assign io_lsu_dis_uops_0_bits_prs2_busy_0 = dis_uops_0_prs2_busy; // @[core.scala:51:7, :167:24] wire _dis_uops_0_prs3_busy_T; // @[core.scala:668:46] assign io_lsu_dis_uops_0_bits_prs3_busy_0 = dis_uops_0_prs3_busy; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_0_stale_pdst_T_1; // @[core.scala:662:34] assign io_lsu_dis_uops_0_bits_stale_pdst_0 = dis_uops_0_stale_pdst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_exception_0 = dis_uops_0_exception; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_exc_cause_0 = dis_uops_0_exc_cause; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_bypassable_0 = dis_uops_0_bypassable; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_mem_cmd_0 = dis_uops_0_mem_cmd; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_mem_size_0 = dis_uops_0_mem_size; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_mem_signed_0 = dis_uops_0_mem_signed; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_fence_0 = dis_uops_0_is_fence; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_fencei_0 = dis_uops_0_is_fencei; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_amo_0 = dis_uops_0_is_amo; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_uses_ldq_0 = dis_uops_0_uses_ldq; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_uses_stq_0 = dis_uops_0_uses_stq; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_sys_pc2epc_0 = dis_uops_0_is_sys_pc2epc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_is_unique_0 = dis_uops_0_is_unique; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_flush_on_commit_0 = dis_uops_0_flush_on_commit; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ldst_is_rs1_0 = dis_uops_0_ldst_is_rs1; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ldst_0 = dis_uops_0_ldst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_lrs1_0 = dis_uops_0_lrs1; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_lrs2_0 = dis_uops_0_lrs2; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_lrs3_0 = dis_uops_0_lrs3; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_ldst_val_0 = dis_uops_0_ldst_val; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_dst_rtype_0 = dis_uops_0_dst_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_lrs1_rtype_0 = dis_uops_0_lrs1_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_lrs2_rtype_0 = dis_uops_0_lrs2_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_frs3_en_0 = dis_uops_0_frs3_en; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_fp_val_0 = dis_uops_0_fp_val; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_fp_single_0 = dis_uops_0_fp_single; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_xcpt_pf_if_0 = dis_uops_0_xcpt_pf_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_xcpt_ae_if_0 = dis_uops_0_xcpt_ae_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_xcpt_ma_if_0 = dis_uops_0_xcpt_ma_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_bp_debug_if_0 = dis_uops_0_bp_debug_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_bp_xcpt_if_0 = dis_uops_0_bp_xcpt_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_debug_fsrc_0 = dis_uops_0_debug_fsrc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_bits_debug_tsrc_0 = dis_uops_0_debug_tsrc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_uopc_0 = dis_uops_1_uopc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_inst_0 = dis_uops_1_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_debug_inst_0 = dis_uops_1_debug_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_rvc_0 = dis_uops_1_is_rvc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_debug_pc_0 = dis_uops_1_debug_pc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_iq_type_0 = dis_uops_1_iq_type; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_fu_code_0 = dis_uops_1_fu_code; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_br_type_0 = dis_uops_1_ctrl_br_type; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_op1_sel_0 = dis_uops_1_ctrl_op1_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_op2_sel_0 = dis_uops_1_ctrl_op2_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_imm_sel_0 = dis_uops_1_ctrl_imm_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_op_fcn_0 = dis_uops_1_ctrl_op_fcn; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_fcn_dw_0 = dis_uops_1_ctrl_fcn_dw; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_csr_cmd_0 = dis_uops_1_ctrl_csr_cmd; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_is_load_0 = dis_uops_1_ctrl_is_load; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_is_sta_0 = dis_uops_1_ctrl_is_sta; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ctrl_is_std_0 = dis_uops_1_ctrl_is_std; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_iw_state_0 = dis_uops_1_iw_state; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_iw_p1_poisoned_0 = dis_uops_1_iw_p1_poisoned; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_iw_p2_poisoned_0 = dis_uops_1_iw_p2_poisoned; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_br_0 = dis_uops_1_is_br; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_jalr_0 = dis_uops_1_is_jalr; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_jal_0 = dis_uops_1_is_jal; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_sfb_0 = dis_uops_1_is_sfb; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_br_mask_0 = dis_uops_1_br_mask; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_br_tag_0 = dis_uops_1_br_tag; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ftq_idx_0 = dis_uops_1_ftq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_edge_inst_0 = dis_uops_1_edge_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_pc_lob_0 = dis_uops_1_pc_lob; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_taken_0 = dis_uops_1_taken; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_imm_packed_0 = dis_uops_1_imm_packed; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_csr_addr_0 = dis_uops_1_csr_addr; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_rob_idx_0 = dis_uops_1_rob_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ldq_idx_0 = dis_uops_1_ldq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_stq_idx_0 = dis_uops_1_stq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_rxq_idx_0 = dis_uops_1_rxq_idx; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_1_pdst_T_3; // @[core.scala:659:28] assign io_lsu_dis_uops_1_bits_pdst_0 = dis_uops_1_pdst; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_1_prs1_T_3; // @[core.scala:654:28] assign io_lsu_dis_uops_1_bits_prs1_0 = dis_uops_1_prs1; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_1_prs2_T_1; // @[core.scala:656:28] assign io_lsu_dis_uops_1_bits_prs2_0 = dis_uops_1_prs2; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_prs3_0 = dis_uops_1_prs3; // @[core.scala:51:7, :167:24] wire _dis_uops_1_prs1_busy_T_4; // @[core.scala:664:85] assign io_lsu_dis_uops_1_bits_prs1_busy_0 = dis_uops_1_prs1_busy; // @[core.scala:51:7, :167:24] wire _dis_uops_1_prs2_busy_T_4; // @[core.scala:666:85] assign io_lsu_dis_uops_1_bits_prs2_busy_0 = dis_uops_1_prs2_busy; // @[core.scala:51:7, :167:24] wire _dis_uops_1_prs3_busy_T; // @[core.scala:668:46] assign io_lsu_dis_uops_1_bits_prs3_busy_0 = dis_uops_1_prs3_busy; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_1_stale_pdst_T_1; // @[core.scala:662:34] assign io_lsu_dis_uops_1_bits_stale_pdst_0 = dis_uops_1_stale_pdst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_exception_0 = dis_uops_1_exception; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_exc_cause_0 = dis_uops_1_exc_cause; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_bypassable_0 = dis_uops_1_bypassable; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_mem_cmd_0 = dis_uops_1_mem_cmd; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_mem_size_0 = dis_uops_1_mem_size; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_mem_signed_0 = dis_uops_1_mem_signed; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_fence_0 = dis_uops_1_is_fence; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_fencei_0 = dis_uops_1_is_fencei; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_amo_0 = dis_uops_1_is_amo; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_uses_ldq_0 = dis_uops_1_uses_ldq; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_uses_stq_0 = dis_uops_1_uses_stq; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_sys_pc2epc_0 = dis_uops_1_is_sys_pc2epc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_is_unique_0 = dis_uops_1_is_unique; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_flush_on_commit_0 = dis_uops_1_flush_on_commit; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ldst_is_rs1_0 = dis_uops_1_ldst_is_rs1; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ldst_0 = dis_uops_1_ldst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_lrs1_0 = dis_uops_1_lrs1; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_lrs2_0 = dis_uops_1_lrs2; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_lrs3_0 = dis_uops_1_lrs3; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_ldst_val_0 = dis_uops_1_ldst_val; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_dst_rtype_0 = dis_uops_1_dst_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_lrs1_rtype_0 = dis_uops_1_lrs1_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_lrs2_rtype_0 = dis_uops_1_lrs2_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_frs3_en_0 = dis_uops_1_frs3_en; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_fp_val_0 = dis_uops_1_fp_val; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_fp_single_0 = dis_uops_1_fp_single; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_xcpt_pf_if_0 = dis_uops_1_xcpt_pf_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_xcpt_ae_if_0 = dis_uops_1_xcpt_ae_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_xcpt_ma_if_0 = dis_uops_1_xcpt_ma_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_bp_debug_if_0 = dis_uops_1_bp_debug_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_bp_xcpt_if_0 = dis_uops_1_bp_xcpt_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_debug_fsrc_0 = dis_uops_1_debug_fsrc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_1_bits_debug_tsrc_0 = dis_uops_1_debug_tsrc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_uopc_0 = dis_uops_2_uopc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_inst_0 = dis_uops_2_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_debug_inst_0 = dis_uops_2_debug_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_rvc_0 = dis_uops_2_is_rvc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_debug_pc_0 = dis_uops_2_debug_pc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_iq_type_0 = dis_uops_2_iq_type; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_fu_code_0 = dis_uops_2_fu_code; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_br_type_0 = dis_uops_2_ctrl_br_type; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_op1_sel_0 = dis_uops_2_ctrl_op1_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_op2_sel_0 = dis_uops_2_ctrl_op2_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_imm_sel_0 = dis_uops_2_ctrl_imm_sel; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_op_fcn_0 = dis_uops_2_ctrl_op_fcn; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_fcn_dw_0 = dis_uops_2_ctrl_fcn_dw; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_csr_cmd_0 = dis_uops_2_ctrl_csr_cmd; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_is_load_0 = dis_uops_2_ctrl_is_load; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_is_sta_0 = dis_uops_2_ctrl_is_sta; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ctrl_is_std_0 = dis_uops_2_ctrl_is_std; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_iw_state_0 = dis_uops_2_iw_state; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_iw_p1_poisoned_0 = dis_uops_2_iw_p1_poisoned; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_iw_p2_poisoned_0 = dis_uops_2_iw_p2_poisoned; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_br_0 = dis_uops_2_is_br; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_jalr_0 = dis_uops_2_is_jalr; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_jal_0 = dis_uops_2_is_jal; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_sfb_0 = dis_uops_2_is_sfb; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_br_mask_0 = dis_uops_2_br_mask; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_br_tag_0 = dis_uops_2_br_tag; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ftq_idx_0 = dis_uops_2_ftq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_edge_inst_0 = dis_uops_2_edge_inst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_pc_lob_0 = dis_uops_2_pc_lob; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_taken_0 = dis_uops_2_taken; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_imm_packed_0 = dis_uops_2_imm_packed; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_csr_addr_0 = dis_uops_2_csr_addr; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_rob_idx_0 = dis_uops_2_rob_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ldq_idx_0 = dis_uops_2_ldq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_stq_idx_0 = dis_uops_2_stq_idx; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_rxq_idx_0 = dis_uops_2_rxq_idx; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_2_pdst_T_3; // @[core.scala:659:28] assign io_lsu_dis_uops_2_bits_pdst_0 = dis_uops_2_pdst; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_2_prs1_T_3; // @[core.scala:654:28] assign io_lsu_dis_uops_2_bits_prs1_0 = dis_uops_2_prs1; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_2_prs2_T_1; // @[core.scala:656:28] assign io_lsu_dis_uops_2_bits_prs2_0 = dis_uops_2_prs2; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_prs3_0 = dis_uops_2_prs3; // @[core.scala:51:7, :167:24] wire _dis_uops_2_prs1_busy_T_4; // @[core.scala:664:85] assign io_lsu_dis_uops_2_bits_prs1_busy_0 = dis_uops_2_prs1_busy; // @[core.scala:51:7, :167:24] wire _dis_uops_2_prs2_busy_T_4; // @[core.scala:666:85] assign io_lsu_dis_uops_2_bits_prs2_busy_0 = dis_uops_2_prs2_busy; // @[core.scala:51:7, :167:24] wire _dis_uops_2_prs3_busy_T; // @[core.scala:668:46] assign io_lsu_dis_uops_2_bits_prs3_busy_0 = dis_uops_2_prs3_busy; // @[core.scala:51:7, :167:24] wire [6:0] _dis_uops_2_stale_pdst_T_1; // @[core.scala:662:34] assign io_lsu_dis_uops_2_bits_stale_pdst_0 = dis_uops_2_stale_pdst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_exception_0 = dis_uops_2_exception; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_exc_cause_0 = dis_uops_2_exc_cause; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_bypassable_0 = dis_uops_2_bypassable; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_mem_cmd_0 = dis_uops_2_mem_cmd; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_mem_size_0 = dis_uops_2_mem_size; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_mem_signed_0 = dis_uops_2_mem_signed; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_fence_0 = dis_uops_2_is_fence; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_fencei_0 = dis_uops_2_is_fencei; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_amo_0 = dis_uops_2_is_amo; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_uses_ldq_0 = dis_uops_2_uses_ldq; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_uses_stq_0 = dis_uops_2_uses_stq; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_sys_pc2epc_0 = dis_uops_2_is_sys_pc2epc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_is_unique_0 = dis_uops_2_is_unique; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_flush_on_commit_0 = dis_uops_2_flush_on_commit; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ldst_is_rs1_0 = dis_uops_2_ldst_is_rs1; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ldst_0 = dis_uops_2_ldst; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_lrs1_0 = dis_uops_2_lrs1; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_lrs2_0 = dis_uops_2_lrs2; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_lrs3_0 = dis_uops_2_lrs3; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_ldst_val_0 = dis_uops_2_ldst_val; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_dst_rtype_0 = dis_uops_2_dst_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_lrs1_rtype_0 = dis_uops_2_lrs1_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_lrs2_rtype_0 = dis_uops_2_lrs2_rtype; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_frs3_en_0 = dis_uops_2_frs3_en; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_fp_val_0 = dis_uops_2_fp_val; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_fp_single_0 = dis_uops_2_fp_single; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_xcpt_pf_if_0 = dis_uops_2_xcpt_pf_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_xcpt_ae_if_0 = dis_uops_2_xcpt_ae_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_xcpt_ma_if_0 = dis_uops_2_xcpt_ma_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_bp_debug_if_0 = dis_uops_2_bp_debug_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_bp_xcpt_if_0 = dis_uops_2_bp_xcpt_if; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_debug_fsrc_0 = dis_uops_2_debug_fsrc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_2_bits_debug_tsrc_0 = dis_uops_2_debug_tsrc; // @[core.scala:51:7, :167:24] assign io_lsu_dis_uops_0_valid_0 = dis_fire_0; // @[core.scala:51:7, :168:24] assign io_lsu_dis_uops_1_valid_0 = dis_fire_1; // @[core.scala:51:7, :168:24] assign io_lsu_dis_uops_2_valid_0 = dis_fire_2; // @[core.scala:51:7, :168:24] wire _dis_ready_T; // @[core.scala:715:16] wire dis_ready; // @[core.scala:169:24] wire iss_valids_0; // @[core.scala:172:24] wire iss_valids_1; // @[core.scala:172:24] wire iss_valids_2; // @[core.scala:172:24] wire iss_valids_3; // @[core.scala:172:24] assign pred_wakeup_bits_uop_uopc = iss_uops_1_uopc; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_uopc = iss_uops_1_uopc; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_inst = iss_uops_1_inst; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_inst = iss_uops_1_inst; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_debug_inst = iss_uops_1_debug_inst; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_debug_inst = iss_uops_1_debug_inst; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_rvc = iss_uops_1_is_rvc; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_rvc = iss_uops_1_is_rvc; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_debug_pc = iss_uops_1_debug_pc; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_debug_pc = iss_uops_1_debug_pc; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_iq_type = iss_uops_1_iq_type; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_iq_type = iss_uops_1_iq_type; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_fu_code = iss_uops_1_fu_code; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_fu_code = iss_uops_1_fu_code; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_br_type = iss_uops_1_ctrl_br_type; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_br_type = iss_uops_1_ctrl_br_type; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_op1_sel = iss_uops_1_ctrl_op1_sel; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_op1_sel = iss_uops_1_ctrl_op1_sel; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_op2_sel = iss_uops_1_ctrl_op2_sel; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_op2_sel = iss_uops_1_ctrl_op2_sel; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_imm_sel = iss_uops_1_ctrl_imm_sel; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_imm_sel = iss_uops_1_ctrl_imm_sel; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_op_fcn = iss_uops_1_ctrl_op_fcn; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_op_fcn = iss_uops_1_ctrl_op_fcn; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_fcn_dw = iss_uops_1_ctrl_fcn_dw; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_fcn_dw = iss_uops_1_ctrl_fcn_dw; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_csr_cmd = iss_uops_1_ctrl_csr_cmd; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_csr_cmd = iss_uops_1_ctrl_csr_cmd; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_is_load = iss_uops_1_ctrl_is_load; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_is_load = iss_uops_1_ctrl_is_load; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_is_sta = iss_uops_1_ctrl_is_sta; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_is_sta = iss_uops_1_ctrl_is_sta; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ctrl_is_std = iss_uops_1_ctrl_is_std; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ctrl_is_std = iss_uops_1_ctrl_is_std; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_iw_state = iss_uops_1_iw_state; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_iw_state = iss_uops_1_iw_state; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_iw_p1_poisoned = iss_uops_1_iw_p1_poisoned; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_iw_p1_poisoned = iss_uops_1_iw_p1_poisoned; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_iw_p2_poisoned = iss_uops_1_iw_p2_poisoned; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_iw_p2_poisoned = iss_uops_1_iw_p2_poisoned; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_br = iss_uops_1_is_br; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_br = iss_uops_1_is_br; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_jalr = iss_uops_1_is_jalr; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_jalr = iss_uops_1_is_jalr; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_jal = iss_uops_1_is_jal; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_jal = iss_uops_1_is_jal; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_sfb = iss_uops_1_is_sfb; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_sfb = iss_uops_1_is_sfb; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_br_mask = iss_uops_1_br_mask; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_br_mask = iss_uops_1_br_mask; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_br_tag = iss_uops_1_br_tag; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_br_tag = iss_uops_1_br_tag; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ftq_idx = iss_uops_1_ftq_idx; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ftq_idx = iss_uops_1_ftq_idx; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_edge_inst = iss_uops_1_edge_inst; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_edge_inst = iss_uops_1_edge_inst; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_pc_lob = iss_uops_1_pc_lob; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_pc_lob = iss_uops_1_pc_lob; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_taken = iss_uops_1_taken; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_taken = iss_uops_1_taken; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_imm_packed = iss_uops_1_imm_packed; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_imm_packed = iss_uops_1_imm_packed; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_csr_addr = iss_uops_1_csr_addr; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_csr_addr = iss_uops_1_csr_addr; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_rob_idx = iss_uops_1_rob_idx; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_rob_idx = iss_uops_1_rob_idx; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ldq_idx = iss_uops_1_ldq_idx; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ldq_idx = iss_uops_1_ldq_idx; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_stq_idx = iss_uops_1_stq_idx; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_stq_idx = iss_uops_1_stq_idx; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_rxq_idx = iss_uops_1_rxq_idx; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_rxq_idx = iss_uops_1_rxq_idx; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_pdst = iss_uops_1_pdst; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_pdst = iss_uops_1_pdst; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_prs1 = iss_uops_1_prs1; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_prs1 = iss_uops_1_prs1; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_prs2 = iss_uops_1_prs2; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_prs2 = iss_uops_1_prs2; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_prs3 = iss_uops_1_prs3; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_prs3 = iss_uops_1_prs3; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ppred = iss_uops_1_ppred; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ppred = iss_uops_1_ppred; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_prs1_busy = iss_uops_1_prs1_busy; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_prs1_busy = iss_uops_1_prs1_busy; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_prs2_busy = iss_uops_1_prs2_busy; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_prs2_busy = iss_uops_1_prs2_busy; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_prs3_busy = iss_uops_1_prs3_busy; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_prs3_busy = iss_uops_1_prs3_busy; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ppred_busy = iss_uops_1_ppred_busy; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ppred_busy = iss_uops_1_ppred_busy; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_stale_pdst = iss_uops_1_stale_pdst; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_stale_pdst = iss_uops_1_stale_pdst; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_exception = iss_uops_1_exception; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_exception = iss_uops_1_exception; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_exc_cause = iss_uops_1_exc_cause; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_exc_cause = iss_uops_1_exc_cause; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_bypassable = iss_uops_1_bypassable; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_bypassable = iss_uops_1_bypassable; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_mem_cmd = iss_uops_1_mem_cmd; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_mem_cmd = iss_uops_1_mem_cmd; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_mem_size = iss_uops_1_mem_size; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_mem_size = iss_uops_1_mem_size; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_mem_signed = iss_uops_1_mem_signed; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_mem_signed = iss_uops_1_mem_signed; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_fence = iss_uops_1_is_fence; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_fence = iss_uops_1_is_fence; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_fencei = iss_uops_1_is_fencei; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_fencei = iss_uops_1_is_fencei; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_amo = iss_uops_1_is_amo; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_amo = iss_uops_1_is_amo; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_uses_ldq = iss_uops_1_uses_ldq; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_uses_ldq = iss_uops_1_uses_ldq; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_uses_stq = iss_uops_1_uses_stq; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_uses_stq = iss_uops_1_uses_stq; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_sys_pc2epc = iss_uops_1_is_sys_pc2epc; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_sys_pc2epc = iss_uops_1_is_sys_pc2epc; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_is_unique = iss_uops_1_is_unique; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_is_unique = iss_uops_1_is_unique; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_flush_on_commit = iss_uops_1_flush_on_commit; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_flush_on_commit = iss_uops_1_flush_on_commit; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ldst_is_rs1 = iss_uops_1_ldst_is_rs1; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ldst_is_rs1 = iss_uops_1_ldst_is_rs1; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ldst = iss_uops_1_ldst; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ldst = iss_uops_1_ldst; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_lrs1 = iss_uops_1_lrs1; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_lrs1 = iss_uops_1_lrs1; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_lrs2 = iss_uops_1_lrs2; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_lrs2 = iss_uops_1_lrs2; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_lrs3 = iss_uops_1_lrs3; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_lrs3 = iss_uops_1_lrs3; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_ldst_val = iss_uops_1_ldst_val; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_ldst_val = iss_uops_1_ldst_val; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_dst_rtype = iss_uops_1_dst_rtype; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_dst_rtype = iss_uops_1_dst_rtype; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_lrs1_rtype = iss_uops_1_lrs1_rtype; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_lrs1_rtype = iss_uops_1_lrs1_rtype; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_lrs2_rtype = iss_uops_1_lrs2_rtype; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_lrs2_rtype = iss_uops_1_lrs2_rtype; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_frs3_en = iss_uops_1_frs3_en; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_frs3_en = iss_uops_1_frs3_en; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_fp_val = iss_uops_1_fp_val; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_fp_val = iss_uops_1_fp_val; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_fp_single = iss_uops_1_fp_single; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_fp_single = iss_uops_1_fp_single; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_xcpt_pf_if = iss_uops_1_xcpt_pf_if; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_xcpt_pf_if = iss_uops_1_xcpt_pf_if; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_xcpt_ae_if = iss_uops_1_xcpt_ae_if; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_xcpt_ae_if = iss_uops_1_xcpt_ae_if; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_xcpt_ma_if = iss_uops_1_xcpt_ma_if; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_xcpt_ma_if = iss_uops_1_xcpt_ma_if; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_bp_debug_if = iss_uops_1_bp_debug_if; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_bp_debug_if = iss_uops_1_bp_debug_if; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_bp_xcpt_if = iss_uops_1_bp_xcpt_if; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_bp_xcpt_if = iss_uops_1_bp_xcpt_if; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_debug_fsrc = iss_uops_1_debug_fsrc; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_debug_fsrc = iss_uops_1_debug_fsrc; // @[core.scala:173:24, :814:29] assign pred_wakeup_bits_uop_debug_tsrc = iss_uops_1_debug_tsrc; // @[core.scala:149:26, :173:24] assign fast_wakeup_bits_uop_debug_tsrc = iss_uops_1_debug_tsrc; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_uopc = iss_uops_2_uopc; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_inst = iss_uops_2_inst; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_debug_inst = iss_uops_2_debug_inst; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_rvc = iss_uops_2_is_rvc; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_debug_pc = iss_uops_2_debug_pc; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_iq_type = iss_uops_2_iq_type; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_fu_code = iss_uops_2_fu_code; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_br_type = iss_uops_2_ctrl_br_type; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_op1_sel = iss_uops_2_ctrl_op1_sel; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_op2_sel = iss_uops_2_ctrl_op2_sel; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_imm_sel = iss_uops_2_ctrl_imm_sel; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_op_fcn = iss_uops_2_ctrl_op_fcn; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_fcn_dw = iss_uops_2_ctrl_fcn_dw; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_csr_cmd = iss_uops_2_ctrl_csr_cmd; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_is_load = iss_uops_2_ctrl_is_load; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_is_sta = iss_uops_2_ctrl_is_sta; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ctrl_is_std = iss_uops_2_ctrl_is_std; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_iw_state = iss_uops_2_iw_state; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_iw_p1_poisoned = iss_uops_2_iw_p1_poisoned; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_iw_p2_poisoned = iss_uops_2_iw_p2_poisoned; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_br = iss_uops_2_is_br; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_jalr = iss_uops_2_is_jalr; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_jal = iss_uops_2_is_jal; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_sfb = iss_uops_2_is_sfb; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_br_mask = iss_uops_2_br_mask; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_br_tag = iss_uops_2_br_tag; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ftq_idx = iss_uops_2_ftq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_edge_inst = iss_uops_2_edge_inst; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_pc_lob = iss_uops_2_pc_lob; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_taken = iss_uops_2_taken; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_imm_packed = iss_uops_2_imm_packed; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_csr_addr = iss_uops_2_csr_addr; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_rob_idx = iss_uops_2_rob_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ldq_idx = iss_uops_2_ldq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_stq_idx = iss_uops_2_stq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_rxq_idx = iss_uops_2_rxq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_pdst = iss_uops_2_pdst; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_prs1 = iss_uops_2_prs1; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_prs2 = iss_uops_2_prs2; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_prs3 = iss_uops_2_prs3; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ppred = iss_uops_2_ppred; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_prs1_busy = iss_uops_2_prs1_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_prs2_busy = iss_uops_2_prs2_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_prs3_busy = iss_uops_2_prs3_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ppred_busy = iss_uops_2_ppred_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_stale_pdst = iss_uops_2_stale_pdst; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_exception = iss_uops_2_exception; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_exc_cause = iss_uops_2_exc_cause; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_bypassable = iss_uops_2_bypassable; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_mem_cmd = iss_uops_2_mem_cmd; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_mem_size = iss_uops_2_mem_size; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_mem_signed = iss_uops_2_mem_signed; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_fence = iss_uops_2_is_fence; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_fencei = iss_uops_2_is_fencei; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_amo = iss_uops_2_is_amo; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_uses_ldq = iss_uops_2_uses_ldq; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_uses_stq = iss_uops_2_uses_stq; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_sys_pc2epc = iss_uops_2_is_sys_pc2epc; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_is_unique = iss_uops_2_is_unique; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_flush_on_commit = iss_uops_2_flush_on_commit; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ldst_is_rs1 = iss_uops_2_ldst_is_rs1; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ldst = iss_uops_2_ldst; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_lrs1 = iss_uops_2_lrs1; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_lrs2 = iss_uops_2_lrs2; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_lrs3 = iss_uops_2_lrs3; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_ldst_val = iss_uops_2_ldst_val; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_dst_rtype = iss_uops_2_dst_rtype; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_lrs1_rtype = iss_uops_2_lrs1_rtype; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_lrs2_rtype = iss_uops_2_lrs2_rtype; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_frs3_en = iss_uops_2_frs3_en; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_fp_val = iss_uops_2_fp_val; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_fp_single = iss_uops_2_fp_single; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_xcpt_pf_if = iss_uops_2_xcpt_pf_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_xcpt_ae_if = iss_uops_2_xcpt_ae_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_xcpt_ma_if = iss_uops_2_xcpt_ma_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_bp_debug_if = iss_uops_2_bp_debug_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_bp_xcpt_if = iss_uops_2_bp_xcpt_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_debug_fsrc = iss_uops_2_debug_fsrc; // @[core.scala:173:24, :814:29] assign fast_wakeup_1_bits_uop_debug_tsrc = iss_uops_2_debug_tsrc; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_uopc = iss_uops_3_uopc; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_inst = iss_uops_3_inst; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_debug_inst = iss_uops_3_debug_inst; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_rvc = iss_uops_3_is_rvc; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_debug_pc = iss_uops_3_debug_pc; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_iq_type = iss_uops_3_iq_type; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_fu_code = iss_uops_3_fu_code; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_br_type = iss_uops_3_ctrl_br_type; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_op1_sel = iss_uops_3_ctrl_op1_sel; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_op2_sel = iss_uops_3_ctrl_op2_sel; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_imm_sel = iss_uops_3_ctrl_imm_sel; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_op_fcn = iss_uops_3_ctrl_op_fcn; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_fcn_dw = iss_uops_3_ctrl_fcn_dw; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_csr_cmd = iss_uops_3_ctrl_csr_cmd; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_is_load = iss_uops_3_ctrl_is_load; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_is_sta = iss_uops_3_ctrl_is_sta; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ctrl_is_std = iss_uops_3_ctrl_is_std; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_iw_state = iss_uops_3_iw_state; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_iw_p1_poisoned = iss_uops_3_iw_p1_poisoned; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_iw_p2_poisoned = iss_uops_3_iw_p2_poisoned; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_br = iss_uops_3_is_br; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_jalr = iss_uops_3_is_jalr; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_jal = iss_uops_3_is_jal; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_sfb = iss_uops_3_is_sfb; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_br_mask = iss_uops_3_br_mask; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_br_tag = iss_uops_3_br_tag; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ftq_idx = iss_uops_3_ftq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_edge_inst = iss_uops_3_edge_inst; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_pc_lob = iss_uops_3_pc_lob; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_taken = iss_uops_3_taken; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_imm_packed = iss_uops_3_imm_packed; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_csr_addr = iss_uops_3_csr_addr; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_rob_idx = iss_uops_3_rob_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ldq_idx = iss_uops_3_ldq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_stq_idx = iss_uops_3_stq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_rxq_idx = iss_uops_3_rxq_idx; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_pdst = iss_uops_3_pdst; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_prs1 = iss_uops_3_prs1; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_prs2 = iss_uops_3_prs2; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_prs3 = iss_uops_3_prs3; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ppred = iss_uops_3_ppred; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_prs1_busy = iss_uops_3_prs1_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_prs2_busy = iss_uops_3_prs2_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_prs3_busy = iss_uops_3_prs3_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ppred_busy = iss_uops_3_ppred_busy; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_stale_pdst = iss_uops_3_stale_pdst; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_exception = iss_uops_3_exception; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_exc_cause = iss_uops_3_exc_cause; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_bypassable = iss_uops_3_bypassable; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_mem_cmd = iss_uops_3_mem_cmd; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_mem_size = iss_uops_3_mem_size; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_mem_signed = iss_uops_3_mem_signed; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_fence = iss_uops_3_is_fence; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_fencei = iss_uops_3_is_fencei; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_amo = iss_uops_3_is_amo; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_uses_ldq = iss_uops_3_uses_ldq; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_uses_stq = iss_uops_3_uses_stq; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_sys_pc2epc = iss_uops_3_is_sys_pc2epc; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_is_unique = iss_uops_3_is_unique; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_flush_on_commit = iss_uops_3_flush_on_commit; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ldst_is_rs1 = iss_uops_3_ldst_is_rs1; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ldst = iss_uops_3_ldst; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_lrs1 = iss_uops_3_lrs1; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_lrs2 = iss_uops_3_lrs2; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_lrs3 = iss_uops_3_lrs3; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_ldst_val = iss_uops_3_ldst_val; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_dst_rtype = iss_uops_3_dst_rtype; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_lrs1_rtype = iss_uops_3_lrs1_rtype; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_lrs2_rtype = iss_uops_3_lrs2_rtype; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_frs3_en = iss_uops_3_frs3_en; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_fp_val = iss_uops_3_fp_val; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_fp_single = iss_uops_3_fp_single; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_xcpt_pf_if = iss_uops_3_xcpt_pf_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_xcpt_ae_if = iss_uops_3_xcpt_ae_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_xcpt_ma_if = iss_uops_3_xcpt_ma_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_bp_debug_if = iss_uops_3_bp_debug_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_bp_xcpt_if = iss_uops_3_bp_xcpt_if; // @[core.scala:173:24, :814:29] assign fast_wakeup_2_bits_uop_debug_fsrc = iss_uops_3_debug_fsrc; // @[core.scala:173:24, :814:29] wire [3:0] iss_uops_0_ctrl_br_type; // @[core.scala:173:24] wire [1:0] iss_uops_0_ctrl_op1_sel; // @[core.scala:173:24] wire [2:0] iss_uops_0_ctrl_op2_sel; // @[core.scala:173:24] wire [2:0] iss_uops_0_ctrl_imm_sel; // @[core.scala:173:24] wire [4:0] iss_uops_0_ctrl_op_fcn; // @[core.scala:173:24] wire iss_uops_0_ctrl_fcn_dw; // @[core.scala:173:24] wire [2:0] iss_uops_0_ctrl_csr_cmd; // @[core.scala:173:24] wire iss_uops_0_ctrl_is_load; // @[core.scala:173:24] wire iss_uops_0_ctrl_is_sta; // @[core.scala:173:24] wire iss_uops_0_ctrl_is_std; // @[core.scala:173:24] assign fast_wakeup_2_bits_uop_debug_tsrc = iss_uops_3_debug_tsrc; // @[core.scala:173:24, :814:29] wire [6:0] iss_uops_0_uopc; // @[core.scala:173:24] wire [31:0] iss_uops_0_inst; // @[core.scala:173:24] wire [31:0] iss_uops_0_debug_inst; // @[core.scala:173:24] wire iss_uops_0_is_rvc; // @[core.scala:173:24] wire [39:0] iss_uops_0_debug_pc; // @[core.scala:173:24] wire [2:0] iss_uops_0_iq_type; // @[core.scala:173:24] wire [9:0] iss_uops_0_fu_code; // @[core.scala:173:24] wire [1:0] iss_uops_0_iw_state; // @[core.scala:173:24] wire iss_uops_0_iw_p1_poisoned; // @[core.scala:173:24] wire iss_uops_0_iw_p2_poisoned; // @[core.scala:173:24] wire iss_uops_0_is_br; // @[core.scala:173:24] wire iss_uops_0_is_jalr; // @[core.scala:173:24] wire iss_uops_0_is_jal; // @[core.scala:173:24] wire iss_uops_0_is_sfb; // @[core.scala:173:24] wire [15:0] iss_uops_0_br_mask; // @[core.scala:173:24] wire [3:0] iss_uops_0_br_tag; // @[core.scala:173:24] wire [4:0] iss_uops_0_ftq_idx; // @[core.scala:173:24] wire iss_uops_0_edge_inst; // @[core.scala:173:24] wire [5:0] iss_uops_0_pc_lob; // @[core.scala:173:24] wire iss_uops_0_taken; // @[core.scala:173:24] wire [19:0] iss_uops_0_imm_packed; // @[core.scala:173:24] wire [11:0] iss_uops_0_csr_addr; // @[core.scala:173:24] wire [6:0] iss_uops_0_rob_idx; // @[core.scala:173:24] wire [4:0] iss_uops_0_ldq_idx; // @[core.scala:173:24] wire [4:0] iss_uops_0_stq_idx; // @[core.scala:173:24] wire [1:0] iss_uops_0_rxq_idx; // @[core.scala:173:24] wire [6:0] iss_uops_0_pdst; // @[core.scala:173:24] wire [6:0] iss_uops_0_prs1; // @[core.scala:173:24] wire [6:0] iss_uops_0_prs2; // @[core.scala:173:24] wire [6:0] iss_uops_0_prs3; // @[core.scala:173:24] wire [4:0] iss_uops_0_ppred; // @[core.scala:173:24] wire iss_uops_0_prs1_busy; // @[core.scala:173:24] wire iss_uops_0_prs2_busy; // @[core.scala:173:24] wire iss_uops_0_prs3_busy; // @[core.scala:173:24] wire iss_uops_0_ppred_busy; // @[core.scala:173:24] wire [6:0] iss_uops_0_stale_pdst; // @[core.scala:173:24] wire iss_uops_0_exception; // @[core.scala:173:24] wire [63:0] iss_uops_0_exc_cause; // @[core.scala:173:24] wire iss_uops_0_bypassable; // @[core.scala:173:24] wire [4:0] iss_uops_0_mem_cmd; // @[core.scala:173:24] wire [1:0] iss_uops_0_mem_size; // @[core.scala:173:24] wire iss_uops_0_mem_signed; // @[core.scala:173:24] wire iss_uops_0_is_fence; // @[core.scala:173:24] wire iss_uops_0_is_fencei; // @[core.scala:173:24] wire iss_uops_0_is_amo; // @[core.scala:173:24] wire iss_uops_0_uses_ldq; // @[core.scala:173:24] wire iss_uops_0_uses_stq; // @[core.scala:173:24] wire iss_uops_0_is_sys_pc2epc; // @[core.scala:173:24] wire iss_uops_0_is_unique; // @[core.scala:173:24] wire iss_uops_0_flush_on_commit; // @[core.scala:173:24] wire iss_uops_0_ldst_is_rs1; // @[core.scala:173:24] wire [5:0] iss_uops_0_ldst; // @[core.scala:173:24] wire [5:0] iss_uops_0_lrs1; // @[core.scala:173:24] wire [5:0] iss_uops_0_lrs2; // @[core.scala:173:24] wire [5:0] iss_uops_0_lrs3; // @[core.scala:173:24] wire iss_uops_0_ldst_val; // @[core.scala:173:24] wire [1:0] iss_uops_0_dst_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_0_lrs1_rtype; // @[core.scala:173:24] wire [1:0] iss_uops_0_lrs2_rtype; // @[core.scala:173:24] wire iss_uops_0_frs3_en; // @[core.scala:173:24] wire iss_uops_0_fp_val; // @[core.scala:173:24] wire iss_uops_0_fp_single; // @[core.scala:173:24] wire iss_uops_0_xcpt_pf_if; // @[core.scala:173:24] wire iss_uops_0_xcpt_ae_if; // @[core.scala:173:24] wire iss_uops_0_xcpt_ma_if; // @[core.scala:173:24] wire iss_uops_0_bp_debug_if; // @[core.scala:173:24] wire iss_uops_0_bp_xcpt_if; // @[core.scala:173:24] wire [1:0] iss_uops_0_debug_fsrc; // @[core.scala:173:24] wire [1:0] iss_uops_0_debug_tsrc; // @[core.scala:173:24] wire [3:0] bypasses_0_bits_uop_ctrl_br_type; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_ctrl_op1_sel; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_uop_ctrl_op2_sel; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_uop_ctrl_imm_sel; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_uop_ctrl_op_fcn; // @[core.scala:174:24] wire bypasses_0_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24] wire bypasses_0_bits_uop_ctrl_is_load; // @[core.scala:174:24] wire bypasses_0_bits_uop_ctrl_is_sta; // @[core.scala:174:24] wire bypasses_0_bits_uop_ctrl_is_std; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_uopc; // @[core.scala:174:24] wire [31:0] bypasses_0_bits_uop_inst; // @[core.scala:174:24] wire [31:0] bypasses_0_bits_uop_debug_inst; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_rvc; // @[core.scala:174:24] wire [39:0] bypasses_0_bits_uop_debug_pc; // @[core.scala:174:24] wire [2:0] bypasses_0_bits_uop_iq_type; // @[core.scala:174:24] wire [9:0] bypasses_0_bits_uop_fu_code; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_iw_state; // @[core.scala:174:24] wire bypasses_0_bits_uop_iw_p1_poisoned; // @[core.scala:174:24] wire bypasses_0_bits_uop_iw_p2_poisoned; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_br; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_jalr; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_jal; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_sfb; // @[core.scala:174:24] wire [15:0] bypasses_0_bits_uop_br_mask; // @[core.scala:174:24] wire [3:0] bypasses_0_bits_uop_br_tag; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_uop_ftq_idx; // @[core.scala:174:24] wire bypasses_0_bits_uop_edge_inst; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_uop_pc_lob; // @[core.scala:174:24] wire bypasses_0_bits_uop_taken; // @[core.scala:174:24] wire [19:0] bypasses_0_bits_uop_imm_packed; // @[core.scala:174:24] wire [11:0] bypasses_0_bits_uop_csr_addr; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_rob_idx; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_uop_ldq_idx; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_uop_stq_idx; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_rxq_idx; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_pdst; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_prs1; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_prs2; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_prs3; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_uop_ppred; // @[core.scala:174:24] wire bypasses_0_bits_uop_prs1_busy; // @[core.scala:174:24] wire bypasses_0_bits_uop_prs2_busy; // @[core.scala:174:24] wire bypasses_0_bits_uop_prs3_busy; // @[core.scala:174:24] wire bypasses_0_bits_uop_ppred_busy; // @[core.scala:174:24] wire [6:0] bypasses_0_bits_uop_stale_pdst; // @[core.scala:174:24] wire bypasses_0_bits_uop_exception; // @[core.scala:174:24] wire [63:0] bypasses_0_bits_uop_exc_cause; // @[core.scala:174:24] wire bypasses_0_bits_uop_bypassable; // @[core.scala:174:24] wire [4:0] bypasses_0_bits_uop_mem_cmd; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_mem_size; // @[core.scala:174:24] wire bypasses_0_bits_uop_mem_signed; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_fence; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_fencei; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_amo; // @[core.scala:174:24] wire bypasses_0_bits_uop_uses_ldq; // @[core.scala:174:24] wire bypasses_0_bits_uop_uses_stq; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_sys_pc2epc; // @[core.scala:174:24] wire bypasses_0_bits_uop_is_unique; // @[core.scala:174:24] wire bypasses_0_bits_uop_flush_on_commit; // @[core.scala:174:24] wire bypasses_0_bits_uop_ldst_is_rs1; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_uop_ldst; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_uop_lrs1; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_uop_lrs2; // @[core.scala:174:24] wire [5:0] bypasses_0_bits_uop_lrs3; // @[core.scala:174:24] wire bypasses_0_bits_uop_ldst_val; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_dst_rtype; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_lrs1_rtype; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_lrs2_rtype; // @[core.scala:174:24] wire bypasses_0_bits_uop_frs3_en; // @[core.scala:174:24] wire bypasses_0_bits_uop_fp_val; // @[core.scala:174:24] wire bypasses_0_bits_uop_fp_single; // @[core.scala:174:24] wire bypasses_0_bits_uop_xcpt_pf_if; // @[core.scala:174:24] wire bypasses_0_bits_uop_xcpt_ae_if; // @[core.scala:174:24] wire bypasses_0_bits_uop_xcpt_ma_if; // @[core.scala:174:24] wire bypasses_0_bits_uop_bp_debug_if; // @[core.scala:174:24] wire bypasses_0_bits_uop_bp_xcpt_if; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_debug_fsrc; // @[core.scala:174:24] wire [1:0] bypasses_0_bits_uop_debug_tsrc; // @[core.scala:174:24] wire [63:0] bypasses_0_bits_data; // @[core.scala:174:24] wire bypasses_0_valid; // @[core.scala:174:24] wire [3:0] bypasses_1_bits_uop_ctrl_br_type; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_ctrl_op1_sel; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_uop_ctrl_op2_sel; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_uop_ctrl_imm_sel; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_uop_ctrl_op_fcn; // @[core.scala:174:24] wire bypasses_1_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24] wire bypasses_1_bits_uop_ctrl_is_load; // @[core.scala:174:24] wire bypasses_1_bits_uop_ctrl_is_sta; // @[core.scala:174:24] wire bypasses_1_bits_uop_ctrl_is_std; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_uopc; // @[core.scala:174:24] wire [31:0] bypasses_1_bits_uop_inst; // @[core.scala:174:24] wire [31:0] bypasses_1_bits_uop_debug_inst; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_rvc; // @[core.scala:174:24] wire [39:0] bypasses_1_bits_uop_debug_pc; // @[core.scala:174:24] wire [2:0] bypasses_1_bits_uop_iq_type; // @[core.scala:174:24] wire [9:0] bypasses_1_bits_uop_fu_code; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_iw_state; // @[core.scala:174:24] wire bypasses_1_bits_uop_iw_p1_poisoned; // @[core.scala:174:24] wire bypasses_1_bits_uop_iw_p2_poisoned; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_br; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_jalr; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_jal; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_sfb; // @[core.scala:174:24] wire [15:0] bypasses_1_bits_uop_br_mask; // @[core.scala:174:24] wire [3:0] bypasses_1_bits_uop_br_tag; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_uop_ftq_idx; // @[core.scala:174:24] wire bypasses_1_bits_uop_edge_inst; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_uop_pc_lob; // @[core.scala:174:24] wire bypasses_1_bits_uop_taken; // @[core.scala:174:24] wire [19:0] bypasses_1_bits_uop_imm_packed; // @[core.scala:174:24] wire [11:0] bypasses_1_bits_uop_csr_addr; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_rob_idx; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_uop_ldq_idx; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_uop_stq_idx; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_rxq_idx; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_pdst; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_prs1; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_prs2; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_prs3; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_uop_ppred; // @[core.scala:174:24] wire bypasses_1_bits_uop_prs1_busy; // @[core.scala:174:24] wire bypasses_1_bits_uop_prs2_busy; // @[core.scala:174:24] wire bypasses_1_bits_uop_prs3_busy; // @[core.scala:174:24] wire bypasses_1_bits_uop_ppred_busy; // @[core.scala:174:24] wire [6:0] bypasses_1_bits_uop_stale_pdst; // @[core.scala:174:24] wire bypasses_1_bits_uop_exception; // @[core.scala:174:24] wire [63:0] bypasses_1_bits_uop_exc_cause; // @[core.scala:174:24] wire bypasses_1_bits_uop_bypassable; // @[core.scala:174:24] wire [4:0] bypasses_1_bits_uop_mem_cmd; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_mem_size; // @[core.scala:174:24] wire bypasses_1_bits_uop_mem_signed; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_fence; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_fencei; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_amo; // @[core.scala:174:24] wire bypasses_1_bits_uop_uses_ldq; // @[core.scala:174:24] wire bypasses_1_bits_uop_uses_stq; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_sys_pc2epc; // @[core.scala:174:24] wire bypasses_1_bits_uop_is_unique; // @[core.scala:174:24] wire bypasses_1_bits_uop_flush_on_commit; // @[core.scala:174:24] wire bypasses_1_bits_uop_ldst_is_rs1; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_uop_ldst; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_uop_lrs1; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_uop_lrs2; // @[core.scala:174:24] wire [5:0] bypasses_1_bits_uop_lrs3; // @[core.scala:174:24] wire bypasses_1_bits_uop_ldst_val; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_dst_rtype; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_lrs1_rtype; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_lrs2_rtype; // @[core.scala:174:24] wire bypasses_1_bits_uop_frs3_en; // @[core.scala:174:24] wire bypasses_1_bits_uop_fp_val; // @[core.scala:174:24] wire bypasses_1_bits_uop_fp_single; // @[core.scala:174:24] wire bypasses_1_bits_uop_xcpt_pf_if; // @[core.scala:174:24] wire bypasses_1_bits_uop_xcpt_ae_if; // @[core.scala:174:24] wire bypasses_1_bits_uop_xcpt_ma_if; // @[core.scala:174:24] wire bypasses_1_bits_uop_bp_debug_if; // @[core.scala:174:24] wire bypasses_1_bits_uop_bp_xcpt_if; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_debug_fsrc; // @[core.scala:174:24] wire [1:0] bypasses_1_bits_uop_debug_tsrc; // @[core.scala:174:24] wire [63:0] bypasses_1_bits_data; // @[core.scala:174:24] wire bypasses_1_valid; // @[core.scala:174:24] wire [3:0] bypasses_2_bits_uop_ctrl_br_type; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_ctrl_op1_sel; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_uop_ctrl_op2_sel; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_uop_ctrl_imm_sel; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_uop_ctrl_op_fcn; // @[core.scala:174:24] wire bypasses_2_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24] wire bypasses_2_bits_uop_ctrl_is_load; // @[core.scala:174:24] wire bypasses_2_bits_uop_ctrl_is_sta; // @[core.scala:174:24] wire bypasses_2_bits_uop_ctrl_is_std; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_uopc; // @[core.scala:174:24] wire [31:0] bypasses_2_bits_uop_inst; // @[core.scala:174:24] wire [31:0] bypasses_2_bits_uop_debug_inst; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_rvc; // @[core.scala:174:24] wire [39:0] bypasses_2_bits_uop_debug_pc; // @[core.scala:174:24] wire [2:0] bypasses_2_bits_uop_iq_type; // @[core.scala:174:24] wire [9:0] bypasses_2_bits_uop_fu_code; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_iw_state; // @[core.scala:174:24] wire bypasses_2_bits_uop_iw_p1_poisoned; // @[core.scala:174:24] wire bypasses_2_bits_uop_iw_p2_poisoned; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_br; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_jalr; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_jal; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_sfb; // @[core.scala:174:24] wire [15:0] bypasses_2_bits_uop_br_mask; // @[core.scala:174:24] wire [3:0] bypasses_2_bits_uop_br_tag; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_uop_ftq_idx; // @[core.scala:174:24] wire bypasses_2_bits_uop_edge_inst; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_uop_pc_lob; // @[core.scala:174:24] wire bypasses_2_bits_uop_taken; // @[core.scala:174:24] wire [19:0] bypasses_2_bits_uop_imm_packed; // @[core.scala:174:24] wire [11:0] bypasses_2_bits_uop_csr_addr; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_rob_idx; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_uop_ldq_idx; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_uop_stq_idx; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_rxq_idx; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_pdst; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_prs1; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_prs2; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_prs3; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_uop_ppred; // @[core.scala:174:24] wire bypasses_2_bits_uop_prs1_busy; // @[core.scala:174:24] wire bypasses_2_bits_uop_prs2_busy; // @[core.scala:174:24] wire bypasses_2_bits_uop_prs3_busy; // @[core.scala:174:24] wire bypasses_2_bits_uop_ppred_busy; // @[core.scala:174:24] wire [6:0] bypasses_2_bits_uop_stale_pdst; // @[core.scala:174:24] wire bypasses_2_bits_uop_exception; // @[core.scala:174:24] wire [63:0] bypasses_2_bits_uop_exc_cause; // @[core.scala:174:24] wire bypasses_2_bits_uop_bypassable; // @[core.scala:174:24] wire [4:0] bypasses_2_bits_uop_mem_cmd; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_mem_size; // @[core.scala:174:24] wire bypasses_2_bits_uop_mem_signed; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_fence; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_fencei; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_amo; // @[core.scala:174:24] wire bypasses_2_bits_uop_uses_ldq; // @[core.scala:174:24] wire bypasses_2_bits_uop_uses_stq; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_sys_pc2epc; // @[core.scala:174:24] wire bypasses_2_bits_uop_is_unique; // @[core.scala:174:24] wire bypasses_2_bits_uop_flush_on_commit; // @[core.scala:174:24] wire bypasses_2_bits_uop_ldst_is_rs1; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_uop_ldst; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_uop_lrs1; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_uop_lrs2; // @[core.scala:174:24] wire [5:0] bypasses_2_bits_uop_lrs3; // @[core.scala:174:24] wire bypasses_2_bits_uop_ldst_val; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_dst_rtype; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_lrs1_rtype; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_lrs2_rtype; // @[core.scala:174:24] wire bypasses_2_bits_uop_frs3_en; // @[core.scala:174:24] wire bypasses_2_bits_uop_fp_val; // @[core.scala:174:24] wire bypasses_2_bits_uop_fp_single; // @[core.scala:174:24] wire bypasses_2_bits_uop_xcpt_pf_if; // @[core.scala:174:24] wire bypasses_2_bits_uop_xcpt_ae_if; // @[core.scala:174:24] wire bypasses_2_bits_uop_xcpt_ma_if; // @[core.scala:174:24] wire bypasses_2_bits_uop_bp_debug_if; // @[core.scala:174:24] wire bypasses_2_bits_uop_bp_xcpt_if; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_debug_fsrc; // @[core.scala:174:24] wire [1:0] bypasses_2_bits_uop_debug_tsrc; // @[core.scala:174:24] wire [63:0] bypasses_2_bits_data; // @[core.scala:174:24] wire bypasses_2_valid; // @[core.scala:174:24] wire [3:0] bypasses_3_bits_uop_ctrl_br_type; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_ctrl_op1_sel; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_uop_ctrl_op2_sel; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_uop_ctrl_imm_sel; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_uop_ctrl_op_fcn; // @[core.scala:174:24] wire bypasses_3_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24] wire bypasses_3_bits_uop_ctrl_is_load; // @[core.scala:174:24] wire bypasses_3_bits_uop_ctrl_is_sta; // @[core.scala:174:24] wire bypasses_3_bits_uop_ctrl_is_std; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_uopc; // @[core.scala:174:24] wire [31:0] bypasses_3_bits_uop_inst; // @[core.scala:174:24] wire [31:0] bypasses_3_bits_uop_debug_inst; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_rvc; // @[core.scala:174:24] wire [39:0] bypasses_3_bits_uop_debug_pc; // @[core.scala:174:24] wire [2:0] bypasses_3_bits_uop_iq_type; // @[core.scala:174:24] wire [9:0] bypasses_3_bits_uop_fu_code; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_iw_state; // @[core.scala:174:24] wire bypasses_3_bits_uop_iw_p1_poisoned; // @[core.scala:174:24] wire bypasses_3_bits_uop_iw_p2_poisoned; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_br; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_jalr; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_jal; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_sfb; // @[core.scala:174:24] wire [15:0] bypasses_3_bits_uop_br_mask; // @[core.scala:174:24] wire [3:0] bypasses_3_bits_uop_br_tag; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_uop_ftq_idx; // @[core.scala:174:24] wire bypasses_3_bits_uop_edge_inst; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_uop_pc_lob; // @[core.scala:174:24] wire bypasses_3_bits_uop_taken; // @[core.scala:174:24] wire [19:0] bypasses_3_bits_uop_imm_packed; // @[core.scala:174:24] wire [11:0] bypasses_3_bits_uop_csr_addr; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_rob_idx; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_uop_ldq_idx; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_uop_stq_idx; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_rxq_idx; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_pdst; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_prs1; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_prs2; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_prs3; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_uop_ppred; // @[core.scala:174:24] wire bypasses_3_bits_uop_prs1_busy; // @[core.scala:174:24] wire bypasses_3_bits_uop_prs2_busy; // @[core.scala:174:24] wire bypasses_3_bits_uop_prs3_busy; // @[core.scala:174:24] wire bypasses_3_bits_uop_ppred_busy; // @[core.scala:174:24] wire [6:0] bypasses_3_bits_uop_stale_pdst; // @[core.scala:174:24] wire bypasses_3_bits_uop_exception; // @[core.scala:174:24] wire [63:0] bypasses_3_bits_uop_exc_cause; // @[core.scala:174:24] wire bypasses_3_bits_uop_bypassable; // @[core.scala:174:24] wire [4:0] bypasses_3_bits_uop_mem_cmd; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_mem_size; // @[core.scala:174:24] wire bypasses_3_bits_uop_mem_signed; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_fence; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_fencei; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_amo; // @[core.scala:174:24] wire bypasses_3_bits_uop_uses_ldq; // @[core.scala:174:24] wire bypasses_3_bits_uop_uses_stq; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_sys_pc2epc; // @[core.scala:174:24] wire bypasses_3_bits_uop_is_unique; // @[core.scala:174:24] wire bypasses_3_bits_uop_flush_on_commit; // @[core.scala:174:24] wire bypasses_3_bits_uop_ldst_is_rs1; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_uop_ldst; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_uop_lrs1; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_uop_lrs2; // @[core.scala:174:24] wire [5:0] bypasses_3_bits_uop_lrs3; // @[core.scala:174:24] wire bypasses_3_bits_uop_ldst_val; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_dst_rtype; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_lrs1_rtype; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_lrs2_rtype; // @[core.scala:174:24] wire bypasses_3_bits_uop_frs3_en; // @[core.scala:174:24] wire bypasses_3_bits_uop_fp_val; // @[core.scala:174:24] wire bypasses_3_bits_uop_fp_single; // @[core.scala:174:24] wire bypasses_3_bits_uop_xcpt_pf_if; // @[core.scala:174:24] wire bypasses_3_bits_uop_xcpt_ae_if; // @[core.scala:174:24] wire bypasses_3_bits_uop_xcpt_ma_if; // @[core.scala:174:24] wire bypasses_3_bits_uop_bp_debug_if; // @[core.scala:174:24] wire bypasses_3_bits_uop_bp_xcpt_if; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_debug_fsrc; // @[core.scala:174:24] wire [1:0] bypasses_3_bits_uop_debug_tsrc; // @[core.scala:174:24] wire [63:0] bypasses_3_bits_data; // @[core.scala:174:24] wire bypasses_3_valid; // @[core.scala:174:24] wire [3:0] bypasses_4_bits_uop_ctrl_br_type; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_ctrl_op1_sel; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_uop_ctrl_op2_sel; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_uop_ctrl_imm_sel; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_uop_ctrl_op_fcn; // @[core.scala:174:24] wire bypasses_4_bits_uop_ctrl_fcn_dw; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_uop_ctrl_csr_cmd; // @[core.scala:174:24] wire bypasses_4_bits_uop_ctrl_is_load; // @[core.scala:174:24] wire bypasses_4_bits_uop_ctrl_is_sta; // @[core.scala:174:24] wire bypasses_4_bits_uop_ctrl_is_std; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_uopc; // @[core.scala:174:24] wire [31:0] bypasses_4_bits_uop_inst; // @[core.scala:174:24] wire [31:0] bypasses_4_bits_uop_debug_inst; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_rvc; // @[core.scala:174:24] wire [39:0] bypasses_4_bits_uop_debug_pc; // @[core.scala:174:24] wire [2:0] bypasses_4_bits_uop_iq_type; // @[core.scala:174:24] wire [9:0] bypasses_4_bits_uop_fu_code; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_iw_state; // @[core.scala:174:24] wire bypasses_4_bits_uop_iw_p1_poisoned; // @[core.scala:174:24] wire bypasses_4_bits_uop_iw_p2_poisoned; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_br; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_jalr; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_jal; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_sfb; // @[core.scala:174:24] wire [15:0] bypasses_4_bits_uop_br_mask; // @[core.scala:174:24] wire [3:0] bypasses_4_bits_uop_br_tag; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_uop_ftq_idx; // @[core.scala:174:24] wire bypasses_4_bits_uop_edge_inst; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_uop_pc_lob; // @[core.scala:174:24] wire bypasses_4_bits_uop_taken; // @[core.scala:174:24] wire [19:0] bypasses_4_bits_uop_imm_packed; // @[core.scala:174:24] wire [11:0] bypasses_4_bits_uop_csr_addr; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_rob_idx; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_uop_ldq_idx; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_uop_stq_idx; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_rxq_idx; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_pdst; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_prs1; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_prs2; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_prs3; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_uop_ppred; // @[core.scala:174:24] wire bypasses_4_bits_uop_prs1_busy; // @[core.scala:174:24] wire bypasses_4_bits_uop_prs2_busy; // @[core.scala:174:24] wire bypasses_4_bits_uop_prs3_busy; // @[core.scala:174:24] wire bypasses_4_bits_uop_ppred_busy; // @[core.scala:174:24] wire [6:0] bypasses_4_bits_uop_stale_pdst; // @[core.scala:174:24] wire bypasses_4_bits_uop_exception; // @[core.scala:174:24] wire [63:0] bypasses_4_bits_uop_exc_cause; // @[core.scala:174:24] wire bypasses_4_bits_uop_bypassable; // @[core.scala:174:24] wire [4:0] bypasses_4_bits_uop_mem_cmd; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_mem_size; // @[core.scala:174:24] wire bypasses_4_bits_uop_mem_signed; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_fence; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_fencei; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_amo; // @[core.scala:174:24] wire bypasses_4_bits_uop_uses_ldq; // @[core.scala:174:24] wire bypasses_4_bits_uop_uses_stq; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_sys_pc2epc; // @[core.scala:174:24] wire bypasses_4_bits_uop_is_unique; // @[core.scala:174:24] wire bypasses_4_bits_uop_flush_on_commit; // @[core.scala:174:24] wire bypasses_4_bits_uop_ldst_is_rs1; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_uop_ldst; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_uop_lrs1; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_uop_lrs2; // @[core.scala:174:24] wire [5:0] bypasses_4_bits_uop_lrs3; // @[core.scala:174:24] wire bypasses_4_bits_uop_ldst_val; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_dst_rtype; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_lrs1_rtype; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_lrs2_rtype; // @[core.scala:174:24] wire bypasses_4_bits_uop_frs3_en; // @[core.scala:174:24] wire bypasses_4_bits_uop_fp_val; // @[core.scala:174:24] wire bypasses_4_bits_uop_fp_single; // @[core.scala:174:24] wire bypasses_4_bits_uop_xcpt_pf_if; // @[core.scala:174:24] wire bypasses_4_bits_uop_xcpt_ae_if; // @[core.scala:174:24] wire bypasses_4_bits_uop_xcpt_ma_if; // @[core.scala:174:24] wire bypasses_4_bits_uop_bp_debug_if; // @[core.scala:174:24] wire bypasses_4_bits_uop_bp_xcpt_if; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_debug_fsrc; // @[core.scala:174:24] wire [1:0] bypasses_4_bits_uop_debug_tsrc; // @[core.scala:174:24] wire [63:0] bypasses_4_bits_data; // @[core.scala:174:24] wire bypasses_4_valid; // @[core.scala:174:24] wire [3:0] pred_bypasses_0_bits_uop_ctrl_br_type; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_ctrl_op1_sel; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_uop_ctrl_op2_sel; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_uop_ctrl_imm_sel; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_uop_ctrl_op_fcn; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ctrl_fcn_dw; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_uop_ctrl_csr_cmd; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ctrl_is_load; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ctrl_is_sta; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ctrl_is_std; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_uopc; // @[core.scala:175:27] wire [31:0] pred_bypasses_0_bits_uop_inst; // @[core.scala:175:27] wire [31:0] pred_bypasses_0_bits_uop_debug_inst; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_rvc; // @[core.scala:175:27] wire [39:0] pred_bypasses_0_bits_uop_debug_pc; // @[core.scala:175:27] wire [2:0] pred_bypasses_0_bits_uop_iq_type; // @[core.scala:175:27] wire [9:0] pred_bypasses_0_bits_uop_fu_code; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_iw_state; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_iw_p1_poisoned; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_iw_p2_poisoned; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_br; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_jalr; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_jal; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_sfb; // @[core.scala:175:27] wire [15:0] pred_bypasses_0_bits_uop_br_mask; // @[core.scala:175:27] wire [3:0] pred_bypasses_0_bits_uop_br_tag; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_uop_ftq_idx; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_edge_inst; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_uop_pc_lob; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_taken; // @[core.scala:175:27] wire [19:0] pred_bypasses_0_bits_uop_imm_packed; // @[core.scala:175:27] wire [11:0] pred_bypasses_0_bits_uop_csr_addr; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_rob_idx; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_uop_ldq_idx; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_uop_stq_idx; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_rxq_idx; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_pdst; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_prs1; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_prs2; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_prs3; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_uop_ppred; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_prs1_busy; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_prs2_busy; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_prs3_busy; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ppred_busy; // @[core.scala:175:27] wire [6:0] pred_bypasses_0_bits_uop_stale_pdst; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_exception; // @[core.scala:175:27] wire [63:0] pred_bypasses_0_bits_uop_exc_cause; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_bypassable; // @[core.scala:175:27] wire [4:0] pred_bypasses_0_bits_uop_mem_cmd; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_mem_size; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_mem_signed; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_fence; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_fencei; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_amo; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_uses_ldq; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_uses_stq; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_sys_pc2epc; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_is_unique; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_flush_on_commit; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ldst_is_rs1; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_uop_ldst; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_uop_lrs1; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_uop_lrs2; // @[core.scala:175:27] wire [5:0] pred_bypasses_0_bits_uop_lrs3; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_ldst_val; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_dst_rtype; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_lrs1_rtype; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_lrs2_rtype; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_frs3_en; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_fp_val; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_fp_single; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_xcpt_pf_if; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_xcpt_ae_if; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_xcpt_ma_if; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_bp_debug_if; // @[core.scala:175:27] wire pred_bypasses_0_bits_uop_bp_xcpt_if; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_debug_fsrc; // @[core.scala:175:27] wire [1:0] pred_bypasses_0_bits_uop_debug_tsrc; // @[core.scala:175:27] wire pred_bypasses_0_bits_data; // @[core.scala:175:27] wire pred_bypasses_0_valid; // @[core.scala:175:27] reg [6:0] brinfos_0_uop_uopc; // @[core.scala:182:20] reg [31:0] brinfos_0_uop_inst; // @[core.scala:182:20] reg [31:0] brinfos_0_uop_debug_inst; // @[core.scala:182:20] reg brinfos_0_uop_is_rvc; // @[core.scala:182:20] reg [39:0] brinfos_0_uop_debug_pc; // @[core.scala:182:20] reg [2:0] brinfos_0_uop_iq_type; // @[core.scala:182:20] reg [9:0] brinfos_0_uop_fu_code; // @[core.scala:182:20] reg [3:0] brinfos_0_uop_ctrl_br_type; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_ctrl_op1_sel; // @[core.scala:182:20] reg [2:0] brinfos_0_uop_ctrl_op2_sel; // @[core.scala:182:20] reg [2:0] brinfos_0_uop_ctrl_imm_sel; // @[core.scala:182:20] reg [4:0] brinfos_0_uop_ctrl_op_fcn; // @[core.scala:182:20] reg brinfos_0_uop_ctrl_fcn_dw; // @[core.scala:182:20] reg [2:0] brinfos_0_uop_ctrl_csr_cmd; // @[core.scala:182:20] reg brinfos_0_uop_ctrl_is_load; // @[core.scala:182:20] reg brinfos_0_uop_ctrl_is_sta; // @[core.scala:182:20] reg brinfos_0_uop_ctrl_is_std; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_iw_state; // @[core.scala:182:20] reg brinfos_0_uop_iw_p1_poisoned; // @[core.scala:182:20] reg brinfos_0_uop_iw_p2_poisoned; // @[core.scala:182:20] reg brinfos_0_uop_is_br; // @[core.scala:182:20] reg brinfos_0_uop_is_jalr; // @[core.scala:182:20] reg brinfos_0_uop_is_jal; // @[core.scala:182:20] reg brinfos_0_uop_is_sfb; // @[core.scala:182:20] reg [15:0] brinfos_0_uop_br_mask; // @[core.scala:182:20] reg [3:0] brinfos_0_uop_br_tag; // @[core.scala:182:20] reg [4:0] brinfos_0_uop_ftq_idx; // @[core.scala:182:20] reg brinfos_0_uop_edge_inst; // @[core.scala:182:20] reg [5:0] brinfos_0_uop_pc_lob; // @[core.scala:182:20] reg brinfos_0_uop_taken; // @[core.scala:182:20] reg [19:0] brinfos_0_uop_imm_packed; // @[core.scala:182:20] reg [11:0] brinfos_0_uop_csr_addr; // @[core.scala:182:20] reg [6:0] brinfos_0_uop_rob_idx; // @[core.scala:182:20] reg [4:0] brinfos_0_uop_ldq_idx; // @[core.scala:182:20] reg [4:0] brinfos_0_uop_stq_idx; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_rxq_idx; // @[core.scala:182:20] reg [6:0] brinfos_0_uop_pdst; // @[core.scala:182:20] reg [6:0] brinfos_0_uop_prs1; // @[core.scala:182:20] reg [6:0] brinfos_0_uop_prs2; // @[core.scala:182:20] reg [6:0] brinfos_0_uop_prs3; // @[core.scala:182:20] reg [4:0] brinfos_0_uop_ppred; // @[core.scala:182:20] reg brinfos_0_uop_prs1_busy; // @[core.scala:182:20] reg brinfos_0_uop_prs2_busy; // @[core.scala:182:20] reg brinfos_0_uop_prs3_busy; // @[core.scala:182:20] reg brinfos_0_uop_ppred_busy; // @[core.scala:182:20] reg [6:0] brinfos_0_uop_stale_pdst; // @[core.scala:182:20] reg brinfos_0_uop_exception; // @[core.scala:182:20] reg [63:0] brinfos_0_uop_exc_cause; // @[core.scala:182:20] reg brinfos_0_uop_bypassable; // @[core.scala:182:20] reg [4:0] brinfos_0_uop_mem_cmd; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_mem_size; // @[core.scala:182:20] reg brinfos_0_uop_mem_signed; // @[core.scala:182:20] reg brinfos_0_uop_is_fence; // @[core.scala:182:20] reg brinfos_0_uop_is_fencei; // @[core.scala:182:20] reg brinfos_0_uop_is_amo; // @[core.scala:182:20] reg brinfos_0_uop_uses_ldq; // @[core.scala:182:20] reg brinfos_0_uop_uses_stq; // @[core.scala:182:20] reg brinfos_0_uop_is_sys_pc2epc; // @[core.scala:182:20] reg brinfos_0_uop_is_unique; // @[core.scala:182:20] reg brinfos_0_uop_flush_on_commit; // @[core.scala:182:20] reg brinfos_0_uop_ldst_is_rs1; // @[core.scala:182:20] reg [5:0] brinfos_0_uop_ldst; // @[core.scala:182:20] reg [5:0] brinfos_0_uop_lrs1; // @[core.scala:182:20] reg [5:0] brinfos_0_uop_lrs2; // @[core.scala:182:20] reg [5:0] brinfos_0_uop_lrs3; // @[core.scala:182:20] reg brinfos_0_uop_ldst_val; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_dst_rtype; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_lrs1_rtype; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_lrs2_rtype; // @[core.scala:182:20] reg brinfos_0_uop_frs3_en; // @[core.scala:182:20] reg brinfos_0_uop_fp_val; // @[core.scala:182:20] reg brinfos_0_uop_fp_single; // @[core.scala:182:20] reg brinfos_0_uop_xcpt_pf_if; // @[core.scala:182:20] reg brinfos_0_uop_xcpt_ae_if; // @[core.scala:182:20] reg brinfos_0_uop_xcpt_ma_if; // @[core.scala:182:20] reg brinfos_0_uop_bp_debug_if; // @[core.scala:182:20] reg brinfos_0_uop_bp_xcpt_if; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_debug_fsrc; // @[core.scala:182:20] reg [1:0] brinfos_0_uop_debug_tsrc; // @[core.scala:182:20] reg brinfos_0_valid; // @[core.scala:182:20] reg brinfos_0_mispredict; // @[core.scala:182:20] reg brinfos_0_taken; // @[core.scala:182:20] reg [2:0] brinfos_0_cfi_type; // @[core.scala:182:20] reg [1:0] brinfos_0_pc_sel; // @[core.scala:182:20] reg [39:0] brinfos_0_jalr_target; // @[core.scala:182:20] reg [20:0] brinfos_0_target_offset; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_uopc; // @[core.scala:182:20] reg [31:0] brinfos_1_uop_inst; // @[core.scala:182:20] reg [31:0] brinfos_1_uop_debug_inst; // @[core.scala:182:20] reg brinfos_1_uop_is_rvc; // @[core.scala:182:20] reg [39:0] brinfos_1_uop_debug_pc; // @[core.scala:182:20] reg [2:0] brinfos_1_uop_iq_type; // @[core.scala:182:20] reg [9:0] brinfos_1_uop_fu_code; // @[core.scala:182:20] reg [3:0] brinfos_1_uop_ctrl_br_type; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_ctrl_op1_sel; // @[core.scala:182:20] reg [2:0] brinfos_1_uop_ctrl_op2_sel; // @[core.scala:182:20] reg [2:0] brinfos_1_uop_ctrl_imm_sel; // @[core.scala:182:20] reg [4:0] brinfos_1_uop_ctrl_op_fcn; // @[core.scala:182:20] reg brinfos_1_uop_ctrl_fcn_dw; // @[core.scala:182:20] reg [2:0] brinfos_1_uop_ctrl_csr_cmd; // @[core.scala:182:20] reg brinfos_1_uop_ctrl_is_load; // @[core.scala:182:20] reg brinfos_1_uop_ctrl_is_sta; // @[core.scala:182:20] reg brinfos_1_uop_ctrl_is_std; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_iw_state; // @[core.scala:182:20] reg brinfos_1_uop_iw_p1_poisoned; // @[core.scala:182:20] reg brinfos_1_uop_iw_p2_poisoned; // @[core.scala:182:20] reg brinfos_1_uop_is_br; // @[core.scala:182:20] reg brinfos_1_uop_is_jalr; // @[core.scala:182:20] reg brinfos_1_uop_is_jal; // @[core.scala:182:20] reg brinfos_1_uop_is_sfb; // @[core.scala:182:20] reg [15:0] brinfos_1_uop_br_mask; // @[core.scala:182:20] reg [3:0] brinfos_1_uop_br_tag; // @[core.scala:182:20] reg [4:0] brinfos_1_uop_ftq_idx; // @[core.scala:182:20] reg brinfos_1_uop_edge_inst; // @[core.scala:182:20] reg [5:0] brinfos_1_uop_pc_lob; // @[core.scala:182:20] reg brinfos_1_uop_taken; // @[core.scala:182:20] reg [19:0] brinfos_1_uop_imm_packed; // @[core.scala:182:20] reg [11:0] brinfos_1_uop_csr_addr; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_rob_idx; // @[core.scala:182:20] reg [4:0] brinfos_1_uop_ldq_idx; // @[core.scala:182:20] reg [4:0] brinfos_1_uop_stq_idx; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_rxq_idx; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_pdst; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_prs1; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_prs2; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_prs3; // @[core.scala:182:20] reg [4:0] brinfos_1_uop_ppred; // @[core.scala:182:20] reg brinfos_1_uop_prs1_busy; // @[core.scala:182:20] reg brinfos_1_uop_prs2_busy; // @[core.scala:182:20] reg brinfos_1_uop_prs3_busy; // @[core.scala:182:20] reg brinfos_1_uop_ppred_busy; // @[core.scala:182:20] reg [6:0] brinfos_1_uop_stale_pdst; // @[core.scala:182:20] reg brinfos_1_uop_exception; // @[core.scala:182:20] reg [63:0] brinfos_1_uop_exc_cause; // @[core.scala:182:20] reg brinfos_1_uop_bypassable; // @[core.scala:182:20] reg [4:0] brinfos_1_uop_mem_cmd; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_mem_size; // @[core.scala:182:20] reg brinfos_1_uop_mem_signed; // @[core.scala:182:20] reg brinfos_1_uop_is_fence; // @[core.scala:182:20] reg brinfos_1_uop_is_fencei; // @[core.scala:182:20] reg brinfos_1_uop_is_amo; // @[core.scala:182:20] reg brinfos_1_uop_uses_ldq; // @[core.scala:182:20] reg brinfos_1_uop_uses_stq; // @[core.scala:182:20] reg brinfos_1_uop_is_sys_pc2epc; // @[core.scala:182:20] reg brinfos_1_uop_is_unique; // @[core.scala:182:20] reg brinfos_1_uop_flush_on_commit; // @[core.scala:182:20] reg brinfos_1_uop_ldst_is_rs1; // @[core.scala:182:20] reg [5:0] brinfos_1_uop_ldst; // @[core.scala:182:20] reg [5:0] brinfos_1_uop_lrs1; // @[core.scala:182:20] reg [5:0] brinfos_1_uop_lrs2; // @[core.scala:182:20] reg [5:0] brinfos_1_uop_lrs3; // @[core.scala:182:20] reg brinfos_1_uop_ldst_val; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_dst_rtype; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_lrs1_rtype; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_lrs2_rtype; // @[core.scala:182:20] reg brinfos_1_uop_frs3_en; // @[core.scala:182:20] reg brinfos_1_uop_fp_val; // @[core.scala:182:20] reg brinfos_1_uop_fp_single; // @[core.scala:182:20] reg brinfos_1_uop_xcpt_pf_if; // @[core.scala:182:20] reg brinfos_1_uop_xcpt_ae_if; // @[core.scala:182:20] reg brinfos_1_uop_xcpt_ma_if; // @[core.scala:182:20] reg brinfos_1_uop_bp_debug_if; // @[core.scala:182:20] reg brinfos_1_uop_bp_xcpt_if; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_debug_fsrc; // @[core.scala:182:20] reg [1:0] brinfos_1_uop_debug_tsrc; // @[core.scala:182:20] reg brinfos_1_valid; // @[core.scala:182:20] reg brinfos_1_mispredict; // @[core.scala:182:20] reg brinfos_1_taken; // @[core.scala:182:20] reg [2:0] brinfos_1_cfi_type; // @[core.scala:182:20] reg [1:0] brinfos_1_pc_sel; // @[core.scala:182:20] reg [20:0] brinfos_1_target_offset; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_uopc; // @[core.scala:182:20] reg [31:0] brinfos_2_uop_inst; // @[core.scala:182:20] reg [31:0] brinfos_2_uop_debug_inst; // @[core.scala:182:20] reg brinfos_2_uop_is_rvc; // @[core.scala:182:20] reg [39:0] brinfos_2_uop_debug_pc; // @[core.scala:182:20] reg [2:0] brinfos_2_uop_iq_type; // @[core.scala:182:20] reg [9:0] brinfos_2_uop_fu_code; // @[core.scala:182:20] reg [3:0] brinfos_2_uop_ctrl_br_type; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_ctrl_op1_sel; // @[core.scala:182:20] reg [2:0] brinfos_2_uop_ctrl_op2_sel; // @[core.scala:182:20] reg [2:0] brinfos_2_uop_ctrl_imm_sel; // @[core.scala:182:20] reg [4:0] brinfos_2_uop_ctrl_op_fcn; // @[core.scala:182:20] reg brinfos_2_uop_ctrl_fcn_dw; // @[core.scala:182:20] reg [2:0] brinfos_2_uop_ctrl_csr_cmd; // @[core.scala:182:20] reg brinfos_2_uop_ctrl_is_load; // @[core.scala:182:20] reg brinfos_2_uop_ctrl_is_sta; // @[core.scala:182:20] reg brinfos_2_uop_ctrl_is_std; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_iw_state; // @[core.scala:182:20] reg brinfos_2_uop_iw_p1_poisoned; // @[core.scala:182:20] reg brinfos_2_uop_iw_p2_poisoned; // @[core.scala:182:20] reg brinfos_2_uop_is_br; // @[core.scala:182:20] reg brinfos_2_uop_is_jalr; // @[core.scala:182:20] reg brinfos_2_uop_is_jal; // @[core.scala:182:20] reg brinfos_2_uop_is_sfb; // @[core.scala:182:20] reg [15:0] brinfos_2_uop_br_mask; // @[core.scala:182:20] reg [3:0] brinfos_2_uop_br_tag; // @[core.scala:182:20] reg [4:0] brinfos_2_uop_ftq_idx; // @[core.scala:182:20] reg brinfos_2_uop_edge_inst; // @[core.scala:182:20] reg [5:0] brinfos_2_uop_pc_lob; // @[core.scala:182:20] reg brinfos_2_uop_taken; // @[core.scala:182:20] reg [19:0] brinfos_2_uop_imm_packed; // @[core.scala:182:20] reg [11:0] brinfos_2_uop_csr_addr; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_rob_idx; // @[core.scala:182:20] reg [4:0] brinfos_2_uop_ldq_idx; // @[core.scala:182:20] reg [4:0] brinfos_2_uop_stq_idx; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_rxq_idx; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_pdst; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_prs1; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_prs2; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_prs3; // @[core.scala:182:20] reg [4:0] brinfos_2_uop_ppred; // @[core.scala:182:20] reg brinfos_2_uop_prs1_busy; // @[core.scala:182:20] reg brinfos_2_uop_prs2_busy; // @[core.scala:182:20] reg brinfos_2_uop_prs3_busy; // @[core.scala:182:20] reg brinfos_2_uop_ppred_busy; // @[core.scala:182:20] reg [6:0] brinfos_2_uop_stale_pdst; // @[core.scala:182:20] reg brinfos_2_uop_exception; // @[core.scala:182:20] reg [63:0] brinfos_2_uop_exc_cause; // @[core.scala:182:20] reg brinfos_2_uop_bypassable; // @[core.scala:182:20] reg [4:0] brinfos_2_uop_mem_cmd; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_mem_size; // @[core.scala:182:20] reg brinfos_2_uop_mem_signed; // @[core.scala:182:20] reg brinfos_2_uop_is_fence; // @[core.scala:182:20] reg brinfos_2_uop_is_fencei; // @[core.scala:182:20] reg brinfos_2_uop_is_amo; // @[core.scala:182:20] reg brinfos_2_uop_uses_ldq; // @[core.scala:182:20] reg brinfos_2_uop_uses_stq; // @[core.scala:182:20] reg brinfos_2_uop_is_sys_pc2epc; // @[core.scala:182:20] reg brinfos_2_uop_is_unique; // @[core.scala:182:20] reg brinfos_2_uop_flush_on_commit; // @[core.scala:182:20] reg brinfos_2_uop_ldst_is_rs1; // @[core.scala:182:20] reg [5:0] brinfos_2_uop_ldst; // @[core.scala:182:20] reg [5:0] brinfos_2_uop_lrs1; // @[core.scala:182:20] reg [5:0] brinfos_2_uop_lrs2; // @[core.scala:182:20] reg [5:0] brinfos_2_uop_lrs3; // @[core.scala:182:20] reg brinfos_2_uop_ldst_val; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_dst_rtype; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_lrs1_rtype; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_lrs2_rtype; // @[core.scala:182:20] reg brinfos_2_uop_frs3_en; // @[core.scala:182:20] reg brinfos_2_uop_fp_val; // @[core.scala:182:20] reg brinfos_2_uop_fp_single; // @[core.scala:182:20] reg brinfos_2_uop_xcpt_pf_if; // @[core.scala:182:20] reg brinfos_2_uop_xcpt_ae_if; // @[core.scala:182:20] reg brinfos_2_uop_xcpt_ma_if; // @[core.scala:182:20] reg brinfos_2_uop_bp_debug_if; // @[core.scala:182:20] reg brinfos_2_uop_bp_xcpt_if; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_debug_fsrc; // @[core.scala:182:20] reg [1:0] brinfos_2_uop_debug_tsrc; // @[core.scala:182:20] reg brinfos_2_valid; // @[core.scala:182:20] reg brinfos_2_mispredict; // @[core.scala:182:20] reg brinfos_2_taken; // @[core.scala:182:20] reg [2:0] brinfos_2_cfi_type; // @[core.scala:182:20] reg [1:0] brinfos_2_pc_sel; // @[core.scala:182:20] reg [20:0] brinfos_2_target_offset; // @[core.scala:182:20] wire [15:0] b1_resolve_mask; // @[core.scala:189:19] assign io_ifu_brupdate_b1_resolve_mask_0 = brupdate_b1_resolve_mask; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b1_resolve_mask_0 = brupdate_b1_resolve_mask; // @[core.scala:51:7, :188:23] wire [15:0] b1_mispredict_mask; // @[core.scala:189:19] assign io_ifu_brupdate_b1_mispredict_mask_0 = brupdate_b1_mispredict_mask; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b1_mispredict_mask_0 = brupdate_b1_mispredict_mask; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_uopc_0 = brupdate_b2_uop_uopc; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_uopc_0 = brupdate_b2_uop_uopc; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_inst_0 = brupdate_b2_uop_inst; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_inst_0 = brupdate_b2_uop_inst; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_debug_inst_0 = brupdate_b2_uop_debug_inst; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_debug_inst_0 = brupdate_b2_uop_debug_inst; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_rvc_0 = brupdate_b2_uop_is_rvc; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_rvc_0 = brupdate_b2_uop_is_rvc; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_debug_pc_0 = brupdate_b2_uop_debug_pc; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_debug_pc_0 = brupdate_b2_uop_debug_pc; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_iq_type_0 = brupdate_b2_uop_iq_type; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_iq_type_0 = brupdate_b2_uop_iq_type; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_fu_code_0 = brupdate_b2_uop_fu_code; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_fu_code_0 = brupdate_b2_uop_fu_code; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_br_type_0 = brupdate_b2_uop_ctrl_br_type; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_br_type_0 = brupdate_b2_uop_ctrl_br_type; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_op1_sel_0 = brupdate_b2_uop_ctrl_op1_sel; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_op1_sel_0 = brupdate_b2_uop_ctrl_op1_sel; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_op2_sel_0 = brupdate_b2_uop_ctrl_op2_sel; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_op2_sel_0 = brupdate_b2_uop_ctrl_op2_sel; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_imm_sel_0 = brupdate_b2_uop_ctrl_imm_sel; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_imm_sel_0 = brupdate_b2_uop_ctrl_imm_sel; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_op_fcn_0 = brupdate_b2_uop_ctrl_op_fcn; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_op_fcn_0 = brupdate_b2_uop_ctrl_op_fcn; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_fcn_dw_0 = brupdate_b2_uop_ctrl_fcn_dw; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_fcn_dw_0 = brupdate_b2_uop_ctrl_fcn_dw; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_csr_cmd_0 = brupdate_b2_uop_ctrl_csr_cmd; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_csr_cmd_0 = brupdate_b2_uop_ctrl_csr_cmd; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_is_load_0 = brupdate_b2_uop_ctrl_is_load; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_is_load_0 = brupdate_b2_uop_ctrl_is_load; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_is_sta_0 = brupdate_b2_uop_ctrl_is_sta; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_is_sta_0 = brupdate_b2_uop_ctrl_is_sta; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ctrl_is_std_0 = brupdate_b2_uop_ctrl_is_std; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ctrl_is_std_0 = brupdate_b2_uop_ctrl_is_std; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_iw_state_0 = brupdate_b2_uop_iw_state; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_iw_state_0 = brupdate_b2_uop_iw_state; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_iw_p1_poisoned_0 = brupdate_b2_uop_iw_p1_poisoned; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_iw_p1_poisoned_0 = brupdate_b2_uop_iw_p1_poisoned; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_iw_p2_poisoned_0 = brupdate_b2_uop_iw_p2_poisoned; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_iw_p2_poisoned_0 = brupdate_b2_uop_iw_p2_poisoned; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_br_0 = brupdate_b2_uop_is_br; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_br_0 = brupdate_b2_uop_is_br; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_jalr_0 = brupdate_b2_uop_is_jalr; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_jalr_0 = brupdate_b2_uop_is_jalr; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_jal_0 = brupdate_b2_uop_is_jal; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_jal_0 = brupdate_b2_uop_is_jal; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_sfb_0 = brupdate_b2_uop_is_sfb; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_sfb_0 = brupdate_b2_uop_is_sfb; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_br_mask_0 = brupdate_b2_uop_br_mask; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_br_mask_0 = brupdate_b2_uop_br_mask; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_br_tag_0 = brupdate_b2_uop_br_tag; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_br_tag_0 = brupdate_b2_uop_br_tag; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ftq_idx_0 = brupdate_b2_uop_ftq_idx; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ftq_idx_0 = brupdate_b2_uop_ftq_idx; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_edge_inst_0 = brupdate_b2_uop_edge_inst; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_edge_inst_0 = brupdate_b2_uop_edge_inst; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_pc_lob_0 = brupdate_b2_uop_pc_lob; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_pc_lob_0 = brupdate_b2_uop_pc_lob; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_taken_0 = brupdate_b2_uop_taken; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_taken_0 = brupdate_b2_uop_taken; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_imm_packed_0 = brupdate_b2_uop_imm_packed; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_imm_packed_0 = brupdate_b2_uop_imm_packed; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_csr_addr_0 = brupdate_b2_uop_csr_addr; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_csr_addr_0 = brupdate_b2_uop_csr_addr; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_rob_idx_0 = brupdate_b2_uop_rob_idx; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_rob_idx_0 = brupdate_b2_uop_rob_idx; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ldq_idx_0 = brupdate_b2_uop_ldq_idx; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ldq_idx_0 = brupdate_b2_uop_ldq_idx; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_stq_idx_0 = brupdate_b2_uop_stq_idx; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_stq_idx_0 = brupdate_b2_uop_stq_idx; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_rxq_idx_0 = brupdate_b2_uop_rxq_idx; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_rxq_idx_0 = brupdate_b2_uop_rxq_idx; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_pdst_0 = brupdate_b2_uop_pdst; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_pdst_0 = brupdate_b2_uop_pdst; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_prs1_0 = brupdate_b2_uop_prs1; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_prs1_0 = brupdate_b2_uop_prs1; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_prs2_0 = brupdate_b2_uop_prs2; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_prs2_0 = brupdate_b2_uop_prs2; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_prs3_0 = brupdate_b2_uop_prs3; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_prs3_0 = brupdate_b2_uop_prs3; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ppred_0 = brupdate_b2_uop_ppred; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ppred_0 = brupdate_b2_uop_ppred; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_prs1_busy_0 = brupdate_b2_uop_prs1_busy; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_prs1_busy_0 = brupdate_b2_uop_prs1_busy; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_prs2_busy_0 = brupdate_b2_uop_prs2_busy; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_prs2_busy_0 = brupdate_b2_uop_prs2_busy; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_prs3_busy_0 = brupdate_b2_uop_prs3_busy; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_prs3_busy_0 = brupdate_b2_uop_prs3_busy; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ppred_busy_0 = brupdate_b2_uop_ppred_busy; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ppred_busy_0 = brupdate_b2_uop_ppred_busy; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_stale_pdst_0 = brupdate_b2_uop_stale_pdst; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_stale_pdst_0 = brupdate_b2_uop_stale_pdst; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_exception_0 = brupdate_b2_uop_exception; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_exception_0 = brupdate_b2_uop_exception; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_exc_cause_0 = brupdate_b2_uop_exc_cause; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_exc_cause_0 = brupdate_b2_uop_exc_cause; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_bypassable_0 = brupdate_b2_uop_bypassable; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_bypassable_0 = brupdate_b2_uop_bypassable; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_mem_cmd_0 = brupdate_b2_uop_mem_cmd; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_mem_cmd_0 = brupdate_b2_uop_mem_cmd; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_mem_size_0 = brupdate_b2_uop_mem_size; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_mem_size_0 = brupdate_b2_uop_mem_size; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_mem_signed_0 = brupdate_b2_uop_mem_signed; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_mem_signed_0 = brupdate_b2_uop_mem_signed; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_fence_0 = brupdate_b2_uop_is_fence; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_fence_0 = brupdate_b2_uop_is_fence; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_fencei_0 = brupdate_b2_uop_is_fencei; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_fencei_0 = brupdate_b2_uop_is_fencei; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_amo_0 = brupdate_b2_uop_is_amo; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_amo_0 = brupdate_b2_uop_is_amo; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_uses_ldq_0 = brupdate_b2_uop_uses_ldq; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_uses_ldq_0 = brupdate_b2_uop_uses_ldq; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_uses_stq_0 = brupdate_b2_uop_uses_stq; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_uses_stq_0 = brupdate_b2_uop_uses_stq; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_sys_pc2epc_0 = brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_sys_pc2epc_0 = brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_is_unique_0 = brupdate_b2_uop_is_unique; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_is_unique_0 = brupdate_b2_uop_is_unique; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_flush_on_commit_0 = brupdate_b2_uop_flush_on_commit; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_flush_on_commit_0 = brupdate_b2_uop_flush_on_commit; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ldst_is_rs1_0 = brupdate_b2_uop_ldst_is_rs1; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ldst_is_rs1_0 = brupdate_b2_uop_ldst_is_rs1; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ldst_0 = brupdate_b2_uop_ldst; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ldst_0 = brupdate_b2_uop_ldst; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_lrs1_0 = brupdate_b2_uop_lrs1; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_lrs1_0 = brupdate_b2_uop_lrs1; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_lrs2_0 = brupdate_b2_uop_lrs2; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_lrs2_0 = brupdate_b2_uop_lrs2; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_lrs3_0 = brupdate_b2_uop_lrs3; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_lrs3_0 = brupdate_b2_uop_lrs3; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_ldst_val_0 = brupdate_b2_uop_ldst_val; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_ldst_val_0 = brupdate_b2_uop_ldst_val; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_dst_rtype_0 = brupdate_b2_uop_dst_rtype; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_dst_rtype_0 = brupdate_b2_uop_dst_rtype; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_lrs1_rtype_0 = brupdate_b2_uop_lrs1_rtype; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_lrs1_rtype_0 = brupdate_b2_uop_lrs1_rtype; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_lrs2_rtype_0 = brupdate_b2_uop_lrs2_rtype; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_lrs2_rtype_0 = brupdate_b2_uop_lrs2_rtype; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_frs3_en_0 = brupdate_b2_uop_frs3_en; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_frs3_en_0 = brupdate_b2_uop_frs3_en; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_fp_val_0 = brupdate_b2_uop_fp_val; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_fp_val_0 = brupdate_b2_uop_fp_val; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_fp_single_0 = brupdate_b2_uop_fp_single; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_fp_single_0 = brupdate_b2_uop_fp_single; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_xcpt_pf_if_0 = brupdate_b2_uop_xcpt_pf_if; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_xcpt_pf_if_0 = brupdate_b2_uop_xcpt_pf_if; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_xcpt_ae_if_0 = brupdate_b2_uop_xcpt_ae_if; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_xcpt_ae_if_0 = brupdate_b2_uop_xcpt_ae_if; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_xcpt_ma_if_0 = brupdate_b2_uop_xcpt_ma_if; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_xcpt_ma_if_0 = brupdate_b2_uop_xcpt_ma_if; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_bp_debug_if_0 = brupdate_b2_uop_bp_debug_if; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_bp_debug_if_0 = brupdate_b2_uop_bp_debug_if; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_bp_xcpt_if_0 = brupdate_b2_uop_bp_xcpt_if; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_bp_xcpt_if_0 = brupdate_b2_uop_bp_xcpt_if; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_debug_fsrc_0 = brupdate_b2_uop_debug_fsrc; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_debug_fsrc_0 = brupdate_b2_uop_debug_fsrc; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_uop_debug_tsrc_0 = brupdate_b2_uop_debug_tsrc; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_uop_debug_tsrc_0 = brupdate_b2_uop_debug_tsrc; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_valid_0 = brupdate_b2_valid; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_valid_0 = brupdate_b2_valid; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_mispredict_0 = brupdate_b2_mispredict; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_mispredict_0 = brupdate_b2_mispredict; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_taken_0 = brupdate_b2_taken; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_taken_0 = brupdate_b2_taken; // @[core.scala:51:7, :188:23] wire _next_ghist_cfi_in_bank_0_T = brupdate_b2_taken; // @[frontend.scala:104:37] wire _next_ghist_new_history_new_saw_branch_taken_T_1 = brupdate_b2_taken; // @[frontend.scala:119:59] assign io_ifu_brupdate_b2_cfi_type_0 = brupdate_b2_cfi_type; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_cfi_type_0 = brupdate_b2_cfi_type; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_pc_sel_0 = brupdate_b2_pc_sel; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_pc_sel_0 = brupdate_b2_pc_sel; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_jalr_target_0 = brupdate_b2_jalr_target; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_jalr_target_0 = brupdate_b2_jalr_target; // @[core.scala:51:7, :188:23] assign io_ifu_brupdate_b2_target_offset_0 = brupdate_b2_target_offset; // @[core.scala:51:7, :188:23] assign io_lsu_brupdate_b2_target_offset_0 = brupdate_b2_target_offset; // @[core.scala:51:7, :188:23] wire [15:0] _b1_resolve_mask_T_4; // @[core.scala:199:72] assign brupdate_b1_resolve_mask = b1_resolve_mask; // @[core.scala:188:23, :189:19] wire [15:0] _b1_mispredict_mask_T_7; // @[core.scala:200:93] assign brupdate_b1_mispredict_mask = b1_mispredict_mask; // @[core.scala:188:23, :189:19] reg [6:0] b2_uop_uopc; // @[core.scala:190:18] assign brupdate_b2_uop_uopc = b2_uop_uopc; // @[core.scala:188:23, :190:18] reg [31:0] b2_uop_inst; // @[core.scala:190:18] assign brupdate_b2_uop_inst = b2_uop_inst; // @[core.scala:188:23, :190:18] reg [31:0] b2_uop_debug_inst; // @[core.scala:190:18] assign brupdate_b2_uop_debug_inst = b2_uop_debug_inst; // @[core.scala:188:23, :190:18] reg b2_uop_is_rvc; // @[core.scala:190:18] assign brupdate_b2_uop_is_rvc = b2_uop_is_rvc; // @[core.scala:188:23, :190:18] reg [39:0] b2_uop_debug_pc; // @[core.scala:190:18] assign brupdate_b2_uop_debug_pc = b2_uop_debug_pc; // @[core.scala:188:23, :190:18] reg [2:0] b2_uop_iq_type; // @[core.scala:190:18] assign brupdate_b2_uop_iq_type = b2_uop_iq_type; // @[core.scala:188:23, :190:18] reg [9:0] b2_uop_fu_code; // @[core.scala:190:18] assign brupdate_b2_uop_fu_code = b2_uop_fu_code; // @[core.scala:188:23, :190:18] reg [3:0] b2_uop_ctrl_br_type; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_br_type = b2_uop_ctrl_br_type; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_ctrl_op1_sel; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_op1_sel = b2_uop_ctrl_op1_sel; // @[core.scala:188:23, :190:18] reg [2:0] b2_uop_ctrl_op2_sel; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_op2_sel = b2_uop_ctrl_op2_sel; // @[core.scala:188:23, :190:18] reg [2:0] b2_uop_ctrl_imm_sel; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_imm_sel = b2_uop_ctrl_imm_sel; // @[core.scala:188:23, :190:18] reg [4:0] b2_uop_ctrl_op_fcn; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_op_fcn = b2_uop_ctrl_op_fcn; // @[core.scala:188:23, :190:18] reg b2_uop_ctrl_fcn_dw; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_fcn_dw = b2_uop_ctrl_fcn_dw; // @[core.scala:188:23, :190:18] reg [2:0] b2_uop_ctrl_csr_cmd; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_csr_cmd = b2_uop_ctrl_csr_cmd; // @[core.scala:188:23, :190:18] reg b2_uop_ctrl_is_load; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_is_load = b2_uop_ctrl_is_load; // @[core.scala:188:23, :190:18] reg b2_uop_ctrl_is_sta; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_is_sta = b2_uop_ctrl_is_sta; // @[core.scala:188:23, :190:18] reg b2_uop_ctrl_is_std; // @[core.scala:190:18] assign brupdate_b2_uop_ctrl_is_std = b2_uop_ctrl_is_std; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_iw_state; // @[core.scala:190:18] assign brupdate_b2_uop_iw_state = b2_uop_iw_state; // @[core.scala:188:23, :190:18] reg b2_uop_iw_p1_poisoned; // @[core.scala:190:18] assign brupdate_b2_uop_iw_p1_poisoned = b2_uop_iw_p1_poisoned; // @[core.scala:188:23, :190:18] reg b2_uop_iw_p2_poisoned; // @[core.scala:190:18] assign brupdate_b2_uop_iw_p2_poisoned = b2_uop_iw_p2_poisoned; // @[core.scala:188:23, :190:18] reg b2_uop_is_br; // @[core.scala:190:18] assign brupdate_b2_uop_is_br = b2_uop_is_br; // @[core.scala:188:23, :190:18] reg b2_uop_is_jalr; // @[core.scala:190:18] assign brupdate_b2_uop_is_jalr = b2_uop_is_jalr; // @[core.scala:188:23, :190:18] reg b2_uop_is_jal; // @[core.scala:190:18] assign brupdate_b2_uop_is_jal = b2_uop_is_jal; // @[core.scala:188:23, :190:18] reg b2_uop_is_sfb; // @[core.scala:190:18] assign brupdate_b2_uop_is_sfb = b2_uop_is_sfb; // @[core.scala:188:23, :190:18] reg [15:0] b2_uop_br_mask; // @[core.scala:190:18] assign brupdate_b2_uop_br_mask = b2_uop_br_mask; // @[core.scala:188:23, :190:18] reg [3:0] b2_uop_br_tag; // @[core.scala:190:18] assign brupdate_b2_uop_br_tag = b2_uop_br_tag; // @[core.scala:188:23, :190:18] reg [4:0] b2_uop_ftq_idx; // @[core.scala:190:18] assign brupdate_b2_uop_ftq_idx = b2_uop_ftq_idx; // @[core.scala:188:23, :190:18] reg b2_uop_edge_inst; // @[core.scala:190:18] assign brupdate_b2_uop_edge_inst = b2_uop_edge_inst; // @[core.scala:188:23, :190:18] reg [5:0] b2_uop_pc_lob; // @[core.scala:190:18] assign brupdate_b2_uop_pc_lob = b2_uop_pc_lob; // @[core.scala:188:23, :190:18] reg b2_uop_taken; // @[core.scala:190:18] assign brupdate_b2_uop_taken = b2_uop_taken; // @[core.scala:188:23, :190:18] reg [19:0] b2_uop_imm_packed; // @[core.scala:190:18] assign brupdate_b2_uop_imm_packed = b2_uop_imm_packed; // @[core.scala:188:23, :190:18] reg [11:0] b2_uop_csr_addr; // @[core.scala:190:18] assign brupdate_b2_uop_csr_addr = b2_uop_csr_addr; // @[core.scala:188:23, :190:18] reg [6:0] b2_uop_rob_idx; // @[core.scala:190:18] assign brupdate_b2_uop_rob_idx = b2_uop_rob_idx; // @[core.scala:188:23, :190:18] reg [4:0] b2_uop_ldq_idx; // @[core.scala:190:18] assign brupdate_b2_uop_ldq_idx = b2_uop_ldq_idx; // @[core.scala:188:23, :190:18] reg [4:0] b2_uop_stq_idx; // @[core.scala:190:18] assign brupdate_b2_uop_stq_idx = b2_uop_stq_idx; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_rxq_idx; // @[core.scala:190:18] assign brupdate_b2_uop_rxq_idx = b2_uop_rxq_idx; // @[core.scala:188:23, :190:18] reg [6:0] b2_uop_pdst; // @[core.scala:190:18] assign brupdate_b2_uop_pdst = b2_uop_pdst; // @[core.scala:188:23, :190:18] reg [6:0] b2_uop_prs1; // @[core.scala:190:18] assign brupdate_b2_uop_prs1 = b2_uop_prs1; // @[core.scala:188:23, :190:18] reg [6:0] b2_uop_prs2; // @[core.scala:190:18] assign brupdate_b2_uop_prs2 = b2_uop_prs2; // @[core.scala:188:23, :190:18] reg [6:0] b2_uop_prs3; // @[core.scala:190:18] assign brupdate_b2_uop_prs3 = b2_uop_prs3; // @[core.scala:188:23, :190:18] reg [4:0] b2_uop_ppred; // @[core.scala:190:18] assign brupdate_b2_uop_ppred = b2_uop_ppred; // @[core.scala:188:23, :190:18] reg b2_uop_prs1_busy; // @[core.scala:190:18] assign brupdate_b2_uop_prs1_busy = b2_uop_prs1_busy; // @[core.scala:188:23, :190:18] reg b2_uop_prs2_busy; // @[core.scala:190:18] assign brupdate_b2_uop_prs2_busy = b2_uop_prs2_busy; // @[core.scala:188:23, :190:18] reg b2_uop_prs3_busy; // @[core.scala:190:18] assign brupdate_b2_uop_prs3_busy = b2_uop_prs3_busy; // @[core.scala:188:23, :190:18] reg b2_uop_ppred_busy; // @[core.scala:190:18] assign brupdate_b2_uop_ppred_busy = b2_uop_ppred_busy; // @[core.scala:188:23, :190:18] reg [6:0] b2_uop_stale_pdst; // @[core.scala:190:18] assign brupdate_b2_uop_stale_pdst = b2_uop_stale_pdst; // @[core.scala:188:23, :190:18] reg b2_uop_exception; // @[core.scala:190:18] assign brupdate_b2_uop_exception = b2_uop_exception; // @[core.scala:188:23, :190:18] reg [63:0] b2_uop_exc_cause; // @[core.scala:190:18] assign brupdate_b2_uop_exc_cause = b2_uop_exc_cause; // @[core.scala:188:23, :190:18] reg b2_uop_bypassable; // @[core.scala:190:18] assign brupdate_b2_uop_bypassable = b2_uop_bypassable; // @[core.scala:188:23, :190:18] reg [4:0] b2_uop_mem_cmd; // @[core.scala:190:18] assign brupdate_b2_uop_mem_cmd = b2_uop_mem_cmd; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_mem_size; // @[core.scala:190:18] assign brupdate_b2_uop_mem_size = b2_uop_mem_size; // @[core.scala:188:23, :190:18] reg b2_uop_mem_signed; // @[core.scala:190:18] assign brupdate_b2_uop_mem_signed = b2_uop_mem_signed; // @[core.scala:188:23, :190:18] reg b2_uop_is_fence; // @[core.scala:190:18] assign brupdate_b2_uop_is_fence = b2_uop_is_fence; // @[core.scala:188:23, :190:18] reg b2_uop_is_fencei; // @[core.scala:190:18] assign brupdate_b2_uop_is_fencei = b2_uop_is_fencei; // @[core.scala:188:23, :190:18] reg b2_uop_is_amo; // @[core.scala:190:18] assign brupdate_b2_uop_is_amo = b2_uop_is_amo; // @[core.scala:188:23, :190:18] reg b2_uop_uses_ldq; // @[core.scala:190:18] assign brupdate_b2_uop_uses_ldq = b2_uop_uses_ldq; // @[core.scala:188:23, :190:18] reg b2_uop_uses_stq; // @[core.scala:190:18] assign brupdate_b2_uop_uses_stq = b2_uop_uses_stq; // @[core.scala:188:23, :190:18] reg b2_uop_is_sys_pc2epc; // @[core.scala:190:18] assign brupdate_b2_uop_is_sys_pc2epc = b2_uop_is_sys_pc2epc; // @[core.scala:188:23, :190:18] reg b2_uop_is_unique; // @[core.scala:190:18] assign brupdate_b2_uop_is_unique = b2_uop_is_unique; // @[core.scala:188:23, :190:18] reg b2_uop_flush_on_commit; // @[core.scala:190:18] assign brupdate_b2_uop_flush_on_commit = b2_uop_flush_on_commit; // @[core.scala:188:23, :190:18] reg b2_uop_ldst_is_rs1; // @[core.scala:190:18] assign brupdate_b2_uop_ldst_is_rs1 = b2_uop_ldst_is_rs1; // @[core.scala:188:23, :190:18] reg [5:0] b2_uop_ldst; // @[core.scala:190:18] assign brupdate_b2_uop_ldst = b2_uop_ldst; // @[core.scala:188:23, :190:18] reg [5:0] b2_uop_lrs1; // @[core.scala:190:18] assign brupdate_b2_uop_lrs1 = b2_uop_lrs1; // @[core.scala:188:23, :190:18] reg [5:0] b2_uop_lrs2; // @[core.scala:190:18] assign brupdate_b2_uop_lrs2 = b2_uop_lrs2; // @[core.scala:188:23, :190:18] reg [5:0] b2_uop_lrs3; // @[core.scala:190:18] assign brupdate_b2_uop_lrs3 = b2_uop_lrs3; // @[core.scala:188:23, :190:18] reg b2_uop_ldst_val; // @[core.scala:190:18] assign brupdate_b2_uop_ldst_val = b2_uop_ldst_val; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_dst_rtype; // @[core.scala:190:18] assign brupdate_b2_uop_dst_rtype = b2_uop_dst_rtype; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_lrs1_rtype; // @[core.scala:190:18] assign brupdate_b2_uop_lrs1_rtype = b2_uop_lrs1_rtype; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_lrs2_rtype; // @[core.scala:190:18] assign brupdate_b2_uop_lrs2_rtype = b2_uop_lrs2_rtype; // @[core.scala:188:23, :190:18] reg b2_uop_frs3_en; // @[core.scala:190:18] assign brupdate_b2_uop_frs3_en = b2_uop_frs3_en; // @[core.scala:188:23, :190:18] reg b2_uop_fp_val; // @[core.scala:190:18] assign brupdate_b2_uop_fp_val = b2_uop_fp_val; // @[core.scala:188:23, :190:18] reg b2_uop_fp_single; // @[core.scala:190:18] assign brupdate_b2_uop_fp_single = b2_uop_fp_single; // @[core.scala:188:23, :190:18] reg b2_uop_xcpt_pf_if; // @[core.scala:190:18] assign brupdate_b2_uop_xcpt_pf_if = b2_uop_xcpt_pf_if; // @[core.scala:188:23, :190:18] reg b2_uop_xcpt_ae_if; // @[core.scala:190:18] assign brupdate_b2_uop_xcpt_ae_if = b2_uop_xcpt_ae_if; // @[core.scala:188:23, :190:18] reg b2_uop_xcpt_ma_if; // @[core.scala:190:18] assign brupdate_b2_uop_xcpt_ma_if = b2_uop_xcpt_ma_if; // @[core.scala:188:23, :190:18] reg b2_uop_bp_debug_if; // @[core.scala:190:18] assign brupdate_b2_uop_bp_debug_if = b2_uop_bp_debug_if; // @[core.scala:188:23, :190:18] reg b2_uop_bp_xcpt_if; // @[core.scala:190:18] assign brupdate_b2_uop_bp_xcpt_if = b2_uop_bp_xcpt_if; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_debug_fsrc; // @[core.scala:190:18] assign brupdate_b2_uop_debug_fsrc = b2_uop_debug_fsrc; // @[core.scala:188:23, :190:18] reg [1:0] b2_uop_debug_tsrc; // @[core.scala:190:18] assign brupdate_b2_uop_debug_tsrc = b2_uop_debug_tsrc; // @[core.scala:188:23, :190:18] reg b2_mispredict; // @[core.scala:190:18] assign brupdate_b2_mispredict = b2_mispredict; // @[core.scala:188:23, :190:18] reg b2_taken; // @[core.scala:190:18] assign brupdate_b2_taken = b2_taken; // @[core.scala:188:23, :190:18] reg [2:0] b2_cfi_type; // @[core.scala:190:18] assign brupdate_b2_cfi_type = b2_cfi_type; // @[core.scala:188:23, :190:18] reg [1:0] b2_pc_sel; // @[core.scala:190:18] assign brupdate_b2_pc_sel = b2_pc_sel; // @[core.scala:188:23, :190:18] reg [39:0] b2_jalr_target; // @[core.scala:190:18] assign brupdate_b2_jalr_target = b2_jalr_target; // @[core.scala:188:23, :190:18] reg [20:0] b2_target_offset; // @[core.scala:190:18] assign brupdate_b2_target_offset = b2_target_offset; // @[core.scala:188:23, :190:18] wire _brinfos_0_valid_T = ~_rob_io_flush_valid; // @[core.scala:143:32, :197:37] wire _brinfos_0_valid_T_1 = _alu_exe_unit_io_brinfo_valid & _brinfos_0_valid_T; // @[execution-units.scala:119:32] wire _brinfos_1_valid_T = ~_rob_io_flush_valid; // @[core.scala:143:32, :197:37] wire _brinfos_1_valid_T_1 = _alu_exe_unit_1_io_brinfo_valid & _brinfos_1_valid_T; // @[execution-units.scala:119:32] wire _brinfos_2_valid_T = ~_rob_io_flush_valid; // @[core.scala:143:32, :197:37] wire _brinfos_2_valid_T_1 = _alu_exe_unit_2_io_brinfo_valid & _brinfos_2_valid_T; // @[execution-units.scala:119:32] wire [15:0] _GEN = {12'h0, brinfos_0_uop_br_tag}; // @[core.scala:182:20, :199:47] wire [15:0] _b1_resolve_mask_T = {15'h0, brinfos_0_valid} << _GEN; // @[core.scala:182:20, :199:47] wire [15:0] _GEN_0 = {12'h0, brinfos_1_uop_br_tag}; // @[core.scala:182:20, :199:47] wire [15:0] _b1_resolve_mask_T_1 = {15'h0, brinfos_1_valid} << _GEN_0; // @[core.scala:182:20, :199:47] wire [15:0] _GEN_1 = {12'h0, brinfos_2_uop_br_tag}; // @[core.scala:182:20, :199:47] wire [15:0] _b1_resolve_mask_T_2 = {15'h0, brinfos_2_valid} << _GEN_1; // @[core.scala:182:20, :199:47] wire [15:0] _b1_resolve_mask_T_3 = _b1_resolve_mask_T \| _b1_resolve_mask_T_1; // @[core.scala:199:{47,72}] assign _b1_resolve_mask_T_4 = _b1_resolve_mask_T_3 \| _b1_resolve_mask_T_2; // @[core.scala:199:{47,72}] assign b1_resolve_mask = _b1_resolve_mask_T_4; // @[core.scala:189:19, :199:72] wire _T_1 = brinfos_0_valid & brinfos_0_mispredict; // @[core.scala:182:20, :200:51] wire _b1_mispredict_mask_T; // @[core.scala:200:51] assign _b1_mispredict_mask_T = _T_1; // @[core.scala:200:51] wire _use_this_mispredict_T_1; // @[core.scala:207:13] assign _use_this_mispredict_T_1 = _T_1; // @[core.scala:200:51, :207:13] wire [15:0] _b1_mispredict_mask_T_1 = {15'h0, _b1_mispredict_mask_T} << _GEN; // @[core.scala:199:47, :200:{51,68}] wire _T_3 = brinfos_1_valid & brinfos_1_mispredict; // @[core.scala:182:20, :200:51] wire _b1_mispredict_mask_T_2; // @[core.scala:200:51] assign _b1_mispredict_mask_T_2 = _T_3; // @[core.scala:200:51] wire _use_this_mispredict_T_9; // @[core.scala:207:13] assign _use_this_mispredict_T_9 = _T_3; // @[core.scala:200:51, :207:13] wire [15:0] _b1_mispredict_mask_T_3 = {15'h0, _b1_mispredict_mask_T_2} << _GEN_0; // @[core.scala:199:47, :200:{51,68}] wire _T_6 = brinfos_2_valid & brinfos_2_mispredict; // @[core.scala:182:20, :200:51] wire _b1_mispredict_mask_T_4; // @[core.scala:200:51] assign _b1_mispredict_mask_T_4 = _T_6; // @[core.scala:200:51] wire _use_this_mispredict_T_17; // @[core.scala:207:13] assign _use_this_mispredict_T_17 = _T_6; // @[core.scala:200:51, :207:13] wire [15:0] _b1_mispredict_mask_T_5 = {15'h0, _b1_mispredict_mask_T_4} << _GEN_1; // @[core.scala:199:47, :200:{51,68}] wire [15:0] _b1_mispredict_mask_T_6 = _b1_mispredict_mask_T_1 \| _b1_mispredict_mask_T_3; // @[core.scala:200:{68,93}] assign _b1_mispredict_mask_T_7 = _b1_mispredict_mask_T_6 \| _b1_mispredict_mask_T_5; // @[core.scala:200:{68,93}] assign b1_mispredict_mask = _b1_mispredict_mask_T_7; // @[core.scala:189:19, :200:93] wire _GEN_2 = brinfos_0_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:64] wire _use_this_mispredict_T_3; // @[util.scala:363:64] assign _use_this_mispredict_T_3 = _GEN_2; // @[util.scala:363:64] wire _use_this_mispredict_T_5; // @[util.scala:363:78] assign _use_this_mispredict_T_5 = _GEN_2; // @[util.scala:363:{64,78}] wire _use_this_mispredict_T_13; // @[util.scala:363:78] assign _use_this_mispredict_T_13 = _GEN_2; // @[util.scala:363:{64,78}] wire _use_this_mispredict_T_4 = _use_this_mispredict_T_3; // @[util.scala:363:{58,64}] wire _use_this_mispredict_T_6 = _use_this_mispredict_T_4 ^ _use_this_mispredict_T_5; // @[util.scala:363:{58,72,78}] wire _use_this_mispredict_T_7 = _use_this_mispredict_T_1 & _use_this_mispredict_T_6; // @[util.scala:363:72] wire _use_this_mispredict_T_8 = ~_T_1; // @[core.scala:200:51, :206:31] wire _use_this_mispredict_T_10 = brinfos_1_uop_rob_idx < brinfos_0_uop_rob_idx; // @[util.scala:363:52] wire _use_this_mispredict_T_11 = brinfos_1_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:64] wire _use_this_mispredict_T_12 = _use_this_mispredict_T_10 ^ _use_this_mispredict_T_11; // @[util.scala:363:{52,58,64}] wire _use_this_mispredict_T_14 = _use_this_mispredict_T_12 ^ _use_this_mispredict_T_13; // @[util.scala:363:{58,72,78}] wire _use_this_mispredict_T_15 = _use_this_mispredict_T_9 & _use_this_mispredict_T_14; // @[util.scala:363:72] wire use_this_mispredict_1 = _use_this_mispredict_T_8 \| _use_this_mispredict_T_15; // @[core.scala:206:{31,47}, :207:29] wire _T_4 = _T_1 \| _T_3; // @[core.scala:200:51, :209:37] wire [6:0] _T_5_uop_rob_idx = use_this_mispredict_1 ? brinfos_1_uop_rob_idx : brinfos_0_uop_rob_idx; // @[core.scala:182:20, :206:47, :210:28] wire _use_this_mispredict_T_16 = ~_T_4; // @[core.scala:206:31, :209:37] wire _use_this_mispredict_T_18 = brinfos_2_uop_rob_idx < _T_5_uop_rob_idx; // @[util.scala:363:52] wire _use_this_mispredict_T_19 = brinfos_2_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:64] wire _use_this_mispredict_T_20 = _use_this_mispredict_T_18 ^ _use_this_mispredict_T_19; // @[util.scala:363:{52,58,64}] wire _use_this_mispredict_T_21 = _T_5_uop_rob_idx < _rob_io_rob_head_idx; // @[util.scala:363:78] wire _use_this_mispredict_T_22 = _use_this_mispredict_T_20 ^ _use_this_mispredict_T_21; // @[util.scala:363:{58,72,78}] wire _use_this_mispredict_T_23 = _use_this_mispredict_T_17 & _use_this_mispredict_T_22; // @[util.scala:363:72] wire use_this_mispredict_2 = _use_this_mispredict_T_16 \| _use_this_mispredict_T_23; // @[core.scala:206:{31,47}, :207:29] wire [6:0] b2_uop_out_uopc = use_this_mispredict_2 ? brinfos_2_uop_uopc : use_this_mispredict_1 ? brinfos_1_uop_uopc : brinfos_0_uop_uopc; // @[util.scala:96:23] wire [31:0] b2_uop_out_inst = use_this_mispredict_2 ? brinfos_2_uop_inst : use_this_mispredict_1 ? brinfos_1_uop_inst : brinfos_0_uop_inst; // @[util.scala:96:23] wire [31:0] b2_uop_out_debug_inst = use_this_mispredict_2 ? brinfos_2_uop_debug_inst : use_this_mispredict_1 ? brinfos_1_uop_debug_inst : brinfos_0_uop_debug_inst; // @[util.scala:96:23] wire b2_uop_out_is_rvc = use_this_mispredict_2 ? brinfos_2_uop_is_rvc : use_this_mispredict_1 ? brinfos_1_uop_is_rvc : brinfos_0_uop_is_rvc; // @[util.scala:96:23] wire [39:0] b2_uop_out_debug_pc = use_this_mispredict_2 ? brinfos_2_uop_debug_pc : use_this_mispredict_1 ? brinfos_1_uop_debug_pc : brinfos_0_uop_debug_pc; // @[util.scala:96:23] wire [2:0] b2_uop_out_iq_type = use_this_mispredict_2 ? brinfos_2_uop_iq_type : use_this_mispredict_1 ? brinfos_1_uop_iq_type : brinfos_0_uop_iq_type; // @[util.scala:96:23] wire [9:0] b2_uop_out_fu_code = use_this_mispredict_2 ? brinfos_2_uop_fu_code : use_this_mispredict_1 ? brinfos_1_uop_fu_code : brinfos_0_uop_fu_code; // @[util.scala:96:23] wire [3:0] b2_uop_out_ctrl_br_type = use_this_mispredict_2 ? brinfos_2_uop_ctrl_br_type : use_this_mispredict_1 ? brinfos_1_uop_ctrl_br_type : brinfos_0_uop_ctrl_br_type; // @[util.scala:96:23] wire [1:0] b2_uop_out_ctrl_op1_sel = use_this_mispredict_2 ? brinfos_2_uop_ctrl_op1_sel : use_this_mispredict_1 ? brinfos_1_uop_ctrl_op1_sel : brinfos_0_uop_ctrl_op1_sel; // @[util.scala:96:23] wire [2:0] b2_uop_out_ctrl_op2_sel = use_this_mispredict_2 ? brinfos_2_uop_ctrl_op2_sel : use_this_mispredict_1 ? brinfos_1_uop_ctrl_op2_sel : brinfos_0_uop_ctrl_op2_sel; // @[util.scala:96:23] wire [2:0] b2_uop_out_ctrl_imm_sel = use_this_mispredict_2 ? brinfos_2_uop_ctrl_imm_sel : use_this_mispredict_1 ? brinfos_1_uop_ctrl_imm_sel : brinfos_0_uop_ctrl_imm_sel; // @[util.scala:96:23] wire [4:0] b2_uop_out_ctrl_op_fcn = use_this_mispredict_2 ? brinfos_2_uop_ctrl_op_fcn : use_this_mispredict_1 ? brinfos_1_uop_ctrl_op_fcn : brinfos_0_uop_ctrl_op_fcn; // @[util.scala:96:23] wire b2_uop_out_ctrl_fcn_dw = use_this_mispredict_2 ? brinfos_2_uop_ctrl_fcn_dw : use_this_mispredict_1 ? brinfos_1_uop_ctrl_fcn_dw : brinfos_0_uop_ctrl_fcn_dw; // @[util.scala:96:23] wire [2:0] b2_uop_out_ctrl_csr_cmd = use_this_mispredict_2 ? brinfos_2_uop_ctrl_csr_cmd : use_this_mispredict_1 ? brinfos_1_uop_ctrl_csr_cmd : brinfos_0_uop_ctrl_csr_cmd; // @[util.scala:96:23] wire b2_uop_out_ctrl_is_load = use_this_mispredict_2 ? brinfos_2_uop_ctrl_is_load : use_this_mispredict_1 ? brinfos_1_uop_ctrl_is_load : brinfos_0_uop_ctrl_is_load; // @[util.scala:96:23] wire b2_uop_out_ctrl_is_sta = use_this_mispredict_2 ? brinfos_2_uop_ctrl_is_sta : use_this_mispredict_1 ? brinfos_1_uop_ctrl_is_sta : brinfos_0_uop_ctrl_is_sta; // @[util.scala:96:23] wire b2_uop_out_ctrl_is_std = use_this_mispredict_2 ? brinfos_2_uop_ctrl_is_std : use_this_mispredict_1 ? brinfos_1_uop_ctrl_is_std : brinfos_0_uop_ctrl_is_std; // @[util.scala:96:23] wire [1:0] b2_uop_out_iw_state = use_this_mispredict_2 ? brinfos_2_uop_iw_state : use_this_mispredict_1 ? brinfos_1_uop_iw_state : brinfos_0_uop_iw_state; // @[util.scala:96:23] wire b2_uop_out_iw_p1_poisoned = use_this_mispredict_2 ? brinfos_2_uop_iw_p1_poisoned : use_this_mispredict_1 ? brinfos_1_uop_iw_p1_poisoned : brinfos_0_uop_iw_p1_poisoned; // @[util.scala:96:23] wire b2_uop_out_iw_p2_poisoned = use_this_mispredict_2 ? brinfos_2_uop_iw_p2_poisoned : use_this_mispredict_1 ? brinfos_1_uop_iw_p2_poisoned : brinfos_0_uop_iw_p2_poisoned; // @[util.scala:96:23] wire b2_uop_out_is_br = use_this_mispredict_2 ? brinfos_2_uop_is_br : use_this_mispredict_1 ? brinfos_1_uop_is_br : brinfos_0_uop_is_br; // @[util.scala:96:23] wire b2_uop_out_is_jalr = use_this_mispredict_2 ? brinfos_2_uop_is_jalr : use_this_mispredict_1 ? brinfos_1_uop_is_jalr : brinfos_0_uop_is_jalr; // @[util.scala:96:23] wire b2_uop_out_is_jal = use_this_mispredict_2 ? brinfos_2_uop_is_jal : use_this_mispredict_1 ? brinfos_1_uop_is_jal : brinfos_0_uop_is_jal; // @[util.scala:96:23] wire b2_uop_out_is_sfb = use_this_mispredict_2 ? brinfos_2_uop_is_sfb : use_this_mispredict_1 ? brinfos_1_uop_is_sfb : brinfos_0_uop_is_sfb; // @[util.scala:96:23] wire [3:0] b2_uop_out_br_tag = use_this_mispredict_2 ? brinfos_2_uop_br_tag : use_this_mispredict_1 ? brinfos_1_uop_br_tag : brinfos_0_uop_br_tag; // @[util.scala:96:23] wire [4:0] _T_8_uop_ftq_idx = use_this_mispredict_2 ? brinfos_2_uop_ftq_idx : use_this_mispredict_1 ? brinfos_1_uop_ftq_idx : brinfos_0_uop_ftq_idx; // @[core.scala:182:20, :206:47, :210:28] assign io_ifu_get_pc_1_ftq_idx_0 = _T_8_uop_ftq_idx; // @[core.scala:51:7, :210:28] wire [4:0] b2_uop_out_ftq_idx; // @[util.scala:96:23] assign b2_uop_out_ftq_idx = _T_8_uop_ftq_idx; // @[util.scala:96:23] wire b2_uop_out_edge_inst = use_this_mispredict_2 ? brinfos_2_uop_edge_inst : use_this_mispredict_1 ? brinfos_1_uop_edge_inst : brinfos_0_uop_edge_inst; // @[util.scala:96:23] wire [5:0] b2_uop_out_pc_lob = use_this_mispredict_2 ? brinfos_2_uop_pc_lob : use_this_mispredict_1 ? brinfos_1_uop_pc_lob : brinfos_0_uop_pc_lob; // @[util.scala:96:23] wire b2_uop_out_taken = use_this_mispredict_2 ? brinfos_2_uop_taken : use_this_mispredict_1 ? brinfos_1_uop_taken : brinfos_0_uop_taken; // @[util.scala:96:23] wire [19:0] b2_uop_out_imm_packed = use_this_mispredict_2 ? brinfos_2_uop_imm_packed : use_this_mispredict_1 ? brinfos_1_uop_imm_packed : brinfos_0_uop_imm_packed; // @[util.scala:96:23] wire [11:0] b2_uop_out_csr_addr = use_this_mispredict_2 ? brinfos_2_uop_csr_addr : use_this_mispredict_1 ? brinfos_1_uop_csr_addr : brinfos_0_uop_csr_addr; // @[util.scala:96:23] wire [6:0] b2_uop_out_rob_idx = use_this_mispredict_2 ? brinfos_2_uop_rob_idx : _T_5_uop_rob_idx; // @[util.scala:96:23] wire [4:0] b2_uop_out_ldq_idx = use_this_mispredict_2 ? brinfos_2_uop_ldq_idx : use_this_mispredict_1 ? brinfos_1_uop_ldq_idx : brinfos_0_uop_ldq_idx; // @[util.scala:96:23] wire [4:0] b2_uop_out_stq_idx = use_this_mispredict_2 ? brinfos_2_uop_stq_idx : use_this_mispredict_1 ? brinfos_1_uop_stq_idx : brinfos_0_uop_stq_idx; // @[util.scala:96:23] wire [1:0] b2_uop_out_rxq_idx = use_this_mispredict_2 ? brinfos_2_uop_rxq_idx : use_this_mispredict_1 ? brinfos_1_uop_rxq_idx : brinfos_0_uop_rxq_idx; // @[util.scala:96:23] wire [6:0] b2_uop_out_pdst = use_this_mispredict_2 ? brinfos_2_uop_pdst : use_this_mispredict_1 ? brinfos_1_uop_pdst : brinfos_0_uop_pdst; // @[util.scala:96:23] wire [6:0] b2_uop_out_prs1 = use_this_mispredict_2 ? brinfos_2_uop_prs1 : use_this_mispredict_1 ? brinfos_1_uop_prs1 : brinfos_0_uop_prs1; // @[util.scala:96:23] wire [6:0] b2_uop_out_prs2 = use_this_mispredict_2 ? brinfos_2_uop_prs2 : use_this_mispredict_1 ? brinfos_1_uop_prs2 : brinfos_0_uop_prs2; // @[util.scala:96:23] wire [6:0] b2_uop_out_prs3 = use_this_mispredict_2 ? brinfos_2_uop_prs3 : use_this_mispredict_1 ? brinfos_1_uop_prs3 : brinfos_0_uop_prs3; // @[util.scala:96:23] wire [4:0] b2_uop_out_ppred = use_this_mispredict_2 ? brinfos_2_uop_ppred : use_this_mispredict_1 ? brinfos_1_uop_ppred : brinfos_0_uop_ppred; // @[util.scala:96:23] wire b2_uop_out_prs1_busy = use_this_mispredict_2 ? brinfos_2_uop_prs1_busy : use_this_mispredict_1 ? brinfos_1_uop_prs1_busy : brinfos_0_uop_prs1_busy; // @[util.scala:96:23] wire b2_uop_out_prs2_busy = use_this_mispredict_2 ? brinfos_2_uop_prs2_busy : use_this_mispredict_1 ? brinfos_1_uop_prs2_busy : brinfos_0_uop_prs2_busy; // @[util.scala:96:23] wire b2_uop_out_prs3_busy = use_this_mispredict_2 ? brinfos_2_uop_prs3_busy : use_this_mispredict_1 ? brinfos_1_uop_prs3_busy : brinfos_0_uop_prs3_busy; // @[util.scala:96:23] wire b2_uop_out_ppred_busy = use_this_mispredict_2 ? brinfos_2_uop_ppred_busy : use_this_mispredict_1 ? brinfos_1_uop_ppred_busy : brinfos_0_uop_ppred_busy; // @[util.scala:96:23] wire [6:0] b2_uop_out_stale_pdst = use_this_mispredict_2 ? brinfos_2_uop_stale_pdst : use_this_mispredict_1 ? brinfos_1_uop_stale_pdst : brinfos_0_uop_stale_pdst; // @[util.scala:96:23] wire b2_uop_out_exception = use_this_mispredict_2 ? brinfos_2_uop_exception : use_this_mispredict_1 ? brinfos_1_uop_exception : brinfos_0_uop_exception; // @[util.scala:96:23] wire [63:0] b2_uop_out_exc_cause = use_this_mispredict_2 ? brinfos_2_uop_exc_cause : use_this_mispredict_1 ? brinfos_1_uop_exc_cause : brinfos_0_uop_exc_cause; // @[util.scala:96:23] wire b2_uop_out_bypassable = use_this_mispredict_2 ? brinfos_2_uop_bypassable : use_this_mispredict_1 ? brinfos_1_uop_bypassable : brinfos_0_uop_bypassable; // @[util.scala:96:23] wire [4:0] b2_uop_out_mem_cmd = use_this_mispredict_2 ? brinfos_2_uop_mem_cmd : use_this_mispredict_1 ? brinfos_1_uop_mem_cmd : brinfos_0_uop_mem_cmd; // @[util.scala:96:23] wire [1:0] b2_uop_out_mem_size = use_this_mispredict_2 ? brinfos_2_uop_mem_size : use_this_mispredict_1 ? brinfos_1_uop_mem_size : brinfos_0_uop_mem_size; // @[util.scala:96:23] wire b2_uop_out_mem_signed = use_this_mispredict_2 ? brinfos_2_uop_mem_signed : use_this_mispredict_1 ? brinfos_1_uop_mem_signed : brinfos_0_uop_mem_signed; // @[util.scala:96:23] wire b2_uop_out_is_fence = use_this_mispredict_2 ? brinfos_2_uop_is_fence : use_this_mispredict_1 ? brinfos_1_uop_is_fence : brinfos_0_uop_is_fence; // @[util.scala:96:23] wire b2_uop_out_is_fencei = use_this_mispredict_2 ? brinfos_2_uop_is_fencei : use_this_mispredict_1 ? brinfos_1_uop_is_fencei : brinfos_0_uop_is_fencei; // @[util.scala:96:23] wire b2_uop_out_is_amo = use_this_mispredict_2 ? brinfos_2_uop_is_amo : use_this_mispredict_1 ? brinfos_1_uop_is_amo : brinfos_0_uop_is_amo; // @[util.scala:96:23] wire b2_uop_out_uses_ldq = use_this_mispredict_2 ? brinfos_2_uop_uses_ldq : use_this_mispredict_1 ? brinfos_1_uop_uses_ldq : brinfos_0_uop_uses_ldq; // @[util.scala:96:23] wire b2_uop_out_uses_stq = use_this_mispredict_2 ? brinfos_2_uop_uses_stq : use_this_mispredict_1 ? brinfos_1_uop_uses_stq : brinfos_0_uop_uses_stq; // @[util.scala:96:23] wire b2_uop_out_is_sys_pc2epc = use_this_mispredict_2 ? brinfos_2_uop_is_sys_pc2epc : use_this_mispredict_1 ? brinfos_1_uop_is_sys_pc2epc : brinfos_0_uop_is_sys_pc2epc; // @[util.scala:96:23] wire b2_uop_out_is_unique = use_this_mispredict_2 ? brinfos_2_uop_is_unique : use_this_mispredict_1 ? brinfos_1_uop_is_unique : brinfos_0_uop_is_unique; // @[util.scala:96:23] wire b2_uop_out_flush_on_commit = use_this_mispredict_2 ? brinfos_2_uop_flush_on_commit : use_this_mispredict_1 ? brinfos_1_uop_flush_on_commit : brinfos_0_uop_flush_on_commit; // @[util.scala:96:23] wire b2_uop_out_ldst_is_rs1 = use_this_mispredict_2 ? brinfos_2_uop_ldst_is_rs1 : use_this_mispredict_1 ? brinfos_1_uop_ldst_is_rs1 : brinfos_0_uop_ldst_is_rs1; // @[util.scala:96:23] wire [5:0] b2_uop_out_ldst = use_this_mispredict_2 ? brinfos_2_uop_ldst : use_this_mispredict_1 ? brinfos_1_uop_ldst : brinfos_0_uop_ldst; // @[util.scala:96:23] wire [5:0] b2_uop_out_lrs1 = use_this_mispredict_2 ? brinfos_2_uop_lrs1 : use_this_mispredict_1 ? brinfos_1_uop_lrs1 : brinfos_0_uop_lrs1; // @[util.scala:96:23] wire [5:0] b2_uop_out_lrs2 = use_this_mispredict_2 ? brinfos_2_uop_lrs2 : use_this_mispredict_1 ? brinfos_1_uop_lrs2 : brinfos_0_uop_lrs2; // @[util.scala:96:23] wire [5:0] b2_uop_out_lrs3 = use_this_mispredict_2 ? brinfos_2_uop_lrs3 : use_this_mispredict_1 ? brinfos_1_uop_lrs3 : brinfos_0_uop_lrs3; // @[util.scala:96:23] wire b2_uop_out_ldst_val = use_this_mispredict_2 ? brinfos_2_uop_ldst_val : use_this_mispredict_1 ? brinfos_1_uop_ldst_val : brinfos_0_uop_ldst_val; // @[util.scala:96:23] wire [1:0] b2_uop_out_dst_rtype = use_this_mispredict_2 ? brinfos_2_uop_dst_rtype : use_this_mispredict_1 ? brinfos_1_uop_dst_rtype : brinfos_0_uop_dst_rtype; // @[util.scala:96:23] wire [1:0] b2_uop_out_lrs1_rtype = use_this_mispredict_2 ? brinfos_2_uop_lrs1_rtype : use_this_mispredict_1 ? brinfos_1_uop_lrs1_rtype : brinfos_0_uop_lrs1_rtype; // @[util.scala:96:23] wire [1:0] b2_uop_out_lrs2_rtype = use_this_mispredict_2 ? brinfos_2_uop_lrs2_rtype : use_this_mispredict_1 ? brinfos_1_uop_lrs2_rtype : brinfos_0_uop_lrs2_rtype; // @[util.scala:96:23] wire b2_uop_out_frs3_en = use_this_mispredict_2 ? brinfos_2_uop_frs3_en : use_this_mispredict_1 ? brinfos_1_uop_frs3_en : brinfos_0_uop_frs3_en; // @[util.scala:96:23] wire b2_uop_out_fp_val = use_this_mispredict_2 ? brinfos_2_uop_fp_val : use_this_mispredict_1 ? brinfos_1_uop_fp_val : brinfos_0_uop_fp_val; // @[util.scala:96:23] wire b2_uop_out_fp_single = use_this_mispredict_2 ? brinfos_2_uop_fp_single : use_this_mispredict_1 ? brinfos_1_uop_fp_single : brinfos_0_uop_fp_single; // @[util.scala:96:23] wire b2_uop_out_xcpt_pf_if = use_this_mispredict_2 ? brinfos_2_uop_xcpt_pf_if : use_this_mispredict_1 ? brinfos_1_uop_xcpt_pf_if : brinfos_0_uop_xcpt_pf_if; // @[util.scala:96:23] wire b2_uop_out_xcpt_ae_if = use_this_mispredict_2 ? brinfos_2_uop_xcpt_ae_if : use_this_mispredict_1 ? brinfos_1_uop_xcpt_ae_if : brinfos_0_uop_xcpt_ae_if; // @[util.scala:96:23] wire b2_uop_out_xcpt_ma_if = use_this_mispredict_2 ? brinfos_2_uop_xcpt_ma_if : use_this_mispredict_1 ? brinfos_1_uop_xcpt_ma_if : brinfos_0_uop_xcpt_ma_if; // @[util.scala:96:23] wire b2_uop_out_bp_debug_if = use_this_mispredict_2 ? brinfos_2_uop_bp_debug_if : use_this_mispredict_1 ? brinfos_1_uop_bp_debug_if : brinfos_0_uop_bp_debug_if; // @[util.scala:96:23] wire b2_uop_out_bp_xcpt_if = use_this_mispredict_2 ? brinfos_2_uop_bp_xcpt_if : use_this_mispredict_1 ? brinfos_1_uop_bp_xcpt_if : brinfos_0_uop_bp_xcpt_if; // @[util.scala:96:23] wire [1:0] b2_uop_out_debug_fsrc = use_this_mispredict_2 ? brinfos_2_uop_debug_fsrc : use_this_mispredict_1 ? brinfos_1_uop_debug_fsrc : brinfos_0_uop_debug_fsrc; // @[util.scala:96:23] wire [1:0] b2_uop_out_debug_tsrc = use_this_mispredict_2 ? brinfos_2_uop_debug_tsrc : use_this_mispredict_1 ? brinfos_1_uop_debug_tsrc : brinfos_0_uop_debug_tsrc; // @[util.scala:96:23] wire [15:0] _b2_uop_out_br_mask_T_1; // @[util.scala:85:25] wire [15:0] b2_uop_out_br_mask; // @[util.scala:96:23] wire [15:0] _b2_uop_out_br_mask_T = ~brupdate_b1_resolve_mask; // @[util.scala:85:27] assign _b2_uop_out_br_mask_T_1 = (use_this_mispredict_2 ? brinfos_2_uop_br_mask : use_this_mispredict_1 ? brinfos_1_uop_br_mask : brinfos_0_uop_br_mask) & _b2_uop_out_br_mask_T; // @[util.scala:85:{25,27}] assign b2_uop_out_br_mask = _b2_uop_out_br_mask_T_1; // @[util.scala:85:25, :96:23] reg [39:0] b2_jalr_target_REG; // @[core.scala:218:28] wire custom_csrs_csrs_0_ren; // @[core.scala:276:25] wire custom_csrs_csrs_0_wen; // @[core.scala:276:25] wire [63:0] custom_csrs_csrs_0_wdata; // @[core.scala:276:25] wire [63:0] custom_csrs_csrs_0_value; // @[core.scala:276:25] wire custom_csrs_csrs_1_ren; // @[core.scala:276:25] wire custom_csrs_csrs_1_wen; // @[core.scala:276:25] wire [63:0] custom_csrs_csrs_1_wdata; // @[core.scala:276:25] wire [63:0] custom_csrs_csrs_1_value; // @[core.scala:276:25] reg [63:0] debug_tsc_reg; // @[core.scala:288:30] assign io_lsu_tsc_reg_0 = debug_tsc_reg; // @[core.scala:51:7, :288:30] reg [63:0] debug_irt_reg; // @[core.scala:289:30] reg [63:0] debug_brs_0; // @[core.scala:290:26] reg [63:0] debug_brs_1; // @[core.scala:290:26] reg [63:0] debug_brs_2; // @[core.scala:290:26] reg [63:0] debug_brs_3; // @[core.scala:290:26] reg [63:0] debug_jals_0; // @[core.scala:291:26] reg [63:0] debug_jals_1; // @[core.scala:291:26] reg [63:0] debug_jals_2; // @[core.scala:291:26] reg [63:0] debug_jals_3; // @[core.scala:291:26] reg [63:0] debug_jalrs_0; // @[core.scala:292:26] reg [63:0] debug_jalrs_1; // @[core.scala:292:26] reg [63:0] debug_jalrs_2; // @[core.scala:292:26] reg [63:0] debug_jalrs_3; // @[core.scala:292:26] wire _GEN_3 = _rob_io_commit_uops_0_debug_fsrc == 2'h0; // @[core.scala:143:32, :297:41] wire _debug_brs_0_T; // @[core.scala:297:41] assign _debug_brs_0_T = _GEN_3; // @[core.scala:297:41] wire _debug_jals_0_T; // @[core.scala:302:41] assign _debug_jals_0_T = _GEN_3; // @[core.scala:297:41, :302:41] wire _debug_jalrs_0_T; // @[core.scala:307:41] assign _debug_jalrs_0_T = _GEN_3; // @[core.scala:297:41, :307:41] wire _debug_brs_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_0_T; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_0_T_2 = _debug_brs_0_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_0_WIRE_0 = _debug_brs_0_T_2; // @[core.scala:295:52, :297:50] wire _GEN_4 = _rob_io_commit_uops_1_debug_fsrc == 2'h0; // @[core.scala:143:32, :297:41] wire _debug_brs_0_T_3; // @[core.scala:297:41] assign _debug_brs_0_T_3 = _GEN_4; // @[core.scala:297:41] wire _debug_jals_0_T_3; // @[core.scala:302:41] assign _debug_jals_0_T_3 = _GEN_4; // @[core.scala:297:41, :302:41] wire _debug_jalrs_0_T_3; // @[core.scala:307:41] assign _debug_jalrs_0_T_3 = _GEN_4; // @[core.scala:297:41, :307:41] wire _debug_brs_0_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_0_T_3; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_0_T_5 = _debug_brs_0_T_4 & _rob_io_commit_uops_1_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_0_WIRE_1 = _debug_brs_0_T_5; // @[core.scala:295:52, :297:50] wire _GEN_5 = _rob_io_commit_uops_2_debug_fsrc == 2'h0; // @[core.scala:143:32, :297:41] wire _debug_brs_0_T_6; // @[core.scala:297:41] assign _debug_brs_0_T_6 = _GEN_5; // @[core.scala:297:41] wire _debug_jals_0_T_6; // @[core.scala:302:41] assign _debug_jals_0_T_6 = _GEN_5; // @[core.scala:297:41, :302:41] wire _debug_jalrs_0_T_6; // @[core.scala:307:41] assign _debug_jalrs_0_T_6 = _GEN_5; // @[core.scala:297:41, :307:41] wire _debug_brs_0_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_0_T_6; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_0_T_8 = _debug_brs_0_T_7 & _rob_io_commit_uops_2_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_0_WIRE_2 = _debug_brs_0_T_8; // @[core.scala:295:52, :297:50] wire [1:0] _debug_brs_0_T_9 = {1'h0, _debug_brs_0_WIRE_1} + {1'h0, _debug_brs_0_WIRE_2}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_0_T_10 = _debug_brs_0_T_9; // @[core.scala:295:44] wire [2:0] _debug_brs_0_T_11 = {2'h0, _debug_brs_0_WIRE_0} + {1'h0, _debug_brs_0_T_10}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_0_T_12 = _debug_brs_0_T_11[1:0]; // @[core.scala:295:44] wire [64:0] _debug_brs_0_T_13 = {1'h0, debug_brs_0} + {63'h0, _debug_brs_0_T_12}; // @[core.scala:290:26, :295:{34,44}] wire [63:0] _debug_brs_0_T_14 = _debug_brs_0_T_13[63:0]; // @[core.scala:295:34] wire _debug_jals_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_0_T; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_0_T_2 = _debug_jals_0_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_0_WIRE_0 = _debug_jals_0_T_2; // @[core.scala:300:54, :302:50] wire _debug_jals_0_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_0_T_3; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_0_T_5 = _debug_jals_0_T_4 & _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_0_WIRE_1 = _debug_jals_0_T_5; // @[core.scala:300:54, :302:50] wire _debug_jals_0_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_0_T_6; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_0_T_8 = _debug_jals_0_T_7 & _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_0_WIRE_2 = _debug_jals_0_T_8; // @[core.scala:300:54, :302:50] wire [1:0] _debug_jals_0_T_9 = {1'h0, _debug_jals_0_WIRE_1} + {1'h0, _debug_jals_0_WIRE_2}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_0_T_10 = _debug_jals_0_T_9; // @[core.scala:300:46] wire [2:0] _debug_jals_0_T_11 = {2'h0, _debug_jals_0_WIRE_0} + {1'h0, _debug_jals_0_T_10}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_0_T_12 = _debug_jals_0_T_11[1:0]; // @[core.scala:300:46] wire [64:0] _debug_jals_0_T_13 = {1'h0, debug_jals_0} + {63'h0, _debug_jals_0_T_12}; // @[core.scala:291:26, :295:34, :300:{36,46}] wire [63:0] _debug_jals_0_T_14 = _debug_jals_0_T_13[63:0]; // @[core.scala:300:36] wire _debug_jalrs_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_0_T; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_0_T_2 = _debug_jalrs_0_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_0_WIRE_0 = _debug_jalrs_0_T_2; // @[core.scala:305:56, :307:50] wire _debug_jalrs_0_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_0_T_3; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_0_T_5 = _debug_jalrs_0_T_4 & _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_0_WIRE_1 = _debug_jalrs_0_T_5; // @[core.scala:305:56, :307:50] wire _debug_jalrs_0_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_0_T_6; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_0_T_8 = _debug_jalrs_0_T_7 & _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_0_WIRE_2 = _debug_jalrs_0_T_8; // @[core.scala:305:56, :307:50] wire [1:0] _debug_jalrs_0_T_9 = {1'h0, _debug_jalrs_0_WIRE_1} + {1'h0, _debug_jalrs_0_WIRE_2}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_0_T_10 = _debug_jalrs_0_T_9; // @[core.scala:305:48] wire [2:0] _debug_jalrs_0_T_11 = {2'h0, _debug_jalrs_0_WIRE_0} + {1'h0, _debug_jalrs_0_T_10}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_0_T_12 = _debug_jalrs_0_T_11[1:0]; // @[core.scala:305:48] wire [64:0] _debug_jalrs_0_T_13 = {1'h0, debug_jalrs_0} + {63'h0, _debug_jalrs_0_T_12}; // @[core.scala:292:26, :295:34, :305:{38,48}] wire [63:0] _debug_jalrs_0_T_14 = _debug_jalrs_0_T_13[63:0]; // @[core.scala:305:38] wire _GEN_6 = _rob_io_commit_uops_0_debug_fsrc == 2'h1; // @[core.scala:143:32, :297:41] wire _debug_brs_1_T; // @[core.scala:297:41] assign _debug_brs_1_T = _GEN_6; // @[core.scala:297:41] wire _debug_jals_1_T; // @[core.scala:302:41] assign _debug_jals_1_T = _GEN_6; // @[core.scala:297:41, :302:41] wire _debug_jalrs_1_T; // @[core.scala:307:41] assign _debug_jalrs_1_T = _GEN_6; // @[core.scala:297:41, :307:41] wire _debug_brs_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_1_T; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_1_T_2 = _debug_brs_1_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_1_WIRE_0 = _debug_brs_1_T_2; // @[core.scala:295:52, :297:50] wire _GEN_7 = _rob_io_commit_uops_1_debug_fsrc == 2'h1; // @[core.scala:143:32, :297:41] wire _debug_brs_1_T_3; // @[core.scala:297:41] assign _debug_brs_1_T_3 = _GEN_7; // @[core.scala:297:41] wire _debug_jals_1_T_3; // @[core.scala:302:41] assign _debug_jals_1_T_3 = _GEN_7; // @[core.scala:297:41, :302:41] wire _debug_jalrs_1_T_3; // @[core.scala:307:41] assign _debug_jalrs_1_T_3 = _GEN_7; // @[core.scala:297:41, :307:41] wire _debug_brs_1_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_1_T_3; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_1_T_5 = _debug_brs_1_T_4 & _rob_io_commit_uops_1_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_1_WIRE_1 = _debug_brs_1_T_5; // @[core.scala:295:52, :297:50] wire _GEN_8 = _rob_io_commit_uops_2_debug_fsrc == 2'h1; // @[core.scala:143:32, :297:41] wire _debug_brs_1_T_6; // @[core.scala:297:41] assign _debug_brs_1_T_6 = _GEN_8; // @[core.scala:297:41] wire _debug_jals_1_T_6; // @[core.scala:302:41] assign _debug_jals_1_T_6 = _GEN_8; // @[core.scala:297:41, :302:41] wire _debug_jalrs_1_T_6; // @[core.scala:307:41] assign _debug_jalrs_1_T_6 = _GEN_8; // @[core.scala:297:41, :307:41] wire _debug_brs_1_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_1_T_6; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_1_T_8 = _debug_brs_1_T_7 & _rob_io_commit_uops_2_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_1_WIRE_2 = _debug_brs_1_T_8; // @[core.scala:295:52, :297:50] wire [1:0] _debug_brs_1_T_9 = {1'h0, _debug_brs_1_WIRE_1} + {1'h0, _debug_brs_1_WIRE_2}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_1_T_10 = _debug_brs_1_T_9; // @[core.scala:295:44] wire [2:0] _debug_brs_1_T_11 = {2'h0, _debug_brs_1_WIRE_0} + {1'h0, _debug_brs_1_T_10}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_1_T_12 = _debug_brs_1_T_11[1:0]; // @[core.scala:295:44] wire [64:0] _debug_brs_1_T_13 = {1'h0, debug_brs_1} + {63'h0, _debug_brs_1_T_12}; // @[core.scala:290:26, :295:{34,44}] wire [63:0] _debug_brs_1_T_14 = _debug_brs_1_T_13[63:0]; // @[core.scala:295:34] wire _debug_jals_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_1_T; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_1_T_2 = _debug_jals_1_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_1_WIRE_0 = _debug_jals_1_T_2; // @[core.scala:300:54, :302:50] wire _debug_jals_1_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_1_T_3; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_1_T_5 = _debug_jals_1_T_4 & _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_1_WIRE_1 = _debug_jals_1_T_5; // @[core.scala:300:54, :302:50] wire _debug_jals_1_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_1_T_6; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_1_T_8 = _debug_jals_1_T_7 & _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_1_WIRE_2 = _debug_jals_1_T_8; // @[core.scala:300:54, :302:50] wire [1:0] _debug_jals_1_T_9 = {1'h0, _debug_jals_1_WIRE_1} + {1'h0, _debug_jals_1_WIRE_2}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_1_T_10 = _debug_jals_1_T_9; // @[core.scala:300:46] wire [2:0] _debug_jals_1_T_11 = {2'h0, _debug_jals_1_WIRE_0} + {1'h0, _debug_jals_1_T_10}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_1_T_12 = _debug_jals_1_T_11[1:0]; // @[core.scala:300:46] wire [64:0] _debug_jals_1_T_13 = {1'h0, debug_jals_1} + {63'h0, _debug_jals_1_T_12}; // @[core.scala:291:26, :295:34, :300:{36,46}] wire [63:0] _debug_jals_1_T_14 = _debug_jals_1_T_13[63:0]; // @[core.scala:300:36] wire _debug_jalrs_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_1_T; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_1_T_2 = _debug_jalrs_1_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_1_WIRE_0 = _debug_jalrs_1_T_2; // @[core.scala:305:56, :307:50] wire _debug_jalrs_1_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_1_T_3; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_1_T_5 = _debug_jalrs_1_T_4 & _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_1_WIRE_1 = _debug_jalrs_1_T_5; // @[core.scala:305:56, :307:50] wire _debug_jalrs_1_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_1_T_6; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_1_T_8 = _debug_jalrs_1_T_7 & _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_1_WIRE_2 = _debug_jalrs_1_T_8; // @[core.scala:305:56, :307:50] wire [1:0] _debug_jalrs_1_T_9 = {1'h0, _debug_jalrs_1_WIRE_1} + {1'h0, _debug_jalrs_1_WIRE_2}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_1_T_10 = _debug_jalrs_1_T_9; // @[core.scala:305:48] wire [2:0] _debug_jalrs_1_T_11 = {2'h0, _debug_jalrs_1_WIRE_0} + {1'h0, _debug_jalrs_1_T_10}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_1_T_12 = _debug_jalrs_1_T_11[1:0]; // @[core.scala:305:48] wire [64:0] _debug_jalrs_1_T_13 = {1'h0, debug_jalrs_1} + {63'h0, _debug_jalrs_1_T_12}; // @[core.scala:292:26, :295:34, :305:{38,48}] wire [63:0] _debug_jalrs_1_T_14 = _debug_jalrs_1_T_13[63:0]; // @[core.scala:305:38] wire _GEN_9 = _rob_io_commit_uops_0_debug_fsrc == 2'h2; // @[core.scala:143:32, :297:41] wire _debug_brs_2_T; // @[core.scala:297:41] assign _debug_brs_2_T = _GEN_9; // @[core.scala:297:41] wire _debug_jals_2_T; // @[core.scala:302:41] assign _debug_jals_2_T = _GEN_9; // @[core.scala:297:41, :302:41] wire _debug_jalrs_2_T; // @[core.scala:307:41] assign _debug_jalrs_2_T = _GEN_9; // @[core.scala:297:41, :307:41] wire _debug_brs_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_2_T; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_2_T_2 = _debug_brs_2_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_2_WIRE_0 = _debug_brs_2_T_2; // @[core.scala:295:52, :297:50] wire _GEN_10 = _rob_io_commit_uops_1_debug_fsrc == 2'h2; // @[core.scala:143:32, :297:41] wire _debug_brs_2_T_3; // @[core.scala:297:41] assign _debug_brs_2_T_3 = _GEN_10; // @[core.scala:297:41] wire _debug_jals_2_T_3; // @[core.scala:302:41] assign _debug_jals_2_T_3 = _GEN_10; // @[core.scala:297:41, :302:41] wire _debug_jalrs_2_T_3; // @[core.scala:307:41] assign _debug_jalrs_2_T_3 = _GEN_10; // @[core.scala:297:41, :307:41] wire _debug_brs_2_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_2_T_3; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_2_T_5 = _debug_brs_2_T_4 & _rob_io_commit_uops_1_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_2_WIRE_1 = _debug_brs_2_T_5; // @[core.scala:295:52, :297:50] wire _GEN_11 = _rob_io_commit_uops_2_debug_fsrc == 2'h2; // @[core.scala:143:32, :297:41] wire _debug_brs_2_T_6; // @[core.scala:297:41] assign _debug_brs_2_T_6 = _GEN_11; // @[core.scala:297:41] wire _debug_jals_2_T_6; // @[core.scala:302:41] assign _debug_jals_2_T_6 = _GEN_11; // @[core.scala:297:41, :302:41] wire _debug_jalrs_2_T_6; // @[core.scala:307:41] assign _debug_jalrs_2_T_6 = _GEN_11; // @[core.scala:297:41, :307:41] wire _debug_brs_2_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_2_T_6; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_2_T_8 = _debug_brs_2_T_7 & _rob_io_commit_uops_2_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_2_WIRE_2 = _debug_brs_2_T_8; // @[core.scala:295:52, :297:50] wire [1:0] _debug_brs_2_T_9 = {1'h0, _debug_brs_2_WIRE_1} + {1'h0, _debug_brs_2_WIRE_2}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_2_T_10 = _debug_brs_2_T_9; // @[core.scala:295:44] wire [2:0] _debug_brs_2_T_11 = {2'h0, _debug_brs_2_WIRE_0} + {1'h0, _debug_brs_2_T_10}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_2_T_12 = _debug_brs_2_T_11[1:0]; // @[core.scala:295:44] wire [64:0] _debug_brs_2_T_13 = {1'h0, debug_brs_2} + {63'h0, _debug_brs_2_T_12}; // @[core.scala:290:26, :295:{34,44}] wire [63:0] _debug_brs_2_T_14 = _debug_brs_2_T_13[63:0]; // @[core.scala:295:34] wire _debug_jals_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_2_T; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_2_T_2 = _debug_jals_2_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_2_WIRE_0 = _debug_jals_2_T_2; // @[core.scala:300:54, :302:50] wire _debug_jals_2_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_2_T_3; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_2_T_5 = _debug_jals_2_T_4 & _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_2_WIRE_1 = _debug_jals_2_T_5; // @[core.scala:300:54, :302:50] wire _debug_jals_2_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_2_T_6; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_2_T_8 = _debug_jals_2_T_7 & _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_2_WIRE_2 = _debug_jals_2_T_8; // @[core.scala:300:54, :302:50] wire [1:0] _debug_jals_2_T_9 = {1'h0, _debug_jals_2_WIRE_1} + {1'h0, _debug_jals_2_WIRE_2}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_2_T_10 = _debug_jals_2_T_9; // @[core.scala:300:46] wire [2:0] _debug_jals_2_T_11 = {2'h0, _debug_jals_2_WIRE_0} + {1'h0, _debug_jals_2_T_10}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_2_T_12 = _debug_jals_2_T_11[1:0]; // @[core.scala:300:46] wire [64:0] _debug_jals_2_T_13 = {1'h0, debug_jals_2} + {63'h0, _debug_jals_2_T_12}; // @[core.scala:291:26, :295:34, :300:{36,46}] wire [63:0] _debug_jals_2_T_14 = _debug_jals_2_T_13[63:0]; // @[core.scala:300:36] wire _debug_jalrs_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_2_T; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_2_T_2 = _debug_jalrs_2_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_2_WIRE_0 = _debug_jalrs_2_T_2; // @[core.scala:305:56, :307:50] wire _debug_jalrs_2_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_2_T_3; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_2_T_5 = _debug_jalrs_2_T_4 & _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_2_WIRE_1 = _debug_jalrs_2_T_5; // @[core.scala:305:56, :307:50] wire _debug_jalrs_2_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_2_T_6; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_2_T_8 = _debug_jalrs_2_T_7 & _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_2_WIRE_2 = _debug_jalrs_2_T_8; // @[core.scala:305:56, :307:50] wire [1:0] _debug_jalrs_2_T_9 = {1'h0, _debug_jalrs_2_WIRE_1} + {1'h0, _debug_jalrs_2_WIRE_2}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_2_T_10 = _debug_jalrs_2_T_9; // @[core.scala:305:48] wire [2:0] _debug_jalrs_2_T_11 = {2'h0, _debug_jalrs_2_WIRE_0} + {1'h0, _debug_jalrs_2_T_10}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_2_T_12 = _debug_jalrs_2_T_11[1:0]; // @[core.scala:305:48] wire [64:0] _debug_jalrs_2_T_13 = {1'h0, debug_jalrs_2} + {63'h0, _debug_jalrs_2_T_12}; // @[core.scala:292:26, :295:34, :305:{38,48}] wire [63:0] _debug_jalrs_2_T_14 = _debug_jalrs_2_T_13[63:0]; // @[core.scala:305:38] wire _debug_brs_3_T = &_rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32, :297:41] wire _debug_brs_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_3_T; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_3_T_2 = _debug_brs_3_T_1 & _rob_io_commit_uops_0_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_3_WIRE_0 = _debug_brs_3_T_2; // @[core.scala:295:52, :297:50] wire _debug_brs_3_T_3 = &_rob_io_commit_uops_1_debug_fsrc; // @[core.scala:143:32, :297:41] wire _debug_brs_3_T_4 = _rob_io_commit_arch_valids_1 & _debug_brs_3_T_3; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_3_T_5 = _debug_brs_3_T_4 & _rob_io_commit_uops_1_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_3_WIRE_1 = _debug_brs_3_T_5; // @[core.scala:295:52, :297:50] wire _debug_brs_3_T_6 = &_rob_io_commit_uops_2_debug_fsrc; // @[core.scala:143:32, :297:41] wire _debug_brs_3_T_7 = _rob_io_commit_arch_valids_2 & _debug_brs_3_T_6; // @[core.scala:143:32, :296:36, :297:41] wire _debug_brs_3_T_8 = _debug_brs_3_T_7 & _rob_io_commit_uops_2_is_br; // @[core.scala:143:32, :296:36, :297:50] wire _debug_brs_3_WIRE_2 = _debug_brs_3_T_8; // @[core.scala:295:52, :297:50] wire [1:0] _debug_brs_3_T_9 = {1'h0, _debug_brs_3_WIRE_1} + {1'h0, _debug_brs_3_WIRE_2}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_3_T_10 = _debug_brs_3_T_9; // @[core.scala:295:44] wire [2:0] _debug_brs_3_T_11 = {2'h0, _debug_brs_3_WIRE_0} + {1'h0, _debug_brs_3_T_10}; // @[core.scala:295:{44,52}] wire [1:0] _debug_brs_3_T_12 = _debug_brs_3_T_11[1:0]; // @[core.scala:295:44] wire [64:0] _debug_brs_3_T_13 = {1'h0, debug_brs_3} + {63'h0, _debug_brs_3_T_12}; // @[core.scala:290:26, :295:{34,44}] wire [63:0] _debug_brs_3_T_14 = _debug_brs_3_T_13[63:0]; // @[core.scala:295:34] wire _debug_jals_3_T = &_rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32, :297:41, :302:41] wire _debug_jals_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_3_T; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_3_T_2 = _debug_jals_3_T_1 & _rob_io_commit_uops_0_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_3_WIRE_0 = _debug_jals_3_T_2; // @[core.scala:300:54, :302:50] wire _debug_jals_3_T_3 = &_rob_io_commit_uops_1_debug_fsrc; // @[core.scala:143:32, :297:41, :302:41] wire _debug_jals_3_T_4 = _rob_io_commit_arch_valids_1 & _debug_jals_3_T_3; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_3_T_5 = _debug_jals_3_T_4 & _rob_io_commit_uops_1_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_3_WIRE_1 = _debug_jals_3_T_5; // @[core.scala:300:54, :302:50] wire _debug_jals_3_T_6 = &_rob_io_commit_uops_2_debug_fsrc; // @[core.scala:143:32, :297:41, :302:41] wire _debug_jals_3_T_7 = _rob_io_commit_arch_valids_2 & _debug_jals_3_T_6; // @[core.scala:143:32, :301:36, :302:41] wire _debug_jals_3_T_8 = _debug_jals_3_T_7 & _rob_io_commit_uops_2_is_jal; // @[core.scala:143:32, :301:36, :302:50] wire _debug_jals_3_WIRE_2 = _debug_jals_3_T_8; // @[core.scala:300:54, :302:50] wire [1:0] _debug_jals_3_T_9 = {1'h0, _debug_jals_3_WIRE_1} + {1'h0, _debug_jals_3_WIRE_2}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_3_T_10 = _debug_jals_3_T_9; // @[core.scala:300:46] wire [2:0] _debug_jals_3_T_11 = {2'h0, _debug_jals_3_WIRE_0} + {1'h0, _debug_jals_3_T_10}; // @[core.scala:300:{46,54}] wire [1:0] _debug_jals_3_T_12 = _debug_jals_3_T_11[1:0]; // @[core.scala:300:46] wire [64:0] _debug_jals_3_T_13 = {1'h0, debug_jals_3} + {63'h0, _debug_jals_3_T_12}; // @[core.scala:291:26, :295:34, :300:{36,46}] wire [63:0] _debug_jals_3_T_14 = _debug_jals_3_T_13[63:0]; // @[core.scala:300:36] wire _debug_jalrs_3_T = &_rob_io_commit_uops_0_debug_fsrc; // @[core.scala:143:32, :297:41, :307:41] wire _debug_jalrs_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_3_T; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_3_T_2 = _debug_jalrs_3_T_1 & _rob_io_commit_uops_0_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_3_WIRE_0 = _debug_jalrs_3_T_2; // @[core.scala:305:56, :307:50] wire _debug_jalrs_3_T_3 = &_rob_io_commit_uops_1_debug_fsrc; // @[core.scala:143:32, :297:41, :307:41] wire _debug_jalrs_3_T_4 = _rob_io_commit_arch_valids_1 & _debug_jalrs_3_T_3; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_3_T_5 = _debug_jalrs_3_T_4 & _rob_io_commit_uops_1_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_3_WIRE_1 = _debug_jalrs_3_T_5; // @[core.scala:305:56, :307:50] wire _debug_jalrs_3_T_6 = &_rob_io_commit_uops_2_debug_fsrc; // @[core.scala:143:32, :297:41, :307:41] wire _debug_jalrs_3_T_7 = _rob_io_commit_arch_valids_2 & _debug_jalrs_3_T_6; // @[core.scala:143:32, :306:36, :307:41] wire _debug_jalrs_3_T_8 = _debug_jalrs_3_T_7 & _rob_io_commit_uops_2_is_jalr; // @[core.scala:143:32, :306:36, :307:50] wire _debug_jalrs_3_WIRE_2 = _debug_jalrs_3_T_8; // @[core.scala:305:56, :307:50] wire [1:0] _debug_jalrs_3_T_9 = {1'h0, _debug_jalrs_3_WIRE_1} + {1'h0, _debug_jalrs_3_WIRE_2}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_3_T_10 = _debug_jalrs_3_T_9; // @[core.scala:305:48] wire [2:0] _debug_jalrs_3_T_11 = {2'h0, _debug_jalrs_3_WIRE_0} + {1'h0, _debug_jalrs_3_T_10}; // @[core.scala:305:{48,56}] wire [1:0] _debug_jalrs_3_T_12 = _debug_jalrs_3_T_11[1:0]; // @[core.scala:305:48] wire [64:0] _debug_jalrs_3_T_13 = {1'h0, debug_jalrs_3} + {63'h0, _debug_jalrs_3_T_12}; // @[core.scala:292:26, :295:34, :305:{38,48}] wire [63:0] _debug_jalrs_3_T_14 = _debug_jalrs_3_T_13[63:0]; // @[core.scala:305:38] wire [64:0] _debug_tsc_reg_T = {1'h0, debug_tsc_reg} + 65'h1; // @[core.scala:288:30, :316:34] wire [63:0] _debug_tsc_reg_T_1 = _debug_tsc_reg_T[63:0]; // @[core.scala:316:34] wire [1:0] _GEN_12 = {_rob_io_commit_arch_valids_2, _rob_io_commit_arch_valids_1}; // @[core.scala:143:32, :317:71] wire [1:0] debug_irt_reg_hi; // @[core.scala:317:71] assign debug_irt_reg_hi = _GEN_12; // @[core.scala:317:71] wire [1:0] csr_io_retire_hi; // @[core.scala:1015:66] assign csr_io_retire_hi = _GEN_12; // @[core.scala:317:71, :1015:66] wire [2:0] _debug_irt_reg_T = {debug_irt_reg_hi, _rob_io_commit_arch_valids_0}; // @[core.scala:143:32, :317:71] wire _debug_irt_reg_T_1 = _debug_irt_reg_T[0]; // @[core.scala:317:{44,71}] wire _debug_irt_reg_T_2 = _debug_irt_reg_T[1]; // @[core.scala:317:{44,71}] wire _debug_irt_reg_T_3 = _debug_irt_reg_T[2]; // @[core.scala:317:{44,71}] wire [1:0] _debug_irt_reg_T_4 = {1'h0, _debug_irt_reg_T_2} + {1'h0, _debug_irt_reg_T_3}; // @[core.scala:317:44] wire [1:0] _debug_irt_reg_T_5 = _debug_irt_reg_T_4; // @[core.scala:317:44] wire [2:0] _debug_irt_reg_T_6 = {2'h0, _debug_irt_reg_T_1} + {1'h0, _debug_irt_reg_T_5}; // @[core.scala:317:44] wire [1:0] _debug_irt_reg_T_7 = _debug_irt_reg_T_6[1:0]; // @[core.scala:317:44] wire [64:0] _debug_irt_reg_T_8 = {1'h0, debug_irt_reg} + {63'h0, _debug_irt_reg_T_7}; // @[core.scala:289:30, :295:34, :317:{34,44}] wire [63:0] _debug_irt_reg_T_9 = _debug_irt_reg_T_8[63:0]; // @[core.scala:317:34] wire _io_ifu_flush_icache_T = _rob_io_commit_arch_valids_0 & _rob_io_commit_uops_0_is_fencei; // @[core.scala:143:32, :388:35] wire _io_ifu_flush_icache_T_1 = dec_valids_0 & dec_uops_0_is_jalr; // @[core.scala:157:24, :158:24, :389:28] wire _io_ifu_flush_icache_T_2 = _io_ifu_flush_icache_T_1 & _csr_io_status_debug; // @[core.scala:271:19, :389:{28,51}] reg io_ifu_flush_icache_REG; // @[core.scala:389:13] wire _io_ifu_flush_icache_T_3 = _io_ifu_flush_icache_T \| io_ifu_flush_icache_REG; // @[core.scala:388:{35,71}, :389:13] wire _io_ifu_flush_icache_T_4 = _rob_io_commit_arch_valids_1 & _rob_io_commit_uops_1_is_fencei; // @[core.scala:143:32, :388:35] wire _io_ifu_flush_icache_T_5 = dec_valids_1 & dec_uops_1_is_jalr; // @[core.scala:157:24, :158:24, :389:28] wire _io_ifu_flush_icache_T_6 = _io_ifu_flush_icache_T_5 & _csr_io_status_debug; // @[core.scala:271:19, :389:{28,51}] reg io_ifu_flush_icache_REG_1; // @[core.scala:389:13] wire _io_ifu_flush_icache_T_7 = _io_ifu_flush_icache_T_4 \| io_ifu_flush_icache_REG_1; // @[core.scala:388:{35,71}, :389:13] wire _io_ifu_flush_icache_T_8 = _rob_io_commit_arch_valids_2 & _rob_io_commit_uops_2_is_fencei; // @[core.scala:143:32, :388:35] wire _io_ifu_flush_icache_T_9 = dec_valids_2 & dec_uops_2_is_jalr; // @[core.scala:157:24, :158:24, :389:28] wire _io_ifu_flush_icache_T_10 = _io_ifu_flush_icache_T_9 & _csr_io_status_debug; // @[core.scala:271:19, :389:{28,51}] reg io_ifu_flush_icache_REG_2; // @[core.scala:389:13] wire _io_ifu_flush_icache_T_11 = _io_ifu_flush_icache_T_8 \| io_ifu_flush_icache_REG_2; // @[core.scala:388:{35,71}, :389:13] wire _io_ifu_flush_icache_T_12 = _io_ifu_flush_icache_T_3 \| _io_ifu_flush_icache_T_7; // @[core.scala:388:71, :390:13] assign _io_ifu_flush_icache_T_13 = _io_ifu_flush_icache_T_12 \| _io_ifu_flush_icache_T_11; // @[core.scala:388:71, :390:13] assign io_ifu_flush_icache_0 = _io_ifu_flush_icache_T_13; // @[core.scala:51:7, :390:13] reg REG; // @[core.scala:401:16] reg [2:0] flush_typ; // @[core.scala:404:28] wire _io_ifu_redirect_pc_T = flush_typ == 3'h3; // @[core.scala:404:28, :411:44] reg [39:0] io_ifu_redirect_pc_REG; // @[core.scala:412:49] reg [39:0] io_ifu_redirect_pc_REG_1; // @[core.scala:412:41] wire [39:0] _io_ifu_redirect_pc_T_1 = _io_ifu_redirect_pc_T ? io_ifu_redirect_pc_REG_1 : _csr_io_evec; // @[core.scala:271:19, :411:{33,44}, :412:41] wire [39:0] _flush_pc_T = ~io_ifu_get_pc_0_pc_0; // @[util.scala:237:7] wire [39:0] _flush_pc_T_1 = {_flush_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}] wire [39:0] _flush_pc_T_2 = ~_flush_pc_T_1; // @[util.scala:237:{5,11}] reg [5:0] flush_pc_REG; // @[core.scala:416:32] wire [40:0] _flush_pc_T_3 = {1'h0, _flush_pc_T_2} + {35'h0, flush_pc_REG}; // @[util.scala:237:5] wire [39:0] _flush_pc_T_4 = _flush_pc_T_3[39:0]; // @[core.scala:416:23] reg flush_pc_REG_1; // @[core.scala:417:36] wire [1:0] _flush_pc_T_5 = {flush_pc_REG_1, 1'h0}; // @[core.scala:417:{28,36}] wire [40:0] _flush_pc_T_6 = {1'h0, _flush_pc_T_4} - {39'h0, _flush_pc_T_5}; // @[core.scala:416:23, :417:{23,28}] wire [39:0] flush_pc = _flush_pc_T_6[39:0]; // @[core.scala:417:23] reg flush_pc_next_REG; // @[core.scala:418:49] wire [2:0] _flush_pc_next_T = flush_pc_next_REG ? 3'h2 : 3'h4; // @[core.scala:418:{41,49}] wire [40:0] _flush_pc_next_T_1 = {1'h0, flush_pc} + {38'h0, _flush_pc_next_T}; // @[core.scala:417:23, :418:{36,41}] wire [39:0] flush_pc_next = _flush_pc_next_T_1[39:0]; // @[core.scala:418:36] wire _io_ifu_redirect_pc_T_2 = flush_typ == 3'h2; // @[rob.scala:167:40] wire [39:0] _io_ifu_redirect_pc_T_3 = _io_ifu_redirect_pc_T_2 ? flush_pc : flush_pc_next; // @[rob.scala:167:40] reg [4:0] io_ifu_redirect_ftq_idx_REG; // @[core.scala:423:39] reg REG_1; // @[core.scala:424:50] wire _T_18 = brupdate_b2_mispredict & ~REG_1; // @[core.scala:188:23, :424:{39,42,50}] wire [39:0] _block_pc_T = ~io_ifu_get_pc_1_pc_0; // @[util.scala:237:7] wire [39:0] _block_pc_T_1 = {_block_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}] wire [39:0] block_pc = ~_block_pc_T_1; // @[util.scala:237:{5,11}] wire [39:0] uop_maybe_pc = {block_pc[39:6], block_pc[5:0] \| brupdate_b2_uop_pc_lob}; // @[util.scala:237:5] wire [39:0] _jal_br_target_T = uop_maybe_pc; // @[core.scala:426:33, :429:36] wire _npc_T = brupdate_b2_uop_is_rvc \| brupdate_b2_uop_edge_inst; // @[core.scala:188:23, :427:57] wire [2:0] _npc_T_1 = _npc_T ? 3'h2 : 3'h4; // @[core.scala:427:{33,57}] wire [40:0] _npc_T_2 = {1'h0, uop_maybe_pc} + {38'h0, _npc_T_1}; // @[core.scala:418:36, :426:33, :427:{28,33}] wire [39:0] npc = _npc_T_2[39:0]; // @[core.scala:427:28] wire [39:0] _jal_br_target_T_10; // @[core.scala:430:75] wire [39:0] jal_br_target; // @[core.scala:428:29] wire [40:0] _jal_br_target_T_1 = {_jal_br_target_T[39], _jal_br_target_T} + {{20{brupdate_b2_target_offset[20]}}, brupdate_b2_target_offset}; // @[core.scala:188:23, :429:{36,43}] wire [39:0] _jal_br_target_T_2 = _jal_br_target_T_1[39:0]; // @[core.scala:429:43] wire [39:0] _jal_br_target_T_3 = _jal_br_target_T_2; // @[core.scala:429:43] wire [38:0] _jal_br_target_T_4 = {39{brupdate_b2_uop_edge_inst}}; // @[core.scala:188:23, :430:12] wire [39:0] _jal_br_target_T_5 = {_jal_br_target_T_4, 1'h0}; // @[core.scala:430:{12,61}] wire [39:0] _jal_br_target_T_6 = _jal_br_target_T_5; // @[core.scala:430:{61,67}] wire [40:0] _jal_br_target_T_7 = {_jal_br_target_T_3[39], _jal_br_target_T_3} + {_jal_br_target_T_6[39], _jal_br_target_T_6}; // @[core.scala:429:{43,71}, :430:67] wire [39:0] _jal_br_target_T_8 = _jal_br_target_T_7[39:0]; // @[core.scala:429:71] wire [39:0] _jal_br_target_T_9 = _jal_br_target_T_8; // @[core.scala:429:71] assign _jal_br_target_T_10 = _jal_br_target_T_9; // @[core.scala:429:71, :430:75] assign jal_br_target = _jal_br_target_T_10; // @[core.scala:428:29, :430:75] wire _bj_addr_T = brupdate_b2_cfi_type == 3'h3; // @[core.scala:188:23, :431:44] wire [39:0] bj_addr = _bj_addr_T ? brupdate_b2_jalr_target : jal_br_target; // @[core.scala:188:23, :428:29, :431:{22,44}] wire _mispredict_target_T = brupdate_b2_pc_sel == 2'h0; // @[core.scala:188:23, :432:52] wire [39:0] mispredict_target = _mispredict_target_T ? npc : bj_addr; // @[core.scala:427:28, :431:22, :432:{32,52}] assign io_ifu_redirect_val_0 = REG \| _T_18; // @[core.scala:51:7, :401:{16,38}, :402:27, :424:{39,72}] assign io_ifu_redirect_pc_0 = REG ? (flush_typ[0] ? _io_ifu_redirect_pc_T_1 : _io_ifu_redirect_pc_T_3) : mispredict_target; // @[rob.scala:166:40] assign io_ifu_redirect_ftq_idx_0 = REG ? io_ifu_redirect_ftq_idx_REG : brupdate_b2_uop_ftq_idx; // @[core.scala:51:7, :188:23, :401:{16,38}, :423:{29,39}, :424:72] wire _GEN_13 = brupdate_b2_cfi_type == 3'h1; // @[core.scala:188:23, :437:48] wire _use_same_ghist_T; // @[core.scala:437:48] assign _use_same_ghist_T = _GEN_13; // @[core.scala:437:48] wire _next_ghist_T; // @[core.scala:447:28] assign _next_ghist_T = _GEN_13; // @[core.scala:437:48, :447:28] wire _use_same_ghist_T_1 = ~brupdate_b2_taken; // @[core.scala:188:23, :438:27] wire _use_same_ghist_T_2 = _use_same_ghist_T & _use_same_ghist_T_1; // @[core.scala:437:{48,59}, :438:27] wire [39:0] _use_same_ghist_T_3 = ~block_pc; // @[util.scala:237:5] wire [39:0] _use_same_ghist_T_4 = {_use_same_ghist_T_3[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] _use_same_ghist_T_5 = ~_use_same_ghist_T_4; // @[frontend.scala:160:{31,39}] wire [39:0] _use_same_ghist_T_6 = ~npc; // @[frontend.scala:160:33] wire [39:0] _use_same_ghist_T_7 = {_use_same_ghist_T_6[39:3], 3'h7}; // @[frontend.scala:160:{33,39}] wire [39:0] _use_same_ghist_T_8 = ~_use_same_ghist_T_7; // @[frontend.scala:160:{31,39}] wire _use_same_ghist_T_9 = _use_same_ghist_T_5 == _use_same_ghist_T_8; // @[frontend.scala:160:31] wire use_same_ghist = _use_same_ghist_T_2 & _use_same_ghist_T_9; // @[core.scala:437:59, :438:46, :439:47] wire [3:0] _cfi_idx_T_2 = {_cfi_idx_T, 3'h0}; // @[core.scala:442:{10,32}] wire [5:0] _cfi_idx_T_3 = {brupdate_b2_uop_pc_lob[5:4], brupdate_b2_uop_pc_lob[3:0] ^ _cfi_idx_T_2}; // @[core.scala:188:23, :441:43, :442:10] wire [2:0] cfi_idx = _cfi_idx_T_3[3:1]; // @[core.scala:441:43, :442:74] wire [2:0] next_ghist_cfi_idx_fixed = cfi_idx; // @[frontend.scala:85:32] wire _GEN_14 = io_ifu_get_pc_1_entry_cfi_idx_bits_0 == cfi_idx; // @[core.scala:51:7, :442:74, :451:55] wire _next_ghist_T_1; // @[core.scala:451:55] assign _next_ghist_T_1 = _GEN_14; // @[core.scala:451:55] wire _next_ghist_T_3; // @[core.scala:452:55] assign _next_ghist_T_3 = _GEN_14; // @[core.scala:451:55, :452:55] wire _next_ghist_T_2 = io_ifu_get_pc_1_entry_cfi_is_call_0 & _next_ghist_T_1; // @[core.scala:51:7, :451:{29,55}] wire _next_ghist_new_history_ras_idx_T = _next_ghist_T_2; // @[frontend.scala:123:42] wire _next_ghist_T_4 = io_ifu_get_pc_1_entry_cfi_is_ret_0 & _next_ghist_T_3; // @[core.scala:51:7, :452:{29,55}] wire _next_ghist_new_history_ras_idx_T_4 = _next_ghist_T_4; // @[frontend.scala:124:42] wire [7:0] next_ghist_cfi_idx_oh = 8'h1 << next_ghist_cfi_idx_fixed; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T = next_ghist_cfi_idx_oh; // @[OneHot.scala:58:35] wire [4:0] _next_ghist_new_history_ras_idx_T_9; // @[frontend.scala:123:31] wire [63:0] next_ghist_old_history; // @[frontend.scala:87:27] wire next_ghist_new_saw_branch_not_taken; // @[frontend.scala:87:27] wire next_ghist_new_saw_branch_taken; // @[frontend.scala:87:27] wire [4:0] next_ghist_ras_idx; // @[frontend.scala:87:27] wire [7:0] _next_ghist_not_taken_branches_T_1 = {1'h0, next_ghist_cfi_idx_oh[7:1]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_2 = {2'h0, next_ghist_cfi_idx_oh[7:2]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_3 = {3'h0, next_ghist_cfi_idx_oh[7:3]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_4 = {4'h0, next_ghist_cfi_idx_oh[7:4]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_5 = {5'h0, next_ghist_cfi_idx_oh[7:5]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_6 = {6'h0, next_ghist_cfi_idx_oh[7:6]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_7 = {7'h0, next_ghist_cfi_idx_oh[7]}; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_8 = _next_ghist_not_taken_branches_T \| _next_ghist_not_taken_branches_T_1; // @[util.scala:373:{29,45}] wire [7:0] _next_ghist_not_taken_branches_T_9 = _next_ghist_not_taken_branches_T_8 \| _next_ghist_not_taken_branches_T_2; // @[util.scala:373:{29,45}] wire [7:0] _next_ghist_not_taken_branches_T_10 = _next_ghist_not_taken_branches_T_9 \| _next_ghist_not_taken_branches_T_3; // @[util.scala:373:{29,45}] wire [7:0] _next_ghist_not_taken_branches_T_11 = _next_ghist_not_taken_branches_T_10 \| _next_ghist_not_taken_branches_T_4; // @[util.scala:373:{29,45}] wire [7:0] _next_ghist_not_taken_branches_T_12 = _next_ghist_not_taken_branches_T_11 \| _next_ghist_not_taken_branches_T_5; // @[util.scala:373:{29,45}] wire [7:0] _next_ghist_not_taken_branches_T_13 = _next_ghist_not_taken_branches_T_12 \| _next_ghist_not_taken_branches_T_6; // @[util.scala:373:{29,45}] wire [7:0] _next_ghist_not_taken_branches_T_14 = _next_ghist_not_taken_branches_T_13 \| _next_ghist_not_taken_branches_T_7; // @[util.scala:373:{29,45}] wire _next_ghist_not_taken_branches_T_15 = _next_ghist_T & brupdate_b2_taken; // @[frontend.scala:90:84] wire [7:0] _next_ghist_not_taken_branches_T_16 = _next_ghist_not_taken_branches_T_15 ? next_ghist_cfi_idx_oh : 8'h0; // @[OneHot.scala:58:35] wire [7:0] _next_ghist_not_taken_branches_T_17 = ~_next_ghist_not_taken_branches_T_16; // @[frontend.scala:90:{69,73}] wire [7:0] _next_ghist_not_taken_branches_T_18 = _next_ghist_not_taken_branches_T_14 & _next_ghist_not_taken_branches_T_17; // @[util.scala:373:45] wire [7:0] _next_ghist_not_taken_branches_T_20 = _next_ghist_not_taken_branches_T_18; // @[frontend.scala:89:44, :90:67] wire [7:0] next_ghist_not_taken_branches = io_ifu_get_pc_1_entry_br_mask_0 & _next_ghist_not_taken_branches_T_20; // @[frontend.scala:89:{39,44}] wire [64:0] _GEN_15 = {io_ifu_get_pc_1_ghist_old_history_0, 1'h0}; // @[frontend.scala:67:75] wire [64:0] _next_ghist_base_T; // @[frontend.scala:67:75] assign _next_ghist_base_T = _GEN_15; // @[frontend.scala:67:75] wire [64:0] _next_ghist_base_T_2; // @[frontend.scala:68:75] assign _next_ghist_base_T_2 = _GEN_15; // @[frontend.scala:67:75, :68:75] wire [64:0] _next_ghist_new_history_old_history_T; // @[frontend.scala:67:75] assign _next_ghist_new_history_old_history_T = _GEN_15; // @[frontend.scala:67:75] wire [64:0] _next_ghist_new_history_old_history_T_2; // @[frontend.scala:68:75] assign _next_ghist_new_history_old_history_T_2 = _GEN_15; // @[frontend.scala:67:75, :68:75] wire [64:0] _next_ghist_new_history_old_history_T_6; // @[frontend.scala:67:75] assign _next_ghist_new_history_old_history_T_6 = _GEN_15; // @[frontend.scala:67:75] wire [64:0] _next_ghist_new_history_old_history_T_8; // @[frontend.scala:68:75] assign _next_ghist_new_history_old_history_T_8 = _GEN_15; // @[frontend.scala:67:75, :68:75] wire [64:0] _next_ghist_new_history_old_history_T_13; // @[frontend.scala:67:75] assign _next_ghist_new_history_old_history_T_13 = _GEN_15; // @[frontend.scala:67:75] wire [64:0] _next_ghist_new_history_old_history_T_15; // @[frontend.scala:68:75] assign _next_ghist_new_history_old_history_T_15 = _GEN_15; // @[frontend.scala:67:75, :68:75] wire [64:0] _next_ghist_new_history_old_history_T_19; // @[frontend.scala:67:75] assign _next_ghist_new_history_old_history_T_19 = _GEN_15; // @[frontend.scala:67:75] wire [64:0] _next_ghist_new_history_old_history_T_21; // @[frontend.scala:68:75] assign _next_ghist_new_history_old_history_T_21 = _GEN_15; // @[frontend.scala:67:75, :68:75] wire [64:0] _next_ghist_base_T_1 = {_next_ghist_base_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _GEN_16 = {1'h0, io_ifu_get_pc_1_ghist_old_history_0}; // @[frontend.scala:68:12] wire [64:0] _next_ghist_base_T_3 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_base_T_2 : _GEN_16; // @[frontend.scala:68:{12,75}] wire [64:0] next_ghist_base = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_base_T_1 : _next_ghist_base_T_3; // @[frontend.scala:67:{12,80}, :68:12] wire _next_ghist_cfi_in_bank_0_T_1 = ~(next_ghist_cfi_idx_fixed[2]); // @[frontend.scala:85:32, :104:67] wire next_ghist_cfi_in_bank_0 = _next_ghist_cfi_in_bank_0_T & _next_ghist_cfi_in_bank_0_T_1; // @[frontend.scala:104:{37,50,67}] wire [2:0] _next_ghist_ignore_second_bank_T = io_ifu_get_pc_1_pc_0[5:3]; // @[frontend.scala:152:28] wire _next_ghist_ignore_second_bank_T_1 = &_next_ghist_ignore_second_bank_T; // @[frontend.scala:152:{28,66}] wire _next_ghist_ignore_second_bank_T_2 = _next_ghist_ignore_second_bank_T_1; // @[frontend.scala:152:{21,66}] wire next_ghist_ignore_second_bank = next_ghist_cfi_in_bank_0 \| _next_ghist_ignore_second_bank_T_2; // @[frontend.scala:104:50, :105:46, :152:21] wire [3:0] _next_ghist_first_bank_saw_not_taken_T = next_ghist_not_taken_branches[3:0]; // @[frontend.scala:89:39, :107:56] wire _next_ghist_first_bank_saw_not_taken_T_1 = \|_next_ghist_first_bank_saw_not_taken_T; // @[frontend.scala:107:{56,72}] wire next_ghist_first_bank_saw_not_taken = _next_ghist_first_bank_saw_not_taken_T_1 \| io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0; // @[frontend.scala:107:{72,80}] wire [64:0] _next_ghist_new_history_old_history_T_1 = {_next_ghist_new_history_old_history_T[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _next_ghist_new_history_old_history_T_3 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_2 : _GEN_16; // @[frontend.scala:68:{12,75}] wire [64:0] _next_ghist_new_history_old_history_T_4 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_1 : _next_ghist_new_history_old_history_T_3; // @[frontend.scala:67:{12,80}, :68:12] wire _GEN_17 = _next_ghist_T & next_ghist_cfi_in_bank_0; // @[frontend.scala:104:50, :112:59] wire _next_ghist_new_history_new_saw_branch_taken_T; // @[frontend.scala:112:59] assign _next_ghist_new_history_new_saw_branch_taken_T = _GEN_17; // @[frontend.scala:112:59] wire _next_ghist_new_history_old_history_T_5; // @[frontend.scala:114:50] assign _next_ghist_new_history_old_history_T_5 = _GEN_17; // @[frontend.scala:112:59, :114:50] wire [64:0] _next_ghist_new_history_old_history_T_7 = {_next_ghist_new_history_old_history_T_6[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _next_ghist_new_history_old_history_T_9 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_8 : _GEN_16; // @[frontend.scala:68:{12,75}] wire [64:0] _next_ghist_new_history_old_history_T_10 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_7 : _next_ghist_new_history_old_history_T_9; // @[frontend.scala:67:{12,80}, :68:12] wire [65:0] _next_ghist_new_history_old_history_T_11 = {_next_ghist_new_history_old_history_T_10, 1'h0}; // @[frontend.scala:67:12, :114:110] wire [65:0] _next_ghist_new_history_old_history_T_12 = {_next_ghist_new_history_old_history_T_11[65:1], 1'h1}; // @[frontend.scala:114:{110,115}] wire [64:0] _next_ghist_new_history_old_history_T_14 = {_next_ghist_new_history_old_history_T_13[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _next_ghist_new_history_old_history_T_16 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_15 : _GEN_16; // @[frontend.scala:68:{12,75}] wire [64:0] _next_ghist_new_history_old_history_T_17 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_14 : _next_ghist_new_history_old_history_T_16; // @[frontend.scala:67:{12,80}, :68:12] wire [65:0] _next_ghist_new_history_old_history_T_18 = {_next_ghist_new_history_old_history_T_17, 1'h0}; // @[frontend.scala:67:12, :115:110] wire [64:0] _next_ghist_new_history_old_history_T_20 = {_next_ghist_new_history_old_history_T_19[64:1], 1'h1}; // @[frontend.scala:67:{75,80}] wire [64:0] _next_ghist_new_history_old_history_T_22 = io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 ? _next_ghist_new_history_old_history_T_21 : _GEN_16; // @[frontend.scala:68:{12,75}] wire [64:0] _next_ghist_new_history_old_history_T_23 = io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 ? _next_ghist_new_history_old_history_T_20 : _next_ghist_new_history_old_history_T_22; // @[frontend.scala:67:{12,80}, :68:12] wire [65:0] _next_ghist_new_history_old_history_T_24 = next_ghist_first_bank_saw_not_taken ? _next_ghist_new_history_old_history_T_18 : {1'h0, _next_ghist_new_history_old_history_T_23}; // @[frontend.scala:67:12, :107:80, :115:{39,110}] wire [65:0] _next_ghist_new_history_old_history_T_25 = _next_ghist_new_history_old_history_T_5 ? _next_ghist_new_history_old_history_T_12 : _next_ghist_new_history_old_history_T_24; // @[frontend.scala:114:{39,50,115}, :115:39] assign next_ghist_old_history = next_ghist_ignore_second_bank ? _next_ghist_new_history_old_history_T_4[63:0] : _next_ghist_new_history_old_history_T_25[63:0]; // @[frontend.scala:67:12, :87:27, :105:46, :109:33, :110:33, :114:{33,39}] wire [3:0] _next_ghist_new_history_new_saw_branch_not_taken_T = next_ghist_not_taken_branches[7:4]; // @[frontend.scala:89:39, :118:67] wire _next_ghist_new_history_new_saw_branch_not_taken_T_1 = \|_next_ghist_new_history_new_saw_branch_not_taken_T; // @[frontend.scala:118:{67,92}] assign next_ghist_new_saw_branch_not_taken = next_ghist_ignore_second_bank ? next_ghist_first_bank_saw_not_taken : _next_ghist_new_history_new_saw_branch_not_taken_T_1; // @[frontend.scala:87:27, :105:46, :107:80, :109:33, :111:46, :118:{46,92}] wire _next_ghist_new_history_new_saw_branch_taken_T_2 = _next_ghist_new_history_new_saw_branch_taken_T_1 & _next_ghist_T; // @[frontend.scala:119:{59,72}] wire _next_ghist_new_history_new_saw_branch_taken_T_3 = ~next_ghist_cfi_in_bank_0; // @[frontend.scala:104:50, :119:88] wire _next_ghist_new_history_new_saw_branch_taken_T_4 = _next_ghist_new_history_new_saw_branch_taken_T_2 & _next_ghist_new_history_new_saw_branch_taken_T_3; // @[frontend.scala:119:{72,85,88}] assign next_ghist_new_saw_branch_taken = next_ghist_ignore_second_bank ? _next_ghist_new_history_new_saw_branch_taken_T : _next_ghist_new_history_new_saw_branch_taken_T_4; // @[frontend.scala:87:27, :105:46, :109:33, :112:{46,59}, :119:{46,85}] wire [5:0] _GEN_18 = {1'h0, io_ifu_get_pc_1_ghist_ras_idx_0}; // @[util.scala:203:14] wire [5:0] _next_ghist_new_history_ras_idx_T_1 = _GEN_18 + 6'h1; // @[util.scala:203:14] wire [4:0] _next_ghist_new_history_ras_idx_T_2 = _next_ghist_new_history_ras_idx_T_1[4:0]; // @[util.scala:203:14] wire [4:0] _next_ghist_new_history_ras_idx_T_3 = _next_ghist_new_history_ras_idx_T_2; // @[util.scala:203:{14,20}] wire [5:0] _next_ghist_new_history_ras_idx_T_5 = _GEN_18 - 6'h1; // @[util.scala:203:14, :220:14] wire [4:0] _next_ghist_new_history_ras_idx_T_6 = _next_ghist_new_history_ras_idx_T_5[4:0]; // @[util.scala:220:14] wire [4:0] _next_ghist_new_history_ras_idx_T_7 = _next_ghist_new_history_ras_idx_T_6; // @[util.scala:220:{14,20}] wire [4:0] _next_ghist_new_history_ras_idx_T_8 = _next_ghist_new_history_ras_idx_T_4 ? _next_ghist_new_history_ras_idx_T_7 : io_ifu_get_pc_1_ghist_ras_idx_0; // @[util.scala:220:20] assign _next_ghist_new_history_ras_idx_T_9 = _next_ghist_new_history_ras_idx_T ? _next_ghist_new_history_ras_idx_T_3 : _next_ghist_new_history_ras_idx_T_8; // @[util.scala:203:20] assign next_ghist_ras_idx = _next_ghist_new_history_ras_idx_T_9; // @[frontend.scala:87:27, :123:31] wire [63:0] _io_ifu_redirect_ghist_T_old_history = use_same_ghist ? io_ifu_get_pc_1_ghist_old_history_0 : next_ghist_old_history; // @[frontend.scala:87:27] wire _io_ifu_redirect_ghist_T_current_saw_branch_not_taken = use_same_ghist & io_ifu_get_pc_1_ghist_current_saw_branch_not_taken_0; // @[core.scala:51:7, :438:46, :455:35] wire _io_ifu_redirect_ghist_T_new_saw_branch_not_taken = use_same_ghist ? io_ifu_get_pc_1_ghist_new_saw_branch_not_taken_0 : next_ghist_new_saw_branch_not_taken; // @[frontend.scala:87:27] wire _io_ifu_redirect_ghist_T_new_saw_branch_taken = use_same_ghist ? io_ifu_get_pc_1_ghist_new_saw_branch_taken_0 : next_ghist_new_saw_branch_taken; // @[frontend.scala:87:27] wire [4:0] _io_ifu_redirect_ghist_T_ras_idx = use_same_ghist ? io_ifu_get_pc_1_ghist_ras_idx_0 : next_ghist_ras_idx; // @[frontend.scala:87:27] assign io_ifu_redirect_ghist_old_history_0 = REG ? 64'h0 : _io_ifu_redirect_ghist_T_old_history; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35] assign io_ifu_redirect_ghist_new_saw_branch_not_taken_0 = ~REG & _io_ifu_redirect_ghist_T_new_saw_branch_not_taken; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35] assign io_ifu_redirect_ghist_new_saw_branch_taken_0 = ~REG & _io_ifu_redirect_ghist_T_new_saw_branch_taken; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :455:35] assign io_ifu_redirect_ghist_ras_idx_0 = REG ? new_ghist_ras_idx : _io_ifu_redirect_ghist_T_ras_idx; // @[core.scala:51:7, :401:{16,38}, :406:29, :409:27, :424:72, :455:35] assign io_ifu_redirect_ghist_current_saw_branch_not_taken_0 = REG \| use_same_ghist; // @[core.scala:51:7, :401:{16,38}, :409:27, :424:72, :438:46] assign io_ifu_redirect_flush_0 = REG \| _T_18 \| (\|{_rob_io_flush_frontend, brupdate_b1_mispredict_mask}); // @[core.scala:51:7, :143:32, :188:23, :224:42, :401:{16,38}, :403:27, :424:{39,72}, :435:29, :460:{38,78}] wire [1:0] _youngest_com_idx_T = _rob_io_commit_valids_1 ? 2'h1 : 2'h2; // @[Mux.scala:50:70] wire [1:0] _youngest_com_idx_T_1 = _rob_io_commit_valids_2 ? 2'h0 : _youngest_com_idx_T; // @[Mux.scala:50:70] wire [2:0] _youngest_com_idx_T_2 = 3'h2 - {1'h0, _youngest_com_idx_T_1}; // @[Mux.scala:50:70] wire [1:0] youngest_com_idx = _youngest_com_idx_T_2[1:0]; // @[core.scala:465:42] wire _io_ifu_commit_valid_T = _rob_io_commit_valids_0 \| _rob_io_commit_valids_1; // @[core.scala:143:32, :466:55] wire _io_ifu_commit_valid_T_1 = _io_ifu_commit_valid_T \| _rob_io_commit_valids_2; // @[core.scala:143:32, :466:55] wire _io_ifu_commit_valid_T_2 = _io_ifu_commit_valid_T_1 \| _rob_io_com_xcpt_valid; // @[core.scala:143:32, :466:{55,59}] wire [3:0][4:0] _GEN_19 = {{_rob_io_commit_uops_0_ftq_idx}, {_rob_io_commit_uops_2_ftq_idx}, {_rob_io_commit_uops_1_ftq_idx}, {_rob_io_commit_uops_0_ftq_idx}}; // @[core.scala:143:32, :467:29] wire [4:0] _io_ifu_commit_bits_T = _rob_io_com_xcpt_valid ? _rob_io_com_xcpt_bits_ftq_idx : _GEN_19[youngest_com_idx]; // @[core.scala:143:32, :465:42, :467:29] reg REG_2; // @[core.scala:475:18] reg io_ifu_sfence_REG_valid; // @[core.scala:476:31] assign io_ifu_sfence_valid_0 = io_ifu_sfence_REG_valid; // @[core.scala:51:7, :476:31] reg io_ifu_sfence_REG_bits_rs1; // @[core.scala:476:31] assign io_ifu_sfence_bits_rs1_0 = io_ifu_sfence_REG_bits_rs1; // @[core.scala:51:7, :476:31] reg io_ifu_sfence_REG_bits_rs2; // @[core.scala:476:31] assign io_ifu_sfence_bits_rs2_0 = io_ifu_sfence_REG_bits_rs2; // @[core.scala:51:7, :476:31] reg [38:0] io_ifu_sfence_REG_bits_addr; // @[core.scala:476:31] assign io_ifu_sfence_bits_addr_0 = io_ifu_sfence_REG_bits_addr; // @[core.scala:51:7, :476:31] reg io_ifu_sfence_REG_bits_asid; // @[core.scala:476:31] assign io_ifu_sfence_bits_asid_0 = io_ifu_sfence_REG_bits_asid; // @[core.scala:51:7, :476:31] reg [2:0] dec_finished_mask; // @[core.scala:496:34] wire _dec_valids_0_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_0_valid_0; // @[core.scala:51:7, :508:68] wire _dec_valids_0_T_1 = dec_finished_mask[0]; // @[core.scala:496:34, :509:61] wire _dec_brmask_logic_io_is_branch_0_T = dec_finished_mask[0]; // @[core.scala:496:34, :509:61, :600:59] wire _dec_valids_0_T_2 = ~_dec_valids_0_T_1; // @[core.scala:509:{43,61}] assign _dec_valids_0_T_3 = _dec_valids_0_T & _dec_valids_0_T_2; // @[core.scala:508:{68,97}, :509:43] assign dec_valids_0 = _dec_valids_0_T_3; // @[core.scala:157:24, :508:97] wire _dec_valids_1_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_1_valid_0; // @[core.scala:51:7, :508:68] wire _dec_valids_1_T_1 = dec_finished_mask[1]; // @[core.scala:496:34, :509:61] wire _dec_brmask_logic_io_is_branch_1_T = dec_finished_mask[1]; // @[core.scala:496:34, :509:61, :600:59] wire _dec_valids_1_T_2 = ~_dec_valids_1_T_1; // @[core.scala:509:{43,61}] assign _dec_valids_1_T_3 = _dec_valids_1_T & _dec_valids_1_T_2; // @[core.scala:508:{68,97}, :509:43] assign dec_valids_1 = _dec_valids_1_T_3; // @[core.scala:157:24, :508:97] wire _dec_valids_2_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_2_valid_0; // @[core.scala:51:7, :508:68] wire _dec_valids_2_T_1 = dec_finished_mask[2]; // @[core.scala:496:34, :509:61] wire _dec_brmask_logic_io_is_branch_2_T = dec_finished_mask[2]; // @[core.scala:496:34, :509:61, :600:59] wire _dec_valids_2_T_2 = ~_dec_valids_2_T_1; // @[core.scala:509:{43,61}] assign _dec_valids_2_T_3 = _dec_valids_2_T & _dec_valids_2_T_2; // @[core.scala:508:{68,97}, :509:43] assign dec_valids_2 = _dec_valids_2_T_3; // @[core.scala:157:24, :508:97] wire jmp_pc_req_ready; // @[core.scala:522:25] wire jmp_pc_req_valid; // @[core.scala:522:25] wire [4:0] jmp_pc_req_bits; // @[core.scala:522:25] wire _xcpt_pc_req_valid_T_1; // @[core.scala:551:45] wire xcpt_pc_req_ready; // @[core.scala:523:25] wire xcpt_pc_req_valid; // @[core.scala:523:25] wire [4:0] xcpt_pc_req_bits; // @[core.scala:523:25] wire flush_pc_req_valid; // @[core.scala:524:26] wire [4:0] flush_pc_req_bits; // @[core.scala:524:26] wire _jmp_pc_req_valid_T = iss_uops_1_fu_code == 10'h2; // @[core.scala:173:24, :539:90] wire _jmp_pc_req_valid_T_1 = iss_valids_1 & _jmp_pc_req_valid_T; // @[core.scala:172:24, :539:{56,90}] reg jmp_pc_req_valid_REG; // @[core.scala:539:30] assign jmp_pc_req_valid = jmp_pc_req_valid_REG; // @[core.scala:522:25, :539:30] reg [4:0] jmp_pc_req_bits_REG; // @[core.scala:540:30] assign jmp_pc_req_bits = jmp_pc_req_bits_REG; // @[core.scala:522:25, :540:30] wire [1:0] _xcpt_idx_T = dec_xcpts_1 ? 2'h1 : 2'h2; // @[Mux.scala:50:70] wire [1:0] xcpt_idx = dec_xcpts_0 ? 2'h0 : _xcpt_idx_T; // @[Mux.scala:50:70] wire _GEN_20 = dec_xcpts_0 \| dec_xcpts_1; // @[core.scala:162:24, :551:45] wire _xcpt_pc_req_valid_T; // @[core.scala:551:45] assign _xcpt_pc_req_valid_T = _GEN_20; // @[core.scala:551:45] wire _dec_xcpt_stall_T; // @[core.scala:567:42] assign _dec_xcpt_stall_T = _GEN_20; // @[core.scala:551:45, :567:42] assign _xcpt_pc_req_valid_T_1 = _xcpt_pc_req_valid_T \| dec_xcpts_2; // @[core.scala:162:24, :551:45] assign xcpt_pc_req_valid = _xcpt_pc_req_valid_T_1; // @[core.scala:523:25, :551:45] wire [3:0][4:0] _GEN_21 = {{dec_uops_0_ftq_idx}, {dec_uops_2_ftq_idx}, {dec_uops_1_ftq_idx}, {dec_uops_0_ftq_idx}}; // @[core.scala:158:24, :552:24] assign xcpt_pc_req_bits = _GEN_21[xcpt_idx]; // @[Mux.scala:50:70] assign dec_xcpts_0 = dec_uops_0_exception & dec_valids_0; // @[core.scala:157:24, :158:24, :162:24, :566:71] assign dec_xcpts_1 = dec_uops_1_exception & dec_valids_1; // @[core.scala:157:24, :158:24, :162:24, :566:71] assign dec_xcpts_2 = dec_uops_2_exception & dec_valids_2; // @[core.scala:157:24, :158:24, :162:24, :566:71] wire _dec_xcpt_stall_T_1 = _dec_xcpt_stall_T \| dec_xcpts_2; // @[core.scala:162:24, :567:42] wire _dec_xcpt_stall_T_2 = ~xcpt_pc_req_ready; // @[core.scala:523:25, :567:50] wire dec_xcpt_stall = _dec_xcpt_stall_T_1 & _dec_xcpt_stall_T_2; // @[core.scala:567:{42,47,50}] wire branch_mask_full_0; // @[core.scala:569:30] wire branch_mask_full_1; // @[core.scala:569:30] wire branch_mask_full_2; // @[core.scala:569:30] wire _dec_hazards_T = ~dis_ready; // @[core.scala:169:24, :573:26] wire _dec_hazards_T_1 = _dec_hazards_T \| _rob_io_commit_rollback; // @[core.scala:143:32, :573:26, :574:23] wire _dec_hazards_T_2 = _dec_hazards_T_1 \| dec_xcpt_stall; // @[core.scala:567:47, :574:23, :575:23] wire _dec_hazards_T_3 = _dec_hazards_T_2 \| branch_mask_full_0; // @[core.scala:569:30, :575:23, :576:23] wire _dec_hazards_T_4 = \|brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :577:54] wire _dec_hazards_T_5 = _dec_hazards_T_3 \| _dec_hazards_T_4; // @[core.scala:576:23, :577:{23,54}] wire _dec_hazards_T_6 = _dec_hazards_T_5 \| brupdate_b2_mispredict; // @[core.scala:188:23, :577:23, :578:23] wire _dec_hazards_T_7 = _dec_hazards_T_6 \| io_ifu_redirect_flush_0; // @[core.scala:51:7, :578:23, :579:23] wire dec_hazards_0 = dec_valids_0 & _dec_hazards_T_7; // @[core.scala:157:24, :572:37, :579:23] wire dec_stalls_0 = dec_hazards_0; // @[core.scala:572:37, :581:62] wire _dec_hazards_T_8 = ~dis_ready; // @[core.scala:169:24, :573:26] wire _dec_hazards_T_9 = _dec_hazards_T_8 \| _rob_io_commit_rollback; // @[core.scala:143:32, :573:26, :574:23] wire _dec_hazards_T_10 = _dec_hazards_T_9 \| dec_xcpt_stall; // @[core.scala:567:47, :574:23, :575:23] wire _dec_hazards_T_11 = _dec_hazards_T_10 \| branch_mask_full_1; // @[core.scala:569:30, :575:23, :576:23] wire _dec_hazards_T_12 = \|brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :577:54] wire _dec_hazards_T_13 = _dec_hazards_T_11 \| _dec_hazards_T_12; // @[core.scala:576:23, :577:{23,54}] wire _dec_hazards_T_14 = _dec_hazards_T_13 \| brupdate_b2_mispredict; // @[core.scala:188:23, :577:23, :578:23] wire _dec_hazards_T_15 = _dec_hazards_T_14 \| io_ifu_redirect_flush_0; // @[core.scala:51:7, :578:23, :579:23] wire dec_hazards_1 = dec_valids_1 & _dec_hazards_T_15; // @[core.scala:157:24, :572:37, :579:23] wire _dec_hazards_T_16 = ~dis_ready; // @[core.scala:169:24, :573:26] wire _dec_hazards_T_17 = _dec_hazards_T_16 \| _rob_io_commit_rollback; // @[core.scala:143:32, :573:26, :574:23] wire _dec_hazards_T_18 = _dec_hazards_T_17 \| dec_xcpt_stall; // @[core.scala:567:47, :574:23, :575:23] wire _dec_hazards_T_19 = _dec_hazards_T_18 \| branch_mask_full_2; // @[core.scala:569:30, :575:23, :576:23] wire _dec_hazards_T_20 = \|brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :577:54] wire _dec_hazards_T_21 = _dec_hazards_T_19 \| _dec_hazards_T_20; // @[core.scala:576:23, :577:{23,54}] wire _dec_hazards_T_22 = _dec_hazards_T_21 \| brupdate_b2_mispredict; // @[core.scala:188:23, :577:23, :578:23] wire _dec_hazards_T_23 = _dec_hazards_T_22 \| io_ifu_redirect_flush_0; // @[core.scala:51:7, :578:23, :579:23] wire dec_hazards_2 = dec_valids_2 & _dec_hazards_T_23; // @[core.scala:157:24, :572:37, :579:23] wire dec_stalls_1 = dec_stalls_0 \| dec_hazards_1; // @[core.scala:572:37, :581:62] wire dec_stalls_2 = dec_stalls_1 \| dec_hazards_2; // @[core.scala:572:37, :581:62] assign dec_fire_0 = dec_valids_0 & ~dec_stalls_0; // @[core.scala:157:24, :159:24, :581:62, :582:{58,61}] assign dec_fire_1 = dec_valids_1 & ~dec_stalls_1; // @[core.scala:157:24, :159:24, :581:62, :582:{58,61}] assign dec_fire_2 = dec_valids_2 & ~dec_stalls_2; // @[core.scala:157:24, :159:24, :581:62, :582:{58,61}] wire [1:0] dec_finished_mask_hi = {dec_fire_2, dec_fire_1}; // @[core.scala:159:24, :590:35] wire [2:0] _dec_finished_mask_T = {dec_finished_mask_hi, dec_fire_0}; // @[core.scala:159:24, :590:35] wire [2:0] _dec_finished_mask_T_1 = _dec_finished_mask_T \| dec_finished_mask; // @[core.scala:496:34, :590:{35,42}] reg dec_brmask_logic_io_flush_pipeline_REG; // @[core.scala:597:48] wire _dec_brmask_logic_io_is_branch_0_T_1 = ~_dec_brmask_logic_io_is_branch_0_T; // @[core.scala:600:{41,59}] wire _dec_brmask_logic_io_is_branch_0_T_2 = ~dec_uops_0_is_sfb; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_0_T_3 = dec_uops_0_is_br & _dec_brmask_logic_io_is_branch_0_T_2; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_0_T_4 = _dec_brmask_logic_io_is_branch_0_T_3 \| dec_uops_0_is_jalr; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_0_T_5 = _dec_brmask_logic_io_is_branch_0_T_1 & _dec_brmask_logic_io_is_branch_0_T_4; // @[core.scala:600:{41,63}] wire _dec_brmask_logic_io_will_fire_0_T = ~dec_uops_0_is_sfb; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_0_T_1 = dec_uops_0_is_br & _dec_brmask_logic_io_will_fire_0_T; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_0_T_2 = _dec_brmask_logic_io_will_fire_0_T_1 \| dec_uops_0_is_jalr; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_0_T_3 = dec_fire_0 & _dec_brmask_logic_io_will_fire_0_T_2; // @[core.scala:159:24, :601:54] wire _dec_brmask_logic_io_is_branch_1_T_1 = ~_dec_brmask_logic_io_is_branch_1_T; // @[core.scala:600:{41,59}] wire _dec_brmask_logic_io_is_branch_1_T_2 = ~dec_uops_1_is_sfb; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_1_T_3 = dec_uops_1_is_br & _dec_brmask_logic_io_is_branch_1_T_2; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_1_T_4 = _dec_brmask_logic_io_is_branch_1_T_3 \| dec_uops_1_is_jalr; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_1_T_5 = _dec_brmask_logic_io_is_branch_1_T_1 & _dec_brmask_logic_io_is_branch_1_T_4; // @[core.scala:600:{41,63}] wire _dec_brmask_logic_io_will_fire_1_T = ~dec_uops_1_is_sfb; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_1_T_1 = dec_uops_1_is_br & _dec_brmask_logic_io_will_fire_1_T; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_1_T_2 = _dec_brmask_logic_io_will_fire_1_T_1 \| dec_uops_1_is_jalr; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_1_T_3 = dec_fire_1 & _dec_brmask_logic_io_will_fire_1_T_2; // @[core.scala:159:24, :601:54] wire _dec_brmask_logic_io_is_branch_2_T_1 = ~_dec_brmask_logic_io_is_branch_2_T; // @[core.scala:600:{41,59}] wire _dec_brmask_logic_io_is_branch_2_T_2 = ~dec_uops_2_is_sfb; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_2_T_3 = dec_uops_2_is_br & _dec_brmask_logic_io_is_branch_2_T_2; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_2_T_4 = _dec_brmask_logic_io_is_branch_2_T_3 \| dec_uops_2_is_jalr; // @[core.scala:158:24] wire _dec_brmask_logic_io_is_branch_2_T_5 = _dec_brmask_logic_io_is_branch_2_T_1 & _dec_brmask_logic_io_is_branch_2_T_4; // @[core.scala:600:{41,63}] wire _dec_brmask_logic_io_will_fire_2_T = ~dec_uops_2_is_sfb; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_2_T_1 = dec_uops_2_is_br & _dec_brmask_logic_io_will_fire_2_T; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_2_T_2 = _dec_brmask_logic_io_will_fire_2_T_1 \| dec_uops_2_is_jalr; // @[core.scala:158:24] wire _dec_brmask_logic_io_will_fire_2_T_3 = dec_fire_2 & _dec_brmask_logic_io_will_fire_2_T_2; // @[core.scala:159:24, :601:54] wire _GEN_22 = dis_uops_0_lrs1_rtype == 2'h1; // @[core.scala:167:24, :654:52] wire _dis_uops_0_prs1_T; // @[core.scala:654:52] assign _dis_uops_0_prs1_T = _GEN_22; // @[core.scala:654:52] wire _dis_uops_0_prs1_busy_T_2; // @[core.scala:665:73] assign _dis_uops_0_prs1_busy_T_2 = _GEN_22; // @[core.scala:654:52, :665:73] wire _GEN_23 = dis_uops_0_lrs1_rtype == 2'h0; // @[core.scala:167:24, :655:52] wire _dis_uops_0_prs1_T_1; // @[core.scala:655:52] assign _dis_uops_0_prs1_T_1 = _GEN_23; // @[core.scala:655:52] wire _dis_uops_0_prs1_busy_T; // @[core.scala:664:73] assign _dis_uops_0_prs1_busy_T = _GEN_23; // @[core.scala:655:52, :664:73] wire [6:0] _dis_uops_0_prs1_T_2 = _dis_uops_0_prs1_T_1 ? _rename_stage_io_ren2_uops_0_prs1 : {1'h0, dis_uops_0_lrs1}; // @[core.scala:103:32, :167:24, :655:{28,52}] assign _dis_uops_0_prs1_T_3 = _dis_uops_0_prs1_T ? _fp_rename_stage_io_ren2_uops_0_prs1 : _dis_uops_0_prs1_T_2; // @[core.scala:104:46, :654:{28,52}, :655:28] assign dis_uops_0_prs1 = _dis_uops_0_prs1_T_3; // @[core.scala:167:24, :654:28] wire _GEN_24 = dis_uops_0_lrs2_rtype == 2'h1; // @[core.scala:167:24, :656:52] wire _dis_uops_0_prs2_T; // @[core.scala:656:52] assign _dis_uops_0_prs2_T = _GEN_24; // @[core.scala:656:52] wire _dis_uops_0_prs2_busy_T_2; // @[core.scala:667:73] assign _dis_uops_0_prs2_busy_T_2 = _GEN_24; // @[core.scala:656:52, :667:73] assign _dis_uops_0_prs2_T_1 = _dis_uops_0_prs2_T ? _fp_rename_stage_io_ren2_uops_0_prs2 : _rename_stage_io_ren2_uops_0_prs2; // @[core.scala:103:32, :104:46, :656:{28,52}] assign dis_uops_0_prs2 = _dis_uops_0_prs2_T_1; // @[core.scala:167:24, :656:28] wire _GEN_25 = dis_uops_0_dst_rtype == 2'h1; // @[core.scala:167:24, :659:52] wire _dis_uops_0_pdst_T; // @[core.scala:659:52] assign _dis_uops_0_pdst_T = _GEN_25; // @[core.scala:659:52] wire _dis_uops_0_stale_pdst_T; // @[core.scala:662:57] assign _dis_uops_0_stale_pdst_T = _GEN_25; // @[core.scala:659:52, :662:57] wire _dis_uops_0_pdst_T_1 = dis_uops_0_dst_rtype == 2'h0; // @[core.scala:167:24, :660:52] wire [6:0] _dis_uops_0_pdst_T_2 = _dis_uops_0_pdst_T_1 ? _rename_stage_io_ren2_uops_0_pdst : 7'h0; // @[core.scala:103:32, :660:{28,52}] assign _dis_uops_0_pdst_T_3 = _dis_uops_0_pdst_T ? _fp_rename_stage_io_ren2_uops_0_pdst : _dis_uops_0_pdst_T_2; // @[core.scala:104:46, :659:{28,52}, :660:28] assign dis_uops_0_pdst = _dis_uops_0_pdst_T_3; // @[core.scala:167:24, :659:28] assign _dis_uops_0_stale_pdst_T_1 = _dis_uops_0_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_0_stale_pdst : _rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:103:32, :104:46, :662:{34,57}] assign dis_uops_0_stale_pdst = _dis_uops_0_stale_pdst_T_1; // @[core.scala:167:24, :662:34] wire _dis_uops_0_prs1_busy_T_1 = _rename_stage_io_ren2_uops_0_prs1_busy & _dis_uops_0_prs1_busy_T; // @[core.scala:103:32, :664:{46,73}] wire _dis_uops_0_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_0_prs1_busy & _dis_uops_0_prs1_busy_T_2; // @[core.scala:104:46, :665:{46,73}] assign _dis_uops_0_prs1_busy_T_4 = _dis_uops_0_prs1_busy_T_1 \| _dis_uops_0_prs1_busy_T_3; // @[core.scala:664:{46,85}, :665:46] assign dis_uops_0_prs1_busy = _dis_uops_0_prs1_busy_T_4; // @[core.scala:167:24, :664:85] wire _dis_uops_0_prs2_busy_T = dis_uops_0_lrs2_rtype == 2'h0; // @[core.scala:167:24, :666:73] wire _dis_uops_0_prs2_busy_T_1 = _rename_stage_io_ren2_uops_0_prs2_busy & _dis_uops_0_prs2_busy_T; // @[core.scala:103:32, :666:{46,73}] wire _dis_uops_0_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_0_prs2_busy & _dis_uops_0_prs2_busy_T_2; // @[core.scala:104:46, :667:{46,73}] assign _dis_uops_0_prs2_busy_T_4 = _dis_uops_0_prs2_busy_T_1 \| _dis_uops_0_prs2_busy_T_3; // @[core.scala:666:{46,85}, :667:46] assign dis_uops_0_prs2_busy = _dis_uops_0_prs2_busy_T_4; // @[core.scala:167:24, :666:85] assign _dis_uops_0_prs3_busy_T = _fp_rename_stage_io_ren2_uops_0_prs3_busy & dis_uops_0_frs3_en; // @[core.scala:104:46, :167:24, :668:46] assign dis_uops_0_prs3_busy = _dis_uops_0_prs3_busy_T; // @[core.scala:167:24, :668:46] wire _dis_uops_0_ppred_busy_T = ~dis_uops_0_is_br; // @[core.scala:167:24] wire _dis_uops_0_ppred_busy_T_1 = _dis_uops_0_ppred_busy_T & dis_uops_0_is_sfb; // @[core.scala:167:24] wire _ren_stalls_0_T = _rename_stage_io_ren_stalls_0 \| _fp_rename_stage_io_ren_stalls_0; // @[core.scala:103:32, :104:46, :671:52] assign _ren_stalls_0_T_1 = _ren_stalls_0_T; // @[core.scala:671:{52,63}] assign ren_stalls_0 = _ren_stalls_0_T_1; // @[core.scala:163:24, :671:63] wire _GEN_26 = dis_uops_1_lrs1_rtype == 2'h1; // @[core.scala:167:24, :654:52] wire _dis_uops_1_prs1_T; // @[core.scala:654:52] assign _dis_uops_1_prs1_T = _GEN_26; // @[core.scala:654:52] wire _dis_uops_1_prs1_busy_T_2; // @[core.scala:665:73] assign _dis_uops_1_prs1_busy_T_2 = _GEN_26; // @[core.scala:654:52, :665:73] wire _GEN_27 = dis_uops_1_lrs1_rtype == 2'h0; // @[core.scala:167:24, :655:52] wire _dis_uops_1_prs1_T_1; // @[core.scala:655:52] assign _dis_uops_1_prs1_T_1 = _GEN_27; // @[core.scala:655:52] wire _dis_uops_1_prs1_busy_T; // @[core.scala:664:73] assign _dis_uops_1_prs1_busy_T = _GEN_27; // @[core.scala:655:52, :664:73] wire [6:0] _dis_uops_1_prs1_T_2 = _dis_uops_1_prs1_T_1 ? _rename_stage_io_ren2_uops_1_prs1 : {1'h0, dis_uops_1_lrs1}; // @[core.scala:103:32, :167:24, :655:{28,52}] assign _dis_uops_1_prs1_T_3 = _dis_uops_1_prs1_T ? _fp_rename_stage_io_ren2_uops_1_prs1 : _dis_uops_1_prs1_T_2; // @[core.scala:104:46, :654:{28,52}, :655:28] assign dis_uops_1_prs1 = _dis_uops_1_prs1_T_3; // @[core.scala:167:24, :654:28] wire _GEN_28 = dis_uops_1_lrs2_rtype == 2'h1; // @[core.scala:167:24, :656:52] wire _dis_uops_1_prs2_T; // @[core.scala:656:52] assign _dis_uops_1_prs2_T = _GEN_28; // @[core.scala:656:52] wire _dis_uops_1_prs2_busy_T_2; // @[core.scala:667:73] assign _dis_uops_1_prs2_busy_T_2 = _GEN_28; // @[core.scala:656:52, :667:73] assign _dis_uops_1_prs2_T_1 = _dis_uops_1_prs2_T ? _fp_rename_stage_io_ren2_uops_1_prs2 : _rename_stage_io_ren2_uops_1_prs2; // @[core.scala:103:32, :104:46, :656:{28,52}] assign dis_uops_1_prs2 = _dis_uops_1_prs2_T_1; // @[core.scala:167:24, :656:28] wire _GEN_29 = dis_uops_1_dst_rtype == 2'h1; // @[core.scala:167:24, :659:52] wire _dis_uops_1_pdst_T; // @[core.scala:659:52] assign _dis_uops_1_pdst_T = _GEN_29; // @[core.scala:659:52] wire _dis_uops_1_stale_pdst_T; // @[core.scala:662:57] assign _dis_uops_1_stale_pdst_T = _GEN_29; // @[core.scala:659:52, :662:57] wire _dis_uops_1_pdst_T_1 = dis_uops_1_dst_rtype == 2'h0; // @[core.scala:167:24, :660:52] wire [6:0] _dis_uops_1_pdst_T_2 = _dis_uops_1_pdst_T_1 ? _rename_stage_io_ren2_uops_1_pdst : 7'h0; // @[core.scala:103:32, :660:{28,52}] assign _dis_uops_1_pdst_T_3 = _dis_uops_1_pdst_T ? _fp_rename_stage_io_ren2_uops_1_pdst : _dis_uops_1_pdst_T_2; // @[core.scala:104:46, :659:{28,52}, :660:28] assign dis_uops_1_pdst = _dis_uops_1_pdst_T_3; // @[core.scala:167:24, :659:28] assign _dis_uops_1_stale_pdst_T_1 = _dis_uops_1_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_1_stale_pdst : _rename_stage_io_ren2_uops_1_stale_pdst; // @[core.scala:103:32, :104:46, :662:{34,57}] assign dis_uops_1_stale_pdst = _dis_uops_1_stale_pdst_T_1; // @[core.scala:167:24, :662:34] wire _dis_uops_1_prs1_busy_T_1 = _rename_stage_io_ren2_uops_1_prs1_busy & _dis_uops_1_prs1_busy_T; // @[core.scala:103:32, :664:{46,73}] wire _dis_uops_1_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_1_prs1_busy & _dis_uops_1_prs1_busy_T_2; // @[core.scala:104:46, :665:{46,73}] assign _dis_uops_1_prs1_busy_T_4 = _dis_uops_1_prs1_busy_T_1 \| _dis_uops_1_prs1_busy_T_3; // @[core.scala:664:{46,85}, :665:46] assign dis_uops_1_prs1_busy = _dis_uops_1_prs1_busy_T_4; // @[core.scala:167:24, :664:85] wire _dis_uops_1_prs2_busy_T = dis_uops_1_lrs2_rtype == 2'h0; // @[core.scala:167:24, :666:73] wire _dis_uops_1_prs2_busy_T_1 = _rename_stage_io_ren2_uops_1_prs2_busy & _dis_uops_1_prs2_busy_T; // @[core.scala:103:32, :666:{46,73}] wire _dis_uops_1_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_1_prs2_busy & _dis_uops_1_prs2_busy_T_2; // @[core.scala:104:46, :667:{46,73}] assign _dis_uops_1_prs2_busy_T_4 = _dis_uops_1_prs2_busy_T_1 \| _dis_uops_1_prs2_busy_T_3; // @[core.scala:666:{46,85}, :667:46] assign dis_uops_1_prs2_busy = _dis_uops_1_prs2_busy_T_4; // @[core.scala:167:24, :666:85] assign _dis_uops_1_prs3_busy_T = _fp_rename_stage_io_ren2_uops_1_prs3_busy & dis_uops_1_frs3_en; // @[core.scala:104:46, :167:24, :668:46] assign dis_uops_1_prs3_busy = _dis_uops_1_prs3_busy_T; // @[core.scala:167:24, :668:46] wire _dis_uops_1_ppred_busy_T = ~dis_uops_1_is_br; // @[core.scala:167:24] wire _dis_uops_1_ppred_busy_T_1 = _dis_uops_1_ppred_busy_T & dis_uops_1_is_sfb; // @[core.scala:167:24] wire _ren_stalls_1_T = _rename_stage_io_ren_stalls_1 \| _fp_rename_stage_io_ren_stalls_1; // @[core.scala:103:32, :104:46, :671:52] assign _ren_stalls_1_T_1 = _ren_stalls_1_T; // @[core.scala:671:{52,63}] assign ren_stalls_1 = _ren_stalls_1_T_1; // @[core.scala:163:24, :671:63] wire _GEN_30 = dis_uops_2_lrs1_rtype == 2'h1; // @[core.scala:167:24, :654:52] wire _dis_uops_2_prs1_T; // @[core.scala:654:52] assign _dis_uops_2_prs1_T = _GEN_30; // @[core.scala:654:52] wire _dis_uops_2_prs1_busy_T_2; // @[core.scala:665:73] assign _dis_uops_2_prs1_busy_T_2 = _GEN_30; // @[core.scala:654:52, :665:73] wire _GEN_31 = dis_uops_2_lrs1_rtype == 2'h0; // @[core.scala:167:24, :655:52] wire _dis_uops_2_prs1_T_1; // @[core.scala:655:52] assign _dis_uops_2_prs1_T_1 = _GEN_31; // @[core.scala:655:52] wire _dis_uops_2_prs1_busy_T; // @[core.scala:664:73] assign _dis_uops_2_prs1_busy_T = _GEN_31; // @[core.scala:655:52, :664:73] wire [6:0] _dis_uops_2_prs1_T_2 = _dis_uops_2_prs1_T_1 ? _rename_stage_io_ren2_uops_2_prs1 : {1'h0, dis_uops_2_lrs1}; // @[core.scala:103:32, :167:24, :655:{28,52}] assign _dis_uops_2_prs1_T_3 = _dis_uops_2_prs1_T ? _fp_rename_stage_io_ren2_uops_2_prs1 : _dis_uops_2_prs1_T_2; // @[core.scala:104:46, :654:{28,52}, :655:28] assign dis_uops_2_prs1 = _dis_uops_2_prs1_T_3; // @[core.scala:167:24, :654:28] wire _GEN_32 = dis_uops_2_lrs2_rtype == 2'h1; // @[core.scala:167:24, :656:52] wire _dis_uops_2_prs2_T; // @[core.scala:656:52] assign _dis_uops_2_prs2_T = _GEN_32; // @[core.scala:656:52] wire _dis_uops_2_prs2_busy_T_2; // @[core.scala:667:73] assign _dis_uops_2_prs2_busy_T_2 = _GEN_32; // @[core.scala:656:52, :667:73] assign _dis_uops_2_prs2_T_1 = _dis_uops_2_prs2_T ? _fp_rename_stage_io_ren2_uops_2_prs2 : _rename_stage_io_ren2_uops_2_prs2; // @[core.scala:103:32, :104:46, :656:{28,52}] assign dis_uops_2_prs2 = _dis_uops_2_prs2_T_1; // @[core.scala:167:24, :656:28] wire _GEN_33 = dis_uops_2_dst_rtype == 2'h1; // @[core.scala:167:24, :659:52] wire _dis_uops_2_pdst_T; // @[core.scala:659:52] assign _dis_uops_2_pdst_T = _GEN_33; // @[core.scala:659:52] wire _dis_uops_2_stale_pdst_T; // @[core.scala:662:57] assign _dis_uops_2_stale_pdst_T = _GEN_33; // @[core.scala:659:52, :662:57] wire _dis_uops_2_pdst_T_1 = dis_uops_2_dst_rtype == 2'h0; // @[core.scala:167:24, :660:52] wire [6:0] _dis_uops_2_pdst_T_2 = _dis_uops_2_pdst_T_1 ? _rename_stage_io_ren2_uops_2_pdst : 7'h0; // @[core.scala:103:32, :660:{28,52}] assign _dis_uops_2_pdst_T_3 = _dis_uops_2_pdst_T ? _fp_rename_stage_io_ren2_uops_2_pdst : _dis_uops_2_pdst_T_2; // @[core.scala:104:46, :659:{28,52}, :660:28] assign dis_uops_2_pdst = _dis_uops_2_pdst_T_3; // @[core.scala:167:24, :659:28] assign _dis_uops_2_stale_pdst_T_1 = _dis_uops_2_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_2_stale_pdst : _rename_stage_io_ren2_uops_2_stale_pdst; // @[core.scala:103:32, :104:46, :662:{34,57}] assign dis_uops_2_stale_pdst = _dis_uops_2_stale_pdst_T_1; // @[core.scala:167:24, :662:34] wire _dis_uops_2_prs1_busy_T_1 = _rename_stage_io_ren2_uops_2_prs1_busy & _dis_uops_2_prs1_busy_T; // @[core.scala:103:32, :664:{46,73}] wire _dis_uops_2_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_2_prs1_busy & _dis_uops_2_prs1_busy_T_2; // @[core.scala:104:46, :665:{46,73}] assign _dis_uops_2_prs1_busy_T_4 = _dis_uops_2_prs1_busy_T_1 \| _dis_uops_2_prs1_busy_T_3; // @[core.scala:664:{46,85}, :665:46] assign dis_uops_2_prs1_busy = _dis_uops_2_prs1_busy_T_4; // @[core.scala:167:24, :664:85] wire _dis_uops_2_prs2_busy_T = dis_uops_2_lrs2_rtype == 2'h0; // @[core.scala:167:24, :666:73] wire _dis_uops_2_prs2_busy_T_1 = _rename_stage_io_ren2_uops_2_prs2_busy & _dis_uops_2_prs2_busy_T; // @[core.scala:103:32, :666:{46,73}] wire _dis_uops_2_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_2_prs2_busy & _dis_uops_2_prs2_busy_T_2; // @[core.scala:104:46, :667:{46,73}] assign _dis_uops_2_prs2_busy_T_4 = _dis_uops_2_prs2_busy_T_1 \| _dis_uops_2_prs2_busy_T_3; // @[core.scala:666:{46,85}, :667:46] assign dis_uops_2_prs2_busy = _dis_uops_2_prs2_busy_T_4; // @[core.scala:167:24, :666:85] assign _dis_uops_2_prs3_busy_T = _fp_rename_stage_io_ren2_uops_2_prs3_busy & dis_uops_2_frs3_en; // @[core.scala:104:46, :167:24, :668:46] assign dis_uops_2_prs3_busy = _dis_uops_2_prs3_busy_T; // @[core.scala:167:24, :668:46] wire _dis_uops_2_ppred_busy_T = ~dis_uops_2_is_br; // @[core.scala:167:24] wire _dis_uops_2_ppred_busy_T_1 = _dis_uops_2_ppred_busy_T & dis_uops_2_is_sfb; // @[core.scala:167:24] wire _ren_stalls_2_T = _rename_stage_io_ren_stalls_2 \| _fp_rename_stage_io_ren_stalls_2; // @[core.scala:103:32, :104:46, :671:52] assign _ren_stalls_2_T_1 = _ren_stalls_2_T; // @[core.scala:671:{52,63}] assign ren_stalls_2 = _ren_stalls_2_T_1; // @[core.scala:163:24, :671:63] wire dis_prior_slot_valid_2 = dis_prior_slot_valid_1 \| dis_valids_1; // @[core.scala:166:24, :683:71] wire dis_prior_slot_valid_3 = dis_prior_slot_valid_2 \| dis_valids_2; // @[core.scala:166:24, :683:71] wire _dis_prior_slot_unique_T = dis_valids_0 & dis_uops_0_is_unique; // @[core.scala:166:24, :167:24, :684:101] wire dis_prior_slot_unique_1 = _dis_prior_slot_unique_T; // @[core.scala:684:{96,101}] wire _dis_prior_slot_unique_T_1 = dis_valids_1 & dis_uops_1_is_unique; // @[core.scala:166:24, :167:24, :684:101] wire dis_prior_slot_unique_2 = dis_prior_slot_unique_1 \| _dis_prior_slot_unique_T_1; // @[core.scala:684:{96,101}] wire _dis_prior_slot_unique_T_2 = dis_valids_2 & dis_uops_2_is_unique; // @[core.scala:166:24, :167:24, :684:101] wire dis_prior_slot_unique_3 = dis_prior_slot_unique_2 \| _dis_prior_slot_unique_T_2; // @[core.scala:684:{96,101}] wire _wait_for_empty_pipeline_T = custom_csrs_csrs_0_value[3]; // @[core.scala:276:25] wire _wait_for_empty_pipeline_T_6 = custom_csrs_csrs_0_value[3]; // @[core.scala:276:25] wire _wait_for_empty_pipeline_T_12 = custom_csrs_csrs_0_value[3]; // @[core.scala:276:25] wire _wait_for_empty_pipeline_T_1 = dis_uops_0_is_unique \| _wait_for_empty_pipeline_T; // @[core.scala:167:24, :685:85] wire _wait_for_empty_pipeline_T_2 = ~_rob_io_empty; // @[core.scala:143:32, :686:36] wire _wait_for_empty_pipeline_T_3 = ~io_lsu_fencei_rdy_0; // @[core.scala:51:7, :686:53] wire _wait_for_empty_pipeline_T_4 = _wait_for_empty_pipeline_T_2 \| _wait_for_empty_pipeline_T_3; // @[core.scala:686:{36,50,53}] wire _wait_for_empty_pipeline_T_5 = _wait_for_empty_pipeline_T_4; // @[core.scala:686:{50,72}] wire wait_for_empty_pipeline_0 = _wait_for_empty_pipeline_T_1 & _wait_for_empty_pipeline_T_5; // @[core.scala:685:{85,112}, :686:72] wire _wait_for_empty_pipeline_T_7 = dis_uops_1_is_unique \| _wait_for_empty_pipeline_T_6; // @[core.scala:167:24, :685:85] wire _wait_for_empty_pipeline_T_8 = ~_rob_io_empty; // @[core.scala:143:32, :686:36] wire _wait_for_empty_pipeline_T_9 = ~io_lsu_fencei_rdy_0; // @[core.scala:51:7, :686:53] wire _wait_for_empty_pipeline_T_10 = _wait_for_empty_pipeline_T_8 \| _wait_for_empty_pipeline_T_9; // @[core.scala:686:{36,50,53}] wire _wait_for_empty_pipeline_T_11 = _wait_for_empty_pipeline_T_10 \| dis_prior_slot_valid_1; // @[core.scala:683:71, :686:{50,72}] wire wait_for_empty_pipeline_1 = _wait_for_empty_pipeline_T_7 & _wait_for_empty_pipeline_T_11; // @[core.scala:685:{85,112}, :686:72] wire _wait_for_empty_pipeline_T_13 = dis_uops_2_is_unique \| _wait_for_empty_pipeline_T_12; // @[core.scala:167:24, :685:85] wire _wait_for_empty_pipeline_T_14 = ~_rob_io_empty; // @[core.scala:143:32, :686:36] wire _wait_for_empty_pipeline_T_15 = ~io_lsu_fencei_rdy_0; // @[core.scala:51:7, :686:53] wire _wait_for_empty_pipeline_T_16 = _wait_for_empty_pipeline_T_14 \| _wait_for_empty_pipeline_T_15; // @[core.scala:686:{36,50,53}] wire _wait_for_empty_pipeline_T_17 = _wait_for_empty_pipeline_T_16 \| dis_prior_slot_valid_2; // @[core.scala:683:71, :686:{50,72}] wire wait_for_empty_pipeline_2 = _wait_for_empty_pipeline_T_13 & _wait_for_empty_pipeline_T_17; // @[core.scala:685:{85,112}, :686:72] wire _wait_for_rocc_T = dis_uops_0_is_fence \| dis_uops_0_is_fencei; // @[core.scala:167:24, :689:47] wire _wait_for_rocc_T_2 = dis_uops_1_is_fence \| dis_uops_1_is_fencei; // @[core.scala:167:24, :689:47] wire _wait_for_rocc_T_4 = dis_uops_2_is_fence \| dis_uops_2_is_fencei; // @[core.scala:167:24, :689:47] wire _GEN_34 = dis_uops_0_uopc == 7'h6C; // @[core.scala:167:24, :691:76] wire _block_rocc_T; // @[core.scala:691:76] assign _block_rocc_T = _GEN_34; // @[core.scala:691:76] wire _dis_rocc_alloc_stall_T; // @[core.scala:692:51] assign _dis_rocc_alloc_stall_T = _GEN_34; // @[core.scala:691:76, :692:51] wire _block_rocc_T_1 = dis_valids_0 & _block_rocc_T; // @[core.scala:166:24, :691:{66,76}] wire block_rocc_1 = _block_rocc_T_1; // @[core.scala:691:{66,109}] wire _GEN_35 = dis_uops_1_uopc == 7'h6C; // @[core.scala:167:24, :691:76] wire _block_rocc_T_2; // @[core.scala:691:76] assign _block_rocc_T_2 = _GEN_35; // @[core.scala:691:76] wire _dis_rocc_alloc_stall_T_1; // @[core.scala:692:51] assign _dis_rocc_alloc_stall_T_1 = _GEN_35; // @[core.scala:691:76, :692:51] wire _block_rocc_T_3 = dis_valids_1 & _block_rocc_T_2; // @[core.scala:166:24, :691:{66,76}] wire _GEN_36 = dis_uops_2_uopc == 7'h6C; // @[core.scala:167:24, :691:76] wire _block_rocc_T_4; // @[core.scala:691:76] assign _block_rocc_T_4 = _GEN_36; // @[core.scala:691:76] wire _dis_rocc_alloc_stall_T_2; // @[core.scala:692:51] assign _dis_rocc_alloc_stall_T_2 = _GEN_36; // @[core.scala:691:76, :692:51] wire _block_rocc_T_5 = dis_valids_2 & _block_rocc_T_4; // @[core.scala:166:24, :691:{66,76}] wire block_rocc_2 = block_rocc_1 \| _block_rocc_T_3; // @[core.scala:691:{66,109}] wire block_rocc_3 = block_rocc_2 \| _block_rocc_T_5; // @[core.scala:691:{66,109}] wire _dis_hazards_T = ~_rob_io_ready; // @[core.scala:143:32, :697:26] wire _dis_hazards_T_1 = _dis_hazards_T \| ren_stalls_0; // @[core.scala:163:24, :697:26, :698:23] wire _dis_hazards_T_2 = io_lsu_ldq_full_0_0 & dis_uops_0_uses_ldq; // @[core.scala:51:7, :167:24, :699:45] wire _dis_hazards_T_3 = _dis_hazards_T_1 \| _dis_hazards_T_2; // @[core.scala:698:23, :699:{23,45}] wire _dis_hazards_T_4 = io_lsu_stq_full_0_0 & dis_uops_0_uses_stq; // @[core.scala:51:7, :167:24, :700:45] wire _dis_hazards_T_5 = _dis_hazards_T_3 \| _dis_hazards_T_4; // @[core.scala:699:23, :700:{23,45}] wire _dis_hazards_T_6 = ~_dispatcher_io_ren_uops_0_ready; // @[core.scala:114:32, :701:26] wire _dis_hazards_T_7 = _dis_hazards_T_5 \| _dis_hazards_T_6; // @[core.scala:700:23, :701:{23,26}] wire _dis_hazards_T_8 = _dis_hazards_T_7 \| wait_for_empty_pipeline_0; // @[core.scala:685:112, :701:23, :702:23] wire _dis_hazards_T_9 = _dis_hazards_T_8; // @[core.scala:702:23, :703:23] wire _dis_hazards_T_10 = _dis_hazards_T_9; // @[core.scala:703:23, :704:23] wire _dis_hazards_T_11 = _dis_hazards_T_10; // @[core.scala:704:23, :705:23] wire _dis_hazards_T_12 = \|brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :706:54] wire _dis_hazards_T_13 = _dis_hazards_T_11 \| _dis_hazards_T_12; // @[core.scala:705:23, :706:{23,54}] wire _dis_hazards_T_14 = _dis_hazards_T_13 \| brupdate_b2_mispredict; // @[core.scala:188:23, :706:23, :707:23] wire _dis_hazards_T_15 = _dis_hazards_T_14 \| io_ifu_redirect_flush_0; // @[core.scala:51:7, :707:23, :708:23] wire dis_hazards_0 = dis_valids_0 & _dis_hazards_T_15; // @[core.scala:166:24, :696:37, :708:23] wire dis_stalls_0 = dis_hazards_0; // @[core.scala:696:37, :713:62] wire _dis_hazards_T_16 = ~_rob_io_ready; // @[core.scala:143:32, :697:26] wire _dis_hazards_T_17 = _dis_hazards_T_16 \| ren_stalls_1; // @[core.scala:163:24, :697:26, :698:23] wire _dis_hazards_T_18 = io_lsu_ldq_full_1_0 & dis_uops_1_uses_ldq; // @[core.scala:51:7, :167:24, :699:45] wire _dis_hazards_T_19 = _dis_hazards_T_17 \| _dis_hazards_T_18; // @[core.scala:698:23, :699:{23,45}] wire _dis_hazards_T_20 = io_lsu_stq_full_1_0 & dis_uops_1_uses_stq; // @[core.scala:51:7, :167:24, :700:45] wire _dis_hazards_T_21 = _dis_hazards_T_19 \| _dis_hazards_T_20; // @[core.scala:699:23, :700:{23,45}] wire _dis_hazards_T_22 = ~_dispatcher_io_ren_uops_1_ready; // @[core.scala:114:32, :701:26] wire _dis_hazards_T_23 = _dis_hazards_T_21 \| _dis_hazards_T_22; // @[core.scala:700:23, :701:{23,26}] wire _dis_hazards_T_24 = _dis_hazards_T_23 \| wait_for_empty_pipeline_1; // @[core.scala:685:112, :701:23, :702:23] wire _dis_hazards_T_25 = _dis_hazards_T_24; // @[core.scala:702:23, :703:23] wire _dis_hazards_T_26 = _dis_hazards_T_25 \| dis_prior_slot_unique_1; // @[core.scala:684:96, :703:23, :704:23] wire _dis_hazards_T_27 = _dis_hazards_T_26; // @[core.scala:704:23, :705:23] wire _dis_hazards_T_28 = \|brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :706:54] wire _dis_hazards_T_29 = _dis_hazards_T_27 \| _dis_hazards_T_28; // @[core.scala:705:23, :706:{23,54}] wire _dis_hazards_T_30 = _dis_hazards_T_29 \| brupdate_b2_mispredict; // @[core.scala:188:23, :706:23, :707:23] wire _dis_hazards_T_31 = _dis_hazards_T_30 \| io_ifu_redirect_flush_0; // @[core.scala:51:7, :707:23, :708:23] wire dis_hazards_1 = dis_valids_1 & _dis_hazards_T_31; // @[core.scala:166:24, :696:37, :708:23] wire _dis_hazards_T_32 = ~_rob_io_ready; // @[core.scala:143:32, :697:26] wire _dis_hazards_T_33 = _dis_hazards_T_32 \| ren_stalls_2; // @[core.scala:163:24, :697:26, :698:23] wire _dis_hazards_T_34 = io_lsu_ldq_full_2_0 & dis_uops_2_uses_ldq; // @[core.scala:51:7, :167:24, :699:45] wire _dis_hazards_T_35 = _dis_hazards_T_33 \| _dis_hazards_T_34; // @[core.scala:698:23, :699:{23,45}] wire _dis_hazards_T_36 = io_lsu_stq_full_2_0 & dis_uops_2_uses_stq; // @[core.scala:51:7, :167:24, :700:45] wire _dis_hazards_T_37 = _dis_hazards_T_35 \| _dis_hazards_T_36; // @[core.scala:699:23, :700:{23,45}] wire _dis_hazards_T_38 = ~_dispatcher_io_ren_uops_2_ready; // @[core.scala:114:32, :701:26] wire _dis_hazards_T_39 = _dis_hazards_T_37 \| _dis_hazards_T_38; // @[core.scala:700:23, :701:{23,26}] wire _dis_hazards_T_40 = _dis_hazards_T_39 \| wait_for_empty_pipeline_2; // @[core.scala:685:112, :701:23, :702:23] wire _dis_hazards_T_41 = _dis_hazards_T_40; // @[core.scala:702:23, :703:23] wire _dis_hazards_T_42 = _dis_hazards_T_41 \| dis_prior_slot_unique_2; // @[core.scala:684:96, :703:23, :704:23] wire _dis_hazards_T_43 = _dis_hazards_T_42; // @[core.scala:704:23, :705:23] wire _dis_hazards_T_44 = \|brupdate_b1_mispredict_mask; // @[core.scala:188:23, :224:42, :706:54] wire _dis_hazards_T_45 = _dis_hazards_T_43 \| _dis_hazards_T_44; // @[core.scala:705:23, :706:{23,54}] wire _dis_hazards_T_46 = _dis_hazards_T_45 \| brupdate_b2_mispredict; // @[core.scala:188:23, :706:23, :707:23] wire _dis_hazards_T_47 = _dis_hazards_T_46 \| io_ifu_redirect_flush_0; // @[core.scala:51:7, :707:23, :708:23] wire dis_hazards_2 = dis_valids_2 & _dis_hazards_T_47; // @[core.scala:166:24, :696:37, :708:23] wire _io_lsu_fence_dmem_T = dis_valids_0 & wait_for_empty_pipeline_0; // @[core.scala:166:24, :685:112, :711:86] wire _io_lsu_fence_dmem_T_1 = dis_valids_1 & wait_for_empty_pipeline_1; // @[core.scala:166:24, :685:112, :711:86] wire _io_lsu_fence_dmem_T_2 = dis_valids_2 & wait_for_empty_pipeline_2; // @[core.scala:166:24, :685:112, :711:86] wire _io_lsu_fence_dmem_T_3 = _io_lsu_fence_dmem_T \| _io_lsu_fence_dmem_T_1; // @[core.scala:711:{86,101}] assign _io_lsu_fence_dmem_T_4 = _io_lsu_fence_dmem_T_3 \| _io_lsu_fence_dmem_T_2; // @[core.scala:711:{86,101}] assign io_lsu_fence_dmem_0 = _io_lsu_fence_dmem_T_4; // @[core.scala:51:7, :711:101] wire dis_stalls_1 = dis_stalls_0 \| dis_hazards_1; // @[core.scala:696:37, :713:62] wire dis_stalls_2 = dis_stalls_1 \| dis_hazards_2; // @[core.scala:696:37, :713:62] assign dis_fire_0 = dis_valids_0 & ~dis_stalls_0; // @[core.scala:166:24, :168:24, :713:62, :714:{62,65}] assign dis_fire_1 = dis_valids_1 & ~dis_stalls_1; // @[core.scala:166:24, :168:24, :713:62, :714:{62,65}] assign dis_fire_2 = dis_valids_2 & ~dis_stalls_2; // @[core.scala:166:24, :168:24, :713:62, :714:{62,65}] assign _dis_ready_T = ~dis_stalls_2; // @[core.scala:713:62, :714:65, :715:16] assign dis_ready = _dis_ready_T; // @[core.scala:169:24, :715:16] reg REG_3; // @[core.scala:738:16] assign io_ifu_commit_valid_0 = REG_3 \| _io_ifu_commit_valid_T_2; // @[core.scala:51:7, :466:{23,59}, :738:{16,94}, :739:25] wire [1:0] _io_ifu_commit_bits_T_1 = dis_valids_1 ? 2'h1 : 2'h2; // @[Mux.scala:50:70] wire [1:0] _io_ifu_commit_bits_T_2 = dis_valids_0 ? 2'h0 : _io_ifu_commit_bits_T_1; // @[Mux.scala:50:70] reg [4:0] io_ifu_commit_bits_REG; // @[core.scala:740:35] assign io_ifu_commit_bits_0 = {27'h0, REG_3 ? io_ifu_commit_bits_REG : _io_ifu_commit_bits_T}; // @[core.scala:51:7, :467:{23,29}, :738:{16,94}, :740:{25,35}] wire [6:0] _GEN_37 = {2'h0, _rob_io_rob_tail_idx[6:2]}; // @[core.scala:143:32, :749:54] wire [6:0] _dis_uops_0_rob_idx_T; // @[core.scala:749:54] assign _dis_uops_0_rob_idx_T = _GEN_37; // @[core.scala:749:54] wire [6:0] _dis_uops_1_rob_idx_T; // @[core.scala:749:54] assign _dis_uops_1_rob_idx_T = _GEN_37; // @[core.scala:749:54] wire [6:0] _dis_uops_2_rob_idx_T; // @[core.scala:749:54] assign _dis_uops_2_rob_idx_T = _GEN_37; // @[core.scala:749:54] wire [8:0] _dis_uops_0_rob_idx_T_1 = {_dis_uops_0_rob_idx_T, 2'h0}; // @[core.scala:749:{33,54}] assign dis_uops_0_rob_idx = _dis_uops_0_rob_idx_T_1[6:0]; // @[core.scala:167:24, :749:{27,33}] wire [8:0] _dis_uops_1_rob_idx_T_1 = {_dis_uops_1_rob_idx_T, 2'h1}; // @[core.scala:749:{33,54}] assign dis_uops_1_rob_idx = _dis_uops_1_rob_idx_T_1[6:0]; // @[core.scala:167:24, :749:{27,33}] wire [8:0] _dis_uops_2_rob_idx_T_1 = {_dis_uops_2_rob_idx_T, 2'h2}; // @[core.scala:749:{33,54}] assign dis_uops_2_rob_idx = _dis_uops_2_rob_idx_T_1[6:0]; // @[core.scala:167:24, :749:{27,33}] wire _GEN_38 = _ll_wbarb_io_out_bits_uop_dst_rtype == 2'h0; // @[core.scala:132:32, :795:90] wire _int_iss_wakeups_0_valid_T_1; // @[core.scala:795:90] assign _int_iss_wakeups_0_valid_T_1 = _GEN_38; // @[core.scala:795:90] wire _int_ren_wakeups_0_valid_T_1; // @[core.scala:798:90] assign _int_ren_wakeups_0_valid_T_1 = _GEN_38; // @[core.scala:795:90, :798:90] wire _iregfile_io_write_ports_0_wport_valid_T; // @[regfile.scala:57:61] assign _iregfile_io_write_ports_0_wport_valid_T = _GEN_38; // @[regfile.scala:57:61] wire _int_iss_wakeups_0_valid_T; // @[Decoupled.scala:51:35] assign _int_iss_wakeups_0_valid_T_2 = _int_iss_wakeups_0_valid_T & _int_iss_wakeups_0_valid_T_1; // @[Decoupled.scala:51:35] assign int_iss_wakeups_0_valid = _int_iss_wakeups_0_valid_T_2; // @[core.scala:147:30, :795:52] wire _int_ren_wakeups_0_valid_T; // @[Decoupled.scala:51:35] assign _int_ren_wakeups_0_valid_T_2 = _int_ren_wakeups_0_valid_T & _int_ren_wakeups_0_valid_T_1; // @[Decoupled.scala:51:35] assign int_ren_wakeups_0_valid = _int_ren_wakeups_0_valid_T_2; // @[core.scala:148:30, :798:52] wire _fast_wakeup_valid_T_7; // @[core.scala:827:52] assign int_iss_wakeups_1_valid = fast_wakeup_valid; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_valid = fast_wakeup_valid; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_uopc = fast_wakeup_bits_uop_uopc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_uopc = fast_wakeup_bits_uop_uopc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_inst = fast_wakeup_bits_uop_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_inst = fast_wakeup_bits_uop_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_debug_inst = fast_wakeup_bits_uop_debug_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_debug_inst = fast_wakeup_bits_uop_debug_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_rvc = fast_wakeup_bits_uop_is_rvc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_rvc = fast_wakeup_bits_uop_is_rvc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_debug_pc = fast_wakeup_bits_uop_debug_pc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_debug_pc = fast_wakeup_bits_uop_debug_pc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_iq_type = fast_wakeup_bits_uop_iq_type; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_iq_type = fast_wakeup_bits_uop_iq_type; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_fu_code = fast_wakeup_bits_uop_fu_code; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_fu_code = fast_wakeup_bits_uop_fu_code; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_br_type = fast_wakeup_bits_uop_ctrl_br_type; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_br_type = fast_wakeup_bits_uop_ctrl_br_type; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_op1_sel = fast_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_op1_sel = fast_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_op2_sel = fast_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_op2_sel = fast_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_imm_sel = fast_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_imm_sel = fast_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_op_fcn = fast_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_op_fcn = fast_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_fcn_dw = fast_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_fcn_dw = fast_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_csr_cmd = fast_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_csr_cmd = fast_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_is_load = fast_wakeup_bits_uop_ctrl_is_load; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_is_load = fast_wakeup_bits_uop_ctrl_is_load; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_is_sta = fast_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_is_sta = fast_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ctrl_is_std = fast_wakeup_bits_uop_ctrl_is_std; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ctrl_is_std = fast_wakeup_bits_uop_ctrl_is_std; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_iw_state = fast_wakeup_bits_uop_iw_state; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_iw_state = fast_wakeup_bits_uop_iw_state; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_iw_p1_poisoned = fast_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_iw_p1_poisoned = fast_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_iw_p2_poisoned = fast_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_iw_p2_poisoned = fast_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_br = fast_wakeup_bits_uop_is_br; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_br = fast_wakeup_bits_uop_is_br; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_jalr = fast_wakeup_bits_uop_is_jalr; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_jalr = fast_wakeup_bits_uop_is_jalr; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_jal = fast_wakeup_bits_uop_is_jal; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_jal = fast_wakeup_bits_uop_is_jal; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_sfb = fast_wakeup_bits_uop_is_sfb; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_sfb = fast_wakeup_bits_uop_is_sfb; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_br_mask = fast_wakeup_bits_uop_br_mask; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_br_mask = fast_wakeup_bits_uop_br_mask; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_br_tag = fast_wakeup_bits_uop_br_tag; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_br_tag = fast_wakeup_bits_uop_br_tag; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ftq_idx = fast_wakeup_bits_uop_ftq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ftq_idx = fast_wakeup_bits_uop_ftq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_edge_inst = fast_wakeup_bits_uop_edge_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_edge_inst = fast_wakeup_bits_uop_edge_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_pc_lob = fast_wakeup_bits_uop_pc_lob; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_pc_lob = fast_wakeup_bits_uop_pc_lob; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_taken = fast_wakeup_bits_uop_taken; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_taken = fast_wakeup_bits_uop_taken; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_imm_packed = fast_wakeup_bits_uop_imm_packed; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_imm_packed = fast_wakeup_bits_uop_imm_packed; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_csr_addr = fast_wakeup_bits_uop_csr_addr; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_csr_addr = fast_wakeup_bits_uop_csr_addr; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_rob_idx = fast_wakeup_bits_uop_rob_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_rob_idx = fast_wakeup_bits_uop_rob_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ldq_idx = fast_wakeup_bits_uop_ldq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ldq_idx = fast_wakeup_bits_uop_ldq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_stq_idx = fast_wakeup_bits_uop_stq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_stq_idx = fast_wakeup_bits_uop_stq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_rxq_idx = fast_wakeup_bits_uop_rxq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_rxq_idx = fast_wakeup_bits_uop_rxq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_pdst = fast_wakeup_bits_uop_pdst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_pdst = fast_wakeup_bits_uop_pdst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_prs1 = fast_wakeup_bits_uop_prs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_prs1 = fast_wakeup_bits_uop_prs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_prs2 = fast_wakeup_bits_uop_prs2; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_prs2 = fast_wakeup_bits_uop_prs2; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_prs3 = fast_wakeup_bits_uop_prs3; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_prs3 = fast_wakeup_bits_uop_prs3; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ppred = fast_wakeup_bits_uop_ppred; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ppred = fast_wakeup_bits_uop_ppred; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_prs1_busy = fast_wakeup_bits_uop_prs1_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_prs1_busy = fast_wakeup_bits_uop_prs1_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_prs2_busy = fast_wakeup_bits_uop_prs2_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_prs2_busy = fast_wakeup_bits_uop_prs2_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_prs3_busy = fast_wakeup_bits_uop_prs3_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_prs3_busy = fast_wakeup_bits_uop_prs3_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ppred_busy = fast_wakeup_bits_uop_ppred_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ppred_busy = fast_wakeup_bits_uop_ppred_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_stale_pdst = fast_wakeup_bits_uop_stale_pdst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_stale_pdst = fast_wakeup_bits_uop_stale_pdst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_exception = fast_wakeup_bits_uop_exception; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_exception = fast_wakeup_bits_uop_exception; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_exc_cause = fast_wakeup_bits_uop_exc_cause; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_exc_cause = fast_wakeup_bits_uop_exc_cause; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_bypassable = fast_wakeup_bits_uop_bypassable; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_bypassable = fast_wakeup_bits_uop_bypassable; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_mem_cmd = fast_wakeup_bits_uop_mem_cmd; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_mem_cmd = fast_wakeup_bits_uop_mem_cmd; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_mem_size = fast_wakeup_bits_uop_mem_size; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_mem_size = fast_wakeup_bits_uop_mem_size; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_mem_signed = fast_wakeup_bits_uop_mem_signed; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_mem_signed = fast_wakeup_bits_uop_mem_signed; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_fence = fast_wakeup_bits_uop_is_fence; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_fence = fast_wakeup_bits_uop_is_fence; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_fencei = fast_wakeup_bits_uop_is_fencei; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_fencei = fast_wakeup_bits_uop_is_fencei; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_amo = fast_wakeup_bits_uop_is_amo; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_amo = fast_wakeup_bits_uop_is_amo; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_uses_ldq = fast_wakeup_bits_uop_uses_ldq; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_uses_ldq = fast_wakeup_bits_uop_uses_ldq; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_uses_stq = fast_wakeup_bits_uop_uses_stq; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_uses_stq = fast_wakeup_bits_uop_uses_stq; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_sys_pc2epc = fast_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_sys_pc2epc = fast_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_is_unique = fast_wakeup_bits_uop_is_unique; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_is_unique = fast_wakeup_bits_uop_is_unique; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_flush_on_commit = fast_wakeup_bits_uop_flush_on_commit; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_flush_on_commit = fast_wakeup_bits_uop_flush_on_commit; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ldst_is_rs1 = fast_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ldst_is_rs1 = fast_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ldst = fast_wakeup_bits_uop_ldst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ldst = fast_wakeup_bits_uop_ldst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_lrs1 = fast_wakeup_bits_uop_lrs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_lrs1 = fast_wakeup_bits_uop_lrs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_lrs2 = fast_wakeup_bits_uop_lrs2; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_lrs2 = fast_wakeup_bits_uop_lrs2; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_lrs3 = fast_wakeup_bits_uop_lrs3; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_lrs3 = fast_wakeup_bits_uop_lrs3; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_ldst_val = fast_wakeup_bits_uop_ldst_val; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_ldst_val = fast_wakeup_bits_uop_ldst_val; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_dst_rtype = fast_wakeup_bits_uop_dst_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_dst_rtype = fast_wakeup_bits_uop_dst_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_lrs1_rtype = fast_wakeup_bits_uop_lrs1_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_lrs1_rtype = fast_wakeup_bits_uop_lrs1_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_lrs2_rtype = fast_wakeup_bits_uop_lrs2_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_lrs2_rtype = fast_wakeup_bits_uop_lrs2_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_frs3_en = fast_wakeup_bits_uop_frs3_en; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_frs3_en = fast_wakeup_bits_uop_frs3_en; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_fp_val = fast_wakeup_bits_uop_fp_val; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_fp_val = fast_wakeup_bits_uop_fp_val; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_fp_single = fast_wakeup_bits_uop_fp_single; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_fp_single = fast_wakeup_bits_uop_fp_single; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_xcpt_pf_if = fast_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_xcpt_pf_if = fast_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_xcpt_ae_if = fast_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_xcpt_ae_if = fast_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_xcpt_ma_if = fast_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_xcpt_ma_if = fast_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_bp_debug_if = fast_wakeup_bits_uop_bp_debug_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_bp_debug_if = fast_wakeup_bits_uop_bp_debug_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_bp_xcpt_if = fast_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_bp_xcpt_if = fast_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_debug_fsrc = fast_wakeup_bits_uop_debug_fsrc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_debug_fsrc = fast_wakeup_bits_uop_debug_fsrc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_1_bits_uop_debug_tsrc = fast_wakeup_bits_uop_debug_tsrc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_1_bits_uop_debug_tsrc = fast_wakeup_bits_uop_debug_tsrc; // @[core.scala:148:30, :814:29] wire _slow_wakeup_valid_T_5; // @[core.scala:834:59] assign int_iss_wakeups_2_valid = slow_wakeup_valid; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_valid = slow_wakeup_valid; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_uopc = slow_wakeup_bits_uop_uopc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_uopc = slow_wakeup_bits_uop_uopc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_inst = slow_wakeup_bits_uop_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_inst = slow_wakeup_bits_uop_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_debug_inst = slow_wakeup_bits_uop_debug_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_debug_inst = slow_wakeup_bits_uop_debug_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_rvc = slow_wakeup_bits_uop_is_rvc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_rvc = slow_wakeup_bits_uop_is_rvc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_debug_pc = slow_wakeup_bits_uop_debug_pc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_debug_pc = slow_wakeup_bits_uop_debug_pc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_iq_type = slow_wakeup_bits_uop_iq_type; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_iq_type = slow_wakeup_bits_uop_iq_type; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_fu_code = slow_wakeup_bits_uop_fu_code; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_fu_code = slow_wakeup_bits_uop_fu_code; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_br_type = slow_wakeup_bits_uop_ctrl_br_type; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_br_type = slow_wakeup_bits_uop_ctrl_br_type; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_op1_sel = slow_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_op1_sel = slow_wakeup_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_op2_sel = slow_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_op2_sel = slow_wakeup_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_imm_sel = slow_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_imm_sel = slow_wakeup_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_op_fcn = slow_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_op_fcn = slow_wakeup_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_fcn_dw = slow_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_fcn_dw = slow_wakeup_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_csr_cmd = slow_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_csr_cmd = slow_wakeup_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_is_load = slow_wakeup_bits_uop_ctrl_is_load; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_is_load = slow_wakeup_bits_uop_ctrl_is_load; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_is_sta = slow_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_is_sta = slow_wakeup_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ctrl_is_std = slow_wakeup_bits_uop_ctrl_is_std; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ctrl_is_std = slow_wakeup_bits_uop_ctrl_is_std; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_iw_state = slow_wakeup_bits_uop_iw_state; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_iw_state = slow_wakeup_bits_uop_iw_state; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_iw_p1_poisoned = slow_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_iw_p1_poisoned = slow_wakeup_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_iw_p2_poisoned = slow_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_iw_p2_poisoned = slow_wakeup_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_br = slow_wakeup_bits_uop_is_br; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_br = slow_wakeup_bits_uop_is_br; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_jalr = slow_wakeup_bits_uop_is_jalr; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_jalr = slow_wakeup_bits_uop_is_jalr; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_jal = slow_wakeup_bits_uop_is_jal; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_jal = slow_wakeup_bits_uop_is_jal; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_sfb = slow_wakeup_bits_uop_is_sfb; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_sfb = slow_wakeup_bits_uop_is_sfb; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_br_mask = slow_wakeup_bits_uop_br_mask; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_br_mask = slow_wakeup_bits_uop_br_mask; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_br_tag = slow_wakeup_bits_uop_br_tag; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_br_tag = slow_wakeup_bits_uop_br_tag; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ftq_idx = slow_wakeup_bits_uop_ftq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ftq_idx = slow_wakeup_bits_uop_ftq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_edge_inst = slow_wakeup_bits_uop_edge_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_edge_inst = slow_wakeup_bits_uop_edge_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_pc_lob = slow_wakeup_bits_uop_pc_lob; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_pc_lob = slow_wakeup_bits_uop_pc_lob; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_taken = slow_wakeup_bits_uop_taken; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_taken = slow_wakeup_bits_uop_taken; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_imm_packed = slow_wakeup_bits_uop_imm_packed; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_imm_packed = slow_wakeup_bits_uop_imm_packed; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_csr_addr = slow_wakeup_bits_uop_csr_addr; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_csr_addr = slow_wakeup_bits_uop_csr_addr; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_rob_idx = slow_wakeup_bits_uop_rob_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_rob_idx = slow_wakeup_bits_uop_rob_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ldq_idx = slow_wakeup_bits_uop_ldq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ldq_idx = slow_wakeup_bits_uop_ldq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_stq_idx = slow_wakeup_bits_uop_stq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_stq_idx = slow_wakeup_bits_uop_stq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_rxq_idx = slow_wakeup_bits_uop_rxq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_rxq_idx = slow_wakeup_bits_uop_rxq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_pdst = slow_wakeup_bits_uop_pdst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_pdst = slow_wakeup_bits_uop_pdst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_prs1 = slow_wakeup_bits_uop_prs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_prs1 = slow_wakeup_bits_uop_prs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_prs2 = slow_wakeup_bits_uop_prs2; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_prs2 = slow_wakeup_bits_uop_prs2; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_prs3 = slow_wakeup_bits_uop_prs3; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_prs3 = slow_wakeup_bits_uop_prs3; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ppred = slow_wakeup_bits_uop_ppred; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ppred = slow_wakeup_bits_uop_ppred; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_prs1_busy = slow_wakeup_bits_uop_prs1_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_prs1_busy = slow_wakeup_bits_uop_prs1_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_prs2_busy = slow_wakeup_bits_uop_prs2_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_prs2_busy = slow_wakeup_bits_uop_prs2_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_prs3_busy = slow_wakeup_bits_uop_prs3_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_prs3_busy = slow_wakeup_bits_uop_prs3_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ppred_busy = slow_wakeup_bits_uop_ppred_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ppred_busy = slow_wakeup_bits_uop_ppred_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_stale_pdst = slow_wakeup_bits_uop_stale_pdst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_stale_pdst = slow_wakeup_bits_uop_stale_pdst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_exception = slow_wakeup_bits_uop_exception; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_exception = slow_wakeup_bits_uop_exception; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_exc_cause = slow_wakeup_bits_uop_exc_cause; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_exc_cause = slow_wakeup_bits_uop_exc_cause; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_bypassable = slow_wakeup_bits_uop_bypassable; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_bypassable = slow_wakeup_bits_uop_bypassable; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_mem_cmd = slow_wakeup_bits_uop_mem_cmd; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_mem_cmd = slow_wakeup_bits_uop_mem_cmd; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_mem_size = slow_wakeup_bits_uop_mem_size; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_mem_size = slow_wakeup_bits_uop_mem_size; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_mem_signed = slow_wakeup_bits_uop_mem_signed; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_mem_signed = slow_wakeup_bits_uop_mem_signed; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_fence = slow_wakeup_bits_uop_is_fence; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_fence = slow_wakeup_bits_uop_is_fence; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_fencei = slow_wakeup_bits_uop_is_fencei; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_fencei = slow_wakeup_bits_uop_is_fencei; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_amo = slow_wakeup_bits_uop_is_amo; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_amo = slow_wakeup_bits_uop_is_amo; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_uses_ldq = slow_wakeup_bits_uop_uses_ldq; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_uses_ldq = slow_wakeup_bits_uop_uses_ldq; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_uses_stq = slow_wakeup_bits_uop_uses_stq; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_uses_stq = slow_wakeup_bits_uop_uses_stq; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_sys_pc2epc = slow_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_sys_pc2epc = slow_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_is_unique = slow_wakeup_bits_uop_is_unique; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_is_unique = slow_wakeup_bits_uop_is_unique; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_flush_on_commit = slow_wakeup_bits_uop_flush_on_commit; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_flush_on_commit = slow_wakeup_bits_uop_flush_on_commit; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ldst_is_rs1 = slow_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ldst_is_rs1 = slow_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ldst = slow_wakeup_bits_uop_ldst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ldst = slow_wakeup_bits_uop_ldst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_lrs1 = slow_wakeup_bits_uop_lrs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_lrs1 = slow_wakeup_bits_uop_lrs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_lrs2 = slow_wakeup_bits_uop_lrs2; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_lrs2 = slow_wakeup_bits_uop_lrs2; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_lrs3 = slow_wakeup_bits_uop_lrs3; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_lrs3 = slow_wakeup_bits_uop_lrs3; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_ldst_val = slow_wakeup_bits_uop_ldst_val; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_ldst_val = slow_wakeup_bits_uop_ldst_val; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_dst_rtype = slow_wakeup_bits_uop_dst_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_dst_rtype = slow_wakeup_bits_uop_dst_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_lrs1_rtype = slow_wakeup_bits_uop_lrs1_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_lrs1_rtype = slow_wakeup_bits_uop_lrs1_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_lrs2_rtype = slow_wakeup_bits_uop_lrs2_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_lrs2_rtype = slow_wakeup_bits_uop_lrs2_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_frs3_en = slow_wakeup_bits_uop_frs3_en; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_frs3_en = slow_wakeup_bits_uop_frs3_en; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_fp_val = slow_wakeup_bits_uop_fp_val; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_fp_val = slow_wakeup_bits_uop_fp_val; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_fp_single = slow_wakeup_bits_uop_fp_single; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_fp_single = slow_wakeup_bits_uop_fp_single; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_xcpt_pf_if = slow_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_xcpt_pf_if = slow_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_xcpt_ae_if = slow_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_xcpt_ae_if = slow_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_xcpt_ma_if = slow_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_xcpt_ma_if = slow_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_bp_debug_if = slow_wakeup_bits_uop_bp_debug_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_bp_debug_if = slow_wakeup_bits_uop_bp_debug_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_bp_xcpt_if = slow_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_bp_xcpt_if = slow_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_debug_fsrc = slow_wakeup_bits_uop_debug_fsrc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_debug_fsrc = slow_wakeup_bits_uop_debug_fsrc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_2_bits_uop_debug_tsrc = slow_wakeup_bits_uop_debug_tsrc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_2_bits_uop_debug_tsrc = slow_wakeup_bits_uop_debug_tsrc; // @[core.scala:148:30, :815:29] wire _T_99 = _alu_exe_unit_io_iresp_bits_uop_dst_rtype != 2'h2; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T; // @[micro-op.scala:149:36] assign _slow_wakeup_valid_T = _T_99; // @[micro-op.scala:149:36] wire _iregfile_io_write_ports_1_valid_T; // @[micro-op.scala:149:36] assign _iregfile_io_write_ports_1_valid_T = _T_99; // @[micro-op.scala:149:36] wire _rob_io_debug_wb_valids_1_T; // @[micro-op.scala:149:36] assign _rob_io_debug_wb_valids_1_T = _T_99; // @[micro-op.scala:149:36] wire _fast_wakeup_valid_T = iss_valids_1 & iss_uops_1_bypassable; // @[core.scala:172:24, :173:24, :824:45] wire _fast_wakeup_valid_T_1 = iss_uops_1_dst_rtype == 2'h0; // @[core.scala:173:24, :826:53] wire _fast_wakeup_valid_T_2 = _fast_wakeup_valid_T & _fast_wakeup_valid_T_1; // @[core.scala:824:45, :825:54, :826:53] wire _fast_wakeup_valid_T_3 = _fast_wakeup_valid_T_2 & iss_uops_1_ldst_val; // @[core.scala:173:24, :825:54, :826:64] wire _GEN_39 = iss_uops_1_iw_p1_poisoned \| iss_uops_1_iw_p2_poisoned; // @[core.scala:173:24, :828:79] wire _fast_wakeup_valid_T_4; // @[core.scala:828:79] assign _fast_wakeup_valid_T_4 = _GEN_39; // @[core.scala:828:79] wire _pred_wakeup_valid_T_3; // @[core.scala:864:84] assign _pred_wakeup_valid_T_3 = _GEN_39; // @[core.scala:828:79, :864:84] wire _iregister_read_io_iss_valids_1_T; // @[core.scala:981:72] assign _iregister_read_io_iss_valids_1_T = _GEN_39; // @[core.scala:828:79, :981:72] wire _fast_wakeup_valid_T_5 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_4; // @[core.scala:51:7, :828:{48,79}] wire _fast_wakeup_valid_T_6 = ~_fast_wakeup_valid_T_5; // @[core.scala:828:{31,48}] assign _fast_wakeup_valid_T_7 = _fast_wakeup_valid_T_3 & _fast_wakeup_valid_T_6; // @[core.scala:826:64, :827:52, :828:31] assign fast_wakeup_valid = _fast_wakeup_valid_T_7; // @[core.scala:814:29, :827:52] wire _slow_wakeup_valid_T_1 = _alu_exe_unit_io_iresp_valid & _slow_wakeup_valid_T; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_2 = ~_alu_exe_unit_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_3 = _slow_wakeup_valid_T_1 & _slow_wakeup_valid_T_2; // @[core.scala:832:42, :833:54, :834:33] wire _T_93 = _alu_exe_unit_io_iresp_bits_uop_dst_rtype == 2'h0; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_4; // @[core.scala:835:57] assign _slow_wakeup_valid_T_4 = _T_93; // @[core.scala:835:57] wire _iregfile_io_write_ports_1_valid_T_2; // @[core.scala:1160:77] assign _iregfile_io_write_ports_1_valid_T_2 = _T_93; // @[core.scala:835:57, :1160:77] wire _rob_io_debug_wb_valids_1_T_2; // @[core.scala:1240:86] assign _rob_io_debug_wb_valids_1_T_2 = _T_93; // @[core.scala:835:57, :1240:86] assign _slow_wakeup_valid_T_5 = _slow_wakeup_valid_T_3 & _slow_wakeup_valid_T_4; // @[core.scala:833:54, :834:59, :835:57] assign slow_wakeup_valid = _slow_wakeup_valid_T_5; // @[core.scala:815:29, :834:59] wire _fast_wakeup_valid_T_15; // @[core.scala:827:52] assign int_iss_wakeups_3_valid = fast_wakeup_1_valid; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_valid = fast_wakeup_1_valid; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_uopc = fast_wakeup_1_bits_uop_uopc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_uopc = fast_wakeup_1_bits_uop_uopc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_inst = fast_wakeup_1_bits_uop_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_inst = fast_wakeup_1_bits_uop_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_debug_inst = fast_wakeup_1_bits_uop_debug_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_debug_inst = fast_wakeup_1_bits_uop_debug_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_rvc = fast_wakeup_1_bits_uop_is_rvc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_rvc = fast_wakeup_1_bits_uop_is_rvc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_debug_pc = fast_wakeup_1_bits_uop_debug_pc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_debug_pc = fast_wakeup_1_bits_uop_debug_pc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_iq_type = fast_wakeup_1_bits_uop_iq_type; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_iq_type = fast_wakeup_1_bits_uop_iq_type; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_fu_code = fast_wakeup_1_bits_uop_fu_code; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_fu_code = fast_wakeup_1_bits_uop_fu_code; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_br_type = fast_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_br_type = fast_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_op1_sel = fast_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_op1_sel = fast_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_op2_sel = fast_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_op2_sel = fast_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_imm_sel = fast_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_imm_sel = fast_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_op_fcn = fast_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_op_fcn = fast_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_fcn_dw = fast_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_fcn_dw = fast_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_csr_cmd = fast_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_csr_cmd = fast_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_is_load = fast_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_is_load = fast_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_is_sta = fast_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_is_sta = fast_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ctrl_is_std = fast_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ctrl_is_std = fast_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_iw_state = fast_wakeup_1_bits_uop_iw_state; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_iw_state = fast_wakeup_1_bits_uop_iw_state; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_iw_p1_poisoned = fast_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_iw_p1_poisoned = fast_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_iw_p2_poisoned = fast_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_iw_p2_poisoned = fast_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_br = fast_wakeup_1_bits_uop_is_br; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_br = fast_wakeup_1_bits_uop_is_br; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_jalr = fast_wakeup_1_bits_uop_is_jalr; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_jalr = fast_wakeup_1_bits_uop_is_jalr; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_jal = fast_wakeup_1_bits_uop_is_jal; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_jal = fast_wakeup_1_bits_uop_is_jal; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_sfb = fast_wakeup_1_bits_uop_is_sfb; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_sfb = fast_wakeup_1_bits_uop_is_sfb; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_br_mask = fast_wakeup_1_bits_uop_br_mask; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_br_mask = fast_wakeup_1_bits_uop_br_mask; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_br_tag = fast_wakeup_1_bits_uop_br_tag; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_br_tag = fast_wakeup_1_bits_uop_br_tag; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ftq_idx = fast_wakeup_1_bits_uop_ftq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ftq_idx = fast_wakeup_1_bits_uop_ftq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_edge_inst = fast_wakeup_1_bits_uop_edge_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_edge_inst = fast_wakeup_1_bits_uop_edge_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_pc_lob = fast_wakeup_1_bits_uop_pc_lob; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_pc_lob = fast_wakeup_1_bits_uop_pc_lob; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_taken = fast_wakeup_1_bits_uop_taken; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_taken = fast_wakeup_1_bits_uop_taken; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_imm_packed = fast_wakeup_1_bits_uop_imm_packed; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_imm_packed = fast_wakeup_1_bits_uop_imm_packed; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_csr_addr = fast_wakeup_1_bits_uop_csr_addr; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_csr_addr = fast_wakeup_1_bits_uop_csr_addr; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_rob_idx = fast_wakeup_1_bits_uop_rob_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_rob_idx = fast_wakeup_1_bits_uop_rob_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ldq_idx = fast_wakeup_1_bits_uop_ldq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ldq_idx = fast_wakeup_1_bits_uop_ldq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_stq_idx = fast_wakeup_1_bits_uop_stq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_stq_idx = fast_wakeup_1_bits_uop_stq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_rxq_idx = fast_wakeup_1_bits_uop_rxq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_rxq_idx = fast_wakeup_1_bits_uop_rxq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_pdst = fast_wakeup_1_bits_uop_pdst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_pdst = fast_wakeup_1_bits_uop_pdst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_prs1 = fast_wakeup_1_bits_uop_prs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_prs1 = fast_wakeup_1_bits_uop_prs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_prs2 = fast_wakeup_1_bits_uop_prs2; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_prs2 = fast_wakeup_1_bits_uop_prs2; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_prs3 = fast_wakeup_1_bits_uop_prs3; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_prs3 = fast_wakeup_1_bits_uop_prs3; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ppred = fast_wakeup_1_bits_uop_ppred; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ppred = fast_wakeup_1_bits_uop_ppred; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_prs1_busy = fast_wakeup_1_bits_uop_prs1_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_prs1_busy = fast_wakeup_1_bits_uop_prs1_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_prs2_busy = fast_wakeup_1_bits_uop_prs2_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_prs2_busy = fast_wakeup_1_bits_uop_prs2_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_prs3_busy = fast_wakeup_1_bits_uop_prs3_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_prs3_busy = fast_wakeup_1_bits_uop_prs3_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ppred_busy = fast_wakeup_1_bits_uop_ppred_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ppred_busy = fast_wakeup_1_bits_uop_ppred_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_stale_pdst = fast_wakeup_1_bits_uop_stale_pdst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_stale_pdst = fast_wakeup_1_bits_uop_stale_pdst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_exception = fast_wakeup_1_bits_uop_exception; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_exception = fast_wakeup_1_bits_uop_exception; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_exc_cause = fast_wakeup_1_bits_uop_exc_cause; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_exc_cause = fast_wakeup_1_bits_uop_exc_cause; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_bypassable = fast_wakeup_1_bits_uop_bypassable; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_bypassable = fast_wakeup_1_bits_uop_bypassable; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_mem_cmd = fast_wakeup_1_bits_uop_mem_cmd; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_mem_cmd = fast_wakeup_1_bits_uop_mem_cmd; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_mem_size = fast_wakeup_1_bits_uop_mem_size; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_mem_size = fast_wakeup_1_bits_uop_mem_size; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_mem_signed = fast_wakeup_1_bits_uop_mem_signed; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_mem_signed = fast_wakeup_1_bits_uop_mem_signed; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_fence = fast_wakeup_1_bits_uop_is_fence; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_fence = fast_wakeup_1_bits_uop_is_fence; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_fencei = fast_wakeup_1_bits_uop_is_fencei; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_fencei = fast_wakeup_1_bits_uop_is_fencei; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_amo = fast_wakeup_1_bits_uop_is_amo; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_amo = fast_wakeup_1_bits_uop_is_amo; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_uses_ldq = fast_wakeup_1_bits_uop_uses_ldq; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_uses_ldq = fast_wakeup_1_bits_uop_uses_ldq; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_uses_stq = fast_wakeup_1_bits_uop_uses_stq; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_uses_stq = fast_wakeup_1_bits_uop_uses_stq; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_sys_pc2epc = fast_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_sys_pc2epc = fast_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_is_unique = fast_wakeup_1_bits_uop_is_unique; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_is_unique = fast_wakeup_1_bits_uop_is_unique; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_flush_on_commit = fast_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_flush_on_commit = fast_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ldst_is_rs1 = fast_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ldst_is_rs1 = fast_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ldst = fast_wakeup_1_bits_uop_ldst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ldst = fast_wakeup_1_bits_uop_ldst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_lrs1 = fast_wakeup_1_bits_uop_lrs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_lrs1 = fast_wakeup_1_bits_uop_lrs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_lrs2 = fast_wakeup_1_bits_uop_lrs2; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_lrs2 = fast_wakeup_1_bits_uop_lrs2; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_lrs3 = fast_wakeup_1_bits_uop_lrs3; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_lrs3 = fast_wakeup_1_bits_uop_lrs3; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_ldst_val = fast_wakeup_1_bits_uop_ldst_val; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_ldst_val = fast_wakeup_1_bits_uop_ldst_val; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_dst_rtype = fast_wakeup_1_bits_uop_dst_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_dst_rtype = fast_wakeup_1_bits_uop_dst_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_lrs1_rtype = fast_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_lrs1_rtype = fast_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_lrs2_rtype = fast_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_lrs2_rtype = fast_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_frs3_en = fast_wakeup_1_bits_uop_frs3_en; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_frs3_en = fast_wakeup_1_bits_uop_frs3_en; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_fp_val = fast_wakeup_1_bits_uop_fp_val; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_fp_val = fast_wakeup_1_bits_uop_fp_val; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_fp_single = fast_wakeup_1_bits_uop_fp_single; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_fp_single = fast_wakeup_1_bits_uop_fp_single; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_xcpt_pf_if = fast_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_xcpt_pf_if = fast_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_xcpt_ae_if = fast_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_xcpt_ae_if = fast_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_xcpt_ma_if = fast_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_xcpt_ma_if = fast_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_bp_debug_if = fast_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_bp_debug_if = fast_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_bp_xcpt_if = fast_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_bp_xcpt_if = fast_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_debug_fsrc = fast_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_debug_fsrc = fast_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_3_bits_uop_debug_tsrc = fast_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_3_bits_uop_debug_tsrc = fast_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:148:30, :814:29] wire _slow_wakeup_valid_T_11; // @[core.scala:834:59] assign int_iss_wakeups_4_valid = slow_wakeup_1_valid; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_valid = slow_wakeup_1_valid; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_uopc = slow_wakeup_1_bits_uop_uopc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_uopc = slow_wakeup_1_bits_uop_uopc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_inst = slow_wakeup_1_bits_uop_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_inst = slow_wakeup_1_bits_uop_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_debug_inst = slow_wakeup_1_bits_uop_debug_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_debug_inst = slow_wakeup_1_bits_uop_debug_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_rvc = slow_wakeup_1_bits_uop_is_rvc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_rvc = slow_wakeup_1_bits_uop_is_rvc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_debug_pc = slow_wakeup_1_bits_uop_debug_pc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_debug_pc = slow_wakeup_1_bits_uop_debug_pc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_iq_type = slow_wakeup_1_bits_uop_iq_type; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_iq_type = slow_wakeup_1_bits_uop_iq_type; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_fu_code = slow_wakeup_1_bits_uop_fu_code; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_fu_code = slow_wakeup_1_bits_uop_fu_code; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_br_type = slow_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_br_type = slow_wakeup_1_bits_uop_ctrl_br_type; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_op1_sel = slow_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_op1_sel = slow_wakeup_1_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_op2_sel = slow_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_op2_sel = slow_wakeup_1_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_imm_sel = slow_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_imm_sel = slow_wakeup_1_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_op_fcn = slow_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_op_fcn = slow_wakeup_1_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_fcn_dw = slow_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_fcn_dw = slow_wakeup_1_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_csr_cmd = slow_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_csr_cmd = slow_wakeup_1_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_is_load = slow_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_is_load = slow_wakeup_1_bits_uop_ctrl_is_load; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_is_sta = slow_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_is_sta = slow_wakeup_1_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ctrl_is_std = slow_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ctrl_is_std = slow_wakeup_1_bits_uop_ctrl_is_std; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_iw_state = slow_wakeup_1_bits_uop_iw_state; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_iw_state = slow_wakeup_1_bits_uop_iw_state; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_iw_p1_poisoned = slow_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_iw_p1_poisoned = slow_wakeup_1_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_iw_p2_poisoned = slow_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_iw_p2_poisoned = slow_wakeup_1_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_br = slow_wakeup_1_bits_uop_is_br; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_br = slow_wakeup_1_bits_uop_is_br; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_jalr = slow_wakeup_1_bits_uop_is_jalr; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_jalr = slow_wakeup_1_bits_uop_is_jalr; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_jal = slow_wakeup_1_bits_uop_is_jal; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_jal = slow_wakeup_1_bits_uop_is_jal; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_sfb = slow_wakeup_1_bits_uop_is_sfb; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_sfb = slow_wakeup_1_bits_uop_is_sfb; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_br_mask = slow_wakeup_1_bits_uop_br_mask; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_br_mask = slow_wakeup_1_bits_uop_br_mask; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_br_tag = slow_wakeup_1_bits_uop_br_tag; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_br_tag = slow_wakeup_1_bits_uop_br_tag; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ftq_idx = slow_wakeup_1_bits_uop_ftq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ftq_idx = slow_wakeup_1_bits_uop_ftq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_edge_inst = slow_wakeup_1_bits_uop_edge_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_edge_inst = slow_wakeup_1_bits_uop_edge_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_pc_lob = slow_wakeup_1_bits_uop_pc_lob; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_pc_lob = slow_wakeup_1_bits_uop_pc_lob; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_taken = slow_wakeup_1_bits_uop_taken; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_taken = slow_wakeup_1_bits_uop_taken; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_imm_packed = slow_wakeup_1_bits_uop_imm_packed; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_imm_packed = slow_wakeup_1_bits_uop_imm_packed; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_csr_addr = slow_wakeup_1_bits_uop_csr_addr; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_csr_addr = slow_wakeup_1_bits_uop_csr_addr; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_rob_idx = slow_wakeup_1_bits_uop_rob_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_rob_idx = slow_wakeup_1_bits_uop_rob_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ldq_idx = slow_wakeup_1_bits_uop_ldq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ldq_idx = slow_wakeup_1_bits_uop_ldq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_stq_idx = slow_wakeup_1_bits_uop_stq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_stq_idx = slow_wakeup_1_bits_uop_stq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_rxq_idx = slow_wakeup_1_bits_uop_rxq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_rxq_idx = slow_wakeup_1_bits_uop_rxq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_pdst = slow_wakeup_1_bits_uop_pdst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_pdst = slow_wakeup_1_bits_uop_pdst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_prs1 = slow_wakeup_1_bits_uop_prs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_prs1 = slow_wakeup_1_bits_uop_prs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_prs2 = slow_wakeup_1_bits_uop_prs2; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_prs2 = slow_wakeup_1_bits_uop_prs2; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_prs3 = slow_wakeup_1_bits_uop_prs3; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_prs3 = slow_wakeup_1_bits_uop_prs3; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ppred = slow_wakeup_1_bits_uop_ppred; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ppred = slow_wakeup_1_bits_uop_ppred; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_prs1_busy = slow_wakeup_1_bits_uop_prs1_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_prs1_busy = slow_wakeup_1_bits_uop_prs1_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_prs2_busy = slow_wakeup_1_bits_uop_prs2_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_prs2_busy = slow_wakeup_1_bits_uop_prs2_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_prs3_busy = slow_wakeup_1_bits_uop_prs3_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_prs3_busy = slow_wakeup_1_bits_uop_prs3_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ppred_busy = slow_wakeup_1_bits_uop_ppred_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ppred_busy = slow_wakeup_1_bits_uop_ppred_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_stale_pdst = slow_wakeup_1_bits_uop_stale_pdst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_stale_pdst = slow_wakeup_1_bits_uop_stale_pdst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_exception = slow_wakeup_1_bits_uop_exception; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_exception = slow_wakeup_1_bits_uop_exception; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_exc_cause = slow_wakeup_1_bits_uop_exc_cause; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_exc_cause = slow_wakeup_1_bits_uop_exc_cause; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_bypassable = slow_wakeup_1_bits_uop_bypassable; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_bypassable = slow_wakeup_1_bits_uop_bypassable; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_mem_cmd = slow_wakeup_1_bits_uop_mem_cmd; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_mem_cmd = slow_wakeup_1_bits_uop_mem_cmd; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_mem_size = slow_wakeup_1_bits_uop_mem_size; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_mem_size = slow_wakeup_1_bits_uop_mem_size; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_mem_signed = slow_wakeup_1_bits_uop_mem_signed; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_mem_signed = slow_wakeup_1_bits_uop_mem_signed; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_fence = slow_wakeup_1_bits_uop_is_fence; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_fence = slow_wakeup_1_bits_uop_is_fence; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_fencei = slow_wakeup_1_bits_uop_is_fencei; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_fencei = slow_wakeup_1_bits_uop_is_fencei; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_amo = slow_wakeup_1_bits_uop_is_amo; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_amo = slow_wakeup_1_bits_uop_is_amo; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_uses_ldq = slow_wakeup_1_bits_uop_uses_ldq; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_uses_ldq = slow_wakeup_1_bits_uop_uses_ldq; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_uses_stq = slow_wakeup_1_bits_uop_uses_stq; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_uses_stq = slow_wakeup_1_bits_uop_uses_stq; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_sys_pc2epc = slow_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_sys_pc2epc = slow_wakeup_1_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_is_unique = slow_wakeup_1_bits_uop_is_unique; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_is_unique = slow_wakeup_1_bits_uop_is_unique; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_flush_on_commit = slow_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_flush_on_commit = slow_wakeup_1_bits_uop_flush_on_commit; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ldst_is_rs1 = slow_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ldst_is_rs1 = slow_wakeup_1_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ldst = slow_wakeup_1_bits_uop_ldst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ldst = slow_wakeup_1_bits_uop_ldst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_lrs1 = slow_wakeup_1_bits_uop_lrs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_lrs1 = slow_wakeup_1_bits_uop_lrs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_lrs2 = slow_wakeup_1_bits_uop_lrs2; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_lrs2 = slow_wakeup_1_bits_uop_lrs2; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_lrs3 = slow_wakeup_1_bits_uop_lrs3; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_lrs3 = slow_wakeup_1_bits_uop_lrs3; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_ldst_val = slow_wakeup_1_bits_uop_ldst_val; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_ldst_val = slow_wakeup_1_bits_uop_ldst_val; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_dst_rtype = slow_wakeup_1_bits_uop_dst_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_dst_rtype = slow_wakeup_1_bits_uop_dst_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_lrs1_rtype = slow_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_lrs1_rtype = slow_wakeup_1_bits_uop_lrs1_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_lrs2_rtype = slow_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_lrs2_rtype = slow_wakeup_1_bits_uop_lrs2_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_frs3_en = slow_wakeup_1_bits_uop_frs3_en; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_frs3_en = slow_wakeup_1_bits_uop_frs3_en; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_fp_val = slow_wakeup_1_bits_uop_fp_val; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_fp_val = slow_wakeup_1_bits_uop_fp_val; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_fp_single = slow_wakeup_1_bits_uop_fp_single; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_fp_single = slow_wakeup_1_bits_uop_fp_single; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_xcpt_pf_if = slow_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_xcpt_pf_if = slow_wakeup_1_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_xcpt_ae_if = slow_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_xcpt_ae_if = slow_wakeup_1_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_xcpt_ma_if = slow_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_xcpt_ma_if = slow_wakeup_1_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_bp_debug_if = slow_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_bp_debug_if = slow_wakeup_1_bits_uop_bp_debug_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_bp_xcpt_if = slow_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_bp_xcpt_if = slow_wakeup_1_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_debug_fsrc = slow_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_debug_fsrc = slow_wakeup_1_bits_uop_debug_fsrc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_4_bits_uop_debug_tsrc = slow_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_4_bits_uop_debug_tsrc = slow_wakeup_1_bits_uop_debug_tsrc; // @[core.scala:148:30, :815:29] wire _T_124 = _alu_exe_unit_1_io_iresp_bits_uop_dst_rtype != 2'h2; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_6; // @[micro-op.scala:149:36] assign _slow_wakeup_valid_T_6 = _T_124; // @[micro-op.scala:149:36] wire _iregfile_io_write_ports_2_valid_T; // @[micro-op.scala:149:36] assign _iregfile_io_write_ports_2_valid_T = _T_124; // @[micro-op.scala:149:36] wire _rob_io_debug_wb_valids_2_T; // @[micro-op.scala:149:36] assign _rob_io_debug_wb_valids_2_T = _T_124; // @[micro-op.scala:149:36] wire _fast_wakeup_valid_T_8 = iss_valids_2 & iss_uops_2_bypassable; // @[core.scala:172:24, :173:24, :824:45] wire _fast_wakeup_valid_T_9 = iss_uops_2_dst_rtype == 2'h0; // @[core.scala:173:24, :826:53] wire _fast_wakeup_valid_T_10 = _fast_wakeup_valid_T_8 & _fast_wakeup_valid_T_9; // @[core.scala:824:45, :825:54, :826:53] wire _fast_wakeup_valid_T_11 = _fast_wakeup_valid_T_10 & iss_uops_2_ldst_val; // @[core.scala:173:24, :825:54, :826:64] wire _GEN_40 = iss_uops_2_iw_p1_poisoned \| iss_uops_2_iw_p2_poisoned; // @[core.scala:173:24, :828:79] wire _fast_wakeup_valid_T_12; // @[core.scala:828:79] assign _fast_wakeup_valid_T_12 = _GEN_40; // @[core.scala:828:79] wire _iregister_read_io_iss_valids_2_T; // @[core.scala:981:72] assign _iregister_read_io_iss_valids_2_T = _GEN_40; // @[core.scala:828:79, :981:72] wire _fast_wakeup_valid_T_13 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_12; // @[core.scala:51:7, :828:{48,79}] wire _fast_wakeup_valid_T_14 = ~_fast_wakeup_valid_T_13; // @[core.scala:828:{31,48}] assign _fast_wakeup_valid_T_15 = _fast_wakeup_valid_T_11 & _fast_wakeup_valid_T_14; // @[core.scala:826:64, :827:52, :828:31] assign fast_wakeup_1_valid = _fast_wakeup_valid_T_15; // @[core.scala:814:29, :827:52] wire _slow_wakeup_valid_T_7 = _alu_exe_unit_1_io_iresp_valid & _slow_wakeup_valid_T_6; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_8 = ~_alu_exe_unit_1_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_9 = _slow_wakeup_valid_T_7 & _slow_wakeup_valid_T_8; // @[core.scala:832:42, :833:54, :834:33] wire _T_118 = _alu_exe_unit_1_io_iresp_bits_uop_dst_rtype == 2'h0; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_10; // @[core.scala:835:57] assign _slow_wakeup_valid_T_10 = _T_118; // @[core.scala:835:57] wire _iregfile_io_write_ports_2_valid_T_2; // @[core.scala:1160:77] assign _iregfile_io_write_ports_2_valid_T_2 = _T_118; // @[core.scala:835:57, :1160:77] wire _rob_io_debug_wb_valids_2_T_2; // @[core.scala:1240:86] assign _rob_io_debug_wb_valids_2_T_2 = _T_118; // @[core.scala:835:57, :1240:86] assign _slow_wakeup_valid_T_11 = _slow_wakeup_valid_T_9 & _slow_wakeup_valid_T_10; // @[core.scala:833:54, :834:59, :835:57] assign slow_wakeup_1_valid = _slow_wakeup_valid_T_11; // @[core.scala:815:29, :834:59] wire _fast_wakeup_valid_T_23; // @[core.scala:827:52] assign int_iss_wakeups_5_valid = fast_wakeup_2_valid; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_valid = fast_wakeup_2_valid; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_uopc = fast_wakeup_2_bits_uop_uopc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_uopc = fast_wakeup_2_bits_uop_uopc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_inst = fast_wakeup_2_bits_uop_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_inst = fast_wakeup_2_bits_uop_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_debug_inst = fast_wakeup_2_bits_uop_debug_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_debug_inst = fast_wakeup_2_bits_uop_debug_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_rvc = fast_wakeup_2_bits_uop_is_rvc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_rvc = fast_wakeup_2_bits_uop_is_rvc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_debug_pc = fast_wakeup_2_bits_uop_debug_pc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_debug_pc = fast_wakeup_2_bits_uop_debug_pc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_iq_type = fast_wakeup_2_bits_uop_iq_type; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_iq_type = fast_wakeup_2_bits_uop_iq_type; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_fu_code = fast_wakeup_2_bits_uop_fu_code; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_fu_code = fast_wakeup_2_bits_uop_fu_code; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_br_type = fast_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_br_type = fast_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_op1_sel = fast_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_op1_sel = fast_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_op2_sel = fast_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_op2_sel = fast_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_imm_sel = fast_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_imm_sel = fast_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_op_fcn = fast_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_op_fcn = fast_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_fcn_dw = fast_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_fcn_dw = fast_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_csr_cmd = fast_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_csr_cmd = fast_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_is_load = fast_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_is_load = fast_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_is_sta = fast_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_is_sta = fast_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ctrl_is_std = fast_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ctrl_is_std = fast_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_iw_state = fast_wakeup_2_bits_uop_iw_state; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_iw_state = fast_wakeup_2_bits_uop_iw_state; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_iw_p1_poisoned = fast_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_iw_p1_poisoned = fast_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_iw_p2_poisoned = fast_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_iw_p2_poisoned = fast_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_br = fast_wakeup_2_bits_uop_is_br; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_br = fast_wakeup_2_bits_uop_is_br; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_jalr = fast_wakeup_2_bits_uop_is_jalr; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_jalr = fast_wakeup_2_bits_uop_is_jalr; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_jal = fast_wakeup_2_bits_uop_is_jal; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_jal = fast_wakeup_2_bits_uop_is_jal; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_sfb = fast_wakeup_2_bits_uop_is_sfb; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_sfb = fast_wakeup_2_bits_uop_is_sfb; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_br_mask = fast_wakeup_2_bits_uop_br_mask; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_br_mask = fast_wakeup_2_bits_uop_br_mask; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_br_tag = fast_wakeup_2_bits_uop_br_tag; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_br_tag = fast_wakeup_2_bits_uop_br_tag; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ftq_idx = fast_wakeup_2_bits_uop_ftq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ftq_idx = fast_wakeup_2_bits_uop_ftq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_edge_inst = fast_wakeup_2_bits_uop_edge_inst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_edge_inst = fast_wakeup_2_bits_uop_edge_inst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_pc_lob = fast_wakeup_2_bits_uop_pc_lob; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_pc_lob = fast_wakeup_2_bits_uop_pc_lob; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_taken = fast_wakeup_2_bits_uop_taken; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_taken = fast_wakeup_2_bits_uop_taken; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_imm_packed = fast_wakeup_2_bits_uop_imm_packed; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_imm_packed = fast_wakeup_2_bits_uop_imm_packed; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_csr_addr = fast_wakeup_2_bits_uop_csr_addr; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_csr_addr = fast_wakeup_2_bits_uop_csr_addr; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_rob_idx = fast_wakeup_2_bits_uop_rob_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_rob_idx = fast_wakeup_2_bits_uop_rob_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ldq_idx = fast_wakeup_2_bits_uop_ldq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ldq_idx = fast_wakeup_2_bits_uop_ldq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_stq_idx = fast_wakeup_2_bits_uop_stq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_stq_idx = fast_wakeup_2_bits_uop_stq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_rxq_idx = fast_wakeup_2_bits_uop_rxq_idx; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_rxq_idx = fast_wakeup_2_bits_uop_rxq_idx; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_pdst = fast_wakeup_2_bits_uop_pdst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_pdst = fast_wakeup_2_bits_uop_pdst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_prs1 = fast_wakeup_2_bits_uop_prs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_prs1 = fast_wakeup_2_bits_uop_prs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_prs2 = fast_wakeup_2_bits_uop_prs2; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_prs2 = fast_wakeup_2_bits_uop_prs2; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_prs3 = fast_wakeup_2_bits_uop_prs3; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_prs3 = fast_wakeup_2_bits_uop_prs3; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ppred = fast_wakeup_2_bits_uop_ppred; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ppred = fast_wakeup_2_bits_uop_ppred; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_prs1_busy = fast_wakeup_2_bits_uop_prs1_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_prs1_busy = fast_wakeup_2_bits_uop_prs1_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_prs2_busy = fast_wakeup_2_bits_uop_prs2_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_prs2_busy = fast_wakeup_2_bits_uop_prs2_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_prs3_busy = fast_wakeup_2_bits_uop_prs3_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_prs3_busy = fast_wakeup_2_bits_uop_prs3_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ppred_busy = fast_wakeup_2_bits_uop_ppred_busy; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ppred_busy = fast_wakeup_2_bits_uop_ppred_busy; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_stale_pdst = fast_wakeup_2_bits_uop_stale_pdst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_stale_pdst = fast_wakeup_2_bits_uop_stale_pdst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_exception = fast_wakeup_2_bits_uop_exception; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_exception = fast_wakeup_2_bits_uop_exception; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_exc_cause = fast_wakeup_2_bits_uop_exc_cause; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_exc_cause = fast_wakeup_2_bits_uop_exc_cause; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_bypassable = fast_wakeup_2_bits_uop_bypassable; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_bypassable = fast_wakeup_2_bits_uop_bypassable; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_mem_cmd = fast_wakeup_2_bits_uop_mem_cmd; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_mem_cmd = fast_wakeup_2_bits_uop_mem_cmd; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_mem_size = fast_wakeup_2_bits_uop_mem_size; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_mem_size = fast_wakeup_2_bits_uop_mem_size; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_mem_signed = fast_wakeup_2_bits_uop_mem_signed; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_mem_signed = fast_wakeup_2_bits_uop_mem_signed; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_fence = fast_wakeup_2_bits_uop_is_fence; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_fence = fast_wakeup_2_bits_uop_is_fence; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_fencei = fast_wakeup_2_bits_uop_is_fencei; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_fencei = fast_wakeup_2_bits_uop_is_fencei; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_amo = fast_wakeup_2_bits_uop_is_amo; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_amo = fast_wakeup_2_bits_uop_is_amo; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_uses_ldq = fast_wakeup_2_bits_uop_uses_ldq; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_uses_ldq = fast_wakeup_2_bits_uop_uses_ldq; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_uses_stq = fast_wakeup_2_bits_uop_uses_stq; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_uses_stq = fast_wakeup_2_bits_uop_uses_stq; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_sys_pc2epc = fast_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_sys_pc2epc = fast_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_is_unique = fast_wakeup_2_bits_uop_is_unique; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_is_unique = fast_wakeup_2_bits_uop_is_unique; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_flush_on_commit = fast_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_flush_on_commit = fast_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ldst_is_rs1 = fast_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ldst_is_rs1 = fast_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ldst = fast_wakeup_2_bits_uop_ldst; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ldst = fast_wakeup_2_bits_uop_ldst; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_lrs1 = fast_wakeup_2_bits_uop_lrs1; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_lrs1 = fast_wakeup_2_bits_uop_lrs1; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_lrs2 = fast_wakeup_2_bits_uop_lrs2; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_lrs2 = fast_wakeup_2_bits_uop_lrs2; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_lrs3 = fast_wakeup_2_bits_uop_lrs3; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_lrs3 = fast_wakeup_2_bits_uop_lrs3; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_ldst_val = fast_wakeup_2_bits_uop_ldst_val; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_ldst_val = fast_wakeup_2_bits_uop_ldst_val; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_dst_rtype = fast_wakeup_2_bits_uop_dst_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_dst_rtype = fast_wakeup_2_bits_uop_dst_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_lrs1_rtype = fast_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_lrs1_rtype = fast_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_lrs2_rtype = fast_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_lrs2_rtype = fast_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_frs3_en = fast_wakeup_2_bits_uop_frs3_en; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_frs3_en = fast_wakeup_2_bits_uop_frs3_en; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_fp_val = fast_wakeup_2_bits_uop_fp_val; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_fp_val = fast_wakeup_2_bits_uop_fp_val; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_fp_single = fast_wakeup_2_bits_uop_fp_single; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_fp_single = fast_wakeup_2_bits_uop_fp_single; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_xcpt_pf_if = fast_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_xcpt_pf_if = fast_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_xcpt_ae_if = fast_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_xcpt_ae_if = fast_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_xcpt_ma_if = fast_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_xcpt_ma_if = fast_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_bp_debug_if = fast_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_bp_debug_if = fast_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_bp_xcpt_if = fast_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_bp_xcpt_if = fast_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_debug_fsrc = fast_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_debug_fsrc = fast_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:148:30, :814:29] assign int_iss_wakeups_5_bits_uop_debug_tsrc = fast_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:147:30, :814:29] assign int_ren_wakeups_5_bits_uop_debug_tsrc = fast_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:148:30, :814:29] wire _slow_wakeup_valid_T_17; // @[core.scala:834:59] assign int_iss_wakeups_6_valid = slow_wakeup_2_valid; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_valid = slow_wakeup_2_valid; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_uopc = slow_wakeup_2_bits_uop_uopc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_uopc = slow_wakeup_2_bits_uop_uopc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_inst = slow_wakeup_2_bits_uop_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_inst = slow_wakeup_2_bits_uop_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_debug_inst = slow_wakeup_2_bits_uop_debug_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_debug_inst = slow_wakeup_2_bits_uop_debug_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_rvc = slow_wakeup_2_bits_uop_is_rvc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_rvc = slow_wakeup_2_bits_uop_is_rvc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_debug_pc = slow_wakeup_2_bits_uop_debug_pc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_debug_pc = slow_wakeup_2_bits_uop_debug_pc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_iq_type = slow_wakeup_2_bits_uop_iq_type; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_iq_type = slow_wakeup_2_bits_uop_iq_type; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_fu_code = slow_wakeup_2_bits_uop_fu_code; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_fu_code = slow_wakeup_2_bits_uop_fu_code; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_br_type = slow_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_br_type = slow_wakeup_2_bits_uop_ctrl_br_type; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_op1_sel = slow_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_op1_sel = slow_wakeup_2_bits_uop_ctrl_op1_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_op2_sel = slow_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_op2_sel = slow_wakeup_2_bits_uop_ctrl_op2_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_imm_sel = slow_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_imm_sel = slow_wakeup_2_bits_uop_ctrl_imm_sel; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_op_fcn = slow_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_op_fcn = slow_wakeup_2_bits_uop_ctrl_op_fcn; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_fcn_dw = slow_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_fcn_dw = slow_wakeup_2_bits_uop_ctrl_fcn_dw; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_csr_cmd = slow_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_csr_cmd = slow_wakeup_2_bits_uop_ctrl_csr_cmd; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_is_load = slow_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_is_load = slow_wakeup_2_bits_uop_ctrl_is_load; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_is_sta = slow_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_is_sta = slow_wakeup_2_bits_uop_ctrl_is_sta; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ctrl_is_std = slow_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ctrl_is_std = slow_wakeup_2_bits_uop_ctrl_is_std; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_iw_state = slow_wakeup_2_bits_uop_iw_state; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_iw_state = slow_wakeup_2_bits_uop_iw_state; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_iw_p1_poisoned = slow_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_iw_p1_poisoned = slow_wakeup_2_bits_uop_iw_p1_poisoned; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_iw_p2_poisoned = slow_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_iw_p2_poisoned = slow_wakeup_2_bits_uop_iw_p2_poisoned; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_br = slow_wakeup_2_bits_uop_is_br; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_br = slow_wakeup_2_bits_uop_is_br; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_jalr = slow_wakeup_2_bits_uop_is_jalr; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_jalr = slow_wakeup_2_bits_uop_is_jalr; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_jal = slow_wakeup_2_bits_uop_is_jal; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_jal = slow_wakeup_2_bits_uop_is_jal; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_sfb = slow_wakeup_2_bits_uop_is_sfb; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_sfb = slow_wakeup_2_bits_uop_is_sfb; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_br_mask = slow_wakeup_2_bits_uop_br_mask; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_br_mask = slow_wakeup_2_bits_uop_br_mask; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_br_tag = slow_wakeup_2_bits_uop_br_tag; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_br_tag = slow_wakeup_2_bits_uop_br_tag; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ftq_idx = slow_wakeup_2_bits_uop_ftq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ftq_idx = slow_wakeup_2_bits_uop_ftq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_edge_inst = slow_wakeup_2_bits_uop_edge_inst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_edge_inst = slow_wakeup_2_bits_uop_edge_inst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_pc_lob = slow_wakeup_2_bits_uop_pc_lob; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_pc_lob = slow_wakeup_2_bits_uop_pc_lob; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_taken = slow_wakeup_2_bits_uop_taken; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_taken = slow_wakeup_2_bits_uop_taken; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_imm_packed = slow_wakeup_2_bits_uop_imm_packed; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_imm_packed = slow_wakeup_2_bits_uop_imm_packed; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_csr_addr = slow_wakeup_2_bits_uop_csr_addr; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_csr_addr = slow_wakeup_2_bits_uop_csr_addr; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_rob_idx = slow_wakeup_2_bits_uop_rob_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_rob_idx = slow_wakeup_2_bits_uop_rob_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ldq_idx = slow_wakeup_2_bits_uop_ldq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ldq_idx = slow_wakeup_2_bits_uop_ldq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_stq_idx = slow_wakeup_2_bits_uop_stq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_stq_idx = slow_wakeup_2_bits_uop_stq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_rxq_idx = slow_wakeup_2_bits_uop_rxq_idx; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_rxq_idx = slow_wakeup_2_bits_uop_rxq_idx; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_pdst = slow_wakeup_2_bits_uop_pdst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_pdst = slow_wakeup_2_bits_uop_pdst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_prs1 = slow_wakeup_2_bits_uop_prs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_prs1 = slow_wakeup_2_bits_uop_prs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_prs2 = slow_wakeup_2_bits_uop_prs2; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_prs2 = slow_wakeup_2_bits_uop_prs2; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_prs3 = slow_wakeup_2_bits_uop_prs3; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_prs3 = slow_wakeup_2_bits_uop_prs3; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ppred = slow_wakeup_2_bits_uop_ppred; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ppred = slow_wakeup_2_bits_uop_ppred; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_prs1_busy = slow_wakeup_2_bits_uop_prs1_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_prs1_busy = slow_wakeup_2_bits_uop_prs1_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_prs2_busy = slow_wakeup_2_bits_uop_prs2_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_prs2_busy = slow_wakeup_2_bits_uop_prs2_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_prs3_busy = slow_wakeup_2_bits_uop_prs3_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_prs3_busy = slow_wakeup_2_bits_uop_prs3_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ppred_busy = slow_wakeup_2_bits_uop_ppred_busy; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ppred_busy = slow_wakeup_2_bits_uop_ppred_busy; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_stale_pdst = slow_wakeup_2_bits_uop_stale_pdst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_stale_pdst = slow_wakeup_2_bits_uop_stale_pdst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_exception = slow_wakeup_2_bits_uop_exception; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_exception = slow_wakeup_2_bits_uop_exception; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_exc_cause = slow_wakeup_2_bits_uop_exc_cause; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_exc_cause = slow_wakeup_2_bits_uop_exc_cause; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_bypassable = slow_wakeup_2_bits_uop_bypassable; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_bypassable = slow_wakeup_2_bits_uop_bypassable; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_mem_cmd = slow_wakeup_2_bits_uop_mem_cmd; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_mem_cmd = slow_wakeup_2_bits_uop_mem_cmd; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_mem_size = slow_wakeup_2_bits_uop_mem_size; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_mem_size = slow_wakeup_2_bits_uop_mem_size; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_mem_signed = slow_wakeup_2_bits_uop_mem_signed; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_mem_signed = slow_wakeup_2_bits_uop_mem_signed; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_fence = slow_wakeup_2_bits_uop_is_fence; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_fence = slow_wakeup_2_bits_uop_is_fence; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_fencei = slow_wakeup_2_bits_uop_is_fencei; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_fencei = slow_wakeup_2_bits_uop_is_fencei; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_amo = slow_wakeup_2_bits_uop_is_amo; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_amo = slow_wakeup_2_bits_uop_is_amo; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_uses_ldq = slow_wakeup_2_bits_uop_uses_ldq; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_uses_ldq = slow_wakeup_2_bits_uop_uses_ldq; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_uses_stq = slow_wakeup_2_bits_uop_uses_stq; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_uses_stq = slow_wakeup_2_bits_uop_uses_stq; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_sys_pc2epc = slow_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_sys_pc2epc = slow_wakeup_2_bits_uop_is_sys_pc2epc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_is_unique = slow_wakeup_2_bits_uop_is_unique; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_is_unique = slow_wakeup_2_bits_uop_is_unique; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_flush_on_commit = slow_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_flush_on_commit = slow_wakeup_2_bits_uop_flush_on_commit; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ldst_is_rs1 = slow_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ldst_is_rs1 = slow_wakeup_2_bits_uop_ldst_is_rs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ldst = slow_wakeup_2_bits_uop_ldst; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ldst = slow_wakeup_2_bits_uop_ldst; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_lrs1 = slow_wakeup_2_bits_uop_lrs1; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_lrs1 = slow_wakeup_2_bits_uop_lrs1; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_lrs2 = slow_wakeup_2_bits_uop_lrs2; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_lrs2 = slow_wakeup_2_bits_uop_lrs2; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_lrs3 = slow_wakeup_2_bits_uop_lrs3; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_lrs3 = slow_wakeup_2_bits_uop_lrs3; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_ldst_val = slow_wakeup_2_bits_uop_ldst_val; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_ldst_val = slow_wakeup_2_bits_uop_ldst_val; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_dst_rtype = slow_wakeup_2_bits_uop_dst_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_dst_rtype = slow_wakeup_2_bits_uop_dst_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_lrs1_rtype = slow_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_lrs1_rtype = slow_wakeup_2_bits_uop_lrs1_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_lrs2_rtype = slow_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_lrs2_rtype = slow_wakeup_2_bits_uop_lrs2_rtype; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_frs3_en = slow_wakeup_2_bits_uop_frs3_en; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_frs3_en = slow_wakeup_2_bits_uop_frs3_en; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_fp_val = slow_wakeup_2_bits_uop_fp_val; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_fp_val = slow_wakeup_2_bits_uop_fp_val; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_fp_single = slow_wakeup_2_bits_uop_fp_single; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_fp_single = slow_wakeup_2_bits_uop_fp_single; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_xcpt_pf_if = slow_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_xcpt_pf_if = slow_wakeup_2_bits_uop_xcpt_pf_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_xcpt_ae_if = slow_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_xcpt_ae_if = slow_wakeup_2_bits_uop_xcpt_ae_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_xcpt_ma_if = slow_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_xcpt_ma_if = slow_wakeup_2_bits_uop_xcpt_ma_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_bp_debug_if = slow_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_bp_debug_if = slow_wakeup_2_bits_uop_bp_debug_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_bp_xcpt_if = slow_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_bp_xcpt_if = slow_wakeup_2_bits_uop_bp_xcpt_if; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_debug_fsrc = slow_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_debug_fsrc = slow_wakeup_2_bits_uop_debug_fsrc; // @[core.scala:148:30, :815:29] assign int_iss_wakeups_6_bits_uop_debug_tsrc = slow_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:147:30, :815:29] assign int_ren_wakeups_6_bits_uop_debug_tsrc = slow_wakeup_2_bits_uop_debug_tsrc; // @[core.scala:148:30, :815:29] wire _T_149 = _alu_exe_unit_2_io_iresp_bits_uop_dst_rtype != 2'h2; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_12; // @[micro-op.scala:149:36] assign _slow_wakeup_valid_T_12 = _T_149; // @[micro-op.scala:149:36] wire _iregfile_io_write_ports_3_valid_T; // @[micro-op.scala:149:36] assign _iregfile_io_write_ports_3_valid_T = _T_149; // @[micro-op.scala:149:36] wire _rob_io_debug_wb_valids_3_T; // @[micro-op.scala:149:36] assign _rob_io_debug_wb_valids_3_T = _T_149; // @[micro-op.scala:149:36] wire _fast_wakeup_valid_T_16 = iss_valids_3 & iss_uops_3_bypassable; // @[core.scala:172:24, :173:24, :824:45] wire _fast_wakeup_valid_T_17 = iss_uops_3_dst_rtype == 2'h0; // @[core.scala:173:24, :826:53] wire _fast_wakeup_valid_T_18 = _fast_wakeup_valid_T_16 & _fast_wakeup_valid_T_17; // @[core.scala:824:45, :825:54, :826:53] wire _fast_wakeup_valid_T_19 = _fast_wakeup_valid_T_18 & iss_uops_3_ldst_val; // @[core.scala:173:24, :825:54, :826:64] wire _GEN_41 = iss_uops_3_iw_p1_poisoned \| iss_uops_3_iw_p2_poisoned; // @[core.scala:173:24, :828:79] wire _fast_wakeup_valid_T_20; // @[core.scala:828:79] assign _fast_wakeup_valid_T_20 = _GEN_41; // @[core.scala:828:79] wire _iregister_read_io_iss_valids_3_T; // @[core.scala:981:72] assign _iregister_read_io_iss_valids_3_T = _GEN_41; // @[core.scala:828:79, :981:72] wire _fast_wakeup_valid_T_21 = io_lsu_ld_miss_0 & _fast_wakeup_valid_T_20; // @[core.scala:51:7, :828:{48,79}] wire _fast_wakeup_valid_T_22 = ~_fast_wakeup_valid_T_21; // @[core.scala:828:{31,48}] assign _fast_wakeup_valid_T_23 = _fast_wakeup_valid_T_19 & _fast_wakeup_valid_T_22; // @[core.scala:826:64, :827:52, :828:31] assign fast_wakeup_2_valid = _fast_wakeup_valid_T_23; // @[core.scala:814:29, :827:52] wire _slow_wakeup_valid_T_13 = _alu_exe_unit_2_io_iresp_valid & _slow_wakeup_valid_T_12; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_14 = ~_alu_exe_unit_2_io_iresp_bits_uop_bypassable; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_15 = _slow_wakeup_valid_T_13 & _slow_wakeup_valid_T_14; // @[core.scala:832:42, :833:54, :834:33] wire _T_143 = _alu_exe_unit_2_io_iresp_bits_uop_dst_rtype == 2'h0; // @[execution-units.scala:119:32] wire _slow_wakeup_valid_T_16; // @[core.scala:835:57] assign _slow_wakeup_valid_T_16 = _T_143; // @[core.scala:835:57] wire _iregfile_io_write_ports_3_valid_T_2; // @[core.scala:1160:77] assign _iregfile_io_write_ports_3_valid_T_2 = _T_143; // @[core.scala:835:57, :1160:77] wire _rob_io_debug_wb_valids_3_T_2; // @[core.scala:1240:86] assign _rob_io_debug_wb_valids_3_T_2 = _T_143; // @[core.scala:835:57, :1240:86] assign _slow_wakeup_valid_T_17 = _slow_wakeup_valid_T_15 & _slow_wakeup_valid_T_16; // @[core.scala:833:54, :834:59, :835:57] assign slow_wakeup_2_valid = _slow_wakeup_valid_T_17; // @[core.scala:815:29, :834:59] wire _pred_wakeup_valid_T = iss_uops_1_is_br & iss_uops_1_is_sfb; // @[core.scala:173:24] wire _pred_wakeup_valid_T_4 = io_lsu_ld_miss_0 & _pred_wakeup_valid_T_3; // @[core.scala:51:7, :864:{42,84}] wire _pred_wakeup_valid_T_5 = ~_pred_wakeup_valid_T_4; // @[core.scala:864:{25,42}] wire loads_saturating = _mem_issue_unit_io_iss_valids_0 & _mem_issue_unit_io_iss_uops_0_uses_ldq; // @[core.scala:108:32, :908:57] reg [4:0] saturating_loads_counter; // @[core.scala:909:41] wire [5:0] _saturating_loads_counter_T = {1'h0, saturating_loads_counter} + 6'h1; // @[core.scala:909:41, :910:82] wire [4:0] _saturating_loads_counter_T_1 = _saturating_loads_counter_T[4:0]; // @[core.scala:910:82] reg pause_mem_REG; // @[core.scala:912:26] wire _pause_mem_T_1 = &saturating_loads_counter; // @[core.scala:909:41, :912:73] wire pause_mem = pause_mem_REG & _pause_mem_T_1; // @[core.scala:912:{26,45,73}] wire [9:0] _mem_issue_unit_io_fu_types_0_T = {7'h0, ~pause_mem, 2'h0}; // @[core.scala:912:45, :931:53] wire [9:0] _idiv_issued_T = iss_uops_1_fu_code & 10'h10; // @[core.scala:173:24] wire _idiv_issued_T_1 = \|_idiv_issued_T; // @[micro-op.scala:154:{40,47}] wire idiv_issued = iss_valids_1 & _idiv_issued_T_1; // @[core.scala:172:24, :924:47] reg [9:0] REG_4; // @[core.scala:925:38] wire [9:0] _idiv_issued_T_2 = iss_uops_3_fu_code & 10'h10; // @[core.scala:173:24] wire _idiv_issued_T_3 = \|_idiv_issued_T_2; // @[micro-op.scala:154:{40,47}] wire idiv_issued_1 = iss_valids_3 & _idiv_issued_T_3; // @[core.scala:172:24, :924:47] reg [9:0] REG_5; // @[core.scala:925:38] reg mem_issue_unit_io_flush_pipeline_REG; // @[core.scala:946:49] reg int_issue_unit_io_flush_pipeline_REG; // @[core.scala:946:49] reg memExeUnit_io_com_exception_REG; // @[core.scala:952:51] wire _GEN_42 = int_iss_wakeups_0_bits_uop_iw_p1_poisoned \| int_iss_wakeups_0_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_0_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_0_bits_poisoned_T = _GEN_42; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_0_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_0_bits_poisoned_T = _GEN_42; // @[core.scala:961:61] wire _GEN_43 = int_iss_wakeups_1_bits_uop_iw_p1_poisoned \| int_iss_wakeups_1_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_1_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_1_bits_poisoned_T = _GEN_43; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_1_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_1_bits_poisoned_T = _GEN_43; // @[core.scala:961:61] wire _GEN_44 = int_iss_wakeups_2_bits_uop_iw_p1_poisoned \| int_iss_wakeups_2_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_2_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_2_bits_poisoned_T = _GEN_44; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_2_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_2_bits_poisoned_T = _GEN_44; // @[core.scala:961:61] wire _GEN_45 = int_iss_wakeups_3_bits_uop_iw_p1_poisoned \| int_iss_wakeups_3_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_3_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_3_bits_poisoned_T = _GEN_45; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_3_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_3_bits_poisoned_T = _GEN_45; // @[core.scala:961:61] wire _GEN_46 = int_iss_wakeups_4_bits_uop_iw_p1_poisoned \| int_iss_wakeups_4_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_4_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_4_bits_poisoned_T = _GEN_46; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_4_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_4_bits_poisoned_T = _GEN_46; // @[core.scala:961:61] wire _GEN_47 = int_iss_wakeups_5_bits_uop_iw_p1_poisoned \| int_iss_wakeups_5_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_5_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_5_bits_poisoned_T = _GEN_47; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_5_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_5_bits_poisoned_T = _GEN_47; // @[core.scala:961:61] wire _GEN_48 = int_iss_wakeups_6_bits_uop_iw_p1_poisoned \| int_iss_wakeups_6_bits_uop_iw_p2_poisoned; // @[core.scala:147:30, :961:61] wire _mem_issue_unit_io_wakeup_ports_6_bits_poisoned_T; // @[core.scala:961:61] assign _mem_issue_unit_io_wakeup_ports_6_bits_poisoned_T = _GEN_48; // @[core.scala:961:61] wire _int_issue_unit_io_wakeup_ports_6_bits_poisoned_T; // @[core.scala:961:61] assign _int_issue_unit_io_wakeup_ports_6_bits_poisoned_T = _GEN_48; // @[core.scala:961:61] wire _iregister_read_io_iss_valids_0_T = iss_uops_0_iw_p1_poisoned \| iss_uops_0_iw_p2_poisoned; // @[core.scala:173:24, :981:72] wire _iregister_read_io_iss_valids_0_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_0_T; // @[core.scala:51:7, :981:{41,72}] wire _iregister_read_io_iss_valids_0_T_2 = ~_iregister_read_io_iss_valids_0_T_1; // @[core.scala:981:{24,41}] wire _iregister_read_io_iss_valids_0_T_3 = iss_valids_0 & _iregister_read_io_iss_valids_0_T_2; // @[core.scala:172:24, :981:{21,24}] wire _iregister_read_io_iss_valids_1_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_1_T; // @[core.scala:51:7, :981:{41,72}] wire _iregister_read_io_iss_valids_1_T_2 = ~_iregister_read_io_iss_valids_1_T_1; // @[core.scala:981:{24,41}] wire _iregister_read_io_iss_valids_1_T_3 = iss_valids_1 & _iregister_read_io_iss_valids_1_T_2; // @[core.scala:172:24, :981:{21,24}] wire _iregister_read_io_iss_valids_2_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_2_T; // @[core.scala:51:7, :981:{41,72}] wire _iregister_read_io_iss_valids_2_T_2 = ~_iregister_read_io_iss_valids_2_T_1; // @[core.scala:981:{24,41}] wire _iregister_read_io_iss_valids_2_T_3 = iss_valids_2 & _iregister_read_io_iss_valids_2_T_2; // @[core.scala:172:24, :981:{21,24}] wire _iregister_read_io_iss_valids_3_T_1 = io_lsu_ld_miss_0 & _iregister_read_io_iss_valids_3_T; // @[core.scala:51:7, :981:{41,72}] wire _iregister_read_io_iss_valids_3_T_2 = ~_iregister_read_io_iss_valids_3_T_1; // @[core.scala:981:{24,41}] wire _iregister_read_io_iss_valids_3_T_3 = iss_valids_3 & _iregister_read_io_iss_valids_3_T_2; // @[core.scala:172:24, :981:{21,24}] reg iregister_read_io_kill_REG; // @[core.scala:987:38] wire [2:0] _csr_io_rw_cmd_T = {~_alu_exe_unit_1_io_iresp_valid, 2'h0}; // @[CSR.scala:183:15] wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}] wire [2:0] _csr_io_rw_cmd_T_2 = _alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd & _csr_io_rw_cmd_T_1; // @[CSR.scala:183:{9,11}] wire [2:0] _csr_io_retire_T = {csr_io_retire_hi, _rob_io_commit_arch_valids_0}; // @[core.scala:143:32, :1015:66] wire _csr_io_retire_T_1 = _csr_io_retire_T[0]; // @[core.scala:1015:{39,66}] wire _csr_io_retire_T_2 = _csr_io_retire_T[1]; // @[core.scala:1015:{39,66}] wire _csr_io_retire_T_3 = _csr_io_retire_T[2]; // @[core.scala:1015:{39,66}] wire [1:0] _csr_io_retire_T_4 = {1'h0, _csr_io_retire_T_2} + {1'h0, _csr_io_retire_T_3}; // @[core.scala:1015:39] wire [1:0] _csr_io_retire_T_5 = _csr_io_retire_T_4; // @[core.scala:1015:39] wire [2:0] _csr_io_retire_T_6 = {2'h0, _csr_io_retire_T_1} + {1'h0, _csr_io_retire_T_5}; // @[core.scala:1015:39] wire [1:0] _csr_io_retire_T_7 = _csr_io_retire_T_6[1:0]; // @[core.scala:1015:39] reg [1:0] csr_io_retire_REG; // @[core.scala:1015:30] reg csr_io_exception_REG; // @[core.scala:1016:30] wire [39:0] _csr_io_pc_T = ~io_ifu_get_pc_0_com_pc_0; // @[util.scala:237:7] wire [39:0] _csr_io_pc_T_1 = {_csr_io_pc_T[39:6], 6'h3F}; // @[util.scala:237:{7,11}] wire [39:0] _csr_io_pc_T_2 = ~_csr_io_pc_T_1; // @[util.scala:237:{5,11}] reg [5:0] csr_io_pc_REG; // @[core.scala:1020:31] wire [40:0] _csr_io_pc_T_3 = {1'h0, _csr_io_pc_T_2} + {35'h0, csr_io_pc_REG}; // @[util.scala:237:5] wire [39:0] _csr_io_pc_T_4 = _csr_io_pc_T_3[39:0]; // @[core.scala:1020:22] reg csr_io_pc_REG_1; // @[core.scala:1021:35] wire [1:0] _csr_io_pc_T_5 = {csr_io_pc_REG_1, 1'h0}; // @[core.scala:1021:{27,35}] wire [40:0] _csr_io_pc_T_6 = {1'h0, _csr_io_pc_T_4} - {39'h0, _csr_io_pc_T_5}; // @[core.scala:1020:22, :1021:{22,27}] wire [39:0] _csr_io_pc_T_7 = _csr_io_pc_T_6[39:0]; // @[core.scala:1021:22] reg [63:0] csr_io_cause_REG; // @[core.scala:1023:30] wire _tval_valid_T = csr_io_cause_REG == 64'h3; // @[package.scala:16:47] wire _tval_valid_T_1 = csr_io_cause_REG == 64'h4; // @[package.scala:16:47] wire _tval_valid_T_2 = csr_io_cause_REG == 64'h6; // @[package.scala:16:47] wire _tval_valid_T_3 = csr_io_cause_REG == 64'h5; // @[package.scala:16:47] wire _tval_valid_T_4 = csr_io_cause_REG == 64'h7; // @[package.scala:16:47] wire _tval_valid_T_5 = csr_io_cause_REG == 64'h1; // @[package.scala:16:47] wire _tval_valid_T_6 = csr_io_cause_REG == 64'hD; // @[package.scala:16:47] wire _tval_valid_T_7 = csr_io_cause_REG == 64'hF; // @[package.scala:16:47] wire _tval_valid_T_8 = csr_io_cause_REG == 64'hC; // @[package.scala:16:47] wire _tval_valid_T_9 = _tval_valid_T \| _tval_valid_T_1; // @[package.scala:16:47, :81:59] wire _tval_valid_T_10 = _tval_valid_T_9 \| _tval_valid_T_2; // @[package.scala:16:47, :81:59] wire _tval_valid_T_11 = _tval_valid_T_10 \| _tval_valid_T_3; // @[package.scala:16:47, :81:59] wire _tval_valid_T_12 = _tval_valid_T_11 \| _tval_valid_T_4; // @[package.scala:16:47, :81:59] wire _tval_valid_T_13 = _tval_valid_T_12 \| _tval_valid_T_5; // @[package.scala:16:47, :81:59] wire _tval_valid_T_14 = _tval_valid_T_13 \| _tval_valid_T_6; // @[package.scala:16:47, :81:59] wire _tval_valid_T_15 = _tval_valid_T_14 \| _tval_valid_T_7; // @[package.scala:16:47, :81:59] wire _tval_valid_T_16 = _tval_valid_T_15 \| _tval_valid_T_8; // @[package.scala:16:47, :81:59] wire tval_valid = csr_io_exception_REG & _tval_valid_T_16; // @[package.scala:81:59] wire [63:0] _csr_io_tval_a_T; // @[core.scala:1049:18] wire [24:0] csr_io_tval_a = _csr_io_tval_a_T[63:39]; // @[core.scala:1049:{18,25}] wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[core.scala:1049:25, :1050:23] wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[core.scala:1049:25, :1050:36] wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T \| _csr_io_tval_msb_T_1; // @[core.scala:1050:{23,31,36}] wire _csr_io_tval_msb_T_3 = _rob_io_com_xcpt_bits_badvaddr[39]; // @[core.scala:143:32, :1050:48] wire _csr_io_tval_msb_T_4 = _rob_io_com_xcpt_bits_badvaddr[38]; // @[core.scala:143:32, :1050:64] wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[core.scala:1050:{61,64}] wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[core.scala:1050:{20,31,48,61}] wire [38:0] _csr_io_tval_T = _rob_io_com_xcpt_bits_badvaddr[38:0]; // @[core.scala:143:32, :1051:18] wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[core.scala:1050:20, :1051:{10,18}] reg [39:0] csr_io_tval_REG; // @[core.scala:1040:12] wire [39:0] _csr_io_tval_T_2 = tval_valid ? csr_io_tval_REG : 40'h0; // @[core.scala:1026:37, :1039:21, :1040:12] assign bypasses_0_bits_data = _alu_exe_unit_io_bypass_0_bits_data[63:0]; // @[execution-units.scala:119:32] assign bypasses_1_bits_data = _alu_exe_unit_1_io_bypass_0_bits_data[63:0]; // @[execution-units.scala:119:32] assign bypasses_2_bits_data = _alu_exe_unit_2_io_bypass_0_bits_data[63:0]; // @[execution-units.scala:119:32] assign bypasses_3_bits_data = _alu_exe_unit_2_io_bypass_1_bits_data[63:0]; // @[execution-units.scala:119:32] assign bypasses_4_bits_data = _alu_exe_unit_2_io_bypass_2_bits_data[63:0]; // @[execution-units.scala:119:32] assign pred_bypasses_0_bits_data = _alu_exe_unit_io_bypass_0_bits_data[0]; // @[execution-units.scala:119:32] reg io_lsu_exception_REG; // @[core.scala:1124:30] assign io_lsu_exception_0 = io_lsu_exception_REG; // @[core.scala:51:7, :1124:30] wire _iregfile_io_write_ports_0_wport_valid_T_1; // @[regfile.scala:57:35] wire [6:0] iregfile_io_write_ports_0_wport_bits_addr; // @[regfile.scala:55:22] wire [63:0] iregfile_io_write_ports_0_wport_bits_data; // @[regfile.scala:55:22] wire iregfile_io_write_ports_0_wport_valid; // @[regfile.scala:55:22] assign _iregfile_io_write_ports_0_wport_valid_T_1 = _ll_wbarb_io_out_valid & _iregfile_io_write_ports_0_wport_valid_T; // @[regfile.scala:57:{35,61}] assign iregfile_io_write_ports_0_wport_valid = _iregfile_io_write_ports_0_wport_valid_T_1; // @[regfile.scala:55:22, :57:35] wire wbReadsCSR = \|_alu_exe_unit_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _iregfile_io_write_ports_1_valid_T_1 = _alu_exe_unit_io_iresp_valid & _iregfile_io_write_ports_1_valid_T; // @[execution-units.scala:119:32] wire _iregfile_io_write_ports_1_valid_T_3 = _iregfile_io_write_ports_1_valid_T_1 & _iregfile_io_write_ports_1_valid_T_2; // @[core.scala:1160:{22,48,77}] wire wbReadsCSR_1 = \|_alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _iregfile_io_write_ports_2_valid_T_1 = _alu_exe_unit_1_io_iresp_valid & _iregfile_io_write_ports_2_valid_T; // @[execution-units.scala:119:32] wire _iregfile_io_write_ports_2_valid_T_3 = _iregfile_io_write_ports_2_valid_T_1 & _iregfile_io_write_ports_2_valid_T_2; // @[core.scala:1160:{22,48,77}] wire [64:0] _GEN_49 = {1'h0, _csr_io_rw_rdata}; // @[core.scala:271:19, :1167:56] wire [64:0] _iregfile_io_write_ports_2_bits_data_T = wbReadsCSR_1 ? _GEN_49 : _alu_exe_unit_1_io_iresp_bits_data; // @[execution-units.scala:119:32] wire wbReadsCSR_2 = \|_alu_exe_unit_2_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire _iregfile_io_write_ports_3_valid_T_1 = _alu_exe_unit_2_io_iresp_valid & _iregfile_io_write_ports_3_valid_T; // @[execution-units.scala:119:32] wire _iregfile_io_write_ports_3_valid_T_3 = _iregfile_io_write_ports_3_valid_T_1 & _iregfile_io_write_ports_3_valid_T_2; // @[core.scala:1160:{22,48,77}] wire _rob_io_wb_resps_0_valid_T = ~_ll_wbarb_io_out_bits_uop_is_amo; // @[core.scala:132:32, :1217:78] wire _rob_io_wb_resps_0_valid_T_1 = _ll_wbarb_io_out_bits_uop_uses_stq & _rob_io_wb_resps_0_valid_T; // @[core.scala:132:32, :1217:{75,78}] wire _rob_io_wb_resps_0_valid_T_2 = ~_rob_io_wb_resps_0_valid_T_1; // @[core.scala:1217:{57,75}] wire _rob_io_wb_resps_0_valid_T_3 = _ll_wbarb_io_out_valid & _rob_io_wb_resps_0_valid_T_2; // @[core.scala:132:32, :1217:{54,57}] wire _rob_io_debug_wb_valids_0_T = _ll_wbarb_io_out_bits_uop_dst_rtype != 2'h2; // @[core.scala:132:32, :1219:74] wire _rob_io_debug_wb_valids_0_T_1 = _ll_wbarb_io_out_valid & _rob_io_debug_wb_valids_0_T; // @[core.scala:132:32, :1219:{54,74}] wire _rob_io_wb_resps_1_valid_T = ~_alu_exe_unit_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_1_valid_T_1 = _alu_exe_unit_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_1_valid_T; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_1_valid_T_2 = ~_rob_io_wb_resps_1_valid_T_1; // @[core.scala:1238:{51,69}] wire _rob_io_wb_resps_1_valid_T_3 = _alu_exe_unit_io_iresp_valid & _rob_io_wb_resps_1_valid_T_2; // @[execution-units.scala:119:32] wire _rob_io_debug_wb_valids_1_T_1 = _alu_exe_unit_io_iresp_valid & _rob_io_debug_wb_valids_1_T; // @[execution-units.scala:119:32] wire _rob_io_debug_wb_valids_1_T_3 = _rob_io_debug_wb_valids_1_T_1 & _rob_io_debug_wb_valids_1_T_2; // @[core.scala:1240:{49,66,86}] wire _rob_io_wb_resps_2_valid_T = ~_alu_exe_unit_1_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_2_valid_T_1 = _alu_exe_unit_1_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_2_valid_T; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_2_valid_T_2 = ~_rob_io_wb_resps_2_valid_T_1; // @[core.scala:1238:{51,69}] wire _rob_io_wb_resps_2_valid_T_3 = _alu_exe_unit_1_io_iresp_valid & _rob_io_wb_resps_2_valid_T_2; // @[execution-units.scala:119:32] wire _rob_io_debug_wb_valids_2_T_1 = _alu_exe_unit_1_io_iresp_valid & _rob_io_debug_wb_valids_2_T; // @[execution-units.scala:119:32] wire _rob_io_debug_wb_valids_2_T_3 = _rob_io_debug_wb_valids_2_T_1 & _rob_io_debug_wb_valids_2_T_2; // @[core.scala:1240:{49,66,86}] wire _rob_io_debug_wb_wdata_2_T = \|_alu_exe_unit_1_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-units.scala:119:32] wire [64:0] _rob_io_debug_wb_wdata_2_T_1 = _rob_io_debug_wb_wdata_2_T ? _GEN_49 : _alu_exe_unit_1_io_iresp_bits_data; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_3_valid_T = ~_alu_exe_unit_2_io_iresp_bits_uop_is_amo; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_3_valid_T_1 = _alu_exe_unit_2_io_iresp_bits_uop_uses_stq & _rob_io_wb_resps_3_valid_T; // @[execution-units.scala:119:32] wire _rob_io_wb_resps_3_valid_T_2 = ~_rob_io_wb_resps_3_valid_T_1; // @[core.scala:1238:{51,69}] wire _rob_io_wb_resps_3_valid_T_3 = _alu_exe_unit_2_io_iresp_valid & _rob_io_wb_resps_3_valid_T_2; // @[execution-units.scala:119:32] wire _rob_io_debug_wb_valids_3_T_1 = _alu_exe_unit_2_io_iresp_valid & _rob_io_debug_wb_valids_3_T; // @[execution-units.scala:119:32] wire _rob_io_debug_wb_valids_3_T_3 = _rob_io_debug_wb_valids_3_T_1 & _rob_io_debug_wb_valids_3_T_2; // @[core.scala:1240:{49,66,86}] reg REG_6; // @[core.scala:1306:45] reg memExeUnit_io_req_bits_kill_REG; // @[core.scala:1310:45] reg alu_exe_unit_io_req_bits_kill_REG; // @[core.scala:1310:45] reg alu_exe_unit_io_req_bits_kill_REG_1; // @[core.scala:1310:45] reg alu_exe_unit_io_req_bits_kill_REG_2; // @[core.scala:1310:45] reg [4:0] small_0; // @[Counters.scala:45:41] wire [5:0] nextSmall = {1'h0, small_0} + 6'h1; // @[Counters.scala:45:41, :46:33] reg [26:0] large_0; // @[Counters.scala:50:31] wire _large_T = nextSmall[5]; // @[Counters.scala:46:33, :51:20] wire _large_T_2 = _large_T; // @[Counters.scala:51:{20,33}] wire [27:0] _large_r_T = {1'h0, large_0} + 28'h1; // @[Counters.scala:50:31, :51:55] wire [26:0] _large_r_T_1 = _large_r_T[26:0]; // @[Counters.scala:51:55] wire [31:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] wire [1:0] hi = {_rob_io_commit_valids_2, _rob_io_commit_valids_1}; // @[core.scala:143:32, :1324:30]
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_115 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_115 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module RoundRawFNToRecFN_e8_s24_115( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_115 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module SinkD_1 : input clock : Clock input reset : Reset output io : { resp : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, source : UInt<4>, flip way : UInt<4>, flip set : UInt<11>, bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<3>, mask : UInt<1>}}, bs_dat : { data : UInt<64>}, grant_req : { set : UInt<11>, way : UInt<4>}, flip grant_safe : UInt<1>} inst d_q of Queue2_TLBundleD_a32d64s4k3z3c_1 connect d_q.clock, clock connect d_q.reset, reset connect d_q.io.enq.valid, io.d.valid connect d_q.io.enq.bits.corrupt, io.d.bits.corrupt connect d_q.io.enq.bits.data, io.d.bits.data connect d_q.io.enq.bits.denied, io.d.bits.denied connect d_q.io.enq.bits.sink, io.d.bits.sink connect d_q.io.enq.bits.source, io.d.bits.source connect d_q.io.enq.bits.size, io.d.bits.size connect d_q.io.enq.bits.param, io.d.bits.param connect d_q.io.enq.bits.opcode, io.d.bits.opcode connect io.d.ready, d_q.io.enq.ready node _T = and(d_q.io.deq.ready, d_q.io.deq.valid) node _r_beats1_decode_T = dshl(UInt<6>(0h3f), d_q.io.deq.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 5, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(d_q.io.deq.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node last = or(_r_last_T, _r_last_T_1) node r_3 = and(last, _T) node _r_count_T = not(r_counter1) node beat = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(first, r_beats1, r_counter1) connect r_counter, _r_counter_T node hasData = bits(d_q.io.deq.bits.opcode, 0, 0) reg io_source_r : UInt<4>, clock when d_q.io.deq.valid : connect io_source_r, d_q.io.deq.bits.source node _io_source_T = mux(d_q.io.deq.valid, d_q.io.deq.bits.source, io_source_r) connect io.source, _io_source_T connect io.grant_req.way, io.way connect io.grant_req.set, io.set node _io_resp_valid_T = or(first, last) node _io_resp_valid_T_1 = and(d_q.io.deq.ready, d_q.io.deq.valid) node _io_resp_valid_T_2 = and(_io_resp_valid_T, _io_resp_valid_T_1) connect io.resp.valid, _io_resp_valid_T_2 node _q_io_deq_ready_T = eq(first, UInt<1>(0h0)) node _q_io_deq_ready_T_1 = or(_q_io_deq_ready_T, io.grant_safe) node _q_io_deq_ready_T_2 = and(io.bs_adr.ready, _q_io_deq_ready_T_1) connect d_q.io.deq.ready, _q_io_deq_ready_T_2 node _io_bs_adr_valid_T = eq(first, UInt<1>(0h0)) node _io_bs_adr_valid_T_1 = and(d_q.io.deq.valid, io.grant_safe) node _io_bs_adr_valid_T_2 = or(_io_bs_adr_valid_T, _io_bs_adr_valid_T_1) connect io.bs_adr.valid, _io_bs_adr_valid_T_2 node _T_1 = and(d_q.io.deq.valid, first) node _T_2 = eq(io.grant_safe, UInt<1>(0h0)) node _T_3 = and(_T_1, _T_2) node _T_4 = eq(io.bs_adr.ready, UInt<1>(0h0)) node _T_5 = and(io.bs_adr.valid, _T_4) connect io.resp.bits.last, last connect io.resp.bits.opcode, d_q.io.deq.bits.opcode connect io.resp.bits.param, d_q.io.deq.bits.param connect io.resp.bits.source, d_q.io.deq.bits.source connect io.resp.bits.sink, d_q.io.deq.bits.sink connect io.resp.bits.denied, d_q.io.deq.bits.denied node _io_bs_adr_bits_noop_T = eq(d_q.io.deq.valid, UInt<1>(0h0)) node _io_bs_adr_bits_noop_T_1 = eq(hasData, UInt<1>(0h0)) node _io_bs_adr_bits_noop_T_2 = or(_io_bs_adr_bits_noop_T, _io_bs_adr_bits_noop_T_1) connect io.bs_adr.bits.noop, _io_bs_adr_bits_noop_T_2 connect io.bs_adr.bits.way, io.way connect io.bs_adr.bits.set, io.set node _io_bs_adr_bits_beat_T = add(beat, io.bs_adr.ready) node _io_bs_adr_bits_beat_T_1 = tail(_io_bs_adr_bits_beat_T, 1) reg io_bs_adr_bits_beat_r : UInt<3>, clock when d_q.io.deq.valid : connect io_bs_adr_bits_beat_r, _io_bs_adr_bits_beat_T_1 node _io_bs_adr_bits_beat_T_2 = mux(d_q.io.deq.valid, beat, io_bs_adr_bits_beat_r) connect io.bs_adr.bits.beat, _io_bs_adr_bits_beat_T_2 node _io_bs_adr_bits_mask_T = not(UInt<1>(0h0)) connect io.bs_adr.bits.mask, _io_bs_adr_bits_mask_T connect io.bs_dat.data, d_q.io.deq.bits.data node _T_6 = and(d_q.io.deq.valid, d_q.io.deq.bits.corrupt) node _T_7 = eq(d_q.io.deq.bits.denied, UInt<1>(0h0)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unsupported\n at SinkD.scala:82 assert (!(d.valid && d.bits.corrupt && !d.bits.denied), \"Data poisoning unsupported\")\n") : printf assert(clock, _T_9, UInt<1>(0h1), "") : assert	module SinkD_1( // @[SinkD.scala:34:7] input clock, // @[SinkD.scala:34:7] input reset, // @[SinkD.scala:34:7] output io_resp_valid, // @[SinkD.scala:36:14] output io_resp_bits_last, // @[SinkD.scala:36:14] output [2:0] io_resp_bits_opcode, // @[SinkD.scala:36:14] output [2:0] io_resp_bits_param, // @[SinkD.scala:36:14] output [3:0] io_resp_bits_source, // @[SinkD.scala:36:14] output [2:0] io_resp_bits_sink, // @[SinkD.scala:36:14] output io_resp_bits_denied, // @[SinkD.scala:36:14] output io_d_ready, // @[SinkD.scala:36:14] input io_d_valid, // @[SinkD.scala:36:14] input [2:0] io_d_bits_opcode, // @[SinkD.scala:36:14] input [1:0] io_d_bits_param, // @[SinkD.scala:36:14] input [2:0] io_d_bits_size, // @[SinkD.scala:36:14] input [3:0] io_d_bits_source, // @[SinkD.scala:36:14] input [2:0] io_d_bits_sink, // @[SinkD.scala:36:14] input io_d_bits_denied, // @[SinkD.scala:36:14] input [63:0] io_d_bits_data, // @[SinkD.scala:36:14] input io_d_bits_corrupt, // @[SinkD.scala:36:14] output [3:0] io_source, // @[SinkD.scala:36:14] input [3:0] io_way, // @[SinkD.scala:36:14] input [10:0] io_set, // @[SinkD.scala:36:14] input io_bs_adr_ready, // @[SinkD.scala:36:14] output io_bs_adr_valid, // @[SinkD.scala:36:14] output io_bs_adr_bits_noop, // @[SinkD.scala:36:14] output [3:0] io_bs_adr_bits_way, // @[SinkD.scala:36:14] output [10:0] io_bs_adr_bits_set, // @[SinkD.scala:36:14] output [2:0] io_bs_adr_bits_beat, // @[SinkD.scala:36:14] output [63:0] io_bs_dat_data, // @[SinkD.scala:36:14] output [10:0] io_grant_req_set, // @[SinkD.scala:36:14] output [3:0] io_grant_req_way, // @[SinkD.scala:36:14] input io_grant_safe // @[SinkD.scala:36:14] ); wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [2:0] _d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [3:0] _d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire io_d_valid_0 = io_d_valid; // @[SinkD.scala:34:7] wire [2:0] io_d_bits_opcode_0 = io_d_bits_opcode; // @[SinkD.scala:34:7] wire [1:0] io_d_bits_param_0 = io_d_bits_param; // @[SinkD.scala:34:7] wire [2:0] io_d_bits_size_0 = io_d_bits_size; // @[SinkD.scala:34:7] wire [3:0] io_d_bits_source_0 = io_d_bits_source; // @[SinkD.scala:34:7] wire [2:0] io_d_bits_sink_0 = io_d_bits_sink; // @[SinkD.scala:34:7] wire io_d_bits_denied_0 = io_d_bits_denied; // @[SinkD.scala:34:7] wire [63:0] io_d_bits_data_0 = io_d_bits_data; // @[SinkD.scala:34:7] wire io_d_bits_corrupt_0 = io_d_bits_corrupt; // @[SinkD.scala:34:7] wire [3:0] io_way_0 = io_way; // @[SinkD.scala:34:7] wire [10:0] io_set_0 = io_set; // @[SinkD.scala:34:7] wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SinkD.scala:34:7] wire io_grant_safe_0 = io_grant_safe; // @[SinkD.scala:34:7] wire io_bs_adr_bits_mask = 1'h1; // @[SinkD.scala:34:7] wire _io_bs_adr_bits_mask_T = 1'h1; // @[SinkD.scala:79:26] wire _io_resp_valid_T_2; // @[SinkD.scala:62:36] wire last; // @[Edges.scala:232:33] wire [3:0] _io_source_T; // @[SinkD.scala:57:19] wire [3:0] io_bs_adr_bits_way_0 = io_way_0; // @[SinkD.scala:34:7] wire [3:0] io_grant_req_way_0 = io_way_0; // @[SinkD.scala:34:7] wire [10:0] io_bs_adr_bits_set_0 = io_set_0; // @[SinkD.scala:34:7] wire [10:0] io_grant_req_set_0 = io_set_0; // @[SinkD.scala:34:7] wire _io_bs_adr_valid_T_2; // @[SinkD.scala:64:29] wire _io_bs_adr_bits_noop_T_2; // @[SinkD.scala:75:35] wire [2:0] _io_bs_adr_bits_beat_T_2; // @[SinkD.scala:78:29] wire io_resp_bits_last_0; // @[SinkD.scala:34:7] wire [2:0] io_resp_bits_opcode_0; // @[SinkD.scala:34:7] wire [2:0] io_resp_bits_param_0; // @[SinkD.scala:34:7] wire [3:0] io_resp_bits_source_0; // @[SinkD.scala:34:7] wire [2:0] io_resp_bits_sink_0; // @[SinkD.scala:34:7] wire io_resp_bits_denied_0; // @[SinkD.scala:34:7] wire io_resp_valid_0; // @[SinkD.scala:34:7] wire io_d_ready_0; // @[SinkD.scala:34:7] wire io_bs_adr_bits_noop_0; // @[SinkD.scala:34:7] wire [2:0] io_bs_adr_bits_beat_0; // @[SinkD.scala:34:7] wire io_bs_adr_valid_0; // @[SinkD.scala:34:7] wire [63:0] io_bs_dat_data_0; // @[SinkD.scala:34:7] wire [3:0] io_source_0; // @[SinkD.scala:34:7] wire _q_io_deq_ready_T_2; // @[SinkD.scala:63:30] wire _io_resp_valid_T_1 = _q_io_deq_ready_T_2 & _d_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [12:0] _r_beats1_decode_T = 13'h3F << _d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] r_beats1_decode = _r_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire r_beats1_opdata = _d_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] wire hasData = _d_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21] wire [2:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] r_counter; // @[Edges.scala:229:27] wire [3:0] _r_counter1_T = {1'h0, r_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] r_counter1 = _r_counter1_T[2:0]; // @[Edges.scala:230:28] wire first = r_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] assign last = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] assign io_resp_bits_last_0 = last; // @[Edges.scala:232:33] wire r_3 = last & _io_resp_valid_T_1; // @[Decoupled.scala:51:35] wire [2:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] beat = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _r_counter_T = first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [3:0] io_source_r; // @[SinkD.scala:57:53] assign _io_source_T = _d_q_io_deq_valid ? _d_q_io_deq_bits_source : io_source_r; // @[Decoupled.scala:362:21] assign io_source_0 = _io_source_T; // @[SinkD.scala:34:7, :57:19] wire _io_resp_valid_T = first \| last; // @[Edges.scala:231:25, :232:33] assign _io_resp_valid_T_2 = _io_resp_valid_T & _io_resp_valid_T_1; // @[Decoupled.scala:51:35] assign io_resp_valid_0 = _io_resp_valid_T_2; // @[SinkD.scala:34:7, :62:36] wire _q_io_deq_ready_T = ~first; // @[Edges.scala:231:25] wire _q_io_deq_ready_T_1 = _q_io_deq_ready_T \| io_grant_safe_0; // @[SinkD.scala:34:7, :63:{34,41}] assign _q_io_deq_ready_T_2 = io_bs_adr_ready_0 & _q_io_deq_ready_T_1; // @[SinkD.scala:34:7, :63:{30,41}] wire _io_bs_adr_valid_T = ~first; // @[Edges.scala:231:25] wire _io_bs_adr_valid_T_1 = _d_q_io_deq_valid & io_grant_safe_0; // @[Decoupled.scala:362:21] assign _io_bs_adr_valid_T_2 = _io_bs_adr_valid_T \| _io_bs_adr_valid_T_1; // @[SinkD.scala:64:{22,29,41}] assign io_bs_adr_valid_0 = _io_bs_adr_valid_T_2; // @[SinkD.scala:34:7, :64:29] assign io_resp_bits_param_0 = {1'h0, _d_q_io_deq_bits_param}; // @[Decoupled.scala:362:21] wire _io_bs_adr_bits_noop_T = ~_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _io_bs_adr_bits_noop_T_1 = ~hasData; // @[Edges.scala:106:36] assign _io_bs_adr_bits_noop_T_2 = _io_bs_adr_bits_noop_T \| _io_bs_adr_bits_noop_T_1; // @[SinkD.scala:75:{26,35,38}] assign io_bs_adr_bits_noop_0 = _io_bs_adr_bits_noop_T_2; // @[SinkD.scala:34:7, :75:35] wire [3:0] _io_bs_adr_bits_beat_T = {1'h0, beat} + {3'h0, io_bs_adr_ready_0}; // @[Edges.scala:234:25] wire [2:0] _io_bs_adr_bits_beat_T_1 = _io_bs_adr_bits_beat_T[2:0]; // @[SinkD.scala:78:60] reg [2:0] io_bs_adr_bits_beat_r; // @[SinkD.scala:78:54] assign _io_bs_adr_bits_beat_T_2 = _d_q_io_deq_valid ? beat : io_bs_adr_bits_beat_r; // @[Decoupled.scala:362:21] assign io_bs_adr_bits_beat_0 = _io_bs_adr_bits_beat_T_2; // @[SinkD.scala:34:7, :78:29]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_208 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x	module OptimizationBarrier_TLBEntryData_208( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_118 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_50 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_51 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_52 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_53 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_54 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_55 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_56 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_57 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_58 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_59 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_60 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_61 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[42] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 connect _source_ok_WIRE[30], _source_ok_T_50 connect _source_ok_WIRE[31], _source_ok_T_51 connect _source_ok_WIRE[32], _source_ok_T_52 connect _source_ok_WIRE[33], _source_ok_T_53 connect _source_ok_WIRE[34], _source_ok_T_54 connect _source_ok_WIRE[35], _source_ok_T_55 connect _source_ok_WIRE[36], _source_ok_T_56 connect _source_ok_WIRE[37], _source_ok_T_57 connect _source_ok_WIRE[38], _source_ok_T_58 connect _source_ok_WIRE[39], _source_ok_T_59 connect _source_ok_WIRE[40], _source_ok_T_60 connect _source_ok_WIRE[41], _source_ok_T_61 node _source_ok_T_62 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[2]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[3]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[4]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[5]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[6]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[7]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[8]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[9]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[10]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[11]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[12]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[13]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[14]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[15]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[16]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[17]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[18]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[19]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[20]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[21]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[22]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[23]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[24]) node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[25]) node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[26]) node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[27]) node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[28]) node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[29]) node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[30]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE[31]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE[32]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE[33]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE[34]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE[35]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE[36]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE[37]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE[38]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE[39]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE[40]) node source_ok = or(_source_ok_T_101, _source_ok_WIRE[41]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_265 = eq(_T_264, UInt<1>(0h0)) node _T_266 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = or(_T_265, _T_270) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = or(_T_273, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_281 = eq(_T_280, UInt<1>(0h0)) node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<1>(0h0))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_289 = eq(_T_288, UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = or(_T_289, _T_294) node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_297 = eq(_T_296, UInt<1>(0h0)) node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = or(_T_297, _T_302) node _T_304 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_305 = eq(_T_304, UInt<1>(0h0)) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = or(_T_305, _T_310) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_313 = eq(_T_312, UInt<1>(0h0)) node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<1>(0h0))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = or(_T_313, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_321 = eq(_T_320, UInt<1>(0h0)) node _T_322 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_323 = cvt(_T_322) node _T_324 = and(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = asSInt(_T_324) node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0))) node _T_327 = or(_T_321, _T_326) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_329 = eq(_T_328, UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = or(_T_329, _T_334) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_337 = eq(_T_336, UInt<1>(0h0)) node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_337, _T_342) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = or(_T_345, _T_350) node _T_352 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_353 = eq(_T_352, UInt<1>(0h0)) node _T_354 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_353, _T_358) node _T_360 = and(_T_11, _T_24) node _T_361 = and(_T_360, _T_37) node _T_362 = and(_T_361, _T_50) node _T_363 = and(_T_362, _T_63) node _T_364 = and(_T_363, _T_71) node _T_365 = and(_T_364, _T_79) node _T_366 = and(_T_365, _T_87) node _T_367 = and(_T_366, _T_95) node _T_368 = and(_T_367, _T_103) node _T_369 = and(_T_368, _T_111) node _T_370 = and(_T_369, _T_119) node _T_371 = and(_T_370, _T_127) node _T_372 = and(_T_371, _T_135) node _T_373 = and(_T_372, _T_143) node _T_374 = and(_T_373, _T_151) node _T_375 = and(_T_374, _T_159) node _T_376 = and(_T_375, _T_167) node _T_377 = and(_T_376, _T_175) node _T_378 = and(_T_377, _T_183) node _T_379 = and(_T_378, _T_191) node _T_380 = and(_T_379, _T_199) node _T_381 = and(_T_380, _T_207) node _T_382 = and(_T_381, _T_215) node _T_383 = and(_T_382, _T_223) node _T_384 = and(_T_383, _T_231) node _T_385 = and(_T_384, _T_239) node _T_386 = and(_T_385, _T_247) node _T_387 = and(_T_386, _T_255) node _T_388 = and(_T_387, _T_263) node _T_389 = and(_T_388, _T_271) node _T_390 = and(_T_389, _T_279) node _T_391 = and(_T_390, _T_287) node _T_392 = and(_T_391, _T_295) node _T_393 = and(_T_392, _T_303) node _T_394 = and(_T_393, _T_311) node _T_395 = and(_T_394, _T_319) node _T_396 = and(_T_395, _T_327) node _T_397 = and(_T_396, _T_335) node _T_398 = and(_T_397, _T_343) node _T_399 = and(_T_398, _T_351) node _T_400 = and(_T_399, _T_359) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_400, UInt<1>(0h1), "") : assert_1 node _T_404 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_404 : node _T_405 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_406 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_407 = and(_T_405, _T_406) node _T_408 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_409 = shr(io.in.a.bits.source, 2) node _T_410 = eq(_T_409, UInt<1>(0h0)) node _T_411 = leq(UInt<1>(0h0), uncommonBits_4) node _T_412 = and(_T_410, _T_411) node _T_413 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_414 = and(_T_412, _T_413) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h1)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_5) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<2>(0h2)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_6) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h3)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_7) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _T_433 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_434 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_441 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_442 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_444 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_449 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_450 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_453 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_454 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_457 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_458 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_459 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_469 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_470 = or(_T_408, _T_414) node _T_471 = or(_T_470, _T_420) node _T_472 = or(_T_471, _T_426) node _T_473 = or(_T_472, _T_432) node _T_474 = or(_T_473, _T_433) node _T_475 = or(_T_474, _T_434) node _T_476 = or(_T_475, _T_435) node _T_477 = or(_T_476, _T_436) node _T_478 = or(_T_477, _T_437) node _T_479 = or(_T_478, _T_438) node _T_480 = or(_T_479, _T_439) node _T_481 = or(_T_480, _T_440) node _T_482 = or(_T_481, _T_441) node _T_483 = or(_T_482, _T_442) node _T_484 = or(_T_483, _T_443) node _T_485 = or(_T_484, _T_444) node _T_486 = or(_T_485, _T_445) node _T_487 = or(_T_486, _T_446) node _T_488 = or(_T_487, _T_447) node _T_489 = or(_T_488, _T_448) node _T_490 = or(_T_489, _T_449) node _T_491 = or(_T_490, _T_450) node _T_492 = or(_T_491, _T_451) node _T_493 = or(_T_492, _T_452) node _T_494 = or(_T_493, _T_453) node _T_495 = or(_T_494, _T_454) node _T_496 = or(_T_495, _T_455) node _T_497 = or(_T_496, _T_456) node _T_498 = or(_T_497, _T_457) node _T_499 = or(_T_498, _T_458) node _T_500 = or(_T_499, _T_459) node _T_501 = or(_T_500, _T_460) node _T_502 = or(_T_501, _T_461) node _T_503 = or(_T_502, _T_462) node _T_504 = or(_T_503, _T_463) node _T_505 = or(_T_504, _T_464) node _T_506 = or(_T_505, _T_465) node _T_507 = or(_T_506, _T_466) node _T_508 = or(_T_507, _T_467) node _T_509 = or(_T_508, _T_468) node _T_510 = or(_T_509, _T_469) node _T_511 = and(_T_407, _T_510) node _T_512 = or(UInt<1>(0h0), _T_511) node _T_513 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_514 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<13>(0h1000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = and(_T_513, _T_518) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = and(_T_512, _T_520) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_521, UInt<1>(0h1), "") : assert_2 node _T_525 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_526 = shr(io.in.a.bits.source, 2) node _T_527 = eq(_T_526, UInt<1>(0h0)) node _T_528 = leq(UInt<1>(0h0), uncommonBits_8) node _T_529 = and(_T_527, _T_528) node _T_530 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_531 = and(_T_529, _T_530) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_532 = shr(io.in.a.bits.source, 2) node _T_533 = eq(_T_532, UInt<1>(0h1)) node _T_534 = leq(UInt<1>(0h0), uncommonBits_9) node _T_535 = and(_T_533, _T_534) node _T_536 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<2>(0h2)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_10) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_543 = and(_T_541, _T_542) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_544 = shr(io.in.a.bits.source, 2) node _T_545 = eq(_T_544, UInt<2>(0h3)) node _T_546 = leq(UInt<1>(0h0), uncommonBits_11) node _T_547 = and(_T_545, _T_546) node _T_548 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_549 = and(_T_547, _T_548) node _T_550 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_553 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_554 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_555 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_556 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_557 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_559 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_560 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_561 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_562 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_564 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_565 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_566 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_569 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_570 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_571 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_572 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_573 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_574 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_576 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_577 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_578 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_579 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_580 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_581 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_582 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_583 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_584 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_585 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_586 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[42] connect _WIRE[0], _T_525 connect _WIRE[1], _T_531 connect _WIRE[2], _T_537 connect _WIRE[3], _T_543 connect _WIRE[4], _T_549 connect _WIRE[5], _T_550 connect _WIRE[6], _T_551 connect _WIRE[7], _T_552 connect _WIRE[8], _T_553 connect _WIRE[9], _T_554 connect _WIRE[10], _T_555 connect _WIRE[11], _T_556 connect _WIRE[12], _T_557 connect _WIRE[13], _T_558 connect _WIRE[14], _T_559 connect _WIRE[15], _T_560 connect _WIRE[16], _T_561 connect _WIRE[17], _T_562 connect _WIRE[18], _T_563 connect _WIRE[19], _T_564 connect _WIRE[20], _T_565 connect _WIRE[21], _T_566 connect _WIRE[22], _T_567 connect _WIRE[23], _T_568 connect _WIRE[24], _T_569 connect _WIRE[25], _T_570 connect _WIRE[26], _T_571 connect _WIRE[27], _T_572 connect _WIRE[28], _T_573 connect _WIRE[29], _T_574 connect _WIRE[30], _T_575 connect _WIRE[31], _T_576 connect _WIRE[32], _T_577 connect _WIRE[33], _T_578 connect _WIRE[34], _T_579 connect _WIRE[35], _T_580 connect _WIRE[36], _T_581 connect _WIRE[37], _T_582 connect _WIRE[38], _T_583 connect _WIRE[39], _T_584 connect _WIRE[40], _T_585 connect _WIRE[41], _T_586 node _T_587 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_588 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_589 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_590 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_591 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_592 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_593 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_594 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_595 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_596 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_597 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_598 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_599 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_600 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_601 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_602 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_603 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_604 = mux(_WIRE[5], _T_587, UInt<1>(0h0)) node _T_605 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_606 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_607 = mux(_WIRE[8], _T_588, UInt<1>(0h0)) node _T_608 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_609 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_610 = mux(_WIRE[11], _T_589, UInt<1>(0h0)) node _T_611 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_612 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = mux(_WIRE[14], _T_590, UInt<1>(0h0)) node _T_614 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_615 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = mux(_WIRE[17], _T_591, UInt<1>(0h0)) node _T_617 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_618 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_619 = mux(_WIRE[20], _T_592, UInt<1>(0h0)) node _T_620 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_621 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_622 = mux(_WIRE[23], _T_593, UInt<1>(0h0)) node _T_623 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_624 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_625 = mux(_WIRE[26], _T_594, UInt<1>(0h0)) node _T_626 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_627 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_628 = mux(_WIRE[29], _T_595, UInt<1>(0h0)) node _T_629 = mux(_WIRE[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_630 = mux(_WIRE[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_631 = mux(_WIRE[32], _T_596, UInt<1>(0h0)) node _T_632 = mux(_WIRE[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_633 = mux(_WIRE[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_634 = mux(_WIRE[35], _T_597, UInt<1>(0h0)) node _T_635 = mux(_WIRE[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_636 = mux(_WIRE[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = mux(_WIRE[38], _T_598, UInt<1>(0h0)) node _T_638 = mux(_WIRE[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_639 = mux(_WIRE[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_640 = mux(_WIRE[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_641 = or(_T_599, _T_600) node _T_642 = or(_T_641, _T_601) node _T_643 = or(_T_642, _T_602) node _T_644 = or(_T_643, _T_603) node _T_645 = or(_T_644, _T_604) node _T_646 = or(_T_645, _T_605) node _T_647 = or(_T_646, _T_606) node _T_648 = or(_T_647, _T_607) node _T_649 = or(_T_648, _T_608) node _T_650 = or(_T_649, _T_609) node _T_651 = or(_T_650, _T_610) node _T_652 = or(_T_651, _T_611) node _T_653 = or(_T_652, _T_612) node _T_654 = or(_T_653, _T_613) node _T_655 = or(_T_654, _T_614) node _T_656 = or(_T_655, _T_615) node _T_657 = or(_T_656, _T_616) node _T_658 = or(_T_657, _T_617) node _T_659 = or(_T_658, _T_618) node _T_660 = or(_T_659, _T_619) node _T_661 = or(_T_660, _T_620) node _T_662 = or(_T_661, _T_621) node _T_663 = or(_T_662, _T_622) node _T_664 = or(_T_663, _T_623) node _T_665 = or(_T_664, _T_624) node _T_666 = or(_T_665, _T_625) node _T_667 = or(_T_666, _T_626) node _T_668 = or(_T_667, _T_627) node _T_669 = or(_T_668, _T_628) node _T_670 = or(_T_669, _T_629) node _T_671 = or(_T_670, _T_630) node _T_672 = or(_T_671, _T_631) node _T_673 = or(_T_672, _T_632) node _T_674 = or(_T_673, _T_633) node _T_675 = or(_T_674, _T_634) node _T_676 = or(_T_675, _T_635) node _T_677 = or(_T_676, _T_636) node _T_678 = or(_T_677, _T_637) node _T_679 = or(_T_678, _T_638) node _T_680 = or(_T_679, _T_639) node _T_681 = or(_T_680, _T_640) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_681 node _T_682 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_683 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_684 = and(_T_682, _T_683) node _T_685 = or(UInt<1>(0h0), _T_684) node _T_686 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = and(_T_685, _T_690) node _T_692 = or(UInt<1>(0h0), _T_691) node _T_693 = and(_WIRE_1, _T_692) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_693, UInt<1>(0h1), "") : assert_3 node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(source_ok, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_700 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_700, UInt<1>(0h1), "") : assert_5 node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(is_aligned, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_707 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_707, UInt<1>(0h1), "") : assert_7 node _T_711 = not(io.in.a.bits.mask) node _T_712 = eq(_T_711, UInt<1>(0h0)) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_712, UInt<1>(0h1), "") : assert_8 node _T_716 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(_T_716, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_716, UInt<1>(0h1), "") : assert_9 node _T_720 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_720 : node _T_721 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_722 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_723 = and(_T_721, _T_722) node _T_724 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_725 = shr(io.in.a.bits.source, 2) node _T_726 = eq(_T_725, UInt<1>(0h0)) node _T_727 = leq(UInt<1>(0h0), uncommonBits_12) node _T_728 = and(_T_726, _T_727) node _T_729 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_730 = and(_T_728, _T_729) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_731 = shr(io.in.a.bits.source, 2) node _T_732 = eq(_T_731, UInt<1>(0h1)) node _T_733 = leq(UInt<1>(0h0), uncommonBits_13) node _T_734 = and(_T_732, _T_733) node _T_735 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_736 = and(_T_734, _T_735) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<2>(0h2)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_14) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<2>(0h3)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_15) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_750 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_751 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_752 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_754 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_755 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_756 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_757 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_758 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_759 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_760 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_761 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_762 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_763 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_767 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_769 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_770 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_771 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_772 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_776 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_777 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_784 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_785 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_786 = or(_T_724, _T_730) node _T_787 = or(_T_786, _T_736) node _T_788 = or(_T_787, _T_742) node _T_789 = or(_T_788, _T_748) node _T_790 = or(_T_789, _T_749) node _T_791 = or(_T_790, _T_750) node _T_792 = or(_T_791, _T_751) node _T_793 = or(_T_792, _T_752) node _T_794 = or(_T_793, _T_753) node _T_795 = or(_T_794, _T_754) node _T_796 = or(_T_795, _T_755) node _T_797 = or(_T_796, _T_756) node _T_798 = or(_T_797, _T_757) node _T_799 = or(_T_798, _T_758) node _T_800 = or(_T_799, _T_759) node _T_801 = or(_T_800, _T_760) node _T_802 = or(_T_801, _T_761) node _T_803 = or(_T_802, _T_762) node _T_804 = or(_T_803, _T_763) node _T_805 = or(_T_804, _T_764) node _T_806 = or(_T_805, _T_765) node _T_807 = or(_T_806, _T_766) node _T_808 = or(_T_807, _T_767) node _T_809 = or(_T_808, _T_768) node _T_810 = or(_T_809, _T_769) node _T_811 = or(_T_810, _T_770) node _T_812 = or(_T_811, _T_771) node _T_813 = or(_T_812, _T_772) node _T_814 = or(_T_813, _T_773) node _T_815 = or(_T_814, _T_774) node _T_816 = or(_T_815, _T_775) node _T_817 = or(_T_816, _T_776) node _T_818 = or(_T_817, _T_777) node _T_819 = or(_T_818, _T_778) node _T_820 = or(_T_819, _T_779) node _T_821 = or(_T_820, _T_780) node _T_822 = or(_T_821, _T_781) node _T_823 = or(_T_822, _T_782) node _T_824 = or(_T_823, _T_783) node _T_825 = or(_T_824, _T_784) node _T_826 = or(_T_825, _T_785) node _T_827 = and(_T_723, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_830 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_831 = cvt(_T_830) node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000))) node _T_833 = asSInt(_T_832) node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0))) node _T_835 = and(_T_829, _T_834) node _T_836 = or(UInt<1>(0h0), _T_835) node _T_837 = and(_T_828, _T_836) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_837, UInt<1>(0h1), "") : assert_10 node _T_841 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_842 = shr(io.in.a.bits.source, 2) node _T_843 = eq(_T_842, UInt<1>(0h0)) node _T_844 = leq(UInt<1>(0h0), uncommonBits_16) node _T_845 = and(_T_843, _T_844) node _T_846 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_847 = and(_T_845, _T_846) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_848 = shr(io.in.a.bits.source, 2) node _T_849 = eq(_T_848, UInt<1>(0h1)) node _T_850 = leq(UInt<1>(0h0), uncommonBits_17) node _T_851 = and(_T_849, _T_850) node _T_852 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_853 = and(_T_851, _T_852) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_854 = shr(io.in.a.bits.source, 2) node _T_855 = eq(_T_854, UInt<2>(0h2)) node _T_856 = leq(UInt<1>(0h0), uncommonBits_18) node _T_857 = and(_T_855, _T_856) node _T_858 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_859 = and(_T_857, _T_858) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_860 = shr(io.in.a.bits.source, 2) node _T_861 = eq(_T_860, UInt<2>(0h3)) node _T_862 = leq(UInt<1>(0h0), uncommonBits_19) node _T_863 = and(_T_861, _T_862) node _T_864 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_865 = and(_T_863, _T_864) node _T_866 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_867 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_868 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_869 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_871 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_872 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_873 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_874 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_875 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_876 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_877 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_878 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_879 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_881 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_882 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_883 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_884 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_885 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_886 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_887 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_888 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_889 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_890 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_891 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_892 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_893 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_894 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_895 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_896 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_897 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_898 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_899 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_900 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_901 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_902 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[42] connect _WIRE_2[0], _T_841 connect _WIRE_2[1], _T_847 connect _WIRE_2[2], _T_853 connect _WIRE_2[3], _T_859 connect _WIRE_2[4], _T_865 connect _WIRE_2[5], _T_866 connect _WIRE_2[6], _T_867 connect _WIRE_2[7], _T_868 connect _WIRE_2[8], _T_869 connect _WIRE_2[9], _T_870 connect _WIRE_2[10], _T_871 connect _WIRE_2[11], _T_872 connect _WIRE_2[12], _T_873 connect _WIRE_2[13], _T_874 connect _WIRE_2[14], _T_875 connect _WIRE_2[15], _T_876 connect _WIRE_2[16], _T_877 connect _WIRE_2[17], _T_878 connect _WIRE_2[18], _T_879 connect _WIRE_2[19], _T_880 connect _WIRE_2[20], _T_881 connect _WIRE_2[21], _T_882 connect _WIRE_2[22], _T_883 connect _WIRE_2[23], _T_884 connect _WIRE_2[24], _T_885 connect _WIRE_2[25], _T_886 connect _WIRE_2[26], _T_887 connect _WIRE_2[27], _T_888 connect _WIRE_2[28], _T_889 connect _WIRE_2[29], _T_890 connect _WIRE_2[30], _T_891 connect _WIRE_2[31], _T_892 connect _WIRE_2[32], _T_893 connect _WIRE_2[33], _T_894 connect _WIRE_2[34], _T_895 connect _WIRE_2[35], _T_896 connect _WIRE_2[36], _T_897 connect _WIRE_2[37], _T_898 connect _WIRE_2[38], _T_899 connect _WIRE_2[39], _T_900 connect _WIRE_2[40], _T_901 connect _WIRE_2[41], _T_902 node _T_903 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_904 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_905 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_906 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_907 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_908 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_909 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_910 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_911 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_912 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_913 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_914 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_915 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_916 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_919 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_920 = mux(_WIRE_2[5], _T_903, UInt<1>(0h0)) node _T_921 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_922 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_923 = mux(_WIRE_2[8], _T_904, UInt<1>(0h0)) node _T_924 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_925 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_926 = mux(_WIRE_2[11], _T_905, UInt<1>(0h0)) node _T_927 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_928 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_929 = mux(_WIRE_2[14], _T_906, UInt<1>(0h0)) node _T_930 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_931 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_932 = mux(_WIRE_2[17], _T_907, UInt<1>(0h0)) node _T_933 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_934 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_935 = mux(_WIRE_2[20], _T_908, UInt<1>(0h0)) node _T_936 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_937 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_938 = mux(_WIRE_2[23], _T_909, UInt<1>(0h0)) node _T_939 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_940 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_941 = mux(_WIRE_2[26], _T_910, UInt<1>(0h0)) node _T_942 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_943 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_944 = mux(_WIRE_2[29], _T_911, UInt<1>(0h0)) node _T_945 = mux(_WIRE_2[30], UInt<1>(0h0), UInt<1>(0h0)) node _T_946 = mux(_WIRE_2[31], UInt<1>(0h0), UInt<1>(0h0)) node _T_947 = mux(_WIRE_2[32], _T_912, UInt<1>(0h0)) node _T_948 = mux(_WIRE_2[33], UInt<1>(0h0), UInt<1>(0h0)) node _T_949 = mux(_WIRE_2[34], UInt<1>(0h0), UInt<1>(0h0)) node _T_950 = mux(_WIRE_2[35], _T_913, UInt<1>(0h0)) node _T_951 = mux(_WIRE_2[36], UInt<1>(0h0), UInt<1>(0h0)) node _T_952 = mux(_WIRE_2[37], UInt<1>(0h0), UInt<1>(0h0)) node _T_953 = mux(_WIRE_2[38], _T_914, UInt<1>(0h0)) node _T_954 = mux(_WIRE_2[39], UInt<1>(0h0), UInt<1>(0h0)) node _T_955 = mux(_WIRE_2[40], UInt<1>(0h0), UInt<1>(0h0)) node _T_956 = mux(_WIRE_2[41], UInt<1>(0h0), UInt<1>(0h0)) node _T_957 = or(_T_915, _T_916) node _T_958 = or(_T_957, _T_917) node _T_959 = or(_T_958, _T_918) node _T_960 = or(_T_959, _T_919) node _T_961 = or(_T_960, _T_920) node _T_962 = or(_T_961, _T_921) node _T_963 = or(_T_962, _T_922) node _T_964 = or(_T_963, _T_923) node _T_965 = or(_T_964, _T_924) node _T_966 = or(_T_965, _T_925) node _T_967 = or(_T_966, _T_926) node _T_968 = or(_T_967, _T_927) node _T_969 = or(_T_968, _T_928) node _T_970 = or(_T_969, _T_929) node _T_971 = or(_T_970, _T_930) node _T_972 = or(_T_971, _T_931) node _T_973 = or(_T_972, _T_932) node _T_974 = or(_T_973, _T_933) node _T_975 = or(_T_974, _T_934) node _T_976 = or(_T_975, _T_935) node _T_977 = or(_T_976, _T_936) node _T_978 = or(_T_977, _T_937) node _T_979 = or(_T_978, _T_938) node _T_980 = or(_T_979, _T_939) node _T_981 = or(_T_980, _T_940) node _T_982 = or(_T_981, _T_941) node _T_983 = or(_T_982, _T_942) node _T_984 = or(_T_983, _T_943) node _T_985 = or(_T_984, _T_944) node _T_986 = or(_T_985, _T_945) node _T_987 = or(_T_986, _T_946) node _T_988 = or(_T_987, _T_947) node _T_989 = or(_T_988, _T_948) node _T_990 = or(_T_989, _T_949) node _T_991 = or(_T_990, _T_950) node _T_992 = or(_T_991, _T_951) node _T_993 = or(_T_992, _T_952) node _T_994 = or(_T_993, _T_953) node _T_995 = or(_T_994, _T_954) node _T_996 = or(_T_995, _T_955) node _T_997 = or(_T_996, _T_956) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_997 node _T_998 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_999 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = or(UInt<1>(0h0), _T_1000) node _T_1002 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<13>(0h1000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = and(_T_1001, _T_1006) node _T_1008 = or(UInt<1>(0h0), _T_1007) node _T_1009 = and(_WIRE_3, _T_1008) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_11 node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(source_ok, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_1016 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_13 node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(is_aligned, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_1023 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_15 node _T_1027 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_16 node _T_1031 = not(io.in.a.bits.mask) node _T_1032 = eq(_T_1031, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_17 node _T_1036 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_18 node _T_1040 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_1040 : node _T_1041 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1042 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1043 = and(_T_1041, _T_1042) node _T_1044 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_1045 = shr(io.in.a.bits.source, 2) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) node _T_1047 = leq(UInt<1>(0h0), uncommonBits_20) node _T_1048 = and(_T_1046, _T_1047) node _T_1049 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_1050 = and(_T_1048, _T_1049) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_1051 = shr(io.in.a.bits.source, 2) node _T_1052 = eq(_T_1051, UInt<1>(0h1)) node _T_1053 = leq(UInt<1>(0h0), uncommonBits_21) node _T_1054 = and(_T_1052, _T_1053) node _T_1055 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_1056 = and(_T_1054, _T_1055) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_1057 = shr(io.in.a.bits.source, 2) node _T_1058 = eq(_T_1057, UInt<2>(0h2)) node _T_1059 = leq(UInt<1>(0h0), uncommonBits_22) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_1062 = and(_T_1060, _T_1061) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_1063 = shr(io.in.a.bits.source, 2) node _T_1064 = eq(_T_1063, UInt<2>(0h3)) node _T_1065 = leq(UInt<1>(0h0), uncommonBits_23) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_1068 = and(_T_1066, _T_1067) node _T_1069 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1070 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1071 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1072 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1073 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1074 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1075 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1076 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1077 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1078 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1079 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1080 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1081 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1082 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1083 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1084 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1085 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1086 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1089 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1090 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1091 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1092 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1093 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1094 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1095 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1096 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1097 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1098 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1099 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1100 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1102 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1105 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1106 = or(_T_1044, _T_1050) node _T_1107 = or(_T_1106, _T_1056) node _T_1108 = or(_T_1107, _T_1062) node _T_1109 = or(_T_1108, _T_1068) node _T_1110 = or(_T_1109, _T_1069) node _T_1111 = or(_T_1110, _T_1070) node _T_1112 = or(_T_1111, _T_1071) node _T_1113 = or(_T_1112, _T_1072) node _T_1114 = or(_T_1113, _T_1073) node _T_1115 = or(_T_1114, _T_1074) node _T_1116 = or(_T_1115, _T_1075) node _T_1117 = or(_T_1116, _T_1076) node _T_1118 = or(_T_1117, _T_1077) node _T_1119 = or(_T_1118, _T_1078) node _T_1120 = or(_T_1119, _T_1079) node _T_1121 = or(_T_1120, _T_1080) node _T_1122 = or(_T_1121, _T_1081) node _T_1123 = or(_T_1122, _T_1082) node _T_1124 = or(_T_1123, _T_1083) node _T_1125 = or(_T_1124, _T_1084) node _T_1126 = or(_T_1125, _T_1085) node _T_1127 = or(_T_1126, _T_1086) node _T_1128 = or(_T_1127, _T_1087) node _T_1129 = or(_T_1128, _T_1088) node _T_1130 = or(_T_1129, _T_1089) node _T_1131 = or(_T_1130, _T_1090) node _T_1132 = or(_T_1131, _T_1091) node _T_1133 = or(_T_1132, _T_1092) node _T_1134 = or(_T_1133, _T_1093) node _T_1135 = or(_T_1134, _T_1094) node _T_1136 = or(_T_1135, _T_1095) node _T_1137 = or(_T_1136, _T_1096) node _T_1138 = or(_T_1137, _T_1097) node _T_1139 = or(_T_1138, _T_1098) node _T_1140 = or(_T_1139, _T_1099) node _T_1141 = or(_T_1140, _T_1100) node _T_1142 = or(_T_1141, _T_1101) node _T_1143 = or(_T_1142, _T_1102) node _T_1144 = or(_T_1143, _T_1103) node _T_1145 = or(_T_1144, _T_1104) node _T_1146 = or(_T_1145, _T_1105) node _T_1147 = and(_T_1043, _T_1146) node _T_1148 = or(UInt<1>(0h0), _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_19 node _T_1152 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1153 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1154 = and(_T_1152, _T_1153) node _T_1155 = or(UInt<1>(0h0), _T_1154) node _T_1156 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1157 = cvt(_T_1156) node _T_1158 = and(_T_1157, asSInt(UInt<13>(0h1000))) node _T_1159 = asSInt(_T_1158) node _T_1160 = eq(_T_1159, asSInt(UInt<1>(0h0))) node _T_1161 = and(_T_1155, _T_1160) node _T_1162 = or(UInt<1>(0h0), _T_1161) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_20 node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(source_ok, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(is_aligned, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_1172 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_23 node _T_1176 = eq(io.in.a.bits.mask, mask) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_24 node _T_1180 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_25 node _T_1184 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_1184 : node _T_1185 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1186 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1187 = and(_T_1185, _T_1186) node _T_1188 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_1189 = shr(io.in.a.bits.source, 2) node _T_1190 = eq(_T_1189, UInt<1>(0h0)) node _T_1191 = leq(UInt<1>(0h0), uncommonBits_24) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_1194 = and(_T_1192, _T_1193) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_1195 = shr(io.in.a.bits.source, 2) node _T_1196 = eq(_T_1195, UInt<1>(0h1)) node _T_1197 = leq(UInt<1>(0h0), uncommonBits_25) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_1200 = and(_T_1198, _T_1199) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_1201 = shr(io.in.a.bits.source, 2) node _T_1202 = eq(_T_1201, UInt<2>(0h2)) node _T_1203 = leq(UInt<1>(0h0), uncommonBits_26) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_1206 = and(_T_1204, _T_1205) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_1207 = shr(io.in.a.bits.source, 2) node _T_1208 = eq(_T_1207, UInt<2>(0h3)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_27) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1214 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1215 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1216 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1217 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1218 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1219 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1220 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1221 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1222 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1223 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1224 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1225 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1226 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1227 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1228 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1229 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1234 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1235 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1236 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1237 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1238 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1241 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1243 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1244 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1249 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1250 = or(_T_1188, _T_1194) node _T_1251 = or(_T_1250, _T_1200) node _T_1252 = or(_T_1251, _T_1206) node _T_1253 = or(_T_1252, _T_1212) node _T_1254 = or(_T_1253, _T_1213) node _T_1255 = or(_T_1254, _T_1214) node _T_1256 = or(_T_1255, _T_1215) node _T_1257 = or(_T_1256, _T_1216) node _T_1258 = or(_T_1257, _T_1217) node _T_1259 = or(_T_1258, _T_1218) node _T_1260 = or(_T_1259, _T_1219) node _T_1261 = or(_T_1260, _T_1220) node _T_1262 = or(_T_1261, _T_1221) node _T_1263 = or(_T_1262, _T_1222) node _T_1264 = or(_T_1263, _T_1223) node _T_1265 = or(_T_1264, _T_1224) node _T_1266 = or(_T_1265, _T_1225) node _T_1267 = or(_T_1266, _T_1226) node _T_1268 = or(_T_1267, _T_1227) node _T_1269 = or(_T_1268, _T_1228) node _T_1270 = or(_T_1269, _T_1229) node _T_1271 = or(_T_1270, _T_1230) node _T_1272 = or(_T_1271, _T_1231) node _T_1273 = or(_T_1272, _T_1232) node _T_1274 = or(_T_1273, _T_1233) node _T_1275 = or(_T_1274, _T_1234) node _T_1276 = or(_T_1275, _T_1235) node _T_1277 = or(_T_1276, _T_1236) node _T_1278 = or(_T_1277, _T_1237) node _T_1279 = or(_T_1278, _T_1238) node _T_1280 = or(_T_1279, _T_1239) node _T_1281 = or(_T_1280, _T_1240) node _T_1282 = or(_T_1281, _T_1241) node _T_1283 = or(_T_1282, _T_1242) node _T_1284 = or(_T_1283, _T_1243) node _T_1285 = or(_T_1284, _T_1244) node _T_1286 = or(_T_1285, _T_1245) node _T_1287 = or(_T_1286, _T_1246) node _T_1288 = or(_T_1287, _T_1247) node _T_1289 = or(_T_1288, _T_1248) node _T_1290 = or(_T_1289, _T_1249) node _T_1291 = and(_T_1187, _T_1290) node _T_1292 = or(UInt<1>(0h0), _T_1291) node _T_1293 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1294 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1295 = and(_T_1293, _T_1294) node _T_1296 = or(UInt<1>(0h0), _T_1295) node _T_1297 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1298 = cvt(_T_1297) node _T_1299 = and(_T_1298, asSInt(UInt<13>(0h1000))) node _T_1300 = asSInt(_T_1299) node _T_1301 = eq(_T_1300, asSInt(UInt<1>(0h0))) node _T_1302 = and(_T_1296, _T_1301) node _T_1303 = or(UInt<1>(0h0), _T_1302) node _T_1304 = and(_T_1292, _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_26 node _T_1308 = asUInt(reset) node _T_1309 = eq(_T_1308, UInt<1>(0h0)) when _T_1309 : node _T_1310 = eq(source_ok, UInt<1>(0h0)) when _T_1310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(is_aligned, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1314 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_29 node _T_1318 = eq(io.in.a.bits.mask, mask) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_30 node _T_1322 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1322 : node _T_1323 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1324 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1325 = and(_T_1323, _T_1324) node _T_1326 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1327 = shr(io.in.a.bits.source, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) node _T_1329 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1332 = and(_T_1330, _T_1331) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1333 = shr(io.in.a.bits.source, 2) node _T_1334 = eq(_T_1333, UInt<1>(0h1)) node _T_1335 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1336 = and(_T_1334, _T_1335) node _T_1337 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1338 = and(_T_1336, _T_1337) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1339 = shr(io.in.a.bits.source, 2) node _T_1340 = eq(_T_1339, UInt<2>(0h2)) node _T_1341 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1342 = and(_T_1340, _T_1341) node _T_1343 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1344 = and(_T_1342, _T_1343) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1345 = shr(io.in.a.bits.source, 2) node _T_1346 = eq(_T_1345, UInt<2>(0h3)) node _T_1347 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1348 = and(_T_1346, _T_1347) node _T_1349 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1350 = and(_T_1348, _T_1349) node _T_1351 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1352 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1353 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1354 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1356 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1357 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1358 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1359 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1360 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1361 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1362 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1363 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1364 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1365 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1366 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1367 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1368 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1369 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1370 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1371 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1372 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1373 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1374 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1375 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1376 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1377 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1378 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1379 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1380 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1381 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1382 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1383 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1384 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1385 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1386 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1387 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1388 = or(_T_1326, _T_1332) node _T_1389 = or(_T_1388, _T_1338) node _T_1390 = or(_T_1389, _T_1344) node _T_1391 = or(_T_1390, _T_1350) node _T_1392 = or(_T_1391, _T_1351) node _T_1393 = or(_T_1392, _T_1352) node _T_1394 = or(_T_1393, _T_1353) node _T_1395 = or(_T_1394, _T_1354) node _T_1396 = or(_T_1395, _T_1355) node _T_1397 = or(_T_1396, _T_1356) node _T_1398 = or(_T_1397, _T_1357) node _T_1399 = or(_T_1398, _T_1358) node _T_1400 = or(_T_1399, _T_1359) node _T_1401 = or(_T_1400, _T_1360) node _T_1402 = or(_T_1401, _T_1361) node _T_1403 = or(_T_1402, _T_1362) node _T_1404 = or(_T_1403, _T_1363) node _T_1405 = or(_T_1404, _T_1364) node _T_1406 = or(_T_1405, _T_1365) node _T_1407 = or(_T_1406, _T_1366) node _T_1408 = or(_T_1407, _T_1367) node _T_1409 = or(_T_1408, _T_1368) node _T_1410 = or(_T_1409, _T_1369) node _T_1411 = or(_T_1410, _T_1370) node _T_1412 = or(_T_1411, _T_1371) node _T_1413 = or(_T_1412, _T_1372) node _T_1414 = or(_T_1413, _T_1373) node _T_1415 = or(_T_1414, _T_1374) node _T_1416 = or(_T_1415, _T_1375) node _T_1417 = or(_T_1416, _T_1376) node _T_1418 = or(_T_1417, _T_1377) node _T_1419 = or(_T_1418, _T_1378) node _T_1420 = or(_T_1419, _T_1379) node _T_1421 = or(_T_1420, _T_1380) node _T_1422 = or(_T_1421, _T_1381) node _T_1423 = or(_T_1422, _T_1382) node _T_1424 = or(_T_1423, _T_1383) node _T_1425 = or(_T_1424, _T_1384) node _T_1426 = or(_T_1425, _T_1385) node _T_1427 = or(_T_1426, _T_1386) node _T_1428 = or(_T_1427, _T_1387) node _T_1429 = and(_T_1325, _T_1428) node _T_1430 = or(UInt<1>(0h0), _T_1429) node _T_1431 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1432 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1433 = and(_T_1431, _T_1432) node _T_1434 = or(UInt<1>(0h0), _T_1433) node _T_1435 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1436 = cvt(_T_1435) node _T_1437 = and(_T_1436, asSInt(UInt<13>(0h1000))) node _T_1438 = asSInt(_T_1437) node _T_1439 = eq(_T_1438, asSInt(UInt<1>(0h0))) node _T_1440 = and(_T_1434, _T_1439) node _T_1441 = or(UInt<1>(0h0), _T_1440) node _T_1442 = and(_T_1430, _T_1441) node _T_1443 = asUInt(reset) node _T_1444 = eq(_T_1443, UInt<1>(0h0)) when _T_1444 : node _T_1445 = eq(_T_1442, UInt<1>(0h0)) when _T_1445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1442, UInt<1>(0h1), "") : assert_31 node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(source_ok, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(is_aligned, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1452 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_34 node _T_1456 = not(mask) node _T_1457 = and(io.in.a.bits.mask, _T_1456) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) node _T_1459 = asUInt(reset) node _T_1460 = eq(_T_1459, UInt<1>(0h0)) when _T_1460 : node _T_1461 = eq(_T_1458, UInt<1>(0h0)) when _T_1461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1458, UInt<1>(0h1), "") : assert_35 node _T_1462 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1462 : node _T_1463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1465 = and(_T_1463, _T_1464) node _T_1466 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1467 = shr(io.in.a.bits.source, 2) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) node _T_1469 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1470 = and(_T_1468, _T_1469) node _T_1471 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1472 = and(_T_1470, _T_1471) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1473 = shr(io.in.a.bits.source, 2) node _T_1474 = eq(_T_1473, UInt<1>(0h1)) node _T_1475 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1476 = and(_T_1474, _T_1475) node _T_1477 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1478 = and(_T_1476, _T_1477) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1479 = shr(io.in.a.bits.source, 2) node _T_1480 = eq(_T_1479, UInt<2>(0h2)) node _T_1481 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1482 = and(_T_1480, _T_1481) node _T_1483 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1484 = and(_T_1482, _T_1483) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1485 = shr(io.in.a.bits.source, 2) node _T_1486 = eq(_T_1485, UInt<2>(0h3)) node _T_1487 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1488 = and(_T_1486, _T_1487) node _T_1489 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1490 = and(_T_1488, _T_1489) node _T_1491 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1492 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1493 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1494 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1495 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1496 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1497 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1498 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1499 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1500 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1501 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1502 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1505 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1506 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1507 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1508 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1509 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1510 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1511 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1512 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1513 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1514 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1515 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1516 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1517 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1518 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1519 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1520 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1521 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1522 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1523 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1524 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1525 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1526 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1527 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1528 = or(_T_1466, _T_1472) node _T_1529 = or(_T_1528, _T_1478) node _T_1530 = or(_T_1529, _T_1484) node _T_1531 = or(_T_1530, _T_1490) node _T_1532 = or(_T_1531, _T_1491) node _T_1533 = or(_T_1532, _T_1492) node _T_1534 = or(_T_1533, _T_1493) node _T_1535 = or(_T_1534, _T_1494) node _T_1536 = or(_T_1535, _T_1495) node _T_1537 = or(_T_1536, _T_1496) node _T_1538 = or(_T_1537, _T_1497) node _T_1539 = or(_T_1538, _T_1498) node _T_1540 = or(_T_1539, _T_1499) node _T_1541 = or(_T_1540, _T_1500) node _T_1542 = or(_T_1541, _T_1501) node _T_1543 = or(_T_1542, _T_1502) node _T_1544 = or(_T_1543, _T_1503) node _T_1545 = or(_T_1544, _T_1504) node _T_1546 = or(_T_1545, _T_1505) node _T_1547 = or(_T_1546, _T_1506) node _T_1548 = or(_T_1547, _T_1507) node _T_1549 = or(_T_1548, _T_1508) node _T_1550 = or(_T_1549, _T_1509) node _T_1551 = or(_T_1550, _T_1510) node _T_1552 = or(_T_1551, _T_1511) node _T_1553 = or(_T_1552, _T_1512) node _T_1554 = or(_T_1553, _T_1513) node _T_1555 = or(_T_1554, _T_1514) node _T_1556 = or(_T_1555, _T_1515) node _T_1557 = or(_T_1556, _T_1516) node _T_1558 = or(_T_1557, _T_1517) node _T_1559 = or(_T_1558, _T_1518) node _T_1560 = or(_T_1559, _T_1519) node _T_1561 = or(_T_1560, _T_1520) node _T_1562 = or(_T_1561, _T_1521) node _T_1563 = or(_T_1562, _T_1522) node _T_1564 = or(_T_1563, _T_1523) node _T_1565 = or(_T_1564, _T_1524) node _T_1566 = or(_T_1565, _T_1525) node _T_1567 = or(_T_1566, _T_1526) node _T_1568 = or(_T_1567, _T_1527) node _T_1569 = and(_T_1465, _T_1568) node _T_1570 = or(UInt<1>(0h0), _T_1569) node _T_1571 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1572 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1573 = cvt(_T_1572) node _T_1574 = and(_T_1573, asSInt(UInt<13>(0h1000))) node _T_1575 = asSInt(_T_1574) node _T_1576 = eq(_T_1575, asSInt(UInt<1>(0h0))) node _T_1577 = and(_T_1571, _T_1576) node _T_1578 = or(UInt<1>(0h0), _T_1577) node _T_1579 = and(_T_1570, _T_1578) node _T_1580 = asUInt(reset) node _T_1581 = eq(_T_1580, UInt<1>(0h0)) when _T_1581 : node _T_1582 = eq(_T_1579, UInt<1>(0h0)) when _T_1582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1579, UInt<1>(0h1), "") : assert_36 node _T_1583 = asUInt(reset) node _T_1584 = eq(_T_1583, UInt<1>(0h0)) when _T_1584 : node _T_1585 = eq(source_ok, UInt<1>(0h0)) when _T_1585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(is_aligned, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1589 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_39 node _T_1593 = eq(io.in.a.bits.mask, mask) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_40 node _T_1597 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1597 : node _T_1598 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1599 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1600 = and(_T_1598, _T_1599) node _T_1601 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1602 = shr(io.in.a.bits.source, 2) node _T_1603 = eq(_T_1602, UInt<1>(0h0)) node _T_1604 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1605 = and(_T_1603, _T_1604) node _T_1606 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1607 = and(_T_1605, _T_1606) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1608 = shr(io.in.a.bits.source, 2) node _T_1609 = eq(_T_1608, UInt<1>(0h1)) node _T_1610 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1613 = and(_T_1611, _T_1612) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1614 = shr(io.in.a.bits.source, 2) node _T_1615 = eq(_T_1614, UInt<2>(0h2)) node _T_1616 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1617 = and(_T_1615, _T_1616) node _T_1618 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1619 = and(_T_1617, _T_1618) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1620 = shr(io.in.a.bits.source, 2) node _T_1621 = eq(_T_1620, UInt<2>(0h3)) node _T_1622 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1625 = and(_T_1623, _T_1624) node _T_1626 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1627 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1628 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1629 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1630 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1631 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1632 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1633 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1634 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1635 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1636 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1637 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1638 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1639 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1640 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1641 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1642 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1643 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1644 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1645 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1646 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1647 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1648 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1649 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1650 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1651 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1652 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1653 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1655 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1656 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1657 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1658 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1659 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1660 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1661 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1662 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1663 = or(_T_1601, _T_1607) node _T_1664 = or(_T_1663, _T_1613) node _T_1665 = or(_T_1664, _T_1619) node _T_1666 = or(_T_1665, _T_1625) node _T_1667 = or(_T_1666, _T_1626) node _T_1668 = or(_T_1667, _T_1627) node _T_1669 = or(_T_1668, _T_1628) node _T_1670 = or(_T_1669, _T_1629) node _T_1671 = or(_T_1670, _T_1630) node _T_1672 = or(_T_1671, _T_1631) node _T_1673 = or(_T_1672, _T_1632) node _T_1674 = or(_T_1673, _T_1633) node _T_1675 = or(_T_1674, _T_1634) node _T_1676 = or(_T_1675, _T_1635) node _T_1677 = or(_T_1676, _T_1636) node _T_1678 = or(_T_1677, _T_1637) node _T_1679 = or(_T_1678, _T_1638) node _T_1680 = or(_T_1679, _T_1639) node _T_1681 = or(_T_1680, _T_1640) node _T_1682 = or(_T_1681, _T_1641) node _T_1683 = or(_T_1682, _T_1642) node _T_1684 = or(_T_1683, _T_1643) node _T_1685 = or(_T_1684, _T_1644) node _T_1686 = or(_T_1685, _T_1645) node _T_1687 = or(_T_1686, _T_1646) node _T_1688 = or(_T_1687, _T_1647) node _T_1689 = or(_T_1688, _T_1648) node _T_1690 = or(_T_1689, _T_1649) node _T_1691 = or(_T_1690, _T_1650) node _T_1692 = or(_T_1691, _T_1651) node _T_1693 = or(_T_1692, _T_1652) node _T_1694 = or(_T_1693, _T_1653) node _T_1695 = or(_T_1694, _T_1654) node _T_1696 = or(_T_1695, _T_1655) node _T_1697 = or(_T_1696, _T_1656) node _T_1698 = or(_T_1697, _T_1657) node _T_1699 = or(_T_1698, _T_1658) node _T_1700 = or(_T_1699, _T_1659) node _T_1701 = or(_T_1700, _T_1660) node _T_1702 = or(_T_1701, _T_1661) node _T_1703 = or(_T_1702, _T_1662) node _T_1704 = and(_T_1600, _T_1703) node _T_1705 = or(UInt<1>(0h0), _T_1704) node _T_1706 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1707 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1708 = cvt(_T_1707) node _T_1709 = and(_T_1708, asSInt(UInt<13>(0h1000))) node _T_1710 = asSInt(_T_1709) node _T_1711 = eq(_T_1710, asSInt(UInt<1>(0h0))) node _T_1712 = and(_T_1706, _T_1711) node _T_1713 = or(UInt<1>(0h0), _T_1712) node _T_1714 = and(_T_1705, _T_1713) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_41 node _T_1718 = asUInt(reset) node _T_1719 = eq(_T_1718, UInt<1>(0h0)) when _T_1719 : node _T_1720 = eq(source_ok, UInt<1>(0h0)) when _T_1720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1721 = asUInt(reset) node _T_1722 = eq(_T_1721, UInt<1>(0h0)) when _T_1722 : node _T_1723 = eq(is_aligned, UInt<1>(0h0)) when _T_1723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1724 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1725 = asUInt(reset) node _T_1726 = eq(_T_1725, UInt<1>(0h0)) when _T_1726 : node _T_1727 = eq(_T_1724, UInt<1>(0h0)) when _T_1727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1724, UInt<1>(0h1), "") : assert_44 node _T_1728 = eq(io.in.a.bits.mask, mask) node _T_1729 = asUInt(reset) node _T_1730 = eq(_T_1729, UInt<1>(0h0)) when _T_1730 : node _T_1731 = eq(_T_1728, UInt<1>(0h0)) when _T_1731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1728, UInt<1>(0h1), "") : assert_45 node _T_1732 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1732 : node _T_1733 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1734 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1735 = and(_T_1733, _T_1734) node _T_1736 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1737 = shr(io.in.a.bits.source, 2) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) node _T_1739 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1740 = and(_T_1738, _T_1739) node _T_1741 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1742 = and(_T_1740, _T_1741) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1743 = shr(io.in.a.bits.source, 2) node _T_1744 = eq(_T_1743, UInt<1>(0h1)) node _T_1745 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1748 = and(_T_1746, _T_1747) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1749 = shr(io.in.a.bits.source, 2) node _T_1750 = eq(_T_1749, UInt<2>(0h2)) node _T_1751 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1752 = and(_T_1750, _T_1751) node _T_1753 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1754 = and(_T_1752, _T_1753) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1755 = shr(io.in.a.bits.source, 2) node _T_1756 = eq(_T_1755, UInt<2>(0h3)) node _T_1757 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1758 = and(_T_1756, _T_1757) node _T_1759 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1760 = and(_T_1758, _T_1759) node _T_1761 = eq(io.in.a.bits.source, UInt<7>(0h4c)) node _T_1762 = eq(io.in.a.bits.source, UInt<7>(0h4d)) node _T_1763 = eq(io.in.a.bits.source, UInt<7>(0h4e)) node _T_1764 = eq(io.in.a.bits.source, UInt<7>(0h48)) node _T_1765 = eq(io.in.a.bits.source, UInt<7>(0h49)) node _T_1766 = eq(io.in.a.bits.source, UInt<7>(0h4a)) node _T_1767 = eq(io.in.a.bits.source, UInt<7>(0h44)) node _T_1768 = eq(io.in.a.bits.source, UInt<7>(0h45)) node _T_1769 = eq(io.in.a.bits.source, UInt<7>(0h46)) node _T_1770 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1771 = eq(io.in.a.bits.source, UInt<7>(0h41)) node _T_1772 = eq(io.in.a.bits.source, UInt<7>(0h42)) node _T_1773 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1774 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1775 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1776 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1777 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1778 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1779 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1780 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1781 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1782 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1783 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1784 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1785 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1786 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1787 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1788 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1789 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1790 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1791 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1792 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1793 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1794 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1795 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1796 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1797 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1798 = or(_T_1736, _T_1742) node _T_1799 = or(_T_1798, _T_1748) node _T_1800 = or(_T_1799, _T_1754) node _T_1801 = or(_T_1800, _T_1760) node _T_1802 = or(_T_1801, _T_1761) node _T_1803 = or(_T_1802, _T_1762) node _T_1804 = or(_T_1803, _T_1763) node _T_1805 = or(_T_1804, _T_1764) node _T_1806 = or(_T_1805, _T_1765) node _T_1807 = or(_T_1806, _T_1766) node _T_1808 = or(_T_1807, _T_1767) node _T_1809 = or(_T_1808, _T_1768) node _T_1810 = or(_T_1809, _T_1769) node _T_1811 = or(_T_1810, _T_1770) node _T_1812 = or(_T_1811, _T_1771) node _T_1813 = or(_T_1812, _T_1772) node _T_1814 = or(_T_1813, _T_1773) node _T_1815 = or(_T_1814, _T_1774) node _T_1816 = or(_T_1815, _T_1775) node _T_1817 = or(_T_1816, _T_1776) node _T_1818 = or(_T_1817, _T_1777) node _T_1819 = or(_T_1818, _T_1778) node _T_1820 = or(_T_1819, _T_1779) node _T_1821 = or(_T_1820, _T_1780) node _T_1822 = or(_T_1821, _T_1781) node _T_1823 = or(_T_1822, _T_1782) node _T_1824 = or(_T_1823, _T_1783) node _T_1825 = or(_T_1824, _T_1784) node _T_1826 = or(_T_1825, _T_1785) node _T_1827 = or(_T_1826, _T_1786) node _T_1828 = or(_T_1827, _T_1787) node _T_1829 = or(_T_1828, _T_1788) node _T_1830 = or(_T_1829, _T_1789) node _T_1831 = or(_T_1830, _T_1790) node _T_1832 = or(_T_1831, _T_1791) node _T_1833 = or(_T_1832, _T_1792) node _T_1834 = or(_T_1833, _T_1793) node _T_1835 = or(_T_1834, _T_1794) node _T_1836 = or(_T_1835, _T_1795) node _T_1837 = or(_T_1836, _T_1796) node _T_1838 = or(_T_1837, _T_1797) node _T_1839 = and(_T_1735, _T_1838) node _T_1840 = or(UInt<1>(0h0), _T_1839) node _T_1841 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1842 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1843 = cvt(_T_1842) node _T_1844 = and(_T_1843, asSInt(UInt<13>(0h1000))) node _T_1845 = asSInt(_T_1844) node _T_1846 = eq(_T_1845, asSInt(UInt<1>(0h0))) node _T_1847 = and(_T_1841, _T_1846) node _T_1848 = or(UInt<1>(0h0), _T_1847) node _T_1849 = and(_T_1840, _T_1848) node _T_1850 = asUInt(reset) node _T_1851 = eq(_T_1850, UInt<1>(0h0)) when _T_1851 : node _T_1852 = eq(_T_1849, UInt<1>(0h0)) when _T_1852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1849, UInt<1>(0h1), "") : assert_46 node _T_1853 = asUInt(reset) node _T_1854 = eq(_T_1853, UInt<1>(0h0)) when _T_1854 : node _T_1855 = eq(source_ok, UInt<1>(0h0)) when _T_1855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1856 = asUInt(reset) node _T_1857 = eq(_T_1856, UInt<1>(0h0)) when _T_1857 : node _T_1858 = eq(is_aligned, UInt<1>(0h0)) when _T_1858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1859 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1860 = asUInt(reset) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) when _T_1861 : node _T_1862 = eq(_T_1859, UInt<1>(0h0)) when _T_1862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1859, UInt<1>(0h1), "") : assert_49 node _T_1863 = eq(io.in.a.bits.mask, mask) node _T_1864 = asUInt(reset) node _T_1865 = eq(_T_1864, UInt<1>(0h0)) when _T_1865 : node _T_1866 = eq(_T_1863, UInt<1>(0h0)) when _T_1866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1863, UInt<1>(0h1), "") : assert_50 node _T_1867 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1868 = asUInt(reset) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) when _T_1869 : node _T_1870 = eq(_T_1867, UInt<1>(0h0)) when _T_1870 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1867, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1871 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1872 = asUInt(reset) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) when _T_1873 : node _T_1874 = eq(_T_1871, UInt<1>(0h0)) when _T_1874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1871, UInt<1>(0h1), "") : assert_52 node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_103 = shr(io.in.d.bits.source, 2) node _source_ok_T_104 = eq(_source_ok_T_103, UInt<1>(0h0)) node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105) node _source_ok_T_107 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_109 = shr(io.in.d.bits.source, 2) node _source_ok_T_110 = eq(_source_ok_T_109, UInt<1>(0h1)) node _source_ok_T_111 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_112 = and(_source_ok_T_110, _source_ok_T_111) node _source_ok_T_113 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_115 = shr(io.in.d.bits.source, 2) node _source_ok_T_116 = eq(_source_ok_T_115, UInt<2>(0h2)) node _source_ok_T_117 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_118 = and(_source_ok_T_116, _source_ok_T_117) node _source_ok_T_119 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_120 = and(_source_ok_T_118, _source_ok_T_119) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_121 = shr(io.in.d.bits.source, 2) node _source_ok_T_122 = eq(_source_ok_T_121, UInt<2>(0h3)) node _source_ok_T_123 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_124 = and(_source_ok_T_122, _source_ok_T_123) node _source_ok_T_125 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_126 = and(_source_ok_T_124, _source_ok_T_125) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h4c)) node _source_ok_T_128 = eq(io.in.d.bits.source, UInt<7>(0h4d)) node _source_ok_T_129 = eq(io.in.d.bits.source, UInt<7>(0h4e)) node _source_ok_T_130 = eq(io.in.d.bits.source, UInt<7>(0h48)) node _source_ok_T_131 = eq(io.in.d.bits.source, UInt<7>(0h49)) node _source_ok_T_132 = eq(io.in.d.bits.source, UInt<7>(0h4a)) node _source_ok_T_133 = eq(io.in.d.bits.source, UInt<7>(0h44)) node _source_ok_T_134 = eq(io.in.d.bits.source, UInt<7>(0h45)) node _source_ok_T_135 = eq(io.in.d.bits.source, UInt<7>(0h46)) node _source_ok_T_136 = eq(io.in.d.bits.source, UInt<7>(0h40)) node _source_ok_T_137 = eq(io.in.d.bits.source, UInt<7>(0h41)) node _source_ok_T_138 = eq(io.in.d.bits.source, UInt<7>(0h42)) node _source_ok_T_139 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_140 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_141 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_142 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_143 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_144 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_145 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_146 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_147 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_148 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_149 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_150 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_151 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_152 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_153 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_154 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_155 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_156 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_157 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_158 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_159 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_160 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_161 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_162 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_163 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[42] connect _source_ok_WIRE_1[0], _source_ok_T_102 connect _source_ok_WIRE_1[1], _source_ok_T_108 connect _source_ok_WIRE_1[2], _source_ok_T_114 connect _source_ok_WIRE_1[3], _source_ok_T_120 connect _source_ok_WIRE_1[4], _source_ok_T_126 connect _source_ok_WIRE_1[5], _source_ok_T_127 connect _source_ok_WIRE_1[6], _source_ok_T_128 connect _source_ok_WIRE_1[7], _source_ok_T_129 connect _source_ok_WIRE_1[8], _source_ok_T_130 connect _source_ok_WIRE_1[9], _source_ok_T_131 connect _source_ok_WIRE_1[10], _source_ok_T_132 connect _source_ok_WIRE_1[11], _source_ok_T_133 connect _source_ok_WIRE_1[12], _source_ok_T_134 connect _source_ok_WIRE_1[13], _source_ok_T_135 connect _source_ok_WIRE_1[14], _source_ok_T_136 connect _source_ok_WIRE_1[15], _source_ok_T_137 connect _source_ok_WIRE_1[16], _source_ok_T_138 connect _source_ok_WIRE_1[17], _source_ok_T_139 connect _source_ok_WIRE_1[18], _source_ok_T_140 connect _source_ok_WIRE_1[19], _source_ok_T_141 connect _source_ok_WIRE_1[20], _source_ok_T_142 connect _source_ok_WIRE_1[21], _source_ok_T_143 connect _source_ok_WIRE_1[22], _source_ok_T_144 connect _source_ok_WIRE_1[23], _source_ok_T_145 connect _source_ok_WIRE_1[24], _source_ok_T_146 connect _source_ok_WIRE_1[25], _source_ok_T_147 connect _source_ok_WIRE_1[26], _source_ok_T_148 connect _source_ok_WIRE_1[27], _source_ok_T_149 connect _source_ok_WIRE_1[28], _source_ok_T_150 connect _source_ok_WIRE_1[29], _source_ok_T_151 connect _source_ok_WIRE_1[30], _source_ok_T_152 connect _source_ok_WIRE_1[31], _source_ok_T_153 connect _source_ok_WIRE_1[32], _source_ok_T_154 connect _source_ok_WIRE_1[33], _source_ok_T_155 connect _source_ok_WIRE_1[34], _source_ok_T_156 connect _source_ok_WIRE_1[35], _source_ok_T_157 connect _source_ok_WIRE_1[36], _source_ok_T_158 connect _source_ok_WIRE_1[37], _source_ok_T_159 connect _source_ok_WIRE_1[38], _source_ok_T_160 connect _source_ok_WIRE_1[39], _source_ok_T_161 connect _source_ok_WIRE_1[40], _source_ok_T_162 connect _source_ok_WIRE_1[41], _source_ok_T_163 node _source_ok_T_164 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_165 = or(_source_ok_T_164, _source_ok_WIRE_1[2]) node _source_ok_T_166 = or(_source_ok_T_165, _source_ok_WIRE_1[3]) node _source_ok_T_167 = or(_source_ok_T_166, _source_ok_WIRE_1[4]) node _source_ok_T_168 = or(_source_ok_T_167, _source_ok_WIRE_1[5]) node _source_ok_T_169 = or(_source_ok_T_168, _source_ok_WIRE_1[6]) node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[7]) node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[8]) node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[9]) node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[10]) node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[11]) node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[12]) node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[13]) node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[14]) node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[15]) node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[16]) node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[17]) node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[18]) node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[19]) node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[20]) node _source_ok_T_184 = or(_source_ok_T_183, _source_ok_WIRE_1[21]) node _source_ok_T_185 = or(_source_ok_T_184, _source_ok_WIRE_1[22]) node _source_ok_T_186 = or(_source_ok_T_185, _source_ok_WIRE_1[23]) node _source_ok_T_187 = or(_source_ok_T_186, _source_ok_WIRE_1[24]) node _source_ok_T_188 = or(_source_ok_T_187, _source_ok_WIRE_1[25]) node _source_ok_T_189 = or(_source_ok_T_188, _source_ok_WIRE_1[26]) node _source_ok_T_190 = or(_source_ok_T_189, _source_ok_WIRE_1[27]) node _source_ok_T_191 = or(_source_ok_T_190, _source_ok_WIRE_1[28]) node _source_ok_T_192 = or(_source_ok_T_191, _source_ok_WIRE_1[29]) node _source_ok_T_193 = or(_source_ok_T_192, _source_ok_WIRE_1[30]) node _source_ok_T_194 = or(_source_ok_T_193, _source_ok_WIRE_1[31]) node _source_ok_T_195 = or(_source_ok_T_194, _source_ok_WIRE_1[32]) node _source_ok_T_196 = or(_source_ok_T_195, _source_ok_WIRE_1[33]) node _source_ok_T_197 = or(_source_ok_T_196, _source_ok_WIRE_1[34]) node _source_ok_T_198 = or(_source_ok_T_197, _source_ok_WIRE_1[35]) node _source_ok_T_199 = or(_source_ok_T_198, _source_ok_WIRE_1[36]) node _source_ok_T_200 = or(_source_ok_T_199, _source_ok_WIRE_1[37]) node _source_ok_T_201 = or(_source_ok_T_200, _source_ok_WIRE_1[38]) node _source_ok_T_202 = or(_source_ok_T_201, _source_ok_WIRE_1[39]) node _source_ok_T_203 = or(_source_ok_T_202, _source_ok_WIRE_1[40]) node source_ok_1 = or(_source_ok_T_203, _source_ok_WIRE_1[41]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1875 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1875 : node _T_1876 = asUInt(reset) node _T_1877 = eq(_T_1876, UInt<1>(0h0)) when _T_1877 : node _T_1878 = eq(source_ok_1, UInt<1>(0h0)) when _T_1878 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1879 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1880 = asUInt(reset) node _T_1881 = eq(_T_1880, UInt<1>(0h0)) when _T_1881 : node _T_1882 = eq(_T_1879, UInt<1>(0h0)) when _T_1882 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1879, UInt<1>(0h1), "") : assert_54 node _T_1883 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1884 = asUInt(reset) node _T_1885 = eq(_T_1884, UInt<1>(0h0)) when _T_1885 : node _T_1886 = eq(_T_1883, UInt<1>(0h0)) when _T_1886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1883, UInt<1>(0h1), "") : assert_55 node _T_1887 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1888 = asUInt(reset) node _T_1889 = eq(_T_1888, UInt<1>(0h0)) when _T_1889 : node _T_1890 = eq(_T_1887, UInt<1>(0h0)) when _T_1890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1887, UInt<1>(0h1), "") : assert_56 node _T_1891 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1892 = asUInt(reset) node _T_1893 = eq(_T_1892, UInt<1>(0h0)) when _T_1893 : node _T_1894 = eq(_T_1891, UInt<1>(0h0)) when _T_1894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1891, UInt<1>(0h1), "") : assert_57 node _T_1895 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1895 : node _T_1896 = asUInt(reset) node _T_1897 = eq(_T_1896, UInt<1>(0h0)) when _T_1897 : node _T_1898 = eq(source_ok_1, UInt<1>(0h0)) when _T_1898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1899 = asUInt(reset) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) when _T_1900 : node _T_1901 = eq(sink_ok, UInt<1>(0h0)) when _T_1901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1902 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1903 = asUInt(reset) node _T_1904 = eq(_T_1903, UInt<1>(0h0)) when _T_1904 : node _T_1905 = eq(_T_1902, UInt<1>(0h0)) when _T_1905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1902, UInt<1>(0h1), "") : assert_60 node _T_1906 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1907 = asUInt(reset) node _T_1908 = eq(_T_1907, UInt<1>(0h0)) when _T_1908 : node _T_1909 = eq(_T_1906, UInt<1>(0h0)) when _T_1909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1906, UInt<1>(0h1), "") : assert_61 node _T_1910 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1911 = asUInt(reset) node _T_1912 = eq(_T_1911, UInt<1>(0h0)) when _T_1912 : node _T_1913 = eq(_T_1910, UInt<1>(0h0)) when _T_1913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1910, UInt<1>(0h1), "") : assert_62 node _T_1914 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1915 = asUInt(reset) node _T_1916 = eq(_T_1915, UInt<1>(0h0)) when _T_1916 : node _T_1917 = eq(_T_1914, UInt<1>(0h0)) when _T_1917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1914, UInt<1>(0h1), "") : assert_63 node _T_1918 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1919 = or(UInt<1>(0h0), _T_1918) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_64 node _T_1923 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1923 : node _T_1924 = asUInt(reset) node _T_1925 = eq(_T_1924, UInt<1>(0h0)) when _T_1925 : node _T_1926 = eq(source_ok_1, UInt<1>(0h0)) when _T_1926 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(sink_ok, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1930 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_67 node _T_1934 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(_T_1934, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1934, UInt<1>(0h1), "") : assert_68 node _T_1938 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1939 = asUInt(reset) node _T_1940 = eq(_T_1939, UInt<1>(0h0)) when _T_1940 : node _T_1941 = eq(_T_1938, UInt<1>(0h0)) when _T_1941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1938, UInt<1>(0h1), "") : assert_69 node _T_1942 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1943 = or(_T_1942, io.in.d.bits.corrupt) node _T_1944 = asUInt(reset) node _T_1945 = eq(_T_1944, UInt<1>(0h0)) when _T_1945 : node _T_1946 = eq(_T_1943, UInt<1>(0h0)) when _T_1946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1943, UInt<1>(0h1), "") : assert_70 node _T_1947 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1948 = or(UInt<1>(0h0), _T_1947) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_71 node _T_1952 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1952 : node _T_1953 = asUInt(reset) node _T_1954 = eq(_T_1953, UInt<1>(0h0)) when _T_1954 : node _T_1955 = eq(source_ok_1, UInt<1>(0h0)) when _T_1955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1956 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1957 = asUInt(reset) node _T_1958 = eq(_T_1957, UInt<1>(0h0)) when _T_1958 : node _T_1959 = eq(_T_1956, UInt<1>(0h0)) when _T_1959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1956, UInt<1>(0h1), "") : assert_73 node _T_1960 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1961 = asUInt(reset) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(_T_1960, UInt<1>(0h0)) when _T_1963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1960, UInt<1>(0h1), "") : assert_74 node _T_1964 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1965 = or(UInt<1>(0h0), _T_1964) node _T_1966 = asUInt(reset) node _T_1967 = eq(_T_1966, UInt<1>(0h0)) when _T_1967 : node _T_1968 = eq(_T_1965, UInt<1>(0h0)) when _T_1968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1965, UInt<1>(0h1), "") : assert_75 node _T_1969 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1969 : node _T_1970 = asUInt(reset) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) when _T_1971 : node _T_1972 = eq(source_ok_1, UInt<1>(0h0)) when _T_1972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1973 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1974 = asUInt(reset) node _T_1975 = eq(_T_1974, UInt<1>(0h0)) when _T_1975 : node _T_1976 = eq(_T_1973, UInt<1>(0h0)) when _T_1976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1973, UInt<1>(0h1), "") : assert_77 node _T_1977 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1978 = or(_T_1977, io.in.d.bits.corrupt) node _T_1979 = asUInt(reset) node _T_1980 = eq(_T_1979, UInt<1>(0h0)) when _T_1980 : node _T_1981 = eq(_T_1978, UInt<1>(0h0)) when _T_1981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1978, UInt<1>(0h1), "") : assert_78 node _T_1982 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1983 = or(UInt<1>(0h0), _T_1982) node _T_1984 = asUInt(reset) node _T_1985 = eq(_T_1984, UInt<1>(0h0)) when _T_1985 : node _T_1986 = eq(_T_1983, UInt<1>(0h0)) when _T_1986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1983, UInt<1>(0h1), "") : assert_79 node _T_1987 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1987 : node _T_1988 = asUInt(reset) node _T_1989 = eq(_T_1988, UInt<1>(0h0)) when _T_1989 : node _T_1990 = eq(source_ok_1, UInt<1>(0h0)) when _T_1990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1991 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1992 = asUInt(reset) node _T_1993 = eq(_T_1992, UInt<1>(0h0)) when _T_1993 : node _T_1994 = eq(_T_1991, UInt<1>(0h0)) when _T_1994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1991, UInt<1>(0h1), "") : assert_81 node _T_1995 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1996 = asUInt(reset) node _T_1997 = eq(_T_1996, UInt<1>(0h0)) when _T_1997 : node _T_1998 = eq(_T_1995, UInt<1>(0h0)) when _T_1998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1995, UInt<1>(0h1), "") : assert_82 node _T_1999 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_2000 = or(UInt<1>(0h0), _T_1999) node _T_2001 = asUInt(reset) node _T_2002 = eq(_T_2001, UInt<1>(0h0)) when _T_2002 : node _T_2003 = eq(_T_2000, UInt<1>(0h0)) when _T_2003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_2000, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_2004 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_2005 = asUInt(reset) node _T_2006 = eq(_T_2005, UInt<1>(0h0)) when _T_2006 : node _T_2007 = eq(_T_2004, UInt<1>(0h0)) when _T_2007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_2004, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_2008 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_2009 = asUInt(reset) node _T_2010 = eq(_T_2009, UInt<1>(0h0)) when _T_2010 : node _T_2011 = eq(_T_2008, UInt<1>(0h0)) when _T_2011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_2008, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_2012 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_2013 = asUInt(reset) node _T_2014 = eq(_T_2013, UInt<1>(0h0)) when _T_2014 : node _T_2015 = eq(_T_2012, UInt<1>(0h0)) when _T_2015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_2012, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2016 = eq(a_first, UInt<1>(0h0)) node _T_2017 = and(io.in.a.valid, _T_2016) when _T_2017 : node _T_2018 = eq(io.in.a.bits.opcode, opcode) node _T_2019 = asUInt(reset) node _T_2020 = eq(_T_2019, UInt<1>(0h0)) when _T_2020 : node _T_2021 = eq(_T_2018, UInt<1>(0h0)) when _T_2021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_2018, UInt<1>(0h1), "") : assert_87 node _T_2022 = eq(io.in.a.bits.param, param) node _T_2023 = asUInt(reset) node _T_2024 = eq(_T_2023, UInt<1>(0h0)) when _T_2024 : node _T_2025 = eq(_T_2022, UInt<1>(0h0)) when _T_2025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_2022, UInt<1>(0h1), "") : assert_88 node _T_2026 = eq(io.in.a.bits.size, size) node _T_2027 = asUInt(reset) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) when _T_2028 : node _T_2029 = eq(_T_2026, UInt<1>(0h0)) when _T_2029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_2026, UInt<1>(0h1), "") : assert_89 node _T_2030 = eq(io.in.a.bits.source, source) node _T_2031 = asUInt(reset) node _T_2032 = eq(_T_2031, UInt<1>(0h0)) when _T_2032 : node _T_2033 = eq(_T_2030, UInt<1>(0h0)) when _T_2033 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_2030, UInt<1>(0h1), "") : assert_90 node _T_2034 = eq(io.in.a.bits.address, address) node _T_2035 = asUInt(reset) node _T_2036 = eq(_T_2035, UInt<1>(0h0)) when _T_2036 : node _T_2037 = eq(_T_2034, UInt<1>(0h0)) when _T_2037 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_2034, UInt<1>(0h1), "") : assert_91 node _T_2038 = and(io.in.a.ready, io.in.a.valid) node _T_2039 = and(_T_2038, a_first) when _T_2039 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2040 = eq(d_first, UInt<1>(0h0)) node _T_2041 = and(io.in.d.valid, _T_2040) when _T_2041 : node _T_2042 = eq(io.in.d.bits.opcode, opcode_1) node _T_2043 = asUInt(reset) node _T_2044 = eq(_T_2043, UInt<1>(0h0)) when _T_2044 : node _T_2045 = eq(_T_2042, UInt<1>(0h0)) when _T_2045 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_2042, UInt<1>(0h1), "") : assert_92 node _T_2046 = eq(io.in.d.bits.param, param_1) node _T_2047 = asUInt(reset) node _T_2048 = eq(_T_2047, UInt<1>(0h0)) when _T_2048 : node _T_2049 = eq(_T_2046, UInt<1>(0h0)) when _T_2049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_2046, UInt<1>(0h1), "") : assert_93 node _T_2050 = eq(io.in.d.bits.size, size_1) node _T_2051 = asUInt(reset) node _T_2052 = eq(_T_2051, UInt<1>(0h0)) when _T_2052 : node _T_2053 = eq(_T_2050, UInt<1>(0h0)) when _T_2053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_2050, UInt<1>(0h1), "") : assert_94 node _T_2054 = eq(io.in.d.bits.source, source_1) node _T_2055 = asUInt(reset) node _T_2056 = eq(_T_2055, UInt<1>(0h0)) when _T_2056 : node _T_2057 = eq(_T_2054, UInt<1>(0h0)) when _T_2057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_2054, UInt<1>(0h1), "") : assert_95 node _T_2058 = eq(io.in.d.bits.sink, sink) node _T_2059 = asUInt(reset) node _T_2060 = eq(_T_2059, UInt<1>(0h0)) when _T_2060 : node _T_2061 = eq(_T_2058, UInt<1>(0h0)) when _T_2061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_2058, UInt<1>(0h1), "") : assert_96 node _T_2062 = eq(io.in.d.bits.denied, denied) node _T_2063 = asUInt(reset) node _T_2064 = eq(_T_2063, UInt<1>(0h0)) when _T_2064 : node _T_2065 = eq(_T_2062, UInt<1>(0h0)) when _T_2065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_2062, UInt<1>(0h1), "") : assert_97 node _T_2066 = and(io.in.d.ready, io.in.d.valid) node _T_2067 = and(_T_2066, d_first) when _T_2067 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<516> connect a_sizes_set, UInt<516>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_2068 = and(io.in.a.valid, a_first_1) node _T_2069 = and(_T_2068, UInt<1>(0h1)) when _T_2069 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2070 = and(io.in.a.ready, io.in.a.valid) node _T_2071 = and(_T_2070, a_first_1) node _T_2072 = and(_T_2071, UInt<1>(0h1)) when _T_2072 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2073 = dshr(inflight, io.in.a.bits.source) node _T_2074 = bits(_T_2073, 0, 0) node _T_2075 = eq(_T_2074, UInt<1>(0h0)) node _T_2076 = asUInt(reset) node _T_2077 = eq(_T_2076, UInt<1>(0h0)) when _T_2077 : node _T_2078 = eq(_T_2075, UInt<1>(0h0)) when _T_2078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_2075, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<516> connect d_sizes_clr, UInt<516>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2079 = and(io.in.d.valid, d_first_1) node _T_2080 = and(_T_2079, UInt<1>(0h1)) node _T_2081 = eq(d_release_ack, UInt<1>(0h0)) node _T_2082 = and(_T_2080, _T_2081) when _T_2082 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2083 = and(io.in.d.ready, io.in.d.valid) node _T_2084 = and(_T_2083, d_first_1) node _T_2085 = and(_T_2084, UInt<1>(0h1)) node _T_2086 = eq(d_release_ack, UInt<1>(0h0)) node _T_2087 = and(_T_2085, _T_2086) when _T_2087 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2088 = and(io.in.d.valid, d_first_1) node _T_2089 = and(_T_2088, UInt<1>(0h1)) node _T_2090 = eq(d_release_ack, UInt<1>(0h0)) node _T_2091 = and(_T_2089, _T_2090) when _T_2091 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2092 = dshr(inflight, io.in.d.bits.source) node _T_2093 = bits(_T_2092, 0, 0) node _T_2094 = or(_T_2093, same_cycle_resp) node _T_2095 = asUInt(reset) node _T_2096 = eq(_T_2095, UInt<1>(0h0)) when _T_2096 : node _T_2097 = eq(_T_2094, UInt<1>(0h0)) when _T_2097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_2094, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_2098 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2099 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2100 = or(_T_2098, _T_2099) node _T_2101 = asUInt(reset) node _T_2102 = eq(_T_2101, UInt<1>(0h0)) when _T_2102 : node _T_2103 = eq(_T_2100, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_2100, UInt<1>(0h1), "") : assert_100 node _T_2104 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2105 = asUInt(reset) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(_T_2104, UInt<1>(0h0)) when _T_2107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_2104, UInt<1>(0h1), "") : assert_101 else : node _T_2108 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2109 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2110 = or(_T_2108, _T_2109) node _T_2111 = asUInt(reset) node _T_2112 = eq(_T_2111, UInt<1>(0h0)) when _T_2112 : node _T_2113 = eq(_T_2110, UInt<1>(0h0)) when _T_2113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_2110, UInt<1>(0h1), "") : assert_102 node _T_2114 = eq(io.in.d.bits.size, a_size_lookup) node _T_2115 = asUInt(reset) node _T_2116 = eq(_T_2115, UInt<1>(0h0)) when _T_2116 : node _T_2117 = eq(_T_2114, UInt<1>(0h0)) when _T_2117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_2114, UInt<1>(0h1), "") : assert_103 node _T_2118 = and(io.in.d.valid, d_first_1) node _T_2119 = and(_T_2118, a_first_1) node _T_2120 = and(_T_2119, io.in.a.valid) node _T_2121 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2122 = and(_T_2120, _T_2121) node _T_2123 = eq(d_release_ack, UInt<1>(0h0)) node _T_2124 = and(_T_2122, _T_2123) when _T_2124 : node _T_2125 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2126 = or(_T_2125, io.in.a.ready) node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(_T_2126, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_2126, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_282 node _T_2130 = orr(inflight) node _T_2131 = eq(_T_2130, UInt<1>(0h0)) node _T_2132 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2133 = or(_T_2131, _T_2132) node _T_2134 = lt(watchdog, plusarg_reader.out) node _T_2135 = or(_T_2133, _T_2134) node _T_2136 = asUInt(reset) node _T_2137 = eq(_T_2136, UInt<1>(0h0)) when _T_2137 : node _T_2138 = eq(_T_2135, UInt<1>(0h0)) when _T_2138 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_2135, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2139 = and(io.in.a.ready, io.in.a.valid) node _T_2140 = and(io.in.d.ready, io.in.d.valid) node _T_2141 = or(_T_2139, _T_2140) when _T_2141 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<516> connect c_sizes_set, UInt<516>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_2142 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_2143 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_2144 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = and(_T_2142, _T_2145) when _T_2146 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_2147 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_2148 = and(_T_2147, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_2149 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_2150 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_2151 = and(_T_2149, _T_2150) node _T_2152 = and(_T_2148, _T_2151) when _T_2152 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_2153 = dshr(inflight_1, _WIRE_19.bits.source) node _T_2154 = bits(_T_2153, 0, 0) node _T_2155 = eq(_T_2154, UInt<1>(0h0)) node _T_2156 = asUInt(reset) node _T_2157 = eq(_T_2156, UInt<1>(0h0)) when _T_2157 : node _T_2158 = eq(_T_2155, UInt<1>(0h0)) when _T_2158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_2155, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<516> connect d_sizes_clr_1, UInt<516>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2159 = and(io.in.d.valid, d_first_2) node _T_2160 = and(_T_2159, UInt<1>(0h1)) node _T_2161 = and(_T_2160, d_release_ack_1) when _T_2161 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2162 = and(io.in.d.ready, io.in.d.valid) node _T_2163 = and(_T_2162, d_first_2) node _T_2164 = and(_T_2163, UInt<1>(0h1)) node _T_2165 = and(_T_2164, d_release_ack_1) when _T_2165 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2166 = and(io.in.d.valid, d_first_2) node _T_2167 = and(_T_2166, UInt<1>(0h1)) node _T_2168 = and(_T_2167, d_release_ack_1) when _T_2168 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2169 = dshr(inflight_1, io.in.d.bits.source) node _T_2170 = bits(_T_2169, 0, 0) node _T_2171 = or(_T_2170, same_cycle_resp_1) node _T_2172 = asUInt(reset) node _T_2173 = eq(_T_2172, UInt<1>(0h0)) when _T_2173 : node _T_2174 = eq(_T_2171, UInt<1>(0h0)) when _T_2174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_2171, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_2175 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_2176 = asUInt(reset) node _T_2177 = eq(_T_2176, UInt<1>(0h0)) when _T_2177 : node _T_2178 = eq(_T_2175, UInt<1>(0h0)) when _T_2178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_2175, UInt<1>(0h1), "") : assert_108 else : node _T_2179 = eq(io.in.d.bits.size, c_size_lookup) node _T_2180 = asUInt(reset) node _T_2181 = eq(_T_2180, UInt<1>(0h0)) when _T_2181 : node _T_2182 = eq(_T_2179, UInt<1>(0h0)) when _T_2182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_2179, UInt<1>(0h1), "") : assert_109 node _T_2183 = and(io.in.d.valid, d_first_2) node _T_2184 = and(_T_2183, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_2185 = and(_T_2184, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_2186 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_2187 = and(_T_2185, _T_2186) node _T_2188 = and(_T_2187, d_release_ack_1) node _T_2189 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2190 = and(_T_2188, _T_2189) when _T_2190 : node _T_2191 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_2192 = or(_T_2191, _WIRE_27.ready) node _T_2193 = asUInt(reset) node _T_2194 = eq(_T_2193, UInt<1>(0h0)) when _T_2194 : node _T_2195 = eq(_T_2192, UInt<1>(0h0)) when _T_2195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_2192, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_283 node _T_2196 = orr(inflight_1) node _T_2197 = eq(_T_2196, UInt<1>(0h0)) node _T_2198 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2199 = or(_T_2197, _T_2198) node _T_2200 = lt(watchdog_1, plusarg_reader_1.out) node _T_2201 = or(_T_2199, _T_2200) node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : node _T_2204 = eq(_T_2201, UInt<1>(0h0)) when _T_2204 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_2201, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_2205 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_2206 = and(io.in.d.ready, io.in.d.valid) node _T_2207 = or(_T_2205, _T_2206) when _T_2207 : connect watchdog_1, UInt<1>(0h0)	module TLMonitor_118( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [128:0] inflight_1; // @[Monitor.scala:726:35] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_315 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_59 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_315( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 \| io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_59 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_422 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_422( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_37 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_37 connect io_out_source_valid_1.clock, clock connect io_out_source_valid_1.reset, reset connect io_out_source_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_1.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_37( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_37 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_5 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<2>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<2>, clock reg probes_toN : UInt<2>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB \|\| !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC \|\| !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_uncommonBits_T = or(request.source, UInt<2>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 1, 0) node _req_clientBit_T = shr(request.source, 2) node _req_clientBit_T_1 = eq(_req_clientBit_T, UInt<4>(0ha)) node _req_clientBit_T_2 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_3 = and(_req_clientBit_T_1, _req_clientBit_T_2) node _req_clientBit_T_4 = leq(req_clientBit_uncommonBits, UInt<2>(0h2)) node _req_clientBit_T_5 = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_clientBit_uncommonBits_T_1 = or(request.source, UInt<2>(0h0)) node req_clientBit_uncommonBits_1 = bits(_req_clientBit_uncommonBits_T_1, 1, 0) node _req_clientBit_T_6 = shr(request.source, 2) node _req_clientBit_T_7 = eq(_req_clientBit_T_6, UInt<4>(0h8)) node _req_clientBit_T_8 = leq(UInt<1>(0h0), req_clientBit_uncommonBits_1) node _req_clientBit_T_9 = and(_req_clientBit_T_7, _req_clientBit_T_8) node _req_clientBit_T_10 = leq(req_clientBit_uncommonBits_1, UInt<2>(0h2)) node _req_clientBit_T_11 = and(_req_clientBit_T_9, _req_clientBit_T_10) node req_clientBit = cat(_req_clientBit_T_11, _req_clientBit_T_5) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid \|\| meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<2>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<2>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 1, 0) node _probe_bit_T = shr(io.sinkc.bits.source, 2) node _probe_bit_T_1 = eq(_probe_bit_T, UInt<4>(0ha)) node _probe_bit_T_2 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_3 = and(_probe_bit_T_1, _probe_bit_T_2) node _probe_bit_T_4 = leq(probe_bit_uncommonBits, UInt<2>(0h2)) node _probe_bit_T_5 = and(_probe_bit_T_3, _probe_bit_T_4) node _probe_bit_uncommonBits_T_1 = or(io.sinkc.bits.source, UInt<2>(0h0)) node probe_bit_uncommonBits_1 = bits(_probe_bit_uncommonBits_T_1, 1, 0) node _probe_bit_T_6 = shr(io.sinkc.bits.source, 2) node _probe_bit_T_7 = eq(_probe_bit_T_6, UInt<4>(0h8)) node _probe_bit_T_8 = leq(UInt<1>(0h0), probe_bit_uncommonBits_1) node _probe_bit_T_9 = and(_probe_bit_T_7, _probe_bit_T_8) node _probe_bit_T_10 = leq(probe_bit_uncommonBits_1, UInt<2>(0h2)) node _probe_bit_T_11 = and(_probe_bit_T_9, _probe_bit_T_10) node probe_bit = cat(_probe_bit_T_11, _probe_bit_T_5) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<2>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 1, 0) node _new_clientBit_T = shr(new_request.source, 2) node _new_clientBit_T_1 = eq(_new_clientBit_T, UInt<4>(0ha)) node _new_clientBit_T_2 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_3 = and(_new_clientBit_T_1, _new_clientBit_T_2) node _new_clientBit_T_4 = leq(new_clientBit_uncommonBits, UInt<2>(0h2)) node _new_clientBit_T_5 = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_clientBit_uncommonBits_T_1 = or(new_request.source, UInt<2>(0h0)) node new_clientBit_uncommonBits_1 = bits(_new_clientBit_uncommonBits_T_1, 1, 0) node _new_clientBit_T_6 = shr(new_request.source, 2) node _new_clientBit_T_7 = eq(_new_clientBit_T_6, UInt<4>(0h8)) node _new_clientBit_T_8 = leq(UInt<1>(0h0), new_clientBit_uncommonBits_1) node _new_clientBit_T_9 = and(_new_clientBit_T_7, _new_clientBit_T_8) node _new_clientBit_T_10 = leq(new_clientBit_uncommonBits_1, UInt<2>(0h2)) node _new_clientBit_T_11 = and(_new_clientBit_T_9, _new_clientBit_T_10) node new_clientBit = cat(_new_clientBit_T_11, _new_clientBit_T_5) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid \|\| (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)	module MSHR_5( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0 = 1'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T = 1'h0; // @[MSHR.scala:279:38] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _excluded_client_T_9 = 1'h0; // @[MSHR.scala:279:57] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire allocate_as_full_prio_0 = 1'h0; // @[MSHR.scala:504:34] wire new_request_prio_0 = 1'h0; // @[MSHR.scala:506:24] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [1:0] _io_schedule_bits_b_bits_clients_T = 2'h3; // @[MSHR.scala:289:53] wire [1:0] _last_probe_T_1 = 2'h3; // @[MSHR.scala:459:66] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_clients = 2'h0; // @[MSHR.scala:268:21] wire [1:0] excluded_client = 2'h0; // @[MSHR.scala:279:28] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire _req_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_8 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [1:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [5:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [5:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [5:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [5:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [1:0] meta_clients; // @[MSHR.scala:100:17] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients; // @[MSHR.scala:100:17, :289:51] wire [1:0] _last_probe_T_2 = meta_clients; // @[MSHR.scala:100:17, :459:64] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [1:0] probes_done; // @[MSHR.scala:150:24] reg [1:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire [1:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T = request_source[5:2]; // @[Parameters.scala:54:10] wire [3:0] _req_clientBit_T_6 = request_source[5:2]; // @[Parameters.scala:54:10] wire _req_clientBit_T_1 = _req_clientBit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_3 = _req_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_4 = req_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_5 = _req_clientBit_T_3 & _req_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_7 = _req_clientBit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_9 = _req_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_10 = req_clientBit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_11 = _req_clientBit_T_9 & _req_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit = {_req_clientBit_T_11, _req_clientBit_T_5}; // @[Parameters.scala:56:48] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [1:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [1:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [1:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [1:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [1:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [1:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 2'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [1:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 2'h0; // @[Parameters.scala:201:10] wire [1:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [1:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [1:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 2'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [1:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire [1:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire [3:0] _probe_bit_T_6 = io_sinkc_bits_source_0[5:2]; // @[Parameters.scala:54:10] wire _probe_bit_T_1 = _probe_bit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_3 = _probe_bit_T_1; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_4 = probe_bit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_5 = _probe_bit_T_3 & _probe_bit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_7 = _probe_bit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_9 = _probe_bit_T_7; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_10 = probe_bit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_11 = _probe_bit_T_9 & _probe_bit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit = {_probe_bit_T_11, _probe_bit_T_5}; // @[Parameters.scala:56:48] wire [1:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [1:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [1:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [1:0] _probes_toN_T = probe_toN ? probe_bit : 2'h0; // @[Parameters.scala:201:10, :282:66] wire [1:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [5:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire [1:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T = new_request_source[5:2]; // @[Parameters.scala:54:10] wire [3:0] _new_clientBit_T_6 = new_request_source[5:2]; // @[Parameters.scala:54:10] wire _new_clientBit_T_1 = _new_clientBit_T == 4'hA; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_3 = _new_clientBit_T_1; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_4 = new_clientBit_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_5 = _new_clientBit_T_3 & _new_clientBit_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_7 = _new_clientBit_T_6 == 4'h8; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_9 = _new_clientBit_T_7; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_10 = new_clientBit_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_11 = _new_clientBit_T_9 & _new_clientBit_T_10; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit = {_new_clientBit_T_11, _new_clientBit_T_5}; // @[Parameters.scala:56:48] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [1:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 2'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module LZ77HashMatcherMemLoader : input clock : Clock input reset : Reset output io : { l2helperUser : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip src_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}, consumer : { flip user_consumed_bytes : UInt<6>, available_output_bytes : UInt<6>, output_valid : UInt<1>, flip output_ready : UInt<1>, output_data : UInt<256>, output_last_chunk : UInt<1>}, optional_hbsram_write : { valid : UInt<1>, bits : { data : UInt<256>, valid_bytes : UInt<6>}}} inst buf_info_queue of Queue16_BufInfoBundle connect buf_info_queue.clock, clock connect buf_info_queue.reset, reset inst load_info_queue of Queue256_LoadInfoBundle connect load_info_queue.clock, clock connect load_info_queue.reset, reset node base_addr_start_index = and(io.src_info.bits.ip, UInt<5>(0h1f)) node _aligned_loadlen_T = add(io.src_info.bits.isize, base_addr_start_index) node aligned_loadlen = tail(_aligned_loadlen_T, 1) node _base_addr_end_index_T = add(io.src_info.bits.isize, base_addr_start_index) node _base_addr_end_index_T_1 = tail(_base_addr_end_index_T, 1) node base_addr_end_index = and(_base_addr_end_index_T_1, UInt<5>(0h1f)) node _base_addr_end_index_inclusive_T = add(io.src_info.bits.isize, base_addr_start_index) node _base_addr_end_index_inclusive_T_1 = tail(_base_addr_end_index_inclusive_T, 1) node _base_addr_end_index_inclusive_T_2 = sub(_base_addr_end_index_inclusive_T_1, UInt<1>(0h1)) node _base_addr_end_index_inclusive_T_3 = tail(_base_addr_end_index_inclusive_T_2, 1) node base_addr_end_index_inclusive = and(_base_addr_end_index_inclusive_T_3, UInt<5>(0h1f)) node _extra_word_T = and(aligned_loadlen, UInt<5>(0h1f)) node extra_word = neq(_extra_word_T, UInt<1>(0h0)) node _base_addr_bytes_aligned_T = dshr(io.src_info.bits.ip, UInt<3>(0h5)) node base_addr_bytes_aligned = dshl(_base_addr_bytes_aligned_T, UInt<3>(0h5)) node _words_to_load_T = dshr(aligned_loadlen, UInt<3>(0h5)) node _words_to_load_T_1 = add(_words_to_load_T, extra_word) node words_to_load = tail(_words_to_load_T_1, 1) node _words_to_load_minus_one_T = sub(words_to_load, UInt<1>(0h1)) node words_to_load_minus_one = tail(_words_to_load_minus_one_T, 1) regreset print_not_done : UInt<1>, clock, reset, UInt<1>(0h1) node _T = and(io.src_info.valid, print_not_done) when _T : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "base_addr_bytes: %x\n", io.src_info.bits.ip) : printf_1 regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "base_len: %x\n", io.src_info.bits.isize) : printf_3 regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "base_addr_start_index: %x\n", base_addr_start_index) : printf_5 regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6 node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "aligned_loadlen: %x\n", aligned_loadlen) : printf_7 regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8 node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "base_addr_end_index: %x\n", base_addr_end_index) : printf_9 regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10 node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "base_addr_end_index_inclusive: %x\n", base_addr_end_index_inclusive) : printf_11 regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12 node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "extra_word: %x\n", extra_word) : printf_13 regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14 node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "base_addr_bytes_aligned: %x\n", base_addr_bytes_aligned) : printf_15 regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_33 = asUInt(reset) node _T_34 = eq(_T_33, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16 node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "words_to_load: %x\n", words_to_load) : printf_17 regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18 node _T_39 = asUInt(reset) node _T_40 = eq(_T_39, UInt<1>(0h0)) when _T_40 : printf(clock, UInt<1>(0h1), "words_to_load_minus_one: %x\n", words_to_load_minus_one) : printf_19 connect print_not_done, UInt<1>(0h0) node _T_41 = and(io.src_info.ready, io.src_info.valid) when _T_41 : connect print_not_done, UInt<1>(0h1) regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_42 = asUInt(reset) node _T_43 = eq(_T_42, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20 node _T_44 = asUInt(reset) node _T_45 = eq(_T_44, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "COMPLETED INPUT LOAD FOR DECOMPRESSION\n") : printf_21 connect io.l2helperUser.req.bits.cmd, UInt<1>(0h0) connect io.l2helperUser.req.bits.size, UInt<3>(0h5) connect io.l2helperUser.req.bits.data, UInt<1>(0h0) regreset addrinc : UInt<64>, clock, reset, UInt<64>(0h0) node _load_info_queue_io_enq_bits_start_byte_T = eq(addrinc, UInt<1>(0h0)) node _load_info_queue_io_enq_bits_start_byte_T_1 = mux(_load_info_queue_io_enq_bits_start_byte_T, base_addr_start_index, UInt<1>(0h0)) connect load_info_queue.io.enq.bits.start_byte, _load_info_queue_io_enq_bits_start_byte_T_1 node _load_info_queue_io_enq_bits_end_byte_T = eq(addrinc, words_to_load_minus_one) node _load_info_queue_io_enq_bits_end_byte_T_1 = mux(_load_info_queue_io_enq_bits_end_byte_T, base_addr_end_index_inclusive, UInt<5>(0h1f)) connect load_info_queue.io.enq.bits.end_byte, _load_info_queue_io_enq_bits_end_byte_T_1 node _T_46 = and(io.l2helperUser.req.ready, io.src_info.valid) node _T_47 = and(_T_46, buf_info_queue.io.enq.ready) node _T_48 = and(_T_47, load_info_queue.io.enq.ready) node _T_49 = eq(addrinc, words_to_load_minus_one) node _T_50 = and(_T_48, _T_49) when _T_50 : connect addrinc, UInt<1>(0h0) else : node _T_51 = and(io.l2helperUser.req.ready, io.src_info.valid) node _T_52 = and(_T_51, buf_info_queue.io.enq.ready) node _T_53 = and(_T_52, load_info_queue.io.enq.ready) when _T_53 : node _addrinc_T = add(addrinc, UInt<1>(0h1)) node _addrinc_T_1 = tail(_addrinc_T, 1) connect addrinc, _addrinc_T_1 node _io_src_info_ready_T = eq(addrinc, words_to_load_minus_one) node _io_src_info_ready_T_1 = and(io.l2helperUser.req.ready, buf_info_queue.io.enq.ready) node _io_src_info_ready_T_2 = and(_io_src_info_ready_T_1, load_info_queue.io.enq.ready) node _io_src_info_ready_T_3 = and(_io_src_info_ready_T_2, _io_src_info_ready_T) connect io.src_info.ready, _io_src_info_ready_T_3 node _buf_info_queue_io_enq_valid_T = eq(addrinc, UInt<1>(0h0)) node _buf_info_queue_io_enq_valid_T_1 = and(io.l2helperUser.req.ready, io.src_info.valid) node _buf_info_queue_io_enq_valid_T_2 = and(_buf_info_queue_io_enq_valid_T_1, load_info_queue.io.enq.ready) node _buf_info_queue_io_enq_valid_T_3 = and(_buf_info_queue_io_enq_valid_T_2, _buf_info_queue_io_enq_valid_T) connect buf_info_queue.io.enq.valid, _buf_info_queue_io_enq_valid_T_3 node _load_info_queue_io_enq_valid_T = and(io.l2helperUser.req.ready, io.src_info.valid) node _load_info_queue_io_enq_valid_T_1 = and(_load_info_queue_io_enq_valid_T, buf_info_queue.io.enq.ready) connect load_info_queue.io.enq.valid, _load_info_queue_io_enq_valid_T_1 connect buf_info_queue.io.enq.bits.len_bytes, io.src_info.bits.isize node _io_l2helperUser_req_bits_addr_T = shl(addrinc, 5) node _io_l2helperUser_req_bits_addr_T_1 = add(base_addr_bytes_aligned, _io_l2helperUser_req_bits_addr_T) node _io_l2helperUser_req_bits_addr_T_2 = tail(_io_l2helperUser_req_bits_addr_T_1, 1) connect io.l2helperUser.req.bits.addr, _io_l2helperUser_req_bits_addr_T_2 node _io_l2helperUser_req_valid_T = and(io.src_info.valid, buf_info_queue.io.enq.ready) node _io_l2helperUser_req_valid_T_1 = and(_io_l2helperUser_req_valid_T, load_info_queue.io.enq.ready) connect io.l2helperUser.req.valid, _io_l2helperUser_req_valid_T_1 regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0) inst Queue32_UInt8 of Queue32_UInt8 connect Queue32_UInt8.clock, clock connect Queue32_UInt8.reset, reset inst Queue32_UInt8_1 of Queue32_UInt8_1 connect Queue32_UInt8_1.clock, clock connect Queue32_UInt8_1.reset, reset inst Queue32_UInt8_2 of Queue32_UInt8_2 connect Queue32_UInt8_2.clock, clock connect Queue32_UInt8_2.reset, reset inst Queue32_UInt8_3 of Queue32_UInt8_3 connect Queue32_UInt8_3.clock, clock connect Queue32_UInt8_3.reset, reset inst Queue32_UInt8_4 of Queue32_UInt8_4 connect Queue32_UInt8_4.clock, clock connect Queue32_UInt8_4.reset, reset inst Queue32_UInt8_5 of Queue32_UInt8_5 connect Queue32_UInt8_5.clock, clock connect Queue32_UInt8_5.reset, reset inst Queue32_UInt8_6 of Queue32_UInt8_6 connect Queue32_UInt8_6.clock, clock connect Queue32_UInt8_6.reset, reset inst Queue32_UInt8_7 of Queue32_UInt8_7 connect Queue32_UInt8_7.clock, clock connect Queue32_UInt8_7.reset, reset inst Queue32_UInt8_8 of Queue32_UInt8_8 connect Queue32_UInt8_8.clock, clock connect Queue32_UInt8_8.reset, reset inst Queue32_UInt8_9 of Queue32_UInt8_9 connect Queue32_UInt8_9.clock, clock connect Queue32_UInt8_9.reset, reset inst Queue32_UInt8_10 of Queue32_UInt8_10 connect Queue32_UInt8_10.clock, clock connect Queue32_UInt8_10.reset, reset inst Queue32_UInt8_11 of Queue32_UInt8_11 connect Queue32_UInt8_11.clock, clock connect Queue32_UInt8_11.reset, reset inst Queue32_UInt8_12 of Queue32_UInt8_12 connect Queue32_UInt8_12.clock, clock connect Queue32_UInt8_12.reset, reset inst Queue32_UInt8_13 of Queue32_UInt8_13 connect Queue32_UInt8_13.clock, clock connect Queue32_UInt8_13.reset, reset inst Queue32_UInt8_14 of Queue32_UInt8_14 connect Queue32_UInt8_14.clock, clock connect Queue32_UInt8_14.reset, reset inst Queue32_UInt8_15 of Queue32_UInt8_15 connect Queue32_UInt8_15.clock, clock connect Queue32_UInt8_15.reset, reset inst Queue32_UInt8_16 of Queue32_UInt8_16 connect Queue32_UInt8_16.clock, clock connect Queue32_UInt8_16.reset, reset inst Queue32_UInt8_17 of Queue32_UInt8_17 connect Queue32_UInt8_17.clock, clock connect Queue32_UInt8_17.reset, reset inst Queue32_UInt8_18 of Queue32_UInt8_18 connect Queue32_UInt8_18.clock, clock connect Queue32_UInt8_18.reset, reset inst Queue32_UInt8_19 of Queue32_UInt8_19 connect Queue32_UInt8_19.clock, clock connect Queue32_UInt8_19.reset, reset inst Queue32_UInt8_20 of Queue32_UInt8_20 connect Queue32_UInt8_20.clock, clock connect Queue32_UInt8_20.reset, reset inst Queue32_UInt8_21 of Queue32_UInt8_21 connect Queue32_UInt8_21.clock, clock connect Queue32_UInt8_21.reset, reset inst Queue32_UInt8_22 of Queue32_UInt8_22 connect Queue32_UInt8_22.clock, clock connect Queue32_UInt8_22.reset, reset inst Queue32_UInt8_23 of Queue32_UInt8_23 connect Queue32_UInt8_23.clock, clock connect Queue32_UInt8_23.reset, reset inst Queue32_UInt8_24 of Queue32_UInt8_24 connect Queue32_UInt8_24.clock, clock connect Queue32_UInt8_24.reset, reset inst Queue32_UInt8_25 of Queue32_UInt8_25 connect Queue32_UInt8_25.clock, clock connect Queue32_UInt8_25.reset, reset inst Queue32_UInt8_26 of Queue32_UInt8_26 connect Queue32_UInt8_26.clock, clock connect Queue32_UInt8_26.reset, reset inst Queue32_UInt8_27 of Queue32_UInt8_27 connect Queue32_UInt8_27.clock, clock connect Queue32_UInt8_27.reset, reset inst Queue32_UInt8_28 of Queue32_UInt8_28 connect Queue32_UInt8_28.clock, clock connect Queue32_UInt8_28.reset, reset inst Queue32_UInt8_29 of Queue32_UInt8_29 connect Queue32_UInt8_29.clock, clock connect Queue32_UInt8_29.reset, reset inst Queue32_UInt8_30 of Queue32_UInt8_30 connect Queue32_UInt8_30.clock, clock connect Queue32_UInt8_30.reset, reset inst Queue32_UInt8_31 of Queue32_UInt8_31 connect Queue32_UInt8_31.clock, clock connect Queue32_UInt8_31.reset, reset inst Queue32_UInt8_32 of Queue32_UInt8_32 connect Queue32_UInt8_32.clock, clock connect Queue32_UInt8_32.reset, reset inst Queue32_UInt8_33 of Queue32_UInt8_33 connect Queue32_UInt8_33.clock, clock connect Queue32_UInt8_33.reset, reset inst Queue32_UInt8_34 of Queue32_UInt8_34 connect Queue32_UInt8_34.clock, clock connect Queue32_UInt8_34.reset, reset inst Queue32_UInt8_35 of Queue32_UInt8_35 connect Queue32_UInt8_35.clock, clock connect Queue32_UInt8_35.reset, reset inst Queue32_UInt8_36 of Queue32_UInt8_36 connect Queue32_UInt8_36.clock, clock connect Queue32_UInt8_36.reset, reset inst Queue32_UInt8_37 of Queue32_UInt8_37 connect Queue32_UInt8_37.clock, clock connect Queue32_UInt8_37.reset, reset inst Queue32_UInt8_38 of Queue32_UInt8_38 connect Queue32_UInt8_38.clock, clock connect Queue32_UInt8_38.reset, reset inst Queue32_UInt8_39 of Queue32_UInt8_39 connect Queue32_UInt8_39.clock, clock connect Queue32_UInt8_39.reset, reset inst Queue32_UInt8_40 of Queue32_UInt8_40 connect Queue32_UInt8_40.clock, clock connect Queue32_UInt8_40.reset, reset inst Queue32_UInt8_41 of Queue32_UInt8_41 connect Queue32_UInt8_41.clock, clock connect Queue32_UInt8_41.reset, reset inst Queue32_UInt8_42 of Queue32_UInt8_42 connect Queue32_UInt8_42.clock, clock connect Queue32_UInt8_42.reset, reset inst Queue32_UInt8_43 of Queue32_UInt8_43 connect Queue32_UInt8_43.clock, clock connect Queue32_UInt8_43.reset, reset inst Queue32_UInt8_44 of Queue32_UInt8_44 connect Queue32_UInt8_44.clock, clock connect Queue32_UInt8_44.reset, reset inst Queue32_UInt8_45 of Queue32_UInt8_45 connect Queue32_UInt8_45.clock, clock connect Queue32_UInt8_45.reset, reset inst Queue32_UInt8_46 of Queue32_UInt8_46 connect Queue32_UInt8_46.clock, clock connect Queue32_UInt8_46.reset, reset inst Queue32_UInt8_47 of Queue32_UInt8_47 connect Queue32_UInt8_47.clock, clock connect Queue32_UInt8_47.reset, reset inst Queue32_UInt8_48 of Queue32_UInt8_48 connect Queue32_UInt8_48.clock, clock connect Queue32_UInt8_48.reset, reset inst Queue32_UInt8_49 of Queue32_UInt8_49 connect Queue32_UInt8_49.clock, clock connect Queue32_UInt8_49.reset, reset inst Queue32_UInt8_50 of Queue32_UInt8_50 connect Queue32_UInt8_50.clock, clock connect Queue32_UInt8_50.reset, reset inst Queue32_UInt8_51 of Queue32_UInt8_51 connect Queue32_UInt8_51.clock, clock connect Queue32_UInt8_51.reset, reset inst Queue32_UInt8_52 of Queue32_UInt8_52 connect Queue32_UInt8_52.clock, clock connect Queue32_UInt8_52.reset, reset inst Queue32_UInt8_53 of Queue32_UInt8_53 connect Queue32_UInt8_53.clock, clock connect Queue32_UInt8_53.reset, reset inst Queue32_UInt8_54 of Queue32_UInt8_54 connect Queue32_UInt8_54.clock, clock connect Queue32_UInt8_54.reset, reset inst Queue32_UInt8_55 of Queue32_UInt8_55 connect Queue32_UInt8_55.clock, clock connect Queue32_UInt8_55.reset, reset inst Queue32_UInt8_56 of Queue32_UInt8_56 connect Queue32_UInt8_56.clock, clock connect Queue32_UInt8_56.reset, reset inst Queue32_UInt8_57 of Queue32_UInt8_57 connect Queue32_UInt8_57.clock, clock connect Queue32_UInt8_57.reset, reset inst Queue32_UInt8_58 of Queue32_UInt8_58 connect Queue32_UInt8_58.clock, clock connect Queue32_UInt8_58.reset, reset inst Queue32_UInt8_59 of Queue32_UInt8_59 connect Queue32_UInt8_59.clock, clock connect Queue32_UInt8_59.reset, reset inst Queue32_UInt8_60 of Queue32_UInt8_60 connect Queue32_UInt8_60.clock, clock connect Queue32_UInt8_60.reset, reset inst Queue32_UInt8_61 of Queue32_UInt8_61 connect Queue32_UInt8_61.clock, clock connect Queue32_UInt8_61.reset, reset inst Queue32_UInt8_62 of Queue32_UInt8_62 connect Queue32_UInt8_62.clock, clock connect Queue32_UInt8_62.reset, reset inst Queue32_UInt8_63 of Queue32_UInt8_63 connect Queue32_UInt8_63.clock, clock connect Queue32_UInt8_63.reset, reset connect Queue32_UInt8_32.io.enq, Queue32_UInt8.io.deq invalidate Queue32_UInt8_32.io.deq.ready connect Queue32_UInt8_33.io.enq, Queue32_UInt8_1.io.deq invalidate Queue32_UInt8_33.io.deq.ready connect Queue32_UInt8_34.io.enq, Queue32_UInt8_2.io.deq invalidate Queue32_UInt8_34.io.deq.ready connect Queue32_UInt8_35.io.enq, Queue32_UInt8_3.io.deq invalidate Queue32_UInt8_35.io.deq.ready connect Queue32_UInt8_36.io.enq, Queue32_UInt8_4.io.deq invalidate Queue32_UInt8_36.io.deq.ready connect Queue32_UInt8_37.io.enq, Queue32_UInt8_5.io.deq invalidate Queue32_UInt8_37.io.deq.ready connect Queue32_UInt8_38.io.enq, Queue32_UInt8_6.io.deq invalidate Queue32_UInt8_38.io.deq.ready connect Queue32_UInt8_39.io.enq, Queue32_UInt8_7.io.deq invalidate Queue32_UInt8_39.io.deq.ready connect Queue32_UInt8_40.io.enq, Queue32_UInt8_8.io.deq invalidate Queue32_UInt8_40.io.deq.ready connect Queue32_UInt8_41.io.enq, Queue32_UInt8_9.io.deq invalidate Queue32_UInt8_41.io.deq.ready connect Queue32_UInt8_42.io.enq, Queue32_UInt8_10.io.deq invalidate Queue32_UInt8_42.io.deq.ready connect Queue32_UInt8_43.io.enq, Queue32_UInt8_11.io.deq invalidate Queue32_UInt8_43.io.deq.ready connect Queue32_UInt8_44.io.enq, Queue32_UInt8_12.io.deq invalidate Queue32_UInt8_44.io.deq.ready connect Queue32_UInt8_45.io.enq, Queue32_UInt8_13.io.deq invalidate Queue32_UInt8_45.io.deq.ready connect Queue32_UInt8_46.io.enq, Queue32_UInt8_14.io.deq invalidate Queue32_UInt8_46.io.deq.ready connect Queue32_UInt8_47.io.enq, Queue32_UInt8_15.io.deq invalidate Queue32_UInt8_47.io.deq.ready connect Queue32_UInt8_48.io.enq, Queue32_UInt8_16.io.deq invalidate Queue32_UInt8_48.io.deq.ready connect Queue32_UInt8_49.io.enq, Queue32_UInt8_17.io.deq invalidate Queue32_UInt8_49.io.deq.ready connect Queue32_UInt8_50.io.enq, Queue32_UInt8_18.io.deq invalidate Queue32_UInt8_50.io.deq.ready connect Queue32_UInt8_51.io.enq, Queue32_UInt8_19.io.deq invalidate Queue32_UInt8_51.io.deq.ready connect Queue32_UInt8_52.io.enq, Queue32_UInt8_20.io.deq invalidate Queue32_UInt8_52.io.deq.ready connect Queue32_UInt8_53.io.enq, Queue32_UInt8_21.io.deq invalidate Queue32_UInt8_53.io.deq.ready connect Queue32_UInt8_54.io.enq, Queue32_UInt8_22.io.deq invalidate Queue32_UInt8_54.io.deq.ready connect Queue32_UInt8_55.io.enq, Queue32_UInt8_23.io.deq invalidate Queue32_UInt8_55.io.deq.ready connect Queue32_UInt8_56.io.enq, Queue32_UInt8_24.io.deq invalidate Queue32_UInt8_56.io.deq.ready connect Queue32_UInt8_57.io.enq, Queue32_UInt8_25.io.deq invalidate Queue32_UInt8_57.io.deq.ready connect Queue32_UInt8_58.io.enq, Queue32_UInt8_26.io.deq invalidate Queue32_UInt8_58.io.deq.ready connect Queue32_UInt8_59.io.enq, Queue32_UInt8_27.io.deq invalidate Queue32_UInt8_59.io.deq.ready connect Queue32_UInt8_60.io.enq, Queue32_UInt8_28.io.deq invalidate Queue32_UInt8_60.io.deq.ready connect Queue32_UInt8_61.io.enq, Queue32_UInt8_29.io.deq invalidate Queue32_UInt8_61.io.deq.ready connect Queue32_UInt8_62.io.enq, Queue32_UInt8_30.io.deq invalidate Queue32_UInt8_62.io.deq.ready connect Queue32_UInt8_63.io.enq, Queue32_UInt8_31.io.deq invalidate Queue32_UInt8_63.io.deq.ready node align_shamt = shl(load_info_queue.io.deq.bits.start_byte, 3) node memresp_bits_shifted = dshr(io.l2helperUser.resp.bits.data, align_shamt) connect Queue32_UInt8.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_1.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_2.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_3.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_4.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_5.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_6.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_7.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_8.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_9.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_10.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_11.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_12.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_13.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_14.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_15.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_16.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_17.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_18.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_19.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_20.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_21.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_22.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_23.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_24.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_25.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_26.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_27.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_28.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_29.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_30.io.enq.bits, UInt<1>(0h0) connect Queue32_UInt8_31.io.enq.bits, UInt<1>(0h0) node _idx_T = add(write_start_index, UInt<1>(0h0)) node idx = rem(_idx_T, UInt<6>(0h20)) node _T_54 = eq(UInt<1>(0h0), idx) when _T_54 : node _T_55 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8.io.enq.bits, _T_55 node _T_56 = eq(UInt<1>(0h1), idx) when _T_56 : node _T_57 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_1.io.enq.bits, _T_57 node _T_58 = eq(UInt<2>(0h2), idx) when _T_58 : node _T_59 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_2.io.enq.bits, _T_59 node _T_60 = eq(UInt<2>(0h3), idx) when _T_60 : node _T_61 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_3.io.enq.bits, _T_61 node _T_62 = eq(UInt<3>(0h4), idx) when _T_62 : node _T_63 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_4.io.enq.bits, _T_63 node _T_64 = eq(UInt<3>(0h5), idx) when _T_64 : node _T_65 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_5.io.enq.bits, _T_65 node _T_66 = eq(UInt<3>(0h6), idx) when _T_66 : node _T_67 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_6.io.enq.bits, _T_67 node _T_68 = eq(UInt<3>(0h7), idx) when _T_68 : node _T_69 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_7.io.enq.bits, _T_69 node _T_70 = eq(UInt<4>(0h8), idx) when _T_70 : node _T_71 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_8.io.enq.bits, _T_71 node _T_72 = eq(UInt<4>(0h9), idx) when _T_72 : node _T_73 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_9.io.enq.bits, _T_73 node _T_74 = eq(UInt<4>(0ha), idx) when _T_74 : node _T_75 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_10.io.enq.bits, _T_75 node _T_76 = eq(UInt<4>(0hb), idx) when _T_76 : node _T_77 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_11.io.enq.bits, _T_77 node _T_78 = eq(UInt<4>(0hc), idx) when _T_78 : node _T_79 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_12.io.enq.bits, _T_79 node _T_80 = eq(UInt<4>(0hd), idx) when _T_80 : node _T_81 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_13.io.enq.bits, _T_81 node _T_82 = eq(UInt<4>(0he), idx) when _T_82 : node _T_83 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_14.io.enq.bits, _T_83 node _T_84 = eq(UInt<4>(0hf), idx) when _T_84 : node _T_85 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_15.io.enq.bits, _T_85 node _T_86 = eq(UInt<5>(0h10), idx) when _T_86 : node _T_87 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_16.io.enq.bits, _T_87 node _T_88 = eq(UInt<5>(0h11), idx) when _T_88 : node _T_89 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_17.io.enq.bits, _T_89 node _T_90 = eq(UInt<5>(0h12), idx) when _T_90 : node _T_91 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_18.io.enq.bits, _T_91 node _T_92 = eq(UInt<5>(0h13), idx) when _T_92 : node _T_93 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_19.io.enq.bits, _T_93 node _T_94 = eq(UInt<5>(0h14), idx) when _T_94 : node _T_95 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_20.io.enq.bits, _T_95 node _T_96 = eq(UInt<5>(0h15), idx) when _T_96 : node _T_97 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_21.io.enq.bits, _T_97 node _T_98 = eq(UInt<5>(0h16), idx) when _T_98 : node _T_99 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_22.io.enq.bits, _T_99 node _T_100 = eq(UInt<5>(0h17), idx) when _T_100 : node _T_101 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_23.io.enq.bits, _T_101 node _T_102 = eq(UInt<5>(0h18), idx) when _T_102 : node _T_103 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_24.io.enq.bits, _T_103 node _T_104 = eq(UInt<5>(0h19), idx) when _T_104 : node _T_105 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_25.io.enq.bits, _T_105 node _T_106 = eq(UInt<5>(0h1a), idx) when _T_106 : node _T_107 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_26.io.enq.bits, _T_107 node _T_108 = eq(UInt<5>(0h1b), idx) when _T_108 : node _T_109 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_27.io.enq.bits, _T_109 node _T_110 = eq(UInt<5>(0h1c), idx) when _T_110 : node _T_111 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_28.io.enq.bits, _T_111 node _T_112 = eq(UInt<5>(0h1d), idx) when _T_112 : node _T_113 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_29.io.enq.bits, _T_113 node _T_114 = eq(UInt<5>(0h1e), idx) when _T_114 : node _T_115 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_30.io.enq.bits, _T_115 node _T_116 = eq(UInt<5>(0h1f), idx) when _T_116 : node _T_117 = shr(memresp_bits_shifted, 0) connect Queue32_UInt8_31.io.enq.bits, _T_117 node _idx_T_1 = add(write_start_index, UInt<1>(0h1)) node idx_1 = rem(_idx_T_1, UInt<6>(0h20)) node _T_118 = eq(UInt<1>(0h0), idx_1) when _T_118 : node _T_119 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8.io.enq.bits, _T_119 node _T_120 = eq(UInt<1>(0h1), idx_1) when _T_120 : node _T_121 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_1.io.enq.bits, _T_121 node _T_122 = eq(UInt<2>(0h2), idx_1) when _T_122 : node _T_123 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_2.io.enq.bits, _T_123 node _T_124 = eq(UInt<2>(0h3), idx_1) when _T_124 : node _T_125 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_3.io.enq.bits, _T_125 node _T_126 = eq(UInt<3>(0h4), idx_1) when _T_126 : node _T_127 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_4.io.enq.bits, _T_127 node _T_128 = eq(UInt<3>(0h5), idx_1) when _T_128 : node _T_129 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_5.io.enq.bits, _T_129 node _T_130 = eq(UInt<3>(0h6), idx_1) when _T_130 : node _T_131 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_6.io.enq.bits, _T_131 node _T_132 = eq(UInt<3>(0h7), idx_1) when _T_132 : node _T_133 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_7.io.enq.bits, _T_133 node _T_134 = eq(UInt<4>(0h8), idx_1) when _T_134 : node _T_135 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_8.io.enq.bits, _T_135 node _T_136 = eq(UInt<4>(0h9), idx_1) when _T_136 : node _T_137 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_9.io.enq.bits, _T_137 node _T_138 = eq(UInt<4>(0ha), idx_1) when _T_138 : node _T_139 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_10.io.enq.bits, _T_139 node _T_140 = eq(UInt<4>(0hb), idx_1) when _T_140 : node _T_141 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_11.io.enq.bits, _T_141 node _T_142 = eq(UInt<4>(0hc), idx_1) when _T_142 : node _T_143 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_12.io.enq.bits, _T_143 node _T_144 = eq(UInt<4>(0hd), idx_1) when _T_144 : node _T_145 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_13.io.enq.bits, _T_145 node _T_146 = eq(UInt<4>(0he), idx_1) when _T_146 : node _T_147 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_14.io.enq.bits, _T_147 node _T_148 = eq(UInt<4>(0hf), idx_1) when _T_148 : node _T_149 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_15.io.enq.bits, _T_149 node _T_150 = eq(UInt<5>(0h10), idx_1) when _T_150 : node _T_151 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_16.io.enq.bits, _T_151 node _T_152 = eq(UInt<5>(0h11), idx_1) when _T_152 : node _T_153 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_17.io.enq.bits, _T_153 node _T_154 = eq(UInt<5>(0h12), idx_1) when _T_154 : node _T_155 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_18.io.enq.bits, _T_155 node _T_156 = eq(UInt<5>(0h13), idx_1) when _T_156 : node _T_157 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_19.io.enq.bits, _T_157 node _T_158 = eq(UInt<5>(0h14), idx_1) when _T_158 : node _T_159 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_20.io.enq.bits, _T_159 node _T_160 = eq(UInt<5>(0h15), idx_1) when _T_160 : node _T_161 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_21.io.enq.bits, _T_161 node _T_162 = eq(UInt<5>(0h16), idx_1) when _T_162 : node _T_163 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_22.io.enq.bits, _T_163 node _T_164 = eq(UInt<5>(0h17), idx_1) when _T_164 : node _T_165 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_23.io.enq.bits, _T_165 node _T_166 = eq(UInt<5>(0h18), idx_1) when _T_166 : node _T_167 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_24.io.enq.bits, _T_167 node _T_168 = eq(UInt<5>(0h19), idx_1) when _T_168 : node _T_169 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_25.io.enq.bits, _T_169 node _T_170 = eq(UInt<5>(0h1a), idx_1) when _T_170 : node _T_171 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_26.io.enq.bits, _T_171 node _T_172 = eq(UInt<5>(0h1b), idx_1) when _T_172 : node _T_173 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_27.io.enq.bits, _T_173 node _T_174 = eq(UInt<5>(0h1c), idx_1) when _T_174 : node _T_175 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_28.io.enq.bits, _T_175 node _T_176 = eq(UInt<5>(0h1d), idx_1) when _T_176 : node _T_177 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_29.io.enq.bits, _T_177 node _T_178 = eq(UInt<5>(0h1e), idx_1) when _T_178 : node _T_179 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_30.io.enq.bits, _T_179 node _T_180 = eq(UInt<5>(0h1f), idx_1) when _T_180 : node _T_181 = shr(memresp_bits_shifted, 8) connect Queue32_UInt8_31.io.enq.bits, _T_181 node _idx_T_2 = add(write_start_index, UInt<2>(0h2)) node idx_2 = rem(_idx_T_2, UInt<6>(0h20)) node _T_182 = eq(UInt<1>(0h0), idx_2) when _T_182 : node _T_183 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8.io.enq.bits, _T_183 node _T_184 = eq(UInt<1>(0h1), idx_2) when _T_184 : node _T_185 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_1.io.enq.bits, _T_185 node _T_186 = eq(UInt<2>(0h2), idx_2) when _T_186 : node _T_187 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_2.io.enq.bits, _T_187 node _T_188 = eq(UInt<2>(0h3), idx_2) when _T_188 : node _T_189 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_3.io.enq.bits, _T_189 node _T_190 = eq(UInt<3>(0h4), idx_2) when _T_190 : node _T_191 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_4.io.enq.bits, _T_191 node _T_192 = eq(UInt<3>(0h5), idx_2) when _T_192 : node _T_193 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_5.io.enq.bits, _T_193 node _T_194 = eq(UInt<3>(0h6), idx_2) when _T_194 : node _T_195 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_6.io.enq.bits, _T_195 node _T_196 = eq(UInt<3>(0h7), idx_2) when _T_196 : node _T_197 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_7.io.enq.bits, _T_197 node _T_198 = eq(UInt<4>(0h8), idx_2) when _T_198 : node _T_199 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_8.io.enq.bits, _T_199 node _T_200 = eq(UInt<4>(0h9), idx_2) when _T_200 : node _T_201 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_9.io.enq.bits, _T_201 node _T_202 = eq(UInt<4>(0ha), idx_2) when _T_202 : node _T_203 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_10.io.enq.bits, _T_203 node _T_204 = eq(UInt<4>(0hb), idx_2) when _T_204 : node _T_205 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_11.io.enq.bits, _T_205 node _T_206 = eq(UInt<4>(0hc), idx_2) when _T_206 : node _T_207 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_12.io.enq.bits, _T_207 node _T_208 = eq(UInt<4>(0hd), idx_2) when _T_208 : node _T_209 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_13.io.enq.bits, _T_209 node _T_210 = eq(UInt<4>(0he), idx_2) when _T_210 : node _T_211 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_14.io.enq.bits, _T_211 node _T_212 = eq(UInt<4>(0hf), idx_2) when _T_212 : node _T_213 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_15.io.enq.bits, _T_213 node _T_214 = eq(UInt<5>(0h10), idx_2) when _T_214 : node _T_215 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_16.io.enq.bits, _T_215 node _T_216 = eq(UInt<5>(0h11), idx_2) when _T_216 : node _T_217 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_17.io.enq.bits, _T_217 node _T_218 = eq(UInt<5>(0h12), idx_2) when _T_218 : node _T_219 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_18.io.enq.bits, _T_219 node _T_220 = eq(UInt<5>(0h13), idx_2) when _T_220 : node _T_221 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_19.io.enq.bits, _T_221 node _T_222 = eq(UInt<5>(0h14), idx_2) when _T_222 : node _T_223 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_20.io.enq.bits, _T_223 node _T_224 = eq(UInt<5>(0h15), idx_2) when _T_224 : node _T_225 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_21.io.enq.bits, _T_225 node _T_226 = eq(UInt<5>(0h16), idx_2) when _T_226 : node _T_227 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_22.io.enq.bits, _T_227 node _T_228 = eq(UInt<5>(0h17), idx_2) when _T_228 : node _T_229 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_23.io.enq.bits, _T_229 node _T_230 = eq(UInt<5>(0h18), idx_2) when _T_230 : node _T_231 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_24.io.enq.bits, _T_231 node _T_232 = eq(UInt<5>(0h19), idx_2) when _T_232 : node _T_233 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_25.io.enq.bits, _T_233 node _T_234 = eq(UInt<5>(0h1a), idx_2) when _T_234 : node _T_235 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_26.io.enq.bits, _T_235 node _T_236 = eq(UInt<5>(0h1b), idx_2) when _T_236 : node _T_237 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_27.io.enq.bits, _T_237 node _T_238 = eq(UInt<5>(0h1c), idx_2) when _T_238 : node _T_239 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_28.io.enq.bits, _T_239 node _T_240 = eq(UInt<5>(0h1d), idx_2) when _T_240 : node _T_241 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_29.io.enq.bits, _T_241 node _T_242 = eq(UInt<5>(0h1e), idx_2) when _T_242 : node _T_243 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_30.io.enq.bits, _T_243 node _T_244 = eq(UInt<5>(0h1f), idx_2) when _T_244 : node _T_245 = shr(memresp_bits_shifted, 16) connect Queue32_UInt8_31.io.enq.bits, _T_245 node _idx_T_3 = add(write_start_index, UInt<2>(0h3)) node idx_3 = rem(_idx_T_3, UInt<6>(0h20)) node _T_246 = eq(UInt<1>(0h0), idx_3) when _T_246 : node _T_247 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8.io.enq.bits, _T_247 node _T_248 = eq(UInt<1>(0h1), idx_3) when _T_248 : node _T_249 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_1.io.enq.bits, _T_249 node _T_250 = eq(UInt<2>(0h2), idx_3) when _T_250 : node _T_251 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_2.io.enq.bits, _T_251 node _T_252 = eq(UInt<2>(0h3), idx_3) when _T_252 : node _T_253 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_3.io.enq.bits, _T_253 node _T_254 = eq(UInt<3>(0h4), idx_3) when _T_254 : node _T_255 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_4.io.enq.bits, _T_255 node _T_256 = eq(UInt<3>(0h5), idx_3) when _T_256 : node _T_257 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_5.io.enq.bits, _T_257 node _T_258 = eq(UInt<3>(0h6), idx_3) when _T_258 : node _T_259 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_6.io.enq.bits, _T_259 node _T_260 = eq(UInt<3>(0h7), idx_3) when _T_260 : node _T_261 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_7.io.enq.bits, _T_261 node _T_262 = eq(UInt<4>(0h8), idx_3) when _T_262 : node _T_263 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_8.io.enq.bits, _T_263 node _T_264 = eq(UInt<4>(0h9), idx_3) when _T_264 : node _T_265 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_9.io.enq.bits, _T_265 node _T_266 = eq(UInt<4>(0ha), idx_3) when _T_266 : node _T_267 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_10.io.enq.bits, _T_267 node _T_268 = eq(UInt<4>(0hb), idx_3) when _T_268 : node _T_269 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_11.io.enq.bits, _T_269 node _T_270 = eq(UInt<4>(0hc), idx_3) when _T_270 : node _T_271 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_12.io.enq.bits, _T_271 node _T_272 = eq(UInt<4>(0hd), idx_3) when _T_272 : node _T_273 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_13.io.enq.bits, _T_273 node _T_274 = eq(UInt<4>(0he), idx_3) when _T_274 : node _T_275 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_14.io.enq.bits, _T_275 node _T_276 = eq(UInt<4>(0hf), idx_3) when _T_276 : node _T_277 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_15.io.enq.bits, _T_277 node _T_278 = eq(UInt<5>(0h10), idx_3) when _T_278 : node _T_279 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_16.io.enq.bits, _T_279 node _T_280 = eq(UInt<5>(0h11), idx_3) when _T_280 : node _T_281 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_17.io.enq.bits, _T_281 node _T_282 = eq(UInt<5>(0h12), idx_3) when _T_282 : node _T_283 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_18.io.enq.bits, _T_283 node _T_284 = eq(UInt<5>(0h13), idx_3) when _T_284 : node _T_285 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_19.io.enq.bits, _T_285 node _T_286 = eq(UInt<5>(0h14), idx_3) when _T_286 : node _T_287 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_20.io.enq.bits, _T_287 node _T_288 = eq(UInt<5>(0h15), idx_3) when _T_288 : node _T_289 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_21.io.enq.bits, _T_289 node _T_290 = eq(UInt<5>(0h16), idx_3) when _T_290 : node _T_291 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_22.io.enq.bits, _T_291 node _T_292 = eq(UInt<5>(0h17), idx_3) when _T_292 : node _T_293 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_23.io.enq.bits, _T_293 node _T_294 = eq(UInt<5>(0h18), idx_3) when _T_294 : node _T_295 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_24.io.enq.bits, _T_295 node _T_296 = eq(UInt<5>(0h19), idx_3) when _T_296 : node _T_297 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_25.io.enq.bits, _T_297 node _T_298 = eq(UInt<5>(0h1a), idx_3) when _T_298 : node _T_299 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_26.io.enq.bits, _T_299 node _T_300 = eq(UInt<5>(0h1b), idx_3) when _T_300 : node _T_301 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_27.io.enq.bits, _T_301 node _T_302 = eq(UInt<5>(0h1c), idx_3) when _T_302 : node _T_303 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_28.io.enq.bits, _T_303 node _T_304 = eq(UInt<5>(0h1d), idx_3) when _T_304 : node _T_305 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_29.io.enq.bits, _T_305 node _T_306 = eq(UInt<5>(0h1e), idx_3) when _T_306 : node _T_307 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_30.io.enq.bits, _T_307 node _T_308 = eq(UInt<5>(0h1f), idx_3) when _T_308 : node _T_309 = shr(memresp_bits_shifted, 24) connect Queue32_UInt8_31.io.enq.bits, _T_309 node _idx_T_4 = add(write_start_index, UInt<3>(0h4)) node idx_4 = rem(_idx_T_4, UInt<6>(0h20)) node _T_310 = eq(UInt<1>(0h0), idx_4) when _T_310 : node _T_311 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8.io.enq.bits, _T_311 node _T_312 = eq(UInt<1>(0h1), idx_4) when _T_312 : node _T_313 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_1.io.enq.bits, _T_313 node _T_314 = eq(UInt<2>(0h2), idx_4) when _T_314 : node _T_315 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_2.io.enq.bits, _T_315 node _T_316 = eq(UInt<2>(0h3), idx_4) when _T_316 : node _T_317 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_3.io.enq.bits, _T_317 node _T_318 = eq(UInt<3>(0h4), idx_4) when _T_318 : node _T_319 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_4.io.enq.bits, _T_319 node _T_320 = eq(UInt<3>(0h5), idx_4) when _T_320 : node _T_321 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_5.io.enq.bits, _T_321 node _T_322 = eq(UInt<3>(0h6), idx_4) when _T_322 : node _T_323 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_6.io.enq.bits, _T_323 node _T_324 = eq(UInt<3>(0h7), idx_4) when _T_324 : node _T_325 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_7.io.enq.bits, _T_325 node _T_326 = eq(UInt<4>(0h8), idx_4) when _T_326 : node _T_327 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_8.io.enq.bits, _T_327 node _T_328 = eq(UInt<4>(0h9), idx_4) when _T_328 : node _T_329 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_9.io.enq.bits, _T_329 node _T_330 = eq(UInt<4>(0ha), idx_4) when _T_330 : node _T_331 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_10.io.enq.bits, _T_331 node _T_332 = eq(UInt<4>(0hb), idx_4) when _T_332 : node _T_333 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_11.io.enq.bits, _T_333 node _T_334 = eq(UInt<4>(0hc), idx_4) when _T_334 : node _T_335 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_12.io.enq.bits, _T_335 node _T_336 = eq(UInt<4>(0hd), idx_4) when _T_336 : node _T_337 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_13.io.enq.bits, _T_337 node _T_338 = eq(UInt<4>(0he), idx_4) when _T_338 : node _T_339 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_14.io.enq.bits, _T_339 node _T_340 = eq(UInt<4>(0hf), idx_4) when _T_340 : node _T_341 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_15.io.enq.bits, _T_341 node _T_342 = eq(UInt<5>(0h10), idx_4) when _T_342 : node _T_343 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_16.io.enq.bits, _T_343 node _T_344 = eq(UInt<5>(0h11), idx_4) when _T_344 : node _T_345 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_17.io.enq.bits, _T_345 node _T_346 = eq(UInt<5>(0h12), idx_4) when _T_346 : node _T_347 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_18.io.enq.bits, _T_347 node _T_348 = eq(UInt<5>(0h13), idx_4) when _T_348 : node _T_349 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_19.io.enq.bits, _T_349 node _T_350 = eq(UInt<5>(0h14), idx_4) when _T_350 : node _T_351 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_20.io.enq.bits, _T_351 node _T_352 = eq(UInt<5>(0h15), idx_4) when _T_352 : node _T_353 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_21.io.enq.bits, _T_353 node _T_354 = eq(UInt<5>(0h16), idx_4) when _T_354 : node _T_355 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_22.io.enq.bits, _T_355 node _T_356 = eq(UInt<5>(0h17), idx_4) when _T_356 : node _T_357 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_23.io.enq.bits, _T_357 node _T_358 = eq(UInt<5>(0h18), idx_4) when _T_358 : node _T_359 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_24.io.enq.bits, _T_359 node _T_360 = eq(UInt<5>(0h19), idx_4) when _T_360 : node _T_361 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_25.io.enq.bits, _T_361 node _T_362 = eq(UInt<5>(0h1a), idx_4) when _T_362 : node _T_363 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_26.io.enq.bits, _T_363 node _T_364 = eq(UInt<5>(0h1b), idx_4) when _T_364 : node _T_365 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_27.io.enq.bits, _T_365 node _T_366 = eq(UInt<5>(0h1c), idx_4) when _T_366 : node _T_367 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_28.io.enq.bits, _T_367 node _T_368 = eq(UInt<5>(0h1d), idx_4) when _T_368 : node _T_369 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_29.io.enq.bits, _T_369 node _T_370 = eq(UInt<5>(0h1e), idx_4) when _T_370 : node _T_371 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_30.io.enq.bits, _T_371 node _T_372 = eq(UInt<5>(0h1f), idx_4) when _T_372 : node _T_373 = shr(memresp_bits_shifted, 32) connect Queue32_UInt8_31.io.enq.bits, _T_373 node _idx_T_5 = add(write_start_index, UInt<3>(0h5)) node idx_5 = rem(_idx_T_5, UInt<6>(0h20)) node _T_374 = eq(UInt<1>(0h0), idx_5) when _T_374 : node _T_375 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8.io.enq.bits, _T_375 node _T_376 = eq(UInt<1>(0h1), idx_5) when _T_376 : node _T_377 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_1.io.enq.bits, _T_377 node _T_378 = eq(UInt<2>(0h2), idx_5) when _T_378 : node _T_379 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_2.io.enq.bits, _T_379 node _T_380 = eq(UInt<2>(0h3), idx_5) when _T_380 : node _T_381 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_3.io.enq.bits, _T_381 node _T_382 = eq(UInt<3>(0h4), idx_5) when _T_382 : node _T_383 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_4.io.enq.bits, _T_383 node _T_384 = eq(UInt<3>(0h5), idx_5) when _T_384 : node _T_385 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_5.io.enq.bits, _T_385 node _T_386 = eq(UInt<3>(0h6), idx_5) when _T_386 : node _T_387 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_6.io.enq.bits, _T_387 node _T_388 = eq(UInt<3>(0h7), idx_5) when _T_388 : node _T_389 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_7.io.enq.bits, _T_389 node _T_390 = eq(UInt<4>(0h8), idx_5) when _T_390 : node _T_391 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_8.io.enq.bits, _T_391 node _T_392 = eq(UInt<4>(0h9), idx_5) when _T_392 : node _T_393 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_9.io.enq.bits, _T_393 node _T_394 = eq(UInt<4>(0ha), idx_5) when _T_394 : node _T_395 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_10.io.enq.bits, _T_395 node _T_396 = eq(UInt<4>(0hb), idx_5) when _T_396 : node _T_397 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_11.io.enq.bits, _T_397 node _T_398 = eq(UInt<4>(0hc), idx_5) when _T_398 : node _T_399 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_12.io.enq.bits, _T_399 node _T_400 = eq(UInt<4>(0hd), idx_5) when _T_400 : node _T_401 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_13.io.enq.bits, _T_401 node _T_402 = eq(UInt<4>(0he), idx_5) when _T_402 : node _T_403 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_14.io.enq.bits, _T_403 node _T_404 = eq(UInt<4>(0hf), idx_5) when _T_404 : node _T_405 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_15.io.enq.bits, _T_405 node _T_406 = eq(UInt<5>(0h10), idx_5) when _T_406 : node _T_407 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_16.io.enq.bits, _T_407 node _T_408 = eq(UInt<5>(0h11), idx_5) when _T_408 : node _T_409 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_17.io.enq.bits, _T_409 node _T_410 = eq(UInt<5>(0h12), idx_5) when _T_410 : node _T_411 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_18.io.enq.bits, _T_411 node _T_412 = eq(UInt<5>(0h13), idx_5) when _T_412 : node _T_413 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_19.io.enq.bits, _T_413 node _T_414 = eq(UInt<5>(0h14), idx_5) when _T_414 : node _T_415 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_20.io.enq.bits, _T_415 node _T_416 = eq(UInt<5>(0h15), idx_5) when _T_416 : node _T_417 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_21.io.enq.bits, _T_417 node _T_418 = eq(UInt<5>(0h16), idx_5) when _T_418 : node _T_419 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_22.io.enq.bits, _T_419 node _T_420 = eq(UInt<5>(0h17), idx_5) when _T_420 : node _T_421 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_23.io.enq.bits, _T_421 node _T_422 = eq(UInt<5>(0h18), idx_5) when _T_422 : node _T_423 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_24.io.enq.bits, _T_423 node _T_424 = eq(UInt<5>(0h19), idx_5) when _T_424 : node _T_425 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_25.io.enq.bits, _T_425 node _T_426 = eq(UInt<5>(0h1a), idx_5) when _T_426 : node _T_427 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_26.io.enq.bits, _T_427 node _T_428 = eq(UInt<5>(0h1b), idx_5) when _T_428 : node _T_429 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_27.io.enq.bits, _T_429 node _T_430 = eq(UInt<5>(0h1c), idx_5) when _T_430 : node _T_431 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_28.io.enq.bits, _T_431 node _T_432 = eq(UInt<5>(0h1d), idx_5) when _T_432 : node _T_433 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_29.io.enq.bits, _T_433 node _T_434 = eq(UInt<5>(0h1e), idx_5) when _T_434 : node _T_435 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_30.io.enq.bits, _T_435 node _T_436 = eq(UInt<5>(0h1f), idx_5) when _T_436 : node _T_437 = shr(memresp_bits_shifted, 40) connect Queue32_UInt8_31.io.enq.bits, _T_437 node _idx_T_6 = add(write_start_index, UInt<3>(0h6)) node idx_6 = rem(_idx_T_6, UInt<6>(0h20)) node _T_438 = eq(UInt<1>(0h0), idx_6) when _T_438 : node _T_439 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8.io.enq.bits, _T_439 node _T_440 = eq(UInt<1>(0h1), idx_6) when _T_440 : node _T_441 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_1.io.enq.bits, _T_441 node _T_442 = eq(UInt<2>(0h2), idx_6) when _T_442 : node _T_443 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_2.io.enq.bits, _T_443 node _T_444 = eq(UInt<2>(0h3), idx_6) when _T_444 : node _T_445 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_3.io.enq.bits, _T_445 node _T_446 = eq(UInt<3>(0h4), idx_6) when _T_446 : node _T_447 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_4.io.enq.bits, _T_447 node _T_448 = eq(UInt<3>(0h5), idx_6) when _T_448 : node _T_449 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_5.io.enq.bits, _T_449 node _T_450 = eq(UInt<3>(0h6), idx_6) when _T_450 : node _T_451 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_6.io.enq.bits, _T_451 node _T_452 = eq(UInt<3>(0h7), idx_6) when _T_452 : node _T_453 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_7.io.enq.bits, _T_453 node _T_454 = eq(UInt<4>(0h8), idx_6) when _T_454 : node _T_455 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_8.io.enq.bits, _T_455 node _T_456 = eq(UInt<4>(0h9), idx_6) when _T_456 : node _T_457 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_9.io.enq.bits, _T_457 node _T_458 = eq(UInt<4>(0ha), idx_6) when _T_458 : node _T_459 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_10.io.enq.bits, _T_459 node _T_460 = eq(UInt<4>(0hb), idx_6) when _T_460 : node _T_461 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_11.io.enq.bits, _T_461 node _T_462 = eq(UInt<4>(0hc), idx_6) when _T_462 : node _T_463 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_12.io.enq.bits, _T_463 node _T_464 = eq(UInt<4>(0hd), idx_6) when _T_464 : node _T_465 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_13.io.enq.bits, _T_465 node _T_466 = eq(UInt<4>(0he), idx_6) when _T_466 : node _T_467 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_14.io.enq.bits, _T_467 node _T_468 = eq(UInt<4>(0hf), idx_6) when _T_468 : node _T_469 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_15.io.enq.bits, _T_469 node _T_470 = eq(UInt<5>(0h10), idx_6) when _T_470 : node _T_471 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_16.io.enq.bits, _T_471 node _T_472 = eq(UInt<5>(0h11), idx_6) when _T_472 : node _T_473 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_17.io.enq.bits, _T_473 node _T_474 = eq(UInt<5>(0h12), idx_6) when _T_474 : node _T_475 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_18.io.enq.bits, _T_475 node _T_476 = eq(UInt<5>(0h13), idx_6) when _T_476 : node _T_477 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_19.io.enq.bits, _T_477 node _T_478 = eq(UInt<5>(0h14), idx_6) when _T_478 : node _T_479 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_20.io.enq.bits, _T_479 node _T_480 = eq(UInt<5>(0h15), idx_6) when _T_480 : node _T_481 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_21.io.enq.bits, _T_481 node _T_482 = eq(UInt<5>(0h16), idx_6) when _T_482 : node _T_483 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_22.io.enq.bits, _T_483 node _T_484 = eq(UInt<5>(0h17), idx_6) when _T_484 : node _T_485 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_23.io.enq.bits, _T_485 node _T_486 = eq(UInt<5>(0h18), idx_6) when _T_486 : node _T_487 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_24.io.enq.bits, _T_487 node _T_488 = eq(UInt<5>(0h19), idx_6) when _T_488 : node _T_489 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_25.io.enq.bits, _T_489 node _T_490 = eq(UInt<5>(0h1a), idx_6) when _T_490 : node _T_491 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_26.io.enq.bits, _T_491 node _T_492 = eq(UInt<5>(0h1b), idx_6) when _T_492 : node _T_493 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_27.io.enq.bits, _T_493 node _T_494 = eq(UInt<5>(0h1c), idx_6) when _T_494 : node _T_495 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_28.io.enq.bits, _T_495 node _T_496 = eq(UInt<5>(0h1d), idx_6) when _T_496 : node _T_497 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_29.io.enq.bits, _T_497 node _T_498 = eq(UInt<5>(0h1e), idx_6) when _T_498 : node _T_499 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_30.io.enq.bits, _T_499 node _T_500 = eq(UInt<5>(0h1f), idx_6) when _T_500 : node _T_501 = shr(memresp_bits_shifted, 48) connect Queue32_UInt8_31.io.enq.bits, _T_501 node _idx_T_7 = add(write_start_index, UInt<3>(0h7)) node idx_7 = rem(_idx_T_7, UInt<6>(0h20)) node _T_502 = eq(UInt<1>(0h0), idx_7) when _T_502 : node _T_503 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8.io.enq.bits, _T_503 node _T_504 = eq(UInt<1>(0h1), idx_7) when _T_504 : node _T_505 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_1.io.enq.bits, _T_505 node _T_506 = eq(UInt<2>(0h2), idx_7) when _T_506 : node _T_507 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_2.io.enq.bits, _T_507 node _T_508 = eq(UInt<2>(0h3), idx_7) when _T_508 : node _T_509 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_3.io.enq.bits, _T_509 node _T_510 = eq(UInt<3>(0h4), idx_7) when _T_510 : node _T_511 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_4.io.enq.bits, _T_511 node _T_512 = eq(UInt<3>(0h5), idx_7) when _T_512 : node _T_513 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_5.io.enq.bits, _T_513 node _T_514 = eq(UInt<3>(0h6), idx_7) when _T_514 : node _T_515 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_6.io.enq.bits, _T_515 node _T_516 = eq(UInt<3>(0h7), idx_7) when _T_516 : node _T_517 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_7.io.enq.bits, _T_517 node _T_518 = eq(UInt<4>(0h8), idx_7) when _T_518 : node _T_519 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_8.io.enq.bits, _T_519 node _T_520 = eq(UInt<4>(0h9), idx_7) when _T_520 : node _T_521 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_9.io.enq.bits, _T_521 node _T_522 = eq(UInt<4>(0ha), idx_7) when _T_522 : node _T_523 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_10.io.enq.bits, _T_523 node _T_524 = eq(UInt<4>(0hb), idx_7) when _T_524 : node _T_525 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_11.io.enq.bits, _T_525 node _T_526 = eq(UInt<4>(0hc), idx_7) when _T_526 : node _T_527 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_12.io.enq.bits, _T_527 node _T_528 = eq(UInt<4>(0hd), idx_7) when _T_528 : node _T_529 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_13.io.enq.bits, _T_529 node _T_530 = eq(UInt<4>(0he), idx_7) when _T_530 : node _T_531 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_14.io.enq.bits, _T_531 node _T_532 = eq(UInt<4>(0hf), idx_7) when _T_532 : node _T_533 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_15.io.enq.bits, _T_533 node _T_534 = eq(UInt<5>(0h10), idx_7) when _T_534 : node _T_535 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_16.io.enq.bits, _T_535 node _T_536 = eq(UInt<5>(0h11), idx_7) when _T_536 : node _T_537 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_17.io.enq.bits, _T_537 node _T_538 = eq(UInt<5>(0h12), idx_7) when _T_538 : node _T_539 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_18.io.enq.bits, _T_539 node _T_540 = eq(UInt<5>(0h13), idx_7) when _T_540 : node _T_541 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_19.io.enq.bits, _T_541 node _T_542 = eq(UInt<5>(0h14), idx_7) when _T_542 : node _T_543 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_20.io.enq.bits, _T_543 node _T_544 = eq(UInt<5>(0h15), idx_7) when _T_544 : node _T_545 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_21.io.enq.bits, _T_545 node _T_546 = eq(UInt<5>(0h16), idx_7) when _T_546 : node _T_547 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_22.io.enq.bits, _T_547 node _T_548 = eq(UInt<5>(0h17), idx_7) when _T_548 : node _T_549 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_23.io.enq.bits, _T_549 node _T_550 = eq(UInt<5>(0h18), idx_7) when _T_550 : node _T_551 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_24.io.enq.bits, _T_551 node _T_552 = eq(UInt<5>(0h19), idx_7) when _T_552 : node _T_553 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_25.io.enq.bits, _T_553 node _T_554 = eq(UInt<5>(0h1a), idx_7) when _T_554 : node _T_555 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_26.io.enq.bits, _T_555 node _T_556 = eq(UInt<5>(0h1b), idx_7) when _T_556 : node _T_557 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_27.io.enq.bits, _T_557 node _T_558 = eq(UInt<5>(0h1c), idx_7) when _T_558 : node _T_559 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_28.io.enq.bits, _T_559 node _T_560 = eq(UInt<5>(0h1d), idx_7) when _T_560 : node _T_561 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_29.io.enq.bits, _T_561 node _T_562 = eq(UInt<5>(0h1e), idx_7) when _T_562 : node _T_563 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_30.io.enq.bits, _T_563 node _T_564 = eq(UInt<5>(0h1f), idx_7) when _T_564 : node _T_565 = shr(memresp_bits_shifted, 56) connect Queue32_UInt8_31.io.enq.bits, _T_565 node _idx_T_8 = add(write_start_index, UInt<4>(0h8)) node idx_8 = rem(_idx_T_8, UInt<6>(0h20)) node _T_566 = eq(UInt<1>(0h0), idx_8) when _T_566 : node _T_567 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8.io.enq.bits, _T_567 node _T_568 = eq(UInt<1>(0h1), idx_8) when _T_568 : node _T_569 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_1.io.enq.bits, _T_569 node _T_570 = eq(UInt<2>(0h2), idx_8) when _T_570 : node _T_571 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_2.io.enq.bits, _T_571 node _T_572 = eq(UInt<2>(0h3), idx_8) when _T_572 : node _T_573 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_3.io.enq.bits, _T_573 node _T_574 = eq(UInt<3>(0h4), idx_8) when _T_574 : node _T_575 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_4.io.enq.bits, _T_575 node _T_576 = eq(UInt<3>(0h5), idx_8) when _T_576 : node _T_577 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_5.io.enq.bits, _T_577 node _T_578 = eq(UInt<3>(0h6), idx_8) when _T_578 : node _T_579 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_6.io.enq.bits, _T_579 node _T_580 = eq(UInt<3>(0h7), idx_8) when _T_580 : node _T_581 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_7.io.enq.bits, _T_581 node _T_582 = eq(UInt<4>(0h8), idx_8) when _T_582 : node _T_583 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_8.io.enq.bits, _T_583 node _T_584 = eq(UInt<4>(0h9), idx_8) when _T_584 : node _T_585 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_9.io.enq.bits, _T_585 node _T_586 = eq(UInt<4>(0ha), idx_8) when _T_586 : node _T_587 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_10.io.enq.bits, _T_587 node _T_588 = eq(UInt<4>(0hb), idx_8) when _T_588 : node _T_589 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_11.io.enq.bits, _T_589 node _T_590 = eq(UInt<4>(0hc), idx_8) when _T_590 : node _T_591 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_12.io.enq.bits, _T_591 node _T_592 = eq(UInt<4>(0hd), idx_8) when _T_592 : node _T_593 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_13.io.enq.bits, _T_593 node _T_594 = eq(UInt<4>(0he), idx_8) when _T_594 : node _T_595 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_14.io.enq.bits, _T_595 node _T_596 = eq(UInt<4>(0hf), idx_8) when _T_596 : node _T_597 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_15.io.enq.bits, _T_597 node _T_598 = eq(UInt<5>(0h10), idx_8) when _T_598 : node _T_599 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_16.io.enq.bits, _T_599 node _T_600 = eq(UInt<5>(0h11), idx_8) when _T_600 : node _T_601 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_17.io.enq.bits, _T_601 node _T_602 = eq(UInt<5>(0h12), idx_8) when _T_602 : node _T_603 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_18.io.enq.bits, _T_603 node _T_604 = eq(UInt<5>(0h13), idx_8) when _T_604 : node _T_605 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_19.io.enq.bits, _T_605 node _T_606 = eq(UInt<5>(0h14), idx_8) when _T_606 : node _T_607 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_20.io.enq.bits, _T_607 node _T_608 = eq(UInt<5>(0h15), idx_8) when _T_608 : node _T_609 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_21.io.enq.bits, _T_609 node _T_610 = eq(UInt<5>(0h16), idx_8) when _T_610 : node _T_611 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_22.io.enq.bits, _T_611 node _T_612 = eq(UInt<5>(0h17), idx_8) when _T_612 : node _T_613 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_23.io.enq.bits, _T_613 node _T_614 = eq(UInt<5>(0h18), idx_8) when _T_614 : node _T_615 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_24.io.enq.bits, _T_615 node _T_616 = eq(UInt<5>(0h19), idx_8) when _T_616 : node _T_617 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_25.io.enq.bits, _T_617 node _T_618 = eq(UInt<5>(0h1a), idx_8) when _T_618 : node _T_619 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_26.io.enq.bits, _T_619 node _T_620 = eq(UInt<5>(0h1b), idx_8) when _T_620 : node _T_621 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_27.io.enq.bits, _T_621 node _T_622 = eq(UInt<5>(0h1c), idx_8) when _T_622 : node _T_623 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_28.io.enq.bits, _T_623 node _T_624 = eq(UInt<5>(0h1d), idx_8) when _T_624 : node _T_625 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_29.io.enq.bits, _T_625 node _T_626 = eq(UInt<5>(0h1e), idx_8) when _T_626 : node _T_627 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_30.io.enq.bits, _T_627 node _T_628 = eq(UInt<5>(0h1f), idx_8) when _T_628 : node _T_629 = shr(memresp_bits_shifted, 64) connect Queue32_UInt8_31.io.enq.bits, _T_629 node _idx_T_9 = add(write_start_index, UInt<4>(0h9)) node idx_9 = rem(_idx_T_9, UInt<6>(0h20)) node _T_630 = eq(UInt<1>(0h0), idx_9) when _T_630 : node _T_631 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8.io.enq.bits, _T_631 node _T_632 = eq(UInt<1>(0h1), idx_9) when _T_632 : node _T_633 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_1.io.enq.bits, _T_633 node _T_634 = eq(UInt<2>(0h2), idx_9) when _T_634 : node _T_635 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_2.io.enq.bits, _T_635 node _T_636 = eq(UInt<2>(0h3), idx_9) when _T_636 : node _T_637 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_3.io.enq.bits, _T_637 node _T_638 = eq(UInt<3>(0h4), idx_9) when _T_638 : node _T_639 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_4.io.enq.bits, _T_639 node _T_640 = eq(UInt<3>(0h5), idx_9) when _T_640 : node _T_641 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_5.io.enq.bits, _T_641 node _T_642 = eq(UInt<3>(0h6), idx_9) when _T_642 : node _T_643 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_6.io.enq.bits, _T_643 node _T_644 = eq(UInt<3>(0h7), idx_9) when _T_644 : node _T_645 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_7.io.enq.bits, _T_645 node _T_646 = eq(UInt<4>(0h8), idx_9) when _T_646 : node _T_647 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_8.io.enq.bits, _T_647 node _T_648 = eq(UInt<4>(0h9), idx_9) when _T_648 : node _T_649 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_9.io.enq.bits, _T_649 node _T_650 = eq(UInt<4>(0ha), idx_9) when _T_650 : node _T_651 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_10.io.enq.bits, _T_651 node _T_652 = eq(UInt<4>(0hb), idx_9) when _T_652 : node _T_653 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_11.io.enq.bits, _T_653 node _T_654 = eq(UInt<4>(0hc), idx_9) when _T_654 : node _T_655 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_12.io.enq.bits, _T_655 node _T_656 = eq(UInt<4>(0hd), idx_9) when _T_656 : node _T_657 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_13.io.enq.bits, _T_657 node _T_658 = eq(UInt<4>(0he), idx_9) when _T_658 : node _T_659 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_14.io.enq.bits, _T_659 node _T_660 = eq(UInt<4>(0hf), idx_9) when _T_660 : node _T_661 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_15.io.enq.bits, _T_661 node _T_662 = eq(UInt<5>(0h10), idx_9) when _T_662 : node _T_663 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_16.io.enq.bits, _T_663 node _T_664 = eq(UInt<5>(0h11), idx_9) when _T_664 : node _T_665 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_17.io.enq.bits, _T_665 node _T_666 = eq(UInt<5>(0h12), idx_9) when _T_666 : node _T_667 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_18.io.enq.bits, _T_667 node _T_668 = eq(UInt<5>(0h13), idx_9) when _T_668 : node _T_669 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_19.io.enq.bits, _T_669 node _T_670 = eq(UInt<5>(0h14), idx_9) when _T_670 : node _T_671 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_20.io.enq.bits, _T_671 node _T_672 = eq(UInt<5>(0h15), idx_9) when _T_672 : node _T_673 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_21.io.enq.bits, _T_673 node _T_674 = eq(UInt<5>(0h16), idx_9) when _T_674 : node _T_675 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_22.io.enq.bits, _T_675 node _T_676 = eq(UInt<5>(0h17), idx_9) when _T_676 : node _T_677 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_23.io.enq.bits, _T_677 node _T_678 = eq(UInt<5>(0h18), idx_9) when _T_678 : node _T_679 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_24.io.enq.bits, _T_679 node _T_680 = eq(UInt<5>(0h19), idx_9) when _T_680 : node _T_681 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_25.io.enq.bits, _T_681 node _T_682 = eq(UInt<5>(0h1a), idx_9) when _T_682 : node _T_683 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_26.io.enq.bits, _T_683 node _T_684 = eq(UInt<5>(0h1b), idx_9) when _T_684 : node _T_685 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_27.io.enq.bits, _T_685 node _T_686 = eq(UInt<5>(0h1c), idx_9) when _T_686 : node _T_687 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_28.io.enq.bits, _T_687 node _T_688 = eq(UInt<5>(0h1d), idx_9) when _T_688 : node _T_689 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_29.io.enq.bits, _T_689 node _T_690 = eq(UInt<5>(0h1e), idx_9) when _T_690 : node _T_691 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_30.io.enq.bits, _T_691 node _T_692 = eq(UInt<5>(0h1f), idx_9) when _T_692 : node _T_693 = shr(memresp_bits_shifted, 72) connect Queue32_UInt8_31.io.enq.bits, _T_693 node _idx_T_10 = add(write_start_index, UInt<4>(0ha)) node idx_10 = rem(_idx_T_10, UInt<6>(0h20)) node _T_694 = eq(UInt<1>(0h0), idx_10) when _T_694 : node _T_695 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8.io.enq.bits, _T_695 node _T_696 = eq(UInt<1>(0h1), idx_10) when _T_696 : node _T_697 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_1.io.enq.bits, _T_697 node _T_698 = eq(UInt<2>(0h2), idx_10) when _T_698 : node _T_699 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_2.io.enq.bits, _T_699 node _T_700 = eq(UInt<2>(0h3), idx_10) when _T_700 : node _T_701 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_3.io.enq.bits, _T_701 node _T_702 = eq(UInt<3>(0h4), idx_10) when _T_702 : node _T_703 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_4.io.enq.bits, _T_703 node _T_704 = eq(UInt<3>(0h5), idx_10) when _T_704 : node _T_705 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_5.io.enq.bits, _T_705 node _T_706 = eq(UInt<3>(0h6), idx_10) when _T_706 : node _T_707 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_6.io.enq.bits, _T_707 node _T_708 = eq(UInt<3>(0h7), idx_10) when _T_708 : node _T_709 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_7.io.enq.bits, _T_709 node _T_710 = eq(UInt<4>(0h8), idx_10) when _T_710 : node _T_711 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_8.io.enq.bits, _T_711 node _T_712 = eq(UInt<4>(0h9), idx_10) when _T_712 : node _T_713 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_9.io.enq.bits, _T_713 node _T_714 = eq(UInt<4>(0ha), idx_10) when _T_714 : node _T_715 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_10.io.enq.bits, _T_715 node _T_716 = eq(UInt<4>(0hb), idx_10) when _T_716 : node _T_717 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_11.io.enq.bits, _T_717 node _T_718 = eq(UInt<4>(0hc), idx_10) when _T_718 : node _T_719 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_12.io.enq.bits, _T_719 node _T_720 = eq(UInt<4>(0hd), idx_10) when _T_720 : node _T_721 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_13.io.enq.bits, _T_721 node _T_722 = eq(UInt<4>(0he), idx_10) when _T_722 : node _T_723 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_14.io.enq.bits, _T_723 node _T_724 = eq(UInt<4>(0hf), idx_10) when _T_724 : node _T_725 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_15.io.enq.bits, _T_725 node _T_726 = eq(UInt<5>(0h10), idx_10) when _T_726 : node _T_727 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_16.io.enq.bits, _T_727 node _T_728 = eq(UInt<5>(0h11), idx_10) when _T_728 : node _T_729 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_17.io.enq.bits, _T_729 node _T_730 = eq(UInt<5>(0h12), idx_10) when _T_730 : node _T_731 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_18.io.enq.bits, _T_731 node _T_732 = eq(UInt<5>(0h13), idx_10) when _T_732 : node _T_733 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_19.io.enq.bits, _T_733 node _T_734 = eq(UInt<5>(0h14), idx_10) when _T_734 : node _T_735 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_20.io.enq.bits, _T_735 node _T_736 = eq(UInt<5>(0h15), idx_10) when _T_736 : node _T_737 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_21.io.enq.bits, _T_737 node _T_738 = eq(UInt<5>(0h16), idx_10) when _T_738 : node _T_739 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_22.io.enq.bits, _T_739 node _T_740 = eq(UInt<5>(0h17), idx_10) when _T_740 : node _T_741 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_23.io.enq.bits, _T_741 node _T_742 = eq(UInt<5>(0h18), idx_10) when _T_742 : node _T_743 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_24.io.enq.bits, _T_743 node _T_744 = eq(UInt<5>(0h19), idx_10) when _T_744 : node _T_745 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_25.io.enq.bits, _T_745 node _T_746 = eq(UInt<5>(0h1a), idx_10) when _T_746 : node _T_747 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_26.io.enq.bits, _T_747 node _T_748 = eq(UInt<5>(0h1b), idx_10) when _T_748 : node _T_749 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_27.io.enq.bits, _T_749 node _T_750 = eq(UInt<5>(0h1c), idx_10) when _T_750 : node _T_751 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_28.io.enq.bits, _T_751 node _T_752 = eq(UInt<5>(0h1d), idx_10) when _T_752 : node _T_753 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_29.io.enq.bits, _T_753 node _T_754 = eq(UInt<5>(0h1e), idx_10) when _T_754 : node _T_755 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_30.io.enq.bits, _T_755 node _T_756 = eq(UInt<5>(0h1f), idx_10) when _T_756 : node _T_757 = shr(memresp_bits_shifted, 80) connect Queue32_UInt8_31.io.enq.bits, _T_757 node _idx_T_11 = add(write_start_index, UInt<4>(0hb)) node idx_11 = rem(_idx_T_11, UInt<6>(0h20)) node _T_758 = eq(UInt<1>(0h0), idx_11) when _T_758 : node _T_759 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8.io.enq.bits, _T_759 node _T_760 = eq(UInt<1>(0h1), idx_11) when _T_760 : node _T_761 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_1.io.enq.bits, _T_761 node _T_762 = eq(UInt<2>(0h2), idx_11) when _T_762 : node _T_763 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_2.io.enq.bits, _T_763 node _T_764 = eq(UInt<2>(0h3), idx_11) when _T_764 : node _T_765 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_3.io.enq.bits, _T_765 node _T_766 = eq(UInt<3>(0h4), idx_11) when _T_766 : node _T_767 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_4.io.enq.bits, _T_767 node _T_768 = eq(UInt<3>(0h5), idx_11) when _T_768 : node _T_769 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_5.io.enq.bits, _T_769 node _T_770 = eq(UInt<3>(0h6), idx_11) when _T_770 : node _T_771 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_6.io.enq.bits, _T_771 node _T_772 = eq(UInt<3>(0h7), idx_11) when _T_772 : node _T_773 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_7.io.enq.bits, _T_773 node _T_774 = eq(UInt<4>(0h8), idx_11) when _T_774 : node _T_775 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_8.io.enq.bits, _T_775 node _T_776 = eq(UInt<4>(0h9), idx_11) when _T_776 : node _T_777 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_9.io.enq.bits, _T_777 node _T_778 = eq(UInt<4>(0ha), idx_11) when _T_778 : node _T_779 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_10.io.enq.bits, _T_779 node _T_780 = eq(UInt<4>(0hb), idx_11) when _T_780 : node _T_781 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_11.io.enq.bits, _T_781 node _T_782 = eq(UInt<4>(0hc), idx_11) when _T_782 : node _T_783 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_12.io.enq.bits, _T_783 node _T_784 = eq(UInt<4>(0hd), idx_11) when _T_784 : node _T_785 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_13.io.enq.bits, _T_785 node _T_786 = eq(UInt<4>(0he), idx_11) when _T_786 : node _T_787 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_14.io.enq.bits, _T_787 node _T_788 = eq(UInt<4>(0hf), idx_11) when _T_788 : node _T_789 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_15.io.enq.bits, _T_789 node _T_790 = eq(UInt<5>(0h10), idx_11) when _T_790 : node _T_791 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_16.io.enq.bits, _T_791 node _T_792 = eq(UInt<5>(0h11), idx_11) when _T_792 : node _T_793 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_17.io.enq.bits, _T_793 node _T_794 = eq(UInt<5>(0h12), idx_11) when _T_794 : node _T_795 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_18.io.enq.bits, _T_795 node _T_796 = eq(UInt<5>(0h13), idx_11) when _T_796 : node _T_797 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_19.io.enq.bits, _T_797 node _T_798 = eq(UInt<5>(0h14), idx_11) when _T_798 : node _T_799 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_20.io.enq.bits, _T_799 node _T_800 = eq(UInt<5>(0h15), idx_11) when _T_800 : node _T_801 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_21.io.enq.bits, _T_801 node _T_802 = eq(UInt<5>(0h16), idx_11) when _T_802 : node _T_803 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_22.io.enq.bits, _T_803 node _T_804 = eq(UInt<5>(0h17), idx_11) when _T_804 : node _T_805 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_23.io.enq.bits, _T_805 node _T_806 = eq(UInt<5>(0h18), idx_11) when _T_806 : node _T_807 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_24.io.enq.bits, _T_807 node _T_808 = eq(UInt<5>(0h19), idx_11) when _T_808 : node _T_809 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_25.io.enq.bits, _T_809 node _T_810 = eq(UInt<5>(0h1a), idx_11) when _T_810 : node _T_811 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_26.io.enq.bits, _T_811 node _T_812 = eq(UInt<5>(0h1b), idx_11) when _T_812 : node _T_813 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_27.io.enq.bits, _T_813 node _T_814 = eq(UInt<5>(0h1c), idx_11) when _T_814 : node _T_815 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_28.io.enq.bits, _T_815 node _T_816 = eq(UInt<5>(0h1d), idx_11) when _T_816 : node _T_817 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_29.io.enq.bits, _T_817 node _T_818 = eq(UInt<5>(0h1e), idx_11) when _T_818 : node _T_819 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_30.io.enq.bits, _T_819 node _T_820 = eq(UInt<5>(0h1f), idx_11) when _T_820 : node _T_821 = shr(memresp_bits_shifted, 88) connect Queue32_UInt8_31.io.enq.bits, _T_821 node _idx_T_12 = add(write_start_index, UInt<4>(0hc)) node idx_12 = rem(_idx_T_12, UInt<6>(0h20)) node _T_822 = eq(UInt<1>(0h0), idx_12) when _T_822 : node _T_823 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8.io.enq.bits, _T_823 node _T_824 = eq(UInt<1>(0h1), idx_12) when _T_824 : node _T_825 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_1.io.enq.bits, _T_825 node _T_826 = eq(UInt<2>(0h2), idx_12) when _T_826 : node _T_827 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_2.io.enq.bits, _T_827 node _T_828 = eq(UInt<2>(0h3), idx_12) when _T_828 : node _T_829 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_3.io.enq.bits, _T_829 node _T_830 = eq(UInt<3>(0h4), idx_12) when _T_830 : node _T_831 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_4.io.enq.bits, _T_831 node _T_832 = eq(UInt<3>(0h5), idx_12) when _T_832 : node _T_833 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_5.io.enq.bits, _T_833 node _T_834 = eq(UInt<3>(0h6), idx_12) when _T_834 : node _T_835 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_6.io.enq.bits, _T_835 node _T_836 = eq(UInt<3>(0h7), idx_12) when _T_836 : node _T_837 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_7.io.enq.bits, _T_837 node _T_838 = eq(UInt<4>(0h8), idx_12) when _T_838 : node _T_839 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_8.io.enq.bits, _T_839 node _T_840 = eq(UInt<4>(0h9), idx_12) when _T_840 : node _T_841 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_9.io.enq.bits, _T_841 node _T_842 = eq(UInt<4>(0ha), idx_12) when _T_842 : node _T_843 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_10.io.enq.bits, _T_843 node _T_844 = eq(UInt<4>(0hb), idx_12) when _T_844 : node _T_845 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_11.io.enq.bits, _T_845 node _T_846 = eq(UInt<4>(0hc), idx_12) when _T_846 : node _T_847 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_12.io.enq.bits, _T_847 node _T_848 = eq(UInt<4>(0hd), idx_12) when _T_848 : node _T_849 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_13.io.enq.bits, _T_849 node _T_850 = eq(UInt<4>(0he), idx_12) when _T_850 : node _T_851 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_14.io.enq.bits, _T_851 node _T_852 = eq(UInt<4>(0hf), idx_12) when _T_852 : node _T_853 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_15.io.enq.bits, _T_853 node _T_854 = eq(UInt<5>(0h10), idx_12) when _T_854 : node _T_855 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_16.io.enq.bits, _T_855 node _T_856 = eq(UInt<5>(0h11), idx_12) when _T_856 : node _T_857 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_17.io.enq.bits, _T_857 node _T_858 = eq(UInt<5>(0h12), idx_12) when _T_858 : node _T_859 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_18.io.enq.bits, _T_859 node _T_860 = eq(UInt<5>(0h13), idx_12) when _T_860 : node _T_861 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_19.io.enq.bits, _T_861 node _T_862 = eq(UInt<5>(0h14), idx_12) when _T_862 : node _T_863 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_20.io.enq.bits, _T_863 node _T_864 = eq(UInt<5>(0h15), idx_12) when _T_864 : node _T_865 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_21.io.enq.bits, _T_865 node _T_866 = eq(UInt<5>(0h16), idx_12) when _T_866 : node _T_867 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_22.io.enq.bits, _T_867 node _T_868 = eq(UInt<5>(0h17), idx_12) when _T_868 : node _T_869 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_23.io.enq.bits, _T_869 node _T_870 = eq(UInt<5>(0h18), idx_12) when _T_870 : node _T_871 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_24.io.enq.bits, _T_871 node _T_872 = eq(UInt<5>(0h19), idx_12) when _T_872 : node _T_873 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_25.io.enq.bits, _T_873 node _T_874 = eq(UInt<5>(0h1a), idx_12) when _T_874 : node _T_875 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_26.io.enq.bits, _T_875 node _T_876 = eq(UInt<5>(0h1b), idx_12) when _T_876 : node _T_877 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_27.io.enq.bits, _T_877 node _T_878 = eq(UInt<5>(0h1c), idx_12) when _T_878 : node _T_879 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_28.io.enq.bits, _T_879 node _T_880 = eq(UInt<5>(0h1d), idx_12) when _T_880 : node _T_881 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_29.io.enq.bits, _T_881 node _T_882 = eq(UInt<5>(0h1e), idx_12) when _T_882 : node _T_883 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_30.io.enq.bits, _T_883 node _T_884 = eq(UInt<5>(0h1f), idx_12) when _T_884 : node _T_885 = shr(memresp_bits_shifted, 96) connect Queue32_UInt8_31.io.enq.bits, _T_885 node _idx_T_13 = add(write_start_index, UInt<4>(0hd)) node idx_13 = rem(_idx_T_13, UInt<6>(0h20)) node _T_886 = eq(UInt<1>(0h0), idx_13) when _T_886 : node _T_887 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8.io.enq.bits, _T_887 node _T_888 = eq(UInt<1>(0h1), idx_13) when _T_888 : node _T_889 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_1.io.enq.bits, _T_889 node _T_890 = eq(UInt<2>(0h2), idx_13) when _T_890 : node _T_891 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_2.io.enq.bits, _T_891 node _T_892 = eq(UInt<2>(0h3), idx_13) when _T_892 : node _T_893 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_3.io.enq.bits, _T_893 node _T_894 = eq(UInt<3>(0h4), idx_13) when _T_894 : node _T_895 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_4.io.enq.bits, _T_895 node _T_896 = eq(UInt<3>(0h5), idx_13) when _T_896 : node _T_897 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_5.io.enq.bits, _T_897 node _T_898 = eq(UInt<3>(0h6), idx_13) when _T_898 : node _T_899 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_6.io.enq.bits, _T_899 node _T_900 = eq(UInt<3>(0h7), idx_13) when _T_900 : node _T_901 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_7.io.enq.bits, _T_901 node _T_902 = eq(UInt<4>(0h8), idx_13) when _T_902 : node _T_903 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_8.io.enq.bits, _T_903 node _T_904 = eq(UInt<4>(0h9), idx_13) when _T_904 : node _T_905 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_9.io.enq.bits, _T_905 node _T_906 = eq(UInt<4>(0ha), idx_13) when _T_906 : node _T_907 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_10.io.enq.bits, _T_907 node _T_908 = eq(UInt<4>(0hb), idx_13) when _T_908 : node _T_909 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_11.io.enq.bits, _T_909 node _T_910 = eq(UInt<4>(0hc), idx_13) when _T_910 : node _T_911 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_12.io.enq.bits, _T_911 node _T_912 = eq(UInt<4>(0hd), idx_13) when _T_912 : node _T_913 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_13.io.enq.bits, _T_913 node _T_914 = eq(UInt<4>(0he), idx_13) when _T_914 : node _T_915 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_14.io.enq.bits, _T_915 node _T_916 = eq(UInt<4>(0hf), idx_13) when _T_916 : node _T_917 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_15.io.enq.bits, _T_917 node _T_918 = eq(UInt<5>(0h10), idx_13) when _T_918 : node _T_919 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_16.io.enq.bits, _T_919 node _T_920 = eq(UInt<5>(0h11), idx_13) when _T_920 : node _T_921 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_17.io.enq.bits, _T_921 node _T_922 = eq(UInt<5>(0h12), idx_13) when _T_922 : node _T_923 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_18.io.enq.bits, _T_923 node _T_924 = eq(UInt<5>(0h13), idx_13) when _T_924 : node _T_925 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_19.io.enq.bits, _T_925 node _T_926 = eq(UInt<5>(0h14), idx_13) when _T_926 : node _T_927 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_20.io.enq.bits, _T_927 node _T_928 = eq(UInt<5>(0h15), idx_13) when _T_928 : node _T_929 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_21.io.enq.bits, _T_929 node _T_930 = eq(UInt<5>(0h16), idx_13) when _T_930 : node _T_931 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_22.io.enq.bits, _T_931 node _T_932 = eq(UInt<5>(0h17), idx_13) when _T_932 : node _T_933 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_23.io.enq.bits, _T_933 node _T_934 = eq(UInt<5>(0h18), idx_13) when _T_934 : node _T_935 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_24.io.enq.bits, _T_935 node _T_936 = eq(UInt<5>(0h19), idx_13) when _T_936 : node _T_937 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_25.io.enq.bits, _T_937 node _T_938 = eq(UInt<5>(0h1a), idx_13) when _T_938 : node _T_939 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_26.io.enq.bits, _T_939 node _T_940 = eq(UInt<5>(0h1b), idx_13) when _T_940 : node _T_941 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_27.io.enq.bits, _T_941 node _T_942 = eq(UInt<5>(0h1c), idx_13) when _T_942 : node _T_943 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_28.io.enq.bits, _T_943 node _T_944 = eq(UInt<5>(0h1d), idx_13) when _T_944 : node _T_945 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_29.io.enq.bits, _T_945 node _T_946 = eq(UInt<5>(0h1e), idx_13) when _T_946 : node _T_947 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_30.io.enq.bits, _T_947 node _T_948 = eq(UInt<5>(0h1f), idx_13) when _T_948 : node _T_949 = shr(memresp_bits_shifted, 104) connect Queue32_UInt8_31.io.enq.bits, _T_949 node _idx_T_14 = add(write_start_index, UInt<4>(0he)) node idx_14 = rem(_idx_T_14, UInt<6>(0h20)) node _T_950 = eq(UInt<1>(0h0), idx_14) when _T_950 : node _T_951 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8.io.enq.bits, _T_951 node _T_952 = eq(UInt<1>(0h1), idx_14) when _T_952 : node _T_953 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_1.io.enq.bits, _T_953 node _T_954 = eq(UInt<2>(0h2), idx_14) when _T_954 : node _T_955 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_2.io.enq.bits, _T_955 node _T_956 = eq(UInt<2>(0h3), idx_14) when _T_956 : node _T_957 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_3.io.enq.bits, _T_957 node _T_958 = eq(UInt<3>(0h4), idx_14) when _T_958 : node _T_959 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_4.io.enq.bits, _T_959 node _T_960 = eq(UInt<3>(0h5), idx_14) when _T_960 : node _T_961 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_5.io.enq.bits, _T_961 node _T_962 = eq(UInt<3>(0h6), idx_14) when _T_962 : node _T_963 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_6.io.enq.bits, _T_963 node _T_964 = eq(UInt<3>(0h7), idx_14) when _T_964 : node _T_965 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_7.io.enq.bits, _T_965 node _T_966 = eq(UInt<4>(0h8), idx_14) when _T_966 : node _T_967 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_8.io.enq.bits, _T_967 node _T_968 = eq(UInt<4>(0h9), idx_14) when _T_968 : node _T_969 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_9.io.enq.bits, _T_969 node _T_970 = eq(UInt<4>(0ha), idx_14) when _T_970 : node _T_971 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_10.io.enq.bits, _T_971 node _T_972 = eq(UInt<4>(0hb), idx_14) when _T_972 : node _T_973 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_11.io.enq.bits, _T_973 node _T_974 = eq(UInt<4>(0hc), idx_14) when _T_974 : node _T_975 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_12.io.enq.bits, _T_975 node _T_976 = eq(UInt<4>(0hd), idx_14) when _T_976 : node _T_977 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_13.io.enq.bits, _T_977 node _T_978 = eq(UInt<4>(0he), idx_14) when _T_978 : node _T_979 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_14.io.enq.bits, _T_979 node _T_980 = eq(UInt<4>(0hf), idx_14) when _T_980 : node _T_981 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_15.io.enq.bits, _T_981 node _T_982 = eq(UInt<5>(0h10), idx_14) when _T_982 : node _T_983 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_16.io.enq.bits, _T_983 node _T_984 = eq(UInt<5>(0h11), idx_14) when _T_984 : node _T_985 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_17.io.enq.bits, _T_985 node _T_986 = eq(UInt<5>(0h12), idx_14) when _T_986 : node _T_987 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_18.io.enq.bits, _T_987 node _T_988 = eq(UInt<5>(0h13), idx_14) when _T_988 : node _T_989 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_19.io.enq.bits, _T_989 node _T_990 = eq(UInt<5>(0h14), idx_14) when _T_990 : node _T_991 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_20.io.enq.bits, _T_991 node _T_992 = eq(UInt<5>(0h15), idx_14) when _T_992 : node _T_993 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_21.io.enq.bits, _T_993 node _T_994 = eq(UInt<5>(0h16), idx_14) when _T_994 : node _T_995 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_22.io.enq.bits, _T_995 node _T_996 = eq(UInt<5>(0h17), idx_14) when _T_996 : node _T_997 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_23.io.enq.bits, _T_997 node _T_998 = eq(UInt<5>(0h18), idx_14) when _T_998 : node _T_999 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_24.io.enq.bits, _T_999 node _T_1000 = eq(UInt<5>(0h19), idx_14) when _T_1000 : node _T_1001 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_25.io.enq.bits, _T_1001 node _T_1002 = eq(UInt<5>(0h1a), idx_14) when _T_1002 : node _T_1003 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_26.io.enq.bits, _T_1003 node _T_1004 = eq(UInt<5>(0h1b), idx_14) when _T_1004 : node _T_1005 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_27.io.enq.bits, _T_1005 node _T_1006 = eq(UInt<5>(0h1c), idx_14) when _T_1006 : node _T_1007 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_28.io.enq.bits, _T_1007 node _T_1008 = eq(UInt<5>(0h1d), idx_14) when _T_1008 : node _T_1009 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_29.io.enq.bits, _T_1009 node _T_1010 = eq(UInt<5>(0h1e), idx_14) when _T_1010 : node _T_1011 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_30.io.enq.bits, _T_1011 node _T_1012 = eq(UInt<5>(0h1f), idx_14) when _T_1012 : node _T_1013 = shr(memresp_bits_shifted, 112) connect Queue32_UInt8_31.io.enq.bits, _T_1013 node _idx_T_15 = add(write_start_index, UInt<4>(0hf)) node idx_15 = rem(_idx_T_15, UInt<6>(0h20)) node _T_1014 = eq(UInt<1>(0h0), idx_15) when _T_1014 : node _T_1015 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8.io.enq.bits, _T_1015 node _T_1016 = eq(UInt<1>(0h1), idx_15) when _T_1016 : node _T_1017 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_1.io.enq.bits, _T_1017 node _T_1018 = eq(UInt<2>(0h2), idx_15) when _T_1018 : node _T_1019 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_2.io.enq.bits, _T_1019 node _T_1020 = eq(UInt<2>(0h3), idx_15) when _T_1020 : node _T_1021 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_3.io.enq.bits, _T_1021 node _T_1022 = eq(UInt<3>(0h4), idx_15) when _T_1022 : node _T_1023 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_4.io.enq.bits, _T_1023 node _T_1024 = eq(UInt<3>(0h5), idx_15) when _T_1024 : node _T_1025 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_5.io.enq.bits, _T_1025 node _T_1026 = eq(UInt<3>(0h6), idx_15) when _T_1026 : node _T_1027 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_6.io.enq.bits, _T_1027 node _T_1028 = eq(UInt<3>(0h7), idx_15) when _T_1028 : node _T_1029 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_7.io.enq.bits, _T_1029 node _T_1030 = eq(UInt<4>(0h8), idx_15) when _T_1030 : node _T_1031 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_8.io.enq.bits, _T_1031 node _T_1032 = eq(UInt<4>(0h9), idx_15) when _T_1032 : node _T_1033 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_9.io.enq.bits, _T_1033 node _T_1034 = eq(UInt<4>(0ha), idx_15) when _T_1034 : node _T_1035 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_10.io.enq.bits, _T_1035 node _T_1036 = eq(UInt<4>(0hb), idx_15) when _T_1036 : node _T_1037 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_11.io.enq.bits, _T_1037 node _T_1038 = eq(UInt<4>(0hc), idx_15) when _T_1038 : node _T_1039 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_12.io.enq.bits, _T_1039 node _T_1040 = eq(UInt<4>(0hd), idx_15) when _T_1040 : node _T_1041 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_13.io.enq.bits, _T_1041 node _T_1042 = eq(UInt<4>(0he), idx_15) when _T_1042 : node _T_1043 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_14.io.enq.bits, _T_1043 node _T_1044 = eq(UInt<4>(0hf), idx_15) when _T_1044 : node _T_1045 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_15.io.enq.bits, _T_1045 node _T_1046 = eq(UInt<5>(0h10), idx_15) when _T_1046 : node _T_1047 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_16.io.enq.bits, _T_1047 node _T_1048 = eq(UInt<5>(0h11), idx_15) when _T_1048 : node _T_1049 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_17.io.enq.bits, _T_1049 node _T_1050 = eq(UInt<5>(0h12), idx_15) when _T_1050 : node _T_1051 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_18.io.enq.bits, _T_1051 node _T_1052 = eq(UInt<5>(0h13), idx_15) when _T_1052 : node _T_1053 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_19.io.enq.bits, _T_1053 node _T_1054 = eq(UInt<5>(0h14), idx_15) when _T_1054 : node _T_1055 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_20.io.enq.bits, _T_1055 node _T_1056 = eq(UInt<5>(0h15), idx_15) when _T_1056 : node _T_1057 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_21.io.enq.bits, _T_1057 node _T_1058 = eq(UInt<5>(0h16), idx_15) when _T_1058 : node _T_1059 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_22.io.enq.bits, _T_1059 node _T_1060 = eq(UInt<5>(0h17), idx_15) when _T_1060 : node _T_1061 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_23.io.enq.bits, _T_1061 node _T_1062 = eq(UInt<5>(0h18), idx_15) when _T_1062 : node _T_1063 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_24.io.enq.bits, _T_1063 node _T_1064 = eq(UInt<5>(0h19), idx_15) when _T_1064 : node _T_1065 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_25.io.enq.bits, _T_1065 node _T_1066 = eq(UInt<5>(0h1a), idx_15) when _T_1066 : node _T_1067 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_26.io.enq.bits, _T_1067 node _T_1068 = eq(UInt<5>(0h1b), idx_15) when _T_1068 : node _T_1069 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_27.io.enq.bits, _T_1069 node _T_1070 = eq(UInt<5>(0h1c), idx_15) when _T_1070 : node _T_1071 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_28.io.enq.bits, _T_1071 node _T_1072 = eq(UInt<5>(0h1d), idx_15) when _T_1072 : node _T_1073 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_29.io.enq.bits, _T_1073 node _T_1074 = eq(UInt<5>(0h1e), idx_15) when _T_1074 : node _T_1075 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_30.io.enq.bits, _T_1075 node _T_1076 = eq(UInt<5>(0h1f), idx_15) when _T_1076 : node _T_1077 = shr(memresp_bits_shifted, 120) connect Queue32_UInt8_31.io.enq.bits, _T_1077 node _idx_T_16 = add(write_start_index, UInt<5>(0h10)) node idx_16 = rem(_idx_T_16, UInt<6>(0h20)) node _T_1078 = eq(UInt<1>(0h0), idx_16) when _T_1078 : node _T_1079 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8.io.enq.bits, _T_1079 node _T_1080 = eq(UInt<1>(0h1), idx_16) when _T_1080 : node _T_1081 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_1.io.enq.bits, _T_1081 node _T_1082 = eq(UInt<2>(0h2), idx_16) when _T_1082 : node _T_1083 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_2.io.enq.bits, _T_1083 node _T_1084 = eq(UInt<2>(0h3), idx_16) when _T_1084 : node _T_1085 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_3.io.enq.bits, _T_1085 node _T_1086 = eq(UInt<3>(0h4), idx_16) when _T_1086 : node _T_1087 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_4.io.enq.bits, _T_1087 node _T_1088 = eq(UInt<3>(0h5), idx_16) when _T_1088 : node _T_1089 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_5.io.enq.bits, _T_1089 node _T_1090 = eq(UInt<3>(0h6), idx_16) when _T_1090 : node _T_1091 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_6.io.enq.bits, _T_1091 node _T_1092 = eq(UInt<3>(0h7), idx_16) when _T_1092 : node _T_1093 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_7.io.enq.bits, _T_1093 node _T_1094 = eq(UInt<4>(0h8), idx_16) when _T_1094 : node _T_1095 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_8.io.enq.bits, _T_1095 node _T_1096 = eq(UInt<4>(0h9), idx_16) when _T_1096 : node _T_1097 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_9.io.enq.bits, _T_1097 node _T_1098 = eq(UInt<4>(0ha), idx_16) when _T_1098 : node _T_1099 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_10.io.enq.bits, _T_1099 node _T_1100 = eq(UInt<4>(0hb), idx_16) when _T_1100 : node _T_1101 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_11.io.enq.bits, _T_1101 node _T_1102 = eq(UInt<4>(0hc), idx_16) when _T_1102 : node _T_1103 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_12.io.enq.bits, _T_1103 node _T_1104 = eq(UInt<4>(0hd), idx_16) when _T_1104 : node _T_1105 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_13.io.enq.bits, _T_1105 node _T_1106 = eq(UInt<4>(0he), idx_16) when _T_1106 : node _T_1107 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_14.io.enq.bits, _T_1107 node _T_1108 = eq(UInt<4>(0hf), idx_16) when _T_1108 : node _T_1109 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_15.io.enq.bits, _T_1109 node _T_1110 = eq(UInt<5>(0h10), idx_16) when _T_1110 : node _T_1111 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_16.io.enq.bits, _T_1111 node _T_1112 = eq(UInt<5>(0h11), idx_16) when _T_1112 : node _T_1113 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_17.io.enq.bits, _T_1113 node _T_1114 = eq(UInt<5>(0h12), idx_16) when _T_1114 : node _T_1115 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_18.io.enq.bits, _T_1115 node _T_1116 = eq(UInt<5>(0h13), idx_16) when _T_1116 : node _T_1117 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_19.io.enq.bits, _T_1117 node _T_1118 = eq(UInt<5>(0h14), idx_16) when _T_1118 : node _T_1119 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_20.io.enq.bits, _T_1119 node _T_1120 = eq(UInt<5>(0h15), idx_16) when _T_1120 : node _T_1121 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_21.io.enq.bits, _T_1121 node _T_1122 = eq(UInt<5>(0h16), idx_16) when _T_1122 : node _T_1123 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_22.io.enq.bits, _T_1123 node _T_1124 = eq(UInt<5>(0h17), idx_16) when _T_1124 : node _T_1125 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_23.io.enq.bits, _T_1125 node _T_1126 = eq(UInt<5>(0h18), idx_16) when _T_1126 : node _T_1127 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_24.io.enq.bits, _T_1127 node _T_1128 = eq(UInt<5>(0h19), idx_16) when _T_1128 : node _T_1129 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_25.io.enq.bits, _T_1129 node _T_1130 = eq(UInt<5>(0h1a), idx_16) when _T_1130 : node _T_1131 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_26.io.enq.bits, _T_1131 node _T_1132 = eq(UInt<5>(0h1b), idx_16) when _T_1132 : node _T_1133 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_27.io.enq.bits, _T_1133 node _T_1134 = eq(UInt<5>(0h1c), idx_16) when _T_1134 : node _T_1135 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_28.io.enq.bits, _T_1135 node _T_1136 = eq(UInt<5>(0h1d), idx_16) when _T_1136 : node _T_1137 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_29.io.enq.bits, _T_1137 node _T_1138 = eq(UInt<5>(0h1e), idx_16) when _T_1138 : node _T_1139 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_30.io.enq.bits, _T_1139 node _T_1140 = eq(UInt<5>(0h1f), idx_16) when _T_1140 : node _T_1141 = shr(memresp_bits_shifted, 128) connect Queue32_UInt8_31.io.enq.bits, _T_1141 node _idx_T_17 = add(write_start_index, UInt<5>(0h11)) node idx_17 = rem(_idx_T_17, UInt<6>(0h20)) node _T_1142 = eq(UInt<1>(0h0), idx_17) when _T_1142 : node _T_1143 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8.io.enq.bits, _T_1143 node _T_1144 = eq(UInt<1>(0h1), idx_17) when _T_1144 : node _T_1145 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_1.io.enq.bits, _T_1145 node _T_1146 = eq(UInt<2>(0h2), idx_17) when _T_1146 : node _T_1147 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_2.io.enq.bits, _T_1147 node _T_1148 = eq(UInt<2>(0h3), idx_17) when _T_1148 : node _T_1149 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_3.io.enq.bits, _T_1149 node _T_1150 = eq(UInt<3>(0h4), idx_17) when _T_1150 : node _T_1151 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_4.io.enq.bits, _T_1151 node _T_1152 = eq(UInt<3>(0h5), idx_17) when _T_1152 : node _T_1153 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_5.io.enq.bits, _T_1153 node _T_1154 = eq(UInt<3>(0h6), idx_17) when _T_1154 : node _T_1155 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_6.io.enq.bits, _T_1155 node _T_1156 = eq(UInt<3>(0h7), idx_17) when _T_1156 : node _T_1157 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_7.io.enq.bits, _T_1157 node _T_1158 = eq(UInt<4>(0h8), idx_17) when _T_1158 : node _T_1159 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_8.io.enq.bits, _T_1159 node _T_1160 = eq(UInt<4>(0h9), idx_17) when _T_1160 : node _T_1161 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_9.io.enq.bits, _T_1161 node _T_1162 = eq(UInt<4>(0ha), idx_17) when _T_1162 : node _T_1163 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_10.io.enq.bits, _T_1163 node _T_1164 = eq(UInt<4>(0hb), idx_17) when _T_1164 : node _T_1165 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_11.io.enq.bits, _T_1165 node _T_1166 = eq(UInt<4>(0hc), idx_17) when _T_1166 : node _T_1167 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_12.io.enq.bits, _T_1167 node _T_1168 = eq(UInt<4>(0hd), idx_17) when _T_1168 : node _T_1169 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_13.io.enq.bits, _T_1169 node _T_1170 = eq(UInt<4>(0he), idx_17) when _T_1170 : node _T_1171 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_14.io.enq.bits, _T_1171 node _T_1172 = eq(UInt<4>(0hf), idx_17) when _T_1172 : node _T_1173 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_15.io.enq.bits, _T_1173 node _T_1174 = eq(UInt<5>(0h10), idx_17) when _T_1174 : node _T_1175 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_16.io.enq.bits, _T_1175 node _T_1176 = eq(UInt<5>(0h11), idx_17) when _T_1176 : node _T_1177 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_17.io.enq.bits, _T_1177 node _T_1178 = eq(UInt<5>(0h12), idx_17) when _T_1178 : node _T_1179 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_18.io.enq.bits, _T_1179 node _T_1180 = eq(UInt<5>(0h13), idx_17) when _T_1180 : node _T_1181 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_19.io.enq.bits, _T_1181 node _T_1182 = eq(UInt<5>(0h14), idx_17) when _T_1182 : node _T_1183 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_20.io.enq.bits, _T_1183 node _T_1184 = eq(UInt<5>(0h15), idx_17) when _T_1184 : node _T_1185 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_21.io.enq.bits, _T_1185 node _T_1186 = eq(UInt<5>(0h16), idx_17) when _T_1186 : node _T_1187 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_22.io.enq.bits, _T_1187 node _T_1188 = eq(UInt<5>(0h17), idx_17) when _T_1188 : node _T_1189 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_23.io.enq.bits, _T_1189 node _T_1190 = eq(UInt<5>(0h18), idx_17) when _T_1190 : node _T_1191 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_24.io.enq.bits, _T_1191 node _T_1192 = eq(UInt<5>(0h19), idx_17) when _T_1192 : node _T_1193 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_25.io.enq.bits, _T_1193 node _T_1194 = eq(UInt<5>(0h1a), idx_17) when _T_1194 : node _T_1195 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_26.io.enq.bits, _T_1195 node _T_1196 = eq(UInt<5>(0h1b), idx_17) when _T_1196 : node _T_1197 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_27.io.enq.bits, _T_1197 node _T_1198 = eq(UInt<5>(0h1c), idx_17) when _T_1198 : node _T_1199 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_28.io.enq.bits, _T_1199 node _T_1200 = eq(UInt<5>(0h1d), idx_17) when _T_1200 : node _T_1201 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_29.io.enq.bits, _T_1201 node _T_1202 = eq(UInt<5>(0h1e), idx_17) when _T_1202 : node _T_1203 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_30.io.enq.bits, _T_1203 node _T_1204 = eq(UInt<5>(0h1f), idx_17) when _T_1204 : node _T_1205 = shr(memresp_bits_shifted, 136) connect Queue32_UInt8_31.io.enq.bits, _T_1205 node _idx_T_18 = add(write_start_index, UInt<5>(0h12)) node idx_18 = rem(_idx_T_18, UInt<6>(0h20)) node _T_1206 = eq(UInt<1>(0h0), idx_18) when _T_1206 : node _T_1207 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8.io.enq.bits, _T_1207 node _T_1208 = eq(UInt<1>(0h1), idx_18) when _T_1208 : node _T_1209 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_1.io.enq.bits, _T_1209 node _T_1210 = eq(UInt<2>(0h2), idx_18) when _T_1210 : node _T_1211 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_2.io.enq.bits, _T_1211 node _T_1212 = eq(UInt<2>(0h3), idx_18) when _T_1212 : node _T_1213 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_3.io.enq.bits, _T_1213 node _T_1214 = eq(UInt<3>(0h4), idx_18) when _T_1214 : node _T_1215 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_4.io.enq.bits, _T_1215 node _T_1216 = eq(UInt<3>(0h5), idx_18) when _T_1216 : node _T_1217 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_5.io.enq.bits, _T_1217 node _T_1218 = eq(UInt<3>(0h6), idx_18) when _T_1218 : node _T_1219 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_6.io.enq.bits, _T_1219 node _T_1220 = eq(UInt<3>(0h7), idx_18) when _T_1220 : node _T_1221 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_7.io.enq.bits, _T_1221 node _T_1222 = eq(UInt<4>(0h8), idx_18) when _T_1222 : node _T_1223 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_8.io.enq.bits, _T_1223 node _T_1224 = eq(UInt<4>(0h9), idx_18) when _T_1224 : node _T_1225 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_9.io.enq.bits, _T_1225 node _T_1226 = eq(UInt<4>(0ha), idx_18) when _T_1226 : node _T_1227 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_10.io.enq.bits, _T_1227 node _T_1228 = eq(UInt<4>(0hb), idx_18) when _T_1228 : node _T_1229 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_11.io.enq.bits, _T_1229 node _T_1230 = eq(UInt<4>(0hc), idx_18) when _T_1230 : node _T_1231 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_12.io.enq.bits, _T_1231 node _T_1232 = eq(UInt<4>(0hd), idx_18) when _T_1232 : node _T_1233 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_13.io.enq.bits, _T_1233 node _T_1234 = eq(UInt<4>(0he), idx_18) when _T_1234 : node _T_1235 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_14.io.enq.bits, _T_1235 node _T_1236 = eq(UInt<4>(0hf), idx_18) when _T_1236 : node _T_1237 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_15.io.enq.bits, _T_1237 node _T_1238 = eq(UInt<5>(0h10), idx_18) when _T_1238 : node _T_1239 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_16.io.enq.bits, _T_1239 node _T_1240 = eq(UInt<5>(0h11), idx_18) when _T_1240 : node _T_1241 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_17.io.enq.bits, _T_1241 node _T_1242 = eq(UInt<5>(0h12), idx_18) when _T_1242 : node _T_1243 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_18.io.enq.bits, _T_1243 node _T_1244 = eq(UInt<5>(0h13), idx_18) when _T_1244 : node _T_1245 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_19.io.enq.bits, _T_1245 node _T_1246 = eq(UInt<5>(0h14), idx_18) when _T_1246 : node _T_1247 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_20.io.enq.bits, _T_1247 node _T_1248 = eq(UInt<5>(0h15), idx_18) when _T_1248 : node _T_1249 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_21.io.enq.bits, _T_1249 node _T_1250 = eq(UInt<5>(0h16), idx_18) when _T_1250 : node _T_1251 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_22.io.enq.bits, _T_1251 node _T_1252 = eq(UInt<5>(0h17), idx_18) when _T_1252 : node _T_1253 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_23.io.enq.bits, _T_1253 node _T_1254 = eq(UInt<5>(0h18), idx_18) when _T_1254 : node _T_1255 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_24.io.enq.bits, _T_1255 node _T_1256 = eq(UInt<5>(0h19), idx_18) when _T_1256 : node _T_1257 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_25.io.enq.bits, _T_1257 node _T_1258 = eq(UInt<5>(0h1a), idx_18) when _T_1258 : node _T_1259 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_26.io.enq.bits, _T_1259 node _T_1260 = eq(UInt<5>(0h1b), idx_18) when _T_1260 : node _T_1261 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_27.io.enq.bits, _T_1261 node _T_1262 = eq(UInt<5>(0h1c), idx_18) when _T_1262 : node _T_1263 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_28.io.enq.bits, _T_1263 node _T_1264 = eq(UInt<5>(0h1d), idx_18) when _T_1264 : node _T_1265 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_29.io.enq.bits, _T_1265 node _T_1266 = eq(UInt<5>(0h1e), idx_18) when _T_1266 : node _T_1267 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_30.io.enq.bits, _T_1267 node _T_1268 = eq(UInt<5>(0h1f), idx_18) when _T_1268 : node _T_1269 = shr(memresp_bits_shifted, 144) connect Queue32_UInt8_31.io.enq.bits, _T_1269 node _idx_T_19 = add(write_start_index, UInt<5>(0h13)) node idx_19 = rem(_idx_T_19, UInt<6>(0h20)) node _T_1270 = eq(UInt<1>(0h0), idx_19) when _T_1270 : node _T_1271 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8.io.enq.bits, _T_1271 node _T_1272 = eq(UInt<1>(0h1), idx_19) when _T_1272 : node _T_1273 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_1.io.enq.bits, _T_1273 node _T_1274 = eq(UInt<2>(0h2), idx_19) when _T_1274 : node _T_1275 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_2.io.enq.bits, _T_1275 node _T_1276 = eq(UInt<2>(0h3), idx_19) when _T_1276 : node _T_1277 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_3.io.enq.bits, _T_1277 node _T_1278 = eq(UInt<3>(0h4), idx_19) when _T_1278 : node _T_1279 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_4.io.enq.bits, _T_1279 node _T_1280 = eq(UInt<3>(0h5), idx_19) when _T_1280 : node _T_1281 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_5.io.enq.bits, _T_1281 node _T_1282 = eq(UInt<3>(0h6), idx_19) when _T_1282 : node _T_1283 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_6.io.enq.bits, _T_1283 node _T_1284 = eq(UInt<3>(0h7), idx_19) when _T_1284 : node _T_1285 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_7.io.enq.bits, _T_1285 node _T_1286 = eq(UInt<4>(0h8), idx_19) when _T_1286 : node _T_1287 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_8.io.enq.bits, _T_1287 node _T_1288 = eq(UInt<4>(0h9), idx_19) when _T_1288 : node _T_1289 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_9.io.enq.bits, _T_1289 node _T_1290 = eq(UInt<4>(0ha), idx_19) when _T_1290 : node _T_1291 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_10.io.enq.bits, _T_1291 node _T_1292 = eq(UInt<4>(0hb), idx_19) when _T_1292 : node _T_1293 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_11.io.enq.bits, _T_1293 node _T_1294 = eq(UInt<4>(0hc), idx_19) when _T_1294 : node _T_1295 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_12.io.enq.bits, _T_1295 node _T_1296 = eq(UInt<4>(0hd), idx_19) when _T_1296 : node _T_1297 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_13.io.enq.bits, _T_1297 node _T_1298 = eq(UInt<4>(0he), idx_19) when _T_1298 : node _T_1299 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_14.io.enq.bits, _T_1299 node _T_1300 = eq(UInt<4>(0hf), idx_19) when _T_1300 : node _T_1301 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_15.io.enq.bits, _T_1301 node _T_1302 = eq(UInt<5>(0h10), idx_19) when _T_1302 : node _T_1303 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_16.io.enq.bits, _T_1303 node _T_1304 = eq(UInt<5>(0h11), idx_19) when _T_1304 : node _T_1305 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_17.io.enq.bits, _T_1305 node _T_1306 = eq(UInt<5>(0h12), idx_19) when _T_1306 : node _T_1307 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_18.io.enq.bits, _T_1307 node _T_1308 = eq(UInt<5>(0h13), idx_19) when _T_1308 : node _T_1309 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_19.io.enq.bits, _T_1309 node _T_1310 = eq(UInt<5>(0h14), idx_19) when _T_1310 : node _T_1311 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_20.io.enq.bits, _T_1311 node _T_1312 = eq(UInt<5>(0h15), idx_19) when _T_1312 : node _T_1313 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_21.io.enq.bits, _T_1313 node _T_1314 = eq(UInt<5>(0h16), idx_19) when _T_1314 : node _T_1315 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_22.io.enq.bits, _T_1315 node _T_1316 = eq(UInt<5>(0h17), idx_19) when _T_1316 : node _T_1317 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_23.io.enq.bits, _T_1317 node _T_1318 = eq(UInt<5>(0h18), idx_19) when _T_1318 : node _T_1319 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_24.io.enq.bits, _T_1319 node _T_1320 = eq(UInt<5>(0h19), idx_19) when _T_1320 : node _T_1321 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_25.io.enq.bits, _T_1321 node _T_1322 = eq(UInt<5>(0h1a), idx_19) when _T_1322 : node _T_1323 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_26.io.enq.bits, _T_1323 node _T_1324 = eq(UInt<5>(0h1b), idx_19) when _T_1324 : node _T_1325 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_27.io.enq.bits, _T_1325 node _T_1326 = eq(UInt<5>(0h1c), idx_19) when _T_1326 : node _T_1327 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_28.io.enq.bits, _T_1327 node _T_1328 = eq(UInt<5>(0h1d), idx_19) when _T_1328 : node _T_1329 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_29.io.enq.bits, _T_1329 node _T_1330 = eq(UInt<5>(0h1e), idx_19) when _T_1330 : node _T_1331 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_30.io.enq.bits, _T_1331 node _T_1332 = eq(UInt<5>(0h1f), idx_19) when _T_1332 : node _T_1333 = shr(memresp_bits_shifted, 152) connect Queue32_UInt8_31.io.enq.bits, _T_1333 node _idx_T_20 = add(write_start_index, UInt<5>(0h14)) node idx_20 = rem(_idx_T_20, UInt<6>(0h20)) node _T_1334 = eq(UInt<1>(0h0), idx_20) when _T_1334 : node _T_1335 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8.io.enq.bits, _T_1335 node _T_1336 = eq(UInt<1>(0h1), idx_20) when _T_1336 : node _T_1337 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_1.io.enq.bits, _T_1337 node _T_1338 = eq(UInt<2>(0h2), idx_20) when _T_1338 : node _T_1339 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_2.io.enq.bits, _T_1339 node _T_1340 = eq(UInt<2>(0h3), idx_20) when _T_1340 : node _T_1341 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_3.io.enq.bits, _T_1341 node _T_1342 = eq(UInt<3>(0h4), idx_20) when _T_1342 : node _T_1343 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_4.io.enq.bits, _T_1343 node _T_1344 = eq(UInt<3>(0h5), idx_20) when _T_1344 : node _T_1345 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_5.io.enq.bits, _T_1345 node _T_1346 = eq(UInt<3>(0h6), idx_20) when _T_1346 : node _T_1347 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_6.io.enq.bits, _T_1347 node _T_1348 = eq(UInt<3>(0h7), idx_20) when _T_1348 : node _T_1349 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_7.io.enq.bits, _T_1349 node _T_1350 = eq(UInt<4>(0h8), idx_20) when _T_1350 : node _T_1351 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_8.io.enq.bits, _T_1351 node _T_1352 = eq(UInt<4>(0h9), idx_20) when _T_1352 : node _T_1353 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_9.io.enq.bits, _T_1353 node _T_1354 = eq(UInt<4>(0ha), idx_20) when _T_1354 : node _T_1355 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_10.io.enq.bits, _T_1355 node _T_1356 = eq(UInt<4>(0hb), idx_20) when _T_1356 : node _T_1357 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_11.io.enq.bits, _T_1357 node _T_1358 = eq(UInt<4>(0hc), idx_20) when _T_1358 : node _T_1359 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_12.io.enq.bits, _T_1359 node _T_1360 = eq(UInt<4>(0hd), idx_20) when _T_1360 : node _T_1361 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_13.io.enq.bits, _T_1361 node _T_1362 = eq(UInt<4>(0he), idx_20) when _T_1362 : node _T_1363 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_14.io.enq.bits, _T_1363 node _T_1364 = eq(UInt<4>(0hf), idx_20) when _T_1364 : node _T_1365 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_15.io.enq.bits, _T_1365 node _T_1366 = eq(UInt<5>(0h10), idx_20) when _T_1366 : node _T_1367 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_16.io.enq.bits, _T_1367 node _T_1368 = eq(UInt<5>(0h11), idx_20) when _T_1368 : node _T_1369 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_17.io.enq.bits, _T_1369 node _T_1370 = eq(UInt<5>(0h12), idx_20) when _T_1370 : node _T_1371 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_18.io.enq.bits, _T_1371 node _T_1372 = eq(UInt<5>(0h13), idx_20) when _T_1372 : node _T_1373 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_19.io.enq.bits, _T_1373 node _T_1374 = eq(UInt<5>(0h14), idx_20) when _T_1374 : node _T_1375 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_20.io.enq.bits, _T_1375 node _T_1376 = eq(UInt<5>(0h15), idx_20) when _T_1376 : node _T_1377 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_21.io.enq.bits, _T_1377 node _T_1378 = eq(UInt<5>(0h16), idx_20) when _T_1378 : node _T_1379 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_22.io.enq.bits, _T_1379 node _T_1380 = eq(UInt<5>(0h17), idx_20) when _T_1380 : node _T_1381 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_23.io.enq.bits, _T_1381 node _T_1382 = eq(UInt<5>(0h18), idx_20) when _T_1382 : node _T_1383 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_24.io.enq.bits, _T_1383 node _T_1384 = eq(UInt<5>(0h19), idx_20) when _T_1384 : node _T_1385 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_25.io.enq.bits, _T_1385 node _T_1386 = eq(UInt<5>(0h1a), idx_20) when _T_1386 : node _T_1387 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_26.io.enq.bits, _T_1387 node _T_1388 = eq(UInt<5>(0h1b), idx_20) when _T_1388 : node _T_1389 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_27.io.enq.bits, _T_1389 node _T_1390 = eq(UInt<5>(0h1c), idx_20) when _T_1390 : node _T_1391 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_28.io.enq.bits, _T_1391 node _T_1392 = eq(UInt<5>(0h1d), idx_20) when _T_1392 : node _T_1393 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_29.io.enq.bits, _T_1393 node _T_1394 = eq(UInt<5>(0h1e), idx_20) when _T_1394 : node _T_1395 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_30.io.enq.bits, _T_1395 node _T_1396 = eq(UInt<5>(0h1f), idx_20) when _T_1396 : node _T_1397 = shr(memresp_bits_shifted, 160) connect Queue32_UInt8_31.io.enq.bits, _T_1397 node _idx_T_21 = add(write_start_index, UInt<5>(0h15)) node idx_21 = rem(_idx_T_21, UInt<6>(0h20)) node _T_1398 = eq(UInt<1>(0h0), idx_21) when _T_1398 : node _T_1399 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8.io.enq.bits, _T_1399 node _T_1400 = eq(UInt<1>(0h1), idx_21) when _T_1400 : node _T_1401 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_1.io.enq.bits, _T_1401 node _T_1402 = eq(UInt<2>(0h2), idx_21) when _T_1402 : node _T_1403 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_2.io.enq.bits, _T_1403 node _T_1404 = eq(UInt<2>(0h3), idx_21) when _T_1404 : node _T_1405 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_3.io.enq.bits, _T_1405 node _T_1406 = eq(UInt<3>(0h4), idx_21) when _T_1406 : node _T_1407 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_4.io.enq.bits, _T_1407 node _T_1408 = eq(UInt<3>(0h5), idx_21) when _T_1408 : node _T_1409 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_5.io.enq.bits, _T_1409 node _T_1410 = eq(UInt<3>(0h6), idx_21) when _T_1410 : node _T_1411 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_6.io.enq.bits, _T_1411 node _T_1412 = eq(UInt<3>(0h7), idx_21) when _T_1412 : node _T_1413 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_7.io.enq.bits, _T_1413 node _T_1414 = eq(UInt<4>(0h8), idx_21) when _T_1414 : node _T_1415 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_8.io.enq.bits, _T_1415 node _T_1416 = eq(UInt<4>(0h9), idx_21) when _T_1416 : node _T_1417 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_9.io.enq.bits, _T_1417 node _T_1418 = eq(UInt<4>(0ha), idx_21) when _T_1418 : node _T_1419 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_10.io.enq.bits, _T_1419 node _T_1420 = eq(UInt<4>(0hb), idx_21) when _T_1420 : node _T_1421 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_11.io.enq.bits, _T_1421 node _T_1422 = eq(UInt<4>(0hc), idx_21) when _T_1422 : node _T_1423 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_12.io.enq.bits, _T_1423 node _T_1424 = eq(UInt<4>(0hd), idx_21) when _T_1424 : node _T_1425 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_13.io.enq.bits, _T_1425 node _T_1426 = eq(UInt<4>(0he), idx_21) when _T_1426 : node _T_1427 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_14.io.enq.bits, _T_1427 node _T_1428 = eq(UInt<4>(0hf), idx_21) when _T_1428 : node _T_1429 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_15.io.enq.bits, _T_1429 node _T_1430 = eq(UInt<5>(0h10), idx_21) when _T_1430 : node _T_1431 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_16.io.enq.bits, _T_1431 node _T_1432 = eq(UInt<5>(0h11), idx_21) when _T_1432 : node _T_1433 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_17.io.enq.bits, _T_1433 node _T_1434 = eq(UInt<5>(0h12), idx_21) when _T_1434 : node _T_1435 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_18.io.enq.bits, _T_1435 node _T_1436 = eq(UInt<5>(0h13), idx_21) when _T_1436 : node _T_1437 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_19.io.enq.bits, _T_1437 node _T_1438 = eq(UInt<5>(0h14), idx_21) when _T_1438 : node _T_1439 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_20.io.enq.bits, _T_1439 node _T_1440 = eq(UInt<5>(0h15), idx_21) when _T_1440 : node _T_1441 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_21.io.enq.bits, _T_1441 node _T_1442 = eq(UInt<5>(0h16), idx_21) when _T_1442 : node _T_1443 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_22.io.enq.bits, _T_1443 node _T_1444 = eq(UInt<5>(0h17), idx_21) when _T_1444 : node _T_1445 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_23.io.enq.bits, _T_1445 node _T_1446 = eq(UInt<5>(0h18), idx_21) when _T_1446 : node _T_1447 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_24.io.enq.bits, _T_1447 node _T_1448 = eq(UInt<5>(0h19), idx_21) when _T_1448 : node _T_1449 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_25.io.enq.bits, _T_1449 node _T_1450 = eq(UInt<5>(0h1a), idx_21) when _T_1450 : node _T_1451 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_26.io.enq.bits, _T_1451 node _T_1452 = eq(UInt<5>(0h1b), idx_21) when _T_1452 : node _T_1453 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_27.io.enq.bits, _T_1453 node _T_1454 = eq(UInt<5>(0h1c), idx_21) when _T_1454 : node _T_1455 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_28.io.enq.bits, _T_1455 node _T_1456 = eq(UInt<5>(0h1d), idx_21) when _T_1456 : node _T_1457 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_29.io.enq.bits, _T_1457 node _T_1458 = eq(UInt<5>(0h1e), idx_21) when _T_1458 : node _T_1459 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_30.io.enq.bits, _T_1459 node _T_1460 = eq(UInt<5>(0h1f), idx_21) when _T_1460 : node _T_1461 = shr(memresp_bits_shifted, 168) connect Queue32_UInt8_31.io.enq.bits, _T_1461 node _idx_T_22 = add(write_start_index, UInt<5>(0h16)) node idx_22 = rem(_idx_T_22, UInt<6>(0h20)) node _T_1462 = eq(UInt<1>(0h0), idx_22) when _T_1462 : node _T_1463 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8.io.enq.bits, _T_1463 node _T_1464 = eq(UInt<1>(0h1), idx_22) when _T_1464 : node _T_1465 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_1.io.enq.bits, _T_1465 node _T_1466 = eq(UInt<2>(0h2), idx_22) when _T_1466 : node _T_1467 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_2.io.enq.bits, _T_1467 node _T_1468 = eq(UInt<2>(0h3), idx_22) when _T_1468 : node _T_1469 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_3.io.enq.bits, _T_1469 node _T_1470 = eq(UInt<3>(0h4), idx_22) when _T_1470 : node _T_1471 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_4.io.enq.bits, _T_1471 node _T_1472 = eq(UInt<3>(0h5), idx_22) when _T_1472 : node _T_1473 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_5.io.enq.bits, _T_1473 node _T_1474 = eq(UInt<3>(0h6), idx_22) when _T_1474 : node _T_1475 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_6.io.enq.bits, _T_1475 node _T_1476 = eq(UInt<3>(0h7), idx_22) when _T_1476 : node _T_1477 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_7.io.enq.bits, _T_1477 node _T_1478 = eq(UInt<4>(0h8), idx_22) when _T_1478 : node _T_1479 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_8.io.enq.bits, _T_1479 node _T_1480 = eq(UInt<4>(0h9), idx_22) when _T_1480 : node _T_1481 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_9.io.enq.bits, _T_1481 node _T_1482 = eq(UInt<4>(0ha), idx_22) when _T_1482 : node _T_1483 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_10.io.enq.bits, _T_1483 node _T_1484 = eq(UInt<4>(0hb), idx_22) when _T_1484 : node _T_1485 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_11.io.enq.bits, _T_1485 node _T_1486 = eq(UInt<4>(0hc), idx_22) when _T_1486 : node _T_1487 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_12.io.enq.bits, _T_1487 node _T_1488 = eq(UInt<4>(0hd), idx_22) when _T_1488 : node _T_1489 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_13.io.enq.bits, _T_1489 node _T_1490 = eq(UInt<4>(0he), idx_22) when _T_1490 : node _T_1491 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_14.io.enq.bits, _T_1491 node _T_1492 = eq(UInt<4>(0hf), idx_22) when _T_1492 : node _T_1493 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_15.io.enq.bits, _T_1493 node _T_1494 = eq(UInt<5>(0h10), idx_22) when _T_1494 : node _T_1495 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_16.io.enq.bits, _T_1495 node _T_1496 = eq(UInt<5>(0h11), idx_22) when _T_1496 : node _T_1497 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_17.io.enq.bits, _T_1497 node _T_1498 = eq(UInt<5>(0h12), idx_22) when _T_1498 : node _T_1499 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_18.io.enq.bits, _T_1499 node _T_1500 = eq(UInt<5>(0h13), idx_22) when _T_1500 : node _T_1501 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_19.io.enq.bits, _T_1501 node _T_1502 = eq(UInt<5>(0h14), idx_22) when _T_1502 : node _T_1503 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_20.io.enq.bits, _T_1503 node _T_1504 = eq(UInt<5>(0h15), idx_22) when _T_1504 : node _T_1505 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_21.io.enq.bits, _T_1505 node _T_1506 = eq(UInt<5>(0h16), idx_22) when _T_1506 : node _T_1507 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_22.io.enq.bits, _T_1507 node _T_1508 = eq(UInt<5>(0h17), idx_22) when _T_1508 : node _T_1509 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_23.io.enq.bits, _T_1509 node _T_1510 = eq(UInt<5>(0h18), idx_22) when _T_1510 : node _T_1511 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_24.io.enq.bits, _T_1511 node _T_1512 = eq(UInt<5>(0h19), idx_22) when _T_1512 : node _T_1513 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_25.io.enq.bits, _T_1513 node _T_1514 = eq(UInt<5>(0h1a), idx_22) when _T_1514 : node _T_1515 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_26.io.enq.bits, _T_1515 node _T_1516 = eq(UInt<5>(0h1b), idx_22) when _T_1516 : node _T_1517 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_27.io.enq.bits, _T_1517 node _T_1518 = eq(UInt<5>(0h1c), idx_22) when _T_1518 : node _T_1519 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_28.io.enq.bits, _T_1519 node _T_1520 = eq(UInt<5>(0h1d), idx_22) when _T_1520 : node _T_1521 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_29.io.enq.bits, _T_1521 node _T_1522 = eq(UInt<5>(0h1e), idx_22) when _T_1522 : node _T_1523 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_30.io.enq.bits, _T_1523 node _T_1524 = eq(UInt<5>(0h1f), idx_22) when _T_1524 : node _T_1525 = shr(memresp_bits_shifted, 176) connect Queue32_UInt8_31.io.enq.bits, _T_1525 node _idx_T_23 = add(write_start_index, UInt<5>(0h17)) node idx_23 = rem(_idx_T_23, UInt<6>(0h20)) node _T_1526 = eq(UInt<1>(0h0), idx_23) when _T_1526 : node _T_1527 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8.io.enq.bits, _T_1527 node _T_1528 = eq(UInt<1>(0h1), idx_23) when _T_1528 : node _T_1529 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_1.io.enq.bits, _T_1529 node _T_1530 = eq(UInt<2>(0h2), idx_23) when _T_1530 : node _T_1531 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_2.io.enq.bits, _T_1531 node _T_1532 = eq(UInt<2>(0h3), idx_23) when _T_1532 : node _T_1533 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_3.io.enq.bits, _T_1533 node _T_1534 = eq(UInt<3>(0h4), idx_23) when _T_1534 : node _T_1535 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_4.io.enq.bits, _T_1535 node _T_1536 = eq(UInt<3>(0h5), idx_23) when _T_1536 : node _T_1537 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_5.io.enq.bits, _T_1537 node _T_1538 = eq(UInt<3>(0h6), idx_23) when _T_1538 : node _T_1539 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_6.io.enq.bits, _T_1539 node _T_1540 = eq(UInt<3>(0h7), idx_23) when _T_1540 : node _T_1541 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_7.io.enq.bits, _T_1541 node _T_1542 = eq(UInt<4>(0h8), idx_23) when _T_1542 : node _T_1543 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_8.io.enq.bits, _T_1543 node _T_1544 = eq(UInt<4>(0h9), idx_23) when _T_1544 : node _T_1545 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_9.io.enq.bits, _T_1545 node _T_1546 = eq(UInt<4>(0ha), idx_23) when _T_1546 : node _T_1547 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_10.io.enq.bits, _T_1547 node _T_1548 = eq(UInt<4>(0hb), idx_23) when _T_1548 : node _T_1549 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_11.io.enq.bits, _T_1549 node _T_1550 = eq(UInt<4>(0hc), idx_23) when _T_1550 : node _T_1551 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_12.io.enq.bits, _T_1551 node _T_1552 = eq(UInt<4>(0hd), idx_23) when _T_1552 : node _T_1553 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_13.io.enq.bits, _T_1553 node _T_1554 = eq(UInt<4>(0he), idx_23) when _T_1554 : node _T_1555 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_14.io.enq.bits, _T_1555 node _T_1556 = eq(UInt<4>(0hf), idx_23) when _T_1556 : node _T_1557 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_15.io.enq.bits, _T_1557 node _T_1558 = eq(UInt<5>(0h10), idx_23) when _T_1558 : node _T_1559 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_16.io.enq.bits, _T_1559 node _T_1560 = eq(UInt<5>(0h11), idx_23) when _T_1560 : node _T_1561 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_17.io.enq.bits, _T_1561 node _T_1562 = eq(UInt<5>(0h12), idx_23) when _T_1562 : node _T_1563 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_18.io.enq.bits, _T_1563 node _T_1564 = eq(UInt<5>(0h13), idx_23) when _T_1564 : node _T_1565 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_19.io.enq.bits, _T_1565 node _T_1566 = eq(UInt<5>(0h14), idx_23) when _T_1566 : node _T_1567 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_20.io.enq.bits, _T_1567 node _T_1568 = eq(UInt<5>(0h15), idx_23) when _T_1568 : node _T_1569 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_21.io.enq.bits, _T_1569 node _T_1570 = eq(UInt<5>(0h16), idx_23) when _T_1570 : node _T_1571 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_22.io.enq.bits, _T_1571 node _T_1572 = eq(UInt<5>(0h17), idx_23) when _T_1572 : node _T_1573 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_23.io.enq.bits, _T_1573 node _T_1574 = eq(UInt<5>(0h18), idx_23) when _T_1574 : node _T_1575 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_24.io.enq.bits, _T_1575 node _T_1576 = eq(UInt<5>(0h19), idx_23) when _T_1576 : node _T_1577 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_25.io.enq.bits, _T_1577 node _T_1578 = eq(UInt<5>(0h1a), idx_23) when _T_1578 : node _T_1579 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_26.io.enq.bits, _T_1579 node _T_1580 = eq(UInt<5>(0h1b), idx_23) when _T_1580 : node _T_1581 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_27.io.enq.bits, _T_1581 node _T_1582 = eq(UInt<5>(0h1c), idx_23) when _T_1582 : node _T_1583 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_28.io.enq.bits, _T_1583 node _T_1584 = eq(UInt<5>(0h1d), idx_23) when _T_1584 : node _T_1585 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_29.io.enq.bits, _T_1585 node _T_1586 = eq(UInt<5>(0h1e), idx_23) when _T_1586 : node _T_1587 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_30.io.enq.bits, _T_1587 node _T_1588 = eq(UInt<5>(0h1f), idx_23) when _T_1588 : node _T_1589 = shr(memresp_bits_shifted, 184) connect Queue32_UInt8_31.io.enq.bits, _T_1589 node _idx_T_24 = add(write_start_index, UInt<5>(0h18)) node idx_24 = rem(_idx_T_24, UInt<6>(0h20)) node _T_1590 = eq(UInt<1>(0h0), idx_24) when _T_1590 : node _T_1591 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8.io.enq.bits, _T_1591 node _T_1592 = eq(UInt<1>(0h1), idx_24) when _T_1592 : node _T_1593 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_1.io.enq.bits, _T_1593 node _T_1594 = eq(UInt<2>(0h2), idx_24) when _T_1594 : node _T_1595 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_2.io.enq.bits, _T_1595 node _T_1596 = eq(UInt<2>(0h3), idx_24) when _T_1596 : node _T_1597 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_3.io.enq.bits, _T_1597 node _T_1598 = eq(UInt<3>(0h4), idx_24) when _T_1598 : node _T_1599 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_4.io.enq.bits, _T_1599 node _T_1600 = eq(UInt<3>(0h5), idx_24) when _T_1600 : node _T_1601 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_5.io.enq.bits, _T_1601 node _T_1602 = eq(UInt<3>(0h6), idx_24) when _T_1602 : node _T_1603 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_6.io.enq.bits, _T_1603 node _T_1604 = eq(UInt<3>(0h7), idx_24) when _T_1604 : node _T_1605 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_7.io.enq.bits, _T_1605 node _T_1606 = eq(UInt<4>(0h8), idx_24) when _T_1606 : node _T_1607 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_8.io.enq.bits, _T_1607 node _T_1608 = eq(UInt<4>(0h9), idx_24) when _T_1608 : node _T_1609 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_9.io.enq.bits, _T_1609 node _T_1610 = eq(UInt<4>(0ha), idx_24) when _T_1610 : node _T_1611 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_10.io.enq.bits, _T_1611 node _T_1612 = eq(UInt<4>(0hb), idx_24) when _T_1612 : node _T_1613 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_11.io.enq.bits, _T_1613 node _T_1614 = eq(UInt<4>(0hc), idx_24) when _T_1614 : node _T_1615 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_12.io.enq.bits, _T_1615 node _T_1616 = eq(UInt<4>(0hd), idx_24) when _T_1616 : node _T_1617 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_13.io.enq.bits, _T_1617 node _T_1618 = eq(UInt<4>(0he), idx_24) when _T_1618 : node _T_1619 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_14.io.enq.bits, _T_1619 node _T_1620 = eq(UInt<4>(0hf), idx_24) when _T_1620 : node _T_1621 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_15.io.enq.bits, _T_1621 node _T_1622 = eq(UInt<5>(0h10), idx_24) when _T_1622 : node _T_1623 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_16.io.enq.bits, _T_1623 node _T_1624 = eq(UInt<5>(0h11), idx_24) when _T_1624 : node _T_1625 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_17.io.enq.bits, _T_1625 node _T_1626 = eq(UInt<5>(0h12), idx_24) when _T_1626 : node _T_1627 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_18.io.enq.bits, _T_1627 node _T_1628 = eq(UInt<5>(0h13), idx_24) when _T_1628 : node _T_1629 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_19.io.enq.bits, _T_1629 node _T_1630 = eq(UInt<5>(0h14), idx_24) when _T_1630 : node _T_1631 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_20.io.enq.bits, _T_1631 node _T_1632 = eq(UInt<5>(0h15), idx_24) when _T_1632 : node _T_1633 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_21.io.enq.bits, _T_1633 node _T_1634 = eq(UInt<5>(0h16), idx_24) when _T_1634 : node _T_1635 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_22.io.enq.bits, _T_1635 node _T_1636 = eq(UInt<5>(0h17), idx_24) when _T_1636 : node _T_1637 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_23.io.enq.bits, _T_1637 node _T_1638 = eq(UInt<5>(0h18), idx_24) when _T_1638 : node _T_1639 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_24.io.enq.bits, _T_1639 node _T_1640 = eq(UInt<5>(0h19), idx_24) when _T_1640 : node _T_1641 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_25.io.enq.bits, _T_1641 node _T_1642 = eq(UInt<5>(0h1a), idx_24) when _T_1642 : node _T_1643 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_26.io.enq.bits, _T_1643 node _T_1644 = eq(UInt<5>(0h1b), idx_24) when _T_1644 : node _T_1645 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_27.io.enq.bits, _T_1645 node _T_1646 = eq(UInt<5>(0h1c), idx_24) when _T_1646 : node _T_1647 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_28.io.enq.bits, _T_1647 node _T_1648 = eq(UInt<5>(0h1d), idx_24) when _T_1648 : node _T_1649 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_29.io.enq.bits, _T_1649 node _T_1650 = eq(UInt<5>(0h1e), idx_24) when _T_1650 : node _T_1651 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_30.io.enq.bits, _T_1651 node _T_1652 = eq(UInt<5>(0h1f), idx_24) when _T_1652 : node _T_1653 = shr(memresp_bits_shifted, 192) connect Queue32_UInt8_31.io.enq.bits, _T_1653 node _idx_T_25 = add(write_start_index, UInt<5>(0h19)) node idx_25 = rem(_idx_T_25, UInt<6>(0h20)) node _T_1654 = eq(UInt<1>(0h0), idx_25) when _T_1654 : node _T_1655 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8.io.enq.bits, _T_1655 node _T_1656 = eq(UInt<1>(0h1), idx_25) when _T_1656 : node _T_1657 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_1.io.enq.bits, _T_1657 node _T_1658 = eq(UInt<2>(0h2), idx_25) when _T_1658 : node _T_1659 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_2.io.enq.bits, _T_1659 node _T_1660 = eq(UInt<2>(0h3), idx_25) when _T_1660 : node _T_1661 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_3.io.enq.bits, _T_1661 node _T_1662 = eq(UInt<3>(0h4), idx_25) when _T_1662 : node _T_1663 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_4.io.enq.bits, _T_1663 node _T_1664 = eq(UInt<3>(0h5), idx_25) when _T_1664 : node _T_1665 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_5.io.enq.bits, _T_1665 node _T_1666 = eq(UInt<3>(0h6), idx_25) when _T_1666 : node _T_1667 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_6.io.enq.bits, _T_1667 node _T_1668 = eq(UInt<3>(0h7), idx_25) when _T_1668 : node _T_1669 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_7.io.enq.bits, _T_1669 node _T_1670 = eq(UInt<4>(0h8), idx_25) when _T_1670 : node _T_1671 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_8.io.enq.bits, _T_1671 node _T_1672 = eq(UInt<4>(0h9), idx_25) when _T_1672 : node _T_1673 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_9.io.enq.bits, _T_1673 node _T_1674 = eq(UInt<4>(0ha), idx_25) when _T_1674 : node _T_1675 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_10.io.enq.bits, _T_1675 node _T_1676 = eq(UInt<4>(0hb), idx_25) when _T_1676 : node _T_1677 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_11.io.enq.bits, _T_1677 node _T_1678 = eq(UInt<4>(0hc), idx_25) when _T_1678 : node _T_1679 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_12.io.enq.bits, _T_1679 node _T_1680 = eq(UInt<4>(0hd), idx_25) when _T_1680 : node _T_1681 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_13.io.enq.bits, _T_1681 node _T_1682 = eq(UInt<4>(0he), idx_25) when _T_1682 : node _T_1683 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_14.io.enq.bits, _T_1683 node _T_1684 = eq(UInt<4>(0hf), idx_25) when _T_1684 : node _T_1685 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_15.io.enq.bits, _T_1685 node _T_1686 = eq(UInt<5>(0h10), idx_25) when _T_1686 : node _T_1687 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_16.io.enq.bits, _T_1687 node _T_1688 = eq(UInt<5>(0h11), idx_25) when _T_1688 : node _T_1689 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_17.io.enq.bits, _T_1689 node _T_1690 = eq(UInt<5>(0h12), idx_25) when _T_1690 : node _T_1691 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_18.io.enq.bits, _T_1691 node _T_1692 = eq(UInt<5>(0h13), idx_25) when _T_1692 : node _T_1693 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_19.io.enq.bits, _T_1693 node _T_1694 = eq(UInt<5>(0h14), idx_25) when _T_1694 : node _T_1695 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_20.io.enq.bits, _T_1695 node _T_1696 = eq(UInt<5>(0h15), idx_25) when _T_1696 : node _T_1697 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_21.io.enq.bits, _T_1697 node _T_1698 = eq(UInt<5>(0h16), idx_25) when _T_1698 : node _T_1699 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_22.io.enq.bits, _T_1699 node _T_1700 = eq(UInt<5>(0h17), idx_25) when _T_1700 : node _T_1701 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_23.io.enq.bits, _T_1701 node _T_1702 = eq(UInt<5>(0h18), idx_25) when _T_1702 : node _T_1703 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_24.io.enq.bits, _T_1703 node _T_1704 = eq(UInt<5>(0h19), idx_25) when _T_1704 : node _T_1705 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_25.io.enq.bits, _T_1705 node _T_1706 = eq(UInt<5>(0h1a), idx_25) when _T_1706 : node _T_1707 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_26.io.enq.bits, _T_1707 node _T_1708 = eq(UInt<5>(0h1b), idx_25) when _T_1708 : node _T_1709 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_27.io.enq.bits, _T_1709 node _T_1710 = eq(UInt<5>(0h1c), idx_25) when _T_1710 : node _T_1711 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_28.io.enq.bits, _T_1711 node _T_1712 = eq(UInt<5>(0h1d), idx_25) when _T_1712 : node _T_1713 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_29.io.enq.bits, _T_1713 node _T_1714 = eq(UInt<5>(0h1e), idx_25) when _T_1714 : node _T_1715 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_30.io.enq.bits, _T_1715 node _T_1716 = eq(UInt<5>(0h1f), idx_25) when _T_1716 : node _T_1717 = shr(memresp_bits_shifted, 200) connect Queue32_UInt8_31.io.enq.bits, _T_1717 node _idx_T_26 = add(write_start_index, UInt<5>(0h1a)) node idx_26 = rem(_idx_T_26, UInt<6>(0h20)) node _T_1718 = eq(UInt<1>(0h0), idx_26) when _T_1718 : node _T_1719 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8.io.enq.bits, _T_1719 node _T_1720 = eq(UInt<1>(0h1), idx_26) when _T_1720 : node _T_1721 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_1.io.enq.bits, _T_1721 node _T_1722 = eq(UInt<2>(0h2), idx_26) when _T_1722 : node _T_1723 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_2.io.enq.bits, _T_1723 node _T_1724 = eq(UInt<2>(0h3), idx_26) when _T_1724 : node _T_1725 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_3.io.enq.bits, _T_1725 node _T_1726 = eq(UInt<3>(0h4), idx_26) when _T_1726 : node _T_1727 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_4.io.enq.bits, _T_1727 node _T_1728 = eq(UInt<3>(0h5), idx_26) when _T_1728 : node _T_1729 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_5.io.enq.bits, _T_1729 node _T_1730 = eq(UInt<3>(0h6), idx_26) when _T_1730 : node _T_1731 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_6.io.enq.bits, _T_1731 node _T_1732 = eq(UInt<3>(0h7), idx_26) when _T_1732 : node _T_1733 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_7.io.enq.bits, _T_1733 node _T_1734 = eq(UInt<4>(0h8), idx_26) when _T_1734 : node _T_1735 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_8.io.enq.bits, _T_1735 node _T_1736 = eq(UInt<4>(0h9), idx_26) when _T_1736 : node _T_1737 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_9.io.enq.bits, _T_1737 node _T_1738 = eq(UInt<4>(0ha), idx_26) when _T_1738 : node _T_1739 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_10.io.enq.bits, _T_1739 node _T_1740 = eq(UInt<4>(0hb), idx_26) when _T_1740 : node _T_1741 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_11.io.enq.bits, _T_1741 node _T_1742 = eq(UInt<4>(0hc), idx_26) when _T_1742 : node _T_1743 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_12.io.enq.bits, _T_1743 node _T_1744 = eq(UInt<4>(0hd), idx_26) when _T_1744 : node _T_1745 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_13.io.enq.bits, _T_1745 node _T_1746 = eq(UInt<4>(0he), idx_26) when _T_1746 : node _T_1747 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_14.io.enq.bits, _T_1747 node _T_1748 = eq(UInt<4>(0hf), idx_26) when _T_1748 : node _T_1749 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_15.io.enq.bits, _T_1749 node _T_1750 = eq(UInt<5>(0h10), idx_26) when _T_1750 : node _T_1751 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_16.io.enq.bits, _T_1751 node _T_1752 = eq(UInt<5>(0h11), idx_26) when _T_1752 : node _T_1753 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_17.io.enq.bits, _T_1753 node _T_1754 = eq(UInt<5>(0h12), idx_26) when _T_1754 : node _T_1755 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_18.io.enq.bits, _T_1755 node _T_1756 = eq(UInt<5>(0h13), idx_26) when _T_1756 : node _T_1757 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_19.io.enq.bits, _T_1757 node _T_1758 = eq(UInt<5>(0h14), idx_26) when _T_1758 : node _T_1759 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_20.io.enq.bits, _T_1759 node _T_1760 = eq(UInt<5>(0h15), idx_26) when _T_1760 : node _T_1761 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_21.io.enq.bits, _T_1761 node _T_1762 = eq(UInt<5>(0h16), idx_26) when _T_1762 : node _T_1763 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_22.io.enq.bits, _T_1763 node _T_1764 = eq(UInt<5>(0h17), idx_26) when _T_1764 : node _T_1765 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_23.io.enq.bits, _T_1765 node _T_1766 = eq(UInt<5>(0h18), idx_26) when _T_1766 : node _T_1767 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_24.io.enq.bits, _T_1767 node _T_1768 = eq(UInt<5>(0h19), idx_26) when _T_1768 : node _T_1769 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_25.io.enq.bits, _T_1769 node _T_1770 = eq(UInt<5>(0h1a), idx_26) when _T_1770 : node _T_1771 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_26.io.enq.bits, _T_1771 node _T_1772 = eq(UInt<5>(0h1b), idx_26) when _T_1772 : node _T_1773 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_27.io.enq.bits, _T_1773 node _T_1774 = eq(UInt<5>(0h1c), idx_26) when _T_1774 : node _T_1775 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_28.io.enq.bits, _T_1775 node _T_1776 = eq(UInt<5>(0h1d), idx_26) when _T_1776 : node _T_1777 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_29.io.enq.bits, _T_1777 node _T_1778 = eq(UInt<5>(0h1e), idx_26) when _T_1778 : node _T_1779 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_30.io.enq.bits, _T_1779 node _T_1780 = eq(UInt<5>(0h1f), idx_26) when _T_1780 : node _T_1781 = shr(memresp_bits_shifted, 208) connect Queue32_UInt8_31.io.enq.bits, _T_1781 node _idx_T_27 = add(write_start_index, UInt<5>(0h1b)) node idx_27 = rem(_idx_T_27, UInt<6>(0h20)) node _T_1782 = eq(UInt<1>(0h0), idx_27) when _T_1782 : node _T_1783 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8.io.enq.bits, _T_1783 node _T_1784 = eq(UInt<1>(0h1), idx_27) when _T_1784 : node _T_1785 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_1.io.enq.bits, _T_1785 node _T_1786 = eq(UInt<2>(0h2), idx_27) when _T_1786 : node _T_1787 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_2.io.enq.bits, _T_1787 node _T_1788 = eq(UInt<2>(0h3), idx_27) when _T_1788 : node _T_1789 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_3.io.enq.bits, _T_1789 node _T_1790 = eq(UInt<3>(0h4), idx_27) when _T_1790 : node _T_1791 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_4.io.enq.bits, _T_1791 node _T_1792 = eq(UInt<3>(0h5), idx_27) when _T_1792 : node _T_1793 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_5.io.enq.bits, _T_1793 node _T_1794 = eq(UInt<3>(0h6), idx_27) when _T_1794 : node _T_1795 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_6.io.enq.bits, _T_1795 node _T_1796 = eq(UInt<3>(0h7), idx_27) when _T_1796 : node _T_1797 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_7.io.enq.bits, _T_1797 node _T_1798 = eq(UInt<4>(0h8), idx_27) when _T_1798 : node _T_1799 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_8.io.enq.bits, _T_1799 node _T_1800 = eq(UInt<4>(0h9), idx_27) when _T_1800 : node _T_1801 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_9.io.enq.bits, _T_1801 node _T_1802 = eq(UInt<4>(0ha), idx_27) when _T_1802 : node _T_1803 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_10.io.enq.bits, _T_1803 node _T_1804 = eq(UInt<4>(0hb), idx_27) when _T_1804 : node _T_1805 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_11.io.enq.bits, _T_1805 node _T_1806 = eq(UInt<4>(0hc), idx_27) when _T_1806 : node _T_1807 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_12.io.enq.bits, _T_1807 node _T_1808 = eq(UInt<4>(0hd), idx_27) when _T_1808 : node _T_1809 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_13.io.enq.bits, _T_1809 node _T_1810 = eq(UInt<4>(0he), idx_27) when _T_1810 : node _T_1811 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_14.io.enq.bits, _T_1811 node _T_1812 = eq(UInt<4>(0hf), idx_27) when _T_1812 : node _T_1813 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_15.io.enq.bits, _T_1813 node _T_1814 = eq(UInt<5>(0h10), idx_27) when _T_1814 : node _T_1815 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_16.io.enq.bits, _T_1815 node _T_1816 = eq(UInt<5>(0h11), idx_27) when _T_1816 : node _T_1817 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_17.io.enq.bits, _T_1817 node _T_1818 = eq(UInt<5>(0h12), idx_27) when _T_1818 : node _T_1819 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_18.io.enq.bits, _T_1819 node _T_1820 = eq(UInt<5>(0h13), idx_27) when _T_1820 : node _T_1821 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_19.io.enq.bits, _T_1821 node _T_1822 = eq(UInt<5>(0h14), idx_27) when _T_1822 : node _T_1823 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_20.io.enq.bits, _T_1823 node _T_1824 = eq(UInt<5>(0h15), idx_27) when _T_1824 : node _T_1825 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_21.io.enq.bits, _T_1825 node _T_1826 = eq(UInt<5>(0h16), idx_27) when _T_1826 : node _T_1827 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_22.io.enq.bits, _T_1827 node _T_1828 = eq(UInt<5>(0h17), idx_27) when _T_1828 : node _T_1829 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_23.io.enq.bits, _T_1829 node _T_1830 = eq(UInt<5>(0h18), idx_27) when _T_1830 : node _T_1831 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_24.io.enq.bits, _T_1831 node _T_1832 = eq(UInt<5>(0h19), idx_27) when _T_1832 : node _T_1833 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_25.io.enq.bits, _T_1833 node _T_1834 = eq(UInt<5>(0h1a), idx_27) when _T_1834 : node _T_1835 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_26.io.enq.bits, _T_1835 node _T_1836 = eq(UInt<5>(0h1b), idx_27) when _T_1836 : node _T_1837 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_27.io.enq.bits, _T_1837 node _T_1838 = eq(UInt<5>(0h1c), idx_27) when _T_1838 : node _T_1839 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_28.io.enq.bits, _T_1839 node _T_1840 = eq(UInt<5>(0h1d), idx_27) when _T_1840 : node _T_1841 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_29.io.enq.bits, _T_1841 node _T_1842 = eq(UInt<5>(0h1e), idx_27) when _T_1842 : node _T_1843 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_30.io.enq.bits, _T_1843 node _T_1844 = eq(UInt<5>(0h1f), idx_27) when _T_1844 : node _T_1845 = shr(memresp_bits_shifted, 216) connect Queue32_UInt8_31.io.enq.bits, _T_1845 node _idx_T_28 = add(write_start_index, UInt<5>(0h1c)) node idx_28 = rem(_idx_T_28, UInt<6>(0h20)) node _T_1846 = eq(UInt<1>(0h0), idx_28) when _T_1846 : node _T_1847 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8.io.enq.bits, _T_1847 node _T_1848 = eq(UInt<1>(0h1), idx_28) when _T_1848 : node _T_1849 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_1.io.enq.bits, _T_1849 node _T_1850 = eq(UInt<2>(0h2), idx_28) when _T_1850 : node _T_1851 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_2.io.enq.bits, _T_1851 node _T_1852 = eq(UInt<2>(0h3), idx_28) when _T_1852 : node _T_1853 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_3.io.enq.bits, _T_1853 node _T_1854 = eq(UInt<3>(0h4), idx_28) when _T_1854 : node _T_1855 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_4.io.enq.bits, _T_1855 node _T_1856 = eq(UInt<3>(0h5), idx_28) when _T_1856 : node _T_1857 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_5.io.enq.bits, _T_1857 node _T_1858 = eq(UInt<3>(0h6), idx_28) when _T_1858 : node _T_1859 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_6.io.enq.bits, _T_1859 node _T_1860 = eq(UInt<3>(0h7), idx_28) when _T_1860 : node _T_1861 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_7.io.enq.bits, _T_1861 node _T_1862 = eq(UInt<4>(0h8), idx_28) when _T_1862 : node _T_1863 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_8.io.enq.bits, _T_1863 node _T_1864 = eq(UInt<4>(0h9), idx_28) when _T_1864 : node _T_1865 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_9.io.enq.bits, _T_1865 node _T_1866 = eq(UInt<4>(0ha), idx_28) when _T_1866 : node _T_1867 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_10.io.enq.bits, _T_1867 node _T_1868 = eq(UInt<4>(0hb), idx_28) when _T_1868 : node _T_1869 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_11.io.enq.bits, _T_1869 node _T_1870 = eq(UInt<4>(0hc), idx_28) when _T_1870 : node _T_1871 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_12.io.enq.bits, _T_1871 node _T_1872 = eq(UInt<4>(0hd), idx_28) when _T_1872 : node _T_1873 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_13.io.enq.bits, _T_1873 node _T_1874 = eq(UInt<4>(0he), idx_28) when _T_1874 : node _T_1875 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_14.io.enq.bits, _T_1875 node _T_1876 = eq(UInt<4>(0hf), idx_28) when _T_1876 : node _T_1877 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_15.io.enq.bits, _T_1877 node _T_1878 = eq(UInt<5>(0h10), idx_28) when _T_1878 : node _T_1879 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_16.io.enq.bits, _T_1879 node _T_1880 = eq(UInt<5>(0h11), idx_28) when _T_1880 : node _T_1881 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_17.io.enq.bits, _T_1881 node _T_1882 = eq(UInt<5>(0h12), idx_28) when _T_1882 : node _T_1883 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_18.io.enq.bits, _T_1883 node _T_1884 = eq(UInt<5>(0h13), idx_28) when _T_1884 : node _T_1885 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_19.io.enq.bits, _T_1885 node _T_1886 = eq(UInt<5>(0h14), idx_28) when _T_1886 : node _T_1887 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_20.io.enq.bits, _T_1887 node _T_1888 = eq(UInt<5>(0h15), idx_28) when _T_1888 : node _T_1889 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_21.io.enq.bits, _T_1889 node _T_1890 = eq(UInt<5>(0h16), idx_28) when _T_1890 : node _T_1891 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_22.io.enq.bits, _T_1891 node _T_1892 = eq(UInt<5>(0h17), idx_28) when _T_1892 : node _T_1893 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_23.io.enq.bits, _T_1893 node _T_1894 = eq(UInt<5>(0h18), idx_28) when _T_1894 : node _T_1895 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_24.io.enq.bits, _T_1895 node _T_1896 = eq(UInt<5>(0h19), idx_28) when _T_1896 : node _T_1897 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_25.io.enq.bits, _T_1897 node _T_1898 = eq(UInt<5>(0h1a), idx_28) when _T_1898 : node _T_1899 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_26.io.enq.bits, _T_1899 node _T_1900 = eq(UInt<5>(0h1b), idx_28) when _T_1900 : node _T_1901 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_27.io.enq.bits, _T_1901 node _T_1902 = eq(UInt<5>(0h1c), idx_28) when _T_1902 : node _T_1903 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_28.io.enq.bits, _T_1903 node _T_1904 = eq(UInt<5>(0h1d), idx_28) when _T_1904 : node _T_1905 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_29.io.enq.bits, _T_1905 node _T_1906 = eq(UInt<5>(0h1e), idx_28) when _T_1906 : node _T_1907 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_30.io.enq.bits, _T_1907 node _T_1908 = eq(UInt<5>(0h1f), idx_28) when _T_1908 : node _T_1909 = shr(memresp_bits_shifted, 224) connect Queue32_UInt8_31.io.enq.bits, _T_1909 node _idx_T_29 = add(write_start_index, UInt<5>(0h1d)) node idx_29 = rem(_idx_T_29, UInt<6>(0h20)) node _T_1910 = eq(UInt<1>(0h0), idx_29) when _T_1910 : node _T_1911 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8.io.enq.bits, _T_1911 node _T_1912 = eq(UInt<1>(0h1), idx_29) when _T_1912 : node _T_1913 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_1.io.enq.bits, _T_1913 node _T_1914 = eq(UInt<2>(0h2), idx_29) when _T_1914 : node _T_1915 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_2.io.enq.bits, _T_1915 node _T_1916 = eq(UInt<2>(0h3), idx_29) when _T_1916 : node _T_1917 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_3.io.enq.bits, _T_1917 node _T_1918 = eq(UInt<3>(0h4), idx_29) when _T_1918 : node _T_1919 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_4.io.enq.bits, _T_1919 node _T_1920 = eq(UInt<3>(0h5), idx_29) when _T_1920 : node _T_1921 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_5.io.enq.bits, _T_1921 node _T_1922 = eq(UInt<3>(0h6), idx_29) when _T_1922 : node _T_1923 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_6.io.enq.bits, _T_1923 node _T_1924 = eq(UInt<3>(0h7), idx_29) when _T_1924 : node _T_1925 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_7.io.enq.bits, _T_1925 node _T_1926 = eq(UInt<4>(0h8), idx_29) when _T_1926 : node _T_1927 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_8.io.enq.bits, _T_1927 node _T_1928 = eq(UInt<4>(0h9), idx_29) when _T_1928 : node _T_1929 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_9.io.enq.bits, _T_1929 node _T_1930 = eq(UInt<4>(0ha), idx_29) when _T_1930 : node _T_1931 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_10.io.enq.bits, _T_1931 node _T_1932 = eq(UInt<4>(0hb), idx_29) when _T_1932 : node _T_1933 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_11.io.enq.bits, _T_1933 node _T_1934 = eq(UInt<4>(0hc), idx_29) when _T_1934 : node _T_1935 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_12.io.enq.bits, _T_1935 node _T_1936 = eq(UInt<4>(0hd), idx_29) when _T_1936 : node _T_1937 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_13.io.enq.bits, _T_1937 node _T_1938 = eq(UInt<4>(0he), idx_29) when _T_1938 : node _T_1939 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_14.io.enq.bits, _T_1939 node _T_1940 = eq(UInt<4>(0hf), idx_29) when _T_1940 : node _T_1941 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_15.io.enq.bits, _T_1941 node _T_1942 = eq(UInt<5>(0h10), idx_29) when _T_1942 : node _T_1943 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_16.io.enq.bits, _T_1943 node _T_1944 = eq(UInt<5>(0h11), idx_29) when _T_1944 : node _T_1945 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_17.io.enq.bits, _T_1945 node _T_1946 = eq(UInt<5>(0h12), idx_29) when _T_1946 : node _T_1947 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_18.io.enq.bits, _T_1947 node _T_1948 = eq(UInt<5>(0h13), idx_29) when _T_1948 : node _T_1949 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_19.io.enq.bits, _T_1949 node _T_1950 = eq(UInt<5>(0h14), idx_29) when _T_1950 : node _T_1951 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_20.io.enq.bits, _T_1951 node _T_1952 = eq(UInt<5>(0h15), idx_29) when _T_1952 : node _T_1953 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_21.io.enq.bits, _T_1953 node _T_1954 = eq(UInt<5>(0h16), idx_29) when _T_1954 : node _T_1955 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_22.io.enq.bits, _T_1955 node _T_1956 = eq(UInt<5>(0h17), idx_29) when _T_1956 : node _T_1957 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_23.io.enq.bits, _T_1957 node _T_1958 = eq(UInt<5>(0h18), idx_29) when _T_1958 : node _T_1959 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_24.io.enq.bits, _T_1959 node _T_1960 = eq(UInt<5>(0h19), idx_29) when _T_1960 : node _T_1961 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_25.io.enq.bits, _T_1961 node _T_1962 = eq(UInt<5>(0h1a), idx_29) when _T_1962 : node _T_1963 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_26.io.enq.bits, _T_1963 node _T_1964 = eq(UInt<5>(0h1b), idx_29) when _T_1964 : node _T_1965 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_27.io.enq.bits, _T_1965 node _T_1966 = eq(UInt<5>(0h1c), idx_29) when _T_1966 : node _T_1967 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_28.io.enq.bits, _T_1967 node _T_1968 = eq(UInt<5>(0h1d), idx_29) when _T_1968 : node _T_1969 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_29.io.enq.bits, _T_1969 node _T_1970 = eq(UInt<5>(0h1e), idx_29) when _T_1970 : node _T_1971 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_30.io.enq.bits, _T_1971 node _T_1972 = eq(UInt<5>(0h1f), idx_29) when _T_1972 : node _T_1973 = shr(memresp_bits_shifted, 232) connect Queue32_UInt8_31.io.enq.bits, _T_1973 node _idx_T_30 = add(write_start_index, UInt<5>(0h1e)) node idx_30 = rem(_idx_T_30, UInt<6>(0h20)) node _T_1974 = eq(UInt<1>(0h0), idx_30) when _T_1974 : node _T_1975 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8.io.enq.bits, _T_1975 node _T_1976 = eq(UInt<1>(0h1), idx_30) when _T_1976 : node _T_1977 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_1.io.enq.bits, _T_1977 node _T_1978 = eq(UInt<2>(0h2), idx_30) when _T_1978 : node _T_1979 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_2.io.enq.bits, _T_1979 node _T_1980 = eq(UInt<2>(0h3), idx_30) when _T_1980 : node _T_1981 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_3.io.enq.bits, _T_1981 node _T_1982 = eq(UInt<3>(0h4), idx_30) when _T_1982 : node _T_1983 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_4.io.enq.bits, _T_1983 node _T_1984 = eq(UInt<3>(0h5), idx_30) when _T_1984 : node _T_1985 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_5.io.enq.bits, _T_1985 node _T_1986 = eq(UInt<3>(0h6), idx_30) when _T_1986 : node _T_1987 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_6.io.enq.bits, _T_1987 node _T_1988 = eq(UInt<3>(0h7), idx_30) when _T_1988 : node _T_1989 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_7.io.enq.bits, _T_1989 node _T_1990 = eq(UInt<4>(0h8), idx_30) when _T_1990 : node _T_1991 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_8.io.enq.bits, _T_1991 node _T_1992 = eq(UInt<4>(0h9), idx_30) when _T_1992 : node _T_1993 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_9.io.enq.bits, _T_1993 node _T_1994 = eq(UInt<4>(0ha), idx_30) when _T_1994 : node _T_1995 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_10.io.enq.bits, _T_1995 node _T_1996 = eq(UInt<4>(0hb), idx_30) when _T_1996 : node _T_1997 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_11.io.enq.bits, _T_1997 node _T_1998 = eq(UInt<4>(0hc), idx_30) when _T_1998 : node _T_1999 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_12.io.enq.bits, _T_1999 node _T_2000 = eq(UInt<4>(0hd), idx_30) when _T_2000 : node _T_2001 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_13.io.enq.bits, _T_2001 node _T_2002 = eq(UInt<4>(0he), idx_30) when _T_2002 : node _T_2003 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_14.io.enq.bits, _T_2003 node _T_2004 = eq(UInt<4>(0hf), idx_30) when _T_2004 : node _T_2005 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_15.io.enq.bits, _T_2005 node _T_2006 = eq(UInt<5>(0h10), idx_30) when _T_2006 : node _T_2007 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_16.io.enq.bits, _T_2007 node _T_2008 = eq(UInt<5>(0h11), idx_30) when _T_2008 : node _T_2009 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_17.io.enq.bits, _T_2009 node _T_2010 = eq(UInt<5>(0h12), idx_30) when _T_2010 : node _T_2011 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_18.io.enq.bits, _T_2011 node _T_2012 = eq(UInt<5>(0h13), idx_30) when _T_2012 : node _T_2013 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_19.io.enq.bits, _T_2013 node _T_2014 = eq(UInt<5>(0h14), idx_30) when _T_2014 : node _T_2015 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_20.io.enq.bits, _T_2015 node _T_2016 = eq(UInt<5>(0h15), idx_30) when _T_2016 : node _T_2017 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_21.io.enq.bits, _T_2017 node _T_2018 = eq(UInt<5>(0h16), idx_30) when _T_2018 : node _T_2019 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_22.io.enq.bits, _T_2019 node _T_2020 = eq(UInt<5>(0h17), idx_30) when _T_2020 : node _T_2021 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_23.io.enq.bits, _T_2021 node _T_2022 = eq(UInt<5>(0h18), idx_30) when _T_2022 : node _T_2023 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_24.io.enq.bits, _T_2023 node _T_2024 = eq(UInt<5>(0h19), idx_30) when _T_2024 : node _T_2025 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_25.io.enq.bits, _T_2025 node _T_2026 = eq(UInt<5>(0h1a), idx_30) when _T_2026 : node _T_2027 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_26.io.enq.bits, _T_2027 node _T_2028 = eq(UInt<5>(0h1b), idx_30) when _T_2028 : node _T_2029 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_27.io.enq.bits, _T_2029 node _T_2030 = eq(UInt<5>(0h1c), idx_30) when _T_2030 : node _T_2031 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_28.io.enq.bits, _T_2031 node _T_2032 = eq(UInt<5>(0h1d), idx_30) when _T_2032 : node _T_2033 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_29.io.enq.bits, _T_2033 node _T_2034 = eq(UInt<5>(0h1e), idx_30) when _T_2034 : node _T_2035 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_30.io.enq.bits, _T_2035 node _T_2036 = eq(UInt<5>(0h1f), idx_30) when _T_2036 : node _T_2037 = shr(memresp_bits_shifted, 240) connect Queue32_UInt8_31.io.enq.bits, _T_2037 node _idx_T_31 = add(write_start_index, UInt<5>(0h1f)) node idx_31 = rem(_idx_T_31, UInt<6>(0h20)) node _T_2038 = eq(UInt<1>(0h0), idx_31) when _T_2038 : node _T_2039 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8.io.enq.bits, _T_2039 node _T_2040 = eq(UInt<1>(0h1), idx_31) when _T_2040 : node _T_2041 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_1.io.enq.bits, _T_2041 node _T_2042 = eq(UInt<2>(0h2), idx_31) when _T_2042 : node _T_2043 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_2.io.enq.bits, _T_2043 node _T_2044 = eq(UInt<2>(0h3), idx_31) when _T_2044 : node _T_2045 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_3.io.enq.bits, _T_2045 node _T_2046 = eq(UInt<3>(0h4), idx_31) when _T_2046 : node _T_2047 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_4.io.enq.bits, _T_2047 node _T_2048 = eq(UInt<3>(0h5), idx_31) when _T_2048 : node _T_2049 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_5.io.enq.bits, _T_2049 node _T_2050 = eq(UInt<3>(0h6), idx_31) when _T_2050 : node _T_2051 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_6.io.enq.bits, _T_2051 node _T_2052 = eq(UInt<3>(0h7), idx_31) when _T_2052 : node _T_2053 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_7.io.enq.bits, _T_2053 node _T_2054 = eq(UInt<4>(0h8), idx_31) when _T_2054 : node _T_2055 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_8.io.enq.bits, _T_2055 node _T_2056 = eq(UInt<4>(0h9), idx_31) when _T_2056 : node _T_2057 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_9.io.enq.bits, _T_2057 node _T_2058 = eq(UInt<4>(0ha), idx_31) when _T_2058 : node _T_2059 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_10.io.enq.bits, _T_2059 node _T_2060 = eq(UInt<4>(0hb), idx_31) when _T_2060 : node _T_2061 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_11.io.enq.bits, _T_2061 node _T_2062 = eq(UInt<4>(0hc), idx_31) when _T_2062 : node _T_2063 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_12.io.enq.bits, _T_2063 node _T_2064 = eq(UInt<4>(0hd), idx_31) when _T_2064 : node _T_2065 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_13.io.enq.bits, _T_2065 node _T_2066 = eq(UInt<4>(0he), idx_31) when _T_2066 : node _T_2067 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_14.io.enq.bits, _T_2067 node _T_2068 = eq(UInt<4>(0hf), idx_31) when _T_2068 : node _T_2069 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_15.io.enq.bits, _T_2069 node _T_2070 = eq(UInt<5>(0h10), idx_31) when _T_2070 : node _T_2071 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_16.io.enq.bits, _T_2071 node _T_2072 = eq(UInt<5>(0h11), idx_31) when _T_2072 : node _T_2073 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_17.io.enq.bits, _T_2073 node _T_2074 = eq(UInt<5>(0h12), idx_31) when _T_2074 : node _T_2075 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_18.io.enq.bits, _T_2075 node _T_2076 = eq(UInt<5>(0h13), idx_31) when _T_2076 : node _T_2077 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_19.io.enq.bits, _T_2077 node _T_2078 = eq(UInt<5>(0h14), idx_31) when _T_2078 : node _T_2079 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_20.io.enq.bits, _T_2079 node _T_2080 = eq(UInt<5>(0h15), idx_31) when _T_2080 : node _T_2081 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_21.io.enq.bits, _T_2081 node _T_2082 = eq(UInt<5>(0h16), idx_31) when _T_2082 : node _T_2083 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_22.io.enq.bits, _T_2083 node _T_2084 = eq(UInt<5>(0h17), idx_31) when _T_2084 : node _T_2085 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_23.io.enq.bits, _T_2085 node _T_2086 = eq(UInt<5>(0h18), idx_31) when _T_2086 : node _T_2087 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_24.io.enq.bits, _T_2087 node _T_2088 = eq(UInt<5>(0h19), idx_31) when _T_2088 : node _T_2089 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_25.io.enq.bits, _T_2089 node _T_2090 = eq(UInt<5>(0h1a), idx_31) when _T_2090 : node _T_2091 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_26.io.enq.bits, _T_2091 node _T_2092 = eq(UInt<5>(0h1b), idx_31) when _T_2092 : node _T_2093 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_27.io.enq.bits, _T_2093 node _T_2094 = eq(UInt<5>(0h1c), idx_31) when _T_2094 : node _T_2095 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_28.io.enq.bits, _T_2095 node _T_2096 = eq(UInt<5>(0h1d), idx_31) when _T_2096 : node _T_2097 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_29.io.enq.bits, _T_2097 node _T_2098 = eq(UInt<5>(0h1e), idx_31) when _T_2098 : node _T_2099 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_30.io.enq.bits, _T_2099 node _T_2100 = eq(UInt<5>(0h1f), idx_31) when _T_2100 : node _T_2101 = shr(memresp_bits_shifted, 248) connect Queue32_UInt8_31.io.enq.bits, _T_2101 node _len_to_write_T = sub(load_info_queue.io.deq.bits.end_byte, load_info_queue.io.deq.bits.start_byte) node _len_to_write_T_1 = tail(_len_to_write_T, 1) node len_to_write = add(_len_to_write_T_1, UInt<1>(0h1)) node wrap_len_index_wide = add(write_start_index, len_to_write) node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20)) node wrapped = geq(wrap_len_index_wide, UInt<6>(0h20)) when load_info_queue.io.deq.valid : regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_2102 = asUInt(reset) node _T_2103 = eq(_T_2102, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22 node _T_2104 = asUInt(reset) node _T_2105 = eq(_T_2104, UInt<1>(0h0)) when _T_2105 : printf(clock, UInt<1>(0h1), "memloader start %x, end %x\n", load_info_queue.io.deq.bits.start_byte, load_info_queue.io.deq.bits.end_byte) : printf_23 node _all_queues_ready_T = and(Queue32_UInt8.io.enq.ready, Queue32_UInt8_1.io.enq.ready) node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue32_UInt8_2.io.enq.ready) node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue32_UInt8_3.io.enq.ready) node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue32_UInt8_4.io.enq.ready) node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue32_UInt8_5.io.enq.ready) node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue32_UInt8_6.io.enq.ready) node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue32_UInt8_7.io.enq.ready) node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue32_UInt8_8.io.enq.ready) node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue32_UInt8_9.io.enq.ready) node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue32_UInt8_10.io.enq.ready) node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue32_UInt8_11.io.enq.ready) node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue32_UInt8_12.io.enq.ready) node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue32_UInt8_13.io.enq.ready) node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue32_UInt8_14.io.enq.ready) node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue32_UInt8_15.io.enq.ready) node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue32_UInt8_16.io.enq.ready) node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue32_UInt8_17.io.enq.ready) node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue32_UInt8_18.io.enq.ready) node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue32_UInt8_19.io.enq.ready) node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue32_UInt8_20.io.enq.ready) node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue32_UInt8_21.io.enq.ready) node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue32_UInt8_22.io.enq.ready) node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue32_UInt8_23.io.enq.ready) node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue32_UInt8_24.io.enq.ready) node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue32_UInt8_25.io.enq.ready) node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue32_UInt8_26.io.enq.ready) node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue32_UInt8_27.io.enq.ready) node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue32_UInt8_28.io.enq.ready) node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue32_UInt8_29.io.enq.ready) node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue32_UInt8_30.io.enq.ready) node all_queues_ready = and(_all_queues_ready_T_29, Queue32_UInt8_31.io.enq.ready) node _load_info_queue_io_deq_ready_T = and(io.l2helperUser.resp.valid, all_queues_ready) connect load_info_queue.io.deq.ready, _load_info_queue_io_deq_ready_T node _io_l2helperUser_resp_ready_T = and(load_info_queue.io.deq.valid, all_queues_ready) connect io.l2helperUser.resp.ready, _io_l2helperUser_resp_ready_T node _io_optional_hbsram_write_valid_T = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _io_optional_hbsram_write_valid_T_1 = and(_io_optional_hbsram_write_valid_T, all_queues_ready) connect io.optional_hbsram_write.valid, _io_optional_hbsram_write_valid_T_1 connect io.optional_hbsram_write.bits.data, memresp_bits_shifted connect io.optional_hbsram_write.bits.valid_bytes, len_to_write node _resp_fire_allqueues_T = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node resp_fire_allqueues = and(_resp_fire_allqueues_T, all_queues_ready) when resp_fire_allqueues : connect write_start_index, wrap_len_index_end node _use_this_queue_T = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_1 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_2 = or(_use_this_queue_T, _use_this_queue_T_1) node _use_this_queue_T_3 = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_4 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_5 = and(_use_this_queue_T_3, _use_this_queue_T_4) node use_this_queue = mux(wrapped, _use_this_queue_T_2, _use_this_queue_T_5) node _T_2106 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2107 = and(_T_2106, use_this_queue) node _T_2108 = and(_T_2107, all_queues_ready) connect Queue32_UInt8.io.enq.valid, _T_2108 node _use_this_queue_T_6 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_7 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_8 = or(_use_this_queue_T_6, _use_this_queue_T_7) node _use_this_queue_T_9 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_10 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_11 = and(_use_this_queue_T_9, _use_this_queue_T_10) node use_this_queue_1 = mux(wrapped, _use_this_queue_T_8, _use_this_queue_T_11) node _T_2109 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2110 = and(_T_2109, use_this_queue_1) node _T_2111 = and(_T_2110, all_queues_ready) connect Queue32_UInt8_1.io.enq.valid, _T_2111 node _use_this_queue_T_12 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_13 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_14 = or(_use_this_queue_T_12, _use_this_queue_T_13) node _use_this_queue_T_15 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_16 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_17 = and(_use_this_queue_T_15, _use_this_queue_T_16) node use_this_queue_2 = mux(wrapped, _use_this_queue_T_14, _use_this_queue_T_17) node _T_2112 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2113 = and(_T_2112, use_this_queue_2) node _T_2114 = and(_T_2113, all_queues_ready) connect Queue32_UInt8_2.io.enq.valid, _T_2114 node _use_this_queue_T_18 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_19 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_20 = or(_use_this_queue_T_18, _use_this_queue_T_19) node _use_this_queue_T_21 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_22 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_23 = and(_use_this_queue_T_21, _use_this_queue_T_22) node use_this_queue_3 = mux(wrapped, _use_this_queue_T_20, _use_this_queue_T_23) node _T_2115 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2116 = and(_T_2115, use_this_queue_3) node _T_2117 = and(_T_2116, all_queues_ready) connect Queue32_UInt8_3.io.enq.valid, _T_2117 node _use_this_queue_T_24 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_25 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_26 = or(_use_this_queue_T_24, _use_this_queue_T_25) node _use_this_queue_T_27 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_28 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_29 = and(_use_this_queue_T_27, _use_this_queue_T_28) node use_this_queue_4 = mux(wrapped, _use_this_queue_T_26, _use_this_queue_T_29) node _T_2118 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2119 = and(_T_2118, use_this_queue_4) node _T_2120 = and(_T_2119, all_queues_ready) connect Queue32_UInt8_4.io.enq.valid, _T_2120 node _use_this_queue_T_30 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_31 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31) node _use_this_queue_T_33 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_34 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_35 = and(_use_this_queue_T_33, _use_this_queue_T_34) node use_this_queue_5 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_35) node _T_2121 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2122 = and(_T_2121, use_this_queue_5) node _T_2123 = and(_T_2122, all_queues_ready) connect Queue32_UInt8_5.io.enq.valid, _T_2123 node _use_this_queue_T_36 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_37 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_38 = or(_use_this_queue_T_36, _use_this_queue_T_37) node _use_this_queue_T_39 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_40 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_41 = and(_use_this_queue_T_39, _use_this_queue_T_40) node use_this_queue_6 = mux(wrapped, _use_this_queue_T_38, _use_this_queue_T_41) node _T_2124 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2125 = and(_T_2124, use_this_queue_6) node _T_2126 = and(_T_2125, all_queues_ready) connect Queue32_UInt8_6.io.enq.valid, _T_2126 node _use_this_queue_T_42 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_43 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_44 = or(_use_this_queue_T_42, _use_this_queue_T_43) node _use_this_queue_T_45 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_46 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_47 = and(_use_this_queue_T_45, _use_this_queue_T_46) node use_this_queue_7 = mux(wrapped, _use_this_queue_T_44, _use_this_queue_T_47) node _T_2127 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2128 = and(_T_2127, use_this_queue_7) node _T_2129 = and(_T_2128, all_queues_ready) connect Queue32_UInt8_7.io.enq.valid, _T_2129 node _use_this_queue_T_48 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_49 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_50 = or(_use_this_queue_T_48, _use_this_queue_T_49) node _use_this_queue_T_51 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_52 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_53 = and(_use_this_queue_T_51, _use_this_queue_T_52) node use_this_queue_8 = mux(wrapped, _use_this_queue_T_50, _use_this_queue_T_53) node _T_2130 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2131 = and(_T_2130, use_this_queue_8) node _T_2132 = and(_T_2131, all_queues_ready) connect Queue32_UInt8_8.io.enq.valid, _T_2132 node _use_this_queue_T_54 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_55 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_56 = or(_use_this_queue_T_54, _use_this_queue_T_55) node _use_this_queue_T_57 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_58 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_59 = and(_use_this_queue_T_57, _use_this_queue_T_58) node use_this_queue_9 = mux(wrapped, _use_this_queue_T_56, _use_this_queue_T_59) node _T_2133 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2134 = and(_T_2133, use_this_queue_9) node _T_2135 = and(_T_2134, all_queues_ready) connect Queue32_UInt8_9.io.enq.valid, _T_2135 node _use_this_queue_T_60 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_61 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_62 = or(_use_this_queue_T_60, _use_this_queue_T_61) node _use_this_queue_T_63 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_64 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_65 = and(_use_this_queue_T_63, _use_this_queue_T_64) node use_this_queue_10 = mux(wrapped, _use_this_queue_T_62, _use_this_queue_T_65) node _T_2136 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2137 = and(_T_2136, use_this_queue_10) node _T_2138 = and(_T_2137, all_queues_ready) connect Queue32_UInt8_10.io.enq.valid, _T_2138 node _use_this_queue_T_66 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_67 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_68 = or(_use_this_queue_T_66, _use_this_queue_T_67) node _use_this_queue_T_69 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_70 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_71 = and(_use_this_queue_T_69, _use_this_queue_T_70) node use_this_queue_11 = mux(wrapped, _use_this_queue_T_68, _use_this_queue_T_71) node _T_2139 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2140 = and(_T_2139, use_this_queue_11) node _T_2141 = and(_T_2140, all_queues_ready) connect Queue32_UInt8_11.io.enq.valid, _T_2141 node _use_this_queue_T_72 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_73 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73) node _use_this_queue_T_75 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_76 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_77 = and(_use_this_queue_T_75, _use_this_queue_T_76) node use_this_queue_12 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_77) node _T_2142 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2143 = and(_T_2142, use_this_queue_12) node _T_2144 = and(_T_2143, all_queues_ready) connect Queue32_UInt8_12.io.enq.valid, _T_2144 node _use_this_queue_T_78 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_79 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_80 = or(_use_this_queue_T_78, _use_this_queue_T_79) node _use_this_queue_T_81 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_82 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_83 = and(_use_this_queue_T_81, _use_this_queue_T_82) node use_this_queue_13 = mux(wrapped, _use_this_queue_T_80, _use_this_queue_T_83) node _T_2145 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2146 = and(_T_2145, use_this_queue_13) node _T_2147 = and(_T_2146, all_queues_ready) connect Queue32_UInt8_13.io.enq.valid, _T_2147 node _use_this_queue_T_84 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_85 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_86 = or(_use_this_queue_T_84, _use_this_queue_T_85) node _use_this_queue_T_87 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_88 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_89 = and(_use_this_queue_T_87, _use_this_queue_T_88) node use_this_queue_14 = mux(wrapped, _use_this_queue_T_86, _use_this_queue_T_89) node _T_2148 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2149 = and(_T_2148, use_this_queue_14) node _T_2150 = and(_T_2149, all_queues_ready) connect Queue32_UInt8_14.io.enq.valid, _T_2150 node _use_this_queue_T_90 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_91 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_92 = or(_use_this_queue_T_90, _use_this_queue_T_91) node _use_this_queue_T_93 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_94 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_95 = and(_use_this_queue_T_93, _use_this_queue_T_94) node use_this_queue_15 = mux(wrapped, _use_this_queue_T_92, _use_this_queue_T_95) node _T_2151 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2152 = and(_T_2151, use_this_queue_15) node _T_2153 = and(_T_2152, all_queues_ready) connect Queue32_UInt8_15.io.enq.valid, _T_2153 node _use_this_queue_T_96 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_97 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_98 = or(_use_this_queue_T_96, _use_this_queue_T_97) node _use_this_queue_T_99 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_100 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_101 = and(_use_this_queue_T_99, _use_this_queue_T_100) node use_this_queue_16 = mux(wrapped, _use_this_queue_T_98, _use_this_queue_T_101) node _T_2154 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2155 = and(_T_2154, use_this_queue_16) node _T_2156 = and(_T_2155, all_queues_ready) connect Queue32_UInt8_16.io.enq.valid, _T_2156 node _use_this_queue_T_102 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_103 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_104 = or(_use_this_queue_T_102, _use_this_queue_T_103) node _use_this_queue_T_105 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_106 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_107 = and(_use_this_queue_T_105, _use_this_queue_T_106) node use_this_queue_17 = mux(wrapped, _use_this_queue_T_104, _use_this_queue_T_107) node _T_2157 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2158 = and(_T_2157, use_this_queue_17) node _T_2159 = and(_T_2158, all_queues_ready) connect Queue32_UInt8_17.io.enq.valid, _T_2159 node _use_this_queue_T_108 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_109 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_110 = or(_use_this_queue_T_108, _use_this_queue_T_109) node _use_this_queue_T_111 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_112 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_113 = and(_use_this_queue_T_111, _use_this_queue_T_112) node use_this_queue_18 = mux(wrapped, _use_this_queue_T_110, _use_this_queue_T_113) node _T_2160 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2161 = and(_T_2160, use_this_queue_18) node _T_2162 = and(_T_2161, all_queues_ready) connect Queue32_UInt8_18.io.enq.valid, _T_2162 node _use_this_queue_T_114 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_115 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115) node _use_this_queue_T_117 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_118 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_119 = and(_use_this_queue_T_117, _use_this_queue_T_118) node use_this_queue_19 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_119) node _T_2163 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2164 = and(_T_2163, use_this_queue_19) node _T_2165 = and(_T_2164, all_queues_ready) connect Queue32_UInt8_19.io.enq.valid, _T_2165 node _use_this_queue_T_120 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_121 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_122 = or(_use_this_queue_T_120, _use_this_queue_T_121) node _use_this_queue_T_123 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_124 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_125 = and(_use_this_queue_T_123, _use_this_queue_T_124) node use_this_queue_20 = mux(wrapped, _use_this_queue_T_122, _use_this_queue_T_125) node _T_2166 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2167 = and(_T_2166, use_this_queue_20) node _T_2168 = and(_T_2167, all_queues_ready) connect Queue32_UInt8_20.io.enq.valid, _T_2168 node _use_this_queue_T_126 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_127 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_128 = or(_use_this_queue_T_126, _use_this_queue_T_127) node _use_this_queue_T_129 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_130 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_131 = and(_use_this_queue_T_129, _use_this_queue_T_130) node use_this_queue_21 = mux(wrapped, _use_this_queue_T_128, _use_this_queue_T_131) node _T_2169 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2170 = and(_T_2169, use_this_queue_21) node _T_2171 = and(_T_2170, all_queues_ready) connect Queue32_UInt8_21.io.enq.valid, _T_2171 node _use_this_queue_T_132 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_133 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_134 = or(_use_this_queue_T_132, _use_this_queue_T_133) node _use_this_queue_T_135 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_136 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_137 = and(_use_this_queue_T_135, _use_this_queue_T_136) node use_this_queue_22 = mux(wrapped, _use_this_queue_T_134, _use_this_queue_T_137) node _T_2172 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2173 = and(_T_2172, use_this_queue_22) node _T_2174 = and(_T_2173, all_queues_ready) connect Queue32_UInt8_22.io.enq.valid, _T_2174 node _use_this_queue_T_138 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_139 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_140 = or(_use_this_queue_T_138, _use_this_queue_T_139) node _use_this_queue_T_141 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_142 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_143 = and(_use_this_queue_T_141, _use_this_queue_T_142) node use_this_queue_23 = mux(wrapped, _use_this_queue_T_140, _use_this_queue_T_143) node _T_2175 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2176 = and(_T_2175, use_this_queue_23) node _T_2177 = and(_T_2176, all_queues_ready) connect Queue32_UInt8_23.io.enq.valid, _T_2177 node _use_this_queue_T_144 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_145 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_146 = or(_use_this_queue_T_144, _use_this_queue_T_145) node _use_this_queue_T_147 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_148 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_149 = and(_use_this_queue_T_147, _use_this_queue_T_148) node use_this_queue_24 = mux(wrapped, _use_this_queue_T_146, _use_this_queue_T_149) node _T_2178 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2179 = and(_T_2178, use_this_queue_24) node _T_2180 = and(_T_2179, all_queues_ready) connect Queue32_UInt8_24.io.enq.valid, _T_2180 node _use_this_queue_T_150 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_151 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_152 = or(_use_this_queue_T_150, _use_this_queue_T_151) node _use_this_queue_T_153 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_154 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_155 = and(_use_this_queue_T_153, _use_this_queue_T_154) node use_this_queue_25 = mux(wrapped, _use_this_queue_T_152, _use_this_queue_T_155) node _T_2181 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2182 = and(_T_2181, use_this_queue_25) node _T_2183 = and(_T_2182, all_queues_ready) connect Queue32_UInt8_25.io.enq.valid, _T_2183 node _use_this_queue_T_156 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_157 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157) node _use_this_queue_T_159 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_160 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_161 = and(_use_this_queue_T_159, _use_this_queue_T_160) node use_this_queue_26 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_161) node _T_2184 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2185 = and(_T_2184, use_this_queue_26) node _T_2186 = and(_T_2185, all_queues_ready) connect Queue32_UInt8_26.io.enq.valid, _T_2186 node _use_this_queue_T_162 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_163 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_164 = or(_use_this_queue_T_162, _use_this_queue_T_163) node _use_this_queue_T_165 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_166 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_167 = and(_use_this_queue_T_165, _use_this_queue_T_166) node use_this_queue_27 = mux(wrapped, _use_this_queue_T_164, _use_this_queue_T_167) node _T_2187 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2188 = and(_T_2187, use_this_queue_27) node _T_2189 = and(_T_2188, all_queues_ready) connect Queue32_UInt8_27.io.enq.valid, _T_2189 node _use_this_queue_T_168 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_169 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_170 = or(_use_this_queue_T_168, _use_this_queue_T_169) node _use_this_queue_T_171 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_172 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_173 = and(_use_this_queue_T_171, _use_this_queue_T_172) node use_this_queue_28 = mux(wrapped, _use_this_queue_T_170, _use_this_queue_T_173) node _T_2190 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2191 = and(_T_2190, use_this_queue_28) node _T_2192 = and(_T_2191, all_queues_ready) connect Queue32_UInt8_28.io.enq.valid, _T_2192 node _use_this_queue_T_174 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_175 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_176 = or(_use_this_queue_T_174, _use_this_queue_T_175) node _use_this_queue_T_177 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_178 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_179 = and(_use_this_queue_T_177, _use_this_queue_T_178) node use_this_queue_29 = mux(wrapped, _use_this_queue_T_176, _use_this_queue_T_179) node _T_2193 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2194 = and(_T_2193, use_this_queue_29) node _T_2195 = and(_T_2194, all_queues_ready) connect Queue32_UInt8_29.io.enq.valid, _T_2195 node _use_this_queue_T_180 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_181 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_182 = or(_use_this_queue_T_180, _use_this_queue_T_181) node _use_this_queue_T_183 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_184 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_185 = and(_use_this_queue_T_183, _use_this_queue_T_184) node use_this_queue_30 = mux(wrapped, _use_this_queue_T_182, _use_this_queue_T_185) node _T_2196 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2197 = and(_T_2196, use_this_queue_30) node _T_2198 = and(_T_2197, all_queues_ready) connect Queue32_UInt8_30.io.enq.valid, _T_2198 node _use_this_queue_T_186 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_187 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_188 = or(_use_this_queue_T_186, _use_this_queue_T_187) node _use_this_queue_T_189 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_190 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_191 = and(_use_this_queue_T_189, _use_this_queue_T_190) node use_this_queue_31 = mux(wrapped, _use_this_queue_T_188, _use_this_queue_T_191) node _T_2199 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2200 = and(_T_2199, use_this_queue_31) node _T_2201 = and(_T_2200, all_queues_ready) connect Queue32_UInt8_31.io.enq.valid, _T_2201 when Queue32_UInt8_32.io.deq.valid : regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24 node _T_2204 = asUInt(reset) node _T_2205 = eq(_T_2204, UInt<1>(0h0)) when _T_2205 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<1>(0h0), Queue32_UInt8_32.io.deq.bits) : printf_25 when Queue32_UInt8_33.io.deq.valid : regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26 node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<1>(0h1), Queue32_UInt8_33.io.deq.bits) : printf_27 when Queue32_UInt8_34.io.deq.valid : regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28 node _T_2212 = asUInt(reset) node _T_2213 = eq(_T_2212, UInt<1>(0h0)) when _T_2213 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<2>(0h2), Queue32_UInt8_34.io.deq.bits) : printf_29 when Queue32_UInt8_35.io.deq.valid : regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_2214 = asUInt(reset) node _T_2215 = eq(_T_2214, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30 node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<2>(0h3), Queue32_UInt8_35.io.deq.bits) : printf_31 when Queue32_UInt8_36.io.deq.valid : regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_2218 = asUInt(reset) node _T_2219 = eq(_T_2218, UInt<1>(0h0)) when _T_2219 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32 node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<3>(0h4), Queue32_UInt8_36.io.deq.bits) : printf_33 when Queue32_UInt8_37.io.deq.valid : regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_2222 = asUInt(reset) node _T_2223 = eq(_T_2222, UInt<1>(0h0)) when _T_2223 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34 node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<3>(0h5), Queue32_UInt8_37.io.deq.bits) : printf_35 when Queue32_UInt8_38.io.deq.valid : regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_2226 = asUInt(reset) node _T_2227 = eq(_T_2226, UInt<1>(0h0)) when _T_2227 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36 node _T_2228 = asUInt(reset) node _T_2229 = eq(_T_2228, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<3>(0h6), Queue32_UInt8_38.io.deq.bits) : printf_37 when Queue32_UInt8_39.io.deq.valid : regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_2230 = asUInt(reset) node _T_2231 = eq(_T_2230, UInt<1>(0h0)) when _T_2231 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38 node _T_2232 = asUInt(reset) node _T_2233 = eq(_T_2232, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<3>(0h7), Queue32_UInt8_39.io.deq.bits) : printf_39 when Queue32_UInt8_40.io.deq.valid : regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_40 node _T_2236 = asUInt(reset) node _T_2237 = eq(_T_2236, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<4>(0h8), Queue32_UInt8_40.io.deq.bits) : printf_41 when Queue32_UInt8_41.io.deq.valid : regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_42 node _T_2240 = asUInt(reset) node _T_2241 = eq(_T_2240, UInt<1>(0h0)) when _T_2241 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<4>(0h9), Queue32_UInt8_41.io.deq.bits) : printf_43 when Queue32_UInt8_42.io.deq.valid : regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_44 node _T_2244 = asUInt(reset) node _T_2245 = eq(_T_2244, UInt<1>(0h0)) when _T_2245 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<4>(0ha), Queue32_UInt8_42.io.deq.bits) : printf_45 when Queue32_UInt8_43.io.deq.valid : regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_2246 = asUInt(reset) node _T_2247 = eq(_T_2246, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_46 node _T_2248 = asUInt(reset) node _T_2249 = eq(_T_2248, UInt<1>(0h0)) when _T_2249 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<4>(0hb), Queue32_UInt8_43.io.deq.bits) : printf_47 when Queue32_UInt8_44.io.deq.valid : regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_2250 = asUInt(reset) node _T_2251 = eq(_T_2250, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_48 node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<4>(0hc), Queue32_UInt8_44.io.deq.bits) : printf_49 when Queue32_UInt8_45.io.deq.valid : regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_2254 = asUInt(reset) node _T_2255 = eq(_T_2254, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_50 node _T_2256 = asUInt(reset) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) when _T_2257 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<4>(0hd), Queue32_UInt8_45.io.deq.bits) : printf_51 when Queue32_UInt8_46.io.deq.valid : regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_52 node _T_2260 = asUInt(reset) node _T_2261 = eq(_T_2260, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<4>(0he), Queue32_UInt8_46.io.deq.bits) : printf_53 when Queue32_UInt8_47.io.deq.valid : regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_2262 = asUInt(reset) node _T_2263 = eq(_T_2262, UInt<1>(0h0)) when _T_2263 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_54 node _T_2264 = asUInt(reset) node _T_2265 = eq(_T_2264, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<4>(0hf), Queue32_UInt8_47.io.deq.bits) : printf_55 when Queue32_UInt8_48.io.deq.valid : regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_2266 = asUInt(reset) node _T_2267 = eq(_T_2266, UInt<1>(0h0)) when _T_2267 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_56 node _T_2268 = asUInt(reset) node _T_2269 = eq(_T_2268, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h10), Queue32_UInt8_48.io.deq.bits) : printf_57 when Queue32_UInt8_49.io.deq.valid : regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_58 node _T_2272 = asUInt(reset) node _T_2273 = eq(_T_2272, UInt<1>(0h0)) when _T_2273 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h11), Queue32_UInt8_49.io.deq.bits) : printf_59 when Queue32_UInt8_50.io.deq.valid : regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_2274 = asUInt(reset) node _T_2275 = eq(_T_2274, UInt<1>(0h0)) when _T_2275 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_60 node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h12), Queue32_UInt8_50.io.deq.bits) : printf_61 when Queue32_UInt8_51.io.deq.valid : regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_2278 = asUInt(reset) node _T_2279 = eq(_T_2278, UInt<1>(0h0)) when _T_2279 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_62 node _T_2280 = asUInt(reset) node _T_2281 = eq(_T_2280, UInt<1>(0h0)) when _T_2281 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h13), Queue32_UInt8_51.io.deq.bits) : printf_63 when Queue32_UInt8_52.io.deq.valid : regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_2282 = asUInt(reset) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_64 node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h14), Queue32_UInt8_52.io.deq.bits) : printf_65 when Queue32_UInt8_53.io.deq.valid : regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_2286 = asUInt(reset) node _T_2287 = eq(_T_2286, UInt<1>(0h0)) when _T_2287 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_66 node _T_2288 = asUInt(reset) node _T_2289 = eq(_T_2288, UInt<1>(0h0)) when _T_2289 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h15), Queue32_UInt8_53.io.deq.bits) : printf_67 when Queue32_UInt8_54.io.deq.valid : regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_2290 = asUInt(reset) node _T_2291 = eq(_T_2290, UInt<1>(0h0)) when _T_2291 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_68 node _T_2292 = asUInt(reset) node _T_2293 = eq(_T_2292, UInt<1>(0h0)) when _T_2293 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h16), Queue32_UInt8_54.io.deq.bits) : printf_69 when Queue32_UInt8_55.io.deq.valid : regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1)) node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1) connect loginfo_cycles_35, _loginfo_cycles_T_71 node _T_2294 = asUInt(reset) node _T_2295 = eq(_T_2294, UInt<1>(0h0)) when _T_2295 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_70 node _T_2296 = asUInt(reset) node _T_2297 = eq(_T_2296, UInt<1>(0h0)) when _T_2297 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h17), Queue32_UInt8_55.io.deq.bits) : printf_71 when Queue32_UInt8_56.io.deq.valid : regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1)) node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1) connect loginfo_cycles_36, _loginfo_cycles_T_73 node _T_2298 = asUInt(reset) node _T_2299 = eq(_T_2298, UInt<1>(0h0)) when _T_2299 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_72 node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h18), Queue32_UInt8_56.io.deq.bits) : printf_73 when Queue32_UInt8_57.io.deq.valid : regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1)) node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1) connect loginfo_cycles_37, _loginfo_cycles_T_75 node _T_2302 = asUInt(reset) node _T_2303 = eq(_T_2302, UInt<1>(0h0)) when _T_2303 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_74 node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h19), Queue32_UInt8_57.io.deq.bits) : printf_75 when Queue32_UInt8_58.io.deq.valid : regreset loginfo_cycles_38 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_76 = add(loginfo_cycles_38, UInt<1>(0h1)) node _loginfo_cycles_T_77 = tail(_loginfo_cycles_T_76, 1) connect loginfo_cycles_38, _loginfo_cycles_T_77 node _T_2306 = asUInt(reset) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) when _T_2307 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_38) : printf_76 node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h1a), Queue32_UInt8_58.io.deq.bits) : printf_77 when Queue32_UInt8_59.io.deq.valid : regreset loginfo_cycles_39 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_78 = add(loginfo_cycles_39, UInt<1>(0h1)) node _loginfo_cycles_T_79 = tail(_loginfo_cycles_T_78, 1) connect loginfo_cycles_39, _loginfo_cycles_T_79 node _T_2310 = asUInt(reset) node _T_2311 = eq(_T_2310, UInt<1>(0h0)) when _T_2311 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_39) : printf_78 node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h1b), Queue32_UInt8_59.io.deq.bits) : printf_79 when Queue32_UInt8_60.io.deq.valid : regreset loginfo_cycles_40 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_80 = add(loginfo_cycles_40, UInt<1>(0h1)) node _loginfo_cycles_T_81 = tail(_loginfo_cycles_T_80, 1) connect loginfo_cycles_40, _loginfo_cycles_T_81 node _T_2314 = asUInt(reset) node _T_2315 = eq(_T_2314, UInt<1>(0h0)) when _T_2315 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_40) : printf_80 node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h1c), Queue32_UInt8_60.io.deq.bits) : printf_81 when Queue32_UInt8_61.io.deq.valid : regreset loginfo_cycles_41 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_82 = add(loginfo_cycles_41, UInt<1>(0h1)) node _loginfo_cycles_T_83 = tail(_loginfo_cycles_T_82, 1) connect loginfo_cycles_41, _loginfo_cycles_T_83 node _T_2318 = asUInt(reset) node _T_2319 = eq(_T_2318, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_41) : printf_82 node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h1d), Queue32_UInt8_61.io.deq.bits) : printf_83 when Queue32_UInt8_62.io.deq.valid : regreset loginfo_cycles_42 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_84 = add(loginfo_cycles_42, UInt<1>(0h1)) node _loginfo_cycles_T_85 = tail(_loginfo_cycles_T_84, 1) connect loginfo_cycles_42, _loginfo_cycles_T_85 node _T_2322 = asUInt(reset) node _T_2323 = eq(_T_2322, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_42) : printf_84 node _T_2324 = asUInt(reset) node _T_2325 = eq(_T_2324, UInt<1>(0h0)) when _T_2325 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h1e), Queue32_UInt8_62.io.deq.bits) : printf_85 when Queue32_UInt8_63.io.deq.valid : regreset loginfo_cycles_43 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_86 = add(loginfo_cycles_43, UInt<1>(0h1)) node _loginfo_cycles_T_87 = tail(_loginfo_cycles_T_86, 1) connect loginfo_cycles_43, _loginfo_cycles_T_87 node _T_2326 = asUInt(reset) node _T_2327 = eq(_T_2326, UInt<1>(0h0)) when _T_2327 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_43) : printf_86 node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : printf(clock, UInt<1>(0h1), "lz77 mrq2 %d, val %x\n", UInt<5>(0h1f), Queue32_UInt8_63.io.deq.bits) : printf_87 regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0) regreset len_already_consumed : UInt<64>, clock, reset, UInt<64>(0h0) wire remapVecData : UInt<8>[32] wire remapVecValids : UInt<1>[32] wire remapVecReadys : UInt<1>[32] connect remapVecData[0], UInt<1>(0h0) connect remapVecValids[0], UInt<1>(0h0) connect Queue32_UInt8_32.io.deq.ready, UInt<1>(0h0) connect remapVecData[1], UInt<1>(0h0) connect remapVecValids[1], UInt<1>(0h0) connect Queue32_UInt8_33.io.deq.ready, UInt<1>(0h0) connect remapVecData[2], UInt<1>(0h0) connect remapVecValids[2], UInt<1>(0h0) connect Queue32_UInt8_34.io.deq.ready, UInt<1>(0h0) connect remapVecData[3], UInt<1>(0h0) connect remapVecValids[3], UInt<1>(0h0) connect Queue32_UInt8_35.io.deq.ready, UInt<1>(0h0) connect remapVecData[4], UInt<1>(0h0) connect remapVecValids[4], UInt<1>(0h0) connect Queue32_UInt8_36.io.deq.ready, UInt<1>(0h0) connect remapVecData[5], UInt<1>(0h0) connect remapVecValids[5], UInt<1>(0h0) connect Queue32_UInt8_37.io.deq.ready, UInt<1>(0h0) connect remapVecData[6], UInt<1>(0h0) connect remapVecValids[6], UInt<1>(0h0) connect Queue32_UInt8_38.io.deq.ready, UInt<1>(0h0) connect remapVecData[7], UInt<1>(0h0) connect remapVecValids[7], UInt<1>(0h0) connect Queue32_UInt8_39.io.deq.ready, UInt<1>(0h0) connect remapVecData[8], UInt<1>(0h0) connect remapVecValids[8], UInt<1>(0h0) connect Queue32_UInt8_40.io.deq.ready, UInt<1>(0h0) connect remapVecData[9], UInt<1>(0h0) connect remapVecValids[9], UInt<1>(0h0) connect Queue32_UInt8_41.io.deq.ready, UInt<1>(0h0) connect remapVecData[10], UInt<1>(0h0) connect remapVecValids[10], UInt<1>(0h0) connect Queue32_UInt8_42.io.deq.ready, UInt<1>(0h0) connect remapVecData[11], UInt<1>(0h0) connect remapVecValids[11], UInt<1>(0h0) connect Queue32_UInt8_43.io.deq.ready, UInt<1>(0h0) connect remapVecData[12], UInt<1>(0h0) connect remapVecValids[12], UInt<1>(0h0) connect Queue32_UInt8_44.io.deq.ready, UInt<1>(0h0) connect remapVecData[13], UInt<1>(0h0) connect remapVecValids[13], UInt<1>(0h0) connect Queue32_UInt8_45.io.deq.ready, UInt<1>(0h0) connect remapVecData[14], UInt<1>(0h0) connect remapVecValids[14], UInt<1>(0h0) connect Queue32_UInt8_46.io.deq.ready, UInt<1>(0h0) connect remapVecData[15], UInt<1>(0h0) connect remapVecValids[15], UInt<1>(0h0) connect Queue32_UInt8_47.io.deq.ready, UInt<1>(0h0) connect remapVecData[16], UInt<1>(0h0) connect remapVecValids[16], UInt<1>(0h0) connect Queue32_UInt8_48.io.deq.ready, UInt<1>(0h0) connect remapVecData[17], UInt<1>(0h0) connect remapVecValids[17], UInt<1>(0h0) connect Queue32_UInt8_49.io.deq.ready, UInt<1>(0h0) connect remapVecData[18], UInt<1>(0h0) connect remapVecValids[18], UInt<1>(0h0) connect Queue32_UInt8_50.io.deq.ready, UInt<1>(0h0) connect remapVecData[19], UInt<1>(0h0) connect remapVecValids[19], UInt<1>(0h0) connect Queue32_UInt8_51.io.deq.ready, UInt<1>(0h0) connect remapVecData[20], UInt<1>(0h0) connect remapVecValids[20], UInt<1>(0h0) connect Queue32_UInt8_52.io.deq.ready, UInt<1>(0h0) connect remapVecData[21], UInt<1>(0h0) connect remapVecValids[21], UInt<1>(0h0) connect Queue32_UInt8_53.io.deq.ready, UInt<1>(0h0) connect remapVecData[22], UInt<1>(0h0) connect remapVecValids[22], UInt<1>(0h0) connect Queue32_UInt8_54.io.deq.ready, UInt<1>(0h0) connect remapVecData[23], UInt<1>(0h0) connect remapVecValids[23], UInt<1>(0h0) connect Queue32_UInt8_55.io.deq.ready, UInt<1>(0h0) connect remapVecData[24], UInt<1>(0h0) connect remapVecValids[24], UInt<1>(0h0) connect Queue32_UInt8_56.io.deq.ready, UInt<1>(0h0) connect remapVecData[25], UInt<1>(0h0) connect remapVecValids[25], UInt<1>(0h0) connect Queue32_UInt8_57.io.deq.ready, UInt<1>(0h0) connect remapVecData[26], UInt<1>(0h0) connect remapVecValids[26], UInt<1>(0h0) connect Queue32_UInt8_58.io.deq.ready, UInt<1>(0h0) connect remapVecData[27], UInt<1>(0h0) connect remapVecValids[27], UInt<1>(0h0) connect Queue32_UInt8_59.io.deq.ready, UInt<1>(0h0) connect remapVecData[28], UInt<1>(0h0) connect remapVecValids[28], UInt<1>(0h0) connect Queue32_UInt8_60.io.deq.ready, UInt<1>(0h0) connect remapVecData[29], UInt<1>(0h0) connect remapVecValids[29], UInt<1>(0h0) connect Queue32_UInt8_61.io.deq.ready, UInt<1>(0h0) connect remapVecData[30], UInt<1>(0h0) connect remapVecValids[30], UInt<1>(0h0) connect Queue32_UInt8_62.io.deq.ready, UInt<1>(0h0) connect remapVecData[31], UInt<1>(0h0) connect remapVecValids[31], UInt<1>(0h0) connect Queue32_UInt8_63.io.deq.ready, UInt<1>(0h0) node _remapindex_T = add(UInt<1>(0h0), read_start_index) node remapindex = rem(_remapindex_T, UInt<6>(0h20)) node _T_2330 = eq(UInt<1>(0h0), remapindex) when _T_2330 : connect remapVecData[0], Queue32_UInt8_32.io.deq.bits connect remapVecValids[0], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[0] node _T_2331 = eq(UInt<1>(0h1), remapindex) when _T_2331 : connect remapVecData[0], Queue32_UInt8_33.io.deq.bits connect remapVecValids[0], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[0] node _T_2332 = eq(UInt<2>(0h2), remapindex) when _T_2332 : connect remapVecData[0], Queue32_UInt8_34.io.deq.bits connect remapVecValids[0], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[0] node _T_2333 = eq(UInt<2>(0h3), remapindex) when _T_2333 : connect remapVecData[0], Queue32_UInt8_35.io.deq.bits connect remapVecValids[0], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[0] node _T_2334 = eq(UInt<3>(0h4), remapindex) when _T_2334 : connect remapVecData[0], Queue32_UInt8_36.io.deq.bits connect remapVecValids[0], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[0] node _T_2335 = eq(UInt<3>(0h5), remapindex) when _T_2335 : connect remapVecData[0], Queue32_UInt8_37.io.deq.bits connect remapVecValids[0], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[0] node _T_2336 = eq(UInt<3>(0h6), remapindex) when _T_2336 : connect remapVecData[0], Queue32_UInt8_38.io.deq.bits connect remapVecValids[0], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[0] node _T_2337 = eq(UInt<3>(0h7), remapindex) when _T_2337 : connect remapVecData[0], Queue32_UInt8_39.io.deq.bits connect remapVecValids[0], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[0] node _T_2338 = eq(UInt<4>(0h8), remapindex) when _T_2338 : connect remapVecData[0], Queue32_UInt8_40.io.deq.bits connect remapVecValids[0], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[0] node _T_2339 = eq(UInt<4>(0h9), remapindex) when _T_2339 : connect remapVecData[0], Queue32_UInt8_41.io.deq.bits connect remapVecValids[0], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[0] node _T_2340 = eq(UInt<4>(0ha), remapindex) when _T_2340 : connect remapVecData[0], Queue32_UInt8_42.io.deq.bits connect remapVecValids[0], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[0] node _T_2341 = eq(UInt<4>(0hb), remapindex) when _T_2341 : connect remapVecData[0], Queue32_UInt8_43.io.deq.bits connect remapVecValids[0], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[0] node _T_2342 = eq(UInt<4>(0hc), remapindex) when _T_2342 : connect remapVecData[0], Queue32_UInt8_44.io.deq.bits connect remapVecValids[0], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[0] node _T_2343 = eq(UInt<4>(0hd), remapindex) when _T_2343 : connect remapVecData[0], Queue32_UInt8_45.io.deq.bits connect remapVecValids[0], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[0] node _T_2344 = eq(UInt<4>(0he), remapindex) when _T_2344 : connect remapVecData[0], Queue32_UInt8_46.io.deq.bits connect remapVecValids[0], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[0] node _T_2345 = eq(UInt<4>(0hf), remapindex) when _T_2345 : connect remapVecData[0], Queue32_UInt8_47.io.deq.bits connect remapVecValids[0], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[0] node _T_2346 = eq(UInt<5>(0h10), remapindex) when _T_2346 : connect remapVecData[0], Queue32_UInt8_48.io.deq.bits connect remapVecValids[0], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[0] node _T_2347 = eq(UInt<5>(0h11), remapindex) when _T_2347 : connect remapVecData[0], Queue32_UInt8_49.io.deq.bits connect remapVecValids[0], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[0] node _T_2348 = eq(UInt<5>(0h12), remapindex) when _T_2348 : connect remapVecData[0], Queue32_UInt8_50.io.deq.bits connect remapVecValids[0], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[0] node _T_2349 = eq(UInt<5>(0h13), remapindex) when _T_2349 : connect remapVecData[0], Queue32_UInt8_51.io.deq.bits connect remapVecValids[0], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[0] node _T_2350 = eq(UInt<5>(0h14), remapindex) when _T_2350 : connect remapVecData[0], Queue32_UInt8_52.io.deq.bits connect remapVecValids[0], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[0] node _T_2351 = eq(UInt<5>(0h15), remapindex) when _T_2351 : connect remapVecData[0], Queue32_UInt8_53.io.deq.bits connect remapVecValids[0], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[0] node _T_2352 = eq(UInt<5>(0h16), remapindex) when _T_2352 : connect remapVecData[0], Queue32_UInt8_54.io.deq.bits connect remapVecValids[0], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[0] node _T_2353 = eq(UInt<5>(0h17), remapindex) when _T_2353 : connect remapVecData[0], Queue32_UInt8_55.io.deq.bits connect remapVecValids[0], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[0] node _T_2354 = eq(UInt<5>(0h18), remapindex) when _T_2354 : connect remapVecData[0], Queue32_UInt8_56.io.deq.bits connect remapVecValids[0], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[0] node _T_2355 = eq(UInt<5>(0h19), remapindex) when _T_2355 : connect remapVecData[0], Queue32_UInt8_57.io.deq.bits connect remapVecValids[0], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[0] node _T_2356 = eq(UInt<5>(0h1a), remapindex) when _T_2356 : connect remapVecData[0], Queue32_UInt8_58.io.deq.bits connect remapVecValids[0], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[0] node _T_2357 = eq(UInt<5>(0h1b), remapindex) when _T_2357 : connect remapVecData[0], Queue32_UInt8_59.io.deq.bits connect remapVecValids[0], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[0] node _T_2358 = eq(UInt<5>(0h1c), remapindex) when _T_2358 : connect remapVecData[0], Queue32_UInt8_60.io.deq.bits connect remapVecValids[0], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[0] node _T_2359 = eq(UInt<5>(0h1d), remapindex) when _T_2359 : connect remapVecData[0], Queue32_UInt8_61.io.deq.bits connect remapVecValids[0], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[0] node _T_2360 = eq(UInt<5>(0h1e), remapindex) when _T_2360 : connect remapVecData[0], Queue32_UInt8_62.io.deq.bits connect remapVecValids[0], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[0] node _T_2361 = eq(UInt<5>(0h1f), remapindex) when _T_2361 : connect remapVecData[0], Queue32_UInt8_63.io.deq.bits connect remapVecValids[0], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[0] node _remapindex_T_1 = add(UInt<1>(0h1), read_start_index) node remapindex_1 = rem(_remapindex_T_1, UInt<6>(0h20)) node _T_2362 = eq(UInt<1>(0h0), remapindex_1) when _T_2362 : connect remapVecData[1], Queue32_UInt8_32.io.deq.bits connect remapVecValids[1], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[1] node _T_2363 = eq(UInt<1>(0h1), remapindex_1) when _T_2363 : connect remapVecData[1], Queue32_UInt8_33.io.deq.bits connect remapVecValids[1], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[1] node _T_2364 = eq(UInt<2>(0h2), remapindex_1) when _T_2364 : connect remapVecData[1], Queue32_UInt8_34.io.deq.bits connect remapVecValids[1], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[1] node _T_2365 = eq(UInt<2>(0h3), remapindex_1) when _T_2365 : connect remapVecData[1], Queue32_UInt8_35.io.deq.bits connect remapVecValids[1], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[1] node _T_2366 = eq(UInt<3>(0h4), remapindex_1) when _T_2366 : connect remapVecData[1], Queue32_UInt8_36.io.deq.bits connect remapVecValids[1], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[1] node _T_2367 = eq(UInt<3>(0h5), remapindex_1) when _T_2367 : connect remapVecData[1], Queue32_UInt8_37.io.deq.bits connect remapVecValids[1], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[1] node _T_2368 = eq(UInt<3>(0h6), remapindex_1) when _T_2368 : connect remapVecData[1], Queue32_UInt8_38.io.deq.bits connect remapVecValids[1], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[1] node _T_2369 = eq(UInt<3>(0h7), remapindex_1) when _T_2369 : connect remapVecData[1], Queue32_UInt8_39.io.deq.bits connect remapVecValids[1], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[1] node _T_2370 = eq(UInt<4>(0h8), remapindex_1) when _T_2370 : connect remapVecData[1], Queue32_UInt8_40.io.deq.bits connect remapVecValids[1], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[1] node _T_2371 = eq(UInt<4>(0h9), remapindex_1) when _T_2371 : connect remapVecData[1], Queue32_UInt8_41.io.deq.bits connect remapVecValids[1], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[1] node _T_2372 = eq(UInt<4>(0ha), remapindex_1) when _T_2372 : connect remapVecData[1], Queue32_UInt8_42.io.deq.bits connect remapVecValids[1], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[1] node _T_2373 = eq(UInt<4>(0hb), remapindex_1) when _T_2373 : connect remapVecData[1], Queue32_UInt8_43.io.deq.bits connect remapVecValids[1], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[1] node _T_2374 = eq(UInt<4>(0hc), remapindex_1) when _T_2374 : connect remapVecData[1], Queue32_UInt8_44.io.deq.bits connect remapVecValids[1], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[1] node _T_2375 = eq(UInt<4>(0hd), remapindex_1) when _T_2375 : connect remapVecData[1], Queue32_UInt8_45.io.deq.bits connect remapVecValids[1], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[1] node _T_2376 = eq(UInt<4>(0he), remapindex_1) when _T_2376 : connect remapVecData[1], Queue32_UInt8_46.io.deq.bits connect remapVecValids[1], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[1] node _T_2377 = eq(UInt<4>(0hf), remapindex_1) when _T_2377 : connect remapVecData[1], Queue32_UInt8_47.io.deq.bits connect remapVecValids[1], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[1] node _T_2378 = eq(UInt<5>(0h10), remapindex_1) when _T_2378 : connect remapVecData[1], Queue32_UInt8_48.io.deq.bits connect remapVecValids[1], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[1] node _T_2379 = eq(UInt<5>(0h11), remapindex_1) when _T_2379 : connect remapVecData[1], Queue32_UInt8_49.io.deq.bits connect remapVecValids[1], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[1] node _T_2380 = eq(UInt<5>(0h12), remapindex_1) when _T_2380 : connect remapVecData[1], Queue32_UInt8_50.io.deq.bits connect remapVecValids[1], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[1] node _T_2381 = eq(UInt<5>(0h13), remapindex_1) when _T_2381 : connect remapVecData[1], Queue32_UInt8_51.io.deq.bits connect remapVecValids[1], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[1] node _T_2382 = eq(UInt<5>(0h14), remapindex_1) when _T_2382 : connect remapVecData[1], Queue32_UInt8_52.io.deq.bits connect remapVecValids[1], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[1] node _T_2383 = eq(UInt<5>(0h15), remapindex_1) when _T_2383 : connect remapVecData[1], Queue32_UInt8_53.io.deq.bits connect remapVecValids[1], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[1] node _T_2384 = eq(UInt<5>(0h16), remapindex_1) when _T_2384 : connect remapVecData[1], Queue32_UInt8_54.io.deq.bits connect remapVecValids[1], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[1] node _T_2385 = eq(UInt<5>(0h17), remapindex_1) when _T_2385 : connect remapVecData[1], Queue32_UInt8_55.io.deq.bits connect remapVecValids[1], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[1] node _T_2386 = eq(UInt<5>(0h18), remapindex_1) when _T_2386 : connect remapVecData[1], Queue32_UInt8_56.io.deq.bits connect remapVecValids[1], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[1] node _T_2387 = eq(UInt<5>(0h19), remapindex_1) when _T_2387 : connect remapVecData[1], Queue32_UInt8_57.io.deq.bits connect remapVecValids[1], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[1] node _T_2388 = eq(UInt<5>(0h1a), remapindex_1) when _T_2388 : connect remapVecData[1], Queue32_UInt8_58.io.deq.bits connect remapVecValids[1], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[1] node _T_2389 = eq(UInt<5>(0h1b), remapindex_1) when _T_2389 : connect remapVecData[1], Queue32_UInt8_59.io.deq.bits connect remapVecValids[1], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[1] node _T_2390 = eq(UInt<5>(0h1c), remapindex_1) when _T_2390 : connect remapVecData[1], Queue32_UInt8_60.io.deq.bits connect remapVecValids[1], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[1] node _T_2391 = eq(UInt<5>(0h1d), remapindex_1) when _T_2391 : connect remapVecData[1], Queue32_UInt8_61.io.deq.bits connect remapVecValids[1], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[1] node _T_2392 = eq(UInt<5>(0h1e), remapindex_1) when _T_2392 : connect remapVecData[1], Queue32_UInt8_62.io.deq.bits connect remapVecValids[1], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[1] node _T_2393 = eq(UInt<5>(0h1f), remapindex_1) when _T_2393 : connect remapVecData[1], Queue32_UInt8_63.io.deq.bits connect remapVecValids[1], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[1] node _remapindex_T_2 = add(UInt<2>(0h2), read_start_index) node remapindex_2 = rem(_remapindex_T_2, UInt<6>(0h20)) node _T_2394 = eq(UInt<1>(0h0), remapindex_2) when _T_2394 : connect remapVecData[2], Queue32_UInt8_32.io.deq.bits connect remapVecValids[2], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[2] node _T_2395 = eq(UInt<1>(0h1), remapindex_2) when _T_2395 : connect remapVecData[2], Queue32_UInt8_33.io.deq.bits connect remapVecValids[2], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[2] node _T_2396 = eq(UInt<2>(0h2), remapindex_2) when _T_2396 : connect remapVecData[2], Queue32_UInt8_34.io.deq.bits connect remapVecValids[2], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[2] node _T_2397 = eq(UInt<2>(0h3), remapindex_2) when _T_2397 : connect remapVecData[2], Queue32_UInt8_35.io.deq.bits connect remapVecValids[2], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[2] node _T_2398 = eq(UInt<3>(0h4), remapindex_2) when _T_2398 : connect remapVecData[2], Queue32_UInt8_36.io.deq.bits connect remapVecValids[2], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[2] node _T_2399 = eq(UInt<3>(0h5), remapindex_2) when _T_2399 : connect remapVecData[2], Queue32_UInt8_37.io.deq.bits connect remapVecValids[2], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[2] node _T_2400 = eq(UInt<3>(0h6), remapindex_2) when _T_2400 : connect remapVecData[2], Queue32_UInt8_38.io.deq.bits connect remapVecValids[2], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[2] node _T_2401 = eq(UInt<3>(0h7), remapindex_2) when _T_2401 : connect remapVecData[2], Queue32_UInt8_39.io.deq.bits connect remapVecValids[2], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[2] node _T_2402 = eq(UInt<4>(0h8), remapindex_2) when _T_2402 : connect remapVecData[2], Queue32_UInt8_40.io.deq.bits connect remapVecValids[2], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[2] node _T_2403 = eq(UInt<4>(0h9), remapindex_2) when _T_2403 : connect remapVecData[2], Queue32_UInt8_41.io.deq.bits connect remapVecValids[2], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[2] node _T_2404 = eq(UInt<4>(0ha), remapindex_2) when _T_2404 : connect remapVecData[2], Queue32_UInt8_42.io.deq.bits connect remapVecValids[2], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[2] node _T_2405 = eq(UInt<4>(0hb), remapindex_2) when _T_2405 : connect remapVecData[2], Queue32_UInt8_43.io.deq.bits connect remapVecValids[2], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[2] node _T_2406 = eq(UInt<4>(0hc), remapindex_2) when _T_2406 : connect remapVecData[2], Queue32_UInt8_44.io.deq.bits connect remapVecValids[2], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[2] node _T_2407 = eq(UInt<4>(0hd), remapindex_2) when _T_2407 : connect remapVecData[2], Queue32_UInt8_45.io.deq.bits connect remapVecValids[2], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[2] node _T_2408 = eq(UInt<4>(0he), remapindex_2) when _T_2408 : connect remapVecData[2], Queue32_UInt8_46.io.deq.bits connect remapVecValids[2], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[2] node _T_2409 = eq(UInt<4>(0hf), remapindex_2) when _T_2409 : connect remapVecData[2], Queue32_UInt8_47.io.deq.bits connect remapVecValids[2], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[2] node _T_2410 = eq(UInt<5>(0h10), remapindex_2) when _T_2410 : connect remapVecData[2], Queue32_UInt8_48.io.deq.bits connect remapVecValids[2], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[2] node _T_2411 = eq(UInt<5>(0h11), remapindex_2) when _T_2411 : connect remapVecData[2], Queue32_UInt8_49.io.deq.bits connect remapVecValids[2], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[2] node _T_2412 = eq(UInt<5>(0h12), remapindex_2) when _T_2412 : connect remapVecData[2], Queue32_UInt8_50.io.deq.bits connect remapVecValids[2], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[2] node _T_2413 = eq(UInt<5>(0h13), remapindex_2) when _T_2413 : connect remapVecData[2], Queue32_UInt8_51.io.deq.bits connect remapVecValids[2], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[2] node _T_2414 = eq(UInt<5>(0h14), remapindex_2) when _T_2414 : connect remapVecData[2], Queue32_UInt8_52.io.deq.bits connect remapVecValids[2], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[2] node _T_2415 = eq(UInt<5>(0h15), remapindex_2) when _T_2415 : connect remapVecData[2], Queue32_UInt8_53.io.deq.bits connect remapVecValids[2], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[2] node _T_2416 = eq(UInt<5>(0h16), remapindex_2) when _T_2416 : connect remapVecData[2], Queue32_UInt8_54.io.deq.bits connect remapVecValids[2], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[2] node _T_2417 = eq(UInt<5>(0h17), remapindex_2) when _T_2417 : connect remapVecData[2], Queue32_UInt8_55.io.deq.bits connect remapVecValids[2], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[2] node _T_2418 = eq(UInt<5>(0h18), remapindex_2) when _T_2418 : connect remapVecData[2], Queue32_UInt8_56.io.deq.bits connect remapVecValids[2], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[2] node _T_2419 = eq(UInt<5>(0h19), remapindex_2) when _T_2419 : connect remapVecData[2], Queue32_UInt8_57.io.deq.bits connect remapVecValids[2], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[2] node _T_2420 = eq(UInt<5>(0h1a), remapindex_2) when _T_2420 : connect remapVecData[2], Queue32_UInt8_58.io.deq.bits connect remapVecValids[2], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[2] node _T_2421 = eq(UInt<5>(0h1b), remapindex_2) when _T_2421 : connect remapVecData[2], Queue32_UInt8_59.io.deq.bits connect remapVecValids[2], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[2] node _T_2422 = eq(UInt<5>(0h1c), remapindex_2) when _T_2422 : connect remapVecData[2], Queue32_UInt8_60.io.deq.bits connect remapVecValids[2], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[2] node _T_2423 = eq(UInt<5>(0h1d), remapindex_2) when _T_2423 : connect remapVecData[2], Queue32_UInt8_61.io.deq.bits connect remapVecValids[2], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[2] node _T_2424 = eq(UInt<5>(0h1e), remapindex_2) when _T_2424 : connect remapVecData[2], Queue32_UInt8_62.io.deq.bits connect remapVecValids[2], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[2] node _T_2425 = eq(UInt<5>(0h1f), remapindex_2) when _T_2425 : connect remapVecData[2], Queue32_UInt8_63.io.deq.bits connect remapVecValids[2], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[2] node _remapindex_T_3 = add(UInt<2>(0h3), read_start_index) node remapindex_3 = rem(_remapindex_T_3, UInt<6>(0h20)) node _T_2426 = eq(UInt<1>(0h0), remapindex_3) when _T_2426 : connect remapVecData[3], Queue32_UInt8_32.io.deq.bits connect remapVecValids[3], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[3] node _T_2427 = eq(UInt<1>(0h1), remapindex_3) when _T_2427 : connect remapVecData[3], Queue32_UInt8_33.io.deq.bits connect remapVecValids[3], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[3] node _T_2428 = eq(UInt<2>(0h2), remapindex_3) when _T_2428 : connect remapVecData[3], Queue32_UInt8_34.io.deq.bits connect remapVecValids[3], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[3] node _T_2429 = eq(UInt<2>(0h3), remapindex_3) when _T_2429 : connect remapVecData[3], Queue32_UInt8_35.io.deq.bits connect remapVecValids[3], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[3] node _T_2430 = eq(UInt<3>(0h4), remapindex_3) when _T_2430 : connect remapVecData[3], Queue32_UInt8_36.io.deq.bits connect remapVecValids[3], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[3] node _T_2431 = eq(UInt<3>(0h5), remapindex_3) when _T_2431 : connect remapVecData[3], Queue32_UInt8_37.io.deq.bits connect remapVecValids[3], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[3] node _T_2432 = eq(UInt<3>(0h6), remapindex_3) when _T_2432 : connect remapVecData[3], Queue32_UInt8_38.io.deq.bits connect remapVecValids[3], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[3] node _T_2433 = eq(UInt<3>(0h7), remapindex_3) when _T_2433 : connect remapVecData[3], Queue32_UInt8_39.io.deq.bits connect remapVecValids[3], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[3] node _T_2434 = eq(UInt<4>(0h8), remapindex_3) when _T_2434 : connect remapVecData[3], Queue32_UInt8_40.io.deq.bits connect remapVecValids[3], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[3] node _T_2435 = eq(UInt<4>(0h9), remapindex_3) when _T_2435 : connect remapVecData[3], Queue32_UInt8_41.io.deq.bits connect remapVecValids[3], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[3] node _T_2436 = eq(UInt<4>(0ha), remapindex_3) when _T_2436 : connect remapVecData[3], Queue32_UInt8_42.io.deq.bits connect remapVecValids[3], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[3] node _T_2437 = eq(UInt<4>(0hb), remapindex_3) when _T_2437 : connect remapVecData[3], Queue32_UInt8_43.io.deq.bits connect remapVecValids[3], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[3] node _T_2438 = eq(UInt<4>(0hc), remapindex_3) when _T_2438 : connect remapVecData[3], Queue32_UInt8_44.io.deq.bits connect remapVecValids[3], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[3] node _T_2439 = eq(UInt<4>(0hd), remapindex_3) when _T_2439 : connect remapVecData[3], Queue32_UInt8_45.io.deq.bits connect remapVecValids[3], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[3] node _T_2440 = eq(UInt<4>(0he), remapindex_3) when _T_2440 : connect remapVecData[3], Queue32_UInt8_46.io.deq.bits connect remapVecValids[3], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[3] node _T_2441 = eq(UInt<4>(0hf), remapindex_3) when _T_2441 : connect remapVecData[3], Queue32_UInt8_47.io.deq.bits connect remapVecValids[3], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[3] node _T_2442 = eq(UInt<5>(0h10), remapindex_3) when _T_2442 : connect remapVecData[3], Queue32_UInt8_48.io.deq.bits connect remapVecValids[3], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[3] node _T_2443 = eq(UInt<5>(0h11), remapindex_3) when _T_2443 : connect remapVecData[3], Queue32_UInt8_49.io.deq.bits connect remapVecValids[3], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[3] node _T_2444 = eq(UInt<5>(0h12), remapindex_3) when _T_2444 : connect remapVecData[3], Queue32_UInt8_50.io.deq.bits connect remapVecValids[3], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[3] node _T_2445 = eq(UInt<5>(0h13), remapindex_3) when _T_2445 : connect remapVecData[3], Queue32_UInt8_51.io.deq.bits connect remapVecValids[3], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[3] node _T_2446 = eq(UInt<5>(0h14), remapindex_3) when _T_2446 : connect remapVecData[3], Queue32_UInt8_52.io.deq.bits connect remapVecValids[3], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[3] node _T_2447 = eq(UInt<5>(0h15), remapindex_3) when _T_2447 : connect remapVecData[3], Queue32_UInt8_53.io.deq.bits connect remapVecValids[3], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[3] node _T_2448 = eq(UInt<5>(0h16), remapindex_3) when _T_2448 : connect remapVecData[3], Queue32_UInt8_54.io.deq.bits connect remapVecValids[3], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[3] node _T_2449 = eq(UInt<5>(0h17), remapindex_3) when _T_2449 : connect remapVecData[3], Queue32_UInt8_55.io.deq.bits connect remapVecValids[3], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[3] node _T_2450 = eq(UInt<5>(0h18), remapindex_3) when _T_2450 : connect remapVecData[3], Queue32_UInt8_56.io.deq.bits connect remapVecValids[3], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[3] node _T_2451 = eq(UInt<5>(0h19), remapindex_3) when _T_2451 : connect remapVecData[3], Queue32_UInt8_57.io.deq.bits connect remapVecValids[3], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[3] node _T_2452 = eq(UInt<5>(0h1a), remapindex_3) when _T_2452 : connect remapVecData[3], Queue32_UInt8_58.io.deq.bits connect remapVecValids[3], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[3] node _T_2453 = eq(UInt<5>(0h1b), remapindex_3) when _T_2453 : connect remapVecData[3], Queue32_UInt8_59.io.deq.bits connect remapVecValids[3], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[3] node _T_2454 = eq(UInt<5>(0h1c), remapindex_3) when _T_2454 : connect remapVecData[3], Queue32_UInt8_60.io.deq.bits connect remapVecValids[3], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[3] node _T_2455 = eq(UInt<5>(0h1d), remapindex_3) when _T_2455 : connect remapVecData[3], Queue32_UInt8_61.io.deq.bits connect remapVecValids[3], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[3] node _T_2456 = eq(UInt<5>(0h1e), remapindex_3) when _T_2456 : connect remapVecData[3], Queue32_UInt8_62.io.deq.bits connect remapVecValids[3], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[3] node _T_2457 = eq(UInt<5>(0h1f), remapindex_3) when _T_2457 : connect remapVecData[3], Queue32_UInt8_63.io.deq.bits connect remapVecValids[3], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[3] node _remapindex_T_4 = add(UInt<3>(0h4), read_start_index) node remapindex_4 = rem(_remapindex_T_4, UInt<6>(0h20)) node _T_2458 = eq(UInt<1>(0h0), remapindex_4) when _T_2458 : connect remapVecData[4], Queue32_UInt8_32.io.deq.bits connect remapVecValids[4], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[4] node _T_2459 = eq(UInt<1>(0h1), remapindex_4) when _T_2459 : connect remapVecData[4], Queue32_UInt8_33.io.deq.bits connect remapVecValids[4], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[4] node _T_2460 = eq(UInt<2>(0h2), remapindex_4) when _T_2460 : connect remapVecData[4], Queue32_UInt8_34.io.deq.bits connect remapVecValids[4], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[4] node _T_2461 = eq(UInt<2>(0h3), remapindex_4) when _T_2461 : connect remapVecData[4], Queue32_UInt8_35.io.deq.bits connect remapVecValids[4], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[4] node _T_2462 = eq(UInt<3>(0h4), remapindex_4) when _T_2462 : connect remapVecData[4], Queue32_UInt8_36.io.deq.bits connect remapVecValids[4], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[4] node _T_2463 = eq(UInt<3>(0h5), remapindex_4) when _T_2463 : connect remapVecData[4], Queue32_UInt8_37.io.deq.bits connect remapVecValids[4], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[4] node _T_2464 = eq(UInt<3>(0h6), remapindex_4) when _T_2464 : connect remapVecData[4], Queue32_UInt8_38.io.deq.bits connect remapVecValids[4], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[4] node _T_2465 = eq(UInt<3>(0h7), remapindex_4) when _T_2465 : connect remapVecData[4], Queue32_UInt8_39.io.deq.bits connect remapVecValids[4], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[4] node _T_2466 = eq(UInt<4>(0h8), remapindex_4) when _T_2466 : connect remapVecData[4], Queue32_UInt8_40.io.deq.bits connect remapVecValids[4], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[4] node _T_2467 = eq(UInt<4>(0h9), remapindex_4) when _T_2467 : connect remapVecData[4], Queue32_UInt8_41.io.deq.bits connect remapVecValids[4], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[4] node _T_2468 = eq(UInt<4>(0ha), remapindex_4) when _T_2468 : connect remapVecData[4], Queue32_UInt8_42.io.deq.bits connect remapVecValids[4], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[4] node _T_2469 = eq(UInt<4>(0hb), remapindex_4) when _T_2469 : connect remapVecData[4], Queue32_UInt8_43.io.deq.bits connect remapVecValids[4], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[4] node _T_2470 = eq(UInt<4>(0hc), remapindex_4) when _T_2470 : connect remapVecData[4], Queue32_UInt8_44.io.deq.bits connect remapVecValids[4], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[4] node _T_2471 = eq(UInt<4>(0hd), remapindex_4) when _T_2471 : connect remapVecData[4], Queue32_UInt8_45.io.deq.bits connect remapVecValids[4], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[4] node _T_2472 = eq(UInt<4>(0he), remapindex_4) when _T_2472 : connect remapVecData[4], Queue32_UInt8_46.io.deq.bits connect remapVecValids[4], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[4] node _T_2473 = eq(UInt<4>(0hf), remapindex_4) when _T_2473 : connect remapVecData[4], Queue32_UInt8_47.io.deq.bits connect remapVecValids[4], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[4] node _T_2474 = eq(UInt<5>(0h10), remapindex_4) when _T_2474 : connect remapVecData[4], Queue32_UInt8_48.io.deq.bits connect remapVecValids[4], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[4] node _T_2475 = eq(UInt<5>(0h11), remapindex_4) when _T_2475 : connect remapVecData[4], Queue32_UInt8_49.io.deq.bits connect remapVecValids[4], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[4] node _T_2476 = eq(UInt<5>(0h12), remapindex_4) when _T_2476 : connect remapVecData[4], Queue32_UInt8_50.io.deq.bits connect remapVecValids[4], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[4] node _T_2477 = eq(UInt<5>(0h13), remapindex_4) when _T_2477 : connect remapVecData[4], Queue32_UInt8_51.io.deq.bits connect remapVecValids[4], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[4] node _T_2478 = eq(UInt<5>(0h14), remapindex_4) when _T_2478 : connect remapVecData[4], Queue32_UInt8_52.io.deq.bits connect remapVecValids[4], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[4] node _T_2479 = eq(UInt<5>(0h15), remapindex_4) when _T_2479 : connect remapVecData[4], Queue32_UInt8_53.io.deq.bits connect remapVecValids[4], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[4] node _T_2480 = eq(UInt<5>(0h16), remapindex_4) when _T_2480 : connect remapVecData[4], Queue32_UInt8_54.io.deq.bits connect remapVecValids[4], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[4] node _T_2481 = eq(UInt<5>(0h17), remapindex_4) when _T_2481 : connect remapVecData[4], Queue32_UInt8_55.io.deq.bits connect remapVecValids[4], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[4] node _T_2482 = eq(UInt<5>(0h18), remapindex_4) when _T_2482 : connect remapVecData[4], Queue32_UInt8_56.io.deq.bits connect remapVecValids[4], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[4] node _T_2483 = eq(UInt<5>(0h19), remapindex_4) when _T_2483 : connect remapVecData[4], Queue32_UInt8_57.io.deq.bits connect remapVecValids[4], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[4] node _T_2484 = eq(UInt<5>(0h1a), remapindex_4) when _T_2484 : connect remapVecData[4], Queue32_UInt8_58.io.deq.bits connect remapVecValids[4], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[4] node _T_2485 = eq(UInt<5>(0h1b), remapindex_4) when _T_2485 : connect remapVecData[4], Queue32_UInt8_59.io.deq.bits connect remapVecValids[4], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[4] node _T_2486 = eq(UInt<5>(0h1c), remapindex_4) when _T_2486 : connect remapVecData[4], Queue32_UInt8_60.io.deq.bits connect remapVecValids[4], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[4] node _T_2487 = eq(UInt<5>(0h1d), remapindex_4) when _T_2487 : connect remapVecData[4], Queue32_UInt8_61.io.deq.bits connect remapVecValids[4], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[4] node _T_2488 = eq(UInt<5>(0h1e), remapindex_4) when _T_2488 : connect remapVecData[4], Queue32_UInt8_62.io.deq.bits connect remapVecValids[4], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[4] node _T_2489 = eq(UInt<5>(0h1f), remapindex_4) when _T_2489 : connect remapVecData[4], Queue32_UInt8_63.io.deq.bits connect remapVecValids[4], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[4] node _remapindex_T_5 = add(UInt<3>(0h5), read_start_index) node remapindex_5 = rem(_remapindex_T_5, UInt<6>(0h20)) node _T_2490 = eq(UInt<1>(0h0), remapindex_5) when _T_2490 : connect remapVecData[5], Queue32_UInt8_32.io.deq.bits connect remapVecValids[5], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[5] node _T_2491 = eq(UInt<1>(0h1), remapindex_5) when _T_2491 : connect remapVecData[5], Queue32_UInt8_33.io.deq.bits connect remapVecValids[5], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[5] node _T_2492 = eq(UInt<2>(0h2), remapindex_5) when _T_2492 : connect remapVecData[5], Queue32_UInt8_34.io.deq.bits connect remapVecValids[5], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[5] node _T_2493 = eq(UInt<2>(0h3), remapindex_5) when _T_2493 : connect remapVecData[5], Queue32_UInt8_35.io.deq.bits connect remapVecValids[5], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[5] node _T_2494 = eq(UInt<3>(0h4), remapindex_5) when _T_2494 : connect remapVecData[5], Queue32_UInt8_36.io.deq.bits connect remapVecValids[5], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[5] node _T_2495 = eq(UInt<3>(0h5), remapindex_5) when _T_2495 : connect remapVecData[5], Queue32_UInt8_37.io.deq.bits connect remapVecValids[5], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[5] node _T_2496 = eq(UInt<3>(0h6), remapindex_5) when _T_2496 : connect remapVecData[5], Queue32_UInt8_38.io.deq.bits connect remapVecValids[5], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[5] node _T_2497 = eq(UInt<3>(0h7), remapindex_5) when _T_2497 : connect remapVecData[5], Queue32_UInt8_39.io.deq.bits connect remapVecValids[5], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[5] node _T_2498 = eq(UInt<4>(0h8), remapindex_5) when _T_2498 : connect remapVecData[5], Queue32_UInt8_40.io.deq.bits connect remapVecValids[5], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[5] node _T_2499 = eq(UInt<4>(0h9), remapindex_5) when _T_2499 : connect remapVecData[5], Queue32_UInt8_41.io.deq.bits connect remapVecValids[5], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[5] node _T_2500 = eq(UInt<4>(0ha), remapindex_5) when _T_2500 : connect remapVecData[5], Queue32_UInt8_42.io.deq.bits connect remapVecValids[5], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[5] node _T_2501 = eq(UInt<4>(0hb), remapindex_5) when _T_2501 : connect remapVecData[5], Queue32_UInt8_43.io.deq.bits connect remapVecValids[5], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[5] node _T_2502 = eq(UInt<4>(0hc), remapindex_5) when _T_2502 : connect remapVecData[5], Queue32_UInt8_44.io.deq.bits connect remapVecValids[5], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[5] node _T_2503 = eq(UInt<4>(0hd), remapindex_5) when _T_2503 : connect remapVecData[5], Queue32_UInt8_45.io.deq.bits connect remapVecValids[5], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[5] node _T_2504 = eq(UInt<4>(0he), remapindex_5) when _T_2504 : connect remapVecData[5], Queue32_UInt8_46.io.deq.bits connect remapVecValids[5], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[5] node _T_2505 = eq(UInt<4>(0hf), remapindex_5) when _T_2505 : connect remapVecData[5], Queue32_UInt8_47.io.deq.bits connect remapVecValids[5], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[5] node _T_2506 = eq(UInt<5>(0h10), remapindex_5) when _T_2506 : connect remapVecData[5], Queue32_UInt8_48.io.deq.bits connect remapVecValids[5], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[5] node _T_2507 = eq(UInt<5>(0h11), remapindex_5) when _T_2507 : connect remapVecData[5], Queue32_UInt8_49.io.deq.bits connect remapVecValids[5], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[5] node _T_2508 = eq(UInt<5>(0h12), remapindex_5) when _T_2508 : connect remapVecData[5], Queue32_UInt8_50.io.deq.bits connect remapVecValids[5], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[5] node _T_2509 = eq(UInt<5>(0h13), remapindex_5) when _T_2509 : connect remapVecData[5], Queue32_UInt8_51.io.deq.bits connect remapVecValids[5], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[5] node _T_2510 = eq(UInt<5>(0h14), remapindex_5) when _T_2510 : connect remapVecData[5], Queue32_UInt8_52.io.deq.bits connect remapVecValids[5], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[5] node _T_2511 = eq(UInt<5>(0h15), remapindex_5) when _T_2511 : connect remapVecData[5], Queue32_UInt8_53.io.deq.bits connect remapVecValids[5], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[5] node _T_2512 = eq(UInt<5>(0h16), remapindex_5) when _T_2512 : connect remapVecData[5], Queue32_UInt8_54.io.deq.bits connect remapVecValids[5], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[5] node _T_2513 = eq(UInt<5>(0h17), remapindex_5) when _T_2513 : connect remapVecData[5], Queue32_UInt8_55.io.deq.bits connect remapVecValids[5], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[5] node _T_2514 = eq(UInt<5>(0h18), remapindex_5) when _T_2514 : connect remapVecData[5], Queue32_UInt8_56.io.deq.bits connect remapVecValids[5], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[5] node _T_2515 = eq(UInt<5>(0h19), remapindex_5) when _T_2515 : connect remapVecData[5], Queue32_UInt8_57.io.deq.bits connect remapVecValids[5], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[5] node _T_2516 = eq(UInt<5>(0h1a), remapindex_5) when _T_2516 : connect remapVecData[5], Queue32_UInt8_58.io.deq.bits connect remapVecValids[5], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[5] node _T_2517 = eq(UInt<5>(0h1b), remapindex_5) when _T_2517 : connect remapVecData[5], Queue32_UInt8_59.io.deq.bits connect remapVecValids[5], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[5] node _T_2518 = eq(UInt<5>(0h1c), remapindex_5) when _T_2518 : connect remapVecData[5], Queue32_UInt8_60.io.deq.bits connect remapVecValids[5], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[5] node _T_2519 = eq(UInt<5>(0h1d), remapindex_5) when _T_2519 : connect remapVecData[5], Queue32_UInt8_61.io.deq.bits connect remapVecValids[5], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[5] node _T_2520 = eq(UInt<5>(0h1e), remapindex_5) when _T_2520 : connect remapVecData[5], Queue32_UInt8_62.io.deq.bits connect remapVecValids[5], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[5] node _T_2521 = eq(UInt<5>(0h1f), remapindex_5) when _T_2521 : connect remapVecData[5], Queue32_UInt8_63.io.deq.bits connect remapVecValids[5], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[5] node _remapindex_T_6 = add(UInt<3>(0h6), read_start_index) node remapindex_6 = rem(_remapindex_T_6, UInt<6>(0h20)) node _T_2522 = eq(UInt<1>(0h0), remapindex_6) when _T_2522 : connect remapVecData[6], Queue32_UInt8_32.io.deq.bits connect remapVecValids[6], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[6] node _T_2523 = eq(UInt<1>(0h1), remapindex_6) when _T_2523 : connect remapVecData[6], Queue32_UInt8_33.io.deq.bits connect remapVecValids[6], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[6] node _T_2524 = eq(UInt<2>(0h2), remapindex_6) when _T_2524 : connect remapVecData[6], Queue32_UInt8_34.io.deq.bits connect remapVecValids[6], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[6] node _T_2525 = eq(UInt<2>(0h3), remapindex_6) when _T_2525 : connect remapVecData[6], Queue32_UInt8_35.io.deq.bits connect remapVecValids[6], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[6] node _T_2526 = eq(UInt<3>(0h4), remapindex_6) when _T_2526 : connect remapVecData[6], Queue32_UInt8_36.io.deq.bits connect remapVecValids[6], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[6] node _T_2527 = eq(UInt<3>(0h5), remapindex_6) when _T_2527 : connect remapVecData[6], Queue32_UInt8_37.io.deq.bits connect remapVecValids[6], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[6] node _T_2528 = eq(UInt<3>(0h6), remapindex_6) when _T_2528 : connect remapVecData[6], Queue32_UInt8_38.io.deq.bits connect remapVecValids[6], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[6] node _T_2529 = eq(UInt<3>(0h7), remapindex_6) when _T_2529 : connect remapVecData[6], Queue32_UInt8_39.io.deq.bits connect remapVecValids[6], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[6] node _T_2530 = eq(UInt<4>(0h8), remapindex_6) when _T_2530 : connect remapVecData[6], Queue32_UInt8_40.io.deq.bits connect remapVecValids[6], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[6] node _T_2531 = eq(UInt<4>(0h9), remapindex_6) when _T_2531 : connect remapVecData[6], Queue32_UInt8_41.io.deq.bits connect remapVecValids[6], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[6] node _T_2532 = eq(UInt<4>(0ha), remapindex_6) when _T_2532 : connect remapVecData[6], Queue32_UInt8_42.io.deq.bits connect remapVecValids[6], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[6] node _T_2533 = eq(UInt<4>(0hb), remapindex_6) when _T_2533 : connect remapVecData[6], Queue32_UInt8_43.io.deq.bits connect remapVecValids[6], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[6] node _T_2534 = eq(UInt<4>(0hc), remapindex_6) when _T_2534 : connect remapVecData[6], Queue32_UInt8_44.io.deq.bits connect remapVecValids[6], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[6] node _T_2535 = eq(UInt<4>(0hd), remapindex_6) when _T_2535 : connect remapVecData[6], Queue32_UInt8_45.io.deq.bits connect remapVecValids[6], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[6] node _T_2536 = eq(UInt<4>(0he), remapindex_6) when _T_2536 : connect remapVecData[6], Queue32_UInt8_46.io.deq.bits connect remapVecValids[6], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[6] node _T_2537 = eq(UInt<4>(0hf), remapindex_6) when _T_2537 : connect remapVecData[6], Queue32_UInt8_47.io.deq.bits connect remapVecValids[6], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[6] node _T_2538 = eq(UInt<5>(0h10), remapindex_6) when _T_2538 : connect remapVecData[6], Queue32_UInt8_48.io.deq.bits connect remapVecValids[6], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[6] node _T_2539 = eq(UInt<5>(0h11), remapindex_6) when _T_2539 : connect remapVecData[6], Queue32_UInt8_49.io.deq.bits connect remapVecValids[6], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[6] node _T_2540 = eq(UInt<5>(0h12), remapindex_6) when _T_2540 : connect remapVecData[6], Queue32_UInt8_50.io.deq.bits connect remapVecValids[6], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[6] node _T_2541 = eq(UInt<5>(0h13), remapindex_6) when _T_2541 : connect remapVecData[6], Queue32_UInt8_51.io.deq.bits connect remapVecValids[6], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[6] node _T_2542 = eq(UInt<5>(0h14), remapindex_6) when _T_2542 : connect remapVecData[6], Queue32_UInt8_52.io.deq.bits connect remapVecValids[6], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[6] node _T_2543 = eq(UInt<5>(0h15), remapindex_6) when _T_2543 : connect remapVecData[6], Queue32_UInt8_53.io.deq.bits connect remapVecValids[6], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[6] node _T_2544 = eq(UInt<5>(0h16), remapindex_6) when _T_2544 : connect remapVecData[6], Queue32_UInt8_54.io.deq.bits connect remapVecValids[6], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[6] node _T_2545 = eq(UInt<5>(0h17), remapindex_6) when _T_2545 : connect remapVecData[6], Queue32_UInt8_55.io.deq.bits connect remapVecValids[6], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[6] node _T_2546 = eq(UInt<5>(0h18), remapindex_6) when _T_2546 : connect remapVecData[6], Queue32_UInt8_56.io.deq.bits connect remapVecValids[6], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[6] node _T_2547 = eq(UInt<5>(0h19), remapindex_6) when _T_2547 : connect remapVecData[6], Queue32_UInt8_57.io.deq.bits connect remapVecValids[6], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[6] node _T_2548 = eq(UInt<5>(0h1a), remapindex_6) when _T_2548 : connect remapVecData[6], Queue32_UInt8_58.io.deq.bits connect remapVecValids[6], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[6] node _T_2549 = eq(UInt<5>(0h1b), remapindex_6) when _T_2549 : connect remapVecData[6], Queue32_UInt8_59.io.deq.bits connect remapVecValids[6], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[6] node _T_2550 = eq(UInt<5>(0h1c), remapindex_6) when _T_2550 : connect remapVecData[6], Queue32_UInt8_60.io.deq.bits connect remapVecValids[6], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[6] node _T_2551 = eq(UInt<5>(0h1d), remapindex_6) when _T_2551 : connect remapVecData[6], Queue32_UInt8_61.io.deq.bits connect remapVecValids[6], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[6] node _T_2552 = eq(UInt<5>(0h1e), remapindex_6) when _T_2552 : connect remapVecData[6], Queue32_UInt8_62.io.deq.bits connect remapVecValids[6], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[6] node _T_2553 = eq(UInt<5>(0h1f), remapindex_6) when _T_2553 : connect remapVecData[6], Queue32_UInt8_63.io.deq.bits connect remapVecValids[6], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[6] node _remapindex_T_7 = add(UInt<3>(0h7), read_start_index) node remapindex_7 = rem(_remapindex_T_7, UInt<6>(0h20)) node _T_2554 = eq(UInt<1>(0h0), remapindex_7) when _T_2554 : connect remapVecData[7], Queue32_UInt8_32.io.deq.bits connect remapVecValids[7], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[7] node _T_2555 = eq(UInt<1>(0h1), remapindex_7) when _T_2555 : connect remapVecData[7], Queue32_UInt8_33.io.deq.bits connect remapVecValids[7], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[7] node _T_2556 = eq(UInt<2>(0h2), remapindex_7) when _T_2556 : connect remapVecData[7], Queue32_UInt8_34.io.deq.bits connect remapVecValids[7], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[7] node _T_2557 = eq(UInt<2>(0h3), remapindex_7) when _T_2557 : connect remapVecData[7], Queue32_UInt8_35.io.deq.bits connect remapVecValids[7], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[7] node _T_2558 = eq(UInt<3>(0h4), remapindex_7) when _T_2558 : connect remapVecData[7], Queue32_UInt8_36.io.deq.bits connect remapVecValids[7], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[7] node _T_2559 = eq(UInt<3>(0h5), remapindex_7) when _T_2559 : connect remapVecData[7], Queue32_UInt8_37.io.deq.bits connect remapVecValids[7], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[7] node _T_2560 = eq(UInt<3>(0h6), remapindex_7) when _T_2560 : connect remapVecData[7], Queue32_UInt8_38.io.deq.bits connect remapVecValids[7], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[7] node _T_2561 = eq(UInt<3>(0h7), remapindex_7) when _T_2561 : connect remapVecData[7], Queue32_UInt8_39.io.deq.bits connect remapVecValids[7], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[7] node _T_2562 = eq(UInt<4>(0h8), remapindex_7) when _T_2562 : connect remapVecData[7], Queue32_UInt8_40.io.deq.bits connect remapVecValids[7], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[7] node _T_2563 = eq(UInt<4>(0h9), remapindex_7) when _T_2563 : connect remapVecData[7], Queue32_UInt8_41.io.deq.bits connect remapVecValids[7], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[7] node _T_2564 = eq(UInt<4>(0ha), remapindex_7) when _T_2564 : connect remapVecData[7], Queue32_UInt8_42.io.deq.bits connect remapVecValids[7], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[7] node _T_2565 = eq(UInt<4>(0hb), remapindex_7) when _T_2565 : connect remapVecData[7], Queue32_UInt8_43.io.deq.bits connect remapVecValids[7], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[7] node _T_2566 = eq(UInt<4>(0hc), remapindex_7) when _T_2566 : connect remapVecData[7], Queue32_UInt8_44.io.deq.bits connect remapVecValids[7], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[7] node _T_2567 = eq(UInt<4>(0hd), remapindex_7) when _T_2567 : connect remapVecData[7], Queue32_UInt8_45.io.deq.bits connect remapVecValids[7], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[7] node _T_2568 = eq(UInt<4>(0he), remapindex_7) when _T_2568 : connect remapVecData[7], Queue32_UInt8_46.io.deq.bits connect remapVecValids[7], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[7] node _T_2569 = eq(UInt<4>(0hf), remapindex_7) when _T_2569 : connect remapVecData[7], Queue32_UInt8_47.io.deq.bits connect remapVecValids[7], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[7] node _T_2570 = eq(UInt<5>(0h10), remapindex_7) when _T_2570 : connect remapVecData[7], Queue32_UInt8_48.io.deq.bits connect remapVecValids[7], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[7] node _T_2571 = eq(UInt<5>(0h11), remapindex_7) when _T_2571 : connect remapVecData[7], Queue32_UInt8_49.io.deq.bits connect remapVecValids[7], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[7] node _T_2572 = eq(UInt<5>(0h12), remapindex_7) when _T_2572 : connect remapVecData[7], Queue32_UInt8_50.io.deq.bits connect remapVecValids[7], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[7] node _T_2573 = eq(UInt<5>(0h13), remapindex_7) when _T_2573 : connect remapVecData[7], Queue32_UInt8_51.io.deq.bits connect remapVecValids[7], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[7] node _T_2574 = eq(UInt<5>(0h14), remapindex_7) when _T_2574 : connect remapVecData[7], Queue32_UInt8_52.io.deq.bits connect remapVecValids[7], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[7] node _T_2575 = eq(UInt<5>(0h15), remapindex_7) when _T_2575 : connect remapVecData[7], Queue32_UInt8_53.io.deq.bits connect remapVecValids[7], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[7] node _T_2576 = eq(UInt<5>(0h16), remapindex_7) when _T_2576 : connect remapVecData[7], Queue32_UInt8_54.io.deq.bits connect remapVecValids[7], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[7] node _T_2577 = eq(UInt<5>(0h17), remapindex_7) when _T_2577 : connect remapVecData[7], Queue32_UInt8_55.io.deq.bits connect remapVecValids[7], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[7] node _T_2578 = eq(UInt<5>(0h18), remapindex_7) when _T_2578 : connect remapVecData[7], Queue32_UInt8_56.io.deq.bits connect remapVecValids[7], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[7] node _T_2579 = eq(UInt<5>(0h19), remapindex_7) when _T_2579 : connect remapVecData[7], Queue32_UInt8_57.io.deq.bits connect remapVecValids[7], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[7] node _T_2580 = eq(UInt<5>(0h1a), remapindex_7) when _T_2580 : connect remapVecData[7], Queue32_UInt8_58.io.deq.bits connect remapVecValids[7], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[7] node _T_2581 = eq(UInt<5>(0h1b), remapindex_7) when _T_2581 : connect remapVecData[7], Queue32_UInt8_59.io.deq.bits connect remapVecValids[7], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[7] node _T_2582 = eq(UInt<5>(0h1c), remapindex_7) when _T_2582 : connect remapVecData[7], Queue32_UInt8_60.io.deq.bits connect remapVecValids[7], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[7] node _T_2583 = eq(UInt<5>(0h1d), remapindex_7) when _T_2583 : connect remapVecData[7], Queue32_UInt8_61.io.deq.bits connect remapVecValids[7], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[7] node _T_2584 = eq(UInt<5>(0h1e), remapindex_7) when _T_2584 : connect remapVecData[7], Queue32_UInt8_62.io.deq.bits connect remapVecValids[7], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[7] node _T_2585 = eq(UInt<5>(0h1f), remapindex_7) when _T_2585 : connect remapVecData[7], Queue32_UInt8_63.io.deq.bits connect remapVecValids[7], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[7] node _remapindex_T_8 = add(UInt<4>(0h8), read_start_index) node remapindex_8 = rem(_remapindex_T_8, UInt<6>(0h20)) node _T_2586 = eq(UInt<1>(0h0), remapindex_8) when _T_2586 : connect remapVecData[8], Queue32_UInt8_32.io.deq.bits connect remapVecValids[8], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[8] node _T_2587 = eq(UInt<1>(0h1), remapindex_8) when _T_2587 : connect remapVecData[8], Queue32_UInt8_33.io.deq.bits connect remapVecValids[8], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[8] node _T_2588 = eq(UInt<2>(0h2), remapindex_8) when _T_2588 : connect remapVecData[8], Queue32_UInt8_34.io.deq.bits connect remapVecValids[8], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[8] node _T_2589 = eq(UInt<2>(0h3), remapindex_8) when _T_2589 : connect remapVecData[8], Queue32_UInt8_35.io.deq.bits connect remapVecValids[8], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[8] node _T_2590 = eq(UInt<3>(0h4), remapindex_8) when _T_2590 : connect remapVecData[8], Queue32_UInt8_36.io.deq.bits connect remapVecValids[8], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[8] node _T_2591 = eq(UInt<3>(0h5), remapindex_8) when _T_2591 : connect remapVecData[8], Queue32_UInt8_37.io.deq.bits connect remapVecValids[8], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[8] node _T_2592 = eq(UInt<3>(0h6), remapindex_8) when _T_2592 : connect remapVecData[8], Queue32_UInt8_38.io.deq.bits connect remapVecValids[8], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[8] node _T_2593 = eq(UInt<3>(0h7), remapindex_8) when _T_2593 : connect remapVecData[8], Queue32_UInt8_39.io.deq.bits connect remapVecValids[8], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[8] node _T_2594 = eq(UInt<4>(0h8), remapindex_8) when _T_2594 : connect remapVecData[8], Queue32_UInt8_40.io.deq.bits connect remapVecValids[8], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[8] node _T_2595 = eq(UInt<4>(0h9), remapindex_8) when _T_2595 : connect remapVecData[8], Queue32_UInt8_41.io.deq.bits connect remapVecValids[8], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[8] node _T_2596 = eq(UInt<4>(0ha), remapindex_8) when _T_2596 : connect remapVecData[8], Queue32_UInt8_42.io.deq.bits connect remapVecValids[8], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[8] node _T_2597 = eq(UInt<4>(0hb), remapindex_8) when _T_2597 : connect remapVecData[8], Queue32_UInt8_43.io.deq.bits connect remapVecValids[8], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[8] node _T_2598 = eq(UInt<4>(0hc), remapindex_8) when _T_2598 : connect remapVecData[8], Queue32_UInt8_44.io.deq.bits connect remapVecValids[8], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[8] node _T_2599 = eq(UInt<4>(0hd), remapindex_8) when _T_2599 : connect remapVecData[8], Queue32_UInt8_45.io.deq.bits connect remapVecValids[8], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[8] node _T_2600 = eq(UInt<4>(0he), remapindex_8) when _T_2600 : connect remapVecData[8], Queue32_UInt8_46.io.deq.bits connect remapVecValids[8], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[8] node _T_2601 = eq(UInt<4>(0hf), remapindex_8) when _T_2601 : connect remapVecData[8], Queue32_UInt8_47.io.deq.bits connect remapVecValids[8], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[8] node _T_2602 = eq(UInt<5>(0h10), remapindex_8) when _T_2602 : connect remapVecData[8], Queue32_UInt8_48.io.deq.bits connect remapVecValids[8], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[8] node _T_2603 = eq(UInt<5>(0h11), remapindex_8) when _T_2603 : connect remapVecData[8], Queue32_UInt8_49.io.deq.bits connect remapVecValids[8], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[8] node _T_2604 = eq(UInt<5>(0h12), remapindex_8) when _T_2604 : connect remapVecData[8], Queue32_UInt8_50.io.deq.bits connect remapVecValids[8], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[8] node _T_2605 = eq(UInt<5>(0h13), remapindex_8) when _T_2605 : connect remapVecData[8], Queue32_UInt8_51.io.deq.bits connect remapVecValids[8], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[8] node _T_2606 = eq(UInt<5>(0h14), remapindex_8) when _T_2606 : connect remapVecData[8], Queue32_UInt8_52.io.deq.bits connect remapVecValids[8], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[8] node _T_2607 = eq(UInt<5>(0h15), remapindex_8) when _T_2607 : connect remapVecData[8], Queue32_UInt8_53.io.deq.bits connect remapVecValids[8], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[8] node _T_2608 = eq(UInt<5>(0h16), remapindex_8) when _T_2608 : connect remapVecData[8], Queue32_UInt8_54.io.deq.bits connect remapVecValids[8], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[8] node _T_2609 = eq(UInt<5>(0h17), remapindex_8) when _T_2609 : connect remapVecData[8], Queue32_UInt8_55.io.deq.bits connect remapVecValids[8], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[8] node _T_2610 = eq(UInt<5>(0h18), remapindex_8) when _T_2610 : connect remapVecData[8], Queue32_UInt8_56.io.deq.bits connect remapVecValids[8], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[8] node _T_2611 = eq(UInt<5>(0h19), remapindex_8) when _T_2611 : connect remapVecData[8], Queue32_UInt8_57.io.deq.bits connect remapVecValids[8], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[8] node _T_2612 = eq(UInt<5>(0h1a), remapindex_8) when _T_2612 : connect remapVecData[8], Queue32_UInt8_58.io.deq.bits connect remapVecValids[8], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[8] node _T_2613 = eq(UInt<5>(0h1b), remapindex_8) when _T_2613 : connect remapVecData[8], Queue32_UInt8_59.io.deq.bits connect remapVecValids[8], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[8] node _T_2614 = eq(UInt<5>(0h1c), remapindex_8) when _T_2614 : connect remapVecData[8], Queue32_UInt8_60.io.deq.bits connect remapVecValids[8], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[8] node _T_2615 = eq(UInt<5>(0h1d), remapindex_8) when _T_2615 : connect remapVecData[8], Queue32_UInt8_61.io.deq.bits connect remapVecValids[8], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[8] node _T_2616 = eq(UInt<5>(0h1e), remapindex_8) when _T_2616 : connect remapVecData[8], Queue32_UInt8_62.io.deq.bits connect remapVecValids[8], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[8] node _T_2617 = eq(UInt<5>(0h1f), remapindex_8) when _T_2617 : connect remapVecData[8], Queue32_UInt8_63.io.deq.bits connect remapVecValids[8], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[8] node _remapindex_T_9 = add(UInt<4>(0h9), read_start_index) node remapindex_9 = rem(_remapindex_T_9, UInt<6>(0h20)) node _T_2618 = eq(UInt<1>(0h0), remapindex_9) when _T_2618 : connect remapVecData[9], Queue32_UInt8_32.io.deq.bits connect remapVecValids[9], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[9] node _T_2619 = eq(UInt<1>(0h1), remapindex_9) when _T_2619 : connect remapVecData[9], Queue32_UInt8_33.io.deq.bits connect remapVecValids[9], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[9] node _T_2620 = eq(UInt<2>(0h2), remapindex_9) when _T_2620 : connect remapVecData[9], Queue32_UInt8_34.io.deq.bits connect remapVecValids[9], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[9] node _T_2621 = eq(UInt<2>(0h3), remapindex_9) when _T_2621 : connect remapVecData[9], Queue32_UInt8_35.io.deq.bits connect remapVecValids[9], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[9] node _T_2622 = eq(UInt<3>(0h4), remapindex_9) when _T_2622 : connect remapVecData[9], Queue32_UInt8_36.io.deq.bits connect remapVecValids[9], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[9] node _T_2623 = eq(UInt<3>(0h5), remapindex_9) when _T_2623 : connect remapVecData[9], Queue32_UInt8_37.io.deq.bits connect remapVecValids[9], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[9] node _T_2624 = eq(UInt<3>(0h6), remapindex_9) when _T_2624 : connect remapVecData[9], Queue32_UInt8_38.io.deq.bits connect remapVecValids[9], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[9] node _T_2625 = eq(UInt<3>(0h7), remapindex_9) when _T_2625 : connect remapVecData[9], Queue32_UInt8_39.io.deq.bits connect remapVecValids[9], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[9] node _T_2626 = eq(UInt<4>(0h8), remapindex_9) when _T_2626 : connect remapVecData[9], Queue32_UInt8_40.io.deq.bits connect remapVecValids[9], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[9] node _T_2627 = eq(UInt<4>(0h9), remapindex_9) when _T_2627 : connect remapVecData[9], Queue32_UInt8_41.io.deq.bits connect remapVecValids[9], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[9] node _T_2628 = eq(UInt<4>(0ha), remapindex_9) when _T_2628 : connect remapVecData[9], Queue32_UInt8_42.io.deq.bits connect remapVecValids[9], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[9] node _T_2629 = eq(UInt<4>(0hb), remapindex_9) when _T_2629 : connect remapVecData[9], Queue32_UInt8_43.io.deq.bits connect remapVecValids[9], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[9] node _T_2630 = eq(UInt<4>(0hc), remapindex_9) when _T_2630 : connect remapVecData[9], Queue32_UInt8_44.io.deq.bits connect remapVecValids[9], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[9] node _T_2631 = eq(UInt<4>(0hd), remapindex_9) when _T_2631 : connect remapVecData[9], Queue32_UInt8_45.io.deq.bits connect remapVecValids[9], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[9] node _T_2632 = eq(UInt<4>(0he), remapindex_9) when _T_2632 : connect remapVecData[9], Queue32_UInt8_46.io.deq.bits connect remapVecValids[9], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[9] node _T_2633 = eq(UInt<4>(0hf), remapindex_9) when _T_2633 : connect remapVecData[9], Queue32_UInt8_47.io.deq.bits connect remapVecValids[9], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[9] node _T_2634 = eq(UInt<5>(0h10), remapindex_9) when _T_2634 : connect remapVecData[9], Queue32_UInt8_48.io.deq.bits connect remapVecValids[9], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[9] node _T_2635 = eq(UInt<5>(0h11), remapindex_9) when _T_2635 : connect remapVecData[9], Queue32_UInt8_49.io.deq.bits connect remapVecValids[9], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[9] node _T_2636 = eq(UInt<5>(0h12), remapindex_9) when _T_2636 : connect remapVecData[9], Queue32_UInt8_50.io.deq.bits connect remapVecValids[9], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[9] node _T_2637 = eq(UInt<5>(0h13), remapindex_9) when _T_2637 : connect remapVecData[9], Queue32_UInt8_51.io.deq.bits connect remapVecValids[9], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[9] node _T_2638 = eq(UInt<5>(0h14), remapindex_9) when _T_2638 : connect remapVecData[9], Queue32_UInt8_52.io.deq.bits connect remapVecValids[9], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[9] node _T_2639 = eq(UInt<5>(0h15), remapindex_9) when _T_2639 : connect remapVecData[9], Queue32_UInt8_53.io.deq.bits connect remapVecValids[9], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[9] node _T_2640 = eq(UInt<5>(0h16), remapindex_9) when _T_2640 : connect remapVecData[9], Queue32_UInt8_54.io.deq.bits connect remapVecValids[9], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[9] node _T_2641 = eq(UInt<5>(0h17), remapindex_9) when _T_2641 : connect remapVecData[9], Queue32_UInt8_55.io.deq.bits connect remapVecValids[9], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[9] node _T_2642 = eq(UInt<5>(0h18), remapindex_9) when _T_2642 : connect remapVecData[9], Queue32_UInt8_56.io.deq.bits connect remapVecValids[9], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[9] node _T_2643 = eq(UInt<5>(0h19), remapindex_9) when _T_2643 : connect remapVecData[9], Queue32_UInt8_57.io.deq.bits connect remapVecValids[9], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[9] node _T_2644 = eq(UInt<5>(0h1a), remapindex_9) when _T_2644 : connect remapVecData[9], Queue32_UInt8_58.io.deq.bits connect remapVecValids[9], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[9] node _T_2645 = eq(UInt<5>(0h1b), remapindex_9) when _T_2645 : connect remapVecData[9], Queue32_UInt8_59.io.deq.bits connect remapVecValids[9], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[9] node _T_2646 = eq(UInt<5>(0h1c), remapindex_9) when _T_2646 : connect remapVecData[9], Queue32_UInt8_60.io.deq.bits connect remapVecValids[9], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[9] node _T_2647 = eq(UInt<5>(0h1d), remapindex_9) when _T_2647 : connect remapVecData[9], Queue32_UInt8_61.io.deq.bits connect remapVecValids[9], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[9] node _T_2648 = eq(UInt<5>(0h1e), remapindex_9) when _T_2648 : connect remapVecData[9], Queue32_UInt8_62.io.deq.bits connect remapVecValids[9], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[9] node _T_2649 = eq(UInt<5>(0h1f), remapindex_9) when _T_2649 : connect remapVecData[9], Queue32_UInt8_63.io.deq.bits connect remapVecValids[9], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[9] node _remapindex_T_10 = add(UInt<4>(0ha), read_start_index) node remapindex_10 = rem(_remapindex_T_10, UInt<6>(0h20)) node _T_2650 = eq(UInt<1>(0h0), remapindex_10) when _T_2650 : connect remapVecData[10], Queue32_UInt8_32.io.deq.bits connect remapVecValids[10], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[10] node _T_2651 = eq(UInt<1>(0h1), remapindex_10) when _T_2651 : connect remapVecData[10], Queue32_UInt8_33.io.deq.bits connect remapVecValids[10], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[10] node _T_2652 = eq(UInt<2>(0h2), remapindex_10) when _T_2652 : connect remapVecData[10], Queue32_UInt8_34.io.deq.bits connect remapVecValids[10], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[10] node _T_2653 = eq(UInt<2>(0h3), remapindex_10) when _T_2653 : connect remapVecData[10], Queue32_UInt8_35.io.deq.bits connect remapVecValids[10], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[10] node _T_2654 = eq(UInt<3>(0h4), remapindex_10) when _T_2654 : connect remapVecData[10], Queue32_UInt8_36.io.deq.bits connect remapVecValids[10], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[10] node _T_2655 = eq(UInt<3>(0h5), remapindex_10) when _T_2655 : connect remapVecData[10], Queue32_UInt8_37.io.deq.bits connect remapVecValids[10], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[10] node _T_2656 = eq(UInt<3>(0h6), remapindex_10) when _T_2656 : connect remapVecData[10], Queue32_UInt8_38.io.deq.bits connect remapVecValids[10], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[10] node _T_2657 = eq(UInt<3>(0h7), remapindex_10) when _T_2657 : connect remapVecData[10], Queue32_UInt8_39.io.deq.bits connect remapVecValids[10], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[10] node _T_2658 = eq(UInt<4>(0h8), remapindex_10) when _T_2658 : connect remapVecData[10], Queue32_UInt8_40.io.deq.bits connect remapVecValids[10], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[10] node _T_2659 = eq(UInt<4>(0h9), remapindex_10) when _T_2659 : connect remapVecData[10], Queue32_UInt8_41.io.deq.bits connect remapVecValids[10], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[10] node _T_2660 = eq(UInt<4>(0ha), remapindex_10) when _T_2660 : connect remapVecData[10], Queue32_UInt8_42.io.deq.bits connect remapVecValids[10], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[10] node _T_2661 = eq(UInt<4>(0hb), remapindex_10) when _T_2661 : connect remapVecData[10], Queue32_UInt8_43.io.deq.bits connect remapVecValids[10], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[10] node _T_2662 = eq(UInt<4>(0hc), remapindex_10) when _T_2662 : connect remapVecData[10], Queue32_UInt8_44.io.deq.bits connect remapVecValids[10], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[10] node _T_2663 = eq(UInt<4>(0hd), remapindex_10) when _T_2663 : connect remapVecData[10], Queue32_UInt8_45.io.deq.bits connect remapVecValids[10], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[10] node _T_2664 = eq(UInt<4>(0he), remapindex_10) when _T_2664 : connect remapVecData[10], Queue32_UInt8_46.io.deq.bits connect remapVecValids[10], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[10] node _T_2665 = eq(UInt<4>(0hf), remapindex_10) when _T_2665 : connect remapVecData[10], Queue32_UInt8_47.io.deq.bits connect remapVecValids[10], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[10] node _T_2666 = eq(UInt<5>(0h10), remapindex_10) when _T_2666 : connect remapVecData[10], Queue32_UInt8_48.io.deq.bits connect remapVecValids[10], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[10] node _T_2667 = eq(UInt<5>(0h11), remapindex_10) when _T_2667 : connect remapVecData[10], Queue32_UInt8_49.io.deq.bits connect remapVecValids[10], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[10] node _T_2668 = eq(UInt<5>(0h12), remapindex_10) when _T_2668 : connect remapVecData[10], Queue32_UInt8_50.io.deq.bits connect remapVecValids[10], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[10] node _T_2669 = eq(UInt<5>(0h13), remapindex_10) when _T_2669 : connect remapVecData[10], Queue32_UInt8_51.io.deq.bits connect remapVecValids[10], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[10] node _T_2670 = eq(UInt<5>(0h14), remapindex_10) when _T_2670 : connect remapVecData[10], Queue32_UInt8_52.io.deq.bits connect remapVecValids[10], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[10] node _T_2671 = eq(UInt<5>(0h15), remapindex_10) when _T_2671 : connect remapVecData[10], Queue32_UInt8_53.io.deq.bits connect remapVecValids[10], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[10] node _T_2672 = eq(UInt<5>(0h16), remapindex_10) when _T_2672 : connect remapVecData[10], Queue32_UInt8_54.io.deq.bits connect remapVecValids[10], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[10] node _T_2673 = eq(UInt<5>(0h17), remapindex_10) when _T_2673 : connect remapVecData[10], Queue32_UInt8_55.io.deq.bits connect remapVecValids[10], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[10] node _T_2674 = eq(UInt<5>(0h18), remapindex_10) when _T_2674 : connect remapVecData[10], Queue32_UInt8_56.io.deq.bits connect remapVecValids[10], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[10] node _T_2675 = eq(UInt<5>(0h19), remapindex_10) when _T_2675 : connect remapVecData[10], Queue32_UInt8_57.io.deq.bits connect remapVecValids[10], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[10] node _T_2676 = eq(UInt<5>(0h1a), remapindex_10) when _T_2676 : connect remapVecData[10], Queue32_UInt8_58.io.deq.bits connect remapVecValids[10], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[10] node _T_2677 = eq(UInt<5>(0h1b), remapindex_10) when _T_2677 : connect remapVecData[10], Queue32_UInt8_59.io.deq.bits connect remapVecValids[10], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[10] node _T_2678 = eq(UInt<5>(0h1c), remapindex_10) when _T_2678 : connect remapVecData[10], Queue32_UInt8_60.io.deq.bits connect remapVecValids[10], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[10] node _T_2679 = eq(UInt<5>(0h1d), remapindex_10) when _T_2679 : connect remapVecData[10], Queue32_UInt8_61.io.deq.bits connect remapVecValids[10], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[10] node _T_2680 = eq(UInt<5>(0h1e), remapindex_10) when _T_2680 : connect remapVecData[10], Queue32_UInt8_62.io.deq.bits connect remapVecValids[10], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[10] node _T_2681 = eq(UInt<5>(0h1f), remapindex_10) when _T_2681 : connect remapVecData[10], Queue32_UInt8_63.io.deq.bits connect remapVecValids[10], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[10] node _remapindex_T_11 = add(UInt<4>(0hb), read_start_index) node remapindex_11 = rem(_remapindex_T_11, UInt<6>(0h20)) node _T_2682 = eq(UInt<1>(0h0), remapindex_11) when _T_2682 : connect remapVecData[11], Queue32_UInt8_32.io.deq.bits connect remapVecValids[11], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[11] node _T_2683 = eq(UInt<1>(0h1), remapindex_11) when _T_2683 : connect remapVecData[11], Queue32_UInt8_33.io.deq.bits connect remapVecValids[11], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[11] node _T_2684 = eq(UInt<2>(0h2), remapindex_11) when _T_2684 : connect remapVecData[11], Queue32_UInt8_34.io.deq.bits connect remapVecValids[11], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[11] node _T_2685 = eq(UInt<2>(0h3), remapindex_11) when _T_2685 : connect remapVecData[11], Queue32_UInt8_35.io.deq.bits connect remapVecValids[11], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[11] node _T_2686 = eq(UInt<3>(0h4), remapindex_11) when _T_2686 : connect remapVecData[11], Queue32_UInt8_36.io.deq.bits connect remapVecValids[11], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[11] node _T_2687 = eq(UInt<3>(0h5), remapindex_11) when _T_2687 : connect remapVecData[11], Queue32_UInt8_37.io.deq.bits connect remapVecValids[11], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[11] node _T_2688 = eq(UInt<3>(0h6), remapindex_11) when _T_2688 : connect remapVecData[11], Queue32_UInt8_38.io.deq.bits connect remapVecValids[11], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[11] node _T_2689 = eq(UInt<3>(0h7), remapindex_11) when _T_2689 : connect remapVecData[11], Queue32_UInt8_39.io.deq.bits connect remapVecValids[11], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[11] node _T_2690 = eq(UInt<4>(0h8), remapindex_11) when _T_2690 : connect remapVecData[11], Queue32_UInt8_40.io.deq.bits connect remapVecValids[11], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[11] node _T_2691 = eq(UInt<4>(0h9), remapindex_11) when _T_2691 : connect remapVecData[11], Queue32_UInt8_41.io.deq.bits connect remapVecValids[11], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[11] node _T_2692 = eq(UInt<4>(0ha), remapindex_11) when _T_2692 : connect remapVecData[11], Queue32_UInt8_42.io.deq.bits connect remapVecValids[11], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[11] node _T_2693 = eq(UInt<4>(0hb), remapindex_11) when _T_2693 : connect remapVecData[11], Queue32_UInt8_43.io.deq.bits connect remapVecValids[11], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[11] node _T_2694 = eq(UInt<4>(0hc), remapindex_11) when _T_2694 : connect remapVecData[11], Queue32_UInt8_44.io.deq.bits connect remapVecValids[11], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[11] node _T_2695 = eq(UInt<4>(0hd), remapindex_11) when _T_2695 : connect remapVecData[11], Queue32_UInt8_45.io.deq.bits connect remapVecValids[11], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[11] node _T_2696 = eq(UInt<4>(0he), remapindex_11) when _T_2696 : connect remapVecData[11], Queue32_UInt8_46.io.deq.bits connect remapVecValids[11], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[11] node _T_2697 = eq(UInt<4>(0hf), remapindex_11) when _T_2697 : connect remapVecData[11], Queue32_UInt8_47.io.deq.bits connect remapVecValids[11], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[11] node _T_2698 = eq(UInt<5>(0h10), remapindex_11) when _T_2698 : connect remapVecData[11], Queue32_UInt8_48.io.deq.bits connect remapVecValids[11], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[11] node _T_2699 = eq(UInt<5>(0h11), remapindex_11) when _T_2699 : connect remapVecData[11], Queue32_UInt8_49.io.deq.bits connect remapVecValids[11], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[11] node _T_2700 = eq(UInt<5>(0h12), remapindex_11) when _T_2700 : connect remapVecData[11], Queue32_UInt8_50.io.deq.bits connect remapVecValids[11], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[11] node _T_2701 = eq(UInt<5>(0h13), remapindex_11) when _T_2701 : connect remapVecData[11], Queue32_UInt8_51.io.deq.bits connect remapVecValids[11], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[11] node _T_2702 = eq(UInt<5>(0h14), remapindex_11) when _T_2702 : connect remapVecData[11], Queue32_UInt8_52.io.deq.bits connect remapVecValids[11], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[11] node _T_2703 = eq(UInt<5>(0h15), remapindex_11) when _T_2703 : connect remapVecData[11], Queue32_UInt8_53.io.deq.bits connect remapVecValids[11], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[11] node _T_2704 = eq(UInt<5>(0h16), remapindex_11) when _T_2704 : connect remapVecData[11], Queue32_UInt8_54.io.deq.bits connect remapVecValids[11], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[11] node _T_2705 = eq(UInt<5>(0h17), remapindex_11) when _T_2705 : connect remapVecData[11], Queue32_UInt8_55.io.deq.bits connect remapVecValids[11], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[11] node _T_2706 = eq(UInt<5>(0h18), remapindex_11) when _T_2706 : connect remapVecData[11], Queue32_UInt8_56.io.deq.bits connect remapVecValids[11], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[11] node _T_2707 = eq(UInt<5>(0h19), remapindex_11) when _T_2707 : connect remapVecData[11], Queue32_UInt8_57.io.deq.bits connect remapVecValids[11], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[11] node _T_2708 = eq(UInt<5>(0h1a), remapindex_11) when _T_2708 : connect remapVecData[11], Queue32_UInt8_58.io.deq.bits connect remapVecValids[11], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[11] node _T_2709 = eq(UInt<5>(0h1b), remapindex_11) when _T_2709 : connect remapVecData[11], Queue32_UInt8_59.io.deq.bits connect remapVecValids[11], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[11] node _T_2710 = eq(UInt<5>(0h1c), remapindex_11) when _T_2710 : connect remapVecData[11], Queue32_UInt8_60.io.deq.bits connect remapVecValids[11], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[11] node _T_2711 = eq(UInt<5>(0h1d), remapindex_11) when _T_2711 : connect remapVecData[11], Queue32_UInt8_61.io.deq.bits connect remapVecValids[11], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[11] node _T_2712 = eq(UInt<5>(0h1e), remapindex_11) when _T_2712 : connect remapVecData[11], Queue32_UInt8_62.io.deq.bits connect remapVecValids[11], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[11] node _T_2713 = eq(UInt<5>(0h1f), remapindex_11) when _T_2713 : connect remapVecData[11], Queue32_UInt8_63.io.deq.bits connect remapVecValids[11], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[11] node _remapindex_T_12 = add(UInt<4>(0hc), read_start_index) node remapindex_12 = rem(_remapindex_T_12, UInt<6>(0h20)) node _T_2714 = eq(UInt<1>(0h0), remapindex_12) when _T_2714 : connect remapVecData[12], Queue32_UInt8_32.io.deq.bits connect remapVecValids[12], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[12] node _T_2715 = eq(UInt<1>(0h1), remapindex_12) when _T_2715 : connect remapVecData[12], Queue32_UInt8_33.io.deq.bits connect remapVecValids[12], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[12] node _T_2716 = eq(UInt<2>(0h2), remapindex_12) when _T_2716 : connect remapVecData[12], Queue32_UInt8_34.io.deq.bits connect remapVecValids[12], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[12] node _T_2717 = eq(UInt<2>(0h3), remapindex_12) when _T_2717 : connect remapVecData[12], Queue32_UInt8_35.io.deq.bits connect remapVecValids[12], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[12] node _T_2718 = eq(UInt<3>(0h4), remapindex_12) when _T_2718 : connect remapVecData[12], Queue32_UInt8_36.io.deq.bits connect remapVecValids[12], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[12] node _T_2719 = eq(UInt<3>(0h5), remapindex_12) when _T_2719 : connect remapVecData[12], Queue32_UInt8_37.io.deq.bits connect remapVecValids[12], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[12] node _T_2720 = eq(UInt<3>(0h6), remapindex_12) when _T_2720 : connect remapVecData[12], Queue32_UInt8_38.io.deq.bits connect remapVecValids[12], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[12] node _T_2721 = eq(UInt<3>(0h7), remapindex_12) when _T_2721 : connect remapVecData[12], Queue32_UInt8_39.io.deq.bits connect remapVecValids[12], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[12] node _T_2722 = eq(UInt<4>(0h8), remapindex_12) when _T_2722 : connect remapVecData[12], Queue32_UInt8_40.io.deq.bits connect remapVecValids[12], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[12] node _T_2723 = eq(UInt<4>(0h9), remapindex_12) when _T_2723 : connect remapVecData[12], Queue32_UInt8_41.io.deq.bits connect remapVecValids[12], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[12] node _T_2724 = eq(UInt<4>(0ha), remapindex_12) when _T_2724 : connect remapVecData[12], Queue32_UInt8_42.io.deq.bits connect remapVecValids[12], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[12] node _T_2725 = eq(UInt<4>(0hb), remapindex_12) when _T_2725 : connect remapVecData[12], Queue32_UInt8_43.io.deq.bits connect remapVecValids[12], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[12] node _T_2726 = eq(UInt<4>(0hc), remapindex_12) when _T_2726 : connect remapVecData[12], Queue32_UInt8_44.io.deq.bits connect remapVecValids[12], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[12] node _T_2727 = eq(UInt<4>(0hd), remapindex_12) when _T_2727 : connect remapVecData[12], Queue32_UInt8_45.io.deq.bits connect remapVecValids[12], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[12] node _T_2728 = eq(UInt<4>(0he), remapindex_12) when _T_2728 : connect remapVecData[12], Queue32_UInt8_46.io.deq.bits connect remapVecValids[12], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[12] node _T_2729 = eq(UInt<4>(0hf), remapindex_12) when _T_2729 : connect remapVecData[12], Queue32_UInt8_47.io.deq.bits connect remapVecValids[12], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[12] node _T_2730 = eq(UInt<5>(0h10), remapindex_12) when _T_2730 : connect remapVecData[12], Queue32_UInt8_48.io.deq.bits connect remapVecValids[12], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[12] node _T_2731 = eq(UInt<5>(0h11), remapindex_12) when _T_2731 : connect remapVecData[12], Queue32_UInt8_49.io.deq.bits connect remapVecValids[12], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[12] node _T_2732 = eq(UInt<5>(0h12), remapindex_12) when _T_2732 : connect remapVecData[12], Queue32_UInt8_50.io.deq.bits connect remapVecValids[12], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[12] node _T_2733 = eq(UInt<5>(0h13), remapindex_12) when _T_2733 : connect remapVecData[12], Queue32_UInt8_51.io.deq.bits connect remapVecValids[12], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[12] node _T_2734 = eq(UInt<5>(0h14), remapindex_12) when _T_2734 : connect remapVecData[12], Queue32_UInt8_52.io.deq.bits connect remapVecValids[12], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[12] node _T_2735 = eq(UInt<5>(0h15), remapindex_12) when _T_2735 : connect remapVecData[12], Queue32_UInt8_53.io.deq.bits connect remapVecValids[12], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[12] node _T_2736 = eq(UInt<5>(0h16), remapindex_12) when _T_2736 : connect remapVecData[12], Queue32_UInt8_54.io.deq.bits connect remapVecValids[12], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[12] node _T_2737 = eq(UInt<5>(0h17), remapindex_12) when _T_2737 : connect remapVecData[12], Queue32_UInt8_55.io.deq.bits connect remapVecValids[12], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[12] node _T_2738 = eq(UInt<5>(0h18), remapindex_12) when _T_2738 : connect remapVecData[12], Queue32_UInt8_56.io.deq.bits connect remapVecValids[12], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[12] node _T_2739 = eq(UInt<5>(0h19), remapindex_12) when _T_2739 : connect remapVecData[12], Queue32_UInt8_57.io.deq.bits connect remapVecValids[12], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[12] node _T_2740 = eq(UInt<5>(0h1a), remapindex_12) when _T_2740 : connect remapVecData[12], Queue32_UInt8_58.io.deq.bits connect remapVecValids[12], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[12] node _T_2741 = eq(UInt<5>(0h1b), remapindex_12) when _T_2741 : connect remapVecData[12], Queue32_UInt8_59.io.deq.bits connect remapVecValids[12], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[12] node _T_2742 = eq(UInt<5>(0h1c), remapindex_12) when _T_2742 : connect remapVecData[12], Queue32_UInt8_60.io.deq.bits connect remapVecValids[12], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[12] node _T_2743 = eq(UInt<5>(0h1d), remapindex_12) when _T_2743 : connect remapVecData[12], Queue32_UInt8_61.io.deq.bits connect remapVecValids[12], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[12] node _T_2744 = eq(UInt<5>(0h1e), remapindex_12) when _T_2744 : connect remapVecData[12], Queue32_UInt8_62.io.deq.bits connect remapVecValids[12], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[12] node _T_2745 = eq(UInt<5>(0h1f), remapindex_12) when _T_2745 : connect remapVecData[12], Queue32_UInt8_63.io.deq.bits connect remapVecValids[12], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[12] node _remapindex_T_13 = add(UInt<4>(0hd), read_start_index) node remapindex_13 = rem(_remapindex_T_13, UInt<6>(0h20)) node _T_2746 = eq(UInt<1>(0h0), remapindex_13) when _T_2746 : connect remapVecData[13], Queue32_UInt8_32.io.deq.bits connect remapVecValids[13], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[13] node _T_2747 = eq(UInt<1>(0h1), remapindex_13) when _T_2747 : connect remapVecData[13], Queue32_UInt8_33.io.deq.bits connect remapVecValids[13], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[13] node _T_2748 = eq(UInt<2>(0h2), remapindex_13) when _T_2748 : connect remapVecData[13], Queue32_UInt8_34.io.deq.bits connect remapVecValids[13], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[13] node _T_2749 = eq(UInt<2>(0h3), remapindex_13) when _T_2749 : connect remapVecData[13], Queue32_UInt8_35.io.deq.bits connect remapVecValids[13], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[13] node _T_2750 = eq(UInt<3>(0h4), remapindex_13) when _T_2750 : connect remapVecData[13], Queue32_UInt8_36.io.deq.bits connect remapVecValids[13], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[13] node _T_2751 = eq(UInt<3>(0h5), remapindex_13) when _T_2751 : connect remapVecData[13], Queue32_UInt8_37.io.deq.bits connect remapVecValids[13], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[13] node _T_2752 = eq(UInt<3>(0h6), remapindex_13) when _T_2752 : connect remapVecData[13], Queue32_UInt8_38.io.deq.bits connect remapVecValids[13], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[13] node _T_2753 = eq(UInt<3>(0h7), remapindex_13) when _T_2753 : connect remapVecData[13], Queue32_UInt8_39.io.deq.bits connect remapVecValids[13], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[13] node _T_2754 = eq(UInt<4>(0h8), remapindex_13) when _T_2754 : connect remapVecData[13], Queue32_UInt8_40.io.deq.bits connect remapVecValids[13], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[13] node _T_2755 = eq(UInt<4>(0h9), remapindex_13) when _T_2755 : connect remapVecData[13], Queue32_UInt8_41.io.deq.bits connect remapVecValids[13], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[13] node _T_2756 = eq(UInt<4>(0ha), remapindex_13) when _T_2756 : connect remapVecData[13], Queue32_UInt8_42.io.deq.bits connect remapVecValids[13], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[13] node _T_2757 = eq(UInt<4>(0hb), remapindex_13) when _T_2757 : connect remapVecData[13], Queue32_UInt8_43.io.deq.bits connect remapVecValids[13], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[13] node _T_2758 = eq(UInt<4>(0hc), remapindex_13) when _T_2758 : connect remapVecData[13], Queue32_UInt8_44.io.deq.bits connect remapVecValids[13], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[13] node _T_2759 = eq(UInt<4>(0hd), remapindex_13) when _T_2759 : connect remapVecData[13], Queue32_UInt8_45.io.deq.bits connect remapVecValids[13], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[13] node _T_2760 = eq(UInt<4>(0he), remapindex_13) when _T_2760 : connect remapVecData[13], Queue32_UInt8_46.io.deq.bits connect remapVecValids[13], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[13] node _T_2761 = eq(UInt<4>(0hf), remapindex_13) when _T_2761 : connect remapVecData[13], Queue32_UInt8_47.io.deq.bits connect remapVecValids[13], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[13] node _T_2762 = eq(UInt<5>(0h10), remapindex_13) when _T_2762 : connect remapVecData[13], Queue32_UInt8_48.io.deq.bits connect remapVecValids[13], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[13] node _T_2763 = eq(UInt<5>(0h11), remapindex_13) when _T_2763 : connect remapVecData[13], Queue32_UInt8_49.io.deq.bits connect remapVecValids[13], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[13] node _T_2764 = eq(UInt<5>(0h12), remapindex_13) when _T_2764 : connect remapVecData[13], Queue32_UInt8_50.io.deq.bits connect remapVecValids[13], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[13] node _T_2765 = eq(UInt<5>(0h13), remapindex_13) when _T_2765 : connect remapVecData[13], Queue32_UInt8_51.io.deq.bits connect remapVecValids[13], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[13] node _T_2766 = eq(UInt<5>(0h14), remapindex_13) when _T_2766 : connect remapVecData[13], Queue32_UInt8_52.io.deq.bits connect remapVecValids[13], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[13] node _T_2767 = eq(UInt<5>(0h15), remapindex_13) when _T_2767 : connect remapVecData[13], Queue32_UInt8_53.io.deq.bits connect remapVecValids[13], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[13] node _T_2768 = eq(UInt<5>(0h16), remapindex_13) when _T_2768 : connect remapVecData[13], Queue32_UInt8_54.io.deq.bits connect remapVecValids[13], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[13] node _T_2769 = eq(UInt<5>(0h17), remapindex_13) when _T_2769 : connect remapVecData[13], Queue32_UInt8_55.io.deq.bits connect remapVecValids[13], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[13] node _T_2770 = eq(UInt<5>(0h18), remapindex_13) when _T_2770 : connect remapVecData[13], Queue32_UInt8_56.io.deq.bits connect remapVecValids[13], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[13] node _T_2771 = eq(UInt<5>(0h19), remapindex_13) when _T_2771 : connect remapVecData[13], Queue32_UInt8_57.io.deq.bits connect remapVecValids[13], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[13] node _T_2772 = eq(UInt<5>(0h1a), remapindex_13) when _T_2772 : connect remapVecData[13], Queue32_UInt8_58.io.deq.bits connect remapVecValids[13], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[13] node _T_2773 = eq(UInt<5>(0h1b), remapindex_13) when _T_2773 : connect remapVecData[13], Queue32_UInt8_59.io.deq.bits connect remapVecValids[13], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[13] node _T_2774 = eq(UInt<5>(0h1c), remapindex_13) when _T_2774 : connect remapVecData[13], Queue32_UInt8_60.io.deq.bits connect remapVecValids[13], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[13] node _T_2775 = eq(UInt<5>(0h1d), remapindex_13) when _T_2775 : connect remapVecData[13], Queue32_UInt8_61.io.deq.bits connect remapVecValids[13], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[13] node _T_2776 = eq(UInt<5>(0h1e), remapindex_13) when _T_2776 : connect remapVecData[13], Queue32_UInt8_62.io.deq.bits connect remapVecValids[13], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[13] node _T_2777 = eq(UInt<5>(0h1f), remapindex_13) when _T_2777 : connect remapVecData[13], Queue32_UInt8_63.io.deq.bits connect remapVecValids[13], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[13] node _remapindex_T_14 = add(UInt<4>(0he), read_start_index) node remapindex_14 = rem(_remapindex_T_14, UInt<6>(0h20)) node _T_2778 = eq(UInt<1>(0h0), remapindex_14) when _T_2778 : connect remapVecData[14], Queue32_UInt8_32.io.deq.bits connect remapVecValids[14], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[14] node _T_2779 = eq(UInt<1>(0h1), remapindex_14) when _T_2779 : connect remapVecData[14], Queue32_UInt8_33.io.deq.bits connect remapVecValids[14], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[14] node _T_2780 = eq(UInt<2>(0h2), remapindex_14) when _T_2780 : connect remapVecData[14], Queue32_UInt8_34.io.deq.bits connect remapVecValids[14], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[14] node _T_2781 = eq(UInt<2>(0h3), remapindex_14) when _T_2781 : connect remapVecData[14], Queue32_UInt8_35.io.deq.bits connect remapVecValids[14], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[14] node _T_2782 = eq(UInt<3>(0h4), remapindex_14) when _T_2782 : connect remapVecData[14], Queue32_UInt8_36.io.deq.bits connect remapVecValids[14], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[14] node _T_2783 = eq(UInt<3>(0h5), remapindex_14) when _T_2783 : connect remapVecData[14], Queue32_UInt8_37.io.deq.bits connect remapVecValids[14], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[14] node _T_2784 = eq(UInt<3>(0h6), remapindex_14) when _T_2784 : connect remapVecData[14], Queue32_UInt8_38.io.deq.bits connect remapVecValids[14], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[14] node _T_2785 = eq(UInt<3>(0h7), remapindex_14) when _T_2785 : connect remapVecData[14], Queue32_UInt8_39.io.deq.bits connect remapVecValids[14], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[14] node _T_2786 = eq(UInt<4>(0h8), remapindex_14) when _T_2786 : connect remapVecData[14], Queue32_UInt8_40.io.deq.bits connect remapVecValids[14], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[14] node _T_2787 = eq(UInt<4>(0h9), remapindex_14) when _T_2787 : connect remapVecData[14], Queue32_UInt8_41.io.deq.bits connect remapVecValids[14], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[14] node _T_2788 = eq(UInt<4>(0ha), remapindex_14) when _T_2788 : connect remapVecData[14], Queue32_UInt8_42.io.deq.bits connect remapVecValids[14], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[14] node _T_2789 = eq(UInt<4>(0hb), remapindex_14) when _T_2789 : connect remapVecData[14], Queue32_UInt8_43.io.deq.bits connect remapVecValids[14], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[14] node _T_2790 = eq(UInt<4>(0hc), remapindex_14) when _T_2790 : connect remapVecData[14], Queue32_UInt8_44.io.deq.bits connect remapVecValids[14], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[14] node _T_2791 = eq(UInt<4>(0hd), remapindex_14) when _T_2791 : connect remapVecData[14], Queue32_UInt8_45.io.deq.bits connect remapVecValids[14], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[14] node _T_2792 = eq(UInt<4>(0he), remapindex_14) when _T_2792 : connect remapVecData[14], Queue32_UInt8_46.io.deq.bits connect remapVecValids[14], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[14] node _T_2793 = eq(UInt<4>(0hf), remapindex_14) when _T_2793 : connect remapVecData[14], Queue32_UInt8_47.io.deq.bits connect remapVecValids[14], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[14] node _T_2794 = eq(UInt<5>(0h10), remapindex_14) when _T_2794 : connect remapVecData[14], Queue32_UInt8_48.io.deq.bits connect remapVecValids[14], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[14] node _T_2795 = eq(UInt<5>(0h11), remapindex_14) when _T_2795 : connect remapVecData[14], Queue32_UInt8_49.io.deq.bits connect remapVecValids[14], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[14] node _T_2796 = eq(UInt<5>(0h12), remapindex_14) when _T_2796 : connect remapVecData[14], Queue32_UInt8_50.io.deq.bits connect remapVecValids[14], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[14] node _T_2797 = eq(UInt<5>(0h13), remapindex_14) when _T_2797 : connect remapVecData[14], Queue32_UInt8_51.io.deq.bits connect remapVecValids[14], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[14] node _T_2798 = eq(UInt<5>(0h14), remapindex_14) when _T_2798 : connect remapVecData[14], Queue32_UInt8_52.io.deq.bits connect remapVecValids[14], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[14] node _T_2799 = eq(UInt<5>(0h15), remapindex_14) when _T_2799 : connect remapVecData[14], Queue32_UInt8_53.io.deq.bits connect remapVecValids[14], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[14] node _T_2800 = eq(UInt<5>(0h16), remapindex_14) when _T_2800 : connect remapVecData[14], Queue32_UInt8_54.io.deq.bits connect remapVecValids[14], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[14] node _T_2801 = eq(UInt<5>(0h17), remapindex_14) when _T_2801 : connect remapVecData[14], Queue32_UInt8_55.io.deq.bits connect remapVecValids[14], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[14] node _T_2802 = eq(UInt<5>(0h18), remapindex_14) when _T_2802 : connect remapVecData[14], Queue32_UInt8_56.io.deq.bits connect remapVecValids[14], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[14] node _T_2803 = eq(UInt<5>(0h19), remapindex_14) when _T_2803 : connect remapVecData[14], Queue32_UInt8_57.io.deq.bits connect remapVecValids[14], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[14] node _T_2804 = eq(UInt<5>(0h1a), remapindex_14) when _T_2804 : connect remapVecData[14], Queue32_UInt8_58.io.deq.bits connect remapVecValids[14], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[14] node _T_2805 = eq(UInt<5>(0h1b), remapindex_14) when _T_2805 : connect remapVecData[14], Queue32_UInt8_59.io.deq.bits connect remapVecValids[14], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[14] node _T_2806 = eq(UInt<5>(0h1c), remapindex_14) when _T_2806 : connect remapVecData[14], Queue32_UInt8_60.io.deq.bits connect remapVecValids[14], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[14] node _T_2807 = eq(UInt<5>(0h1d), remapindex_14) when _T_2807 : connect remapVecData[14], Queue32_UInt8_61.io.deq.bits connect remapVecValids[14], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[14] node _T_2808 = eq(UInt<5>(0h1e), remapindex_14) when _T_2808 : connect remapVecData[14], Queue32_UInt8_62.io.deq.bits connect remapVecValids[14], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[14] node _T_2809 = eq(UInt<5>(0h1f), remapindex_14) when _T_2809 : connect remapVecData[14], Queue32_UInt8_63.io.deq.bits connect remapVecValids[14], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[14] node _remapindex_T_15 = add(UInt<4>(0hf), read_start_index) node remapindex_15 = rem(_remapindex_T_15, UInt<6>(0h20)) node _T_2810 = eq(UInt<1>(0h0), remapindex_15) when _T_2810 : connect remapVecData[15], Queue32_UInt8_32.io.deq.bits connect remapVecValids[15], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[15] node _T_2811 = eq(UInt<1>(0h1), remapindex_15) when _T_2811 : connect remapVecData[15], Queue32_UInt8_33.io.deq.bits connect remapVecValids[15], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[15] node _T_2812 = eq(UInt<2>(0h2), remapindex_15) when _T_2812 : connect remapVecData[15], Queue32_UInt8_34.io.deq.bits connect remapVecValids[15], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[15] node _T_2813 = eq(UInt<2>(0h3), remapindex_15) when _T_2813 : connect remapVecData[15], Queue32_UInt8_35.io.deq.bits connect remapVecValids[15], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[15] node _T_2814 = eq(UInt<3>(0h4), remapindex_15) when _T_2814 : connect remapVecData[15], Queue32_UInt8_36.io.deq.bits connect remapVecValids[15], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[15] node _T_2815 = eq(UInt<3>(0h5), remapindex_15) when _T_2815 : connect remapVecData[15], Queue32_UInt8_37.io.deq.bits connect remapVecValids[15], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[15] node _T_2816 = eq(UInt<3>(0h6), remapindex_15) when _T_2816 : connect remapVecData[15], Queue32_UInt8_38.io.deq.bits connect remapVecValids[15], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[15] node _T_2817 = eq(UInt<3>(0h7), remapindex_15) when _T_2817 : connect remapVecData[15], Queue32_UInt8_39.io.deq.bits connect remapVecValids[15], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[15] node _T_2818 = eq(UInt<4>(0h8), remapindex_15) when _T_2818 : connect remapVecData[15], Queue32_UInt8_40.io.deq.bits connect remapVecValids[15], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[15] node _T_2819 = eq(UInt<4>(0h9), remapindex_15) when _T_2819 : connect remapVecData[15], Queue32_UInt8_41.io.deq.bits connect remapVecValids[15], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[15] node _T_2820 = eq(UInt<4>(0ha), remapindex_15) when _T_2820 : connect remapVecData[15], Queue32_UInt8_42.io.deq.bits connect remapVecValids[15], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[15] node _T_2821 = eq(UInt<4>(0hb), remapindex_15) when _T_2821 : connect remapVecData[15], Queue32_UInt8_43.io.deq.bits connect remapVecValids[15], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[15] node _T_2822 = eq(UInt<4>(0hc), remapindex_15) when _T_2822 : connect remapVecData[15], Queue32_UInt8_44.io.deq.bits connect remapVecValids[15], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[15] node _T_2823 = eq(UInt<4>(0hd), remapindex_15) when _T_2823 : connect remapVecData[15], Queue32_UInt8_45.io.deq.bits connect remapVecValids[15], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[15] node _T_2824 = eq(UInt<4>(0he), remapindex_15) when _T_2824 : connect remapVecData[15], Queue32_UInt8_46.io.deq.bits connect remapVecValids[15], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[15] node _T_2825 = eq(UInt<4>(0hf), remapindex_15) when _T_2825 : connect remapVecData[15], Queue32_UInt8_47.io.deq.bits connect remapVecValids[15], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[15] node _T_2826 = eq(UInt<5>(0h10), remapindex_15) when _T_2826 : connect remapVecData[15], Queue32_UInt8_48.io.deq.bits connect remapVecValids[15], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[15] node _T_2827 = eq(UInt<5>(0h11), remapindex_15) when _T_2827 : connect remapVecData[15], Queue32_UInt8_49.io.deq.bits connect remapVecValids[15], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[15] node _T_2828 = eq(UInt<5>(0h12), remapindex_15) when _T_2828 : connect remapVecData[15], Queue32_UInt8_50.io.deq.bits connect remapVecValids[15], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[15] node _T_2829 = eq(UInt<5>(0h13), remapindex_15) when _T_2829 : connect remapVecData[15], Queue32_UInt8_51.io.deq.bits connect remapVecValids[15], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[15] node _T_2830 = eq(UInt<5>(0h14), remapindex_15) when _T_2830 : connect remapVecData[15], Queue32_UInt8_52.io.deq.bits connect remapVecValids[15], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[15] node _T_2831 = eq(UInt<5>(0h15), remapindex_15) when _T_2831 : connect remapVecData[15], Queue32_UInt8_53.io.deq.bits connect remapVecValids[15], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[15] node _T_2832 = eq(UInt<5>(0h16), remapindex_15) when _T_2832 : connect remapVecData[15], Queue32_UInt8_54.io.deq.bits connect remapVecValids[15], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[15] node _T_2833 = eq(UInt<5>(0h17), remapindex_15) when _T_2833 : connect remapVecData[15], Queue32_UInt8_55.io.deq.bits connect remapVecValids[15], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[15] node _T_2834 = eq(UInt<5>(0h18), remapindex_15) when _T_2834 : connect remapVecData[15], Queue32_UInt8_56.io.deq.bits connect remapVecValids[15], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[15] node _T_2835 = eq(UInt<5>(0h19), remapindex_15) when _T_2835 : connect remapVecData[15], Queue32_UInt8_57.io.deq.bits connect remapVecValids[15], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[15] node _T_2836 = eq(UInt<5>(0h1a), remapindex_15) when _T_2836 : connect remapVecData[15], Queue32_UInt8_58.io.deq.bits connect remapVecValids[15], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[15] node _T_2837 = eq(UInt<5>(0h1b), remapindex_15) when _T_2837 : connect remapVecData[15], Queue32_UInt8_59.io.deq.bits connect remapVecValids[15], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[15] node _T_2838 = eq(UInt<5>(0h1c), remapindex_15) when _T_2838 : connect remapVecData[15], Queue32_UInt8_60.io.deq.bits connect remapVecValids[15], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[15] node _T_2839 = eq(UInt<5>(0h1d), remapindex_15) when _T_2839 : connect remapVecData[15], Queue32_UInt8_61.io.deq.bits connect remapVecValids[15], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[15] node _T_2840 = eq(UInt<5>(0h1e), remapindex_15) when _T_2840 : connect remapVecData[15], Queue32_UInt8_62.io.deq.bits connect remapVecValids[15], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[15] node _T_2841 = eq(UInt<5>(0h1f), remapindex_15) when _T_2841 : connect remapVecData[15], Queue32_UInt8_63.io.deq.bits connect remapVecValids[15], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[15] node _remapindex_T_16 = add(UInt<5>(0h10), read_start_index) node remapindex_16 = rem(_remapindex_T_16, UInt<6>(0h20)) node _T_2842 = eq(UInt<1>(0h0), remapindex_16) when _T_2842 : connect remapVecData[16], Queue32_UInt8_32.io.deq.bits connect remapVecValids[16], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[16] node _T_2843 = eq(UInt<1>(0h1), remapindex_16) when _T_2843 : connect remapVecData[16], Queue32_UInt8_33.io.deq.bits connect remapVecValids[16], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[16] node _T_2844 = eq(UInt<2>(0h2), remapindex_16) when _T_2844 : connect remapVecData[16], Queue32_UInt8_34.io.deq.bits connect remapVecValids[16], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[16] node _T_2845 = eq(UInt<2>(0h3), remapindex_16) when _T_2845 : connect remapVecData[16], Queue32_UInt8_35.io.deq.bits connect remapVecValids[16], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[16] node _T_2846 = eq(UInt<3>(0h4), remapindex_16) when _T_2846 : connect remapVecData[16], Queue32_UInt8_36.io.deq.bits connect remapVecValids[16], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[16] node _T_2847 = eq(UInt<3>(0h5), remapindex_16) when _T_2847 : connect remapVecData[16], Queue32_UInt8_37.io.deq.bits connect remapVecValids[16], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[16] node _T_2848 = eq(UInt<3>(0h6), remapindex_16) when _T_2848 : connect remapVecData[16], Queue32_UInt8_38.io.deq.bits connect remapVecValids[16], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[16] node _T_2849 = eq(UInt<3>(0h7), remapindex_16) when _T_2849 : connect remapVecData[16], Queue32_UInt8_39.io.deq.bits connect remapVecValids[16], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[16] node _T_2850 = eq(UInt<4>(0h8), remapindex_16) when _T_2850 : connect remapVecData[16], Queue32_UInt8_40.io.deq.bits connect remapVecValids[16], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[16] node _T_2851 = eq(UInt<4>(0h9), remapindex_16) when _T_2851 : connect remapVecData[16], Queue32_UInt8_41.io.deq.bits connect remapVecValids[16], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[16] node _T_2852 = eq(UInt<4>(0ha), remapindex_16) when _T_2852 : connect remapVecData[16], Queue32_UInt8_42.io.deq.bits connect remapVecValids[16], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[16] node _T_2853 = eq(UInt<4>(0hb), remapindex_16) when _T_2853 : connect remapVecData[16], Queue32_UInt8_43.io.deq.bits connect remapVecValids[16], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[16] node _T_2854 = eq(UInt<4>(0hc), remapindex_16) when _T_2854 : connect remapVecData[16], Queue32_UInt8_44.io.deq.bits connect remapVecValids[16], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[16] node _T_2855 = eq(UInt<4>(0hd), remapindex_16) when _T_2855 : connect remapVecData[16], Queue32_UInt8_45.io.deq.bits connect remapVecValids[16], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[16] node _T_2856 = eq(UInt<4>(0he), remapindex_16) when _T_2856 : connect remapVecData[16], Queue32_UInt8_46.io.deq.bits connect remapVecValids[16], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[16] node _T_2857 = eq(UInt<4>(0hf), remapindex_16) when _T_2857 : connect remapVecData[16], Queue32_UInt8_47.io.deq.bits connect remapVecValids[16], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[16] node _T_2858 = eq(UInt<5>(0h10), remapindex_16) when _T_2858 : connect remapVecData[16], Queue32_UInt8_48.io.deq.bits connect remapVecValids[16], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[16] node _T_2859 = eq(UInt<5>(0h11), remapindex_16) when _T_2859 : connect remapVecData[16], Queue32_UInt8_49.io.deq.bits connect remapVecValids[16], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[16] node _T_2860 = eq(UInt<5>(0h12), remapindex_16) when _T_2860 : connect remapVecData[16], Queue32_UInt8_50.io.deq.bits connect remapVecValids[16], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[16] node _T_2861 = eq(UInt<5>(0h13), remapindex_16) when _T_2861 : connect remapVecData[16], Queue32_UInt8_51.io.deq.bits connect remapVecValids[16], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[16] node _T_2862 = eq(UInt<5>(0h14), remapindex_16) when _T_2862 : connect remapVecData[16], Queue32_UInt8_52.io.deq.bits connect remapVecValids[16], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[16] node _T_2863 = eq(UInt<5>(0h15), remapindex_16) when _T_2863 : connect remapVecData[16], Queue32_UInt8_53.io.deq.bits connect remapVecValids[16], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[16] node _T_2864 = eq(UInt<5>(0h16), remapindex_16) when _T_2864 : connect remapVecData[16], Queue32_UInt8_54.io.deq.bits connect remapVecValids[16], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[16] node _T_2865 = eq(UInt<5>(0h17), remapindex_16) when _T_2865 : connect remapVecData[16], Queue32_UInt8_55.io.deq.bits connect remapVecValids[16], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[16] node _T_2866 = eq(UInt<5>(0h18), remapindex_16) when _T_2866 : connect remapVecData[16], Queue32_UInt8_56.io.deq.bits connect remapVecValids[16], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[16] node _T_2867 = eq(UInt<5>(0h19), remapindex_16) when _T_2867 : connect remapVecData[16], Queue32_UInt8_57.io.deq.bits connect remapVecValids[16], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[16] node _T_2868 = eq(UInt<5>(0h1a), remapindex_16) when _T_2868 : connect remapVecData[16], Queue32_UInt8_58.io.deq.bits connect remapVecValids[16], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[16] node _T_2869 = eq(UInt<5>(0h1b), remapindex_16) when _T_2869 : connect remapVecData[16], Queue32_UInt8_59.io.deq.bits connect remapVecValids[16], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[16] node _T_2870 = eq(UInt<5>(0h1c), remapindex_16) when _T_2870 : connect remapVecData[16], Queue32_UInt8_60.io.deq.bits connect remapVecValids[16], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[16] node _T_2871 = eq(UInt<5>(0h1d), remapindex_16) when _T_2871 : connect remapVecData[16], Queue32_UInt8_61.io.deq.bits connect remapVecValids[16], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[16] node _T_2872 = eq(UInt<5>(0h1e), remapindex_16) when _T_2872 : connect remapVecData[16], Queue32_UInt8_62.io.deq.bits connect remapVecValids[16], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[16] node _T_2873 = eq(UInt<5>(0h1f), remapindex_16) when _T_2873 : connect remapVecData[16], Queue32_UInt8_63.io.deq.bits connect remapVecValids[16], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[16] node _remapindex_T_17 = add(UInt<5>(0h11), read_start_index) node remapindex_17 = rem(_remapindex_T_17, UInt<6>(0h20)) node _T_2874 = eq(UInt<1>(0h0), remapindex_17) when _T_2874 : connect remapVecData[17], Queue32_UInt8_32.io.deq.bits connect remapVecValids[17], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[17] node _T_2875 = eq(UInt<1>(0h1), remapindex_17) when _T_2875 : connect remapVecData[17], Queue32_UInt8_33.io.deq.bits connect remapVecValids[17], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[17] node _T_2876 = eq(UInt<2>(0h2), remapindex_17) when _T_2876 : connect remapVecData[17], Queue32_UInt8_34.io.deq.bits connect remapVecValids[17], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[17] node _T_2877 = eq(UInt<2>(0h3), remapindex_17) when _T_2877 : connect remapVecData[17], Queue32_UInt8_35.io.deq.bits connect remapVecValids[17], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[17] node _T_2878 = eq(UInt<3>(0h4), remapindex_17) when _T_2878 : connect remapVecData[17], Queue32_UInt8_36.io.deq.bits connect remapVecValids[17], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[17] node _T_2879 = eq(UInt<3>(0h5), remapindex_17) when _T_2879 : connect remapVecData[17], Queue32_UInt8_37.io.deq.bits connect remapVecValids[17], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[17] node _T_2880 = eq(UInt<3>(0h6), remapindex_17) when _T_2880 : connect remapVecData[17], Queue32_UInt8_38.io.deq.bits connect remapVecValids[17], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[17] node _T_2881 = eq(UInt<3>(0h7), remapindex_17) when _T_2881 : connect remapVecData[17], Queue32_UInt8_39.io.deq.bits connect remapVecValids[17], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[17] node _T_2882 = eq(UInt<4>(0h8), remapindex_17) when _T_2882 : connect remapVecData[17], Queue32_UInt8_40.io.deq.bits connect remapVecValids[17], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[17] node _T_2883 = eq(UInt<4>(0h9), remapindex_17) when _T_2883 : connect remapVecData[17], Queue32_UInt8_41.io.deq.bits connect remapVecValids[17], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[17] node _T_2884 = eq(UInt<4>(0ha), remapindex_17) when _T_2884 : connect remapVecData[17], Queue32_UInt8_42.io.deq.bits connect remapVecValids[17], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[17] node _T_2885 = eq(UInt<4>(0hb), remapindex_17) when _T_2885 : connect remapVecData[17], Queue32_UInt8_43.io.deq.bits connect remapVecValids[17], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[17] node _T_2886 = eq(UInt<4>(0hc), remapindex_17) when _T_2886 : connect remapVecData[17], Queue32_UInt8_44.io.deq.bits connect remapVecValids[17], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[17] node _T_2887 = eq(UInt<4>(0hd), remapindex_17) when _T_2887 : connect remapVecData[17], Queue32_UInt8_45.io.deq.bits connect remapVecValids[17], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[17] node _T_2888 = eq(UInt<4>(0he), remapindex_17) when _T_2888 : connect remapVecData[17], Queue32_UInt8_46.io.deq.bits connect remapVecValids[17], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[17] node _T_2889 = eq(UInt<4>(0hf), remapindex_17) when _T_2889 : connect remapVecData[17], Queue32_UInt8_47.io.deq.bits connect remapVecValids[17], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[17] node _T_2890 = eq(UInt<5>(0h10), remapindex_17) when _T_2890 : connect remapVecData[17], Queue32_UInt8_48.io.deq.bits connect remapVecValids[17], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[17] node _T_2891 = eq(UInt<5>(0h11), remapindex_17) when _T_2891 : connect remapVecData[17], Queue32_UInt8_49.io.deq.bits connect remapVecValids[17], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[17] node _T_2892 = eq(UInt<5>(0h12), remapindex_17) when _T_2892 : connect remapVecData[17], Queue32_UInt8_50.io.deq.bits connect remapVecValids[17], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[17] node _T_2893 = eq(UInt<5>(0h13), remapindex_17) when _T_2893 : connect remapVecData[17], Queue32_UInt8_51.io.deq.bits connect remapVecValids[17], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[17] node _T_2894 = eq(UInt<5>(0h14), remapindex_17) when _T_2894 : connect remapVecData[17], Queue32_UInt8_52.io.deq.bits connect remapVecValids[17], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[17] node _T_2895 = eq(UInt<5>(0h15), remapindex_17) when _T_2895 : connect remapVecData[17], Queue32_UInt8_53.io.deq.bits connect remapVecValids[17], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[17] node _T_2896 = eq(UInt<5>(0h16), remapindex_17) when _T_2896 : connect remapVecData[17], Queue32_UInt8_54.io.deq.bits connect remapVecValids[17], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[17] node _T_2897 = eq(UInt<5>(0h17), remapindex_17) when _T_2897 : connect remapVecData[17], Queue32_UInt8_55.io.deq.bits connect remapVecValids[17], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[17] node _T_2898 = eq(UInt<5>(0h18), remapindex_17) when _T_2898 : connect remapVecData[17], Queue32_UInt8_56.io.deq.bits connect remapVecValids[17], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[17] node _T_2899 = eq(UInt<5>(0h19), remapindex_17) when _T_2899 : connect remapVecData[17], Queue32_UInt8_57.io.deq.bits connect remapVecValids[17], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[17] node _T_2900 = eq(UInt<5>(0h1a), remapindex_17) when _T_2900 : connect remapVecData[17], Queue32_UInt8_58.io.deq.bits connect remapVecValids[17], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[17] node _T_2901 = eq(UInt<5>(0h1b), remapindex_17) when _T_2901 : connect remapVecData[17], Queue32_UInt8_59.io.deq.bits connect remapVecValids[17], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[17] node _T_2902 = eq(UInt<5>(0h1c), remapindex_17) when _T_2902 : connect remapVecData[17], Queue32_UInt8_60.io.deq.bits connect remapVecValids[17], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[17] node _T_2903 = eq(UInt<5>(0h1d), remapindex_17) when _T_2903 : connect remapVecData[17], Queue32_UInt8_61.io.deq.bits connect remapVecValids[17], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[17] node _T_2904 = eq(UInt<5>(0h1e), remapindex_17) when _T_2904 : connect remapVecData[17], Queue32_UInt8_62.io.deq.bits connect remapVecValids[17], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[17] node _T_2905 = eq(UInt<5>(0h1f), remapindex_17) when _T_2905 : connect remapVecData[17], Queue32_UInt8_63.io.deq.bits connect remapVecValids[17], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[17] node _remapindex_T_18 = add(UInt<5>(0h12), read_start_index) node remapindex_18 = rem(_remapindex_T_18, UInt<6>(0h20)) node _T_2906 = eq(UInt<1>(0h0), remapindex_18) when _T_2906 : connect remapVecData[18], Queue32_UInt8_32.io.deq.bits connect remapVecValids[18], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[18] node _T_2907 = eq(UInt<1>(0h1), remapindex_18) when _T_2907 : connect remapVecData[18], Queue32_UInt8_33.io.deq.bits connect remapVecValids[18], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[18] node _T_2908 = eq(UInt<2>(0h2), remapindex_18) when _T_2908 : connect remapVecData[18], Queue32_UInt8_34.io.deq.bits connect remapVecValids[18], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[18] node _T_2909 = eq(UInt<2>(0h3), remapindex_18) when _T_2909 : connect remapVecData[18], Queue32_UInt8_35.io.deq.bits connect remapVecValids[18], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[18] node _T_2910 = eq(UInt<3>(0h4), remapindex_18) when _T_2910 : connect remapVecData[18], Queue32_UInt8_36.io.deq.bits connect remapVecValids[18], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[18] node _T_2911 = eq(UInt<3>(0h5), remapindex_18) when _T_2911 : connect remapVecData[18], Queue32_UInt8_37.io.deq.bits connect remapVecValids[18], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[18] node _T_2912 = eq(UInt<3>(0h6), remapindex_18) when _T_2912 : connect remapVecData[18], Queue32_UInt8_38.io.deq.bits connect remapVecValids[18], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[18] node _T_2913 = eq(UInt<3>(0h7), remapindex_18) when _T_2913 : connect remapVecData[18], Queue32_UInt8_39.io.deq.bits connect remapVecValids[18], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[18] node _T_2914 = eq(UInt<4>(0h8), remapindex_18) when _T_2914 : connect remapVecData[18], Queue32_UInt8_40.io.deq.bits connect remapVecValids[18], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[18] node _T_2915 = eq(UInt<4>(0h9), remapindex_18) when _T_2915 : connect remapVecData[18], Queue32_UInt8_41.io.deq.bits connect remapVecValids[18], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[18] node _T_2916 = eq(UInt<4>(0ha), remapindex_18) when _T_2916 : connect remapVecData[18], Queue32_UInt8_42.io.deq.bits connect remapVecValids[18], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[18] node _T_2917 = eq(UInt<4>(0hb), remapindex_18) when _T_2917 : connect remapVecData[18], Queue32_UInt8_43.io.deq.bits connect remapVecValids[18], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[18] node _T_2918 = eq(UInt<4>(0hc), remapindex_18) when _T_2918 : connect remapVecData[18], Queue32_UInt8_44.io.deq.bits connect remapVecValids[18], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[18] node _T_2919 = eq(UInt<4>(0hd), remapindex_18) when _T_2919 : connect remapVecData[18], Queue32_UInt8_45.io.deq.bits connect remapVecValids[18], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[18] node _T_2920 = eq(UInt<4>(0he), remapindex_18) when _T_2920 : connect remapVecData[18], Queue32_UInt8_46.io.deq.bits connect remapVecValids[18], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[18] node _T_2921 = eq(UInt<4>(0hf), remapindex_18) when _T_2921 : connect remapVecData[18], Queue32_UInt8_47.io.deq.bits connect remapVecValids[18], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[18] node _T_2922 = eq(UInt<5>(0h10), remapindex_18) when _T_2922 : connect remapVecData[18], Queue32_UInt8_48.io.deq.bits connect remapVecValids[18], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[18] node _T_2923 = eq(UInt<5>(0h11), remapindex_18) when _T_2923 : connect remapVecData[18], Queue32_UInt8_49.io.deq.bits connect remapVecValids[18], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[18] node _T_2924 = eq(UInt<5>(0h12), remapindex_18) when _T_2924 : connect remapVecData[18], Queue32_UInt8_50.io.deq.bits connect remapVecValids[18], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[18] node _T_2925 = eq(UInt<5>(0h13), remapindex_18) when _T_2925 : connect remapVecData[18], Queue32_UInt8_51.io.deq.bits connect remapVecValids[18], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[18] node _T_2926 = eq(UInt<5>(0h14), remapindex_18) when _T_2926 : connect remapVecData[18], Queue32_UInt8_52.io.deq.bits connect remapVecValids[18], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[18] node _T_2927 = eq(UInt<5>(0h15), remapindex_18) when _T_2927 : connect remapVecData[18], Queue32_UInt8_53.io.deq.bits connect remapVecValids[18], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[18] node _T_2928 = eq(UInt<5>(0h16), remapindex_18) when _T_2928 : connect remapVecData[18], Queue32_UInt8_54.io.deq.bits connect remapVecValids[18], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[18] node _T_2929 = eq(UInt<5>(0h17), remapindex_18) when _T_2929 : connect remapVecData[18], Queue32_UInt8_55.io.deq.bits connect remapVecValids[18], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[18] node _T_2930 = eq(UInt<5>(0h18), remapindex_18) when _T_2930 : connect remapVecData[18], Queue32_UInt8_56.io.deq.bits connect remapVecValids[18], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[18] node _T_2931 = eq(UInt<5>(0h19), remapindex_18) when _T_2931 : connect remapVecData[18], Queue32_UInt8_57.io.deq.bits connect remapVecValids[18], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[18] node _T_2932 = eq(UInt<5>(0h1a), remapindex_18) when _T_2932 : connect remapVecData[18], Queue32_UInt8_58.io.deq.bits connect remapVecValids[18], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[18] node _T_2933 = eq(UInt<5>(0h1b), remapindex_18) when _T_2933 : connect remapVecData[18], Queue32_UInt8_59.io.deq.bits connect remapVecValids[18], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[18] node _T_2934 = eq(UInt<5>(0h1c), remapindex_18) when _T_2934 : connect remapVecData[18], Queue32_UInt8_60.io.deq.bits connect remapVecValids[18], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[18] node _T_2935 = eq(UInt<5>(0h1d), remapindex_18) when _T_2935 : connect remapVecData[18], Queue32_UInt8_61.io.deq.bits connect remapVecValids[18], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[18] node _T_2936 = eq(UInt<5>(0h1e), remapindex_18) when _T_2936 : connect remapVecData[18], Queue32_UInt8_62.io.deq.bits connect remapVecValids[18], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[18] node _T_2937 = eq(UInt<5>(0h1f), remapindex_18) when _T_2937 : connect remapVecData[18], Queue32_UInt8_63.io.deq.bits connect remapVecValids[18], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[18] node _remapindex_T_19 = add(UInt<5>(0h13), read_start_index) node remapindex_19 = rem(_remapindex_T_19, UInt<6>(0h20)) node _T_2938 = eq(UInt<1>(0h0), remapindex_19) when _T_2938 : connect remapVecData[19], Queue32_UInt8_32.io.deq.bits connect remapVecValids[19], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[19] node _T_2939 = eq(UInt<1>(0h1), remapindex_19) when _T_2939 : connect remapVecData[19], Queue32_UInt8_33.io.deq.bits connect remapVecValids[19], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[19] node _T_2940 = eq(UInt<2>(0h2), remapindex_19) when _T_2940 : connect remapVecData[19], Queue32_UInt8_34.io.deq.bits connect remapVecValids[19], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[19] node _T_2941 = eq(UInt<2>(0h3), remapindex_19) when _T_2941 : connect remapVecData[19], Queue32_UInt8_35.io.deq.bits connect remapVecValids[19], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[19] node _T_2942 = eq(UInt<3>(0h4), remapindex_19) when _T_2942 : connect remapVecData[19], Queue32_UInt8_36.io.deq.bits connect remapVecValids[19], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[19] node _T_2943 = eq(UInt<3>(0h5), remapindex_19) when _T_2943 : connect remapVecData[19], Queue32_UInt8_37.io.deq.bits connect remapVecValids[19], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[19] node _T_2944 = eq(UInt<3>(0h6), remapindex_19) when _T_2944 : connect remapVecData[19], Queue32_UInt8_38.io.deq.bits connect remapVecValids[19], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[19] node _T_2945 = eq(UInt<3>(0h7), remapindex_19) when _T_2945 : connect remapVecData[19], Queue32_UInt8_39.io.deq.bits connect remapVecValids[19], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[19] node _T_2946 = eq(UInt<4>(0h8), remapindex_19) when _T_2946 : connect remapVecData[19], Queue32_UInt8_40.io.deq.bits connect remapVecValids[19], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[19] node _T_2947 = eq(UInt<4>(0h9), remapindex_19) when _T_2947 : connect remapVecData[19], Queue32_UInt8_41.io.deq.bits connect remapVecValids[19], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[19] node _T_2948 = eq(UInt<4>(0ha), remapindex_19) when _T_2948 : connect remapVecData[19], Queue32_UInt8_42.io.deq.bits connect remapVecValids[19], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[19] node _T_2949 = eq(UInt<4>(0hb), remapindex_19) when _T_2949 : connect remapVecData[19], Queue32_UInt8_43.io.deq.bits connect remapVecValids[19], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[19] node _T_2950 = eq(UInt<4>(0hc), remapindex_19) when _T_2950 : connect remapVecData[19], Queue32_UInt8_44.io.deq.bits connect remapVecValids[19], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[19] node _T_2951 = eq(UInt<4>(0hd), remapindex_19) when _T_2951 : connect remapVecData[19], Queue32_UInt8_45.io.deq.bits connect remapVecValids[19], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[19] node _T_2952 = eq(UInt<4>(0he), remapindex_19) when _T_2952 : connect remapVecData[19], Queue32_UInt8_46.io.deq.bits connect remapVecValids[19], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[19] node _T_2953 = eq(UInt<4>(0hf), remapindex_19) when _T_2953 : connect remapVecData[19], Queue32_UInt8_47.io.deq.bits connect remapVecValids[19], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[19] node _T_2954 = eq(UInt<5>(0h10), remapindex_19) when _T_2954 : connect remapVecData[19], Queue32_UInt8_48.io.deq.bits connect remapVecValids[19], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[19] node _T_2955 = eq(UInt<5>(0h11), remapindex_19) when _T_2955 : connect remapVecData[19], Queue32_UInt8_49.io.deq.bits connect remapVecValids[19], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[19] node _T_2956 = eq(UInt<5>(0h12), remapindex_19) when _T_2956 : connect remapVecData[19], Queue32_UInt8_50.io.deq.bits connect remapVecValids[19], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[19] node _T_2957 = eq(UInt<5>(0h13), remapindex_19) when _T_2957 : connect remapVecData[19], Queue32_UInt8_51.io.deq.bits connect remapVecValids[19], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[19] node _T_2958 = eq(UInt<5>(0h14), remapindex_19) when _T_2958 : connect remapVecData[19], Queue32_UInt8_52.io.deq.bits connect remapVecValids[19], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[19] node _T_2959 = eq(UInt<5>(0h15), remapindex_19) when _T_2959 : connect remapVecData[19], Queue32_UInt8_53.io.deq.bits connect remapVecValids[19], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[19] node _T_2960 = eq(UInt<5>(0h16), remapindex_19) when _T_2960 : connect remapVecData[19], Queue32_UInt8_54.io.deq.bits connect remapVecValids[19], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[19] node _T_2961 = eq(UInt<5>(0h17), remapindex_19) when _T_2961 : connect remapVecData[19], Queue32_UInt8_55.io.deq.bits connect remapVecValids[19], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[19] node _T_2962 = eq(UInt<5>(0h18), remapindex_19) when _T_2962 : connect remapVecData[19], Queue32_UInt8_56.io.deq.bits connect remapVecValids[19], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[19] node _T_2963 = eq(UInt<5>(0h19), remapindex_19) when _T_2963 : connect remapVecData[19], Queue32_UInt8_57.io.deq.bits connect remapVecValids[19], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[19] node _T_2964 = eq(UInt<5>(0h1a), remapindex_19) when _T_2964 : connect remapVecData[19], Queue32_UInt8_58.io.deq.bits connect remapVecValids[19], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[19] node _T_2965 = eq(UInt<5>(0h1b), remapindex_19) when _T_2965 : connect remapVecData[19], Queue32_UInt8_59.io.deq.bits connect remapVecValids[19], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[19] node _T_2966 = eq(UInt<5>(0h1c), remapindex_19) when _T_2966 : connect remapVecData[19], Queue32_UInt8_60.io.deq.bits connect remapVecValids[19], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[19] node _T_2967 = eq(UInt<5>(0h1d), remapindex_19) when _T_2967 : connect remapVecData[19], Queue32_UInt8_61.io.deq.bits connect remapVecValids[19], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[19] node _T_2968 = eq(UInt<5>(0h1e), remapindex_19) when _T_2968 : connect remapVecData[19], Queue32_UInt8_62.io.deq.bits connect remapVecValids[19], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[19] node _T_2969 = eq(UInt<5>(0h1f), remapindex_19) when _T_2969 : connect remapVecData[19], Queue32_UInt8_63.io.deq.bits connect remapVecValids[19], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[19] node _remapindex_T_20 = add(UInt<5>(0h14), read_start_index) node remapindex_20 = rem(_remapindex_T_20, UInt<6>(0h20)) node _T_2970 = eq(UInt<1>(0h0), remapindex_20) when _T_2970 : connect remapVecData[20], Queue32_UInt8_32.io.deq.bits connect remapVecValids[20], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[20] node _T_2971 = eq(UInt<1>(0h1), remapindex_20) when _T_2971 : connect remapVecData[20], Queue32_UInt8_33.io.deq.bits connect remapVecValids[20], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[20] node _T_2972 = eq(UInt<2>(0h2), remapindex_20) when _T_2972 : connect remapVecData[20], Queue32_UInt8_34.io.deq.bits connect remapVecValids[20], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[20] node _T_2973 = eq(UInt<2>(0h3), remapindex_20) when _T_2973 : connect remapVecData[20], Queue32_UInt8_35.io.deq.bits connect remapVecValids[20], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[20] node _T_2974 = eq(UInt<3>(0h4), remapindex_20) when _T_2974 : connect remapVecData[20], Queue32_UInt8_36.io.deq.bits connect remapVecValids[20], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[20] node _T_2975 = eq(UInt<3>(0h5), remapindex_20) when _T_2975 : connect remapVecData[20], Queue32_UInt8_37.io.deq.bits connect remapVecValids[20], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[20] node _T_2976 = eq(UInt<3>(0h6), remapindex_20) when _T_2976 : connect remapVecData[20], Queue32_UInt8_38.io.deq.bits connect remapVecValids[20], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[20] node _T_2977 = eq(UInt<3>(0h7), remapindex_20) when _T_2977 : connect remapVecData[20], Queue32_UInt8_39.io.deq.bits connect remapVecValids[20], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[20] node _T_2978 = eq(UInt<4>(0h8), remapindex_20) when _T_2978 : connect remapVecData[20], Queue32_UInt8_40.io.deq.bits connect remapVecValids[20], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[20] node _T_2979 = eq(UInt<4>(0h9), remapindex_20) when _T_2979 : connect remapVecData[20], Queue32_UInt8_41.io.deq.bits connect remapVecValids[20], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[20] node _T_2980 = eq(UInt<4>(0ha), remapindex_20) when _T_2980 : connect remapVecData[20], Queue32_UInt8_42.io.deq.bits connect remapVecValids[20], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[20] node _T_2981 = eq(UInt<4>(0hb), remapindex_20) when _T_2981 : connect remapVecData[20], Queue32_UInt8_43.io.deq.bits connect remapVecValids[20], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[20] node _T_2982 = eq(UInt<4>(0hc), remapindex_20) when _T_2982 : connect remapVecData[20], Queue32_UInt8_44.io.deq.bits connect remapVecValids[20], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[20] node _T_2983 = eq(UInt<4>(0hd), remapindex_20) when _T_2983 : connect remapVecData[20], Queue32_UInt8_45.io.deq.bits connect remapVecValids[20], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[20] node _T_2984 = eq(UInt<4>(0he), remapindex_20) when _T_2984 : connect remapVecData[20], Queue32_UInt8_46.io.deq.bits connect remapVecValids[20], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[20] node _T_2985 = eq(UInt<4>(0hf), remapindex_20) when _T_2985 : connect remapVecData[20], Queue32_UInt8_47.io.deq.bits connect remapVecValids[20], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[20] node _T_2986 = eq(UInt<5>(0h10), remapindex_20) when _T_2986 : connect remapVecData[20], Queue32_UInt8_48.io.deq.bits connect remapVecValids[20], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[20] node _T_2987 = eq(UInt<5>(0h11), remapindex_20) when _T_2987 : connect remapVecData[20], Queue32_UInt8_49.io.deq.bits connect remapVecValids[20], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[20] node _T_2988 = eq(UInt<5>(0h12), remapindex_20) when _T_2988 : connect remapVecData[20], Queue32_UInt8_50.io.deq.bits connect remapVecValids[20], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[20] node _T_2989 = eq(UInt<5>(0h13), remapindex_20) when _T_2989 : connect remapVecData[20], Queue32_UInt8_51.io.deq.bits connect remapVecValids[20], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[20] node _T_2990 = eq(UInt<5>(0h14), remapindex_20) when _T_2990 : connect remapVecData[20], Queue32_UInt8_52.io.deq.bits connect remapVecValids[20], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[20] node _T_2991 = eq(UInt<5>(0h15), remapindex_20) when _T_2991 : connect remapVecData[20], Queue32_UInt8_53.io.deq.bits connect remapVecValids[20], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[20] node _T_2992 = eq(UInt<5>(0h16), remapindex_20) when _T_2992 : connect remapVecData[20], Queue32_UInt8_54.io.deq.bits connect remapVecValids[20], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[20] node _T_2993 = eq(UInt<5>(0h17), remapindex_20) when _T_2993 : connect remapVecData[20], Queue32_UInt8_55.io.deq.bits connect remapVecValids[20], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[20] node _T_2994 = eq(UInt<5>(0h18), remapindex_20) when _T_2994 : connect remapVecData[20], Queue32_UInt8_56.io.deq.bits connect remapVecValids[20], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[20] node _T_2995 = eq(UInt<5>(0h19), remapindex_20) when _T_2995 : connect remapVecData[20], Queue32_UInt8_57.io.deq.bits connect remapVecValids[20], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[20] node _T_2996 = eq(UInt<5>(0h1a), remapindex_20) when _T_2996 : connect remapVecData[20], Queue32_UInt8_58.io.deq.bits connect remapVecValids[20], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[20] node _T_2997 = eq(UInt<5>(0h1b), remapindex_20) when _T_2997 : connect remapVecData[20], Queue32_UInt8_59.io.deq.bits connect remapVecValids[20], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[20] node _T_2998 = eq(UInt<5>(0h1c), remapindex_20) when _T_2998 : connect remapVecData[20], Queue32_UInt8_60.io.deq.bits connect remapVecValids[20], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[20] node _T_2999 = eq(UInt<5>(0h1d), remapindex_20) when _T_2999 : connect remapVecData[20], Queue32_UInt8_61.io.deq.bits connect remapVecValids[20], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[20] node _T_3000 = eq(UInt<5>(0h1e), remapindex_20) when _T_3000 : connect remapVecData[20], Queue32_UInt8_62.io.deq.bits connect remapVecValids[20], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[20] node _T_3001 = eq(UInt<5>(0h1f), remapindex_20) when _T_3001 : connect remapVecData[20], Queue32_UInt8_63.io.deq.bits connect remapVecValids[20], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[20] node _remapindex_T_21 = add(UInt<5>(0h15), read_start_index) node remapindex_21 = rem(_remapindex_T_21, UInt<6>(0h20)) node _T_3002 = eq(UInt<1>(0h0), remapindex_21) when _T_3002 : connect remapVecData[21], Queue32_UInt8_32.io.deq.bits connect remapVecValids[21], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[21] node _T_3003 = eq(UInt<1>(0h1), remapindex_21) when _T_3003 : connect remapVecData[21], Queue32_UInt8_33.io.deq.bits connect remapVecValids[21], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[21] node _T_3004 = eq(UInt<2>(0h2), remapindex_21) when _T_3004 : connect remapVecData[21], Queue32_UInt8_34.io.deq.bits connect remapVecValids[21], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[21] node _T_3005 = eq(UInt<2>(0h3), remapindex_21) when _T_3005 : connect remapVecData[21], Queue32_UInt8_35.io.deq.bits connect remapVecValids[21], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[21] node _T_3006 = eq(UInt<3>(0h4), remapindex_21) when _T_3006 : connect remapVecData[21], Queue32_UInt8_36.io.deq.bits connect remapVecValids[21], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[21] node _T_3007 = eq(UInt<3>(0h5), remapindex_21) when _T_3007 : connect remapVecData[21], Queue32_UInt8_37.io.deq.bits connect remapVecValids[21], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[21] node _T_3008 = eq(UInt<3>(0h6), remapindex_21) when _T_3008 : connect remapVecData[21], Queue32_UInt8_38.io.deq.bits connect remapVecValids[21], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[21] node _T_3009 = eq(UInt<3>(0h7), remapindex_21) when _T_3009 : connect remapVecData[21], Queue32_UInt8_39.io.deq.bits connect remapVecValids[21], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[21] node _T_3010 = eq(UInt<4>(0h8), remapindex_21) when _T_3010 : connect remapVecData[21], Queue32_UInt8_40.io.deq.bits connect remapVecValids[21], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[21] node _T_3011 = eq(UInt<4>(0h9), remapindex_21) when _T_3011 : connect remapVecData[21], Queue32_UInt8_41.io.deq.bits connect remapVecValids[21], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[21] node _T_3012 = eq(UInt<4>(0ha), remapindex_21) when _T_3012 : connect remapVecData[21], Queue32_UInt8_42.io.deq.bits connect remapVecValids[21], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[21] node _T_3013 = eq(UInt<4>(0hb), remapindex_21) when _T_3013 : connect remapVecData[21], Queue32_UInt8_43.io.deq.bits connect remapVecValids[21], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[21] node _T_3014 = eq(UInt<4>(0hc), remapindex_21) when _T_3014 : connect remapVecData[21], Queue32_UInt8_44.io.deq.bits connect remapVecValids[21], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[21] node _T_3015 = eq(UInt<4>(0hd), remapindex_21) when _T_3015 : connect remapVecData[21], Queue32_UInt8_45.io.deq.bits connect remapVecValids[21], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[21] node _T_3016 = eq(UInt<4>(0he), remapindex_21) when _T_3016 : connect remapVecData[21], Queue32_UInt8_46.io.deq.bits connect remapVecValids[21], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[21] node _T_3017 = eq(UInt<4>(0hf), remapindex_21) when _T_3017 : connect remapVecData[21], Queue32_UInt8_47.io.deq.bits connect remapVecValids[21], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[21] node _T_3018 = eq(UInt<5>(0h10), remapindex_21) when _T_3018 : connect remapVecData[21], Queue32_UInt8_48.io.deq.bits connect remapVecValids[21], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[21] node _T_3019 = eq(UInt<5>(0h11), remapindex_21) when _T_3019 : connect remapVecData[21], Queue32_UInt8_49.io.deq.bits connect remapVecValids[21], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[21] node _T_3020 = eq(UInt<5>(0h12), remapindex_21) when _T_3020 : connect remapVecData[21], Queue32_UInt8_50.io.deq.bits connect remapVecValids[21], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[21] node _T_3021 = eq(UInt<5>(0h13), remapindex_21) when _T_3021 : connect remapVecData[21], Queue32_UInt8_51.io.deq.bits connect remapVecValids[21], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[21] node _T_3022 = eq(UInt<5>(0h14), remapindex_21) when _T_3022 : connect remapVecData[21], Queue32_UInt8_52.io.deq.bits connect remapVecValids[21], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[21] node _T_3023 = eq(UInt<5>(0h15), remapindex_21) when _T_3023 : connect remapVecData[21], Queue32_UInt8_53.io.deq.bits connect remapVecValids[21], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[21] node _T_3024 = eq(UInt<5>(0h16), remapindex_21) when _T_3024 : connect remapVecData[21], Queue32_UInt8_54.io.deq.bits connect remapVecValids[21], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[21] node _T_3025 = eq(UInt<5>(0h17), remapindex_21) when _T_3025 : connect remapVecData[21], Queue32_UInt8_55.io.deq.bits connect remapVecValids[21], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[21] node _T_3026 = eq(UInt<5>(0h18), remapindex_21) when _T_3026 : connect remapVecData[21], Queue32_UInt8_56.io.deq.bits connect remapVecValids[21], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[21] node _T_3027 = eq(UInt<5>(0h19), remapindex_21) when _T_3027 : connect remapVecData[21], Queue32_UInt8_57.io.deq.bits connect remapVecValids[21], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[21] node _T_3028 = eq(UInt<5>(0h1a), remapindex_21) when _T_3028 : connect remapVecData[21], Queue32_UInt8_58.io.deq.bits connect remapVecValids[21], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[21] node _T_3029 = eq(UInt<5>(0h1b), remapindex_21) when _T_3029 : connect remapVecData[21], Queue32_UInt8_59.io.deq.bits connect remapVecValids[21], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[21] node _T_3030 = eq(UInt<5>(0h1c), remapindex_21) when _T_3030 : connect remapVecData[21], Queue32_UInt8_60.io.deq.bits connect remapVecValids[21], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[21] node _T_3031 = eq(UInt<5>(0h1d), remapindex_21) when _T_3031 : connect remapVecData[21], Queue32_UInt8_61.io.deq.bits connect remapVecValids[21], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[21] node _T_3032 = eq(UInt<5>(0h1e), remapindex_21) when _T_3032 : connect remapVecData[21], Queue32_UInt8_62.io.deq.bits connect remapVecValids[21], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[21] node _T_3033 = eq(UInt<5>(0h1f), remapindex_21) when _T_3033 : connect remapVecData[21], Queue32_UInt8_63.io.deq.bits connect remapVecValids[21], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[21] node _remapindex_T_22 = add(UInt<5>(0h16), read_start_index) node remapindex_22 = rem(_remapindex_T_22, UInt<6>(0h20)) node _T_3034 = eq(UInt<1>(0h0), remapindex_22) when _T_3034 : connect remapVecData[22], Queue32_UInt8_32.io.deq.bits connect remapVecValids[22], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[22] node _T_3035 = eq(UInt<1>(0h1), remapindex_22) when _T_3035 : connect remapVecData[22], Queue32_UInt8_33.io.deq.bits connect remapVecValids[22], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[22] node _T_3036 = eq(UInt<2>(0h2), remapindex_22) when _T_3036 : connect remapVecData[22], Queue32_UInt8_34.io.deq.bits connect remapVecValids[22], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[22] node _T_3037 = eq(UInt<2>(0h3), remapindex_22) when _T_3037 : connect remapVecData[22], Queue32_UInt8_35.io.deq.bits connect remapVecValids[22], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[22] node _T_3038 = eq(UInt<3>(0h4), remapindex_22) when _T_3038 : connect remapVecData[22], Queue32_UInt8_36.io.deq.bits connect remapVecValids[22], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[22] node _T_3039 = eq(UInt<3>(0h5), remapindex_22) when _T_3039 : connect remapVecData[22], Queue32_UInt8_37.io.deq.bits connect remapVecValids[22], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[22] node _T_3040 = eq(UInt<3>(0h6), remapindex_22) when _T_3040 : connect remapVecData[22], Queue32_UInt8_38.io.deq.bits connect remapVecValids[22], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[22] node _T_3041 = eq(UInt<3>(0h7), remapindex_22) when _T_3041 : connect remapVecData[22], Queue32_UInt8_39.io.deq.bits connect remapVecValids[22], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[22] node _T_3042 = eq(UInt<4>(0h8), remapindex_22) when _T_3042 : connect remapVecData[22], Queue32_UInt8_40.io.deq.bits connect remapVecValids[22], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[22] node _T_3043 = eq(UInt<4>(0h9), remapindex_22) when _T_3043 : connect remapVecData[22], Queue32_UInt8_41.io.deq.bits connect remapVecValids[22], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[22] node _T_3044 = eq(UInt<4>(0ha), remapindex_22) when _T_3044 : connect remapVecData[22], Queue32_UInt8_42.io.deq.bits connect remapVecValids[22], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[22] node _T_3045 = eq(UInt<4>(0hb), remapindex_22) when _T_3045 : connect remapVecData[22], Queue32_UInt8_43.io.deq.bits connect remapVecValids[22], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[22] node _T_3046 = eq(UInt<4>(0hc), remapindex_22) when _T_3046 : connect remapVecData[22], Queue32_UInt8_44.io.deq.bits connect remapVecValids[22], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[22] node _T_3047 = eq(UInt<4>(0hd), remapindex_22) when _T_3047 : connect remapVecData[22], Queue32_UInt8_45.io.deq.bits connect remapVecValids[22], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[22] node _T_3048 = eq(UInt<4>(0he), remapindex_22) when _T_3048 : connect remapVecData[22], Queue32_UInt8_46.io.deq.bits connect remapVecValids[22], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[22] node _T_3049 = eq(UInt<4>(0hf), remapindex_22) when _T_3049 : connect remapVecData[22], Queue32_UInt8_47.io.deq.bits connect remapVecValids[22], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[22] node _T_3050 = eq(UInt<5>(0h10), remapindex_22) when _T_3050 : connect remapVecData[22], Queue32_UInt8_48.io.deq.bits connect remapVecValids[22], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[22] node _T_3051 = eq(UInt<5>(0h11), remapindex_22) when _T_3051 : connect remapVecData[22], Queue32_UInt8_49.io.deq.bits connect remapVecValids[22], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[22] node _T_3052 = eq(UInt<5>(0h12), remapindex_22) when _T_3052 : connect remapVecData[22], Queue32_UInt8_50.io.deq.bits connect remapVecValids[22], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[22] node _T_3053 = eq(UInt<5>(0h13), remapindex_22) when _T_3053 : connect remapVecData[22], Queue32_UInt8_51.io.deq.bits connect remapVecValids[22], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[22] node _T_3054 = eq(UInt<5>(0h14), remapindex_22) when _T_3054 : connect remapVecData[22], Queue32_UInt8_52.io.deq.bits connect remapVecValids[22], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[22] node _T_3055 = eq(UInt<5>(0h15), remapindex_22) when _T_3055 : connect remapVecData[22], Queue32_UInt8_53.io.deq.bits connect remapVecValids[22], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[22] node _T_3056 = eq(UInt<5>(0h16), remapindex_22) when _T_3056 : connect remapVecData[22], Queue32_UInt8_54.io.deq.bits connect remapVecValids[22], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[22] node _T_3057 = eq(UInt<5>(0h17), remapindex_22) when _T_3057 : connect remapVecData[22], Queue32_UInt8_55.io.deq.bits connect remapVecValids[22], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[22] node _T_3058 = eq(UInt<5>(0h18), remapindex_22) when _T_3058 : connect remapVecData[22], Queue32_UInt8_56.io.deq.bits connect remapVecValids[22], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[22] node _T_3059 = eq(UInt<5>(0h19), remapindex_22) when _T_3059 : connect remapVecData[22], Queue32_UInt8_57.io.deq.bits connect remapVecValids[22], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[22] node _T_3060 = eq(UInt<5>(0h1a), remapindex_22) when _T_3060 : connect remapVecData[22], Queue32_UInt8_58.io.deq.bits connect remapVecValids[22], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[22] node _T_3061 = eq(UInt<5>(0h1b), remapindex_22) when _T_3061 : connect remapVecData[22], Queue32_UInt8_59.io.deq.bits connect remapVecValids[22], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[22] node _T_3062 = eq(UInt<5>(0h1c), remapindex_22) when _T_3062 : connect remapVecData[22], Queue32_UInt8_60.io.deq.bits connect remapVecValids[22], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[22] node _T_3063 = eq(UInt<5>(0h1d), remapindex_22) when _T_3063 : connect remapVecData[22], Queue32_UInt8_61.io.deq.bits connect remapVecValids[22], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[22] node _T_3064 = eq(UInt<5>(0h1e), remapindex_22) when _T_3064 : connect remapVecData[22], Queue32_UInt8_62.io.deq.bits connect remapVecValids[22], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[22] node _T_3065 = eq(UInt<5>(0h1f), remapindex_22) when _T_3065 : connect remapVecData[22], Queue32_UInt8_63.io.deq.bits connect remapVecValids[22], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[22] node _remapindex_T_23 = add(UInt<5>(0h17), read_start_index) node remapindex_23 = rem(_remapindex_T_23, UInt<6>(0h20)) node _T_3066 = eq(UInt<1>(0h0), remapindex_23) when _T_3066 : connect remapVecData[23], Queue32_UInt8_32.io.deq.bits connect remapVecValids[23], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[23] node _T_3067 = eq(UInt<1>(0h1), remapindex_23) when _T_3067 : connect remapVecData[23], Queue32_UInt8_33.io.deq.bits connect remapVecValids[23], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[23] node _T_3068 = eq(UInt<2>(0h2), remapindex_23) when _T_3068 : connect remapVecData[23], Queue32_UInt8_34.io.deq.bits connect remapVecValids[23], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[23] node _T_3069 = eq(UInt<2>(0h3), remapindex_23) when _T_3069 : connect remapVecData[23], Queue32_UInt8_35.io.deq.bits connect remapVecValids[23], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[23] node _T_3070 = eq(UInt<3>(0h4), remapindex_23) when _T_3070 : connect remapVecData[23], Queue32_UInt8_36.io.deq.bits connect remapVecValids[23], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[23] node _T_3071 = eq(UInt<3>(0h5), remapindex_23) when _T_3071 : connect remapVecData[23], Queue32_UInt8_37.io.deq.bits connect remapVecValids[23], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[23] node _T_3072 = eq(UInt<3>(0h6), remapindex_23) when _T_3072 : connect remapVecData[23], Queue32_UInt8_38.io.deq.bits connect remapVecValids[23], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[23] node _T_3073 = eq(UInt<3>(0h7), remapindex_23) when _T_3073 : connect remapVecData[23], Queue32_UInt8_39.io.deq.bits connect remapVecValids[23], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[23] node _T_3074 = eq(UInt<4>(0h8), remapindex_23) when _T_3074 : connect remapVecData[23], Queue32_UInt8_40.io.deq.bits connect remapVecValids[23], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[23] node _T_3075 = eq(UInt<4>(0h9), remapindex_23) when _T_3075 : connect remapVecData[23], Queue32_UInt8_41.io.deq.bits connect remapVecValids[23], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[23] node _T_3076 = eq(UInt<4>(0ha), remapindex_23) when _T_3076 : connect remapVecData[23], Queue32_UInt8_42.io.deq.bits connect remapVecValids[23], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[23] node _T_3077 = eq(UInt<4>(0hb), remapindex_23) when _T_3077 : connect remapVecData[23], Queue32_UInt8_43.io.deq.bits connect remapVecValids[23], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[23] node _T_3078 = eq(UInt<4>(0hc), remapindex_23) when _T_3078 : connect remapVecData[23], Queue32_UInt8_44.io.deq.bits connect remapVecValids[23], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[23] node _T_3079 = eq(UInt<4>(0hd), remapindex_23) when _T_3079 : connect remapVecData[23], Queue32_UInt8_45.io.deq.bits connect remapVecValids[23], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[23] node _T_3080 = eq(UInt<4>(0he), remapindex_23) when _T_3080 : connect remapVecData[23], Queue32_UInt8_46.io.deq.bits connect remapVecValids[23], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[23] node _T_3081 = eq(UInt<4>(0hf), remapindex_23) when _T_3081 : connect remapVecData[23], Queue32_UInt8_47.io.deq.bits connect remapVecValids[23], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[23] node _T_3082 = eq(UInt<5>(0h10), remapindex_23) when _T_3082 : connect remapVecData[23], Queue32_UInt8_48.io.deq.bits connect remapVecValids[23], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[23] node _T_3083 = eq(UInt<5>(0h11), remapindex_23) when _T_3083 : connect remapVecData[23], Queue32_UInt8_49.io.deq.bits connect remapVecValids[23], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[23] node _T_3084 = eq(UInt<5>(0h12), remapindex_23) when _T_3084 : connect remapVecData[23], Queue32_UInt8_50.io.deq.bits connect remapVecValids[23], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[23] node _T_3085 = eq(UInt<5>(0h13), remapindex_23) when _T_3085 : connect remapVecData[23], Queue32_UInt8_51.io.deq.bits connect remapVecValids[23], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[23] node _T_3086 = eq(UInt<5>(0h14), remapindex_23) when _T_3086 : connect remapVecData[23], Queue32_UInt8_52.io.deq.bits connect remapVecValids[23], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[23] node _T_3087 = eq(UInt<5>(0h15), remapindex_23) when _T_3087 : connect remapVecData[23], Queue32_UInt8_53.io.deq.bits connect remapVecValids[23], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[23] node _T_3088 = eq(UInt<5>(0h16), remapindex_23) when _T_3088 : connect remapVecData[23], Queue32_UInt8_54.io.deq.bits connect remapVecValids[23], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[23] node _T_3089 = eq(UInt<5>(0h17), remapindex_23) when _T_3089 : connect remapVecData[23], Queue32_UInt8_55.io.deq.bits connect remapVecValids[23], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[23] node _T_3090 = eq(UInt<5>(0h18), remapindex_23) when _T_3090 : connect remapVecData[23], Queue32_UInt8_56.io.deq.bits connect remapVecValids[23], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[23] node _T_3091 = eq(UInt<5>(0h19), remapindex_23) when _T_3091 : connect remapVecData[23], Queue32_UInt8_57.io.deq.bits connect remapVecValids[23], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[23] node _T_3092 = eq(UInt<5>(0h1a), remapindex_23) when _T_3092 : connect remapVecData[23], Queue32_UInt8_58.io.deq.bits connect remapVecValids[23], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[23] node _T_3093 = eq(UInt<5>(0h1b), remapindex_23) when _T_3093 : connect remapVecData[23], Queue32_UInt8_59.io.deq.bits connect remapVecValids[23], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[23] node _T_3094 = eq(UInt<5>(0h1c), remapindex_23) when _T_3094 : connect remapVecData[23], Queue32_UInt8_60.io.deq.bits connect remapVecValids[23], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[23] node _T_3095 = eq(UInt<5>(0h1d), remapindex_23) when _T_3095 : connect remapVecData[23], Queue32_UInt8_61.io.deq.bits connect remapVecValids[23], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[23] node _T_3096 = eq(UInt<5>(0h1e), remapindex_23) when _T_3096 : connect remapVecData[23], Queue32_UInt8_62.io.deq.bits connect remapVecValids[23], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[23] node _T_3097 = eq(UInt<5>(0h1f), remapindex_23) when _T_3097 : connect remapVecData[23], Queue32_UInt8_63.io.deq.bits connect remapVecValids[23], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[23] node _remapindex_T_24 = add(UInt<5>(0h18), read_start_index) node remapindex_24 = rem(_remapindex_T_24, UInt<6>(0h20)) node _T_3098 = eq(UInt<1>(0h0), remapindex_24) when _T_3098 : connect remapVecData[24], Queue32_UInt8_32.io.deq.bits connect remapVecValids[24], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[24] node _T_3099 = eq(UInt<1>(0h1), remapindex_24) when _T_3099 : connect remapVecData[24], Queue32_UInt8_33.io.deq.bits connect remapVecValids[24], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[24] node _T_3100 = eq(UInt<2>(0h2), remapindex_24) when _T_3100 : connect remapVecData[24], Queue32_UInt8_34.io.deq.bits connect remapVecValids[24], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[24] node _T_3101 = eq(UInt<2>(0h3), remapindex_24) when _T_3101 : connect remapVecData[24], Queue32_UInt8_35.io.deq.bits connect remapVecValids[24], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[24] node _T_3102 = eq(UInt<3>(0h4), remapindex_24) when _T_3102 : connect remapVecData[24], Queue32_UInt8_36.io.deq.bits connect remapVecValids[24], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[24] node _T_3103 = eq(UInt<3>(0h5), remapindex_24) when _T_3103 : connect remapVecData[24], Queue32_UInt8_37.io.deq.bits connect remapVecValids[24], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[24] node _T_3104 = eq(UInt<3>(0h6), remapindex_24) when _T_3104 : connect remapVecData[24], Queue32_UInt8_38.io.deq.bits connect remapVecValids[24], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[24] node _T_3105 = eq(UInt<3>(0h7), remapindex_24) when _T_3105 : connect remapVecData[24], Queue32_UInt8_39.io.deq.bits connect remapVecValids[24], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[24] node _T_3106 = eq(UInt<4>(0h8), remapindex_24) when _T_3106 : connect remapVecData[24], Queue32_UInt8_40.io.deq.bits connect remapVecValids[24], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[24] node _T_3107 = eq(UInt<4>(0h9), remapindex_24) when _T_3107 : connect remapVecData[24], Queue32_UInt8_41.io.deq.bits connect remapVecValids[24], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[24] node _T_3108 = eq(UInt<4>(0ha), remapindex_24) when _T_3108 : connect remapVecData[24], Queue32_UInt8_42.io.deq.bits connect remapVecValids[24], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[24] node _T_3109 = eq(UInt<4>(0hb), remapindex_24) when _T_3109 : connect remapVecData[24], Queue32_UInt8_43.io.deq.bits connect remapVecValids[24], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[24] node _T_3110 = eq(UInt<4>(0hc), remapindex_24) when _T_3110 : connect remapVecData[24], Queue32_UInt8_44.io.deq.bits connect remapVecValids[24], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[24] node _T_3111 = eq(UInt<4>(0hd), remapindex_24) when _T_3111 : connect remapVecData[24], Queue32_UInt8_45.io.deq.bits connect remapVecValids[24], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[24] node _T_3112 = eq(UInt<4>(0he), remapindex_24) when _T_3112 : connect remapVecData[24], Queue32_UInt8_46.io.deq.bits connect remapVecValids[24], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[24] node _T_3113 = eq(UInt<4>(0hf), remapindex_24) when _T_3113 : connect remapVecData[24], Queue32_UInt8_47.io.deq.bits connect remapVecValids[24], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[24] node _T_3114 = eq(UInt<5>(0h10), remapindex_24) when _T_3114 : connect remapVecData[24], Queue32_UInt8_48.io.deq.bits connect remapVecValids[24], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[24] node _T_3115 = eq(UInt<5>(0h11), remapindex_24) when _T_3115 : connect remapVecData[24], Queue32_UInt8_49.io.deq.bits connect remapVecValids[24], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[24] node _T_3116 = eq(UInt<5>(0h12), remapindex_24) when _T_3116 : connect remapVecData[24], Queue32_UInt8_50.io.deq.bits connect remapVecValids[24], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[24] node _T_3117 = eq(UInt<5>(0h13), remapindex_24) when _T_3117 : connect remapVecData[24], Queue32_UInt8_51.io.deq.bits connect remapVecValids[24], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[24] node _T_3118 = eq(UInt<5>(0h14), remapindex_24) when _T_3118 : connect remapVecData[24], Queue32_UInt8_52.io.deq.bits connect remapVecValids[24], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[24] node _T_3119 = eq(UInt<5>(0h15), remapindex_24) when _T_3119 : connect remapVecData[24], Queue32_UInt8_53.io.deq.bits connect remapVecValids[24], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[24] node _T_3120 = eq(UInt<5>(0h16), remapindex_24) when _T_3120 : connect remapVecData[24], Queue32_UInt8_54.io.deq.bits connect remapVecValids[24], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[24] node _T_3121 = eq(UInt<5>(0h17), remapindex_24) when _T_3121 : connect remapVecData[24], Queue32_UInt8_55.io.deq.bits connect remapVecValids[24], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[24] node _T_3122 = eq(UInt<5>(0h18), remapindex_24) when _T_3122 : connect remapVecData[24], Queue32_UInt8_56.io.deq.bits connect remapVecValids[24], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[24] node _T_3123 = eq(UInt<5>(0h19), remapindex_24) when _T_3123 : connect remapVecData[24], Queue32_UInt8_57.io.deq.bits connect remapVecValids[24], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[24] node _T_3124 = eq(UInt<5>(0h1a), remapindex_24) when _T_3124 : connect remapVecData[24], Queue32_UInt8_58.io.deq.bits connect remapVecValids[24], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[24] node _T_3125 = eq(UInt<5>(0h1b), remapindex_24) when _T_3125 : connect remapVecData[24], Queue32_UInt8_59.io.deq.bits connect remapVecValids[24], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[24] node _T_3126 = eq(UInt<5>(0h1c), remapindex_24) when _T_3126 : connect remapVecData[24], Queue32_UInt8_60.io.deq.bits connect remapVecValids[24], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[24] node _T_3127 = eq(UInt<5>(0h1d), remapindex_24) when _T_3127 : connect remapVecData[24], Queue32_UInt8_61.io.deq.bits connect remapVecValids[24], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[24] node _T_3128 = eq(UInt<5>(0h1e), remapindex_24) when _T_3128 : connect remapVecData[24], Queue32_UInt8_62.io.deq.bits connect remapVecValids[24], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[24] node _T_3129 = eq(UInt<5>(0h1f), remapindex_24) when _T_3129 : connect remapVecData[24], Queue32_UInt8_63.io.deq.bits connect remapVecValids[24], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[24] node _remapindex_T_25 = add(UInt<5>(0h19), read_start_index) node remapindex_25 = rem(_remapindex_T_25, UInt<6>(0h20)) node _T_3130 = eq(UInt<1>(0h0), remapindex_25) when _T_3130 : connect remapVecData[25], Queue32_UInt8_32.io.deq.bits connect remapVecValids[25], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[25] node _T_3131 = eq(UInt<1>(0h1), remapindex_25) when _T_3131 : connect remapVecData[25], Queue32_UInt8_33.io.deq.bits connect remapVecValids[25], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[25] node _T_3132 = eq(UInt<2>(0h2), remapindex_25) when _T_3132 : connect remapVecData[25], Queue32_UInt8_34.io.deq.bits connect remapVecValids[25], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[25] node _T_3133 = eq(UInt<2>(0h3), remapindex_25) when _T_3133 : connect remapVecData[25], Queue32_UInt8_35.io.deq.bits connect remapVecValids[25], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[25] node _T_3134 = eq(UInt<3>(0h4), remapindex_25) when _T_3134 : connect remapVecData[25], Queue32_UInt8_36.io.deq.bits connect remapVecValids[25], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[25] node _T_3135 = eq(UInt<3>(0h5), remapindex_25) when _T_3135 : connect remapVecData[25], Queue32_UInt8_37.io.deq.bits connect remapVecValids[25], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[25] node _T_3136 = eq(UInt<3>(0h6), remapindex_25) when _T_3136 : connect remapVecData[25], Queue32_UInt8_38.io.deq.bits connect remapVecValids[25], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[25] node _T_3137 = eq(UInt<3>(0h7), remapindex_25) when _T_3137 : connect remapVecData[25], Queue32_UInt8_39.io.deq.bits connect remapVecValids[25], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[25] node _T_3138 = eq(UInt<4>(0h8), remapindex_25) when _T_3138 : connect remapVecData[25], Queue32_UInt8_40.io.deq.bits connect remapVecValids[25], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[25] node _T_3139 = eq(UInt<4>(0h9), remapindex_25) when _T_3139 : connect remapVecData[25], Queue32_UInt8_41.io.deq.bits connect remapVecValids[25], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[25] node _T_3140 = eq(UInt<4>(0ha), remapindex_25) when _T_3140 : connect remapVecData[25], Queue32_UInt8_42.io.deq.bits connect remapVecValids[25], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[25] node _T_3141 = eq(UInt<4>(0hb), remapindex_25) when _T_3141 : connect remapVecData[25], Queue32_UInt8_43.io.deq.bits connect remapVecValids[25], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[25] node _T_3142 = eq(UInt<4>(0hc), remapindex_25) when _T_3142 : connect remapVecData[25], Queue32_UInt8_44.io.deq.bits connect remapVecValids[25], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[25] node _T_3143 = eq(UInt<4>(0hd), remapindex_25) when _T_3143 : connect remapVecData[25], Queue32_UInt8_45.io.deq.bits connect remapVecValids[25], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[25] node _T_3144 = eq(UInt<4>(0he), remapindex_25) when _T_3144 : connect remapVecData[25], Queue32_UInt8_46.io.deq.bits connect remapVecValids[25], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[25] node _T_3145 = eq(UInt<4>(0hf), remapindex_25) when _T_3145 : connect remapVecData[25], Queue32_UInt8_47.io.deq.bits connect remapVecValids[25], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[25] node _T_3146 = eq(UInt<5>(0h10), remapindex_25) when _T_3146 : connect remapVecData[25], Queue32_UInt8_48.io.deq.bits connect remapVecValids[25], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[25] node _T_3147 = eq(UInt<5>(0h11), remapindex_25) when _T_3147 : connect remapVecData[25], Queue32_UInt8_49.io.deq.bits connect remapVecValids[25], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[25] node _T_3148 = eq(UInt<5>(0h12), remapindex_25) when _T_3148 : connect remapVecData[25], Queue32_UInt8_50.io.deq.bits connect remapVecValids[25], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[25] node _T_3149 = eq(UInt<5>(0h13), remapindex_25) when _T_3149 : connect remapVecData[25], Queue32_UInt8_51.io.deq.bits connect remapVecValids[25], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[25] node _T_3150 = eq(UInt<5>(0h14), remapindex_25) when _T_3150 : connect remapVecData[25], Queue32_UInt8_52.io.deq.bits connect remapVecValids[25], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[25] node _T_3151 = eq(UInt<5>(0h15), remapindex_25) when _T_3151 : connect remapVecData[25], Queue32_UInt8_53.io.deq.bits connect remapVecValids[25], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[25] node _T_3152 = eq(UInt<5>(0h16), remapindex_25) when _T_3152 : connect remapVecData[25], Queue32_UInt8_54.io.deq.bits connect remapVecValids[25], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[25] node _T_3153 = eq(UInt<5>(0h17), remapindex_25) when _T_3153 : connect remapVecData[25], Queue32_UInt8_55.io.deq.bits connect remapVecValids[25], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[25] node _T_3154 = eq(UInt<5>(0h18), remapindex_25) when _T_3154 : connect remapVecData[25], Queue32_UInt8_56.io.deq.bits connect remapVecValids[25], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[25] node _T_3155 = eq(UInt<5>(0h19), remapindex_25) when _T_3155 : connect remapVecData[25], Queue32_UInt8_57.io.deq.bits connect remapVecValids[25], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[25] node _T_3156 = eq(UInt<5>(0h1a), remapindex_25) when _T_3156 : connect remapVecData[25], Queue32_UInt8_58.io.deq.bits connect remapVecValids[25], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[25] node _T_3157 = eq(UInt<5>(0h1b), remapindex_25) when _T_3157 : connect remapVecData[25], Queue32_UInt8_59.io.deq.bits connect remapVecValids[25], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[25] node _T_3158 = eq(UInt<5>(0h1c), remapindex_25) when _T_3158 : connect remapVecData[25], Queue32_UInt8_60.io.deq.bits connect remapVecValids[25], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[25] node _T_3159 = eq(UInt<5>(0h1d), remapindex_25) when _T_3159 : connect remapVecData[25], Queue32_UInt8_61.io.deq.bits connect remapVecValids[25], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[25] node _T_3160 = eq(UInt<5>(0h1e), remapindex_25) when _T_3160 : connect remapVecData[25], Queue32_UInt8_62.io.deq.bits connect remapVecValids[25], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[25] node _T_3161 = eq(UInt<5>(0h1f), remapindex_25) when _T_3161 : connect remapVecData[25], Queue32_UInt8_63.io.deq.bits connect remapVecValids[25], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[25] node _remapindex_T_26 = add(UInt<5>(0h1a), read_start_index) node remapindex_26 = rem(_remapindex_T_26, UInt<6>(0h20)) node _T_3162 = eq(UInt<1>(0h0), remapindex_26) when _T_3162 : connect remapVecData[26], Queue32_UInt8_32.io.deq.bits connect remapVecValids[26], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[26] node _T_3163 = eq(UInt<1>(0h1), remapindex_26) when _T_3163 : connect remapVecData[26], Queue32_UInt8_33.io.deq.bits connect remapVecValids[26], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[26] node _T_3164 = eq(UInt<2>(0h2), remapindex_26) when _T_3164 : connect remapVecData[26], Queue32_UInt8_34.io.deq.bits connect remapVecValids[26], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[26] node _T_3165 = eq(UInt<2>(0h3), remapindex_26) when _T_3165 : connect remapVecData[26], Queue32_UInt8_35.io.deq.bits connect remapVecValids[26], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[26] node _T_3166 = eq(UInt<3>(0h4), remapindex_26) when _T_3166 : connect remapVecData[26], Queue32_UInt8_36.io.deq.bits connect remapVecValids[26], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[26] node _T_3167 = eq(UInt<3>(0h5), remapindex_26) when _T_3167 : connect remapVecData[26], Queue32_UInt8_37.io.deq.bits connect remapVecValids[26], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[26] node _T_3168 = eq(UInt<3>(0h6), remapindex_26) when _T_3168 : connect remapVecData[26], Queue32_UInt8_38.io.deq.bits connect remapVecValids[26], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[26] node _T_3169 = eq(UInt<3>(0h7), remapindex_26) when _T_3169 : connect remapVecData[26], Queue32_UInt8_39.io.deq.bits connect remapVecValids[26], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[26] node _T_3170 = eq(UInt<4>(0h8), remapindex_26) when _T_3170 : connect remapVecData[26], Queue32_UInt8_40.io.deq.bits connect remapVecValids[26], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[26] node _T_3171 = eq(UInt<4>(0h9), remapindex_26) when _T_3171 : connect remapVecData[26], Queue32_UInt8_41.io.deq.bits connect remapVecValids[26], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[26] node _T_3172 = eq(UInt<4>(0ha), remapindex_26) when _T_3172 : connect remapVecData[26], Queue32_UInt8_42.io.deq.bits connect remapVecValids[26], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[26] node _T_3173 = eq(UInt<4>(0hb), remapindex_26) when _T_3173 : connect remapVecData[26], Queue32_UInt8_43.io.deq.bits connect remapVecValids[26], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[26] node _T_3174 = eq(UInt<4>(0hc), remapindex_26) when _T_3174 : connect remapVecData[26], Queue32_UInt8_44.io.deq.bits connect remapVecValids[26], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[26] node _T_3175 = eq(UInt<4>(0hd), remapindex_26) when _T_3175 : connect remapVecData[26], Queue32_UInt8_45.io.deq.bits connect remapVecValids[26], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[26] node _T_3176 = eq(UInt<4>(0he), remapindex_26) when _T_3176 : connect remapVecData[26], Queue32_UInt8_46.io.deq.bits connect remapVecValids[26], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[26] node _T_3177 = eq(UInt<4>(0hf), remapindex_26) when _T_3177 : connect remapVecData[26], Queue32_UInt8_47.io.deq.bits connect remapVecValids[26], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[26] node _T_3178 = eq(UInt<5>(0h10), remapindex_26) when _T_3178 : connect remapVecData[26], Queue32_UInt8_48.io.deq.bits connect remapVecValids[26], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[26] node _T_3179 = eq(UInt<5>(0h11), remapindex_26) when _T_3179 : connect remapVecData[26], Queue32_UInt8_49.io.deq.bits connect remapVecValids[26], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[26] node _T_3180 = eq(UInt<5>(0h12), remapindex_26) when _T_3180 : connect remapVecData[26], Queue32_UInt8_50.io.deq.bits connect remapVecValids[26], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[26] node _T_3181 = eq(UInt<5>(0h13), remapindex_26) when _T_3181 : connect remapVecData[26], Queue32_UInt8_51.io.deq.bits connect remapVecValids[26], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[26] node _T_3182 = eq(UInt<5>(0h14), remapindex_26) when _T_3182 : connect remapVecData[26], Queue32_UInt8_52.io.deq.bits connect remapVecValids[26], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[26] node _T_3183 = eq(UInt<5>(0h15), remapindex_26) when _T_3183 : connect remapVecData[26], Queue32_UInt8_53.io.deq.bits connect remapVecValids[26], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[26] node _T_3184 = eq(UInt<5>(0h16), remapindex_26) when _T_3184 : connect remapVecData[26], Queue32_UInt8_54.io.deq.bits connect remapVecValids[26], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[26] node _T_3185 = eq(UInt<5>(0h17), remapindex_26) when _T_3185 : connect remapVecData[26], Queue32_UInt8_55.io.deq.bits connect remapVecValids[26], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[26] node _T_3186 = eq(UInt<5>(0h18), remapindex_26) when _T_3186 : connect remapVecData[26], Queue32_UInt8_56.io.deq.bits connect remapVecValids[26], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[26] node _T_3187 = eq(UInt<5>(0h19), remapindex_26) when _T_3187 : connect remapVecData[26], Queue32_UInt8_57.io.deq.bits connect remapVecValids[26], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[26] node _T_3188 = eq(UInt<5>(0h1a), remapindex_26) when _T_3188 : connect remapVecData[26], Queue32_UInt8_58.io.deq.bits connect remapVecValids[26], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[26] node _T_3189 = eq(UInt<5>(0h1b), remapindex_26) when _T_3189 : connect remapVecData[26], Queue32_UInt8_59.io.deq.bits connect remapVecValids[26], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[26] node _T_3190 = eq(UInt<5>(0h1c), remapindex_26) when _T_3190 : connect remapVecData[26], Queue32_UInt8_60.io.deq.bits connect remapVecValids[26], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[26] node _T_3191 = eq(UInt<5>(0h1d), remapindex_26) when _T_3191 : connect remapVecData[26], Queue32_UInt8_61.io.deq.bits connect remapVecValids[26], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[26] node _T_3192 = eq(UInt<5>(0h1e), remapindex_26) when _T_3192 : connect remapVecData[26], Queue32_UInt8_62.io.deq.bits connect remapVecValids[26], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[26] node _T_3193 = eq(UInt<5>(0h1f), remapindex_26) when _T_3193 : connect remapVecData[26], Queue32_UInt8_63.io.deq.bits connect remapVecValids[26], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[26] node _remapindex_T_27 = add(UInt<5>(0h1b), read_start_index) node remapindex_27 = rem(_remapindex_T_27, UInt<6>(0h20)) node _T_3194 = eq(UInt<1>(0h0), remapindex_27) when _T_3194 : connect remapVecData[27], Queue32_UInt8_32.io.deq.bits connect remapVecValids[27], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[27] node _T_3195 = eq(UInt<1>(0h1), remapindex_27) when _T_3195 : connect remapVecData[27], Queue32_UInt8_33.io.deq.bits connect remapVecValids[27], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[27] node _T_3196 = eq(UInt<2>(0h2), remapindex_27) when _T_3196 : connect remapVecData[27], Queue32_UInt8_34.io.deq.bits connect remapVecValids[27], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[27] node _T_3197 = eq(UInt<2>(0h3), remapindex_27) when _T_3197 : connect remapVecData[27], Queue32_UInt8_35.io.deq.bits connect remapVecValids[27], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[27] node _T_3198 = eq(UInt<3>(0h4), remapindex_27) when _T_3198 : connect remapVecData[27], Queue32_UInt8_36.io.deq.bits connect remapVecValids[27], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[27] node _T_3199 = eq(UInt<3>(0h5), remapindex_27) when _T_3199 : connect remapVecData[27], Queue32_UInt8_37.io.deq.bits connect remapVecValids[27], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[27] node _T_3200 = eq(UInt<3>(0h6), remapindex_27) when _T_3200 : connect remapVecData[27], Queue32_UInt8_38.io.deq.bits connect remapVecValids[27], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[27] node _T_3201 = eq(UInt<3>(0h7), remapindex_27) when _T_3201 : connect remapVecData[27], Queue32_UInt8_39.io.deq.bits connect remapVecValids[27], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[27] node _T_3202 = eq(UInt<4>(0h8), remapindex_27) when _T_3202 : connect remapVecData[27], Queue32_UInt8_40.io.deq.bits connect remapVecValids[27], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[27] node _T_3203 = eq(UInt<4>(0h9), remapindex_27) when _T_3203 : connect remapVecData[27], Queue32_UInt8_41.io.deq.bits connect remapVecValids[27], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[27] node _T_3204 = eq(UInt<4>(0ha), remapindex_27) when _T_3204 : connect remapVecData[27], Queue32_UInt8_42.io.deq.bits connect remapVecValids[27], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[27] node _T_3205 = eq(UInt<4>(0hb), remapindex_27) when _T_3205 : connect remapVecData[27], Queue32_UInt8_43.io.deq.bits connect remapVecValids[27], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[27] node _T_3206 = eq(UInt<4>(0hc), remapindex_27) when _T_3206 : connect remapVecData[27], Queue32_UInt8_44.io.deq.bits connect remapVecValids[27], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[27] node _T_3207 = eq(UInt<4>(0hd), remapindex_27) when _T_3207 : connect remapVecData[27], Queue32_UInt8_45.io.deq.bits connect remapVecValids[27], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[27] node _T_3208 = eq(UInt<4>(0he), remapindex_27) when _T_3208 : connect remapVecData[27], Queue32_UInt8_46.io.deq.bits connect remapVecValids[27], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[27] node _T_3209 = eq(UInt<4>(0hf), remapindex_27) when _T_3209 : connect remapVecData[27], Queue32_UInt8_47.io.deq.bits connect remapVecValids[27], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[27] node _T_3210 = eq(UInt<5>(0h10), remapindex_27) when _T_3210 : connect remapVecData[27], Queue32_UInt8_48.io.deq.bits connect remapVecValids[27], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[27] node _T_3211 = eq(UInt<5>(0h11), remapindex_27) when _T_3211 : connect remapVecData[27], Queue32_UInt8_49.io.deq.bits connect remapVecValids[27], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[27] node _T_3212 = eq(UInt<5>(0h12), remapindex_27) when _T_3212 : connect remapVecData[27], Queue32_UInt8_50.io.deq.bits connect remapVecValids[27], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[27] node _T_3213 = eq(UInt<5>(0h13), remapindex_27) when _T_3213 : connect remapVecData[27], Queue32_UInt8_51.io.deq.bits connect remapVecValids[27], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[27] node _T_3214 = eq(UInt<5>(0h14), remapindex_27) when _T_3214 : connect remapVecData[27], Queue32_UInt8_52.io.deq.bits connect remapVecValids[27], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[27] node _T_3215 = eq(UInt<5>(0h15), remapindex_27) when _T_3215 : connect remapVecData[27], Queue32_UInt8_53.io.deq.bits connect remapVecValids[27], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[27] node _T_3216 = eq(UInt<5>(0h16), remapindex_27) when _T_3216 : connect remapVecData[27], Queue32_UInt8_54.io.deq.bits connect remapVecValids[27], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[27] node _T_3217 = eq(UInt<5>(0h17), remapindex_27) when _T_3217 : connect remapVecData[27], Queue32_UInt8_55.io.deq.bits connect remapVecValids[27], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[27] node _T_3218 = eq(UInt<5>(0h18), remapindex_27) when _T_3218 : connect remapVecData[27], Queue32_UInt8_56.io.deq.bits connect remapVecValids[27], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[27] node _T_3219 = eq(UInt<5>(0h19), remapindex_27) when _T_3219 : connect remapVecData[27], Queue32_UInt8_57.io.deq.bits connect remapVecValids[27], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[27] node _T_3220 = eq(UInt<5>(0h1a), remapindex_27) when _T_3220 : connect remapVecData[27], Queue32_UInt8_58.io.deq.bits connect remapVecValids[27], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[27] node _T_3221 = eq(UInt<5>(0h1b), remapindex_27) when _T_3221 : connect remapVecData[27], Queue32_UInt8_59.io.deq.bits connect remapVecValids[27], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[27] node _T_3222 = eq(UInt<5>(0h1c), remapindex_27) when _T_3222 : connect remapVecData[27], Queue32_UInt8_60.io.deq.bits connect remapVecValids[27], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[27] node _T_3223 = eq(UInt<5>(0h1d), remapindex_27) when _T_3223 : connect remapVecData[27], Queue32_UInt8_61.io.deq.bits connect remapVecValids[27], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[27] node _T_3224 = eq(UInt<5>(0h1e), remapindex_27) when _T_3224 : connect remapVecData[27], Queue32_UInt8_62.io.deq.bits connect remapVecValids[27], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[27] node _T_3225 = eq(UInt<5>(0h1f), remapindex_27) when _T_3225 : connect remapVecData[27], Queue32_UInt8_63.io.deq.bits connect remapVecValids[27], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[27] node _remapindex_T_28 = add(UInt<5>(0h1c), read_start_index) node remapindex_28 = rem(_remapindex_T_28, UInt<6>(0h20)) node _T_3226 = eq(UInt<1>(0h0), remapindex_28) when _T_3226 : connect remapVecData[28], Queue32_UInt8_32.io.deq.bits connect remapVecValids[28], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[28] node _T_3227 = eq(UInt<1>(0h1), remapindex_28) when _T_3227 : connect remapVecData[28], Queue32_UInt8_33.io.deq.bits connect remapVecValids[28], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[28] node _T_3228 = eq(UInt<2>(0h2), remapindex_28) when _T_3228 : connect remapVecData[28], Queue32_UInt8_34.io.deq.bits connect remapVecValids[28], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[28] node _T_3229 = eq(UInt<2>(0h3), remapindex_28) when _T_3229 : connect remapVecData[28], Queue32_UInt8_35.io.deq.bits connect remapVecValids[28], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[28] node _T_3230 = eq(UInt<3>(0h4), remapindex_28) when _T_3230 : connect remapVecData[28], Queue32_UInt8_36.io.deq.bits connect remapVecValids[28], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[28] node _T_3231 = eq(UInt<3>(0h5), remapindex_28) when _T_3231 : connect remapVecData[28], Queue32_UInt8_37.io.deq.bits connect remapVecValids[28], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[28] node _T_3232 = eq(UInt<3>(0h6), remapindex_28) when _T_3232 : connect remapVecData[28], Queue32_UInt8_38.io.deq.bits connect remapVecValids[28], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[28] node _T_3233 = eq(UInt<3>(0h7), remapindex_28) when _T_3233 : connect remapVecData[28], Queue32_UInt8_39.io.deq.bits connect remapVecValids[28], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[28] node _T_3234 = eq(UInt<4>(0h8), remapindex_28) when _T_3234 : connect remapVecData[28], Queue32_UInt8_40.io.deq.bits connect remapVecValids[28], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[28] node _T_3235 = eq(UInt<4>(0h9), remapindex_28) when _T_3235 : connect remapVecData[28], Queue32_UInt8_41.io.deq.bits connect remapVecValids[28], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[28] node _T_3236 = eq(UInt<4>(0ha), remapindex_28) when _T_3236 : connect remapVecData[28], Queue32_UInt8_42.io.deq.bits connect remapVecValids[28], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[28] node _T_3237 = eq(UInt<4>(0hb), remapindex_28) when _T_3237 : connect remapVecData[28], Queue32_UInt8_43.io.deq.bits connect remapVecValids[28], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[28] node _T_3238 = eq(UInt<4>(0hc), remapindex_28) when _T_3238 : connect remapVecData[28], Queue32_UInt8_44.io.deq.bits connect remapVecValids[28], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[28] node _T_3239 = eq(UInt<4>(0hd), remapindex_28) when _T_3239 : connect remapVecData[28], Queue32_UInt8_45.io.deq.bits connect remapVecValids[28], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[28] node _T_3240 = eq(UInt<4>(0he), remapindex_28) when _T_3240 : connect remapVecData[28], Queue32_UInt8_46.io.deq.bits connect remapVecValids[28], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[28] node _T_3241 = eq(UInt<4>(0hf), remapindex_28) when _T_3241 : connect remapVecData[28], Queue32_UInt8_47.io.deq.bits connect remapVecValids[28], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[28] node _T_3242 = eq(UInt<5>(0h10), remapindex_28) when _T_3242 : connect remapVecData[28], Queue32_UInt8_48.io.deq.bits connect remapVecValids[28], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[28] node _T_3243 = eq(UInt<5>(0h11), remapindex_28) when _T_3243 : connect remapVecData[28], Queue32_UInt8_49.io.deq.bits connect remapVecValids[28], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[28] node _T_3244 = eq(UInt<5>(0h12), remapindex_28) when _T_3244 : connect remapVecData[28], Queue32_UInt8_50.io.deq.bits connect remapVecValids[28], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[28] node _T_3245 = eq(UInt<5>(0h13), remapindex_28) when _T_3245 : connect remapVecData[28], Queue32_UInt8_51.io.deq.bits connect remapVecValids[28], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[28] node _T_3246 = eq(UInt<5>(0h14), remapindex_28) when _T_3246 : connect remapVecData[28], Queue32_UInt8_52.io.deq.bits connect remapVecValids[28], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[28] node _T_3247 = eq(UInt<5>(0h15), remapindex_28) when _T_3247 : connect remapVecData[28], Queue32_UInt8_53.io.deq.bits connect remapVecValids[28], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[28] node _T_3248 = eq(UInt<5>(0h16), remapindex_28) when _T_3248 : connect remapVecData[28], Queue32_UInt8_54.io.deq.bits connect remapVecValids[28], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[28] node _T_3249 = eq(UInt<5>(0h17), remapindex_28) when _T_3249 : connect remapVecData[28], Queue32_UInt8_55.io.deq.bits connect remapVecValids[28], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[28] node _T_3250 = eq(UInt<5>(0h18), remapindex_28) when _T_3250 : connect remapVecData[28], Queue32_UInt8_56.io.deq.bits connect remapVecValids[28], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[28] node _T_3251 = eq(UInt<5>(0h19), remapindex_28) when _T_3251 : connect remapVecData[28], Queue32_UInt8_57.io.deq.bits connect remapVecValids[28], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[28] node _T_3252 = eq(UInt<5>(0h1a), remapindex_28) when _T_3252 : connect remapVecData[28], Queue32_UInt8_58.io.deq.bits connect remapVecValids[28], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[28] node _T_3253 = eq(UInt<5>(0h1b), remapindex_28) when _T_3253 : connect remapVecData[28], Queue32_UInt8_59.io.deq.bits connect remapVecValids[28], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[28] node _T_3254 = eq(UInt<5>(0h1c), remapindex_28) when _T_3254 : connect remapVecData[28], Queue32_UInt8_60.io.deq.bits connect remapVecValids[28], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[28] node _T_3255 = eq(UInt<5>(0h1d), remapindex_28) when _T_3255 : connect remapVecData[28], Queue32_UInt8_61.io.deq.bits connect remapVecValids[28], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[28] node _T_3256 = eq(UInt<5>(0h1e), remapindex_28) when _T_3256 : connect remapVecData[28], Queue32_UInt8_62.io.deq.bits connect remapVecValids[28], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[28] node _T_3257 = eq(UInt<5>(0h1f), remapindex_28) when _T_3257 : connect remapVecData[28], Queue32_UInt8_63.io.deq.bits connect remapVecValids[28], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[28] node _remapindex_T_29 = add(UInt<5>(0h1d), read_start_index) node remapindex_29 = rem(_remapindex_T_29, UInt<6>(0h20)) node _T_3258 = eq(UInt<1>(0h0), remapindex_29) when _T_3258 : connect remapVecData[29], Queue32_UInt8_32.io.deq.bits connect remapVecValids[29], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[29] node _T_3259 = eq(UInt<1>(0h1), remapindex_29) when _T_3259 : connect remapVecData[29], Queue32_UInt8_33.io.deq.bits connect remapVecValids[29], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[29] node _T_3260 = eq(UInt<2>(0h2), remapindex_29) when _T_3260 : connect remapVecData[29], Queue32_UInt8_34.io.deq.bits connect remapVecValids[29], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[29] node _T_3261 = eq(UInt<2>(0h3), remapindex_29) when _T_3261 : connect remapVecData[29], Queue32_UInt8_35.io.deq.bits connect remapVecValids[29], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[29] node _T_3262 = eq(UInt<3>(0h4), remapindex_29) when _T_3262 : connect remapVecData[29], Queue32_UInt8_36.io.deq.bits connect remapVecValids[29], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[29] node _T_3263 = eq(UInt<3>(0h5), remapindex_29) when _T_3263 : connect remapVecData[29], Queue32_UInt8_37.io.deq.bits connect remapVecValids[29], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[29] node _T_3264 = eq(UInt<3>(0h6), remapindex_29) when _T_3264 : connect remapVecData[29], Queue32_UInt8_38.io.deq.bits connect remapVecValids[29], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[29] node _T_3265 = eq(UInt<3>(0h7), remapindex_29) when _T_3265 : connect remapVecData[29], Queue32_UInt8_39.io.deq.bits connect remapVecValids[29], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[29] node _T_3266 = eq(UInt<4>(0h8), remapindex_29) when _T_3266 : connect remapVecData[29], Queue32_UInt8_40.io.deq.bits connect remapVecValids[29], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[29] node _T_3267 = eq(UInt<4>(0h9), remapindex_29) when _T_3267 : connect remapVecData[29], Queue32_UInt8_41.io.deq.bits connect remapVecValids[29], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[29] node _T_3268 = eq(UInt<4>(0ha), remapindex_29) when _T_3268 : connect remapVecData[29], Queue32_UInt8_42.io.deq.bits connect remapVecValids[29], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[29] node _T_3269 = eq(UInt<4>(0hb), remapindex_29) when _T_3269 : connect remapVecData[29], Queue32_UInt8_43.io.deq.bits connect remapVecValids[29], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[29] node _T_3270 = eq(UInt<4>(0hc), remapindex_29) when _T_3270 : connect remapVecData[29], Queue32_UInt8_44.io.deq.bits connect remapVecValids[29], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[29] node _T_3271 = eq(UInt<4>(0hd), remapindex_29) when _T_3271 : connect remapVecData[29], Queue32_UInt8_45.io.deq.bits connect remapVecValids[29], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[29] node _T_3272 = eq(UInt<4>(0he), remapindex_29) when _T_3272 : connect remapVecData[29], Queue32_UInt8_46.io.deq.bits connect remapVecValids[29], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[29] node _T_3273 = eq(UInt<4>(0hf), remapindex_29) when _T_3273 : connect remapVecData[29], Queue32_UInt8_47.io.deq.bits connect remapVecValids[29], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[29] node _T_3274 = eq(UInt<5>(0h10), remapindex_29) when _T_3274 : connect remapVecData[29], Queue32_UInt8_48.io.deq.bits connect remapVecValids[29], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[29] node _T_3275 = eq(UInt<5>(0h11), remapindex_29) when _T_3275 : connect remapVecData[29], Queue32_UInt8_49.io.deq.bits connect remapVecValids[29], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[29] node _T_3276 = eq(UInt<5>(0h12), remapindex_29) when _T_3276 : connect remapVecData[29], Queue32_UInt8_50.io.deq.bits connect remapVecValids[29], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[29] node _T_3277 = eq(UInt<5>(0h13), remapindex_29) when _T_3277 : connect remapVecData[29], Queue32_UInt8_51.io.deq.bits connect remapVecValids[29], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[29] node _T_3278 = eq(UInt<5>(0h14), remapindex_29) when _T_3278 : connect remapVecData[29], Queue32_UInt8_52.io.deq.bits connect remapVecValids[29], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[29] node _T_3279 = eq(UInt<5>(0h15), remapindex_29) when _T_3279 : connect remapVecData[29], Queue32_UInt8_53.io.deq.bits connect remapVecValids[29], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[29] node _T_3280 = eq(UInt<5>(0h16), remapindex_29) when _T_3280 : connect remapVecData[29], Queue32_UInt8_54.io.deq.bits connect remapVecValids[29], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[29] node _T_3281 = eq(UInt<5>(0h17), remapindex_29) when _T_3281 : connect remapVecData[29], Queue32_UInt8_55.io.deq.bits connect remapVecValids[29], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[29] node _T_3282 = eq(UInt<5>(0h18), remapindex_29) when _T_3282 : connect remapVecData[29], Queue32_UInt8_56.io.deq.bits connect remapVecValids[29], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[29] node _T_3283 = eq(UInt<5>(0h19), remapindex_29) when _T_3283 : connect remapVecData[29], Queue32_UInt8_57.io.deq.bits connect remapVecValids[29], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[29] node _T_3284 = eq(UInt<5>(0h1a), remapindex_29) when _T_3284 : connect remapVecData[29], Queue32_UInt8_58.io.deq.bits connect remapVecValids[29], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[29] node _T_3285 = eq(UInt<5>(0h1b), remapindex_29) when _T_3285 : connect remapVecData[29], Queue32_UInt8_59.io.deq.bits connect remapVecValids[29], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[29] node _T_3286 = eq(UInt<5>(0h1c), remapindex_29) when _T_3286 : connect remapVecData[29], Queue32_UInt8_60.io.deq.bits connect remapVecValids[29], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[29] node _T_3287 = eq(UInt<5>(0h1d), remapindex_29) when _T_3287 : connect remapVecData[29], Queue32_UInt8_61.io.deq.bits connect remapVecValids[29], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[29] node _T_3288 = eq(UInt<5>(0h1e), remapindex_29) when _T_3288 : connect remapVecData[29], Queue32_UInt8_62.io.deq.bits connect remapVecValids[29], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[29] node _T_3289 = eq(UInt<5>(0h1f), remapindex_29) when _T_3289 : connect remapVecData[29], Queue32_UInt8_63.io.deq.bits connect remapVecValids[29], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[29] node _remapindex_T_30 = add(UInt<5>(0h1e), read_start_index) node remapindex_30 = rem(_remapindex_T_30, UInt<6>(0h20)) node _T_3290 = eq(UInt<1>(0h0), remapindex_30) when _T_3290 : connect remapVecData[30], Queue32_UInt8_32.io.deq.bits connect remapVecValids[30], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[30] node _T_3291 = eq(UInt<1>(0h1), remapindex_30) when _T_3291 : connect remapVecData[30], Queue32_UInt8_33.io.deq.bits connect remapVecValids[30], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[30] node _T_3292 = eq(UInt<2>(0h2), remapindex_30) when _T_3292 : connect remapVecData[30], Queue32_UInt8_34.io.deq.bits connect remapVecValids[30], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[30] node _T_3293 = eq(UInt<2>(0h3), remapindex_30) when _T_3293 : connect remapVecData[30], Queue32_UInt8_35.io.deq.bits connect remapVecValids[30], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[30] node _T_3294 = eq(UInt<3>(0h4), remapindex_30) when _T_3294 : connect remapVecData[30], Queue32_UInt8_36.io.deq.bits connect remapVecValids[30], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[30] node _T_3295 = eq(UInt<3>(0h5), remapindex_30) when _T_3295 : connect remapVecData[30], Queue32_UInt8_37.io.deq.bits connect remapVecValids[30], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[30] node _T_3296 = eq(UInt<3>(0h6), remapindex_30) when _T_3296 : connect remapVecData[30], Queue32_UInt8_38.io.deq.bits connect remapVecValids[30], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[30] node _T_3297 = eq(UInt<3>(0h7), remapindex_30) when _T_3297 : connect remapVecData[30], Queue32_UInt8_39.io.deq.bits connect remapVecValids[30], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[30] node _T_3298 = eq(UInt<4>(0h8), remapindex_30) when _T_3298 : connect remapVecData[30], Queue32_UInt8_40.io.deq.bits connect remapVecValids[30], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[30] node _T_3299 = eq(UInt<4>(0h9), remapindex_30) when _T_3299 : connect remapVecData[30], Queue32_UInt8_41.io.deq.bits connect remapVecValids[30], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[30] node _T_3300 = eq(UInt<4>(0ha), remapindex_30) when _T_3300 : connect remapVecData[30], Queue32_UInt8_42.io.deq.bits connect remapVecValids[30], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[30] node _T_3301 = eq(UInt<4>(0hb), remapindex_30) when _T_3301 : connect remapVecData[30], Queue32_UInt8_43.io.deq.bits connect remapVecValids[30], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[30] node _T_3302 = eq(UInt<4>(0hc), remapindex_30) when _T_3302 : connect remapVecData[30], Queue32_UInt8_44.io.deq.bits connect remapVecValids[30], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[30] node _T_3303 = eq(UInt<4>(0hd), remapindex_30) when _T_3303 : connect remapVecData[30], Queue32_UInt8_45.io.deq.bits connect remapVecValids[30], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[30] node _T_3304 = eq(UInt<4>(0he), remapindex_30) when _T_3304 : connect remapVecData[30], Queue32_UInt8_46.io.deq.bits connect remapVecValids[30], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[30] node _T_3305 = eq(UInt<4>(0hf), remapindex_30) when _T_3305 : connect remapVecData[30], Queue32_UInt8_47.io.deq.bits connect remapVecValids[30], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[30] node _T_3306 = eq(UInt<5>(0h10), remapindex_30) when _T_3306 : connect remapVecData[30], Queue32_UInt8_48.io.deq.bits connect remapVecValids[30], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[30] node _T_3307 = eq(UInt<5>(0h11), remapindex_30) when _T_3307 : connect remapVecData[30], Queue32_UInt8_49.io.deq.bits connect remapVecValids[30], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[30] node _T_3308 = eq(UInt<5>(0h12), remapindex_30) when _T_3308 : connect remapVecData[30], Queue32_UInt8_50.io.deq.bits connect remapVecValids[30], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[30] node _T_3309 = eq(UInt<5>(0h13), remapindex_30) when _T_3309 : connect remapVecData[30], Queue32_UInt8_51.io.deq.bits connect remapVecValids[30], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[30] node _T_3310 = eq(UInt<5>(0h14), remapindex_30) when _T_3310 : connect remapVecData[30], Queue32_UInt8_52.io.deq.bits connect remapVecValids[30], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[30] node _T_3311 = eq(UInt<5>(0h15), remapindex_30) when _T_3311 : connect remapVecData[30], Queue32_UInt8_53.io.deq.bits connect remapVecValids[30], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[30] node _T_3312 = eq(UInt<5>(0h16), remapindex_30) when _T_3312 : connect remapVecData[30], Queue32_UInt8_54.io.deq.bits connect remapVecValids[30], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[30] node _T_3313 = eq(UInt<5>(0h17), remapindex_30) when _T_3313 : connect remapVecData[30], Queue32_UInt8_55.io.deq.bits connect remapVecValids[30], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[30] node _T_3314 = eq(UInt<5>(0h18), remapindex_30) when _T_3314 : connect remapVecData[30], Queue32_UInt8_56.io.deq.bits connect remapVecValids[30], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[30] node _T_3315 = eq(UInt<5>(0h19), remapindex_30) when _T_3315 : connect remapVecData[30], Queue32_UInt8_57.io.deq.bits connect remapVecValids[30], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[30] node _T_3316 = eq(UInt<5>(0h1a), remapindex_30) when _T_3316 : connect remapVecData[30], Queue32_UInt8_58.io.deq.bits connect remapVecValids[30], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[30] node _T_3317 = eq(UInt<5>(0h1b), remapindex_30) when _T_3317 : connect remapVecData[30], Queue32_UInt8_59.io.deq.bits connect remapVecValids[30], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[30] node _T_3318 = eq(UInt<5>(0h1c), remapindex_30) when _T_3318 : connect remapVecData[30], Queue32_UInt8_60.io.deq.bits connect remapVecValids[30], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[30] node _T_3319 = eq(UInt<5>(0h1d), remapindex_30) when _T_3319 : connect remapVecData[30], Queue32_UInt8_61.io.deq.bits connect remapVecValids[30], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[30] node _T_3320 = eq(UInt<5>(0h1e), remapindex_30) when _T_3320 : connect remapVecData[30], Queue32_UInt8_62.io.deq.bits connect remapVecValids[30], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[30] node _T_3321 = eq(UInt<5>(0h1f), remapindex_30) when _T_3321 : connect remapVecData[30], Queue32_UInt8_63.io.deq.bits connect remapVecValids[30], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[30] node _remapindex_T_31 = add(UInt<5>(0h1f), read_start_index) node remapindex_31 = rem(_remapindex_T_31, UInt<6>(0h20)) node _T_3322 = eq(UInt<1>(0h0), remapindex_31) when _T_3322 : connect remapVecData[31], Queue32_UInt8_32.io.deq.bits connect remapVecValids[31], Queue32_UInt8_32.io.deq.valid connect Queue32_UInt8_32.io.deq.ready, remapVecReadys[31] node _T_3323 = eq(UInt<1>(0h1), remapindex_31) when _T_3323 : connect remapVecData[31], Queue32_UInt8_33.io.deq.bits connect remapVecValids[31], Queue32_UInt8_33.io.deq.valid connect Queue32_UInt8_33.io.deq.ready, remapVecReadys[31] node _T_3324 = eq(UInt<2>(0h2), remapindex_31) when _T_3324 : connect remapVecData[31], Queue32_UInt8_34.io.deq.bits connect remapVecValids[31], Queue32_UInt8_34.io.deq.valid connect Queue32_UInt8_34.io.deq.ready, remapVecReadys[31] node _T_3325 = eq(UInt<2>(0h3), remapindex_31) when _T_3325 : connect remapVecData[31], Queue32_UInt8_35.io.deq.bits connect remapVecValids[31], Queue32_UInt8_35.io.deq.valid connect Queue32_UInt8_35.io.deq.ready, remapVecReadys[31] node _T_3326 = eq(UInt<3>(0h4), remapindex_31) when _T_3326 : connect remapVecData[31], Queue32_UInt8_36.io.deq.bits connect remapVecValids[31], Queue32_UInt8_36.io.deq.valid connect Queue32_UInt8_36.io.deq.ready, remapVecReadys[31] node _T_3327 = eq(UInt<3>(0h5), remapindex_31) when _T_3327 : connect remapVecData[31], Queue32_UInt8_37.io.deq.bits connect remapVecValids[31], Queue32_UInt8_37.io.deq.valid connect Queue32_UInt8_37.io.deq.ready, remapVecReadys[31] node _T_3328 = eq(UInt<3>(0h6), remapindex_31) when _T_3328 : connect remapVecData[31], Queue32_UInt8_38.io.deq.bits connect remapVecValids[31], Queue32_UInt8_38.io.deq.valid connect Queue32_UInt8_38.io.deq.ready, remapVecReadys[31] node _T_3329 = eq(UInt<3>(0h7), remapindex_31) when _T_3329 : connect remapVecData[31], Queue32_UInt8_39.io.deq.bits connect remapVecValids[31], Queue32_UInt8_39.io.deq.valid connect Queue32_UInt8_39.io.deq.ready, remapVecReadys[31] node _T_3330 = eq(UInt<4>(0h8), remapindex_31) when _T_3330 : connect remapVecData[31], Queue32_UInt8_40.io.deq.bits connect remapVecValids[31], Queue32_UInt8_40.io.deq.valid connect Queue32_UInt8_40.io.deq.ready, remapVecReadys[31] node _T_3331 = eq(UInt<4>(0h9), remapindex_31) when _T_3331 : connect remapVecData[31], Queue32_UInt8_41.io.deq.bits connect remapVecValids[31], Queue32_UInt8_41.io.deq.valid connect Queue32_UInt8_41.io.deq.ready, remapVecReadys[31] node _T_3332 = eq(UInt<4>(0ha), remapindex_31) when _T_3332 : connect remapVecData[31], Queue32_UInt8_42.io.deq.bits connect remapVecValids[31], Queue32_UInt8_42.io.deq.valid connect Queue32_UInt8_42.io.deq.ready, remapVecReadys[31] node _T_3333 = eq(UInt<4>(0hb), remapindex_31) when _T_3333 : connect remapVecData[31], Queue32_UInt8_43.io.deq.bits connect remapVecValids[31], Queue32_UInt8_43.io.deq.valid connect Queue32_UInt8_43.io.deq.ready, remapVecReadys[31] node _T_3334 = eq(UInt<4>(0hc), remapindex_31) when _T_3334 : connect remapVecData[31], Queue32_UInt8_44.io.deq.bits connect remapVecValids[31], Queue32_UInt8_44.io.deq.valid connect Queue32_UInt8_44.io.deq.ready, remapVecReadys[31] node _T_3335 = eq(UInt<4>(0hd), remapindex_31) when _T_3335 : connect remapVecData[31], Queue32_UInt8_45.io.deq.bits connect remapVecValids[31], Queue32_UInt8_45.io.deq.valid connect Queue32_UInt8_45.io.deq.ready, remapVecReadys[31] node _T_3336 = eq(UInt<4>(0he), remapindex_31) when _T_3336 : connect remapVecData[31], Queue32_UInt8_46.io.deq.bits connect remapVecValids[31], Queue32_UInt8_46.io.deq.valid connect Queue32_UInt8_46.io.deq.ready, remapVecReadys[31] node _T_3337 = eq(UInt<4>(0hf), remapindex_31) when _T_3337 : connect remapVecData[31], Queue32_UInt8_47.io.deq.bits connect remapVecValids[31], Queue32_UInt8_47.io.deq.valid connect Queue32_UInt8_47.io.deq.ready, remapVecReadys[31] node _T_3338 = eq(UInt<5>(0h10), remapindex_31) when _T_3338 : connect remapVecData[31], Queue32_UInt8_48.io.deq.bits connect remapVecValids[31], Queue32_UInt8_48.io.deq.valid connect Queue32_UInt8_48.io.deq.ready, remapVecReadys[31] node _T_3339 = eq(UInt<5>(0h11), remapindex_31) when _T_3339 : connect remapVecData[31], Queue32_UInt8_49.io.deq.bits connect remapVecValids[31], Queue32_UInt8_49.io.deq.valid connect Queue32_UInt8_49.io.deq.ready, remapVecReadys[31] node _T_3340 = eq(UInt<5>(0h12), remapindex_31) when _T_3340 : connect remapVecData[31], Queue32_UInt8_50.io.deq.bits connect remapVecValids[31], Queue32_UInt8_50.io.deq.valid connect Queue32_UInt8_50.io.deq.ready, remapVecReadys[31] node _T_3341 = eq(UInt<5>(0h13), remapindex_31) when _T_3341 : connect remapVecData[31], Queue32_UInt8_51.io.deq.bits connect remapVecValids[31], Queue32_UInt8_51.io.deq.valid connect Queue32_UInt8_51.io.deq.ready, remapVecReadys[31] node _T_3342 = eq(UInt<5>(0h14), remapindex_31) when _T_3342 : connect remapVecData[31], Queue32_UInt8_52.io.deq.bits connect remapVecValids[31], Queue32_UInt8_52.io.deq.valid connect Queue32_UInt8_52.io.deq.ready, remapVecReadys[31] node _T_3343 = eq(UInt<5>(0h15), remapindex_31) when _T_3343 : connect remapVecData[31], Queue32_UInt8_53.io.deq.bits connect remapVecValids[31], Queue32_UInt8_53.io.deq.valid connect Queue32_UInt8_53.io.deq.ready, remapVecReadys[31] node _T_3344 = eq(UInt<5>(0h16), remapindex_31) when _T_3344 : connect remapVecData[31], Queue32_UInt8_54.io.deq.bits connect remapVecValids[31], Queue32_UInt8_54.io.deq.valid connect Queue32_UInt8_54.io.deq.ready, remapVecReadys[31] node _T_3345 = eq(UInt<5>(0h17), remapindex_31) when _T_3345 : connect remapVecData[31], Queue32_UInt8_55.io.deq.bits connect remapVecValids[31], Queue32_UInt8_55.io.deq.valid connect Queue32_UInt8_55.io.deq.ready, remapVecReadys[31] node _T_3346 = eq(UInt<5>(0h18), remapindex_31) when _T_3346 : connect remapVecData[31], Queue32_UInt8_56.io.deq.bits connect remapVecValids[31], Queue32_UInt8_56.io.deq.valid connect Queue32_UInt8_56.io.deq.ready, remapVecReadys[31] node _T_3347 = eq(UInt<5>(0h19), remapindex_31) when _T_3347 : connect remapVecData[31], Queue32_UInt8_57.io.deq.bits connect remapVecValids[31], Queue32_UInt8_57.io.deq.valid connect Queue32_UInt8_57.io.deq.ready, remapVecReadys[31] node _T_3348 = eq(UInt<5>(0h1a), remapindex_31) when _T_3348 : connect remapVecData[31], Queue32_UInt8_58.io.deq.bits connect remapVecValids[31], Queue32_UInt8_58.io.deq.valid connect Queue32_UInt8_58.io.deq.ready, remapVecReadys[31] node _T_3349 = eq(UInt<5>(0h1b), remapindex_31) when _T_3349 : connect remapVecData[31], Queue32_UInt8_59.io.deq.bits connect remapVecValids[31], Queue32_UInt8_59.io.deq.valid connect Queue32_UInt8_59.io.deq.ready, remapVecReadys[31] node _T_3350 = eq(UInt<5>(0h1c), remapindex_31) when _T_3350 : connect remapVecData[31], Queue32_UInt8_60.io.deq.bits connect remapVecValids[31], Queue32_UInt8_60.io.deq.valid connect Queue32_UInt8_60.io.deq.ready, remapVecReadys[31] node _T_3351 = eq(UInt<5>(0h1d), remapindex_31) when _T_3351 : connect remapVecData[31], Queue32_UInt8_61.io.deq.bits connect remapVecValids[31], Queue32_UInt8_61.io.deq.valid connect Queue32_UInt8_61.io.deq.ready, remapVecReadys[31] node _T_3352 = eq(UInt<5>(0h1e), remapindex_31) when _T_3352 : connect remapVecData[31], Queue32_UInt8_62.io.deq.bits connect remapVecValids[31], Queue32_UInt8_62.io.deq.valid connect Queue32_UInt8_62.io.deq.ready, remapVecReadys[31] node _T_3353 = eq(UInt<5>(0h1f), remapindex_31) when _T_3353 : connect remapVecData[31], Queue32_UInt8_63.io.deq.bits connect remapVecValids[31], Queue32_UInt8_63.io.deq.valid connect Queue32_UInt8_63.io.deq.ready, remapVecReadys[31] node io_consumer_output_data_lo_lo_lo_lo = cat(remapVecData[1], remapVecData[0]) node io_consumer_output_data_lo_lo_lo_hi = cat(remapVecData[3], remapVecData[2]) node io_consumer_output_data_lo_lo_lo = cat(io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo) node io_consumer_output_data_lo_lo_hi_lo = cat(remapVecData[5], remapVecData[4]) node io_consumer_output_data_lo_lo_hi_hi = cat(remapVecData[7], remapVecData[6]) node io_consumer_output_data_lo_lo_hi = cat(io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo) node io_consumer_output_data_lo_lo = cat(io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo) node io_consumer_output_data_lo_hi_lo_lo = cat(remapVecData[9], remapVecData[8]) node io_consumer_output_data_lo_hi_lo_hi = cat(remapVecData[11], remapVecData[10]) node io_consumer_output_data_lo_hi_lo = cat(io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo) node io_consumer_output_data_lo_hi_hi_lo = cat(remapVecData[13], remapVecData[12]) node io_consumer_output_data_lo_hi_hi_hi = cat(remapVecData[15], remapVecData[14]) node io_consumer_output_data_lo_hi_hi = cat(io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo) node io_consumer_output_data_lo_hi = cat(io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo) node io_consumer_output_data_lo = cat(io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo) node io_consumer_output_data_hi_lo_lo_lo = cat(remapVecData[17], remapVecData[16]) node io_consumer_output_data_hi_lo_lo_hi = cat(remapVecData[19], remapVecData[18]) node io_consumer_output_data_hi_lo_lo = cat(io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo) node io_consumer_output_data_hi_lo_hi_lo = cat(remapVecData[21], remapVecData[20]) node io_consumer_output_data_hi_lo_hi_hi = cat(remapVecData[23], remapVecData[22]) node io_consumer_output_data_hi_lo_hi = cat(io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo) node io_consumer_output_data_hi_lo = cat(io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo) node io_consumer_output_data_hi_hi_lo_lo = cat(remapVecData[25], remapVecData[24]) node io_consumer_output_data_hi_hi_lo_hi = cat(remapVecData[27], remapVecData[26]) node io_consumer_output_data_hi_hi_lo = cat(io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo) node io_consumer_output_data_hi_hi_hi_lo = cat(remapVecData[29], remapVecData[28]) node io_consumer_output_data_hi_hi_hi_hi = cat(remapVecData[31], remapVecData[30]) node io_consumer_output_data_hi_hi_hi = cat(io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo) node io_consumer_output_data_hi_hi = cat(io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo) node io_consumer_output_data_hi = cat(io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo) node _io_consumer_output_data_T = cat(io_consumer_output_data_hi, io_consumer_output_data_lo) connect io.consumer.output_data, _io_consumer_output_data_T node _buf_last_T = add(len_already_consumed, io.consumer.user_consumed_bytes) node _buf_last_T_1 = tail(_buf_last_T, 1) node buf_last = eq(_buf_last_T_1, buf_info_queue.io.deq.bits.len_bytes) node _count_valids_T = add(remapVecValids[0], remapVecValids[1]) node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2]) node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3]) node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4]) node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5]) node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6]) node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7]) node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8]) node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9]) node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10]) node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11]) node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12]) node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13]) node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14]) node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15]) node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16]) node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17]) node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18]) node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19]) node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20]) node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21]) node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22]) node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23]) node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24]) node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25]) node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26]) node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27]) node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28]) node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29]) node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30]) node count_valids = add(_count_valids_T_29, remapVecValids[31]) node _unconsumed_bytes_so_far_T = sub(buf_info_queue.io.deq.bits.len_bytes, len_already_consumed) node unconsumed_bytes_so_far = tail(_unconsumed_bytes_so_far_T, 1) node _enough_data_T = geq(unconsumed_bytes_so_far, UInt<6>(0h20)) node _enough_data_T_1 = eq(count_valids, UInt<6>(0h20)) node _enough_data_T_2 = geq(count_valids, unconsumed_bytes_so_far) node enough_data = mux(_enough_data_T, _enough_data_T_1, _enough_data_T_2) node _io_consumer_available_output_bytes_T = geq(unconsumed_bytes_so_far, UInt<6>(0h20)) node _io_consumer_available_output_bytes_T_1 = mux(_io_consumer_available_output_bytes_T, UInt<6>(0h20), unconsumed_bytes_so_far) connect io.consumer.available_output_bytes, _io_consumer_available_output_bytes_T_1 node _io_consumer_output_last_chunk_T = leq(unconsumed_bytes_so_far, UInt<6>(0h20)) connect io.consumer.output_last_chunk, _io_consumer_output_last_chunk_T node _T_3354 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _T_3355 = and(_T_3354, enough_data) when _T_3355 : regreset loginfo_cycles_44 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_88 = add(loginfo_cycles_44, UInt<1>(0h1)) node _loginfo_cycles_T_89 = tail(_loginfo_cycles_T_88, 1) connect loginfo_cycles_44, _loginfo_cycles_T_89 node _T_3356 = asUInt(reset) node _T_3357 = eq(_T_3356, UInt<1>(0h0)) when _T_3357 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_44) : printf_88 node _T_3358 = asUInt(reset) node _T_3359 = eq(_T_3358, UInt<1>(0h0)) when _T_3359 : printf(clock, UInt<1>(0h1), "MEMLOADER READ: bytesread %d\n", io.consumer.user_consumed_bytes) : printf_89 node _io_consumer_output_valid_T = and(buf_info_queue.io.deq.valid, enough_data) connect io.consumer.output_valid, _io_consumer_output_valid_T node _remapVecReadys_0_T = lt(UInt<1>(0h0), io.consumer.user_consumed_bytes) node _remapVecReadys_0_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T_1, enough_data) node _remapVecReadys_0_T_3 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_2) connect remapVecReadys[0], _remapVecReadys_0_T_3 node _remapVecReadys_1_T = lt(UInt<1>(0h1), io.consumer.user_consumed_bytes) node _remapVecReadys_1_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T_1, enough_data) node _remapVecReadys_1_T_3 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_2) connect remapVecReadys[1], _remapVecReadys_1_T_3 node _remapVecReadys_2_T = lt(UInt<2>(0h2), io.consumer.user_consumed_bytes) node _remapVecReadys_2_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T_1, enough_data) node _remapVecReadys_2_T_3 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_2) connect remapVecReadys[2], _remapVecReadys_2_T_3 node _remapVecReadys_3_T = lt(UInt<2>(0h3), io.consumer.user_consumed_bytes) node _remapVecReadys_3_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T_1, enough_data) node _remapVecReadys_3_T_3 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_2) connect remapVecReadys[3], _remapVecReadys_3_T_3 node _remapVecReadys_4_T = lt(UInt<3>(0h4), io.consumer.user_consumed_bytes) node _remapVecReadys_4_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T_1, enough_data) node _remapVecReadys_4_T_3 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_2) connect remapVecReadys[4], _remapVecReadys_4_T_3 node _remapVecReadys_5_T = lt(UInt<3>(0h5), io.consumer.user_consumed_bytes) node _remapVecReadys_5_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T_1, enough_data) node _remapVecReadys_5_T_3 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_2) connect remapVecReadys[5], _remapVecReadys_5_T_3 node _remapVecReadys_6_T = lt(UInt<3>(0h6), io.consumer.user_consumed_bytes) node _remapVecReadys_6_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T_1, enough_data) node _remapVecReadys_6_T_3 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_2) connect remapVecReadys[6], _remapVecReadys_6_T_3 node _remapVecReadys_7_T = lt(UInt<3>(0h7), io.consumer.user_consumed_bytes) node _remapVecReadys_7_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T_1, enough_data) node _remapVecReadys_7_T_3 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_2) connect remapVecReadys[7], _remapVecReadys_7_T_3 node _remapVecReadys_8_T = lt(UInt<4>(0h8), io.consumer.user_consumed_bytes) node _remapVecReadys_8_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T_1, enough_data) node _remapVecReadys_8_T_3 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_2) connect remapVecReadys[8], _remapVecReadys_8_T_3 node _remapVecReadys_9_T = lt(UInt<4>(0h9), io.consumer.user_consumed_bytes) node _remapVecReadys_9_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T_1, enough_data) node _remapVecReadys_9_T_3 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_2) connect remapVecReadys[9], _remapVecReadys_9_T_3 node _remapVecReadys_10_T = lt(UInt<4>(0ha), io.consumer.user_consumed_bytes) node _remapVecReadys_10_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T_1, enough_data) node _remapVecReadys_10_T_3 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_2) connect remapVecReadys[10], _remapVecReadys_10_T_3 node _remapVecReadys_11_T = lt(UInt<4>(0hb), io.consumer.user_consumed_bytes) node _remapVecReadys_11_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T_1, enough_data) node _remapVecReadys_11_T_3 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_2) connect remapVecReadys[11], _remapVecReadys_11_T_3 node _remapVecReadys_12_T = lt(UInt<4>(0hc), io.consumer.user_consumed_bytes) node _remapVecReadys_12_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T_1, enough_data) node _remapVecReadys_12_T_3 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_2) connect remapVecReadys[12], _remapVecReadys_12_T_3 node _remapVecReadys_13_T = lt(UInt<4>(0hd), io.consumer.user_consumed_bytes) node _remapVecReadys_13_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T_1, enough_data) node _remapVecReadys_13_T_3 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_2) connect remapVecReadys[13], _remapVecReadys_13_T_3 node _remapVecReadys_14_T = lt(UInt<4>(0he), io.consumer.user_consumed_bytes) node _remapVecReadys_14_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T_1, enough_data) node _remapVecReadys_14_T_3 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_2) connect remapVecReadys[14], _remapVecReadys_14_T_3 node _remapVecReadys_15_T = lt(UInt<4>(0hf), io.consumer.user_consumed_bytes) node _remapVecReadys_15_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T_1, enough_data) node _remapVecReadys_15_T_3 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_2) connect remapVecReadys[15], _remapVecReadys_15_T_3 node _remapVecReadys_16_T = lt(UInt<5>(0h10), io.consumer.user_consumed_bytes) node _remapVecReadys_16_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T_1, enough_data) node _remapVecReadys_16_T_3 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_2) connect remapVecReadys[16], _remapVecReadys_16_T_3 node _remapVecReadys_17_T = lt(UInt<5>(0h11), io.consumer.user_consumed_bytes) node _remapVecReadys_17_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T_1, enough_data) node _remapVecReadys_17_T_3 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_2) connect remapVecReadys[17], _remapVecReadys_17_T_3 node _remapVecReadys_18_T = lt(UInt<5>(0h12), io.consumer.user_consumed_bytes) node _remapVecReadys_18_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T_1, enough_data) node _remapVecReadys_18_T_3 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_2) connect remapVecReadys[18], _remapVecReadys_18_T_3 node _remapVecReadys_19_T = lt(UInt<5>(0h13), io.consumer.user_consumed_bytes) node _remapVecReadys_19_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T_1, enough_data) node _remapVecReadys_19_T_3 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_2) connect remapVecReadys[19], _remapVecReadys_19_T_3 node _remapVecReadys_20_T = lt(UInt<5>(0h14), io.consumer.user_consumed_bytes) node _remapVecReadys_20_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T_1, enough_data) node _remapVecReadys_20_T_3 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_2) connect remapVecReadys[20], _remapVecReadys_20_T_3 node _remapVecReadys_21_T = lt(UInt<5>(0h15), io.consumer.user_consumed_bytes) node _remapVecReadys_21_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T_1, enough_data) node _remapVecReadys_21_T_3 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_2) connect remapVecReadys[21], _remapVecReadys_21_T_3 node _remapVecReadys_22_T = lt(UInt<5>(0h16), io.consumer.user_consumed_bytes) node _remapVecReadys_22_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T_1, enough_data) node _remapVecReadys_22_T_3 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_2) connect remapVecReadys[22], _remapVecReadys_22_T_3 node _remapVecReadys_23_T = lt(UInt<5>(0h17), io.consumer.user_consumed_bytes) node _remapVecReadys_23_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T_1, enough_data) node _remapVecReadys_23_T_3 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_2) connect remapVecReadys[23], _remapVecReadys_23_T_3 node _remapVecReadys_24_T = lt(UInt<5>(0h18), io.consumer.user_consumed_bytes) node _remapVecReadys_24_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T_1, enough_data) node _remapVecReadys_24_T_3 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_2) connect remapVecReadys[24], _remapVecReadys_24_T_3 node _remapVecReadys_25_T = lt(UInt<5>(0h19), io.consumer.user_consumed_bytes) node _remapVecReadys_25_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T_1, enough_data) node _remapVecReadys_25_T_3 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_2) connect remapVecReadys[25], _remapVecReadys_25_T_3 node _remapVecReadys_26_T = lt(UInt<5>(0h1a), io.consumer.user_consumed_bytes) node _remapVecReadys_26_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T_1, enough_data) node _remapVecReadys_26_T_3 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_2) connect remapVecReadys[26], _remapVecReadys_26_T_3 node _remapVecReadys_27_T = lt(UInt<5>(0h1b), io.consumer.user_consumed_bytes) node _remapVecReadys_27_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T_1, enough_data) node _remapVecReadys_27_T_3 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_2) connect remapVecReadys[27], _remapVecReadys_27_T_3 node _remapVecReadys_28_T = lt(UInt<5>(0h1c), io.consumer.user_consumed_bytes) node _remapVecReadys_28_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T_1, enough_data) node _remapVecReadys_28_T_3 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_2) connect remapVecReadys[28], _remapVecReadys_28_T_3 node _remapVecReadys_29_T = lt(UInt<5>(0h1d), io.consumer.user_consumed_bytes) node _remapVecReadys_29_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T_1, enough_data) node _remapVecReadys_29_T_3 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_2) connect remapVecReadys[29], _remapVecReadys_29_T_3 node _remapVecReadys_30_T = lt(UInt<5>(0h1e), io.consumer.user_consumed_bytes) node _remapVecReadys_30_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T_1, enough_data) node _remapVecReadys_30_T_3 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_2) connect remapVecReadys[30], _remapVecReadys_30_T_3 node _remapVecReadys_31_T = lt(UInt<5>(0h1f), io.consumer.user_consumed_bytes) node _remapVecReadys_31_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T_1, enough_data) node _remapVecReadys_31_T_3 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_2) connect remapVecReadys[31], _remapVecReadys_31_T_3 node _T_3360 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _T_3361 = and(_T_3360, enough_data) when _T_3361 : node _read_start_index_T = add(read_start_index, io.consumer.user_consumed_bytes) node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20)) connect read_start_index, _read_start_index_T_1 node _buf_info_queue_io_deq_ready_T = and(io.consumer.output_ready, enough_data) node _buf_info_queue_io_deq_ready_T_1 = and(_buf_info_queue_io_deq_ready_T, buf_last) connect buf_info_queue.io.deq.ready, _buf_info_queue_io_deq_ready_T_1 node _T_3362 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _T_3363 = and(_T_3362, enough_data) when _T_3363 : when buf_last : connect len_already_consumed, UInt<1>(0h0) else : node _len_already_consumed_T = add(len_already_consumed, io.consumer.user_consumed_bytes) node _len_already_consumed_T_1 = tail(_len_already_consumed_T, 1) connect len_already_consumed, _len_already_consumed_T_1	module LZ77HashMatcherMemLoader( // @[LZ77HashMatcherMemLoader.scala:17:7] input clock, // @[LZ77HashMatcherMemLoader.scala:17:7] input reset, // @[LZ77HashMatcherMemLoader.scala:17:7] input io_l2helperUser_req_ready, // @[LZ77HashMatcherMemLoader.scala:20:14] output io_l2helperUser_req_valid, // @[LZ77HashMatcherMemLoader.scala:20:14] output [70:0] io_l2helperUser_req_bits_addr, // @[LZ77HashMatcherMemLoader.scala:20:14] output io_l2helperUser_resp_ready, // @[LZ77HashMatcherMemLoader.scala:20:14] input io_l2helperUser_resp_valid, // @[LZ77HashMatcherMemLoader.scala:20:14] input [255:0] io_l2helperUser_resp_bits_data, // @[LZ77HashMatcherMemLoader.scala:20:14] input io_l2helperUser_no_memops_inflight, // @[LZ77HashMatcherMemLoader.scala:20:14] output io_src_info_ready, // @[LZ77HashMatcherMemLoader.scala:20:14] input io_src_info_valid, // @[LZ77HashMatcherMemLoader.scala:20:14] input [63:0] io_src_info_bits_ip, // @[LZ77HashMatcherMemLoader.scala:20:14] input [63:0] io_src_info_bits_isize, // @[LZ77HashMatcherMemLoader.scala:20:14] input [5:0] io_consumer_user_consumed_bytes, // @[LZ77HashMatcherMemLoader.scala:20:14] output [5:0] io_consumer_available_output_bytes, // @[LZ77HashMatcherMemLoader.scala:20:14] output io_consumer_output_valid, // @[LZ77HashMatcherMemLoader.scala:20:14] input io_consumer_output_ready, // @[LZ77HashMatcherMemLoader.scala:20:14] output [255:0] io_consumer_output_data, // @[LZ77HashMatcherMemLoader.scala:20:14] output io_consumer_output_last_chunk, // @[LZ77HashMatcherMemLoader.scala:20:14] output io_optional_hbsram_write_valid, // @[LZ77HashMatcherMemLoader.scala:20:14] output [255:0] io_optional_hbsram_write_bits_data, // @[LZ77HashMatcherMemLoader.scala:20:14] output [5:0] io_optional_hbsram_write_bits_valid_bytes // @[LZ77HashMatcherMemLoader.scala:20:14] ); wire _Queue32_UInt8_63_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_63_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_63_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_62_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_62_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_62_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_61_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_61_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_61_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_60_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_60_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_60_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_59_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_59_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_59_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_58_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_58_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_58_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_57_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_57_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_57_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_56_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_56_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_56_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_55_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_55_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_55_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_54_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_54_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_54_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_53_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_53_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_53_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_52_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_52_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_52_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_51_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_51_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_51_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_50_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_50_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_50_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_49_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_49_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_49_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_48_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_48_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_48_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_47_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_47_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_47_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_46_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_46_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_46_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_45_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_45_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_45_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_44_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_44_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_44_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_43_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_43_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_43_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_42_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_42_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_42_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_41_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_41_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_41_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_40_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_40_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_40_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_39_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_39_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_39_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_38_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_38_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_38_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_37_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_37_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_37_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_36_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_36_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_36_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_35_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_35_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_35_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_34_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_34_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_34_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_33_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_33_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_33_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_32_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56] wire [7:0] _Queue32_UInt8_32_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:113:56] wire _Queue32_UInt8_31_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_31_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_31_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_30_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_30_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_30_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_29_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_29_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_29_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_28_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_28_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_28_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_27_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_27_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_27_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_26_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_26_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_26_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_25_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_25_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_25_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_24_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_24_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_24_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_23_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_23_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_23_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_22_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_22_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_22_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_21_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_21_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_21_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_20_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_20_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_20_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_19_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_19_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_19_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_18_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_18_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_18_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_17_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_17_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_17_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_16_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_16_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_16_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_15_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_15_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_15_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_14_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_14_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_14_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_13_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_13_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_13_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_12_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_12_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_12_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_11_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_11_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_11_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_10_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_10_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_10_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_9_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_9_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_9_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_8_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_8_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_8_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_7_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_7_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_7_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_6_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_6_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_6_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_5_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_5_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_5_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_4_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_4_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_4_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_3_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_3_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_3_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_2_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_2_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_2_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_1_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_1_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_1_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _Queue32_UInt8_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:112:52] wire [7:0] _Queue32_UInt8_io_deq_bits; // @[LZ77HashMatcherMemLoader.scala:112:52] wire _load_info_queue_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:33:31] wire _load_info_queue_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:33:31] wire [4:0] _load_info_queue_io_deq_bits_start_byte; // @[LZ77HashMatcherMemLoader.scala:33:31] wire [4:0] _load_info_queue_io_deq_bits_end_byte; // @[LZ77HashMatcherMemLoader.scala:33:31] wire _buf_info_queue_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:31:30] wire _buf_info_queue_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:31:30] wire [63:0] _buf_info_queue_io_deq_bits_len_bytes; // @[LZ77HashMatcherMemLoader.scala:31:30] wire io_l2helperUser_req_ready_0 = io_l2helperUser_req_ready; // @[LZ77HashMatcherMemLoader.scala:17:7] wire io_l2helperUser_resp_valid_0 = io_l2helperUser_resp_valid; // @[LZ77HashMatcherMemLoader.scala:17:7] wire [255:0] io_l2helperUser_resp_bits_data_0 = io_l2helperUser_resp_bits_data; // @[LZ77HashMatcherMemLoader.scala:17:7] wire io_l2helperUser_no_memops_inflight_0 = io_l2helperUser_no_memops_inflight; // @[LZ77HashMatcherMemLoader.scala:17:7] wire io_src_info_valid_0 = io_src_info_valid; // @[LZ77HashMatcherMemLoader.scala:17:7] wire [63:0] io_src_info_bits_ip_0 = io_src_info_bits_ip; // @[LZ77HashMatcherMemLoader.scala:17:7] wire [63:0] io_src_info_bits_isize_0 = io_src_info_bits_isize; // @[LZ77HashMatcherMemLoader.scala:17:7] wire [5:0] io_consumer_user_consumed_bytes_0 = io_consumer_user_consumed_bytes; // @[LZ77HashMatcherMemLoader.scala:17:7] wire io_consumer_output_ready_0 = io_consumer_output_ready; // @[LZ77HashMatcherMemLoader.scala:17:7] wire [2:0] io_l2helperUser_req_bits_size = 3'h5; // @[LZ77HashMatcherMemLoader.scala:17:7] wire [255:0] io_l2helperUser_req_bits_data = 256'h0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire io_l2helperUser_req_bits_cmd = 1'h0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire _io_l2helperUser_req_valid_T_1; // @[Misc.scala:26:53] wire [70:0] _io_l2helperUser_req_bits_addr_T_2; // @[LZ77HashMatcherMemLoader.scala:101:62] wire _io_l2helperUser_resp_ready_T; // @[Misc.scala:26:53] wire _io_src_info_ready_T_3; // @[Misc.scala:26:53] wire _io_consumer_output_valid_T; // @[Misc.scala:26:53] wire [255:0] _io_consumer_output_data_T; // @[LZ77HashMatcherMemLoader.scala:207:33] wire _io_consumer_output_last_chunk_T; // @[LZ77HashMatcherMemLoader.scala:222:61] wire _io_optional_hbsram_write_valid_T_1; // @[LZ77HashMatcherMemLoader.scala:157:61] wire [255:0] memresp_bits_shifted; // @[LZ77HashMatcherMemLoader.scala:122:61] wire [5:0] len_to_write; // @[LZ77HashMatcherMemLoader.scala:137:102] wire [70:0] io_l2helperUser_req_bits_addr_0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire io_l2helperUser_req_valid_0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire io_l2helperUser_resp_ready_0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire io_src_info_ready_0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire [5:0] io_consumer_available_output_bytes_0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire io_consumer_output_valid_0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire [255:0] io_consumer_output_data_0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire io_consumer_output_last_chunk_0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire [255:0] io_optional_hbsram_write_bits_data_0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire [5:0] io_optional_hbsram_write_bits_valid_bytes_0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire io_optional_hbsram_write_valid_0; // @[LZ77HashMatcherMemLoader.scala:17:7] wire [63:0] base_addr_start_index = {59'h0, io_src_info_bits_ip_0[4:0]}; // @[LZ77HashMatcherMemLoader.scala:17:7, :37:51] wire [64:0] _GEN = {1'h0, io_src_info_bits_isize_0} + {1'h0, base_addr_start_index}; // @[LZ77HashMatcherMemLoader.scala:17:7, :37:51, :38:35] wire [64:0] _aligned_loadlen_T; // @[LZ77HashMatcherMemLoader.scala:38:35] assign _aligned_loadlen_T = _GEN; // @[LZ77HashMatcherMemLoader.scala:38:35] wire [64:0] _base_addr_end_index_T; // @[LZ77HashMatcherMemLoader.scala:39:39] assign _base_addr_end_index_T = _GEN; // @[LZ77HashMatcherMemLoader.scala:38:35, :39:39] wire [64:0] _base_addr_end_index_inclusive_T; // @[LZ77HashMatcherMemLoader.scala:40:49] assign _base_addr_end_index_inclusive_T = _GEN; // @[LZ77HashMatcherMemLoader.scala:38:35, :40:49] wire [63:0] aligned_loadlen = _aligned_loadlen_T[63:0]; // @[LZ77HashMatcherMemLoader.scala:38:35] wire [63:0] _base_addr_end_index_T_1 = _base_addr_end_index_T[63:0]; // @[LZ77HashMatcherMemLoader.scala:39:39] wire [63:0] base_addr_end_index = {59'h0, _base_addr_end_index_T_1[4:0]}; // @[LZ77HashMatcherMemLoader.scala:39:{39,64}] wire [63:0] _base_addr_end_index_inclusive_T_1 = _base_addr_end_index_inclusive_T[63:0]; // @[LZ77HashMatcherMemLoader.scala:40:49] wire [64:0] _base_addr_end_index_inclusive_T_2 = {1'h0, _base_addr_end_index_inclusive_T_1} - 65'h1; // @[LZ77HashMatcherMemLoader.scala:40:{49,73}] wire [63:0] _base_addr_end_index_inclusive_T_3 = _base_addr_end_index_inclusive_T_2[63:0]; // @[LZ77HashMatcherMemLoader.scala:40:73] wire [63:0] base_addr_end_index_inclusive = {59'h0, _base_addr_end_index_inclusive_T_3[4:0]}; // @[LZ77HashMatcherMemLoader.scala:40:{73,80}] wire [63:0] _extra_word_T = {59'h0, aligned_loadlen[4:0]}; // @[LZ77HashMatcherMemLoader.scala:38:35, :41:38] wire extra_word = \|_extra_word_T; // @[LZ77HashMatcherMemLoader.scala:41:{38,48}] wire [63:0] _base_addr_bytes_aligned_T = {5'h0, io_src_info_bits_ip_0[63:5]}; // @[LZ77HashMatcherMemLoader.scala:17:7, :43:50] wire [70:0] base_addr_bytes_aligned = {2'h0, _base_addr_bytes_aligned_T, 5'h0}; // @[LZ77HashMatcherMemLoader.scala:43:{50,58}] wire [63:0] _words_to_load_T = {5'h0, aligned_loadlen[63:5]}; // @[LZ77HashMatcherMemLoader.scala:38:35, :44:40] wire [64:0] _words_to_load_T_1 = {1'h0, _words_to_load_T} + {64'h0, extra_word}; // @[LZ77HashMatcherMemLoader.scala:41:48, :44:{40,48}] wire [63:0] words_to_load = _words_to_load_T_1[63:0]; // @[LZ77HashMatcherMemLoader.scala:44:48] wire [64:0] _words_to_load_minus_one_T = {1'h0, words_to_load} - 65'h1; // @[LZ77HashMatcherMemLoader.scala:44:48, :45:47] wire [63:0] words_to_load_minus_one = _words_to_load_minus_one_T[63:0]; // @[LZ77HashMatcherMemLoader.scala:45:47] reg print_not_done; // @[LZ77HashMatcherMemLoader.scala:48:31] wire _T = io_src_info_valid_0 & print_not_done; // @[LZ77HashMatcherMemLoader.scala:17:7, :48:31, :50:27] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] wire _T_41 = io_src_info_ready_0 & io_src_info_valid_0; // @[Decoupled.scala:51:35] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] addrinc; // @[LZ77HashMatcherMemLoader.scala:80:24] wire _GEN_0 = addrinc == 64'h0; // @[LZ77HashMatcherMemLoader.scala:80:24, :82:57] wire _load_info_queue_io_enq_bits_start_byte_T; // @[LZ77HashMatcherMemLoader.scala:82:57] assign _load_info_queue_io_enq_bits_start_byte_T = _GEN_0; // @[LZ77HashMatcherMemLoader.scala:82:57] wire _buf_info_queue_io_enq_valid_T; // @[LZ77HashMatcherMemLoader.scala:96:53] assign _buf_info_queue_io_enq_valid_T = _GEN_0; // @[LZ77HashMatcherMemLoader.scala:82:57, :96:53] wire [63:0] _load_info_queue_io_enq_bits_start_byte_T_1 = _load_info_queue_io_enq_bits_start_byte_T ? base_addr_start_index : 64'h0; // @[LZ77HashMatcherMemLoader.scala:37:51, :82:{48,57}] wire _T_49 = addrinc == words_to_load_minus_one; // @[LZ77HashMatcherMemLoader.scala:45:47, :80:24, :83:55] wire _load_info_queue_io_enq_bits_end_byte_T; // @[LZ77HashMatcherMemLoader.scala:83:55] assign _load_info_queue_io_enq_bits_end_byte_T = _T_49; // @[LZ77HashMatcherMemLoader.scala:83:55] wire _io_src_info_ready_T; // @[LZ77HashMatcherMemLoader.scala:93:53] assign _io_src_info_ready_T = _T_49; // @[LZ77HashMatcherMemLoader.scala:83:55, :93:53] wire [63:0] _load_info_queue_io_enq_bits_end_byte_T_1 = _load_info_queue_io_enq_bits_end_byte_T ? base_addr_end_index_inclusive : 64'h1F; // @[LZ77HashMatcherMemLoader.scala:40:80, :83:{46,55}] wire _T_51 = io_l2helperUser_req_ready_0 & io_src_info_valid_0; // @[Misc.scala:29:18] wire _buf_info_queue_io_enq_valid_T_1; // @[Misc.scala:26:53] assign _buf_info_queue_io_enq_valid_T_1 = _T_51; // @[Misc.scala:26:53, :29:18] wire _load_info_queue_io_enq_valid_T; // @[Misc.scala:26:53] assign _load_info_queue_io_enq_valid_T = _T_51; // @[Misc.scala:26:53, :29:18] wire [64:0] _addrinc_T = {1'h0, addrinc} + 65'h1; // @[LZ77HashMatcherMemLoader.scala:80:24, :89:24] wire [63:0] _addrinc_T_1 = _addrinc_T[63:0]; // @[LZ77HashMatcherMemLoader.scala:89:24] wire _io_src_info_ready_T_1 = io_l2helperUser_req_ready_0 & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53] wire _io_src_info_ready_T_2 = _io_src_info_ready_T_1 & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53] assign _io_src_info_ready_T_3 = _io_src_info_ready_T_2 & _io_src_info_ready_T; // @[Misc.scala:26:53] assign io_src_info_ready_0 = _io_src_info_ready_T_3; // @[Misc.scala:26:53] wire _buf_info_queue_io_enq_valid_T_2 = _buf_info_queue_io_enq_valid_T_1 & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53] wire _buf_info_queue_io_enq_valid_T_3 = _buf_info_queue_io_enq_valid_T_2 & _buf_info_queue_io_enq_valid_T; // @[Misc.scala:26:53] wire _load_info_queue_io_enq_valid_T_1 = _load_info_queue_io_enq_valid_T & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53] wire [68:0] _io_l2helperUser_req_bits_addr_T = {addrinc, 5'h0}; // @[LZ77HashMatcherMemLoader.scala:80:24, :101:73] wire [71:0] _io_l2helperUser_req_bits_addr_T_1 = {1'h0, base_addr_bytes_aligned} + {3'h0, _io_l2helperUser_req_bits_addr_T}; // @[LZ77HashMatcherMemLoader.scala:43:58, :101:{62,73}] assign _io_l2helperUser_req_bits_addr_T_2 = _io_l2helperUser_req_bits_addr_T_1[70:0]; // @[LZ77HashMatcherMemLoader.scala:101:62] assign io_l2helperUser_req_bits_addr_0 = _io_l2helperUser_req_bits_addr_T_2; // @[LZ77HashMatcherMemLoader.scala:17:7, :101:62] wire _io_l2helperUser_req_valid_T = io_src_info_valid_0 & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53] assign _io_l2helperUser_req_valid_T_1 = _io_l2helperUser_req_valid_T & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53] assign io_l2helperUser_req_valid_0 = _io_l2helperUser_req_valid_T_1; // @[Misc.scala:26:53] reg [5:0] write_start_index; // @[LZ77HashMatcherMemLoader.scala:110:34] wire [7:0] align_shamt = {_load_info_queue_io_deq_bits_start_byte, 3'h0}; // @[LZ77HashMatcherMemLoader.scala:33:31, :121:61] assign memresp_bits_shifted = io_l2helperUser_resp_bits_data_0 >> align_shamt; // @[LZ77HashMatcherMemLoader.scala:17:7, :121:61, :122:61] assign io_optional_hbsram_write_bits_data_0 = memresp_bits_shifted; // @[LZ77HashMatcherMemLoader.scala:17:7, :122:61] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[LZ77HashMatcherMemLoader.scala:110:34, :129:34] wire [6:0] _GEN_1 = _idx_T % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx = _GEN_1[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_2 = _idx_T_1 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_1 = _GEN_2[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_3 = _idx_T_2 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_2 = _GEN_3[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_4 = _idx_T_3 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_3 = _GEN_4[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_5 = _idx_T_4 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_4 = _GEN_5[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_6 = _idx_T_5 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_5 = _GEN_6[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_7 = _idx_T_6 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_6 = _GEN_7[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_8 = _idx_T_7 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_7 = _GEN_8[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_9 = _idx_T_8 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_8 = _GEN_9[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_10 = _idx_T_9 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_9 = _GEN_10[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_11 = _idx_T_10 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_10 = _GEN_11[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_12 = _idx_T_11 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_11 = _GEN_12[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_13 = _idx_T_12 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_12 = _GEN_13[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_14 = _idx_T_13 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_13 = _GEN_14[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_15 = _idx_T_14 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_14 = _GEN_15[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_16 = _idx_T_15 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_15 = _GEN_16[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_17 = _idx_T_16 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_16 = _GEN_17[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_18 = _idx_T_17 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_17 = _GEN_18[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_19 = _idx_T_18 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_18 = _GEN_19[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_20 = _idx_T_19 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_19 = _GEN_20[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_21 = _idx_T_20 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_20 = _GEN_21[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_22 = _idx_T_21 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_21 = _GEN_22[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_23 = _idx_T_22 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_22 = _GEN_23[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_24 = _idx_T_23 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_23 = _GEN_24[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_25 = _idx_T_24 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_24 = _GEN_25[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_26 = _idx_T_25 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_25 = _GEN_26[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_27 = _idx_T_26 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_26 = _GEN_27[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_28 = _idx_T_27 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_27 = _GEN_28[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_29 = _idx_T_28 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_28 = _GEN_29[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_30 = _idx_T_29 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_29 = _GEN_30[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_31 = _idx_T_30 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_30 = _GEN_31[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[LZ77HashMatcherMemLoader.scala:129:34] wire [6:0] _GEN_32 = _idx_T_31 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:129:{34,48}] wire [5:0] idx_31 = _GEN_32[5:0]; // @[LZ77HashMatcherMemLoader.scala:129:48] wire [5:0] _len_to_write_T = {1'h0, _load_info_queue_io_deq_bits_end_byte} - {1'h0, _load_info_queue_io_deq_bits_start_byte}; // @[LZ77HashMatcherMemLoader.scala:33:31, :137:60] wire [4:0] _len_to_write_T_1 = _len_to_write_T[4:0]; // @[LZ77HashMatcherMemLoader.scala:137:60] assign len_to_write = {1'h0, _len_to_write_T_1} + 6'h1; // @[LZ77HashMatcherMemLoader.scala:137:{60,102}] assign io_optional_hbsram_write_bits_valid_bytes_0 = len_to_write; // @[LZ77HashMatcherMemLoader.scala:17:7, :137:102] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, len_to_write}; // @[LZ77HashMatcherMemLoader.scala:129:34, :137:102, :139:47] wire [6:0] _GEN_33 = wrap_len_index_wide % 7'h20; // @[LZ77HashMatcherMemLoader.scala:139:47, :140:48] wire [5:0] wrap_len_index_end = _GEN_33[5:0]; // @[LZ77HashMatcherMemLoader.scala:140:48] wire wrapped = \|(wrap_len_index_wide[6:5]); // @[LZ77HashMatcherMemLoader.scala:139:47, :141:37] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] wire _all_queues_ready_T = _Queue32_UInt8_io_enq_ready & _Queue32_UInt8_1_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue32_UInt8_2_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue32_UInt8_3_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue32_UInt8_4_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue32_UInt8_5_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue32_UInt8_6_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue32_UInt8_7_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue32_UInt8_8_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue32_UInt8_9_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue32_UInt8_10_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue32_UInt8_11_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue32_UInt8_12_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue32_UInt8_13_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue32_UInt8_14_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue32_UInt8_15_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue32_UInt8_16_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue32_UInt8_17_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue32_UInt8_18_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue32_UInt8_19_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue32_UInt8_20_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue32_UInt8_21_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue32_UInt8_22_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue32_UInt8_23_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue32_UInt8_24_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue32_UInt8_25_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue32_UInt8_26_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue32_UInt8_27_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue32_UInt8_28_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue32_UInt8_29_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue32_UInt8_30_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue32_UInt8_31_io_enq_ready; // @[LZ77HashMatcherMemLoader.scala:112:52, :152:68] wire _load_info_queue_io_deq_ready_T = io_l2helperUser_resp_valid_0 & all_queues_ready; // @[Misc.scala:26:53] assign _io_l2helperUser_resp_ready_T = _load_info_queue_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53] assign io_l2helperUser_resp_ready_0 = _io_l2helperUser_resp_ready_T; // @[Misc.scala:26:53] wire _T_2199 = io_l2helperUser_resp_valid_0 & _load_info_queue_io_deq_valid; // @[Misc.scala:29:18] wire _io_optional_hbsram_write_valid_T; // @[Misc.scala:29:18] assign _io_optional_hbsram_write_valid_T = _T_2199; // @[Misc.scala:29:18] wire _resp_fire_allqueues_T; // @[Misc.scala:29:18] assign _resp_fire_allqueues_T = _T_2199; // @[Misc.scala:29:18] assign _io_optional_hbsram_write_valid_T_1 = _io_optional_hbsram_write_valid_T & all_queues_ready; // @[Misc.scala:29:18] assign io_optional_hbsram_write_valid_0 = _io_optional_hbsram_write_valid_T_1; // @[LZ77HashMatcherMemLoader.scala:17:7, :157:61] wire resp_fire_allqueues = _resp_fire_allqueues_T & all_queues_ready; // @[Misc.scala:29:18] wire _GEN_34 = write_start_index == 6'h0; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T = _GEN_34; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_3; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_3 = _GEN_34; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _use_this_queue_T_1 = \|wrap_len_index_end; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_2 = _use_this_queue_T \| _use_this_queue_T_1; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_4 = \|wrap_len_index_end; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77, :169:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_35 = write_start_index < 6'h2; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_6; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_6 = _GEN_35; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_9; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_9 = _GEN_35; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _use_this_queue_T_7 = \|(wrap_len_index_end[5:1]); // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 \| _use_this_queue_T_7; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_10 = \|(wrap_len_index_end[5:1]); // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77, :169:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_36 = write_start_index < 6'h3; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_12; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_12 = _GEN_36; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_15; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_15 = _GEN_36; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_37 = wrap_len_index_end > 6'h2; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_13; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_13 = _GEN_37; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_16; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_16 = _GEN_37; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 \| _use_this_queue_T_13; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_38 = write_start_index < 6'h4; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_18; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_18 = _GEN_38; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_21; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_21 = _GEN_38; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _use_this_queue_T_19 = \|(wrap_len_index_end[5:2]); // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 \| _use_this_queue_T_19; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_22 = \|(wrap_len_index_end[5:2]); // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77, :169:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_39 = write_start_index < 6'h5; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_24; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_24 = _GEN_39; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_27; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_27 = _GEN_39; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_40 = wrap_len_index_end > 6'h4; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_25; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_25 = _GEN_40; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_28; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_28 = _GEN_40; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 \| _use_this_queue_T_25; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_41 = write_start_index < 6'h6; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_30; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_30 = _GEN_41; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_33; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_33 = _GEN_41; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_42 = wrap_len_index_end > 6'h5; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_31; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_31 = _GEN_42; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_34; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_34 = _GEN_42; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 \| _use_this_queue_T_31; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_43 = write_start_index < 6'h7; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_36; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_36 = _GEN_43; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_39; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_39 = _GEN_43; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_44 = wrap_len_index_end > 6'h6; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_37; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_37 = _GEN_44; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_40; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_40 = _GEN_44; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 \| _use_this_queue_T_37; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_45 = write_start_index < 6'h8; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_42; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_42 = _GEN_45; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_45; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_45 = _GEN_45; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _use_this_queue_T_43 = \|(wrap_len_index_end[5:3]); // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 \| _use_this_queue_T_43; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_46 = \|(wrap_len_index_end[5:3]); // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77, :169:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_46 = write_start_index < 6'h9; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_48; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_48 = _GEN_46; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_51; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_51 = _GEN_46; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_47 = wrap_len_index_end > 6'h8; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_49; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_49 = _GEN_47; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_52; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_52 = _GEN_47; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 \| _use_this_queue_T_49; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_48 = write_start_index < 6'hA; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_54; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_54 = _GEN_48; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_57; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_57 = _GEN_48; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_49 = wrap_len_index_end > 6'h9; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_55; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_55 = _GEN_49; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_58; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_58 = _GEN_49; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 \| _use_this_queue_T_55; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_50 = write_start_index < 6'hB; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_60; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_60 = _GEN_50; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_63; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_63 = _GEN_50; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_51 = wrap_len_index_end > 6'hA; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_61; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_61 = _GEN_51; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_64; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_64 = _GEN_51; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 \| _use_this_queue_T_61; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_52 = write_start_index < 6'hC; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_66; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_66 = _GEN_52; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_69; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_69 = _GEN_52; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_53 = wrap_len_index_end > 6'hB; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_67; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_67 = _GEN_53; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_70; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_70 = _GEN_53; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 \| _use_this_queue_T_67; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_54 = write_start_index < 6'hD; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_72; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_72 = _GEN_54; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_75; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_75 = _GEN_54; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_55 = wrap_len_index_end > 6'hC; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_73; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_73 = _GEN_55; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_76; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_76 = _GEN_55; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 \| _use_this_queue_T_73; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_56 = write_start_index < 6'hE; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_78; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_78 = _GEN_56; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_81; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_81 = _GEN_56; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_57 = wrap_len_index_end > 6'hD; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_79; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_79 = _GEN_57; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_82; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_82 = _GEN_57; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 \| _use_this_queue_T_79; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_58 = write_start_index < 6'hF; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_84; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_84 = _GEN_58; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_87; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_87 = _GEN_58; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_59 = wrap_len_index_end > 6'hE; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_85; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_85 = _GEN_59; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_88; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_88 = _GEN_59; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 \| _use_this_queue_T_85; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_60 = write_start_index < 6'h10; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_90; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_90 = _GEN_60; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_93; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_93 = _GEN_60; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _use_this_queue_T_91 = \|(wrap_len_index_end[5:4]); // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 \| _use_this_queue_T_91; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_94 = \|(wrap_len_index_end[5:4]); // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77, :169:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_61 = write_start_index < 6'h11; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_96; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_96 = _GEN_61; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_99; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_99 = _GEN_61; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_62 = wrap_len_index_end > 6'h10; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_97; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_97 = _GEN_62; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_100; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_100 = _GEN_62; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 \| _use_this_queue_T_97; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_63 = write_start_index < 6'h12; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_102; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_102 = _GEN_63; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_105; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_105 = _GEN_63; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_64 = wrap_len_index_end > 6'h11; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_103; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_103 = _GEN_64; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_106; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_106 = _GEN_64; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 \| _use_this_queue_T_103; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_65 = write_start_index < 6'h13; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_108; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_108 = _GEN_65; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_111; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_111 = _GEN_65; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_66 = wrap_len_index_end > 6'h12; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_109; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_109 = _GEN_66; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_112; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_112 = _GEN_66; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 \| _use_this_queue_T_109; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_67 = write_start_index < 6'h14; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_114; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_114 = _GEN_67; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_117; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_117 = _GEN_67; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_68 = wrap_len_index_end > 6'h13; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_115; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_115 = _GEN_68; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_118; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_118 = _GEN_68; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 \| _use_this_queue_T_115; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_69 = write_start_index < 6'h15; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_120; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_120 = _GEN_69; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_123; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_123 = _GEN_69; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_70 = wrap_len_index_end > 6'h14; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_121; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_121 = _GEN_70; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_124; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_124 = _GEN_70; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 \| _use_this_queue_T_121; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_71 = write_start_index < 6'h16; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_126; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_126 = _GEN_71; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_129; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_129 = _GEN_71; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_72 = wrap_len_index_end > 6'h15; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_127; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_127 = _GEN_72; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_130; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_130 = _GEN_72; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 \| _use_this_queue_T_127; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_73 = write_start_index < 6'h17; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_132; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_132 = _GEN_73; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_135; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_135 = _GEN_73; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_74 = wrap_len_index_end > 6'h16; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_133; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_133 = _GEN_74; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_136; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_136 = _GEN_74; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 \| _use_this_queue_T_133; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_75 = write_start_index < 6'h18; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_138; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_138 = _GEN_75; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_141; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_141 = _GEN_75; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_76 = wrap_len_index_end > 6'h17; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_139; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_139 = _GEN_76; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_142; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_142 = _GEN_76; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 \| _use_this_queue_T_139; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_77 = write_start_index < 6'h19; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_144; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_144 = _GEN_77; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_147; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_147 = _GEN_77; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_78 = wrap_len_index_end > 6'h18; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_145; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_145 = _GEN_78; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_148; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_148 = _GEN_78; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 \| _use_this_queue_T_145; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_79 = write_start_index < 6'h1A; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_150; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_150 = _GEN_79; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_153; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_153 = _GEN_79; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_80 = wrap_len_index_end > 6'h19; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_151; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_151 = _GEN_80; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_154; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_154 = _GEN_80; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 \| _use_this_queue_T_151; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_81 = write_start_index < 6'h1B; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_156; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_156 = _GEN_81; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_159; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_159 = _GEN_81; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_82 = wrap_len_index_end > 6'h1A; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_157; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_157 = _GEN_82; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_160; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_160 = _GEN_82; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 \| _use_this_queue_T_157; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_83 = write_start_index < 6'h1C; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_162; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_162 = _GEN_83; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_165; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_165 = _GEN_83; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_84 = wrap_len_index_end > 6'h1B; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_163; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_163 = _GEN_84; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_166; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_166 = _GEN_84; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 \| _use_this_queue_T_163; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_85 = write_start_index < 6'h1D; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_168; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_168 = _GEN_85; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_171; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_171 = _GEN_85; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_86 = wrap_len_index_end > 6'h1C; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_169; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_169 = _GEN_86; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_172; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_172 = _GEN_86; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 \| _use_this_queue_T_169; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_87 = write_start_index < 6'h1E; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_174; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_174 = _GEN_87; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_177; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_177 = _GEN_87; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_88 = wrap_len_index_end > 6'h1D; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_175; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_175 = _GEN_88; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_178; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_178 = _GEN_88; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 \| _use_this_queue_T_175; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _GEN_89 = write_start_index < 6'h1F; // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_180; // @[LZ77HashMatcherMemLoader.scala:168:41] assign _use_this_queue_T_180 = _GEN_89; // @[LZ77HashMatcherMemLoader.scala:168:41] wire _use_this_queue_T_183; // @[LZ77HashMatcherMemLoader.scala:169:41] assign _use_this_queue_T_183 = _GEN_89; // @[LZ77HashMatcherMemLoader.scala:168:41, :169:41] wire _GEN_90 = wrap_len_index_end > 6'h1E; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_181; // @[LZ77HashMatcherMemLoader.scala:168:77] assign _use_this_queue_T_181 = _GEN_90; // @[LZ77HashMatcherMemLoader.scala:168:77] wire _use_this_queue_T_184; // @[LZ77HashMatcherMemLoader.scala:169:77] assign _use_this_queue_T_184 = _GEN_90; // @[LZ77HashMatcherMemLoader.scala:168:77, :169:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 \| _use_this_queue_T_181; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[LZ77HashMatcherMemLoader.scala:140:48, :168:77, :169:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 \| _use_this_queue_T_187; // @[LZ77HashMatcherMemLoader.scala:168:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[LZ77HashMatcherMemLoader.scala:110:34, :168:41, :169:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[LZ77HashMatcherMemLoader.scala:169:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[LZ77HashMatcherMemLoader.scala:141:37, :167:29, :168:63, :169:63] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_43; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_86 = {1'h0, loginfo_cycles_43} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_87 = _loginfo_cycles_T_86[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[LZ77HashMatcherMemLoader.scala:181:33] reg [63:0] len_already_consumed; // @[LZ77HashMatcherMemLoader.scala:184:37] wire [7:0] remapVecData_0; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_1; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_2; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_3; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_4; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_5; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_6; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_7; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_8; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_9; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_10; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_11; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_12; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_13; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_14; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_15; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_16; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_17; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_18; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_19; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_20; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_21; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_22; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_23; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_24; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_25; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_26; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_27; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_28; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_29; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_30; // @[LZ77HashMatcherMemLoader.scala:186:26] wire [7:0] remapVecData_31; // @[LZ77HashMatcherMemLoader.scala:186:26] wire remapVecValids_0; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_1; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_2; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_3; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_4; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_5; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_6; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_7; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_8; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_9; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_10; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_11; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_12; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_13; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_14; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_15; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_16; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_17; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_18; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_19; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_20; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_21; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_22; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_23; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_24; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_25; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_26; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_27; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_28; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_29; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_30; // @[LZ77HashMatcherMemLoader.scala:187:28] wire remapVecValids_31; // @[LZ77HashMatcherMemLoader.scala:187:28] wire _remapVecReadys_0_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_1_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_2_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_3_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_4_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_5_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_6_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_7_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_8_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_9_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_10_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_11_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_12_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_13_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_14_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_15_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_16_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_17_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_18_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_19_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_20_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_21_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_22_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_23_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_24_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_25_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_26_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_27_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_28_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_29_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_30_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire _remapVecReadys_31_T_3; // @[LZ77HashMatcherMemLoader.scala:238:78] wire remapVecReadys_0; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_1; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_2; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_3; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_4; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_5; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_6; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_7; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_8; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_9; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_10; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_11; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_12; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_13; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_14; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_15; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_16; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_17; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_18; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_19; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_20; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_21; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_22; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_23; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_24; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_25; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_26; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_27; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_28; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_29; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_30; // @[LZ77HashMatcherMemLoader.scala:188:28] wire remapVecReadys_31; // @[LZ77HashMatcherMemLoader.scala:188:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[LZ77HashMatcherMemLoader.scala:181:33, :198:33] wire [6:0] _GEN_91 = _remapindex_T % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex = _GEN_91[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2330 = remapindex == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2331 = remapindex == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2332 = remapindex == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2333 = remapindex == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2334 = remapindex == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2335 = remapindex == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2336 = remapindex == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2337 = remapindex == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2338 = remapindex == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2339 = remapindex == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2340 = remapindex == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2341 = remapindex == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2342 = remapindex == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2343 = remapindex == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2344 = remapindex == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2345 = remapindex == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2346 = remapindex == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2347 = remapindex == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2348 = remapindex == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2349 = remapindex == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2350 = remapindex == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2351 = remapindex == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2352 = remapindex == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2353 = remapindex == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2354 = remapindex == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2355 = remapindex == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2356 = remapindex == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2357 = remapindex == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2358 = remapindex == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2359 = remapindex == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2360 = remapindex == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2361 = remapindex == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_0 = _T_2361 ? _Queue32_UInt8_63_io_deq_bits : _T_2360 ? _Queue32_UInt8_62_io_deq_bits : _T_2359 ? _Queue32_UInt8_61_io_deq_bits : _T_2358 ? _Queue32_UInt8_60_io_deq_bits : _T_2357 ? _Queue32_UInt8_59_io_deq_bits : _T_2356 ? _Queue32_UInt8_58_io_deq_bits : _T_2355 ? _Queue32_UInt8_57_io_deq_bits : _T_2354 ? _Queue32_UInt8_56_io_deq_bits : _T_2353 ? _Queue32_UInt8_55_io_deq_bits : _T_2352 ? _Queue32_UInt8_54_io_deq_bits : _T_2351 ? _Queue32_UInt8_53_io_deq_bits : _T_2350 ? _Queue32_UInt8_52_io_deq_bits : _T_2349 ? _Queue32_UInt8_51_io_deq_bits : _T_2348 ? _Queue32_UInt8_50_io_deq_bits : _T_2347 ? _Queue32_UInt8_49_io_deq_bits : _T_2346 ? _Queue32_UInt8_48_io_deq_bits : _T_2345 ? _Queue32_UInt8_47_io_deq_bits : _T_2344 ? _Queue32_UInt8_46_io_deq_bits : _T_2343 ? _Queue32_UInt8_45_io_deq_bits : _T_2342 ? _Queue32_UInt8_44_io_deq_bits : _T_2341 ? _Queue32_UInt8_43_io_deq_bits : _T_2340 ? _Queue32_UInt8_42_io_deq_bits : _T_2339 ? _Queue32_UInt8_41_io_deq_bits : _T_2338 ? _Queue32_UInt8_40_io_deq_bits : _T_2337 ? _Queue32_UInt8_39_io_deq_bits : _T_2336 ? _Queue32_UInt8_38_io_deq_bits : _T_2335 ? _Queue32_UInt8_37_io_deq_bits : _T_2334 ? _Queue32_UInt8_36_io_deq_bits : _T_2333 ? _Queue32_UInt8_35_io_deq_bits : _T_2332 ? _Queue32_UInt8_34_io_deq_bits : _T_2331 ? _Queue32_UInt8_33_io_deq_bits : _T_2330 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_0 = _T_2361 ? _Queue32_UInt8_63_io_deq_valid : _T_2360 ? _Queue32_UInt8_62_io_deq_valid : _T_2359 ? _Queue32_UInt8_61_io_deq_valid : _T_2358 ? _Queue32_UInt8_60_io_deq_valid : _T_2357 ? _Queue32_UInt8_59_io_deq_valid : _T_2356 ? _Queue32_UInt8_58_io_deq_valid : _T_2355 ? _Queue32_UInt8_57_io_deq_valid : _T_2354 ? _Queue32_UInt8_56_io_deq_valid : _T_2353 ? _Queue32_UInt8_55_io_deq_valid : _T_2352 ? _Queue32_UInt8_54_io_deq_valid : _T_2351 ? _Queue32_UInt8_53_io_deq_valid : _T_2350 ? _Queue32_UInt8_52_io_deq_valid : _T_2349 ? _Queue32_UInt8_51_io_deq_valid : _T_2348 ? _Queue32_UInt8_50_io_deq_valid : _T_2347 ? _Queue32_UInt8_49_io_deq_valid : _T_2346 ? _Queue32_UInt8_48_io_deq_valid : _T_2345 ? _Queue32_UInt8_47_io_deq_valid : _T_2344 ? _Queue32_UInt8_46_io_deq_valid : _T_2343 ? _Queue32_UInt8_45_io_deq_valid : _T_2342 ? _Queue32_UInt8_44_io_deq_valid : _T_2341 ? _Queue32_UInt8_43_io_deq_valid : _T_2340 ? _Queue32_UInt8_42_io_deq_valid : _T_2339 ? _Queue32_UInt8_41_io_deq_valid : _T_2338 ? _Queue32_UInt8_40_io_deq_valid : _T_2337 ? _Queue32_UInt8_39_io_deq_valid : _T_2336 ? _Queue32_UInt8_38_io_deq_valid : _T_2335 ? _Queue32_UInt8_37_io_deq_valid : _T_2334 ? _Queue32_UInt8_36_io_deq_valid : _T_2333 ? _Queue32_UInt8_35_io_deq_valid : _T_2332 ? _Queue32_UInt8_34_io_deq_valid : _T_2331 ? _Queue32_UInt8_33_io_deq_valid : _T_2330 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_92 = _remapindex_T_1 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_1 = _GEN_92[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2362 = remapindex_1 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2363 = remapindex_1 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2364 = remapindex_1 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2365 = remapindex_1 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2366 = remapindex_1 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2367 = remapindex_1 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2368 = remapindex_1 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2369 = remapindex_1 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2370 = remapindex_1 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2371 = remapindex_1 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2372 = remapindex_1 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2373 = remapindex_1 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2374 = remapindex_1 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2375 = remapindex_1 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2376 = remapindex_1 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2377 = remapindex_1 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2378 = remapindex_1 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2379 = remapindex_1 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2380 = remapindex_1 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2381 = remapindex_1 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2382 = remapindex_1 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2383 = remapindex_1 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2384 = remapindex_1 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2385 = remapindex_1 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2386 = remapindex_1 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2387 = remapindex_1 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2388 = remapindex_1 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2389 = remapindex_1 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2390 = remapindex_1 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2391 = remapindex_1 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2392 = remapindex_1 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2393 = remapindex_1 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_1 = _T_2393 ? _Queue32_UInt8_63_io_deq_bits : _T_2392 ? _Queue32_UInt8_62_io_deq_bits : _T_2391 ? _Queue32_UInt8_61_io_deq_bits : _T_2390 ? _Queue32_UInt8_60_io_deq_bits : _T_2389 ? _Queue32_UInt8_59_io_deq_bits : _T_2388 ? _Queue32_UInt8_58_io_deq_bits : _T_2387 ? _Queue32_UInt8_57_io_deq_bits : _T_2386 ? _Queue32_UInt8_56_io_deq_bits : _T_2385 ? _Queue32_UInt8_55_io_deq_bits : _T_2384 ? _Queue32_UInt8_54_io_deq_bits : _T_2383 ? _Queue32_UInt8_53_io_deq_bits : _T_2382 ? _Queue32_UInt8_52_io_deq_bits : _T_2381 ? _Queue32_UInt8_51_io_deq_bits : _T_2380 ? _Queue32_UInt8_50_io_deq_bits : _T_2379 ? _Queue32_UInt8_49_io_deq_bits : _T_2378 ? _Queue32_UInt8_48_io_deq_bits : _T_2377 ? _Queue32_UInt8_47_io_deq_bits : _T_2376 ? _Queue32_UInt8_46_io_deq_bits : _T_2375 ? _Queue32_UInt8_45_io_deq_bits : _T_2374 ? _Queue32_UInt8_44_io_deq_bits : _T_2373 ? _Queue32_UInt8_43_io_deq_bits : _T_2372 ? _Queue32_UInt8_42_io_deq_bits : _T_2371 ? _Queue32_UInt8_41_io_deq_bits : _T_2370 ? _Queue32_UInt8_40_io_deq_bits : _T_2369 ? _Queue32_UInt8_39_io_deq_bits : _T_2368 ? _Queue32_UInt8_38_io_deq_bits : _T_2367 ? _Queue32_UInt8_37_io_deq_bits : _T_2366 ? _Queue32_UInt8_36_io_deq_bits : _T_2365 ? _Queue32_UInt8_35_io_deq_bits : _T_2364 ? _Queue32_UInt8_34_io_deq_bits : _T_2363 ? _Queue32_UInt8_33_io_deq_bits : _T_2362 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_1 = _T_2393 ? _Queue32_UInt8_63_io_deq_valid : _T_2392 ? _Queue32_UInt8_62_io_deq_valid : _T_2391 ? _Queue32_UInt8_61_io_deq_valid : _T_2390 ? _Queue32_UInt8_60_io_deq_valid : _T_2389 ? _Queue32_UInt8_59_io_deq_valid : _T_2388 ? _Queue32_UInt8_58_io_deq_valid : _T_2387 ? _Queue32_UInt8_57_io_deq_valid : _T_2386 ? _Queue32_UInt8_56_io_deq_valid : _T_2385 ? _Queue32_UInt8_55_io_deq_valid : _T_2384 ? _Queue32_UInt8_54_io_deq_valid : _T_2383 ? _Queue32_UInt8_53_io_deq_valid : _T_2382 ? _Queue32_UInt8_52_io_deq_valid : _T_2381 ? _Queue32_UInt8_51_io_deq_valid : _T_2380 ? _Queue32_UInt8_50_io_deq_valid : _T_2379 ? _Queue32_UInt8_49_io_deq_valid : _T_2378 ? _Queue32_UInt8_48_io_deq_valid : _T_2377 ? _Queue32_UInt8_47_io_deq_valid : _T_2376 ? _Queue32_UInt8_46_io_deq_valid : _T_2375 ? _Queue32_UInt8_45_io_deq_valid : _T_2374 ? _Queue32_UInt8_44_io_deq_valid : _T_2373 ? _Queue32_UInt8_43_io_deq_valid : _T_2372 ? _Queue32_UInt8_42_io_deq_valid : _T_2371 ? _Queue32_UInt8_41_io_deq_valid : _T_2370 ? _Queue32_UInt8_40_io_deq_valid : _T_2369 ? _Queue32_UInt8_39_io_deq_valid : _T_2368 ? _Queue32_UInt8_38_io_deq_valid : _T_2367 ? _Queue32_UInt8_37_io_deq_valid : _T_2366 ? _Queue32_UInt8_36_io_deq_valid : _T_2365 ? _Queue32_UInt8_35_io_deq_valid : _T_2364 ? _Queue32_UInt8_34_io_deq_valid : _T_2363 ? _Queue32_UInt8_33_io_deq_valid : _T_2362 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_93 = _remapindex_T_2 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_2 = _GEN_93[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2394 = remapindex_2 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2395 = remapindex_2 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2396 = remapindex_2 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2397 = remapindex_2 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2398 = remapindex_2 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2399 = remapindex_2 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2400 = remapindex_2 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2401 = remapindex_2 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2402 = remapindex_2 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2403 = remapindex_2 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2404 = remapindex_2 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2405 = remapindex_2 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2406 = remapindex_2 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2407 = remapindex_2 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2408 = remapindex_2 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2409 = remapindex_2 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2410 = remapindex_2 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2411 = remapindex_2 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2412 = remapindex_2 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2413 = remapindex_2 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2414 = remapindex_2 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2415 = remapindex_2 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2416 = remapindex_2 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2417 = remapindex_2 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2418 = remapindex_2 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2419 = remapindex_2 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2420 = remapindex_2 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2421 = remapindex_2 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2422 = remapindex_2 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2423 = remapindex_2 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2424 = remapindex_2 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2425 = remapindex_2 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_2 = _T_2425 ? _Queue32_UInt8_63_io_deq_bits : _T_2424 ? _Queue32_UInt8_62_io_deq_bits : _T_2423 ? _Queue32_UInt8_61_io_deq_bits : _T_2422 ? _Queue32_UInt8_60_io_deq_bits : _T_2421 ? _Queue32_UInt8_59_io_deq_bits : _T_2420 ? _Queue32_UInt8_58_io_deq_bits : _T_2419 ? _Queue32_UInt8_57_io_deq_bits : _T_2418 ? _Queue32_UInt8_56_io_deq_bits : _T_2417 ? _Queue32_UInt8_55_io_deq_bits : _T_2416 ? _Queue32_UInt8_54_io_deq_bits : _T_2415 ? _Queue32_UInt8_53_io_deq_bits : _T_2414 ? _Queue32_UInt8_52_io_deq_bits : _T_2413 ? _Queue32_UInt8_51_io_deq_bits : _T_2412 ? _Queue32_UInt8_50_io_deq_bits : _T_2411 ? _Queue32_UInt8_49_io_deq_bits : _T_2410 ? _Queue32_UInt8_48_io_deq_bits : _T_2409 ? _Queue32_UInt8_47_io_deq_bits : _T_2408 ? _Queue32_UInt8_46_io_deq_bits : _T_2407 ? _Queue32_UInt8_45_io_deq_bits : _T_2406 ? _Queue32_UInt8_44_io_deq_bits : _T_2405 ? _Queue32_UInt8_43_io_deq_bits : _T_2404 ? _Queue32_UInt8_42_io_deq_bits : _T_2403 ? _Queue32_UInt8_41_io_deq_bits : _T_2402 ? _Queue32_UInt8_40_io_deq_bits : _T_2401 ? _Queue32_UInt8_39_io_deq_bits : _T_2400 ? _Queue32_UInt8_38_io_deq_bits : _T_2399 ? _Queue32_UInt8_37_io_deq_bits : _T_2398 ? _Queue32_UInt8_36_io_deq_bits : _T_2397 ? _Queue32_UInt8_35_io_deq_bits : _T_2396 ? _Queue32_UInt8_34_io_deq_bits : _T_2395 ? _Queue32_UInt8_33_io_deq_bits : _T_2394 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_2 = _T_2425 ? _Queue32_UInt8_63_io_deq_valid : _T_2424 ? _Queue32_UInt8_62_io_deq_valid : _T_2423 ? _Queue32_UInt8_61_io_deq_valid : _T_2422 ? _Queue32_UInt8_60_io_deq_valid : _T_2421 ? _Queue32_UInt8_59_io_deq_valid : _T_2420 ? _Queue32_UInt8_58_io_deq_valid : _T_2419 ? _Queue32_UInt8_57_io_deq_valid : _T_2418 ? _Queue32_UInt8_56_io_deq_valid : _T_2417 ? _Queue32_UInt8_55_io_deq_valid : _T_2416 ? _Queue32_UInt8_54_io_deq_valid : _T_2415 ? _Queue32_UInt8_53_io_deq_valid : _T_2414 ? _Queue32_UInt8_52_io_deq_valid : _T_2413 ? _Queue32_UInt8_51_io_deq_valid : _T_2412 ? _Queue32_UInt8_50_io_deq_valid : _T_2411 ? _Queue32_UInt8_49_io_deq_valid : _T_2410 ? _Queue32_UInt8_48_io_deq_valid : _T_2409 ? _Queue32_UInt8_47_io_deq_valid : _T_2408 ? _Queue32_UInt8_46_io_deq_valid : _T_2407 ? _Queue32_UInt8_45_io_deq_valid : _T_2406 ? _Queue32_UInt8_44_io_deq_valid : _T_2405 ? _Queue32_UInt8_43_io_deq_valid : _T_2404 ? _Queue32_UInt8_42_io_deq_valid : _T_2403 ? _Queue32_UInt8_41_io_deq_valid : _T_2402 ? _Queue32_UInt8_40_io_deq_valid : _T_2401 ? _Queue32_UInt8_39_io_deq_valid : _T_2400 ? _Queue32_UInt8_38_io_deq_valid : _T_2399 ? _Queue32_UInt8_37_io_deq_valid : _T_2398 ? _Queue32_UInt8_36_io_deq_valid : _T_2397 ? _Queue32_UInt8_35_io_deq_valid : _T_2396 ? _Queue32_UInt8_34_io_deq_valid : _T_2395 ? _Queue32_UInt8_33_io_deq_valid : _T_2394 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_94 = _remapindex_T_3 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_3 = _GEN_94[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2426 = remapindex_3 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2427 = remapindex_3 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2428 = remapindex_3 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2429 = remapindex_3 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2430 = remapindex_3 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2431 = remapindex_3 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2432 = remapindex_3 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2433 = remapindex_3 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2434 = remapindex_3 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2435 = remapindex_3 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2436 = remapindex_3 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2437 = remapindex_3 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2438 = remapindex_3 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2439 = remapindex_3 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2440 = remapindex_3 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2441 = remapindex_3 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2442 = remapindex_3 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2443 = remapindex_3 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2444 = remapindex_3 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2445 = remapindex_3 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2446 = remapindex_3 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2447 = remapindex_3 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2448 = remapindex_3 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2449 = remapindex_3 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2450 = remapindex_3 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2451 = remapindex_3 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2452 = remapindex_3 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2453 = remapindex_3 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2454 = remapindex_3 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2455 = remapindex_3 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2456 = remapindex_3 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2457 = remapindex_3 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_3 = _T_2457 ? _Queue32_UInt8_63_io_deq_bits : _T_2456 ? _Queue32_UInt8_62_io_deq_bits : _T_2455 ? _Queue32_UInt8_61_io_deq_bits : _T_2454 ? _Queue32_UInt8_60_io_deq_bits : _T_2453 ? _Queue32_UInt8_59_io_deq_bits : _T_2452 ? _Queue32_UInt8_58_io_deq_bits : _T_2451 ? _Queue32_UInt8_57_io_deq_bits : _T_2450 ? _Queue32_UInt8_56_io_deq_bits : _T_2449 ? _Queue32_UInt8_55_io_deq_bits : _T_2448 ? _Queue32_UInt8_54_io_deq_bits : _T_2447 ? _Queue32_UInt8_53_io_deq_bits : _T_2446 ? _Queue32_UInt8_52_io_deq_bits : _T_2445 ? _Queue32_UInt8_51_io_deq_bits : _T_2444 ? _Queue32_UInt8_50_io_deq_bits : _T_2443 ? _Queue32_UInt8_49_io_deq_bits : _T_2442 ? _Queue32_UInt8_48_io_deq_bits : _T_2441 ? _Queue32_UInt8_47_io_deq_bits : _T_2440 ? _Queue32_UInt8_46_io_deq_bits : _T_2439 ? _Queue32_UInt8_45_io_deq_bits : _T_2438 ? _Queue32_UInt8_44_io_deq_bits : _T_2437 ? _Queue32_UInt8_43_io_deq_bits : _T_2436 ? _Queue32_UInt8_42_io_deq_bits : _T_2435 ? _Queue32_UInt8_41_io_deq_bits : _T_2434 ? _Queue32_UInt8_40_io_deq_bits : _T_2433 ? _Queue32_UInt8_39_io_deq_bits : _T_2432 ? _Queue32_UInt8_38_io_deq_bits : _T_2431 ? _Queue32_UInt8_37_io_deq_bits : _T_2430 ? _Queue32_UInt8_36_io_deq_bits : _T_2429 ? _Queue32_UInt8_35_io_deq_bits : _T_2428 ? _Queue32_UInt8_34_io_deq_bits : _T_2427 ? _Queue32_UInt8_33_io_deq_bits : _T_2426 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_3 = _T_2457 ? _Queue32_UInt8_63_io_deq_valid : _T_2456 ? _Queue32_UInt8_62_io_deq_valid : _T_2455 ? _Queue32_UInt8_61_io_deq_valid : _T_2454 ? _Queue32_UInt8_60_io_deq_valid : _T_2453 ? _Queue32_UInt8_59_io_deq_valid : _T_2452 ? _Queue32_UInt8_58_io_deq_valid : _T_2451 ? _Queue32_UInt8_57_io_deq_valid : _T_2450 ? _Queue32_UInt8_56_io_deq_valid : _T_2449 ? _Queue32_UInt8_55_io_deq_valid : _T_2448 ? _Queue32_UInt8_54_io_deq_valid : _T_2447 ? _Queue32_UInt8_53_io_deq_valid : _T_2446 ? _Queue32_UInt8_52_io_deq_valid : _T_2445 ? _Queue32_UInt8_51_io_deq_valid : _T_2444 ? _Queue32_UInt8_50_io_deq_valid : _T_2443 ? _Queue32_UInt8_49_io_deq_valid : _T_2442 ? _Queue32_UInt8_48_io_deq_valid : _T_2441 ? _Queue32_UInt8_47_io_deq_valid : _T_2440 ? _Queue32_UInt8_46_io_deq_valid : _T_2439 ? _Queue32_UInt8_45_io_deq_valid : _T_2438 ? _Queue32_UInt8_44_io_deq_valid : _T_2437 ? _Queue32_UInt8_43_io_deq_valid : _T_2436 ? _Queue32_UInt8_42_io_deq_valid : _T_2435 ? _Queue32_UInt8_41_io_deq_valid : _T_2434 ? _Queue32_UInt8_40_io_deq_valid : _T_2433 ? _Queue32_UInt8_39_io_deq_valid : _T_2432 ? _Queue32_UInt8_38_io_deq_valid : _T_2431 ? _Queue32_UInt8_37_io_deq_valid : _T_2430 ? _Queue32_UInt8_36_io_deq_valid : _T_2429 ? _Queue32_UInt8_35_io_deq_valid : _T_2428 ? _Queue32_UInt8_34_io_deq_valid : _T_2427 ? _Queue32_UInt8_33_io_deq_valid : _T_2426 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_95 = _remapindex_T_4 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_4 = _GEN_95[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2458 = remapindex_4 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2459 = remapindex_4 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2460 = remapindex_4 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2461 = remapindex_4 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2462 = remapindex_4 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2463 = remapindex_4 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2464 = remapindex_4 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2465 = remapindex_4 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2466 = remapindex_4 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2467 = remapindex_4 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2468 = remapindex_4 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2469 = remapindex_4 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2470 = remapindex_4 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2471 = remapindex_4 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2472 = remapindex_4 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2473 = remapindex_4 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2474 = remapindex_4 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2475 = remapindex_4 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2476 = remapindex_4 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2477 = remapindex_4 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2478 = remapindex_4 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2479 = remapindex_4 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2480 = remapindex_4 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2481 = remapindex_4 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2482 = remapindex_4 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2483 = remapindex_4 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2484 = remapindex_4 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2485 = remapindex_4 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2486 = remapindex_4 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2487 = remapindex_4 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2488 = remapindex_4 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2489 = remapindex_4 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_4 = _T_2489 ? _Queue32_UInt8_63_io_deq_bits : _T_2488 ? _Queue32_UInt8_62_io_deq_bits : _T_2487 ? _Queue32_UInt8_61_io_deq_bits : _T_2486 ? _Queue32_UInt8_60_io_deq_bits : _T_2485 ? _Queue32_UInt8_59_io_deq_bits : _T_2484 ? _Queue32_UInt8_58_io_deq_bits : _T_2483 ? _Queue32_UInt8_57_io_deq_bits : _T_2482 ? _Queue32_UInt8_56_io_deq_bits : _T_2481 ? _Queue32_UInt8_55_io_deq_bits : _T_2480 ? _Queue32_UInt8_54_io_deq_bits : _T_2479 ? _Queue32_UInt8_53_io_deq_bits : _T_2478 ? _Queue32_UInt8_52_io_deq_bits : _T_2477 ? _Queue32_UInt8_51_io_deq_bits : _T_2476 ? _Queue32_UInt8_50_io_deq_bits : _T_2475 ? _Queue32_UInt8_49_io_deq_bits : _T_2474 ? _Queue32_UInt8_48_io_deq_bits : _T_2473 ? _Queue32_UInt8_47_io_deq_bits : _T_2472 ? _Queue32_UInt8_46_io_deq_bits : _T_2471 ? _Queue32_UInt8_45_io_deq_bits : _T_2470 ? _Queue32_UInt8_44_io_deq_bits : _T_2469 ? _Queue32_UInt8_43_io_deq_bits : _T_2468 ? _Queue32_UInt8_42_io_deq_bits : _T_2467 ? _Queue32_UInt8_41_io_deq_bits : _T_2466 ? _Queue32_UInt8_40_io_deq_bits : _T_2465 ? _Queue32_UInt8_39_io_deq_bits : _T_2464 ? _Queue32_UInt8_38_io_deq_bits : _T_2463 ? _Queue32_UInt8_37_io_deq_bits : _T_2462 ? _Queue32_UInt8_36_io_deq_bits : _T_2461 ? _Queue32_UInt8_35_io_deq_bits : _T_2460 ? _Queue32_UInt8_34_io_deq_bits : _T_2459 ? _Queue32_UInt8_33_io_deq_bits : _T_2458 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_4 = _T_2489 ? _Queue32_UInt8_63_io_deq_valid : _T_2488 ? _Queue32_UInt8_62_io_deq_valid : _T_2487 ? _Queue32_UInt8_61_io_deq_valid : _T_2486 ? _Queue32_UInt8_60_io_deq_valid : _T_2485 ? _Queue32_UInt8_59_io_deq_valid : _T_2484 ? _Queue32_UInt8_58_io_deq_valid : _T_2483 ? _Queue32_UInt8_57_io_deq_valid : _T_2482 ? _Queue32_UInt8_56_io_deq_valid : _T_2481 ? _Queue32_UInt8_55_io_deq_valid : _T_2480 ? _Queue32_UInt8_54_io_deq_valid : _T_2479 ? _Queue32_UInt8_53_io_deq_valid : _T_2478 ? _Queue32_UInt8_52_io_deq_valid : _T_2477 ? _Queue32_UInt8_51_io_deq_valid : _T_2476 ? _Queue32_UInt8_50_io_deq_valid : _T_2475 ? _Queue32_UInt8_49_io_deq_valid : _T_2474 ? _Queue32_UInt8_48_io_deq_valid : _T_2473 ? _Queue32_UInt8_47_io_deq_valid : _T_2472 ? _Queue32_UInt8_46_io_deq_valid : _T_2471 ? _Queue32_UInt8_45_io_deq_valid : _T_2470 ? _Queue32_UInt8_44_io_deq_valid : _T_2469 ? _Queue32_UInt8_43_io_deq_valid : _T_2468 ? _Queue32_UInt8_42_io_deq_valid : _T_2467 ? _Queue32_UInt8_41_io_deq_valid : _T_2466 ? _Queue32_UInt8_40_io_deq_valid : _T_2465 ? _Queue32_UInt8_39_io_deq_valid : _T_2464 ? _Queue32_UInt8_38_io_deq_valid : _T_2463 ? _Queue32_UInt8_37_io_deq_valid : _T_2462 ? _Queue32_UInt8_36_io_deq_valid : _T_2461 ? _Queue32_UInt8_35_io_deq_valid : _T_2460 ? _Queue32_UInt8_34_io_deq_valid : _T_2459 ? _Queue32_UInt8_33_io_deq_valid : _T_2458 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_96 = _remapindex_T_5 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_5 = _GEN_96[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2490 = remapindex_5 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2491 = remapindex_5 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2492 = remapindex_5 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2493 = remapindex_5 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2494 = remapindex_5 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2495 = remapindex_5 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2496 = remapindex_5 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2497 = remapindex_5 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2498 = remapindex_5 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2499 = remapindex_5 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2500 = remapindex_5 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2501 = remapindex_5 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2502 = remapindex_5 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2503 = remapindex_5 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2504 = remapindex_5 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2505 = remapindex_5 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2506 = remapindex_5 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2507 = remapindex_5 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2508 = remapindex_5 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2509 = remapindex_5 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2510 = remapindex_5 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2511 = remapindex_5 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2512 = remapindex_5 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2513 = remapindex_5 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2514 = remapindex_5 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2515 = remapindex_5 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2516 = remapindex_5 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2517 = remapindex_5 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2518 = remapindex_5 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2519 = remapindex_5 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2520 = remapindex_5 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2521 = remapindex_5 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_5 = _T_2521 ? _Queue32_UInt8_63_io_deq_bits : _T_2520 ? _Queue32_UInt8_62_io_deq_bits : _T_2519 ? _Queue32_UInt8_61_io_deq_bits : _T_2518 ? _Queue32_UInt8_60_io_deq_bits : _T_2517 ? _Queue32_UInt8_59_io_deq_bits : _T_2516 ? _Queue32_UInt8_58_io_deq_bits : _T_2515 ? _Queue32_UInt8_57_io_deq_bits : _T_2514 ? _Queue32_UInt8_56_io_deq_bits : _T_2513 ? _Queue32_UInt8_55_io_deq_bits : _T_2512 ? _Queue32_UInt8_54_io_deq_bits : _T_2511 ? _Queue32_UInt8_53_io_deq_bits : _T_2510 ? _Queue32_UInt8_52_io_deq_bits : _T_2509 ? _Queue32_UInt8_51_io_deq_bits : _T_2508 ? _Queue32_UInt8_50_io_deq_bits : _T_2507 ? _Queue32_UInt8_49_io_deq_bits : _T_2506 ? _Queue32_UInt8_48_io_deq_bits : _T_2505 ? _Queue32_UInt8_47_io_deq_bits : _T_2504 ? _Queue32_UInt8_46_io_deq_bits : _T_2503 ? _Queue32_UInt8_45_io_deq_bits : _T_2502 ? _Queue32_UInt8_44_io_deq_bits : _T_2501 ? _Queue32_UInt8_43_io_deq_bits : _T_2500 ? _Queue32_UInt8_42_io_deq_bits : _T_2499 ? _Queue32_UInt8_41_io_deq_bits : _T_2498 ? _Queue32_UInt8_40_io_deq_bits : _T_2497 ? _Queue32_UInt8_39_io_deq_bits : _T_2496 ? _Queue32_UInt8_38_io_deq_bits : _T_2495 ? _Queue32_UInt8_37_io_deq_bits : _T_2494 ? _Queue32_UInt8_36_io_deq_bits : _T_2493 ? _Queue32_UInt8_35_io_deq_bits : _T_2492 ? _Queue32_UInt8_34_io_deq_bits : _T_2491 ? _Queue32_UInt8_33_io_deq_bits : _T_2490 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_5 = _T_2521 ? _Queue32_UInt8_63_io_deq_valid : _T_2520 ? _Queue32_UInt8_62_io_deq_valid : _T_2519 ? _Queue32_UInt8_61_io_deq_valid : _T_2518 ? _Queue32_UInt8_60_io_deq_valid : _T_2517 ? _Queue32_UInt8_59_io_deq_valid : _T_2516 ? _Queue32_UInt8_58_io_deq_valid : _T_2515 ? _Queue32_UInt8_57_io_deq_valid : _T_2514 ? _Queue32_UInt8_56_io_deq_valid : _T_2513 ? _Queue32_UInt8_55_io_deq_valid : _T_2512 ? _Queue32_UInt8_54_io_deq_valid : _T_2511 ? _Queue32_UInt8_53_io_deq_valid : _T_2510 ? _Queue32_UInt8_52_io_deq_valid : _T_2509 ? _Queue32_UInt8_51_io_deq_valid : _T_2508 ? _Queue32_UInt8_50_io_deq_valid : _T_2507 ? _Queue32_UInt8_49_io_deq_valid : _T_2506 ? _Queue32_UInt8_48_io_deq_valid : _T_2505 ? _Queue32_UInt8_47_io_deq_valid : _T_2504 ? _Queue32_UInt8_46_io_deq_valid : _T_2503 ? _Queue32_UInt8_45_io_deq_valid : _T_2502 ? _Queue32_UInt8_44_io_deq_valid : _T_2501 ? _Queue32_UInt8_43_io_deq_valid : _T_2500 ? _Queue32_UInt8_42_io_deq_valid : _T_2499 ? _Queue32_UInt8_41_io_deq_valid : _T_2498 ? _Queue32_UInt8_40_io_deq_valid : _T_2497 ? _Queue32_UInt8_39_io_deq_valid : _T_2496 ? _Queue32_UInt8_38_io_deq_valid : _T_2495 ? _Queue32_UInt8_37_io_deq_valid : _T_2494 ? _Queue32_UInt8_36_io_deq_valid : _T_2493 ? _Queue32_UInt8_35_io_deq_valid : _T_2492 ? _Queue32_UInt8_34_io_deq_valid : _T_2491 ? _Queue32_UInt8_33_io_deq_valid : _T_2490 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_97 = _remapindex_T_6 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_6 = _GEN_97[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2522 = remapindex_6 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2523 = remapindex_6 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2524 = remapindex_6 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2525 = remapindex_6 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2526 = remapindex_6 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2527 = remapindex_6 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2528 = remapindex_6 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2529 = remapindex_6 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2530 = remapindex_6 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2531 = remapindex_6 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2532 = remapindex_6 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2533 = remapindex_6 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2534 = remapindex_6 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2535 = remapindex_6 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2536 = remapindex_6 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2537 = remapindex_6 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2538 = remapindex_6 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2539 = remapindex_6 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2540 = remapindex_6 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2541 = remapindex_6 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2542 = remapindex_6 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2543 = remapindex_6 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2544 = remapindex_6 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2545 = remapindex_6 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2546 = remapindex_6 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2547 = remapindex_6 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2548 = remapindex_6 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2549 = remapindex_6 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2550 = remapindex_6 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2551 = remapindex_6 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2552 = remapindex_6 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2553 = remapindex_6 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_6 = _T_2553 ? _Queue32_UInt8_63_io_deq_bits : _T_2552 ? _Queue32_UInt8_62_io_deq_bits : _T_2551 ? _Queue32_UInt8_61_io_deq_bits : _T_2550 ? _Queue32_UInt8_60_io_deq_bits : _T_2549 ? _Queue32_UInt8_59_io_deq_bits : _T_2548 ? _Queue32_UInt8_58_io_deq_bits : _T_2547 ? _Queue32_UInt8_57_io_deq_bits : _T_2546 ? _Queue32_UInt8_56_io_deq_bits : _T_2545 ? _Queue32_UInt8_55_io_deq_bits : _T_2544 ? _Queue32_UInt8_54_io_deq_bits : _T_2543 ? _Queue32_UInt8_53_io_deq_bits : _T_2542 ? _Queue32_UInt8_52_io_deq_bits : _T_2541 ? _Queue32_UInt8_51_io_deq_bits : _T_2540 ? _Queue32_UInt8_50_io_deq_bits : _T_2539 ? _Queue32_UInt8_49_io_deq_bits : _T_2538 ? _Queue32_UInt8_48_io_deq_bits : _T_2537 ? _Queue32_UInt8_47_io_deq_bits : _T_2536 ? _Queue32_UInt8_46_io_deq_bits : _T_2535 ? _Queue32_UInt8_45_io_deq_bits : _T_2534 ? _Queue32_UInt8_44_io_deq_bits : _T_2533 ? _Queue32_UInt8_43_io_deq_bits : _T_2532 ? _Queue32_UInt8_42_io_deq_bits : _T_2531 ? _Queue32_UInt8_41_io_deq_bits : _T_2530 ? _Queue32_UInt8_40_io_deq_bits : _T_2529 ? _Queue32_UInt8_39_io_deq_bits : _T_2528 ? _Queue32_UInt8_38_io_deq_bits : _T_2527 ? _Queue32_UInt8_37_io_deq_bits : _T_2526 ? _Queue32_UInt8_36_io_deq_bits : _T_2525 ? _Queue32_UInt8_35_io_deq_bits : _T_2524 ? _Queue32_UInt8_34_io_deq_bits : _T_2523 ? _Queue32_UInt8_33_io_deq_bits : _T_2522 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_6 = _T_2553 ? _Queue32_UInt8_63_io_deq_valid : _T_2552 ? _Queue32_UInt8_62_io_deq_valid : _T_2551 ? _Queue32_UInt8_61_io_deq_valid : _T_2550 ? _Queue32_UInt8_60_io_deq_valid : _T_2549 ? _Queue32_UInt8_59_io_deq_valid : _T_2548 ? _Queue32_UInt8_58_io_deq_valid : _T_2547 ? _Queue32_UInt8_57_io_deq_valid : _T_2546 ? _Queue32_UInt8_56_io_deq_valid : _T_2545 ? _Queue32_UInt8_55_io_deq_valid : _T_2544 ? _Queue32_UInt8_54_io_deq_valid : _T_2543 ? _Queue32_UInt8_53_io_deq_valid : _T_2542 ? _Queue32_UInt8_52_io_deq_valid : _T_2541 ? _Queue32_UInt8_51_io_deq_valid : _T_2540 ? _Queue32_UInt8_50_io_deq_valid : _T_2539 ? _Queue32_UInt8_49_io_deq_valid : _T_2538 ? _Queue32_UInt8_48_io_deq_valid : _T_2537 ? _Queue32_UInt8_47_io_deq_valid : _T_2536 ? _Queue32_UInt8_46_io_deq_valid : _T_2535 ? _Queue32_UInt8_45_io_deq_valid : _T_2534 ? _Queue32_UInt8_44_io_deq_valid : _T_2533 ? _Queue32_UInt8_43_io_deq_valid : _T_2532 ? _Queue32_UInt8_42_io_deq_valid : _T_2531 ? _Queue32_UInt8_41_io_deq_valid : _T_2530 ? _Queue32_UInt8_40_io_deq_valid : _T_2529 ? _Queue32_UInt8_39_io_deq_valid : _T_2528 ? _Queue32_UInt8_38_io_deq_valid : _T_2527 ? _Queue32_UInt8_37_io_deq_valid : _T_2526 ? _Queue32_UInt8_36_io_deq_valid : _T_2525 ? _Queue32_UInt8_35_io_deq_valid : _T_2524 ? _Queue32_UInt8_34_io_deq_valid : _T_2523 ? _Queue32_UInt8_33_io_deq_valid : _T_2522 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_98 = _remapindex_T_7 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_7 = _GEN_98[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2554 = remapindex_7 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2555 = remapindex_7 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2556 = remapindex_7 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2557 = remapindex_7 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2558 = remapindex_7 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2559 = remapindex_7 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2560 = remapindex_7 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2561 = remapindex_7 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2562 = remapindex_7 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2563 = remapindex_7 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2564 = remapindex_7 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2565 = remapindex_7 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2566 = remapindex_7 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2567 = remapindex_7 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2568 = remapindex_7 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2569 = remapindex_7 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2570 = remapindex_7 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2571 = remapindex_7 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2572 = remapindex_7 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2573 = remapindex_7 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2574 = remapindex_7 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2575 = remapindex_7 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2576 = remapindex_7 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2577 = remapindex_7 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2578 = remapindex_7 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2579 = remapindex_7 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2580 = remapindex_7 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2581 = remapindex_7 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2582 = remapindex_7 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2583 = remapindex_7 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2584 = remapindex_7 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2585 = remapindex_7 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_7 = _T_2585 ? _Queue32_UInt8_63_io_deq_bits : _T_2584 ? _Queue32_UInt8_62_io_deq_bits : _T_2583 ? _Queue32_UInt8_61_io_deq_bits : _T_2582 ? _Queue32_UInt8_60_io_deq_bits : _T_2581 ? _Queue32_UInt8_59_io_deq_bits : _T_2580 ? _Queue32_UInt8_58_io_deq_bits : _T_2579 ? _Queue32_UInt8_57_io_deq_bits : _T_2578 ? _Queue32_UInt8_56_io_deq_bits : _T_2577 ? _Queue32_UInt8_55_io_deq_bits : _T_2576 ? _Queue32_UInt8_54_io_deq_bits : _T_2575 ? _Queue32_UInt8_53_io_deq_bits : _T_2574 ? _Queue32_UInt8_52_io_deq_bits : _T_2573 ? _Queue32_UInt8_51_io_deq_bits : _T_2572 ? _Queue32_UInt8_50_io_deq_bits : _T_2571 ? _Queue32_UInt8_49_io_deq_bits : _T_2570 ? _Queue32_UInt8_48_io_deq_bits : _T_2569 ? _Queue32_UInt8_47_io_deq_bits : _T_2568 ? _Queue32_UInt8_46_io_deq_bits : _T_2567 ? _Queue32_UInt8_45_io_deq_bits : _T_2566 ? _Queue32_UInt8_44_io_deq_bits : _T_2565 ? _Queue32_UInt8_43_io_deq_bits : _T_2564 ? _Queue32_UInt8_42_io_deq_bits : _T_2563 ? _Queue32_UInt8_41_io_deq_bits : _T_2562 ? _Queue32_UInt8_40_io_deq_bits : _T_2561 ? _Queue32_UInt8_39_io_deq_bits : _T_2560 ? _Queue32_UInt8_38_io_deq_bits : _T_2559 ? _Queue32_UInt8_37_io_deq_bits : _T_2558 ? _Queue32_UInt8_36_io_deq_bits : _T_2557 ? _Queue32_UInt8_35_io_deq_bits : _T_2556 ? _Queue32_UInt8_34_io_deq_bits : _T_2555 ? _Queue32_UInt8_33_io_deq_bits : _T_2554 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_7 = _T_2585 ? _Queue32_UInt8_63_io_deq_valid : _T_2584 ? _Queue32_UInt8_62_io_deq_valid : _T_2583 ? _Queue32_UInt8_61_io_deq_valid : _T_2582 ? _Queue32_UInt8_60_io_deq_valid : _T_2581 ? _Queue32_UInt8_59_io_deq_valid : _T_2580 ? _Queue32_UInt8_58_io_deq_valid : _T_2579 ? _Queue32_UInt8_57_io_deq_valid : _T_2578 ? _Queue32_UInt8_56_io_deq_valid : _T_2577 ? _Queue32_UInt8_55_io_deq_valid : _T_2576 ? _Queue32_UInt8_54_io_deq_valid : _T_2575 ? _Queue32_UInt8_53_io_deq_valid : _T_2574 ? _Queue32_UInt8_52_io_deq_valid : _T_2573 ? _Queue32_UInt8_51_io_deq_valid : _T_2572 ? _Queue32_UInt8_50_io_deq_valid : _T_2571 ? _Queue32_UInt8_49_io_deq_valid : _T_2570 ? _Queue32_UInt8_48_io_deq_valid : _T_2569 ? _Queue32_UInt8_47_io_deq_valid : _T_2568 ? _Queue32_UInt8_46_io_deq_valid : _T_2567 ? _Queue32_UInt8_45_io_deq_valid : _T_2566 ? _Queue32_UInt8_44_io_deq_valid : _T_2565 ? _Queue32_UInt8_43_io_deq_valid : _T_2564 ? _Queue32_UInt8_42_io_deq_valid : _T_2563 ? _Queue32_UInt8_41_io_deq_valid : _T_2562 ? _Queue32_UInt8_40_io_deq_valid : _T_2561 ? _Queue32_UInt8_39_io_deq_valid : _T_2560 ? _Queue32_UInt8_38_io_deq_valid : _T_2559 ? _Queue32_UInt8_37_io_deq_valid : _T_2558 ? _Queue32_UInt8_36_io_deq_valid : _T_2557 ? _Queue32_UInt8_35_io_deq_valid : _T_2556 ? _Queue32_UInt8_34_io_deq_valid : _T_2555 ? _Queue32_UInt8_33_io_deq_valid : _T_2554 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_99 = _remapindex_T_8 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_8 = _GEN_99[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2586 = remapindex_8 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2587 = remapindex_8 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2588 = remapindex_8 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2589 = remapindex_8 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2590 = remapindex_8 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2591 = remapindex_8 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2592 = remapindex_8 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2593 = remapindex_8 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2594 = remapindex_8 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2595 = remapindex_8 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2596 = remapindex_8 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2597 = remapindex_8 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2598 = remapindex_8 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2599 = remapindex_8 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2600 = remapindex_8 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2601 = remapindex_8 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2602 = remapindex_8 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2603 = remapindex_8 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2604 = remapindex_8 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2605 = remapindex_8 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2606 = remapindex_8 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2607 = remapindex_8 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2608 = remapindex_8 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2609 = remapindex_8 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2610 = remapindex_8 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2611 = remapindex_8 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2612 = remapindex_8 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2613 = remapindex_8 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2614 = remapindex_8 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2615 = remapindex_8 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2616 = remapindex_8 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2617 = remapindex_8 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_8 = _T_2617 ? _Queue32_UInt8_63_io_deq_bits : _T_2616 ? _Queue32_UInt8_62_io_deq_bits : _T_2615 ? _Queue32_UInt8_61_io_deq_bits : _T_2614 ? _Queue32_UInt8_60_io_deq_bits : _T_2613 ? _Queue32_UInt8_59_io_deq_bits : _T_2612 ? _Queue32_UInt8_58_io_deq_bits : _T_2611 ? _Queue32_UInt8_57_io_deq_bits : _T_2610 ? _Queue32_UInt8_56_io_deq_bits : _T_2609 ? _Queue32_UInt8_55_io_deq_bits : _T_2608 ? _Queue32_UInt8_54_io_deq_bits : _T_2607 ? _Queue32_UInt8_53_io_deq_bits : _T_2606 ? _Queue32_UInt8_52_io_deq_bits : _T_2605 ? _Queue32_UInt8_51_io_deq_bits : _T_2604 ? _Queue32_UInt8_50_io_deq_bits : _T_2603 ? _Queue32_UInt8_49_io_deq_bits : _T_2602 ? _Queue32_UInt8_48_io_deq_bits : _T_2601 ? _Queue32_UInt8_47_io_deq_bits : _T_2600 ? _Queue32_UInt8_46_io_deq_bits : _T_2599 ? _Queue32_UInt8_45_io_deq_bits : _T_2598 ? _Queue32_UInt8_44_io_deq_bits : _T_2597 ? _Queue32_UInt8_43_io_deq_bits : _T_2596 ? _Queue32_UInt8_42_io_deq_bits : _T_2595 ? _Queue32_UInt8_41_io_deq_bits : _T_2594 ? _Queue32_UInt8_40_io_deq_bits : _T_2593 ? _Queue32_UInt8_39_io_deq_bits : _T_2592 ? _Queue32_UInt8_38_io_deq_bits : _T_2591 ? _Queue32_UInt8_37_io_deq_bits : _T_2590 ? _Queue32_UInt8_36_io_deq_bits : _T_2589 ? _Queue32_UInt8_35_io_deq_bits : _T_2588 ? _Queue32_UInt8_34_io_deq_bits : _T_2587 ? _Queue32_UInt8_33_io_deq_bits : _T_2586 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_8 = _T_2617 ? _Queue32_UInt8_63_io_deq_valid : _T_2616 ? _Queue32_UInt8_62_io_deq_valid : _T_2615 ? _Queue32_UInt8_61_io_deq_valid : _T_2614 ? _Queue32_UInt8_60_io_deq_valid : _T_2613 ? _Queue32_UInt8_59_io_deq_valid : _T_2612 ? _Queue32_UInt8_58_io_deq_valid : _T_2611 ? _Queue32_UInt8_57_io_deq_valid : _T_2610 ? _Queue32_UInt8_56_io_deq_valid : _T_2609 ? _Queue32_UInt8_55_io_deq_valid : _T_2608 ? _Queue32_UInt8_54_io_deq_valid : _T_2607 ? _Queue32_UInt8_53_io_deq_valid : _T_2606 ? _Queue32_UInt8_52_io_deq_valid : _T_2605 ? _Queue32_UInt8_51_io_deq_valid : _T_2604 ? _Queue32_UInt8_50_io_deq_valid : _T_2603 ? _Queue32_UInt8_49_io_deq_valid : _T_2602 ? _Queue32_UInt8_48_io_deq_valid : _T_2601 ? _Queue32_UInt8_47_io_deq_valid : _T_2600 ? _Queue32_UInt8_46_io_deq_valid : _T_2599 ? _Queue32_UInt8_45_io_deq_valid : _T_2598 ? _Queue32_UInt8_44_io_deq_valid : _T_2597 ? _Queue32_UInt8_43_io_deq_valid : _T_2596 ? _Queue32_UInt8_42_io_deq_valid : _T_2595 ? _Queue32_UInt8_41_io_deq_valid : _T_2594 ? _Queue32_UInt8_40_io_deq_valid : _T_2593 ? _Queue32_UInt8_39_io_deq_valid : _T_2592 ? _Queue32_UInt8_38_io_deq_valid : _T_2591 ? _Queue32_UInt8_37_io_deq_valid : _T_2590 ? _Queue32_UInt8_36_io_deq_valid : _T_2589 ? _Queue32_UInt8_35_io_deq_valid : _T_2588 ? _Queue32_UInt8_34_io_deq_valid : _T_2587 ? _Queue32_UInt8_33_io_deq_valid : _T_2586 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_100 = _remapindex_T_9 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_9 = _GEN_100[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2618 = remapindex_9 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2619 = remapindex_9 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2620 = remapindex_9 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2621 = remapindex_9 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2622 = remapindex_9 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2623 = remapindex_9 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2624 = remapindex_9 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2625 = remapindex_9 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2626 = remapindex_9 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2627 = remapindex_9 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2628 = remapindex_9 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2629 = remapindex_9 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2630 = remapindex_9 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2631 = remapindex_9 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2632 = remapindex_9 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2633 = remapindex_9 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2634 = remapindex_9 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2635 = remapindex_9 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2636 = remapindex_9 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2637 = remapindex_9 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2638 = remapindex_9 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2639 = remapindex_9 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2640 = remapindex_9 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2641 = remapindex_9 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2642 = remapindex_9 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2643 = remapindex_9 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2644 = remapindex_9 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2645 = remapindex_9 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2646 = remapindex_9 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2647 = remapindex_9 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2648 = remapindex_9 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2649 = remapindex_9 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_9 = _T_2649 ? _Queue32_UInt8_63_io_deq_bits : _T_2648 ? _Queue32_UInt8_62_io_deq_bits : _T_2647 ? _Queue32_UInt8_61_io_deq_bits : _T_2646 ? _Queue32_UInt8_60_io_deq_bits : _T_2645 ? _Queue32_UInt8_59_io_deq_bits : _T_2644 ? _Queue32_UInt8_58_io_deq_bits : _T_2643 ? _Queue32_UInt8_57_io_deq_bits : _T_2642 ? _Queue32_UInt8_56_io_deq_bits : _T_2641 ? _Queue32_UInt8_55_io_deq_bits : _T_2640 ? _Queue32_UInt8_54_io_deq_bits : _T_2639 ? _Queue32_UInt8_53_io_deq_bits : _T_2638 ? _Queue32_UInt8_52_io_deq_bits : _T_2637 ? _Queue32_UInt8_51_io_deq_bits : _T_2636 ? _Queue32_UInt8_50_io_deq_bits : _T_2635 ? _Queue32_UInt8_49_io_deq_bits : _T_2634 ? _Queue32_UInt8_48_io_deq_bits : _T_2633 ? _Queue32_UInt8_47_io_deq_bits : _T_2632 ? _Queue32_UInt8_46_io_deq_bits : _T_2631 ? _Queue32_UInt8_45_io_deq_bits : _T_2630 ? _Queue32_UInt8_44_io_deq_bits : _T_2629 ? _Queue32_UInt8_43_io_deq_bits : _T_2628 ? _Queue32_UInt8_42_io_deq_bits : _T_2627 ? _Queue32_UInt8_41_io_deq_bits : _T_2626 ? _Queue32_UInt8_40_io_deq_bits : _T_2625 ? _Queue32_UInt8_39_io_deq_bits : _T_2624 ? _Queue32_UInt8_38_io_deq_bits : _T_2623 ? _Queue32_UInt8_37_io_deq_bits : _T_2622 ? _Queue32_UInt8_36_io_deq_bits : _T_2621 ? _Queue32_UInt8_35_io_deq_bits : _T_2620 ? _Queue32_UInt8_34_io_deq_bits : _T_2619 ? _Queue32_UInt8_33_io_deq_bits : _T_2618 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_9 = _T_2649 ? _Queue32_UInt8_63_io_deq_valid : _T_2648 ? _Queue32_UInt8_62_io_deq_valid : _T_2647 ? _Queue32_UInt8_61_io_deq_valid : _T_2646 ? _Queue32_UInt8_60_io_deq_valid : _T_2645 ? _Queue32_UInt8_59_io_deq_valid : _T_2644 ? _Queue32_UInt8_58_io_deq_valid : _T_2643 ? _Queue32_UInt8_57_io_deq_valid : _T_2642 ? _Queue32_UInt8_56_io_deq_valid : _T_2641 ? _Queue32_UInt8_55_io_deq_valid : _T_2640 ? _Queue32_UInt8_54_io_deq_valid : _T_2639 ? _Queue32_UInt8_53_io_deq_valid : _T_2638 ? _Queue32_UInt8_52_io_deq_valid : _T_2637 ? _Queue32_UInt8_51_io_deq_valid : _T_2636 ? _Queue32_UInt8_50_io_deq_valid : _T_2635 ? _Queue32_UInt8_49_io_deq_valid : _T_2634 ? _Queue32_UInt8_48_io_deq_valid : _T_2633 ? _Queue32_UInt8_47_io_deq_valid : _T_2632 ? _Queue32_UInt8_46_io_deq_valid : _T_2631 ? _Queue32_UInt8_45_io_deq_valid : _T_2630 ? _Queue32_UInt8_44_io_deq_valid : _T_2629 ? _Queue32_UInt8_43_io_deq_valid : _T_2628 ? _Queue32_UInt8_42_io_deq_valid : _T_2627 ? _Queue32_UInt8_41_io_deq_valid : _T_2626 ? _Queue32_UInt8_40_io_deq_valid : _T_2625 ? _Queue32_UInt8_39_io_deq_valid : _T_2624 ? _Queue32_UInt8_38_io_deq_valid : _T_2623 ? _Queue32_UInt8_37_io_deq_valid : _T_2622 ? _Queue32_UInt8_36_io_deq_valid : _T_2621 ? _Queue32_UInt8_35_io_deq_valid : _T_2620 ? _Queue32_UInt8_34_io_deq_valid : _T_2619 ? _Queue32_UInt8_33_io_deq_valid : _T_2618 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_101 = _remapindex_T_10 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_10 = _GEN_101[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2650 = remapindex_10 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2651 = remapindex_10 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2652 = remapindex_10 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2653 = remapindex_10 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2654 = remapindex_10 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2655 = remapindex_10 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2656 = remapindex_10 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2657 = remapindex_10 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2658 = remapindex_10 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2659 = remapindex_10 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2660 = remapindex_10 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2661 = remapindex_10 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2662 = remapindex_10 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2663 = remapindex_10 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2664 = remapindex_10 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2665 = remapindex_10 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2666 = remapindex_10 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2667 = remapindex_10 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2668 = remapindex_10 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2669 = remapindex_10 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2670 = remapindex_10 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2671 = remapindex_10 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2672 = remapindex_10 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2673 = remapindex_10 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2674 = remapindex_10 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2675 = remapindex_10 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2676 = remapindex_10 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2677 = remapindex_10 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2678 = remapindex_10 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2679 = remapindex_10 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2680 = remapindex_10 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2681 = remapindex_10 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_10 = _T_2681 ? _Queue32_UInt8_63_io_deq_bits : _T_2680 ? _Queue32_UInt8_62_io_deq_bits : _T_2679 ? _Queue32_UInt8_61_io_deq_bits : _T_2678 ? _Queue32_UInt8_60_io_deq_bits : _T_2677 ? _Queue32_UInt8_59_io_deq_bits : _T_2676 ? _Queue32_UInt8_58_io_deq_bits : _T_2675 ? _Queue32_UInt8_57_io_deq_bits : _T_2674 ? _Queue32_UInt8_56_io_deq_bits : _T_2673 ? _Queue32_UInt8_55_io_deq_bits : _T_2672 ? _Queue32_UInt8_54_io_deq_bits : _T_2671 ? _Queue32_UInt8_53_io_deq_bits : _T_2670 ? _Queue32_UInt8_52_io_deq_bits : _T_2669 ? _Queue32_UInt8_51_io_deq_bits : _T_2668 ? _Queue32_UInt8_50_io_deq_bits : _T_2667 ? _Queue32_UInt8_49_io_deq_bits : _T_2666 ? _Queue32_UInt8_48_io_deq_bits : _T_2665 ? _Queue32_UInt8_47_io_deq_bits : _T_2664 ? _Queue32_UInt8_46_io_deq_bits : _T_2663 ? _Queue32_UInt8_45_io_deq_bits : _T_2662 ? _Queue32_UInt8_44_io_deq_bits : _T_2661 ? _Queue32_UInt8_43_io_deq_bits : _T_2660 ? _Queue32_UInt8_42_io_deq_bits : _T_2659 ? _Queue32_UInt8_41_io_deq_bits : _T_2658 ? _Queue32_UInt8_40_io_deq_bits : _T_2657 ? _Queue32_UInt8_39_io_deq_bits : _T_2656 ? _Queue32_UInt8_38_io_deq_bits : _T_2655 ? _Queue32_UInt8_37_io_deq_bits : _T_2654 ? _Queue32_UInt8_36_io_deq_bits : _T_2653 ? _Queue32_UInt8_35_io_deq_bits : _T_2652 ? _Queue32_UInt8_34_io_deq_bits : _T_2651 ? _Queue32_UInt8_33_io_deq_bits : _T_2650 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_10 = _T_2681 ? _Queue32_UInt8_63_io_deq_valid : _T_2680 ? _Queue32_UInt8_62_io_deq_valid : _T_2679 ? _Queue32_UInt8_61_io_deq_valid : _T_2678 ? _Queue32_UInt8_60_io_deq_valid : _T_2677 ? _Queue32_UInt8_59_io_deq_valid : _T_2676 ? _Queue32_UInt8_58_io_deq_valid : _T_2675 ? _Queue32_UInt8_57_io_deq_valid : _T_2674 ? _Queue32_UInt8_56_io_deq_valid : _T_2673 ? _Queue32_UInt8_55_io_deq_valid : _T_2672 ? _Queue32_UInt8_54_io_deq_valid : _T_2671 ? _Queue32_UInt8_53_io_deq_valid : _T_2670 ? _Queue32_UInt8_52_io_deq_valid : _T_2669 ? _Queue32_UInt8_51_io_deq_valid : _T_2668 ? _Queue32_UInt8_50_io_deq_valid : _T_2667 ? _Queue32_UInt8_49_io_deq_valid : _T_2666 ? _Queue32_UInt8_48_io_deq_valid : _T_2665 ? _Queue32_UInt8_47_io_deq_valid : _T_2664 ? _Queue32_UInt8_46_io_deq_valid : _T_2663 ? _Queue32_UInt8_45_io_deq_valid : _T_2662 ? _Queue32_UInt8_44_io_deq_valid : _T_2661 ? _Queue32_UInt8_43_io_deq_valid : _T_2660 ? _Queue32_UInt8_42_io_deq_valid : _T_2659 ? _Queue32_UInt8_41_io_deq_valid : _T_2658 ? _Queue32_UInt8_40_io_deq_valid : _T_2657 ? _Queue32_UInt8_39_io_deq_valid : _T_2656 ? _Queue32_UInt8_38_io_deq_valid : _T_2655 ? _Queue32_UInt8_37_io_deq_valid : _T_2654 ? _Queue32_UInt8_36_io_deq_valid : _T_2653 ? _Queue32_UInt8_35_io_deq_valid : _T_2652 ? _Queue32_UInt8_34_io_deq_valid : _T_2651 ? _Queue32_UInt8_33_io_deq_valid : _T_2650 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_102 = _remapindex_T_11 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_11 = _GEN_102[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2682 = remapindex_11 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2683 = remapindex_11 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2684 = remapindex_11 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2685 = remapindex_11 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2686 = remapindex_11 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2687 = remapindex_11 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2688 = remapindex_11 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2689 = remapindex_11 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2690 = remapindex_11 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2691 = remapindex_11 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2692 = remapindex_11 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2693 = remapindex_11 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2694 = remapindex_11 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2695 = remapindex_11 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2696 = remapindex_11 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2697 = remapindex_11 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2698 = remapindex_11 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2699 = remapindex_11 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2700 = remapindex_11 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2701 = remapindex_11 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2702 = remapindex_11 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2703 = remapindex_11 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2704 = remapindex_11 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2705 = remapindex_11 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2706 = remapindex_11 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2707 = remapindex_11 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2708 = remapindex_11 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2709 = remapindex_11 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2710 = remapindex_11 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2711 = remapindex_11 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2712 = remapindex_11 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2713 = remapindex_11 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_11 = _T_2713 ? _Queue32_UInt8_63_io_deq_bits : _T_2712 ? _Queue32_UInt8_62_io_deq_bits : _T_2711 ? _Queue32_UInt8_61_io_deq_bits : _T_2710 ? _Queue32_UInt8_60_io_deq_bits : _T_2709 ? _Queue32_UInt8_59_io_deq_bits : _T_2708 ? _Queue32_UInt8_58_io_deq_bits : _T_2707 ? _Queue32_UInt8_57_io_deq_bits : _T_2706 ? _Queue32_UInt8_56_io_deq_bits : _T_2705 ? _Queue32_UInt8_55_io_deq_bits : _T_2704 ? _Queue32_UInt8_54_io_deq_bits : _T_2703 ? _Queue32_UInt8_53_io_deq_bits : _T_2702 ? _Queue32_UInt8_52_io_deq_bits : _T_2701 ? _Queue32_UInt8_51_io_deq_bits : _T_2700 ? _Queue32_UInt8_50_io_deq_bits : _T_2699 ? _Queue32_UInt8_49_io_deq_bits : _T_2698 ? _Queue32_UInt8_48_io_deq_bits : _T_2697 ? _Queue32_UInt8_47_io_deq_bits : _T_2696 ? _Queue32_UInt8_46_io_deq_bits : _T_2695 ? _Queue32_UInt8_45_io_deq_bits : _T_2694 ? _Queue32_UInt8_44_io_deq_bits : _T_2693 ? _Queue32_UInt8_43_io_deq_bits : _T_2692 ? _Queue32_UInt8_42_io_deq_bits : _T_2691 ? _Queue32_UInt8_41_io_deq_bits : _T_2690 ? _Queue32_UInt8_40_io_deq_bits : _T_2689 ? _Queue32_UInt8_39_io_deq_bits : _T_2688 ? _Queue32_UInt8_38_io_deq_bits : _T_2687 ? _Queue32_UInt8_37_io_deq_bits : _T_2686 ? _Queue32_UInt8_36_io_deq_bits : _T_2685 ? _Queue32_UInt8_35_io_deq_bits : _T_2684 ? _Queue32_UInt8_34_io_deq_bits : _T_2683 ? _Queue32_UInt8_33_io_deq_bits : _T_2682 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_11 = _T_2713 ? _Queue32_UInt8_63_io_deq_valid : _T_2712 ? _Queue32_UInt8_62_io_deq_valid : _T_2711 ? _Queue32_UInt8_61_io_deq_valid : _T_2710 ? _Queue32_UInt8_60_io_deq_valid : _T_2709 ? _Queue32_UInt8_59_io_deq_valid : _T_2708 ? _Queue32_UInt8_58_io_deq_valid : _T_2707 ? _Queue32_UInt8_57_io_deq_valid : _T_2706 ? _Queue32_UInt8_56_io_deq_valid : _T_2705 ? _Queue32_UInt8_55_io_deq_valid : _T_2704 ? _Queue32_UInt8_54_io_deq_valid : _T_2703 ? _Queue32_UInt8_53_io_deq_valid : _T_2702 ? _Queue32_UInt8_52_io_deq_valid : _T_2701 ? _Queue32_UInt8_51_io_deq_valid : _T_2700 ? _Queue32_UInt8_50_io_deq_valid : _T_2699 ? _Queue32_UInt8_49_io_deq_valid : _T_2698 ? _Queue32_UInt8_48_io_deq_valid : _T_2697 ? _Queue32_UInt8_47_io_deq_valid : _T_2696 ? _Queue32_UInt8_46_io_deq_valid : _T_2695 ? _Queue32_UInt8_45_io_deq_valid : _T_2694 ? _Queue32_UInt8_44_io_deq_valid : _T_2693 ? _Queue32_UInt8_43_io_deq_valid : _T_2692 ? _Queue32_UInt8_42_io_deq_valid : _T_2691 ? _Queue32_UInt8_41_io_deq_valid : _T_2690 ? _Queue32_UInt8_40_io_deq_valid : _T_2689 ? _Queue32_UInt8_39_io_deq_valid : _T_2688 ? _Queue32_UInt8_38_io_deq_valid : _T_2687 ? _Queue32_UInt8_37_io_deq_valid : _T_2686 ? _Queue32_UInt8_36_io_deq_valid : _T_2685 ? _Queue32_UInt8_35_io_deq_valid : _T_2684 ? _Queue32_UInt8_34_io_deq_valid : _T_2683 ? _Queue32_UInt8_33_io_deq_valid : _T_2682 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_103 = _remapindex_T_12 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_12 = _GEN_103[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2714 = remapindex_12 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2715 = remapindex_12 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2716 = remapindex_12 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2717 = remapindex_12 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2718 = remapindex_12 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2719 = remapindex_12 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2720 = remapindex_12 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2721 = remapindex_12 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2722 = remapindex_12 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2723 = remapindex_12 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2724 = remapindex_12 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2725 = remapindex_12 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2726 = remapindex_12 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2727 = remapindex_12 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2728 = remapindex_12 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2729 = remapindex_12 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2730 = remapindex_12 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2731 = remapindex_12 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2732 = remapindex_12 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2733 = remapindex_12 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2734 = remapindex_12 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2735 = remapindex_12 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2736 = remapindex_12 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2737 = remapindex_12 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2738 = remapindex_12 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2739 = remapindex_12 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2740 = remapindex_12 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2741 = remapindex_12 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2742 = remapindex_12 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2743 = remapindex_12 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2744 = remapindex_12 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2745 = remapindex_12 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_12 = _T_2745 ? _Queue32_UInt8_63_io_deq_bits : _T_2744 ? _Queue32_UInt8_62_io_deq_bits : _T_2743 ? _Queue32_UInt8_61_io_deq_bits : _T_2742 ? _Queue32_UInt8_60_io_deq_bits : _T_2741 ? _Queue32_UInt8_59_io_deq_bits : _T_2740 ? _Queue32_UInt8_58_io_deq_bits : _T_2739 ? _Queue32_UInt8_57_io_deq_bits : _T_2738 ? _Queue32_UInt8_56_io_deq_bits : _T_2737 ? _Queue32_UInt8_55_io_deq_bits : _T_2736 ? _Queue32_UInt8_54_io_deq_bits : _T_2735 ? _Queue32_UInt8_53_io_deq_bits : _T_2734 ? _Queue32_UInt8_52_io_deq_bits : _T_2733 ? _Queue32_UInt8_51_io_deq_bits : _T_2732 ? _Queue32_UInt8_50_io_deq_bits : _T_2731 ? _Queue32_UInt8_49_io_deq_bits : _T_2730 ? _Queue32_UInt8_48_io_deq_bits : _T_2729 ? _Queue32_UInt8_47_io_deq_bits : _T_2728 ? _Queue32_UInt8_46_io_deq_bits : _T_2727 ? _Queue32_UInt8_45_io_deq_bits : _T_2726 ? _Queue32_UInt8_44_io_deq_bits : _T_2725 ? _Queue32_UInt8_43_io_deq_bits : _T_2724 ? _Queue32_UInt8_42_io_deq_bits : _T_2723 ? _Queue32_UInt8_41_io_deq_bits : _T_2722 ? _Queue32_UInt8_40_io_deq_bits : _T_2721 ? _Queue32_UInt8_39_io_deq_bits : _T_2720 ? _Queue32_UInt8_38_io_deq_bits : _T_2719 ? _Queue32_UInt8_37_io_deq_bits : _T_2718 ? _Queue32_UInt8_36_io_deq_bits : _T_2717 ? _Queue32_UInt8_35_io_deq_bits : _T_2716 ? _Queue32_UInt8_34_io_deq_bits : _T_2715 ? _Queue32_UInt8_33_io_deq_bits : _T_2714 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_12 = _T_2745 ? _Queue32_UInt8_63_io_deq_valid : _T_2744 ? _Queue32_UInt8_62_io_deq_valid : _T_2743 ? _Queue32_UInt8_61_io_deq_valid : _T_2742 ? _Queue32_UInt8_60_io_deq_valid : _T_2741 ? _Queue32_UInt8_59_io_deq_valid : _T_2740 ? _Queue32_UInt8_58_io_deq_valid : _T_2739 ? _Queue32_UInt8_57_io_deq_valid : _T_2738 ? _Queue32_UInt8_56_io_deq_valid : _T_2737 ? _Queue32_UInt8_55_io_deq_valid : _T_2736 ? _Queue32_UInt8_54_io_deq_valid : _T_2735 ? _Queue32_UInt8_53_io_deq_valid : _T_2734 ? _Queue32_UInt8_52_io_deq_valid : _T_2733 ? _Queue32_UInt8_51_io_deq_valid : _T_2732 ? _Queue32_UInt8_50_io_deq_valid : _T_2731 ? _Queue32_UInt8_49_io_deq_valid : _T_2730 ? _Queue32_UInt8_48_io_deq_valid : _T_2729 ? _Queue32_UInt8_47_io_deq_valid : _T_2728 ? _Queue32_UInt8_46_io_deq_valid : _T_2727 ? _Queue32_UInt8_45_io_deq_valid : _T_2726 ? _Queue32_UInt8_44_io_deq_valid : _T_2725 ? _Queue32_UInt8_43_io_deq_valid : _T_2724 ? _Queue32_UInt8_42_io_deq_valid : _T_2723 ? _Queue32_UInt8_41_io_deq_valid : _T_2722 ? _Queue32_UInt8_40_io_deq_valid : _T_2721 ? _Queue32_UInt8_39_io_deq_valid : _T_2720 ? _Queue32_UInt8_38_io_deq_valid : _T_2719 ? _Queue32_UInt8_37_io_deq_valid : _T_2718 ? _Queue32_UInt8_36_io_deq_valid : _T_2717 ? _Queue32_UInt8_35_io_deq_valid : _T_2716 ? _Queue32_UInt8_34_io_deq_valid : _T_2715 ? _Queue32_UInt8_33_io_deq_valid : _T_2714 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_104 = _remapindex_T_13 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_13 = _GEN_104[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2746 = remapindex_13 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2747 = remapindex_13 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2748 = remapindex_13 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2749 = remapindex_13 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2750 = remapindex_13 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2751 = remapindex_13 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2752 = remapindex_13 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2753 = remapindex_13 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2754 = remapindex_13 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2755 = remapindex_13 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2756 = remapindex_13 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2757 = remapindex_13 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2758 = remapindex_13 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2759 = remapindex_13 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2760 = remapindex_13 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2761 = remapindex_13 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2762 = remapindex_13 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2763 = remapindex_13 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2764 = remapindex_13 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2765 = remapindex_13 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2766 = remapindex_13 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2767 = remapindex_13 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2768 = remapindex_13 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2769 = remapindex_13 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2770 = remapindex_13 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2771 = remapindex_13 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2772 = remapindex_13 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2773 = remapindex_13 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2774 = remapindex_13 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2775 = remapindex_13 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2776 = remapindex_13 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2777 = remapindex_13 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_13 = _T_2777 ? _Queue32_UInt8_63_io_deq_bits : _T_2776 ? _Queue32_UInt8_62_io_deq_bits : _T_2775 ? _Queue32_UInt8_61_io_deq_bits : _T_2774 ? _Queue32_UInt8_60_io_deq_bits : _T_2773 ? _Queue32_UInt8_59_io_deq_bits : _T_2772 ? _Queue32_UInt8_58_io_deq_bits : _T_2771 ? _Queue32_UInt8_57_io_deq_bits : _T_2770 ? _Queue32_UInt8_56_io_deq_bits : _T_2769 ? _Queue32_UInt8_55_io_deq_bits : _T_2768 ? _Queue32_UInt8_54_io_deq_bits : _T_2767 ? _Queue32_UInt8_53_io_deq_bits : _T_2766 ? _Queue32_UInt8_52_io_deq_bits : _T_2765 ? _Queue32_UInt8_51_io_deq_bits : _T_2764 ? _Queue32_UInt8_50_io_deq_bits : _T_2763 ? _Queue32_UInt8_49_io_deq_bits : _T_2762 ? _Queue32_UInt8_48_io_deq_bits : _T_2761 ? _Queue32_UInt8_47_io_deq_bits : _T_2760 ? _Queue32_UInt8_46_io_deq_bits : _T_2759 ? _Queue32_UInt8_45_io_deq_bits : _T_2758 ? _Queue32_UInt8_44_io_deq_bits : _T_2757 ? _Queue32_UInt8_43_io_deq_bits : _T_2756 ? _Queue32_UInt8_42_io_deq_bits : _T_2755 ? _Queue32_UInt8_41_io_deq_bits : _T_2754 ? _Queue32_UInt8_40_io_deq_bits : _T_2753 ? _Queue32_UInt8_39_io_deq_bits : _T_2752 ? _Queue32_UInt8_38_io_deq_bits : _T_2751 ? _Queue32_UInt8_37_io_deq_bits : _T_2750 ? _Queue32_UInt8_36_io_deq_bits : _T_2749 ? _Queue32_UInt8_35_io_deq_bits : _T_2748 ? _Queue32_UInt8_34_io_deq_bits : _T_2747 ? _Queue32_UInt8_33_io_deq_bits : _T_2746 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_13 = _T_2777 ? _Queue32_UInt8_63_io_deq_valid : _T_2776 ? _Queue32_UInt8_62_io_deq_valid : _T_2775 ? _Queue32_UInt8_61_io_deq_valid : _T_2774 ? _Queue32_UInt8_60_io_deq_valid : _T_2773 ? _Queue32_UInt8_59_io_deq_valid : _T_2772 ? _Queue32_UInt8_58_io_deq_valid : _T_2771 ? _Queue32_UInt8_57_io_deq_valid : _T_2770 ? _Queue32_UInt8_56_io_deq_valid : _T_2769 ? _Queue32_UInt8_55_io_deq_valid : _T_2768 ? _Queue32_UInt8_54_io_deq_valid : _T_2767 ? _Queue32_UInt8_53_io_deq_valid : _T_2766 ? _Queue32_UInt8_52_io_deq_valid : _T_2765 ? _Queue32_UInt8_51_io_deq_valid : _T_2764 ? _Queue32_UInt8_50_io_deq_valid : _T_2763 ? _Queue32_UInt8_49_io_deq_valid : _T_2762 ? _Queue32_UInt8_48_io_deq_valid : _T_2761 ? _Queue32_UInt8_47_io_deq_valid : _T_2760 ? _Queue32_UInt8_46_io_deq_valid : _T_2759 ? _Queue32_UInt8_45_io_deq_valid : _T_2758 ? _Queue32_UInt8_44_io_deq_valid : _T_2757 ? _Queue32_UInt8_43_io_deq_valid : _T_2756 ? _Queue32_UInt8_42_io_deq_valid : _T_2755 ? _Queue32_UInt8_41_io_deq_valid : _T_2754 ? _Queue32_UInt8_40_io_deq_valid : _T_2753 ? _Queue32_UInt8_39_io_deq_valid : _T_2752 ? _Queue32_UInt8_38_io_deq_valid : _T_2751 ? _Queue32_UInt8_37_io_deq_valid : _T_2750 ? _Queue32_UInt8_36_io_deq_valid : _T_2749 ? _Queue32_UInt8_35_io_deq_valid : _T_2748 ? _Queue32_UInt8_34_io_deq_valid : _T_2747 ? _Queue32_UInt8_33_io_deq_valid : _T_2746 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_105 = _remapindex_T_14 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_14 = _GEN_105[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2778 = remapindex_14 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2779 = remapindex_14 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2780 = remapindex_14 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2781 = remapindex_14 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2782 = remapindex_14 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2783 = remapindex_14 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2784 = remapindex_14 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2785 = remapindex_14 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2786 = remapindex_14 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2787 = remapindex_14 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2788 = remapindex_14 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2789 = remapindex_14 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2790 = remapindex_14 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2791 = remapindex_14 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2792 = remapindex_14 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2793 = remapindex_14 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2794 = remapindex_14 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2795 = remapindex_14 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2796 = remapindex_14 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2797 = remapindex_14 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2798 = remapindex_14 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2799 = remapindex_14 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2800 = remapindex_14 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2801 = remapindex_14 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2802 = remapindex_14 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2803 = remapindex_14 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2804 = remapindex_14 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2805 = remapindex_14 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2806 = remapindex_14 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2807 = remapindex_14 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2808 = remapindex_14 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2809 = remapindex_14 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_14 = _T_2809 ? _Queue32_UInt8_63_io_deq_bits : _T_2808 ? _Queue32_UInt8_62_io_deq_bits : _T_2807 ? _Queue32_UInt8_61_io_deq_bits : _T_2806 ? _Queue32_UInt8_60_io_deq_bits : _T_2805 ? _Queue32_UInt8_59_io_deq_bits : _T_2804 ? _Queue32_UInt8_58_io_deq_bits : _T_2803 ? _Queue32_UInt8_57_io_deq_bits : _T_2802 ? _Queue32_UInt8_56_io_deq_bits : _T_2801 ? _Queue32_UInt8_55_io_deq_bits : _T_2800 ? _Queue32_UInt8_54_io_deq_bits : _T_2799 ? _Queue32_UInt8_53_io_deq_bits : _T_2798 ? _Queue32_UInt8_52_io_deq_bits : _T_2797 ? _Queue32_UInt8_51_io_deq_bits : _T_2796 ? _Queue32_UInt8_50_io_deq_bits : _T_2795 ? _Queue32_UInt8_49_io_deq_bits : _T_2794 ? _Queue32_UInt8_48_io_deq_bits : _T_2793 ? _Queue32_UInt8_47_io_deq_bits : _T_2792 ? _Queue32_UInt8_46_io_deq_bits : _T_2791 ? _Queue32_UInt8_45_io_deq_bits : _T_2790 ? _Queue32_UInt8_44_io_deq_bits : _T_2789 ? _Queue32_UInt8_43_io_deq_bits : _T_2788 ? _Queue32_UInt8_42_io_deq_bits : _T_2787 ? _Queue32_UInt8_41_io_deq_bits : _T_2786 ? _Queue32_UInt8_40_io_deq_bits : _T_2785 ? _Queue32_UInt8_39_io_deq_bits : _T_2784 ? _Queue32_UInt8_38_io_deq_bits : _T_2783 ? _Queue32_UInt8_37_io_deq_bits : _T_2782 ? _Queue32_UInt8_36_io_deq_bits : _T_2781 ? _Queue32_UInt8_35_io_deq_bits : _T_2780 ? _Queue32_UInt8_34_io_deq_bits : _T_2779 ? _Queue32_UInt8_33_io_deq_bits : _T_2778 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_14 = _T_2809 ? _Queue32_UInt8_63_io_deq_valid : _T_2808 ? _Queue32_UInt8_62_io_deq_valid : _T_2807 ? _Queue32_UInt8_61_io_deq_valid : _T_2806 ? _Queue32_UInt8_60_io_deq_valid : _T_2805 ? _Queue32_UInt8_59_io_deq_valid : _T_2804 ? _Queue32_UInt8_58_io_deq_valid : _T_2803 ? _Queue32_UInt8_57_io_deq_valid : _T_2802 ? _Queue32_UInt8_56_io_deq_valid : _T_2801 ? _Queue32_UInt8_55_io_deq_valid : _T_2800 ? _Queue32_UInt8_54_io_deq_valid : _T_2799 ? _Queue32_UInt8_53_io_deq_valid : _T_2798 ? _Queue32_UInt8_52_io_deq_valid : _T_2797 ? _Queue32_UInt8_51_io_deq_valid : _T_2796 ? _Queue32_UInt8_50_io_deq_valid : _T_2795 ? _Queue32_UInt8_49_io_deq_valid : _T_2794 ? _Queue32_UInt8_48_io_deq_valid : _T_2793 ? _Queue32_UInt8_47_io_deq_valid : _T_2792 ? _Queue32_UInt8_46_io_deq_valid : _T_2791 ? _Queue32_UInt8_45_io_deq_valid : _T_2790 ? _Queue32_UInt8_44_io_deq_valid : _T_2789 ? _Queue32_UInt8_43_io_deq_valid : _T_2788 ? _Queue32_UInt8_42_io_deq_valid : _T_2787 ? _Queue32_UInt8_41_io_deq_valid : _T_2786 ? _Queue32_UInt8_40_io_deq_valid : _T_2785 ? _Queue32_UInt8_39_io_deq_valid : _T_2784 ? _Queue32_UInt8_38_io_deq_valid : _T_2783 ? _Queue32_UInt8_37_io_deq_valid : _T_2782 ? _Queue32_UInt8_36_io_deq_valid : _T_2781 ? _Queue32_UInt8_35_io_deq_valid : _T_2780 ? _Queue32_UInt8_34_io_deq_valid : _T_2779 ? _Queue32_UInt8_33_io_deq_valid : _T_2778 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_106 = _remapindex_T_15 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_15 = _GEN_106[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2810 = remapindex_15 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2811 = remapindex_15 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2812 = remapindex_15 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2813 = remapindex_15 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2814 = remapindex_15 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2815 = remapindex_15 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2816 = remapindex_15 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2817 = remapindex_15 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2818 = remapindex_15 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2819 = remapindex_15 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2820 = remapindex_15 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2821 = remapindex_15 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2822 = remapindex_15 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2823 = remapindex_15 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2824 = remapindex_15 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2825 = remapindex_15 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2826 = remapindex_15 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2827 = remapindex_15 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2828 = remapindex_15 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2829 = remapindex_15 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2830 = remapindex_15 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2831 = remapindex_15 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2832 = remapindex_15 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2833 = remapindex_15 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2834 = remapindex_15 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2835 = remapindex_15 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2836 = remapindex_15 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2837 = remapindex_15 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2838 = remapindex_15 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2839 = remapindex_15 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2840 = remapindex_15 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2841 = remapindex_15 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_15 = _T_2841 ? _Queue32_UInt8_63_io_deq_bits : _T_2840 ? _Queue32_UInt8_62_io_deq_bits : _T_2839 ? _Queue32_UInt8_61_io_deq_bits : _T_2838 ? _Queue32_UInt8_60_io_deq_bits : _T_2837 ? _Queue32_UInt8_59_io_deq_bits : _T_2836 ? _Queue32_UInt8_58_io_deq_bits : _T_2835 ? _Queue32_UInt8_57_io_deq_bits : _T_2834 ? _Queue32_UInt8_56_io_deq_bits : _T_2833 ? _Queue32_UInt8_55_io_deq_bits : _T_2832 ? _Queue32_UInt8_54_io_deq_bits : _T_2831 ? _Queue32_UInt8_53_io_deq_bits : _T_2830 ? _Queue32_UInt8_52_io_deq_bits : _T_2829 ? _Queue32_UInt8_51_io_deq_bits : _T_2828 ? _Queue32_UInt8_50_io_deq_bits : _T_2827 ? _Queue32_UInt8_49_io_deq_bits : _T_2826 ? _Queue32_UInt8_48_io_deq_bits : _T_2825 ? _Queue32_UInt8_47_io_deq_bits : _T_2824 ? _Queue32_UInt8_46_io_deq_bits : _T_2823 ? _Queue32_UInt8_45_io_deq_bits : _T_2822 ? _Queue32_UInt8_44_io_deq_bits : _T_2821 ? _Queue32_UInt8_43_io_deq_bits : _T_2820 ? _Queue32_UInt8_42_io_deq_bits : _T_2819 ? _Queue32_UInt8_41_io_deq_bits : _T_2818 ? _Queue32_UInt8_40_io_deq_bits : _T_2817 ? _Queue32_UInt8_39_io_deq_bits : _T_2816 ? _Queue32_UInt8_38_io_deq_bits : _T_2815 ? _Queue32_UInt8_37_io_deq_bits : _T_2814 ? _Queue32_UInt8_36_io_deq_bits : _T_2813 ? _Queue32_UInt8_35_io_deq_bits : _T_2812 ? _Queue32_UInt8_34_io_deq_bits : _T_2811 ? _Queue32_UInt8_33_io_deq_bits : _T_2810 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_15 = _T_2841 ? _Queue32_UInt8_63_io_deq_valid : _T_2840 ? _Queue32_UInt8_62_io_deq_valid : _T_2839 ? _Queue32_UInt8_61_io_deq_valid : _T_2838 ? _Queue32_UInt8_60_io_deq_valid : _T_2837 ? _Queue32_UInt8_59_io_deq_valid : _T_2836 ? _Queue32_UInt8_58_io_deq_valid : _T_2835 ? _Queue32_UInt8_57_io_deq_valid : _T_2834 ? _Queue32_UInt8_56_io_deq_valid : _T_2833 ? _Queue32_UInt8_55_io_deq_valid : _T_2832 ? _Queue32_UInt8_54_io_deq_valid : _T_2831 ? _Queue32_UInt8_53_io_deq_valid : _T_2830 ? _Queue32_UInt8_52_io_deq_valid : _T_2829 ? _Queue32_UInt8_51_io_deq_valid : _T_2828 ? _Queue32_UInt8_50_io_deq_valid : _T_2827 ? _Queue32_UInt8_49_io_deq_valid : _T_2826 ? _Queue32_UInt8_48_io_deq_valid : _T_2825 ? _Queue32_UInt8_47_io_deq_valid : _T_2824 ? _Queue32_UInt8_46_io_deq_valid : _T_2823 ? _Queue32_UInt8_45_io_deq_valid : _T_2822 ? _Queue32_UInt8_44_io_deq_valid : _T_2821 ? _Queue32_UInt8_43_io_deq_valid : _T_2820 ? _Queue32_UInt8_42_io_deq_valid : _T_2819 ? _Queue32_UInt8_41_io_deq_valid : _T_2818 ? _Queue32_UInt8_40_io_deq_valid : _T_2817 ? _Queue32_UInt8_39_io_deq_valid : _T_2816 ? _Queue32_UInt8_38_io_deq_valid : _T_2815 ? _Queue32_UInt8_37_io_deq_valid : _T_2814 ? _Queue32_UInt8_36_io_deq_valid : _T_2813 ? _Queue32_UInt8_35_io_deq_valid : _T_2812 ? _Queue32_UInt8_34_io_deq_valid : _T_2811 ? _Queue32_UInt8_33_io_deq_valid : _T_2810 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_107 = _remapindex_T_16 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_16 = _GEN_107[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2842 = remapindex_16 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2843 = remapindex_16 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2844 = remapindex_16 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2845 = remapindex_16 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2846 = remapindex_16 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2847 = remapindex_16 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2848 = remapindex_16 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2849 = remapindex_16 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2850 = remapindex_16 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2851 = remapindex_16 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2852 = remapindex_16 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2853 = remapindex_16 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2854 = remapindex_16 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2855 = remapindex_16 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2856 = remapindex_16 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2857 = remapindex_16 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2858 = remapindex_16 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2859 = remapindex_16 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2860 = remapindex_16 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2861 = remapindex_16 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2862 = remapindex_16 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2863 = remapindex_16 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2864 = remapindex_16 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2865 = remapindex_16 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2866 = remapindex_16 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2867 = remapindex_16 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2868 = remapindex_16 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2869 = remapindex_16 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2870 = remapindex_16 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2871 = remapindex_16 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2872 = remapindex_16 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2873 = remapindex_16 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_16 = _T_2873 ? _Queue32_UInt8_63_io_deq_bits : _T_2872 ? _Queue32_UInt8_62_io_deq_bits : _T_2871 ? _Queue32_UInt8_61_io_deq_bits : _T_2870 ? _Queue32_UInt8_60_io_deq_bits : _T_2869 ? _Queue32_UInt8_59_io_deq_bits : _T_2868 ? _Queue32_UInt8_58_io_deq_bits : _T_2867 ? _Queue32_UInt8_57_io_deq_bits : _T_2866 ? _Queue32_UInt8_56_io_deq_bits : _T_2865 ? _Queue32_UInt8_55_io_deq_bits : _T_2864 ? _Queue32_UInt8_54_io_deq_bits : _T_2863 ? _Queue32_UInt8_53_io_deq_bits : _T_2862 ? _Queue32_UInt8_52_io_deq_bits : _T_2861 ? _Queue32_UInt8_51_io_deq_bits : _T_2860 ? _Queue32_UInt8_50_io_deq_bits : _T_2859 ? _Queue32_UInt8_49_io_deq_bits : _T_2858 ? _Queue32_UInt8_48_io_deq_bits : _T_2857 ? _Queue32_UInt8_47_io_deq_bits : _T_2856 ? _Queue32_UInt8_46_io_deq_bits : _T_2855 ? _Queue32_UInt8_45_io_deq_bits : _T_2854 ? _Queue32_UInt8_44_io_deq_bits : _T_2853 ? _Queue32_UInt8_43_io_deq_bits : _T_2852 ? _Queue32_UInt8_42_io_deq_bits : _T_2851 ? _Queue32_UInt8_41_io_deq_bits : _T_2850 ? _Queue32_UInt8_40_io_deq_bits : _T_2849 ? _Queue32_UInt8_39_io_deq_bits : _T_2848 ? _Queue32_UInt8_38_io_deq_bits : _T_2847 ? _Queue32_UInt8_37_io_deq_bits : _T_2846 ? _Queue32_UInt8_36_io_deq_bits : _T_2845 ? _Queue32_UInt8_35_io_deq_bits : _T_2844 ? _Queue32_UInt8_34_io_deq_bits : _T_2843 ? _Queue32_UInt8_33_io_deq_bits : _T_2842 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_16 = _T_2873 ? _Queue32_UInt8_63_io_deq_valid : _T_2872 ? _Queue32_UInt8_62_io_deq_valid : _T_2871 ? _Queue32_UInt8_61_io_deq_valid : _T_2870 ? _Queue32_UInt8_60_io_deq_valid : _T_2869 ? _Queue32_UInt8_59_io_deq_valid : _T_2868 ? _Queue32_UInt8_58_io_deq_valid : _T_2867 ? _Queue32_UInt8_57_io_deq_valid : _T_2866 ? _Queue32_UInt8_56_io_deq_valid : _T_2865 ? _Queue32_UInt8_55_io_deq_valid : _T_2864 ? _Queue32_UInt8_54_io_deq_valid : _T_2863 ? _Queue32_UInt8_53_io_deq_valid : _T_2862 ? _Queue32_UInt8_52_io_deq_valid : _T_2861 ? _Queue32_UInt8_51_io_deq_valid : _T_2860 ? _Queue32_UInt8_50_io_deq_valid : _T_2859 ? _Queue32_UInt8_49_io_deq_valid : _T_2858 ? _Queue32_UInt8_48_io_deq_valid : _T_2857 ? _Queue32_UInt8_47_io_deq_valid : _T_2856 ? _Queue32_UInt8_46_io_deq_valid : _T_2855 ? _Queue32_UInt8_45_io_deq_valid : _T_2854 ? _Queue32_UInt8_44_io_deq_valid : _T_2853 ? _Queue32_UInt8_43_io_deq_valid : _T_2852 ? _Queue32_UInt8_42_io_deq_valid : _T_2851 ? _Queue32_UInt8_41_io_deq_valid : _T_2850 ? _Queue32_UInt8_40_io_deq_valid : _T_2849 ? _Queue32_UInt8_39_io_deq_valid : _T_2848 ? _Queue32_UInt8_38_io_deq_valid : _T_2847 ? _Queue32_UInt8_37_io_deq_valid : _T_2846 ? _Queue32_UInt8_36_io_deq_valid : _T_2845 ? _Queue32_UInt8_35_io_deq_valid : _T_2844 ? _Queue32_UInt8_34_io_deq_valid : _T_2843 ? _Queue32_UInt8_33_io_deq_valid : _T_2842 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_108 = _remapindex_T_17 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_17 = _GEN_108[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2874 = remapindex_17 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2875 = remapindex_17 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2876 = remapindex_17 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2877 = remapindex_17 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2878 = remapindex_17 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2879 = remapindex_17 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2880 = remapindex_17 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2881 = remapindex_17 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2882 = remapindex_17 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2883 = remapindex_17 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2884 = remapindex_17 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2885 = remapindex_17 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2886 = remapindex_17 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2887 = remapindex_17 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2888 = remapindex_17 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2889 = remapindex_17 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2890 = remapindex_17 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2891 = remapindex_17 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2892 = remapindex_17 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2893 = remapindex_17 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2894 = remapindex_17 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2895 = remapindex_17 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2896 = remapindex_17 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2897 = remapindex_17 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2898 = remapindex_17 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2899 = remapindex_17 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2900 = remapindex_17 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2901 = remapindex_17 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2902 = remapindex_17 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2903 = remapindex_17 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2904 = remapindex_17 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2905 = remapindex_17 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_17 = _T_2905 ? _Queue32_UInt8_63_io_deq_bits : _T_2904 ? _Queue32_UInt8_62_io_deq_bits : _T_2903 ? _Queue32_UInt8_61_io_deq_bits : _T_2902 ? _Queue32_UInt8_60_io_deq_bits : _T_2901 ? _Queue32_UInt8_59_io_deq_bits : _T_2900 ? _Queue32_UInt8_58_io_deq_bits : _T_2899 ? _Queue32_UInt8_57_io_deq_bits : _T_2898 ? _Queue32_UInt8_56_io_deq_bits : _T_2897 ? _Queue32_UInt8_55_io_deq_bits : _T_2896 ? _Queue32_UInt8_54_io_deq_bits : _T_2895 ? _Queue32_UInt8_53_io_deq_bits : _T_2894 ? _Queue32_UInt8_52_io_deq_bits : _T_2893 ? _Queue32_UInt8_51_io_deq_bits : _T_2892 ? _Queue32_UInt8_50_io_deq_bits : _T_2891 ? _Queue32_UInt8_49_io_deq_bits : _T_2890 ? _Queue32_UInt8_48_io_deq_bits : _T_2889 ? _Queue32_UInt8_47_io_deq_bits : _T_2888 ? _Queue32_UInt8_46_io_deq_bits : _T_2887 ? _Queue32_UInt8_45_io_deq_bits : _T_2886 ? _Queue32_UInt8_44_io_deq_bits : _T_2885 ? _Queue32_UInt8_43_io_deq_bits : _T_2884 ? _Queue32_UInt8_42_io_deq_bits : _T_2883 ? _Queue32_UInt8_41_io_deq_bits : _T_2882 ? _Queue32_UInt8_40_io_deq_bits : _T_2881 ? _Queue32_UInt8_39_io_deq_bits : _T_2880 ? _Queue32_UInt8_38_io_deq_bits : _T_2879 ? _Queue32_UInt8_37_io_deq_bits : _T_2878 ? _Queue32_UInt8_36_io_deq_bits : _T_2877 ? _Queue32_UInt8_35_io_deq_bits : _T_2876 ? _Queue32_UInt8_34_io_deq_bits : _T_2875 ? _Queue32_UInt8_33_io_deq_bits : _T_2874 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_17 = _T_2905 ? _Queue32_UInt8_63_io_deq_valid : _T_2904 ? _Queue32_UInt8_62_io_deq_valid : _T_2903 ? _Queue32_UInt8_61_io_deq_valid : _T_2902 ? _Queue32_UInt8_60_io_deq_valid : _T_2901 ? _Queue32_UInt8_59_io_deq_valid : _T_2900 ? _Queue32_UInt8_58_io_deq_valid : _T_2899 ? _Queue32_UInt8_57_io_deq_valid : _T_2898 ? _Queue32_UInt8_56_io_deq_valid : _T_2897 ? _Queue32_UInt8_55_io_deq_valid : _T_2896 ? _Queue32_UInt8_54_io_deq_valid : _T_2895 ? _Queue32_UInt8_53_io_deq_valid : _T_2894 ? _Queue32_UInt8_52_io_deq_valid : _T_2893 ? _Queue32_UInt8_51_io_deq_valid : _T_2892 ? _Queue32_UInt8_50_io_deq_valid : _T_2891 ? _Queue32_UInt8_49_io_deq_valid : _T_2890 ? _Queue32_UInt8_48_io_deq_valid : _T_2889 ? _Queue32_UInt8_47_io_deq_valid : _T_2888 ? _Queue32_UInt8_46_io_deq_valid : _T_2887 ? _Queue32_UInt8_45_io_deq_valid : _T_2886 ? _Queue32_UInt8_44_io_deq_valid : _T_2885 ? _Queue32_UInt8_43_io_deq_valid : _T_2884 ? _Queue32_UInt8_42_io_deq_valid : _T_2883 ? _Queue32_UInt8_41_io_deq_valid : _T_2882 ? _Queue32_UInt8_40_io_deq_valid : _T_2881 ? _Queue32_UInt8_39_io_deq_valid : _T_2880 ? _Queue32_UInt8_38_io_deq_valid : _T_2879 ? _Queue32_UInt8_37_io_deq_valid : _T_2878 ? _Queue32_UInt8_36_io_deq_valid : _T_2877 ? _Queue32_UInt8_35_io_deq_valid : _T_2876 ? _Queue32_UInt8_34_io_deq_valid : _T_2875 ? _Queue32_UInt8_33_io_deq_valid : _T_2874 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_109 = _remapindex_T_18 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_18 = _GEN_109[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2906 = remapindex_18 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2907 = remapindex_18 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2908 = remapindex_18 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2909 = remapindex_18 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2910 = remapindex_18 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2911 = remapindex_18 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2912 = remapindex_18 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2913 = remapindex_18 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2914 = remapindex_18 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2915 = remapindex_18 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2916 = remapindex_18 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2917 = remapindex_18 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2918 = remapindex_18 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2919 = remapindex_18 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2920 = remapindex_18 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2921 = remapindex_18 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2922 = remapindex_18 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2923 = remapindex_18 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2924 = remapindex_18 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2925 = remapindex_18 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2926 = remapindex_18 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2927 = remapindex_18 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2928 = remapindex_18 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2929 = remapindex_18 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2930 = remapindex_18 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2931 = remapindex_18 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2932 = remapindex_18 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2933 = remapindex_18 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2934 = remapindex_18 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2935 = remapindex_18 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2936 = remapindex_18 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2937 = remapindex_18 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_18 = _T_2937 ? _Queue32_UInt8_63_io_deq_bits : _T_2936 ? _Queue32_UInt8_62_io_deq_bits : _T_2935 ? _Queue32_UInt8_61_io_deq_bits : _T_2934 ? _Queue32_UInt8_60_io_deq_bits : _T_2933 ? _Queue32_UInt8_59_io_deq_bits : _T_2932 ? _Queue32_UInt8_58_io_deq_bits : _T_2931 ? _Queue32_UInt8_57_io_deq_bits : _T_2930 ? _Queue32_UInt8_56_io_deq_bits : _T_2929 ? _Queue32_UInt8_55_io_deq_bits : _T_2928 ? _Queue32_UInt8_54_io_deq_bits : _T_2927 ? _Queue32_UInt8_53_io_deq_bits : _T_2926 ? _Queue32_UInt8_52_io_deq_bits : _T_2925 ? _Queue32_UInt8_51_io_deq_bits : _T_2924 ? _Queue32_UInt8_50_io_deq_bits : _T_2923 ? _Queue32_UInt8_49_io_deq_bits : _T_2922 ? _Queue32_UInt8_48_io_deq_bits : _T_2921 ? _Queue32_UInt8_47_io_deq_bits : _T_2920 ? _Queue32_UInt8_46_io_deq_bits : _T_2919 ? _Queue32_UInt8_45_io_deq_bits : _T_2918 ? _Queue32_UInt8_44_io_deq_bits : _T_2917 ? _Queue32_UInt8_43_io_deq_bits : _T_2916 ? _Queue32_UInt8_42_io_deq_bits : _T_2915 ? _Queue32_UInt8_41_io_deq_bits : _T_2914 ? _Queue32_UInt8_40_io_deq_bits : _T_2913 ? _Queue32_UInt8_39_io_deq_bits : _T_2912 ? _Queue32_UInt8_38_io_deq_bits : _T_2911 ? _Queue32_UInt8_37_io_deq_bits : _T_2910 ? _Queue32_UInt8_36_io_deq_bits : _T_2909 ? _Queue32_UInt8_35_io_deq_bits : _T_2908 ? _Queue32_UInt8_34_io_deq_bits : _T_2907 ? _Queue32_UInt8_33_io_deq_bits : _T_2906 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_18 = _T_2937 ? _Queue32_UInt8_63_io_deq_valid : _T_2936 ? _Queue32_UInt8_62_io_deq_valid : _T_2935 ? _Queue32_UInt8_61_io_deq_valid : _T_2934 ? _Queue32_UInt8_60_io_deq_valid : _T_2933 ? _Queue32_UInt8_59_io_deq_valid : _T_2932 ? _Queue32_UInt8_58_io_deq_valid : _T_2931 ? _Queue32_UInt8_57_io_deq_valid : _T_2930 ? _Queue32_UInt8_56_io_deq_valid : _T_2929 ? _Queue32_UInt8_55_io_deq_valid : _T_2928 ? _Queue32_UInt8_54_io_deq_valid : _T_2927 ? _Queue32_UInt8_53_io_deq_valid : _T_2926 ? _Queue32_UInt8_52_io_deq_valid : _T_2925 ? _Queue32_UInt8_51_io_deq_valid : _T_2924 ? _Queue32_UInt8_50_io_deq_valid : _T_2923 ? _Queue32_UInt8_49_io_deq_valid : _T_2922 ? _Queue32_UInt8_48_io_deq_valid : _T_2921 ? _Queue32_UInt8_47_io_deq_valid : _T_2920 ? _Queue32_UInt8_46_io_deq_valid : _T_2919 ? _Queue32_UInt8_45_io_deq_valid : _T_2918 ? _Queue32_UInt8_44_io_deq_valid : _T_2917 ? _Queue32_UInt8_43_io_deq_valid : _T_2916 ? _Queue32_UInt8_42_io_deq_valid : _T_2915 ? _Queue32_UInt8_41_io_deq_valid : _T_2914 ? _Queue32_UInt8_40_io_deq_valid : _T_2913 ? _Queue32_UInt8_39_io_deq_valid : _T_2912 ? _Queue32_UInt8_38_io_deq_valid : _T_2911 ? _Queue32_UInt8_37_io_deq_valid : _T_2910 ? _Queue32_UInt8_36_io_deq_valid : _T_2909 ? _Queue32_UInt8_35_io_deq_valid : _T_2908 ? _Queue32_UInt8_34_io_deq_valid : _T_2907 ? _Queue32_UInt8_33_io_deq_valid : _T_2906 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_110 = _remapindex_T_19 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_19 = _GEN_110[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2938 = remapindex_19 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2939 = remapindex_19 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2940 = remapindex_19 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2941 = remapindex_19 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2942 = remapindex_19 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2943 = remapindex_19 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2944 = remapindex_19 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2945 = remapindex_19 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2946 = remapindex_19 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2947 = remapindex_19 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2948 = remapindex_19 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2949 = remapindex_19 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2950 = remapindex_19 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2951 = remapindex_19 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2952 = remapindex_19 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2953 = remapindex_19 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2954 = remapindex_19 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2955 = remapindex_19 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2956 = remapindex_19 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2957 = remapindex_19 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2958 = remapindex_19 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2959 = remapindex_19 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2960 = remapindex_19 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2961 = remapindex_19 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2962 = remapindex_19 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2963 = remapindex_19 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2964 = remapindex_19 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2965 = remapindex_19 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2966 = remapindex_19 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2967 = remapindex_19 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2968 = remapindex_19 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2969 = remapindex_19 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_19 = _T_2969 ? _Queue32_UInt8_63_io_deq_bits : _T_2968 ? _Queue32_UInt8_62_io_deq_bits : _T_2967 ? _Queue32_UInt8_61_io_deq_bits : _T_2966 ? _Queue32_UInt8_60_io_deq_bits : _T_2965 ? _Queue32_UInt8_59_io_deq_bits : _T_2964 ? _Queue32_UInt8_58_io_deq_bits : _T_2963 ? _Queue32_UInt8_57_io_deq_bits : _T_2962 ? _Queue32_UInt8_56_io_deq_bits : _T_2961 ? _Queue32_UInt8_55_io_deq_bits : _T_2960 ? _Queue32_UInt8_54_io_deq_bits : _T_2959 ? _Queue32_UInt8_53_io_deq_bits : _T_2958 ? _Queue32_UInt8_52_io_deq_bits : _T_2957 ? _Queue32_UInt8_51_io_deq_bits : _T_2956 ? _Queue32_UInt8_50_io_deq_bits : _T_2955 ? _Queue32_UInt8_49_io_deq_bits : _T_2954 ? _Queue32_UInt8_48_io_deq_bits : _T_2953 ? _Queue32_UInt8_47_io_deq_bits : _T_2952 ? _Queue32_UInt8_46_io_deq_bits : _T_2951 ? _Queue32_UInt8_45_io_deq_bits : _T_2950 ? _Queue32_UInt8_44_io_deq_bits : _T_2949 ? _Queue32_UInt8_43_io_deq_bits : _T_2948 ? _Queue32_UInt8_42_io_deq_bits : _T_2947 ? _Queue32_UInt8_41_io_deq_bits : _T_2946 ? _Queue32_UInt8_40_io_deq_bits : _T_2945 ? _Queue32_UInt8_39_io_deq_bits : _T_2944 ? _Queue32_UInt8_38_io_deq_bits : _T_2943 ? _Queue32_UInt8_37_io_deq_bits : _T_2942 ? _Queue32_UInt8_36_io_deq_bits : _T_2941 ? _Queue32_UInt8_35_io_deq_bits : _T_2940 ? _Queue32_UInt8_34_io_deq_bits : _T_2939 ? _Queue32_UInt8_33_io_deq_bits : _T_2938 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_19 = _T_2969 ? _Queue32_UInt8_63_io_deq_valid : _T_2968 ? _Queue32_UInt8_62_io_deq_valid : _T_2967 ? _Queue32_UInt8_61_io_deq_valid : _T_2966 ? _Queue32_UInt8_60_io_deq_valid : _T_2965 ? _Queue32_UInt8_59_io_deq_valid : _T_2964 ? _Queue32_UInt8_58_io_deq_valid : _T_2963 ? _Queue32_UInt8_57_io_deq_valid : _T_2962 ? _Queue32_UInt8_56_io_deq_valid : _T_2961 ? _Queue32_UInt8_55_io_deq_valid : _T_2960 ? _Queue32_UInt8_54_io_deq_valid : _T_2959 ? _Queue32_UInt8_53_io_deq_valid : _T_2958 ? _Queue32_UInt8_52_io_deq_valid : _T_2957 ? _Queue32_UInt8_51_io_deq_valid : _T_2956 ? _Queue32_UInt8_50_io_deq_valid : _T_2955 ? _Queue32_UInt8_49_io_deq_valid : _T_2954 ? _Queue32_UInt8_48_io_deq_valid : _T_2953 ? _Queue32_UInt8_47_io_deq_valid : _T_2952 ? _Queue32_UInt8_46_io_deq_valid : _T_2951 ? _Queue32_UInt8_45_io_deq_valid : _T_2950 ? _Queue32_UInt8_44_io_deq_valid : _T_2949 ? _Queue32_UInt8_43_io_deq_valid : _T_2948 ? _Queue32_UInt8_42_io_deq_valid : _T_2947 ? _Queue32_UInt8_41_io_deq_valid : _T_2946 ? _Queue32_UInt8_40_io_deq_valid : _T_2945 ? _Queue32_UInt8_39_io_deq_valid : _T_2944 ? _Queue32_UInt8_38_io_deq_valid : _T_2943 ? _Queue32_UInt8_37_io_deq_valid : _T_2942 ? _Queue32_UInt8_36_io_deq_valid : _T_2941 ? _Queue32_UInt8_35_io_deq_valid : _T_2940 ? _Queue32_UInt8_34_io_deq_valid : _T_2939 ? _Queue32_UInt8_33_io_deq_valid : _T_2938 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_111 = _remapindex_T_20 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_20 = _GEN_111[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_2970 = remapindex_20 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2971 = remapindex_20 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2972 = remapindex_20 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2973 = remapindex_20 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2974 = remapindex_20 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2975 = remapindex_20 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2976 = remapindex_20 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2977 = remapindex_20 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2978 = remapindex_20 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2979 = remapindex_20 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2980 = remapindex_20 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2981 = remapindex_20 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2982 = remapindex_20 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2983 = remapindex_20 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2984 = remapindex_20 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2985 = remapindex_20 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2986 = remapindex_20 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2987 = remapindex_20 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2988 = remapindex_20 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2989 = remapindex_20 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2990 = remapindex_20 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2991 = remapindex_20 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2992 = remapindex_20 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2993 = remapindex_20 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2994 = remapindex_20 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2995 = remapindex_20 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2996 = remapindex_20 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2997 = remapindex_20 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2998 = remapindex_20 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_2999 = remapindex_20 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3000 = remapindex_20 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3001 = remapindex_20 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_20 = _T_3001 ? _Queue32_UInt8_63_io_deq_bits : _T_3000 ? _Queue32_UInt8_62_io_deq_bits : _T_2999 ? _Queue32_UInt8_61_io_deq_bits : _T_2998 ? _Queue32_UInt8_60_io_deq_bits : _T_2997 ? _Queue32_UInt8_59_io_deq_bits : _T_2996 ? _Queue32_UInt8_58_io_deq_bits : _T_2995 ? _Queue32_UInt8_57_io_deq_bits : _T_2994 ? _Queue32_UInt8_56_io_deq_bits : _T_2993 ? _Queue32_UInt8_55_io_deq_bits : _T_2992 ? _Queue32_UInt8_54_io_deq_bits : _T_2991 ? _Queue32_UInt8_53_io_deq_bits : _T_2990 ? _Queue32_UInt8_52_io_deq_bits : _T_2989 ? _Queue32_UInt8_51_io_deq_bits : _T_2988 ? _Queue32_UInt8_50_io_deq_bits : _T_2987 ? _Queue32_UInt8_49_io_deq_bits : _T_2986 ? _Queue32_UInt8_48_io_deq_bits : _T_2985 ? _Queue32_UInt8_47_io_deq_bits : _T_2984 ? _Queue32_UInt8_46_io_deq_bits : _T_2983 ? _Queue32_UInt8_45_io_deq_bits : _T_2982 ? _Queue32_UInt8_44_io_deq_bits : _T_2981 ? _Queue32_UInt8_43_io_deq_bits : _T_2980 ? _Queue32_UInt8_42_io_deq_bits : _T_2979 ? _Queue32_UInt8_41_io_deq_bits : _T_2978 ? _Queue32_UInt8_40_io_deq_bits : _T_2977 ? _Queue32_UInt8_39_io_deq_bits : _T_2976 ? _Queue32_UInt8_38_io_deq_bits : _T_2975 ? _Queue32_UInt8_37_io_deq_bits : _T_2974 ? _Queue32_UInt8_36_io_deq_bits : _T_2973 ? _Queue32_UInt8_35_io_deq_bits : _T_2972 ? _Queue32_UInt8_34_io_deq_bits : _T_2971 ? _Queue32_UInt8_33_io_deq_bits : _T_2970 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_20 = _T_3001 ? _Queue32_UInt8_63_io_deq_valid : _T_3000 ? _Queue32_UInt8_62_io_deq_valid : _T_2999 ? _Queue32_UInt8_61_io_deq_valid : _T_2998 ? _Queue32_UInt8_60_io_deq_valid : _T_2997 ? _Queue32_UInt8_59_io_deq_valid : _T_2996 ? _Queue32_UInt8_58_io_deq_valid : _T_2995 ? _Queue32_UInt8_57_io_deq_valid : _T_2994 ? _Queue32_UInt8_56_io_deq_valid : _T_2993 ? _Queue32_UInt8_55_io_deq_valid : _T_2992 ? _Queue32_UInt8_54_io_deq_valid : _T_2991 ? _Queue32_UInt8_53_io_deq_valid : _T_2990 ? _Queue32_UInt8_52_io_deq_valid : _T_2989 ? _Queue32_UInt8_51_io_deq_valid : _T_2988 ? _Queue32_UInt8_50_io_deq_valid : _T_2987 ? _Queue32_UInt8_49_io_deq_valid : _T_2986 ? _Queue32_UInt8_48_io_deq_valid : _T_2985 ? _Queue32_UInt8_47_io_deq_valid : _T_2984 ? _Queue32_UInt8_46_io_deq_valid : _T_2983 ? _Queue32_UInt8_45_io_deq_valid : _T_2982 ? _Queue32_UInt8_44_io_deq_valid : _T_2981 ? _Queue32_UInt8_43_io_deq_valid : _T_2980 ? _Queue32_UInt8_42_io_deq_valid : _T_2979 ? _Queue32_UInt8_41_io_deq_valid : _T_2978 ? _Queue32_UInt8_40_io_deq_valid : _T_2977 ? _Queue32_UInt8_39_io_deq_valid : _T_2976 ? _Queue32_UInt8_38_io_deq_valid : _T_2975 ? _Queue32_UInt8_37_io_deq_valid : _T_2974 ? _Queue32_UInt8_36_io_deq_valid : _T_2973 ? _Queue32_UInt8_35_io_deq_valid : _T_2972 ? _Queue32_UInt8_34_io_deq_valid : _T_2971 ? _Queue32_UInt8_33_io_deq_valid : _T_2970 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_112 = _remapindex_T_21 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_21 = _GEN_112[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_3002 = remapindex_21 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3003 = remapindex_21 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3004 = remapindex_21 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3005 = remapindex_21 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3006 = remapindex_21 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3007 = remapindex_21 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3008 = remapindex_21 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3009 = remapindex_21 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3010 = remapindex_21 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3011 = remapindex_21 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3012 = remapindex_21 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3013 = remapindex_21 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3014 = remapindex_21 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3015 = remapindex_21 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3016 = remapindex_21 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3017 = remapindex_21 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3018 = remapindex_21 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3019 = remapindex_21 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3020 = remapindex_21 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3021 = remapindex_21 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3022 = remapindex_21 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3023 = remapindex_21 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3024 = remapindex_21 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3025 = remapindex_21 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3026 = remapindex_21 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3027 = remapindex_21 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3028 = remapindex_21 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3029 = remapindex_21 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3030 = remapindex_21 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3031 = remapindex_21 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3032 = remapindex_21 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3033 = remapindex_21 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_21 = _T_3033 ? _Queue32_UInt8_63_io_deq_bits : _T_3032 ? _Queue32_UInt8_62_io_deq_bits : _T_3031 ? _Queue32_UInt8_61_io_deq_bits : _T_3030 ? _Queue32_UInt8_60_io_deq_bits : _T_3029 ? _Queue32_UInt8_59_io_deq_bits : _T_3028 ? _Queue32_UInt8_58_io_deq_bits : _T_3027 ? _Queue32_UInt8_57_io_deq_bits : _T_3026 ? _Queue32_UInt8_56_io_deq_bits : _T_3025 ? _Queue32_UInt8_55_io_deq_bits : _T_3024 ? _Queue32_UInt8_54_io_deq_bits : _T_3023 ? _Queue32_UInt8_53_io_deq_bits : _T_3022 ? _Queue32_UInt8_52_io_deq_bits : _T_3021 ? _Queue32_UInt8_51_io_deq_bits : _T_3020 ? _Queue32_UInt8_50_io_deq_bits : _T_3019 ? _Queue32_UInt8_49_io_deq_bits : _T_3018 ? _Queue32_UInt8_48_io_deq_bits : _T_3017 ? _Queue32_UInt8_47_io_deq_bits : _T_3016 ? _Queue32_UInt8_46_io_deq_bits : _T_3015 ? _Queue32_UInt8_45_io_deq_bits : _T_3014 ? _Queue32_UInt8_44_io_deq_bits : _T_3013 ? _Queue32_UInt8_43_io_deq_bits : _T_3012 ? _Queue32_UInt8_42_io_deq_bits : _T_3011 ? _Queue32_UInt8_41_io_deq_bits : _T_3010 ? _Queue32_UInt8_40_io_deq_bits : _T_3009 ? _Queue32_UInt8_39_io_deq_bits : _T_3008 ? _Queue32_UInt8_38_io_deq_bits : _T_3007 ? _Queue32_UInt8_37_io_deq_bits : _T_3006 ? _Queue32_UInt8_36_io_deq_bits : _T_3005 ? _Queue32_UInt8_35_io_deq_bits : _T_3004 ? _Queue32_UInt8_34_io_deq_bits : _T_3003 ? _Queue32_UInt8_33_io_deq_bits : _T_3002 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_21 = _T_3033 ? _Queue32_UInt8_63_io_deq_valid : _T_3032 ? _Queue32_UInt8_62_io_deq_valid : _T_3031 ? _Queue32_UInt8_61_io_deq_valid : _T_3030 ? _Queue32_UInt8_60_io_deq_valid : _T_3029 ? _Queue32_UInt8_59_io_deq_valid : _T_3028 ? _Queue32_UInt8_58_io_deq_valid : _T_3027 ? _Queue32_UInt8_57_io_deq_valid : _T_3026 ? _Queue32_UInt8_56_io_deq_valid : _T_3025 ? _Queue32_UInt8_55_io_deq_valid : _T_3024 ? _Queue32_UInt8_54_io_deq_valid : _T_3023 ? _Queue32_UInt8_53_io_deq_valid : _T_3022 ? _Queue32_UInt8_52_io_deq_valid : _T_3021 ? _Queue32_UInt8_51_io_deq_valid : _T_3020 ? _Queue32_UInt8_50_io_deq_valid : _T_3019 ? _Queue32_UInt8_49_io_deq_valid : _T_3018 ? _Queue32_UInt8_48_io_deq_valid : _T_3017 ? _Queue32_UInt8_47_io_deq_valid : _T_3016 ? _Queue32_UInt8_46_io_deq_valid : _T_3015 ? _Queue32_UInt8_45_io_deq_valid : _T_3014 ? _Queue32_UInt8_44_io_deq_valid : _T_3013 ? _Queue32_UInt8_43_io_deq_valid : _T_3012 ? _Queue32_UInt8_42_io_deq_valid : _T_3011 ? _Queue32_UInt8_41_io_deq_valid : _T_3010 ? _Queue32_UInt8_40_io_deq_valid : _T_3009 ? _Queue32_UInt8_39_io_deq_valid : _T_3008 ? _Queue32_UInt8_38_io_deq_valid : _T_3007 ? _Queue32_UInt8_37_io_deq_valid : _T_3006 ? _Queue32_UInt8_36_io_deq_valid : _T_3005 ? _Queue32_UInt8_35_io_deq_valid : _T_3004 ? _Queue32_UInt8_34_io_deq_valid : _T_3003 ? _Queue32_UInt8_33_io_deq_valid : _T_3002 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_113 = _remapindex_T_22 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_22 = _GEN_113[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_3034 = remapindex_22 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3035 = remapindex_22 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3036 = remapindex_22 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3037 = remapindex_22 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3038 = remapindex_22 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3039 = remapindex_22 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3040 = remapindex_22 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3041 = remapindex_22 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3042 = remapindex_22 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3043 = remapindex_22 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3044 = remapindex_22 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3045 = remapindex_22 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3046 = remapindex_22 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3047 = remapindex_22 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3048 = remapindex_22 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3049 = remapindex_22 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3050 = remapindex_22 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3051 = remapindex_22 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3052 = remapindex_22 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3053 = remapindex_22 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3054 = remapindex_22 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3055 = remapindex_22 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3056 = remapindex_22 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3057 = remapindex_22 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3058 = remapindex_22 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3059 = remapindex_22 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3060 = remapindex_22 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3061 = remapindex_22 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3062 = remapindex_22 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3063 = remapindex_22 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3064 = remapindex_22 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3065 = remapindex_22 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_22 = _T_3065 ? _Queue32_UInt8_63_io_deq_bits : _T_3064 ? _Queue32_UInt8_62_io_deq_bits : _T_3063 ? _Queue32_UInt8_61_io_deq_bits : _T_3062 ? _Queue32_UInt8_60_io_deq_bits : _T_3061 ? _Queue32_UInt8_59_io_deq_bits : _T_3060 ? _Queue32_UInt8_58_io_deq_bits : _T_3059 ? _Queue32_UInt8_57_io_deq_bits : _T_3058 ? _Queue32_UInt8_56_io_deq_bits : _T_3057 ? _Queue32_UInt8_55_io_deq_bits : _T_3056 ? _Queue32_UInt8_54_io_deq_bits : _T_3055 ? _Queue32_UInt8_53_io_deq_bits : _T_3054 ? _Queue32_UInt8_52_io_deq_bits : _T_3053 ? _Queue32_UInt8_51_io_deq_bits : _T_3052 ? _Queue32_UInt8_50_io_deq_bits : _T_3051 ? _Queue32_UInt8_49_io_deq_bits : _T_3050 ? _Queue32_UInt8_48_io_deq_bits : _T_3049 ? _Queue32_UInt8_47_io_deq_bits : _T_3048 ? _Queue32_UInt8_46_io_deq_bits : _T_3047 ? _Queue32_UInt8_45_io_deq_bits : _T_3046 ? _Queue32_UInt8_44_io_deq_bits : _T_3045 ? _Queue32_UInt8_43_io_deq_bits : _T_3044 ? _Queue32_UInt8_42_io_deq_bits : _T_3043 ? _Queue32_UInt8_41_io_deq_bits : _T_3042 ? _Queue32_UInt8_40_io_deq_bits : _T_3041 ? _Queue32_UInt8_39_io_deq_bits : _T_3040 ? _Queue32_UInt8_38_io_deq_bits : _T_3039 ? _Queue32_UInt8_37_io_deq_bits : _T_3038 ? _Queue32_UInt8_36_io_deq_bits : _T_3037 ? _Queue32_UInt8_35_io_deq_bits : _T_3036 ? _Queue32_UInt8_34_io_deq_bits : _T_3035 ? _Queue32_UInt8_33_io_deq_bits : _T_3034 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_22 = _T_3065 ? _Queue32_UInt8_63_io_deq_valid : _T_3064 ? _Queue32_UInt8_62_io_deq_valid : _T_3063 ? _Queue32_UInt8_61_io_deq_valid : _T_3062 ? _Queue32_UInt8_60_io_deq_valid : _T_3061 ? _Queue32_UInt8_59_io_deq_valid : _T_3060 ? _Queue32_UInt8_58_io_deq_valid : _T_3059 ? _Queue32_UInt8_57_io_deq_valid : _T_3058 ? _Queue32_UInt8_56_io_deq_valid : _T_3057 ? _Queue32_UInt8_55_io_deq_valid : _T_3056 ? _Queue32_UInt8_54_io_deq_valid : _T_3055 ? _Queue32_UInt8_53_io_deq_valid : _T_3054 ? _Queue32_UInt8_52_io_deq_valid : _T_3053 ? _Queue32_UInt8_51_io_deq_valid : _T_3052 ? _Queue32_UInt8_50_io_deq_valid : _T_3051 ? _Queue32_UInt8_49_io_deq_valid : _T_3050 ? _Queue32_UInt8_48_io_deq_valid : _T_3049 ? _Queue32_UInt8_47_io_deq_valid : _T_3048 ? _Queue32_UInt8_46_io_deq_valid : _T_3047 ? _Queue32_UInt8_45_io_deq_valid : _T_3046 ? _Queue32_UInt8_44_io_deq_valid : _T_3045 ? _Queue32_UInt8_43_io_deq_valid : _T_3044 ? _Queue32_UInt8_42_io_deq_valid : _T_3043 ? _Queue32_UInt8_41_io_deq_valid : _T_3042 ? _Queue32_UInt8_40_io_deq_valid : _T_3041 ? _Queue32_UInt8_39_io_deq_valid : _T_3040 ? _Queue32_UInt8_38_io_deq_valid : _T_3039 ? _Queue32_UInt8_37_io_deq_valid : _T_3038 ? _Queue32_UInt8_36_io_deq_valid : _T_3037 ? _Queue32_UInt8_35_io_deq_valid : _T_3036 ? _Queue32_UInt8_34_io_deq_valid : _T_3035 ? _Queue32_UInt8_33_io_deq_valid : _T_3034 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_114 = _remapindex_T_23 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_23 = _GEN_114[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_3066 = remapindex_23 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3067 = remapindex_23 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3068 = remapindex_23 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3069 = remapindex_23 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3070 = remapindex_23 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3071 = remapindex_23 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3072 = remapindex_23 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3073 = remapindex_23 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3074 = remapindex_23 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3075 = remapindex_23 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3076 = remapindex_23 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3077 = remapindex_23 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3078 = remapindex_23 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3079 = remapindex_23 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3080 = remapindex_23 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3081 = remapindex_23 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3082 = remapindex_23 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3083 = remapindex_23 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3084 = remapindex_23 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3085 = remapindex_23 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3086 = remapindex_23 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3087 = remapindex_23 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3088 = remapindex_23 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3089 = remapindex_23 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3090 = remapindex_23 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3091 = remapindex_23 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3092 = remapindex_23 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3093 = remapindex_23 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3094 = remapindex_23 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3095 = remapindex_23 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3096 = remapindex_23 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3097 = remapindex_23 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_23 = _T_3097 ? _Queue32_UInt8_63_io_deq_bits : _T_3096 ? _Queue32_UInt8_62_io_deq_bits : _T_3095 ? _Queue32_UInt8_61_io_deq_bits : _T_3094 ? _Queue32_UInt8_60_io_deq_bits : _T_3093 ? _Queue32_UInt8_59_io_deq_bits : _T_3092 ? _Queue32_UInt8_58_io_deq_bits : _T_3091 ? _Queue32_UInt8_57_io_deq_bits : _T_3090 ? _Queue32_UInt8_56_io_deq_bits : _T_3089 ? _Queue32_UInt8_55_io_deq_bits : _T_3088 ? _Queue32_UInt8_54_io_deq_bits : _T_3087 ? _Queue32_UInt8_53_io_deq_bits : _T_3086 ? _Queue32_UInt8_52_io_deq_bits : _T_3085 ? _Queue32_UInt8_51_io_deq_bits : _T_3084 ? _Queue32_UInt8_50_io_deq_bits : _T_3083 ? _Queue32_UInt8_49_io_deq_bits : _T_3082 ? _Queue32_UInt8_48_io_deq_bits : _T_3081 ? _Queue32_UInt8_47_io_deq_bits : _T_3080 ? _Queue32_UInt8_46_io_deq_bits : _T_3079 ? _Queue32_UInt8_45_io_deq_bits : _T_3078 ? _Queue32_UInt8_44_io_deq_bits : _T_3077 ? _Queue32_UInt8_43_io_deq_bits : _T_3076 ? _Queue32_UInt8_42_io_deq_bits : _T_3075 ? _Queue32_UInt8_41_io_deq_bits : _T_3074 ? _Queue32_UInt8_40_io_deq_bits : _T_3073 ? _Queue32_UInt8_39_io_deq_bits : _T_3072 ? _Queue32_UInt8_38_io_deq_bits : _T_3071 ? _Queue32_UInt8_37_io_deq_bits : _T_3070 ? _Queue32_UInt8_36_io_deq_bits : _T_3069 ? _Queue32_UInt8_35_io_deq_bits : _T_3068 ? _Queue32_UInt8_34_io_deq_bits : _T_3067 ? _Queue32_UInt8_33_io_deq_bits : _T_3066 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_23 = _T_3097 ? _Queue32_UInt8_63_io_deq_valid : _T_3096 ? _Queue32_UInt8_62_io_deq_valid : _T_3095 ? _Queue32_UInt8_61_io_deq_valid : _T_3094 ? _Queue32_UInt8_60_io_deq_valid : _T_3093 ? _Queue32_UInt8_59_io_deq_valid : _T_3092 ? _Queue32_UInt8_58_io_deq_valid : _T_3091 ? _Queue32_UInt8_57_io_deq_valid : _T_3090 ? _Queue32_UInt8_56_io_deq_valid : _T_3089 ? _Queue32_UInt8_55_io_deq_valid : _T_3088 ? _Queue32_UInt8_54_io_deq_valid : _T_3087 ? _Queue32_UInt8_53_io_deq_valid : _T_3086 ? _Queue32_UInt8_52_io_deq_valid : _T_3085 ? _Queue32_UInt8_51_io_deq_valid : _T_3084 ? _Queue32_UInt8_50_io_deq_valid : _T_3083 ? _Queue32_UInt8_49_io_deq_valid : _T_3082 ? _Queue32_UInt8_48_io_deq_valid : _T_3081 ? _Queue32_UInt8_47_io_deq_valid : _T_3080 ? _Queue32_UInt8_46_io_deq_valid : _T_3079 ? _Queue32_UInt8_45_io_deq_valid : _T_3078 ? _Queue32_UInt8_44_io_deq_valid : _T_3077 ? _Queue32_UInt8_43_io_deq_valid : _T_3076 ? _Queue32_UInt8_42_io_deq_valid : _T_3075 ? _Queue32_UInt8_41_io_deq_valid : _T_3074 ? _Queue32_UInt8_40_io_deq_valid : _T_3073 ? _Queue32_UInt8_39_io_deq_valid : _T_3072 ? _Queue32_UInt8_38_io_deq_valid : _T_3071 ? _Queue32_UInt8_37_io_deq_valid : _T_3070 ? _Queue32_UInt8_36_io_deq_valid : _T_3069 ? _Queue32_UInt8_35_io_deq_valid : _T_3068 ? _Queue32_UInt8_34_io_deq_valid : _T_3067 ? _Queue32_UInt8_33_io_deq_valid : _T_3066 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_115 = _remapindex_T_24 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_24 = _GEN_115[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_3098 = remapindex_24 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3099 = remapindex_24 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3100 = remapindex_24 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3101 = remapindex_24 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3102 = remapindex_24 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3103 = remapindex_24 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3104 = remapindex_24 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3105 = remapindex_24 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3106 = remapindex_24 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3107 = remapindex_24 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3108 = remapindex_24 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3109 = remapindex_24 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3110 = remapindex_24 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3111 = remapindex_24 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3112 = remapindex_24 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3113 = remapindex_24 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3114 = remapindex_24 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3115 = remapindex_24 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3116 = remapindex_24 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3117 = remapindex_24 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3118 = remapindex_24 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3119 = remapindex_24 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3120 = remapindex_24 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3121 = remapindex_24 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3122 = remapindex_24 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3123 = remapindex_24 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3124 = remapindex_24 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3125 = remapindex_24 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3126 = remapindex_24 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3127 = remapindex_24 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3128 = remapindex_24 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3129 = remapindex_24 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_24 = _T_3129 ? _Queue32_UInt8_63_io_deq_bits : _T_3128 ? _Queue32_UInt8_62_io_deq_bits : _T_3127 ? _Queue32_UInt8_61_io_deq_bits : _T_3126 ? _Queue32_UInt8_60_io_deq_bits : _T_3125 ? _Queue32_UInt8_59_io_deq_bits : _T_3124 ? _Queue32_UInt8_58_io_deq_bits : _T_3123 ? _Queue32_UInt8_57_io_deq_bits : _T_3122 ? _Queue32_UInt8_56_io_deq_bits : _T_3121 ? _Queue32_UInt8_55_io_deq_bits : _T_3120 ? _Queue32_UInt8_54_io_deq_bits : _T_3119 ? _Queue32_UInt8_53_io_deq_bits : _T_3118 ? _Queue32_UInt8_52_io_deq_bits : _T_3117 ? _Queue32_UInt8_51_io_deq_bits : _T_3116 ? _Queue32_UInt8_50_io_deq_bits : _T_3115 ? _Queue32_UInt8_49_io_deq_bits : _T_3114 ? _Queue32_UInt8_48_io_deq_bits : _T_3113 ? _Queue32_UInt8_47_io_deq_bits : _T_3112 ? _Queue32_UInt8_46_io_deq_bits : _T_3111 ? _Queue32_UInt8_45_io_deq_bits : _T_3110 ? _Queue32_UInt8_44_io_deq_bits : _T_3109 ? _Queue32_UInt8_43_io_deq_bits : _T_3108 ? _Queue32_UInt8_42_io_deq_bits : _T_3107 ? _Queue32_UInt8_41_io_deq_bits : _T_3106 ? _Queue32_UInt8_40_io_deq_bits : _T_3105 ? _Queue32_UInt8_39_io_deq_bits : _T_3104 ? _Queue32_UInt8_38_io_deq_bits : _T_3103 ? _Queue32_UInt8_37_io_deq_bits : _T_3102 ? _Queue32_UInt8_36_io_deq_bits : _T_3101 ? _Queue32_UInt8_35_io_deq_bits : _T_3100 ? _Queue32_UInt8_34_io_deq_bits : _T_3099 ? _Queue32_UInt8_33_io_deq_bits : _T_3098 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_24 = _T_3129 ? _Queue32_UInt8_63_io_deq_valid : _T_3128 ? _Queue32_UInt8_62_io_deq_valid : _T_3127 ? _Queue32_UInt8_61_io_deq_valid : _T_3126 ? _Queue32_UInt8_60_io_deq_valid : _T_3125 ? _Queue32_UInt8_59_io_deq_valid : _T_3124 ? _Queue32_UInt8_58_io_deq_valid : _T_3123 ? _Queue32_UInt8_57_io_deq_valid : _T_3122 ? _Queue32_UInt8_56_io_deq_valid : _T_3121 ? _Queue32_UInt8_55_io_deq_valid : _T_3120 ? _Queue32_UInt8_54_io_deq_valid : _T_3119 ? _Queue32_UInt8_53_io_deq_valid : _T_3118 ? _Queue32_UInt8_52_io_deq_valid : _T_3117 ? _Queue32_UInt8_51_io_deq_valid : _T_3116 ? _Queue32_UInt8_50_io_deq_valid : _T_3115 ? _Queue32_UInt8_49_io_deq_valid : _T_3114 ? _Queue32_UInt8_48_io_deq_valid : _T_3113 ? _Queue32_UInt8_47_io_deq_valid : _T_3112 ? _Queue32_UInt8_46_io_deq_valid : _T_3111 ? _Queue32_UInt8_45_io_deq_valid : _T_3110 ? _Queue32_UInt8_44_io_deq_valid : _T_3109 ? _Queue32_UInt8_43_io_deq_valid : _T_3108 ? _Queue32_UInt8_42_io_deq_valid : _T_3107 ? _Queue32_UInt8_41_io_deq_valid : _T_3106 ? _Queue32_UInt8_40_io_deq_valid : _T_3105 ? _Queue32_UInt8_39_io_deq_valid : _T_3104 ? _Queue32_UInt8_38_io_deq_valid : _T_3103 ? _Queue32_UInt8_37_io_deq_valid : _T_3102 ? _Queue32_UInt8_36_io_deq_valid : _T_3101 ? _Queue32_UInt8_35_io_deq_valid : _T_3100 ? _Queue32_UInt8_34_io_deq_valid : _T_3099 ? _Queue32_UInt8_33_io_deq_valid : _T_3098 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_116 = _remapindex_T_25 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_25 = _GEN_116[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_3130 = remapindex_25 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3131 = remapindex_25 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3132 = remapindex_25 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3133 = remapindex_25 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3134 = remapindex_25 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3135 = remapindex_25 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3136 = remapindex_25 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3137 = remapindex_25 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3138 = remapindex_25 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3139 = remapindex_25 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3140 = remapindex_25 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3141 = remapindex_25 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3142 = remapindex_25 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3143 = remapindex_25 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3144 = remapindex_25 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3145 = remapindex_25 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3146 = remapindex_25 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3147 = remapindex_25 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3148 = remapindex_25 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3149 = remapindex_25 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3150 = remapindex_25 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3151 = remapindex_25 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3152 = remapindex_25 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3153 = remapindex_25 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3154 = remapindex_25 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3155 = remapindex_25 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3156 = remapindex_25 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3157 = remapindex_25 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3158 = remapindex_25 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3159 = remapindex_25 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3160 = remapindex_25 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3161 = remapindex_25 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_25 = _T_3161 ? _Queue32_UInt8_63_io_deq_bits : _T_3160 ? _Queue32_UInt8_62_io_deq_bits : _T_3159 ? _Queue32_UInt8_61_io_deq_bits : _T_3158 ? _Queue32_UInt8_60_io_deq_bits : _T_3157 ? _Queue32_UInt8_59_io_deq_bits : _T_3156 ? _Queue32_UInt8_58_io_deq_bits : _T_3155 ? _Queue32_UInt8_57_io_deq_bits : _T_3154 ? _Queue32_UInt8_56_io_deq_bits : _T_3153 ? _Queue32_UInt8_55_io_deq_bits : _T_3152 ? _Queue32_UInt8_54_io_deq_bits : _T_3151 ? _Queue32_UInt8_53_io_deq_bits : _T_3150 ? _Queue32_UInt8_52_io_deq_bits : _T_3149 ? _Queue32_UInt8_51_io_deq_bits : _T_3148 ? _Queue32_UInt8_50_io_deq_bits : _T_3147 ? _Queue32_UInt8_49_io_deq_bits : _T_3146 ? _Queue32_UInt8_48_io_deq_bits : _T_3145 ? _Queue32_UInt8_47_io_deq_bits : _T_3144 ? _Queue32_UInt8_46_io_deq_bits : _T_3143 ? _Queue32_UInt8_45_io_deq_bits : _T_3142 ? _Queue32_UInt8_44_io_deq_bits : _T_3141 ? _Queue32_UInt8_43_io_deq_bits : _T_3140 ? _Queue32_UInt8_42_io_deq_bits : _T_3139 ? _Queue32_UInt8_41_io_deq_bits : _T_3138 ? _Queue32_UInt8_40_io_deq_bits : _T_3137 ? _Queue32_UInt8_39_io_deq_bits : _T_3136 ? _Queue32_UInt8_38_io_deq_bits : _T_3135 ? _Queue32_UInt8_37_io_deq_bits : _T_3134 ? _Queue32_UInt8_36_io_deq_bits : _T_3133 ? _Queue32_UInt8_35_io_deq_bits : _T_3132 ? _Queue32_UInt8_34_io_deq_bits : _T_3131 ? _Queue32_UInt8_33_io_deq_bits : _T_3130 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_25 = _T_3161 ? _Queue32_UInt8_63_io_deq_valid : _T_3160 ? _Queue32_UInt8_62_io_deq_valid : _T_3159 ? _Queue32_UInt8_61_io_deq_valid : _T_3158 ? _Queue32_UInt8_60_io_deq_valid : _T_3157 ? _Queue32_UInt8_59_io_deq_valid : _T_3156 ? _Queue32_UInt8_58_io_deq_valid : _T_3155 ? _Queue32_UInt8_57_io_deq_valid : _T_3154 ? _Queue32_UInt8_56_io_deq_valid : _T_3153 ? _Queue32_UInt8_55_io_deq_valid : _T_3152 ? _Queue32_UInt8_54_io_deq_valid : _T_3151 ? _Queue32_UInt8_53_io_deq_valid : _T_3150 ? _Queue32_UInt8_52_io_deq_valid : _T_3149 ? _Queue32_UInt8_51_io_deq_valid : _T_3148 ? _Queue32_UInt8_50_io_deq_valid : _T_3147 ? _Queue32_UInt8_49_io_deq_valid : _T_3146 ? _Queue32_UInt8_48_io_deq_valid : _T_3145 ? _Queue32_UInt8_47_io_deq_valid : _T_3144 ? _Queue32_UInt8_46_io_deq_valid : _T_3143 ? _Queue32_UInt8_45_io_deq_valid : _T_3142 ? _Queue32_UInt8_44_io_deq_valid : _T_3141 ? _Queue32_UInt8_43_io_deq_valid : _T_3140 ? _Queue32_UInt8_42_io_deq_valid : _T_3139 ? _Queue32_UInt8_41_io_deq_valid : _T_3138 ? _Queue32_UInt8_40_io_deq_valid : _T_3137 ? _Queue32_UInt8_39_io_deq_valid : _T_3136 ? _Queue32_UInt8_38_io_deq_valid : _T_3135 ? _Queue32_UInt8_37_io_deq_valid : _T_3134 ? _Queue32_UInt8_36_io_deq_valid : _T_3133 ? _Queue32_UInt8_35_io_deq_valid : _T_3132 ? _Queue32_UInt8_34_io_deq_valid : _T_3131 ? _Queue32_UInt8_33_io_deq_valid : _T_3130 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_117 = _remapindex_T_26 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_26 = _GEN_117[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_3162 = remapindex_26 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3163 = remapindex_26 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3164 = remapindex_26 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3165 = remapindex_26 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3166 = remapindex_26 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3167 = remapindex_26 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3168 = remapindex_26 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3169 = remapindex_26 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3170 = remapindex_26 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3171 = remapindex_26 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3172 = remapindex_26 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3173 = remapindex_26 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3174 = remapindex_26 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3175 = remapindex_26 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3176 = remapindex_26 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3177 = remapindex_26 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3178 = remapindex_26 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3179 = remapindex_26 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3180 = remapindex_26 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3181 = remapindex_26 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3182 = remapindex_26 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3183 = remapindex_26 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3184 = remapindex_26 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3185 = remapindex_26 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3186 = remapindex_26 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3187 = remapindex_26 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3188 = remapindex_26 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3189 = remapindex_26 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3190 = remapindex_26 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3191 = remapindex_26 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3192 = remapindex_26 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3193 = remapindex_26 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_26 = _T_3193 ? _Queue32_UInt8_63_io_deq_bits : _T_3192 ? _Queue32_UInt8_62_io_deq_bits : _T_3191 ? _Queue32_UInt8_61_io_deq_bits : _T_3190 ? _Queue32_UInt8_60_io_deq_bits : _T_3189 ? _Queue32_UInt8_59_io_deq_bits : _T_3188 ? _Queue32_UInt8_58_io_deq_bits : _T_3187 ? _Queue32_UInt8_57_io_deq_bits : _T_3186 ? _Queue32_UInt8_56_io_deq_bits : _T_3185 ? _Queue32_UInt8_55_io_deq_bits : _T_3184 ? _Queue32_UInt8_54_io_deq_bits : _T_3183 ? _Queue32_UInt8_53_io_deq_bits : _T_3182 ? _Queue32_UInt8_52_io_deq_bits : _T_3181 ? _Queue32_UInt8_51_io_deq_bits : _T_3180 ? _Queue32_UInt8_50_io_deq_bits : _T_3179 ? _Queue32_UInt8_49_io_deq_bits : _T_3178 ? _Queue32_UInt8_48_io_deq_bits : _T_3177 ? _Queue32_UInt8_47_io_deq_bits : _T_3176 ? _Queue32_UInt8_46_io_deq_bits : _T_3175 ? _Queue32_UInt8_45_io_deq_bits : _T_3174 ? _Queue32_UInt8_44_io_deq_bits : _T_3173 ? _Queue32_UInt8_43_io_deq_bits : _T_3172 ? _Queue32_UInt8_42_io_deq_bits : _T_3171 ? _Queue32_UInt8_41_io_deq_bits : _T_3170 ? _Queue32_UInt8_40_io_deq_bits : _T_3169 ? _Queue32_UInt8_39_io_deq_bits : _T_3168 ? _Queue32_UInt8_38_io_deq_bits : _T_3167 ? _Queue32_UInt8_37_io_deq_bits : _T_3166 ? _Queue32_UInt8_36_io_deq_bits : _T_3165 ? _Queue32_UInt8_35_io_deq_bits : _T_3164 ? _Queue32_UInt8_34_io_deq_bits : _T_3163 ? _Queue32_UInt8_33_io_deq_bits : _T_3162 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_26 = _T_3193 ? _Queue32_UInt8_63_io_deq_valid : _T_3192 ? _Queue32_UInt8_62_io_deq_valid : _T_3191 ? _Queue32_UInt8_61_io_deq_valid : _T_3190 ? _Queue32_UInt8_60_io_deq_valid : _T_3189 ? _Queue32_UInt8_59_io_deq_valid : _T_3188 ? _Queue32_UInt8_58_io_deq_valid : _T_3187 ? _Queue32_UInt8_57_io_deq_valid : _T_3186 ? _Queue32_UInt8_56_io_deq_valid : _T_3185 ? _Queue32_UInt8_55_io_deq_valid : _T_3184 ? _Queue32_UInt8_54_io_deq_valid : _T_3183 ? _Queue32_UInt8_53_io_deq_valid : _T_3182 ? _Queue32_UInt8_52_io_deq_valid : _T_3181 ? _Queue32_UInt8_51_io_deq_valid : _T_3180 ? _Queue32_UInt8_50_io_deq_valid : _T_3179 ? _Queue32_UInt8_49_io_deq_valid : _T_3178 ? _Queue32_UInt8_48_io_deq_valid : _T_3177 ? _Queue32_UInt8_47_io_deq_valid : _T_3176 ? _Queue32_UInt8_46_io_deq_valid : _T_3175 ? _Queue32_UInt8_45_io_deq_valid : _T_3174 ? _Queue32_UInt8_44_io_deq_valid : _T_3173 ? _Queue32_UInt8_43_io_deq_valid : _T_3172 ? _Queue32_UInt8_42_io_deq_valid : _T_3171 ? _Queue32_UInt8_41_io_deq_valid : _T_3170 ? _Queue32_UInt8_40_io_deq_valid : _T_3169 ? _Queue32_UInt8_39_io_deq_valid : _T_3168 ? _Queue32_UInt8_38_io_deq_valid : _T_3167 ? _Queue32_UInt8_37_io_deq_valid : _T_3166 ? _Queue32_UInt8_36_io_deq_valid : _T_3165 ? _Queue32_UInt8_35_io_deq_valid : _T_3164 ? _Queue32_UInt8_34_io_deq_valid : _T_3163 ? _Queue32_UInt8_33_io_deq_valid : _T_3162 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_118 = _remapindex_T_27 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_27 = _GEN_118[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_3194 = remapindex_27 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3195 = remapindex_27 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3196 = remapindex_27 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3197 = remapindex_27 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3198 = remapindex_27 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3199 = remapindex_27 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3200 = remapindex_27 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3201 = remapindex_27 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3202 = remapindex_27 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3203 = remapindex_27 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3204 = remapindex_27 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3205 = remapindex_27 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3206 = remapindex_27 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3207 = remapindex_27 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3208 = remapindex_27 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3209 = remapindex_27 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3210 = remapindex_27 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3211 = remapindex_27 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3212 = remapindex_27 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3213 = remapindex_27 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3214 = remapindex_27 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3215 = remapindex_27 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3216 = remapindex_27 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3217 = remapindex_27 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3218 = remapindex_27 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3219 = remapindex_27 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3220 = remapindex_27 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3221 = remapindex_27 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3222 = remapindex_27 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3223 = remapindex_27 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3224 = remapindex_27 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3225 = remapindex_27 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_27 = _T_3225 ? _Queue32_UInt8_63_io_deq_bits : _T_3224 ? _Queue32_UInt8_62_io_deq_bits : _T_3223 ? _Queue32_UInt8_61_io_deq_bits : _T_3222 ? _Queue32_UInt8_60_io_deq_bits : _T_3221 ? _Queue32_UInt8_59_io_deq_bits : _T_3220 ? _Queue32_UInt8_58_io_deq_bits : _T_3219 ? _Queue32_UInt8_57_io_deq_bits : _T_3218 ? _Queue32_UInt8_56_io_deq_bits : _T_3217 ? _Queue32_UInt8_55_io_deq_bits : _T_3216 ? _Queue32_UInt8_54_io_deq_bits : _T_3215 ? _Queue32_UInt8_53_io_deq_bits : _T_3214 ? _Queue32_UInt8_52_io_deq_bits : _T_3213 ? _Queue32_UInt8_51_io_deq_bits : _T_3212 ? _Queue32_UInt8_50_io_deq_bits : _T_3211 ? _Queue32_UInt8_49_io_deq_bits : _T_3210 ? _Queue32_UInt8_48_io_deq_bits : _T_3209 ? _Queue32_UInt8_47_io_deq_bits : _T_3208 ? _Queue32_UInt8_46_io_deq_bits : _T_3207 ? _Queue32_UInt8_45_io_deq_bits : _T_3206 ? _Queue32_UInt8_44_io_deq_bits : _T_3205 ? _Queue32_UInt8_43_io_deq_bits : _T_3204 ? _Queue32_UInt8_42_io_deq_bits : _T_3203 ? _Queue32_UInt8_41_io_deq_bits : _T_3202 ? _Queue32_UInt8_40_io_deq_bits : _T_3201 ? _Queue32_UInt8_39_io_deq_bits : _T_3200 ? _Queue32_UInt8_38_io_deq_bits : _T_3199 ? _Queue32_UInt8_37_io_deq_bits : _T_3198 ? _Queue32_UInt8_36_io_deq_bits : _T_3197 ? _Queue32_UInt8_35_io_deq_bits : _T_3196 ? _Queue32_UInt8_34_io_deq_bits : _T_3195 ? _Queue32_UInt8_33_io_deq_bits : _T_3194 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_27 = _T_3225 ? _Queue32_UInt8_63_io_deq_valid : _T_3224 ? _Queue32_UInt8_62_io_deq_valid : _T_3223 ? _Queue32_UInt8_61_io_deq_valid : _T_3222 ? _Queue32_UInt8_60_io_deq_valid : _T_3221 ? _Queue32_UInt8_59_io_deq_valid : _T_3220 ? _Queue32_UInt8_58_io_deq_valid : _T_3219 ? _Queue32_UInt8_57_io_deq_valid : _T_3218 ? _Queue32_UInt8_56_io_deq_valid : _T_3217 ? _Queue32_UInt8_55_io_deq_valid : _T_3216 ? _Queue32_UInt8_54_io_deq_valid : _T_3215 ? _Queue32_UInt8_53_io_deq_valid : _T_3214 ? _Queue32_UInt8_52_io_deq_valid : _T_3213 ? _Queue32_UInt8_51_io_deq_valid : _T_3212 ? _Queue32_UInt8_50_io_deq_valid : _T_3211 ? _Queue32_UInt8_49_io_deq_valid : _T_3210 ? _Queue32_UInt8_48_io_deq_valid : _T_3209 ? _Queue32_UInt8_47_io_deq_valid : _T_3208 ? _Queue32_UInt8_46_io_deq_valid : _T_3207 ? _Queue32_UInt8_45_io_deq_valid : _T_3206 ? _Queue32_UInt8_44_io_deq_valid : _T_3205 ? _Queue32_UInt8_43_io_deq_valid : _T_3204 ? _Queue32_UInt8_42_io_deq_valid : _T_3203 ? _Queue32_UInt8_41_io_deq_valid : _T_3202 ? _Queue32_UInt8_40_io_deq_valid : _T_3201 ? _Queue32_UInt8_39_io_deq_valid : _T_3200 ? _Queue32_UInt8_38_io_deq_valid : _T_3199 ? _Queue32_UInt8_37_io_deq_valid : _T_3198 ? _Queue32_UInt8_36_io_deq_valid : _T_3197 ? _Queue32_UInt8_35_io_deq_valid : _T_3196 ? _Queue32_UInt8_34_io_deq_valid : _T_3195 ? _Queue32_UInt8_33_io_deq_valid : _T_3194 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_119 = _remapindex_T_28 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_28 = _GEN_119[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_3226 = remapindex_28 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3227 = remapindex_28 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3228 = remapindex_28 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3229 = remapindex_28 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3230 = remapindex_28 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3231 = remapindex_28 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3232 = remapindex_28 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3233 = remapindex_28 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3234 = remapindex_28 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3235 = remapindex_28 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3236 = remapindex_28 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3237 = remapindex_28 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3238 = remapindex_28 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3239 = remapindex_28 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3240 = remapindex_28 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3241 = remapindex_28 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3242 = remapindex_28 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3243 = remapindex_28 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3244 = remapindex_28 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3245 = remapindex_28 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3246 = remapindex_28 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3247 = remapindex_28 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3248 = remapindex_28 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3249 = remapindex_28 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3250 = remapindex_28 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3251 = remapindex_28 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3252 = remapindex_28 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3253 = remapindex_28 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3254 = remapindex_28 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3255 = remapindex_28 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3256 = remapindex_28 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3257 = remapindex_28 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_28 = _T_3257 ? _Queue32_UInt8_63_io_deq_bits : _T_3256 ? _Queue32_UInt8_62_io_deq_bits : _T_3255 ? _Queue32_UInt8_61_io_deq_bits : _T_3254 ? _Queue32_UInt8_60_io_deq_bits : _T_3253 ? _Queue32_UInt8_59_io_deq_bits : _T_3252 ? _Queue32_UInt8_58_io_deq_bits : _T_3251 ? _Queue32_UInt8_57_io_deq_bits : _T_3250 ? _Queue32_UInt8_56_io_deq_bits : _T_3249 ? _Queue32_UInt8_55_io_deq_bits : _T_3248 ? _Queue32_UInt8_54_io_deq_bits : _T_3247 ? _Queue32_UInt8_53_io_deq_bits : _T_3246 ? _Queue32_UInt8_52_io_deq_bits : _T_3245 ? _Queue32_UInt8_51_io_deq_bits : _T_3244 ? _Queue32_UInt8_50_io_deq_bits : _T_3243 ? _Queue32_UInt8_49_io_deq_bits : _T_3242 ? _Queue32_UInt8_48_io_deq_bits : _T_3241 ? _Queue32_UInt8_47_io_deq_bits : _T_3240 ? _Queue32_UInt8_46_io_deq_bits : _T_3239 ? _Queue32_UInt8_45_io_deq_bits : _T_3238 ? _Queue32_UInt8_44_io_deq_bits : _T_3237 ? _Queue32_UInt8_43_io_deq_bits : _T_3236 ? _Queue32_UInt8_42_io_deq_bits : _T_3235 ? _Queue32_UInt8_41_io_deq_bits : _T_3234 ? _Queue32_UInt8_40_io_deq_bits : _T_3233 ? _Queue32_UInt8_39_io_deq_bits : _T_3232 ? _Queue32_UInt8_38_io_deq_bits : _T_3231 ? _Queue32_UInt8_37_io_deq_bits : _T_3230 ? _Queue32_UInt8_36_io_deq_bits : _T_3229 ? _Queue32_UInt8_35_io_deq_bits : _T_3228 ? _Queue32_UInt8_34_io_deq_bits : _T_3227 ? _Queue32_UInt8_33_io_deq_bits : _T_3226 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_28 = _T_3257 ? _Queue32_UInt8_63_io_deq_valid : _T_3256 ? _Queue32_UInt8_62_io_deq_valid : _T_3255 ? _Queue32_UInt8_61_io_deq_valid : _T_3254 ? _Queue32_UInt8_60_io_deq_valid : _T_3253 ? _Queue32_UInt8_59_io_deq_valid : _T_3252 ? _Queue32_UInt8_58_io_deq_valid : _T_3251 ? _Queue32_UInt8_57_io_deq_valid : _T_3250 ? _Queue32_UInt8_56_io_deq_valid : _T_3249 ? _Queue32_UInt8_55_io_deq_valid : _T_3248 ? _Queue32_UInt8_54_io_deq_valid : _T_3247 ? _Queue32_UInt8_53_io_deq_valid : _T_3246 ? _Queue32_UInt8_52_io_deq_valid : _T_3245 ? _Queue32_UInt8_51_io_deq_valid : _T_3244 ? _Queue32_UInt8_50_io_deq_valid : _T_3243 ? _Queue32_UInt8_49_io_deq_valid : _T_3242 ? _Queue32_UInt8_48_io_deq_valid : _T_3241 ? _Queue32_UInt8_47_io_deq_valid : _T_3240 ? _Queue32_UInt8_46_io_deq_valid : _T_3239 ? _Queue32_UInt8_45_io_deq_valid : _T_3238 ? _Queue32_UInt8_44_io_deq_valid : _T_3237 ? _Queue32_UInt8_43_io_deq_valid : _T_3236 ? _Queue32_UInt8_42_io_deq_valid : _T_3235 ? _Queue32_UInt8_41_io_deq_valid : _T_3234 ? _Queue32_UInt8_40_io_deq_valid : _T_3233 ? _Queue32_UInt8_39_io_deq_valid : _T_3232 ? _Queue32_UInt8_38_io_deq_valid : _T_3231 ? _Queue32_UInt8_37_io_deq_valid : _T_3230 ? _Queue32_UInt8_36_io_deq_valid : _T_3229 ? _Queue32_UInt8_35_io_deq_valid : _T_3228 ? _Queue32_UInt8_34_io_deq_valid : _T_3227 ? _Queue32_UInt8_33_io_deq_valid : _T_3226 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_120 = _remapindex_T_29 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_29 = _GEN_120[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_3258 = remapindex_29 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3259 = remapindex_29 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3260 = remapindex_29 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3261 = remapindex_29 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3262 = remapindex_29 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3263 = remapindex_29 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3264 = remapindex_29 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3265 = remapindex_29 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3266 = remapindex_29 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3267 = remapindex_29 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3268 = remapindex_29 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3269 = remapindex_29 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3270 = remapindex_29 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3271 = remapindex_29 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3272 = remapindex_29 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3273 = remapindex_29 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3274 = remapindex_29 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3275 = remapindex_29 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3276 = remapindex_29 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3277 = remapindex_29 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3278 = remapindex_29 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3279 = remapindex_29 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3280 = remapindex_29 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3281 = remapindex_29 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3282 = remapindex_29 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3283 = remapindex_29 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3284 = remapindex_29 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3285 = remapindex_29 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3286 = remapindex_29 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3287 = remapindex_29 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3288 = remapindex_29 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3289 = remapindex_29 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_29 = _T_3289 ? _Queue32_UInt8_63_io_deq_bits : _T_3288 ? _Queue32_UInt8_62_io_deq_bits : _T_3287 ? _Queue32_UInt8_61_io_deq_bits : _T_3286 ? _Queue32_UInt8_60_io_deq_bits : _T_3285 ? _Queue32_UInt8_59_io_deq_bits : _T_3284 ? _Queue32_UInt8_58_io_deq_bits : _T_3283 ? _Queue32_UInt8_57_io_deq_bits : _T_3282 ? _Queue32_UInt8_56_io_deq_bits : _T_3281 ? _Queue32_UInt8_55_io_deq_bits : _T_3280 ? _Queue32_UInt8_54_io_deq_bits : _T_3279 ? _Queue32_UInt8_53_io_deq_bits : _T_3278 ? _Queue32_UInt8_52_io_deq_bits : _T_3277 ? _Queue32_UInt8_51_io_deq_bits : _T_3276 ? _Queue32_UInt8_50_io_deq_bits : _T_3275 ? _Queue32_UInt8_49_io_deq_bits : _T_3274 ? _Queue32_UInt8_48_io_deq_bits : _T_3273 ? _Queue32_UInt8_47_io_deq_bits : _T_3272 ? _Queue32_UInt8_46_io_deq_bits : _T_3271 ? _Queue32_UInt8_45_io_deq_bits : _T_3270 ? _Queue32_UInt8_44_io_deq_bits : _T_3269 ? _Queue32_UInt8_43_io_deq_bits : _T_3268 ? _Queue32_UInt8_42_io_deq_bits : _T_3267 ? _Queue32_UInt8_41_io_deq_bits : _T_3266 ? _Queue32_UInt8_40_io_deq_bits : _T_3265 ? _Queue32_UInt8_39_io_deq_bits : _T_3264 ? _Queue32_UInt8_38_io_deq_bits : _T_3263 ? _Queue32_UInt8_37_io_deq_bits : _T_3262 ? _Queue32_UInt8_36_io_deq_bits : _T_3261 ? _Queue32_UInt8_35_io_deq_bits : _T_3260 ? _Queue32_UInt8_34_io_deq_bits : _T_3259 ? _Queue32_UInt8_33_io_deq_bits : _T_3258 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_29 = _T_3289 ? _Queue32_UInt8_63_io_deq_valid : _T_3288 ? _Queue32_UInt8_62_io_deq_valid : _T_3287 ? _Queue32_UInt8_61_io_deq_valid : _T_3286 ? _Queue32_UInt8_60_io_deq_valid : _T_3285 ? _Queue32_UInt8_59_io_deq_valid : _T_3284 ? _Queue32_UInt8_58_io_deq_valid : _T_3283 ? _Queue32_UInt8_57_io_deq_valid : _T_3282 ? _Queue32_UInt8_56_io_deq_valid : _T_3281 ? _Queue32_UInt8_55_io_deq_valid : _T_3280 ? _Queue32_UInt8_54_io_deq_valid : _T_3279 ? _Queue32_UInt8_53_io_deq_valid : _T_3278 ? _Queue32_UInt8_52_io_deq_valid : _T_3277 ? _Queue32_UInt8_51_io_deq_valid : _T_3276 ? _Queue32_UInt8_50_io_deq_valid : _T_3275 ? _Queue32_UInt8_49_io_deq_valid : _T_3274 ? _Queue32_UInt8_48_io_deq_valid : _T_3273 ? _Queue32_UInt8_47_io_deq_valid : _T_3272 ? _Queue32_UInt8_46_io_deq_valid : _T_3271 ? _Queue32_UInt8_45_io_deq_valid : _T_3270 ? _Queue32_UInt8_44_io_deq_valid : _T_3269 ? _Queue32_UInt8_43_io_deq_valid : _T_3268 ? _Queue32_UInt8_42_io_deq_valid : _T_3267 ? _Queue32_UInt8_41_io_deq_valid : _T_3266 ? _Queue32_UInt8_40_io_deq_valid : _T_3265 ? _Queue32_UInt8_39_io_deq_valid : _T_3264 ? _Queue32_UInt8_38_io_deq_valid : _T_3263 ? _Queue32_UInt8_37_io_deq_valid : _T_3262 ? _Queue32_UInt8_36_io_deq_valid : _T_3261 ? _Queue32_UInt8_35_io_deq_valid : _T_3260 ? _Queue32_UInt8_34_io_deq_valid : _T_3259 ? _Queue32_UInt8_33_io_deq_valid : _T_3258 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_121 = _remapindex_T_30 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_30 = _GEN_121[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_3290 = remapindex_30 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3291 = remapindex_30 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3292 = remapindex_30 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3293 = remapindex_30 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3294 = remapindex_30 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3295 = remapindex_30 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3296 = remapindex_30 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3297 = remapindex_30 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3298 = remapindex_30 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3299 = remapindex_30 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3300 = remapindex_30 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3301 = remapindex_30 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3302 = remapindex_30 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3303 = remapindex_30 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3304 = remapindex_30 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3305 = remapindex_30 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3306 = remapindex_30 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3307 = remapindex_30 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3308 = remapindex_30 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3309 = remapindex_30 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3310 = remapindex_30 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3311 = remapindex_30 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3312 = remapindex_30 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3313 = remapindex_30 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3314 = remapindex_30 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3315 = remapindex_30 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3316 = remapindex_30 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3317 = remapindex_30 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3318 = remapindex_30 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3319 = remapindex_30 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3320 = remapindex_30 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3321 = remapindex_30 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_30 = _T_3321 ? _Queue32_UInt8_63_io_deq_bits : _T_3320 ? _Queue32_UInt8_62_io_deq_bits : _T_3319 ? _Queue32_UInt8_61_io_deq_bits : _T_3318 ? _Queue32_UInt8_60_io_deq_bits : _T_3317 ? _Queue32_UInt8_59_io_deq_bits : _T_3316 ? _Queue32_UInt8_58_io_deq_bits : _T_3315 ? _Queue32_UInt8_57_io_deq_bits : _T_3314 ? _Queue32_UInt8_56_io_deq_bits : _T_3313 ? _Queue32_UInt8_55_io_deq_bits : _T_3312 ? _Queue32_UInt8_54_io_deq_bits : _T_3311 ? _Queue32_UInt8_53_io_deq_bits : _T_3310 ? _Queue32_UInt8_52_io_deq_bits : _T_3309 ? _Queue32_UInt8_51_io_deq_bits : _T_3308 ? _Queue32_UInt8_50_io_deq_bits : _T_3307 ? _Queue32_UInt8_49_io_deq_bits : _T_3306 ? _Queue32_UInt8_48_io_deq_bits : _T_3305 ? _Queue32_UInt8_47_io_deq_bits : _T_3304 ? _Queue32_UInt8_46_io_deq_bits : _T_3303 ? _Queue32_UInt8_45_io_deq_bits : _T_3302 ? _Queue32_UInt8_44_io_deq_bits : _T_3301 ? _Queue32_UInt8_43_io_deq_bits : _T_3300 ? _Queue32_UInt8_42_io_deq_bits : _T_3299 ? _Queue32_UInt8_41_io_deq_bits : _T_3298 ? _Queue32_UInt8_40_io_deq_bits : _T_3297 ? _Queue32_UInt8_39_io_deq_bits : _T_3296 ? _Queue32_UInt8_38_io_deq_bits : _T_3295 ? _Queue32_UInt8_37_io_deq_bits : _T_3294 ? _Queue32_UInt8_36_io_deq_bits : _T_3293 ? _Queue32_UInt8_35_io_deq_bits : _T_3292 ? _Queue32_UInt8_34_io_deq_bits : _T_3291 ? _Queue32_UInt8_33_io_deq_bits : _T_3290 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_30 = _T_3321 ? _Queue32_UInt8_63_io_deq_valid : _T_3320 ? _Queue32_UInt8_62_io_deq_valid : _T_3319 ? _Queue32_UInt8_61_io_deq_valid : _T_3318 ? _Queue32_UInt8_60_io_deq_valid : _T_3317 ? _Queue32_UInt8_59_io_deq_valid : _T_3316 ? _Queue32_UInt8_58_io_deq_valid : _T_3315 ? _Queue32_UInt8_57_io_deq_valid : _T_3314 ? _Queue32_UInt8_56_io_deq_valid : _T_3313 ? _Queue32_UInt8_55_io_deq_valid : _T_3312 ? _Queue32_UInt8_54_io_deq_valid : _T_3311 ? _Queue32_UInt8_53_io_deq_valid : _T_3310 ? _Queue32_UInt8_52_io_deq_valid : _T_3309 ? _Queue32_UInt8_51_io_deq_valid : _T_3308 ? _Queue32_UInt8_50_io_deq_valid : _T_3307 ? _Queue32_UInt8_49_io_deq_valid : _T_3306 ? _Queue32_UInt8_48_io_deq_valid : _T_3305 ? _Queue32_UInt8_47_io_deq_valid : _T_3304 ? _Queue32_UInt8_46_io_deq_valid : _T_3303 ? _Queue32_UInt8_45_io_deq_valid : _T_3302 ? _Queue32_UInt8_44_io_deq_valid : _T_3301 ? _Queue32_UInt8_43_io_deq_valid : _T_3300 ? _Queue32_UInt8_42_io_deq_valid : _T_3299 ? _Queue32_UInt8_41_io_deq_valid : _T_3298 ? _Queue32_UInt8_40_io_deq_valid : _T_3297 ? _Queue32_UInt8_39_io_deq_valid : _T_3296 ? _Queue32_UInt8_38_io_deq_valid : _T_3295 ? _Queue32_UInt8_37_io_deq_valid : _T_3294 ? _Queue32_UInt8_36_io_deq_valid : _T_3293 ? _Queue32_UInt8_35_io_deq_valid : _T_3292 ? _Queue32_UInt8_34_io_deq_valid : _T_3291 ? _Queue32_UInt8_33_io_deq_valid : _T_3290 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[LZ77HashMatcherMemLoader.scala:198:33] wire [6:0] _GEN_122 = _remapindex_T_31 % 7'h20; // @[LZ77HashMatcherMemLoader.scala:198:{33,54}] wire [5:0] remapindex_31 = _GEN_122[5:0]; // @[LZ77HashMatcherMemLoader.scala:198:54] wire _T_3322 = remapindex_31 == 6'h0; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3323 = remapindex_31 == 6'h1; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3324 = remapindex_31 == 6'h2; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3325 = remapindex_31 == 6'h3; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3326 = remapindex_31 == 6'h4; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3327 = remapindex_31 == 6'h5; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3328 = remapindex_31 == 6'h6; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3329 = remapindex_31 == 6'h7; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3330 = remapindex_31 == 6'h8; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3331 = remapindex_31 == 6'h9; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3332 = remapindex_31 == 6'hA; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3333 = remapindex_31 == 6'hB; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3334 = remapindex_31 == 6'hC; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3335 = remapindex_31 == 6'hD; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3336 = remapindex_31 == 6'hE; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3337 = remapindex_31 == 6'hF; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3338 = remapindex_31 == 6'h10; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3339 = remapindex_31 == 6'h11; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3340 = remapindex_31 == 6'h12; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3341 = remapindex_31 == 6'h13; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3342 = remapindex_31 == 6'h14; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3343 = remapindex_31 == 6'h15; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3344 = remapindex_31 == 6'h16; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3345 = remapindex_31 == 6'h17; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3346 = remapindex_31 == 6'h18; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3347 = remapindex_31 == 6'h19; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3348 = remapindex_31 == 6'h1A; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3349 = remapindex_31 == 6'h1B; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3350 = remapindex_31 == 6'h1C; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3351 = remapindex_31 == 6'h1D; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3352 = remapindex_31 == 6'h1E; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] wire _T_3353 = remapindex_31 == 6'h1F; // @[LZ77HashMatcherMemLoader.scala:198:54, :200:17] assign remapVecData_31 = _T_3353 ? _Queue32_UInt8_63_io_deq_bits : _T_3352 ? _Queue32_UInt8_62_io_deq_bits : _T_3351 ? _Queue32_UInt8_61_io_deq_bits : _T_3350 ? _Queue32_UInt8_60_io_deq_bits : _T_3349 ? _Queue32_UInt8_59_io_deq_bits : _T_3348 ? _Queue32_UInt8_58_io_deq_bits : _T_3347 ? _Queue32_UInt8_57_io_deq_bits : _T_3346 ? _Queue32_UInt8_56_io_deq_bits : _T_3345 ? _Queue32_UInt8_55_io_deq_bits : _T_3344 ? _Queue32_UInt8_54_io_deq_bits : _T_3343 ? _Queue32_UInt8_53_io_deq_bits : _T_3342 ? _Queue32_UInt8_52_io_deq_bits : _T_3341 ? _Queue32_UInt8_51_io_deq_bits : _T_3340 ? _Queue32_UInt8_50_io_deq_bits : _T_3339 ? _Queue32_UInt8_49_io_deq_bits : _T_3338 ? _Queue32_UInt8_48_io_deq_bits : _T_3337 ? _Queue32_UInt8_47_io_deq_bits : _T_3336 ? _Queue32_UInt8_46_io_deq_bits : _T_3335 ? _Queue32_UInt8_45_io_deq_bits : _T_3334 ? _Queue32_UInt8_44_io_deq_bits : _T_3333 ? _Queue32_UInt8_43_io_deq_bits : _T_3332 ? _Queue32_UInt8_42_io_deq_bits : _T_3331 ? _Queue32_UInt8_41_io_deq_bits : _T_3330 ? _Queue32_UInt8_40_io_deq_bits : _T_3329 ? _Queue32_UInt8_39_io_deq_bits : _T_3328 ? _Queue32_UInt8_38_io_deq_bits : _T_3327 ? _Queue32_UInt8_37_io_deq_bits : _T_3326 ? _Queue32_UInt8_36_io_deq_bits : _T_3325 ? _Queue32_UInt8_35_io_deq_bits : _T_3324 ? _Queue32_UInt8_34_io_deq_bits : _T_3323 ? _Queue32_UInt8_33_io_deq_bits : _T_3322 ? _Queue32_UInt8_32_io_deq_bits : 8'h0; // @[LZ77HashMatcherMemLoader.scala:113:56, :186:26, :192:27, :200:{17,33}, :201:31] assign remapVecValids_31 = _T_3353 ? _Queue32_UInt8_63_io_deq_valid : _T_3352 ? _Queue32_UInt8_62_io_deq_valid : _T_3351 ? _Queue32_UInt8_61_io_deq_valid : _T_3350 ? _Queue32_UInt8_60_io_deq_valid : _T_3349 ? _Queue32_UInt8_59_io_deq_valid : _T_3348 ? _Queue32_UInt8_58_io_deq_valid : _T_3347 ? _Queue32_UInt8_57_io_deq_valid : _T_3346 ? _Queue32_UInt8_56_io_deq_valid : _T_3345 ? _Queue32_UInt8_55_io_deq_valid : _T_3344 ? _Queue32_UInt8_54_io_deq_valid : _T_3343 ? _Queue32_UInt8_53_io_deq_valid : _T_3342 ? _Queue32_UInt8_52_io_deq_valid : _T_3341 ? _Queue32_UInt8_51_io_deq_valid : _T_3340 ? _Queue32_UInt8_50_io_deq_valid : _T_3339 ? _Queue32_UInt8_49_io_deq_valid : _T_3338 ? _Queue32_UInt8_48_io_deq_valid : _T_3337 ? _Queue32_UInt8_47_io_deq_valid : _T_3336 ? _Queue32_UInt8_46_io_deq_valid : _T_3335 ? _Queue32_UInt8_45_io_deq_valid : _T_3334 ? _Queue32_UInt8_44_io_deq_valid : _T_3333 ? _Queue32_UInt8_43_io_deq_valid : _T_3332 ? _Queue32_UInt8_42_io_deq_valid : _T_3331 ? _Queue32_UInt8_41_io_deq_valid : _T_3330 ? _Queue32_UInt8_40_io_deq_valid : _T_3329 ? _Queue32_UInt8_39_io_deq_valid : _T_3328 ? _Queue32_UInt8_38_io_deq_valid : _T_3327 ? _Queue32_UInt8_37_io_deq_valid : _T_3326 ? _Queue32_UInt8_36_io_deq_valid : _T_3325 ? _Queue32_UInt8_35_io_deq_valid : _T_3324 ? _Queue32_UInt8_34_io_deq_valid : _T_3323 ? _Queue32_UInt8_33_io_deq_valid : _T_3322 & _Queue32_UInt8_32_io_deq_valid; // @[LZ77HashMatcherMemLoader.scala:113:56, :187:28, :193:29, :200:{17,33}, :202:33] wire [15:0] io_consumer_output_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [15:0] io_consumer_output_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [31:0] io_consumer_output_data_lo_lo_lo = {io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [15:0] io_consumer_output_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [15:0] io_consumer_output_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [31:0] io_consumer_output_data_lo_lo_hi = {io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [63:0] io_consumer_output_data_lo_lo = {io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [15:0] io_consumer_output_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [15:0] io_consumer_output_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [31:0] io_consumer_output_data_lo_hi_lo = {io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [15:0] io_consumer_output_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [15:0] io_consumer_output_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [31:0] io_consumer_output_data_lo_hi_hi = {io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [63:0] io_consumer_output_data_lo_hi = {io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [127:0] io_consumer_output_data_lo = {io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [15:0] io_consumer_output_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [15:0] io_consumer_output_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [31:0] io_consumer_output_data_hi_lo_lo = {io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [15:0] io_consumer_output_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [15:0] io_consumer_output_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [31:0] io_consumer_output_data_hi_lo_hi = {io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [63:0] io_consumer_output_data_hi_lo = {io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [15:0] io_consumer_output_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [15:0] io_consumer_output_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [31:0] io_consumer_output_data_hi_hi_lo = {io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [15:0] io_consumer_output_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [15:0] io_consumer_output_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[LZ77HashMatcherMemLoader.scala:186:26, :207:33] wire [31:0] io_consumer_output_data_hi_hi_hi = {io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [63:0] io_consumer_output_data_hi_hi = {io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] wire [127:0] io_consumer_output_data_hi = {io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] assign _io_consumer_output_data_T = {io_consumer_output_data_hi, io_consumer_output_data_lo}; // @[LZ77HashMatcherMemLoader.scala:207:33] assign io_consumer_output_data_0 = _io_consumer_output_data_T; // @[LZ77HashMatcherMemLoader.scala:17:7, :207:33] wire [64:0] _GEN_123 = {1'h0, len_already_consumed}; // @[LZ77HashMatcherMemLoader.scala:184:37, :210:40] wire [64:0] _GEN_124 = _GEN_123 + {59'h0, io_consumer_user_consumed_bytes_0}; // @[LZ77HashMatcherMemLoader.scala:17:7, :210:40] wire [64:0] _buf_last_T; // @[LZ77HashMatcherMemLoader.scala:210:40] assign _buf_last_T = _GEN_124; // @[LZ77HashMatcherMemLoader.scala:210:40] wire [64:0] _len_already_consumed_T; // @[LZ77HashMatcherMemLoader.scala:251:52] assign _len_already_consumed_T = _GEN_124; // @[LZ77HashMatcherMemLoader.scala:210:40, :251:52] wire [63:0] _buf_last_T_1 = _buf_last_T[63:0]; // @[LZ77HashMatcherMemLoader.scala:210:40] wire buf_last = _buf_last_T_1 == _buf_info_queue_io_deq_bits_len_bytes; // @[LZ77HashMatcherMemLoader.scala:31:30, :210:{40,75}] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[LZ77HashMatcherMemLoader.scala:187:28, :211:60] wire [64:0] _unconsumed_bytes_so_far_T = {1'h0, _buf_info_queue_io_deq_bits_len_bytes} - _GEN_123; // @[LZ77HashMatcherMemLoader.scala:31:30, :210:40, :212:70] wire [63:0] unconsumed_bytes_so_far = _unconsumed_bytes_so_far_T[63:0]; // @[LZ77HashMatcherMemLoader.scala:212:70] wire _enough_data_T = \|(unconsumed_bytes_so_far[63:5]); // @[LZ77HashMatcherMemLoader.scala:212:70, :214:49] wire _enough_data_T_1 = count_valids == 32'h20; // @[LZ77HashMatcherMemLoader.scala:211:60, :215:38] wire _enough_data_T_2 = {32'h0, count_valids} >= unconsumed_bytes_so_far; // @[LZ77HashMatcherMemLoader.scala:211:60, :212:70, :216:38] wire enough_data = _enough_data_T ? _enough_data_T_1 : _enough_data_T_2; // @[LZ77HashMatcherMemLoader.scala:214:{24,49}, :215:38, :216:38] wire _io_consumer_available_output_bytes_T = \|(unconsumed_bytes_so_far[63:5]); // @[LZ77HashMatcherMemLoader.scala:212:70, :214:49, :218:69] wire [63:0] _io_consumer_available_output_bytes_T_1 = _io_consumer_available_output_bytes_T ? 64'h20 : unconsumed_bytes_so_far; // @[LZ77HashMatcherMemLoader.scala:212:70, :218:{44,69}] assign io_consumer_available_output_bytes_0 = _io_consumer_available_output_bytes_T_1[5:0]; // @[LZ77HashMatcherMemLoader.scala:17:7, :218:{38,44}] assign _io_consumer_output_last_chunk_T = unconsumed_bytes_so_far < 64'h21; // @[LZ77HashMatcherMemLoader.scala:212:70, :222:61] assign io_consumer_output_last_chunk_0 = _io_consumer_output_last_chunk_T; // @[LZ77HashMatcherMemLoader.scala:17:7, :222:61] wire _T_3362 = io_consumer_output_ready_0 & _buf_info_queue_io_deq_valid; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_3362; // @[Misc.scala:29:18] reg [63:0] loginfo_cycles_44; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_88 = {1'h0, loginfo_cycles_44} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_89 = _loginfo_cycles_T_88[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_119 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3	module MacUnit_119( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_350 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_94 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c	module PE_350( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_94 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_7 : input clock : Clock input reset : Reset output io : { flip inR : { bits : UInt<32>}, flip inD : { bits : UInt<32>}, outL : { bits : UInt<32>}, outU : { bits : UInt<32>}, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : { bits : UInt<32>}, clock when io.en : connect reg.bits, _reg_T_1.bits connect io.outU, reg connect io.outL, reg	module PE_7( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [31:0] io_inR_bits, // @[Transposer.scala:101:16] input [31:0] io_inD_bits, // @[Transposer.scala:101:16] output [31:0] io_outL_bits, // @[Transposer.scala:101:16] output [31:0] io_outU_bits, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [31:0] io_inR_bits_0 = io_inR_bits; // @[Transposer.scala:100:9] wire [31:0] io_inD_bits_0 = io_inD_bits; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [31:0] io_outL_bits_0; // @[Transposer.scala:100:9] wire [31:0] io_outU_bits_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [31:0] _reg_T_1_bits = _reg_T ? io_inR_bits_0 : io_inD_bits_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [31:0] reg_bits; // @[Transposer.scala:110:24] assign io_outL_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] assign io_outU_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_bits <= _reg_T_1_bits; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL_bits = io_outL_bits_0; // @[Transposer.scala:100:9] assign io_outU_bits = io_outU_bits_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DTLB_14 : input clock : Clock input reset : Reset output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, flip kill : UInt<1>} invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren node vpn = bits(io.req.bits.vaddr, 38, 12) node memIdx = bits(vpn, 1, 0) reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4][4], clock reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[1], clock reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock regreset state : UInt<2>, clock, reset, UInt<2>(0h0) reg r_refill_tag : UInt<27>, clock reg r_superpage_repl_addr : UInt<0>, clock reg r_sectored_repl_addr : UInt<2>, clock reg r_sectored_hit : { valid : UInt<1>, bits : UInt<2>}, clock reg r_superpage_hit : { valid : UInt<1>, bits : UInt<0>}, clock reg r_vstage1_en : UInt<1>, clock reg r_stage2_en : UInt<1>, clock reg r_need_gpa : UInt<1>, clock reg r_gpa_valid : UInt<1>, clock reg r_gpa : UInt<39>, clock reg r_gpa_vpn : UInt<27>, clock reg r_gpa_is_pte : UInt<1>, clock node priv_v = and(UInt<1>(0h0), io.req.bits.v) node priv_s = bits(io.req.bits.prv, 0, 0) node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1)) node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) node _stage1_en_T = bits(satp.mode, 3, 3) node stage1_en = and(UInt<1>(0h1), _stage1_en_T) node _vstage1_en_T = and(UInt<1>(0h0), priv_v) node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3) node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1) node _stage2_en_T = and(UInt<1>(0h0), priv_v) node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3) node stage2_en = and(_stage2_en_T, _stage2_en_T_1) node _vm_enabled_T = or(stage1_en, stage2_en) node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm) node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2) regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0) node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1) node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T) node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0)) node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2) node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0) node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid) node _invalidate_refill_T = eq(state, UInt<2>(0h1)) node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3)) node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1) node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid) node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1)) wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _mpu_ppn_WIRE_1 : UInt<42> connect _mpu_ppn_WIRE_1, special_entry.data[0] node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0) connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1 node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1) connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2 node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2) connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3 node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3) connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4 node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4) connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5 node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5) connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6 node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6) connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7 node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7) connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8 node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8) connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9 node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9) connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10 node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10) connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11 node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11) connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12 node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12) connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13 node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13) connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14 node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14) connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15 node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15) connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16 node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16) connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17 node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17) connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18 node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18) connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19 node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19) connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20 node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20) connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21 node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21) connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22 node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22) connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23 inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData_112 connect mpu_ppn_barrier.clock, clock connect mpu_ppn_barrier.reset, reset connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2 connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18) node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1)) node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0)) node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0)) node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9) node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26) node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2)) node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0)) node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0)) node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn) node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0) node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30) node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12) node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32) node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33) node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0) node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T) node _mpu_priv_T = or(do_refill, io.req.bits.passthrough) node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T) node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv) node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2) inst pmp of PMPChecker_s3_14 connect pmp.clock, clock connect pmp.reset, reset connect pmp.io.addr, mpu_physaddr connect pmp.io.size, io.req.bits.size connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l connect pmp.io.prv, mpu_priv inst pma of PMAChecker_14 connect pma.clock, clock connect pma.reset, reset connect pma.io.paddr, mpu_physaddr node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1)) node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_1 = cvt(_homogeneous_T) node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000))) node _homogeneous_T_3 = asSInt(_homogeneous_T_2) node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0))) node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_6 = cvt(_homogeneous_T_5) node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000))) node _homogeneous_T_8 = asSInt(_homogeneous_T_7) node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0))) node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_11 = cvt(_homogeneous_T_10) node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000))) node _homogeneous_T_13 = asSInt(_homogeneous_T_12) node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0))) node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000)) node _homogeneous_T_16 = cvt(_homogeneous_T_15) node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000))) node _homogeneous_T_18 = asSInt(_homogeneous_T_17) node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0))) node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000)) node _homogeneous_T_21 = cvt(_homogeneous_T_20) node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000))) node _homogeneous_T_23 = asSInt(_homogeneous_T_22) node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0))) node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000)) node _homogeneous_T_26 = cvt(_homogeneous_T_25) node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000))) node _homogeneous_T_28 = asSInt(_homogeneous_T_27) node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0))) node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_31 = cvt(_homogeneous_T_30) node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000))) node _homogeneous_T_33 = asSInt(_homogeneous_T_32) node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0))) node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000)) node _homogeneous_T_36 = cvt(_homogeneous_T_35) node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000))) node _homogeneous_T_38 = asSInt(_homogeneous_T_37) node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0))) node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000)) node _homogeneous_T_41 = cvt(_homogeneous_T_40) node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000))) node _homogeneous_T_43 = asSInt(_homogeneous_T_42) node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0))) node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_46 = cvt(_homogeneous_T_45) node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000))) node _homogeneous_T_48 = asSInt(_homogeneous_T_47) node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0))) node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4) node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9) node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14) node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19) node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24) node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29) node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34) node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39) node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44) node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49) node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_61 = cvt(_homogeneous_T_60) node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_63 = asSInt(_homogeneous_T_62) node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0))) node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64) node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0)) node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0)) node _homogeneous_T_68 = cvt(_homogeneous_T_67) node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_70 = asSInt(_homogeneous_T_69) node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0))) node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000)) node _homogeneous_T_73 = cvt(_homogeneous_T_72) node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000))) node _homogeneous_T_75 = asSInt(_homogeneous_T_74) node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0))) node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_78 = cvt(_homogeneous_T_77) node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_80 = asSInt(_homogeneous_T_79) node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0))) node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_83 = cvt(_homogeneous_T_82) node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000))) node _homogeneous_T_85 = asSInt(_homogeneous_T_84) node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0))) node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_88 = cvt(_homogeneous_T_87) node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000))) node _homogeneous_T_90 = asSInt(_homogeneous_T_89) node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0))) node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71) node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76) node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81) node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86) node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91) node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000)) node _homogeneous_T_98 = cvt(_homogeneous_T_97) node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000))) node _homogeneous_T_100 = asSInt(_homogeneous_T_99) node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0))) node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000)) node _homogeneous_T_103 = cvt(_homogeneous_T_102) node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000))) node _homogeneous_T_105 = asSInt(_homogeneous_T_104) node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0))) node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101) node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106) node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_110 = cvt(_homogeneous_T_109) node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_112 = asSInt(_homogeneous_T_111) node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0))) node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113) node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0)) node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000)) node _homogeneous_T_117 = cvt(_homogeneous_T_116) node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000))) node _homogeneous_T_119 = asSInt(_homogeneous_T_118) node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0))) node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120) node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0)) node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3)) node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0)) node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1) node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000))) node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3) node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0))) node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5) node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T) node prot_r = and(_prot_r_T_1, pmp.io.r) node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T) node prot_w = and(_prot_w_T_1, pmp.io.w) node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0)) node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T) node prot_x = and(_prot_x_T_1, pmp.io.x) node _sector_hits_T = xor(sectored_entries[memIdx][0].tag_vpn, vpn) node _sector_hits_T_1 = shr(_sector_hits_T, 0) node _sector_hits_T_2 = eq(_sector_hits_T_1, UInt<1>(0h0)) node _sector_hits_T_3 = eq(sectored_entries[memIdx][0].tag_v, priv_v) node _sector_hits_T_4 = and(_sector_hits_T_2, _sector_hits_T_3) node sector_hits_0 = and(sectored_entries[memIdx][0].valid[0], _sector_hits_T_4) node _sector_hits_T_5 = xor(sectored_entries[memIdx][1].tag_vpn, vpn) node _sector_hits_T_6 = shr(_sector_hits_T_5, 0) node _sector_hits_T_7 = eq(_sector_hits_T_6, UInt<1>(0h0)) node _sector_hits_T_8 = eq(sectored_entries[memIdx][1].tag_v, priv_v) node _sector_hits_T_9 = and(_sector_hits_T_7, _sector_hits_T_8) node sector_hits_1 = and(sectored_entries[memIdx][1].valid[0], _sector_hits_T_9) node _sector_hits_T_10 = xor(sectored_entries[memIdx][2].tag_vpn, vpn) node _sector_hits_T_11 = shr(_sector_hits_T_10, 0) node _sector_hits_T_12 = eq(_sector_hits_T_11, UInt<1>(0h0)) node _sector_hits_T_13 = eq(sectored_entries[memIdx][2].tag_v, priv_v) node _sector_hits_T_14 = and(_sector_hits_T_12, _sector_hits_T_13) node sector_hits_2 = and(sectored_entries[memIdx][2].valid[0], _sector_hits_T_14) node _sector_hits_T_15 = xor(sectored_entries[memIdx][3].tag_vpn, vpn) node _sector_hits_T_16 = shr(_sector_hits_T_15, 0) node _sector_hits_T_17 = eq(_sector_hits_T_16, UInt<1>(0h0)) node _sector_hits_T_18 = eq(sectored_entries[memIdx][3].tag_v, priv_v) node _sector_hits_T_19 = and(_sector_hits_T_17, _sector_hits_T_18) node sector_hits_3 = and(sectored_entries[memIdx][3].valid[0], _sector_hits_T_19) node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T) node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0)) node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18) node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0)) node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2) node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3) node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0)) node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9) node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0)) node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7) node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8) node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1)) node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn) node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0) node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0)) node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12) node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13) node _hitsVec_T = xor(sectored_entries[memIdx][0].tag_vpn, vpn) node _hitsVec_T_1 = shr(_hitsVec_T, 0) node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0)) node _hitsVec_T_3 = eq(sectored_entries[memIdx][0].tag_v, priv_v) node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3) node _hitsVec_T_5 = and(sectored_entries[memIdx][0].valid[0], _hitsVec_T_4) node hitsVec_0 = and(vm_enabled, _hitsVec_T_5) node _hitsVec_T_6 = xor(sectored_entries[memIdx][1].tag_vpn, vpn) node _hitsVec_T_7 = shr(_hitsVec_T_6, 0) node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0)) node _hitsVec_T_9 = eq(sectored_entries[memIdx][1].tag_v, priv_v) node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9) node _hitsVec_T_11 = and(sectored_entries[memIdx][1].valid[0], _hitsVec_T_10) node hitsVec_1 = and(vm_enabled, _hitsVec_T_11) node _hitsVec_T_12 = xor(sectored_entries[memIdx][2].tag_vpn, vpn) node _hitsVec_T_13 = shr(_hitsVec_T_12, 0) node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0)) node _hitsVec_T_15 = eq(sectored_entries[memIdx][2].tag_v, priv_v) node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15) node _hitsVec_T_17 = and(sectored_entries[memIdx][2].valid[0], _hitsVec_T_16) node hitsVec_2 = and(vm_enabled, _hitsVec_T_17) node _hitsVec_T_18 = xor(sectored_entries[memIdx][3].tag_vpn, vpn) node _hitsVec_T_19 = shr(_hitsVec_T_18, 0) node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0)) node _hitsVec_T_21 = eq(sectored_entries[memIdx][3].tag_v, priv_v) node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21) node _hitsVec_T_23 = and(sectored_entries[memIdx][3].valid[0], _hitsVec_T_22) node hitsVec_3 = and(vm_enabled, _hitsVec_T_23) node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v) node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T) node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0)) node _hitsVec_T_24 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_25 = bits(_hitsVec_T_24, 26, 18) node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0)) node _hitsVec_T_27 = or(hitsVec_ignore, _hitsVec_T_26) node _hitsVec_T_28 = and(hitsVec_tagMatch, _hitsVec_T_27) node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0)) node _hitsVec_T_29 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_30 = bits(_hitsVec_T_29, 17, 9) node _hitsVec_T_31 = eq(_hitsVec_T_30, UInt<1>(0h0)) node _hitsVec_T_32 = or(hitsVec_ignore_1, _hitsVec_T_31) node _hitsVec_T_33 = and(_hitsVec_T_28, _hitsVec_T_32) node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1)) node _hitsVec_T_34 = xor(superpage_entries[0].tag_vpn, vpn) node _hitsVec_T_35 = bits(_hitsVec_T_34, 8, 0) node _hitsVec_T_36 = eq(_hitsVec_T_35, UInt<1>(0h0)) node _hitsVec_T_37 = or(hitsVec_ignore_2, _hitsVec_T_36) node _hitsVec_T_38 = and(_hitsVec_T_33, _hitsVec_T_37) node hitsVec_4 = and(vm_enabled, _hitsVec_T_38) node _hitsVec_tagMatch_T_1 = eq(special_entry.tag_v, priv_v) node hitsVec_tagMatch_1 = and(special_entry.valid[0], _hitsVec_tagMatch_T_1) node _hitsVec_ignore_T_3 = lt(special_entry.level, UInt<1>(0h0)) node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0)) node _hitsVec_T_39 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_40 = bits(_hitsVec_T_39, 26, 18) node _hitsVec_T_41 = eq(_hitsVec_T_40, UInt<1>(0h0)) node _hitsVec_T_42 = or(hitsVec_ignore_3, _hitsVec_T_41) node _hitsVec_T_43 = and(hitsVec_tagMatch_1, _hitsVec_T_42) node _hitsVec_ignore_T_4 = lt(special_entry.level, UInt<1>(0h1)) node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0)) node _hitsVec_T_44 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_45 = bits(_hitsVec_T_44, 17, 9) node _hitsVec_T_46 = eq(_hitsVec_T_45, UInt<1>(0h0)) node _hitsVec_T_47 = or(hitsVec_ignore_4, _hitsVec_T_46) node _hitsVec_T_48 = and(_hitsVec_T_43, _hitsVec_T_47) node _hitsVec_ignore_T_5 = lt(special_entry.level, UInt<2>(0h2)) node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h0)) node _hitsVec_T_49 = xor(special_entry.tag_vpn, vpn) node _hitsVec_T_50 = bits(_hitsVec_T_49, 8, 0) node _hitsVec_T_51 = eq(_hitsVec_T_50, UInt<1>(0h0)) node _hitsVec_T_52 = or(hitsVec_ignore_5, _hitsVec_T_51) node _hitsVec_T_53 = and(_hitsVec_T_48, _hitsVec_T_52) node hitsVec_5 = and(vm_enabled, _hitsVec_T_53) node real_hits_lo_hi = cat(hitsVec_2, hitsVec_1) node real_hits_lo = cat(real_hits_lo_hi, hitsVec_0) node real_hits_hi_hi = cat(hitsVec_5, hitsVec_4) node real_hits_hi = cat(real_hits_hi_hi, hitsVec_3) node real_hits = cat(real_hits_hi, real_hits_lo) node _hits_T = eq(vm_enabled, UInt<1>(0h0)) node hits = cat(_hits_T, real_hits) when do_refill : node refill_v = or(r_vstage1_en, r_stage2_en) wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} connect newEntry.ppn, io.ptw.resp.bits.pte.ppn connect newEntry.c, cacheable connect newEntry.u, io.ptw.resp.bits.pte.u node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v) connect newEntry.g, _newEntry_g_T connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw connect newEntry.ae_final, io.ptw.resp.bits.ae_final node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte) node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en) connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1 connect newEntry.pf, io.ptw.resp.bits.pf connect newEntry.gf, io.ptw.resp.bits.gf connect newEntry.hr, io.ptw.resp.bits.hr connect newEntry.hw, io.ptw.resp.bits.hw connect newEntry.hx, io.ptw.resp.bits.hx node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T) node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1) node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2) node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r) connect newEntry.sr, _newEntry_sr_T_5 node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T) node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1) node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2) node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w) node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d) connect newEntry.sw, _newEntry_sw_T_6 node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0)) node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T) node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1) node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2) node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a) node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x) connect newEntry.sx, _newEntry_sx_T_5 connect newEntry.pr, prot_r connect newEntry.pw, prot_w connect newEntry.px, prot_x connect newEntry.ppp, pma.io.resp.pp connect newEntry.pal, pma.io.resp.al connect newEntry.paa, pma.io.resp.aa connect newEntry.eff, pma.io.resp.eff connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) when _T_1 : connect special_entry.tag_vpn, r_refill_tag connect special_entry.tag_v, refill_v node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0) connect special_entry.level, _special_entry_level_T connect special_entry.valid[0], UInt<1>(0h1) node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff) node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo) node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp) node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw) node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo) node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo) node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw) node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw) node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo) node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g) node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo) node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo) node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo) connect special_entry.data[0], _special_entry_data_0_T else : node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2)) when _T_2 : node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0)) node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr) node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0)) when _T_3 : connect superpage_entries[0].tag_vpn, r_refill_tag connect superpage_entries[0].tag_v, refill_v node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0) connect superpage_entries[0].level, _superpage_entries_0_level_T connect superpage_entries[0].valid[0], UInt<1>(0h1) node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo) node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo) node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo) node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo) node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo) node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo) node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo) connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T when invalidate_refill : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node r_memIdx = bits(r_refill_tag, 1, 0) node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) node _T_4 = eq(waddr_1, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_5 : connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][0].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][0].tag_v, refill_v connect sectored_entries[r_memIdx][0].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h1) node sectored_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_0_data_0_lo_lo_hi = cat(sectored_entries_0_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_0_data_0_lo_lo = cat(sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo) node sectored_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_0_data_0_lo_hi_lo = cat(sectored_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_0_data_0_lo_hi_hi = cat(sectored_entries_0_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_0_data_0_lo_hi = cat(sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo) node sectored_entries_0_data_0_lo = cat(sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo) node sectored_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_0_data_0_hi_lo_lo = cat(sectored_entries_0_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_0_data_0_hi_lo_hi = cat(sectored_entries_0_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_0_data_0_hi_lo = cat(sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo) node sectored_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_0_data_0_hi_hi_lo = cat(sectored_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_0_data_0_hi_hi_hi = cat(sectored_entries_0_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_0_data_0_hi_hi = cat(sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo) node sectored_entries_0_data_0_hi = cat(sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo) node _sectored_entries_0_data_0_T = cat(sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo) connect sectored_entries[r_memIdx][0].data[0], _sectored_entries_0_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][0].valid[0], UInt<1>(0h0) node _T_6 = eq(waddr_1, UInt<1>(0h1)) when _T_6 : node _T_7 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_7 : connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][1].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][1].tag_v, refill_v connect sectored_entries[r_memIdx][1].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h1) node sectored_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_1_data_0_lo_lo_hi = cat(sectored_entries_1_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_1_data_0_lo_lo = cat(sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo) node sectored_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_1_data_0_lo_hi_lo = cat(sectored_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_1_data_0_lo_hi_hi = cat(sectored_entries_1_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_1_data_0_lo_hi = cat(sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo) node sectored_entries_1_data_0_lo = cat(sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo) node sectored_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_1_data_0_hi_lo_lo = cat(sectored_entries_1_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_1_data_0_hi_lo_hi = cat(sectored_entries_1_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_1_data_0_hi_lo = cat(sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo) node sectored_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_1_data_0_hi_hi_lo = cat(sectored_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_1_data_0_hi_hi_hi = cat(sectored_entries_1_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_1_data_0_hi_hi = cat(sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo) node sectored_entries_1_data_0_hi = cat(sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo) node _sectored_entries_1_data_0_T = cat(sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo) connect sectored_entries[r_memIdx][1].data[0], _sectored_entries_1_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][1].valid[0], UInt<1>(0h0) node _T_8 = eq(waddr_1, UInt<2>(0h2)) when _T_8 : node _T_9 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_9 : connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][2].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][2].tag_v, refill_v connect sectored_entries[r_memIdx][2].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h1) node sectored_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_2_data_0_lo_lo_hi = cat(sectored_entries_2_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_2_data_0_lo_lo = cat(sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo) node sectored_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_2_data_0_lo_hi_lo = cat(sectored_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_2_data_0_lo_hi_hi = cat(sectored_entries_2_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_2_data_0_lo_hi = cat(sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo) node sectored_entries_2_data_0_lo = cat(sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo) node sectored_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_2_data_0_hi_lo_lo = cat(sectored_entries_2_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_2_data_0_hi_lo_hi = cat(sectored_entries_2_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_2_data_0_hi_lo = cat(sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo) node sectored_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_2_data_0_hi_hi_lo = cat(sectored_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_2_data_0_hi_hi_hi = cat(sectored_entries_2_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_2_data_0_hi_hi = cat(sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo) node sectored_entries_2_data_0_hi = cat(sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo) node _sectored_entries_2_data_0_T = cat(sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo) connect sectored_entries[r_memIdx][2].data[0], _sectored_entries_2_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][2].valid[0], UInt<1>(0h0) node _T_10 = eq(waddr_1, UInt<2>(0h3)) when _T_10 : node _T_11 = eq(r_sectored_hit.valid, UInt<1>(0h0)) when _T_11 : connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h0) connect sectored_entries[r_memIdx][3].tag_vpn, r_refill_tag connect sectored_entries[r_memIdx][3].tag_v, refill_v connect sectored_entries[r_memIdx][3].level, UInt<2>(0h0) connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h1) node sectored_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage) node sectored_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa) node sectored_entries_3_data_0_lo_lo_hi = cat(sectored_entries_3_data_0_lo_lo_hi_hi, newEntry.eff) node sectored_entries_3_data_0_lo_lo = cat(sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo) node sectored_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr) node sectored_entries_3_data_0_lo_hi_lo = cat(sectored_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp) node sectored_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr) node sectored_entries_3_data_0_lo_hi_hi = cat(sectored_entries_3_data_0_lo_hi_hi_hi, newEntry.pw) node sectored_entries_3_data_0_lo_hi = cat(sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo) node sectored_entries_3_data_0_lo = cat(sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo) node sectored_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr) node sectored_entries_3_data_0_hi_lo_lo = cat(sectored_entries_3_data_0_hi_lo_lo_hi, newEntry.hw) node sectored_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf) node sectored_entries_3_data_0_hi_lo_hi = cat(sectored_entries_3_data_0_hi_lo_hi_hi, newEntry.sw) node sectored_entries_3_data_0_hi_lo = cat(sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo) node sectored_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final) node sectored_entries_3_data_0_hi_hi_lo = cat(sectored_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2) node sectored_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u) node sectored_entries_3_data_0_hi_hi_hi = cat(sectored_entries_3_data_0_hi_hi_hi_hi, newEntry.g) node sectored_entries_3_data_0_hi_hi = cat(sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo) node sectored_entries_3_data_0_hi = cat(sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo) node _sectored_entries_3_data_0_T = cat(sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo) connect sectored_entries[r_memIdx][3].data[0], _sectored_entries_3_data_0_T when invalidate_refill : connect sectored_entries[r_memIdx][3].valid[0], UInt<1>(0h0) connect r_gpa_valid, io.ptw.resp.bits.gpa.valid connect r_gpa, io.ptw.resp.bits.gpa.bits connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_1 : UInt<42> connect _entries_WIRE_1, sectored_entries[memIdx][0].data[0] node _entries_T = bits(_entries_WIRE_1, 0, 0) connect _entries_WIRE.fragmented_superpage, _entries_T node _entries_T_1 = bits(_entries_WIRE_1, 1, 1) connect _entries_WIRE.c, _entries_T_1 node _entries_T_2 = bits(_entries_WIRE_1, 2, 2) connect _entries_WIRE.eff, _entries_T_2 node _entries_T_3 = bits(_entries_WIRE_1, 3, 3) connect _entries_WIRE.paa, _entries_T_3 node _entries_T_4 = bits(_entries_WIRE_1, 4, 4) connect _entries_WIRE.pal, _entries_T_4 node _entries_T_5 = bits(_entries_WIRE_1, 5, 5) connect _entries_WIRE.ppp, _entries_T_5 node _entries_T_6 = bits(_entries_WIRE_1, 6, 6) connect _entries_WIRE.pr, _entries_T_6 node _entries_T_7 = bits(_entries_WIRE_1, 7, 7) connect _entries_WIRE.px, _entries_T_7 node _entries_T_8 = bits(_entries_WIRE_1, 8, 8) connect _entries_WIRE.pw, _entries_T_8 node _entries_T_9 = bits(_entries_WIRE_1, 9, 9) connect _entries_WIRE.hr, _entries_T_9 node _entries_T_10 = bits(_entries_WIRE_1, 10, 10) connect _entries_WIRE.hx, _entries_T_10 node _entries_T_11 = bits(_entries_WIRE_1, 11, 11) connect _entries_WIRE.hw, _entries_T_11 node _entries_T_12 = bits(_entries_WIRE_1, 12, 12) connect _entries_WIRE.sr, _entries_T_12 node _entries_T_13 = bits(_entries_WIRE_1, 13, 13) connect _entries_WIRE.sx, _entries_T_13 node _entries_T_14 = bits(_entries_WIRE_1, 14, 14) connect _entries_WIRE.sw, _entries_T_14 node _entries_T_15 = bits(_entries_WIRE_1, 15, 15) connect _entries_WIRE.gf, _entries_T_15 node _entries_T_16 = bits(_entries_WIRE_1, 16, 16) connect _entries_WIRE.pf, _entries_T_16 node _entries_T_17 = bits(_entries_WIRE_1, 17, 17) connect _entries_WIRE.ae_stage2, _entries_T_17 node _entries_T_18 = bits(_entries_WIRE_1, 18, 18) connect _entries_WIRE.ae_final, _entries_T_18 node _entries_T_19 = bits(_entries_WIRE_1, 19, 19) connect _entries_WIRE.ae_ptw, _entries_T_19 node _entries_T_20 = bits(_entries_WIRE_1, 20, 20) connect _entries_WIRE.g, _entries_T_20 node _entries_T_21 = bits(_entries_WIRE_1, 21, 21) connect _entries_WIRE.u, _entries_T_21 node _entries_T_22 = bits(_entries_WIRE_1, 41, 22) connect _entries_WIRE.ppn, _entries_T_22 inst entries_barrier of OptimizationBarrier_TLBEntryData_113 connect entries_barrier.clock, clock connect entries_barrier.reset, reset connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage connect entries_barrier.io.x.c, _entries_WIRE.c connect entries_barrier.io.x.eff, _entries_WIRE.eff connect entries_barrier.io.x.paa, _entries_WIRE.paa connect entries_barrier.io.x.pal, _entries_WIRE.pal connect entries_barrier.io.x.ppp, _entries_WIRE.ppp connect entries_barrier.io.x.pr, _entries_WIRE.pr connect entries_barrier.io.x.px, _entries_WIRE.px connect entries_barrier.io.x.pw, _entries_WIRE.pw connect entries_barrier.io.x.hr, _entries_WIRE.hr connect entries_barrier.io.x.hx, _entries_WIRE.hx connect entries_barrier.io.x.hw, _entries_WIRE.hw connect entries_barrier.io.x.sr, _entries_WIRE.sr connect entries_barrier.io.x.sx, _entries_WIRE.sx connect entries_barrier.io.x.sw, _entries_WIRE.sw connect entries_barrier.io.x.gf, _entries_WIRE.gf connect entries_barrier.io.x.pf, _entries_WIRE.pf connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2 connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw connect entries_barrier.io.x.g, _entries_WIRE.g connect entries_barrier.io.x.u, _entries_WIRE.u connect entries_barrier.io.x.ppn, _entries_WIRE.ppn wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_3 : UInt<42> connect _entries_WIRE_3, sectored_entries[memIdx][1].data[0] node _entries_T_23 = bits(_entries_WIRE_3, 0, 0) connect _entries_WIRE_2.fragmented_superpage, _entries_T_23 node _entries_T_24 = bits(_entries_WIRE_3, 1, 1) connect _entries_WIRE_2.c, _entries_T_24 node _entries_T_25 = bits(_entries_WIRE_3, 2, 2) connect _entries_WIRE_2.eff, _entries_T_25 node _entries_T_26 = bits(_entries_WIRE_3, 3, 3) connect _entries_WIRE_2.paa, _entries_T_26 node _entries_T_27 = bits(_entries_WIRE_3, 4, 4) connect _entries_WIRE_2.pal, _entries_T_27 node _entries_T_28 = bits(_entries_WIRE_3, 5, 5) connect _entries_WIRE_2.ppp, _entries_T_28 node _entries_T_29 = bits(_entries_WIRE_3, 6, 6) connect _entries_WIRE_2.pr, _entries_T_29 node _entries_T_30 = bits(_entries_WIRE_3, 7, 7) connect _entries_WIRE_2.px, _entries_T_30 node _entries_T_31 = bits(_entries_WIRE_3, 8, 8) connect _entries_WIRE_2.pw, _entries_T_31 node _entries_T_32 = bits(_entries_WIRE_3, 9, 9) connect _entries_WIRE_2.hr, _entries_T_32 node _entries_T_33 = bits(_entries_WIRE_3, 10, 10) connect _entries_WIRE_2.hx, _entries_T_33 node _entries_T_34 = bits(_entries_WIRE_3, 11, 11) connect _entries_WIRE_2.hw, _entries_T_34 node _entries_T_35 = bits(_entries_WIRE_3, 12, 12) connect _entries_WIRE_2.sr, _entries_T_35 node _entries_T_36 = bits(_entries_WIRE_3, 13, 13) connect _entries_WIRE_2.sx, _entries_T_36 node _entries_T_37 = bits(_entries_WIRE_3, 14, 14) connect _entries_WIRE_2.sw, _entries_T_37 node _entries_T_38 = bits(_entries_WIRE_3, 15, 15) connect _entries_WIRE_2.gf, _entries_T_38 node _entries_T_39 = bits(_entries_WIRE_3, 16, 16) connect _entries_WIRE_2.pf, _entries_T_39 node _entries_T_40 = bits(_entries_WIRE_3, 17, 17) connect _entries_WIRE_2.ae_stage2, _entries_T_40 node _entries_T_41 = bits(_entries_WIRE_3, 18, 18) connect _entries_WIRE_2.ae_final, _entries_T_41 node _entries_T_42 = bits(_entries_WIRE_3, 19, 19) connect _entries_WIRE_2.ae_ptw, _entries_T_42 node _entries_T_43 = bits(_entries_WIRE_3, 20, 20) connect _entries_WIRE_2.g, _entries_T_43 node _entries_T_44 = bits(_entries_WIRE_3, 21, 21) connect _entries_WIRE_2.u, _entries_T_44 node _entries_T_45 = bits(_entries_WIRE_3, 41, 22) connect _entries_WIRE_2.ppn, _entries_T_45 inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_114 connect entries_barrier_1.clock, clock connect entries_barrier_1.reset, reset connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage connect entries_barrier_1.io.x.c, _entries_WIRE_2.c connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr connect entries_barrier_1.io.x.px, _entries_WIRE_2.px connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2 connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw connect entries_barrier_1.io.x.g, _entries_WIRE_2.g connect entries_barrier_1.io.x.u, _entries_WIRE_2.u connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_5 : UInt<42> connect _entries_WIRE_5, sectored_entries[memIdx][2].data[0] node _entries_T_46 = bits(_entries_WIRE_5, 0, 0) connect _entries_WIRE_4.fragmented_superpage, _entries_T_46 node _entries_T_47 = bits(_entries_WIRE_5, 1, 1) connect _entries_WIRE_4.c, _entries_T_47 node _entries_T_48 = bits(_entries_WIRE_5, 2, 2) connect _entries_WIRE_4.eff, _entries_T_48 node _entries_T_49 = bits(_entries_WIRE_5, 3, 3) connect _entries_WIRE_4.paa, _entries_T_49 node _entries_T_50 = bits(_entries_WIRE_5, 4, 4) connect _entries_WIRE_4.pal, _entries_T_50 node _entries_T_51 = bits(_entries_WIRE_5, 5, 5) connect _entries_WIRE_4.ppp, _entries_T_51 node _entries_T_52 = bits(_entries_WIRE_5, 6, 6) connect _entries_WIRE_4.pr, _entries_T_52 node _entries_T_53 = bits(_entries_WIRE_5, 7, 7) connect _entries_WIRE_4.px, _entries_T_53 node _entries_T_54 = bits(_entries_WIRE_5, 8, 8) connect _entries_WIRE_4.pw, _entries_T_54 node _entries_T_55 = bits(_entries_WIRE_5, 9, 9) connect _entries_WIRE_4.hr, _entries_T_55 node _entries_T_56 = bits(_entries_WIRE_5, 10, 10) connect _entries_WIRE_4.hx, _entries_T_56 node _entries_T_57 = bits(_entries_WIRE_5, 11, 11) connect _entries_WIRE_4.hw, _entries_T_57 node _entries_T_58 = bits(_entries_WIRE_5, 12, 12) connect _entries_WIRE_4.sr, _entries_T_58 node _entries_T_59 = bits(_entries_WIRE_5, 13, 13) connect _entries_WIRE_4.sx, _entries_T_59 node _entries_T_60 = bits(_entries_WIRE_5, 14, 14) connect _entries_WIRE_4.sw, _entries_T_60 node _entries_T_61 = bits(_entries_WIRE_5, 15, 15) connect _entries_WIRE_4.gf, _entries_T_61 node _entries_T_62 = bits(_entries_WIRE_5, 16, 16) connect _entries_WIRE_4.pf, _entries_T_62 node _entries_T_63 = bits(_entries_WIRE_5, 17, 17) connect _entries_WIRE_4.ae_stage2, _entries_T_63 node _entries_T_64 = bits(_entries_WIRE_5, 18, 18) connect _entries_WIRE_4.ae_final, _entries_T_64 node _entries_T_65 = bits(_entries_WIRE_5, 19, 19) connect _entries_WIRE_4.ae_ptw, _entries_T_65 node _entries_T_66 = bits(_entries_WIRE_5, 20, 20) connect _entries_WIRE_4.g, _entries_T_66 node _entries_T_67 = bits(_entries_WIRE_5, 21, 21) connect _entries_WIRE_4.u, _entries_T_67 node _entries_T_68 = bits(_entries_WIRE_5, 41, 22) connect _entries_WIRE_4.ppn, _entries_T_68 inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_115 connect entries_barrier_2.clock, clock connect entries_barrier_2.reset, reset connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage connect entries_barrier_2.io.x.c, _entries_WIRE_4.c connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr connect entries_barrier_2.io.x.px, _entries_WIRE_4.px connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2 connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw connect entries_barrier_2.io.x.g, _entries_WIRE_4.g connect entries_barrier_2.io.x.u, _entries_WIRE_4.u connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_7 : UInt<42> connect _entries_WIRE_7, sectored_entries[memIdx][3].data[0] node _entries_T_69 = bits(_entries_WIRE_7, 0, 0) connect _entries_WIRE_6.fragmented_superpage, _entries_T_69 node _entries_T_70 = bits(_entries_WIRE_7, 1, 1) connect _entries_WIRE_6.c, _entries_T_70 node _entries_T_71 = bits(_entries_WIRE_7, 2, 2) connect _entries_WIRE_6.eff, _entries_T_71 node _entries_T_72 = bits(_entries_WIRE_7, 3, 3) connect _entries_WIRE_6.paa, _entries_T_72 node _entries_T_73 = bits(_entries_WIRE_7, 4, 4) connect _entries_WIRE_6.pal, _entries_T_73 node _entries_T_74 = bits(_entries_WIRE_7, 5, 5) connect _entries_WIRE_6.ppp, _entries_T_74 node _entries_T_75 = bits(_entries_WIRE_7, 6, 6) connect _entries_WIRE_6.pr, _entries_T_75 node _entries_T_76 = bits(_entries_WIRE_7, 7, 7) connect _entries_WIRE_6.px, _entries_T_76 node _entries_T_77 = bits(_entries_WIRE_7, 8, 8) connect _entries_WIRE_6.pw, _entries_T_77 node _entries_T_78 = bits(_entries_WIRE_7, 9, 9) connect _entries_WIRE_6.hr, _entries_T_78 node _entries_T_79 = bits(_entries_WIRE_7, 10, 10) connect _entries_WIRE_6.hx, _entries_T_79 node _entries_T_80 = bits(_entries_WIRE_7, 11, 11) connect _entries_WIRE_6.hw, _entries_T_80 node _entries_T_81 = bits(_entries_WIRE_7, 12, 12) connect _entries_WIRE_6.sr, _entries_T_81 node _entries_T_82 = bits(_entries_WIRE_7, 13, 13) connect _entries_WIRE_6.sx, _entries_T_82 node _entries_T_83 = bits(_entries_WIRE_7, 14, 14) connect _entries_WIRE_6.sw, _entries_T_83 node _entries_T_84 = bits(_entries_WIRE_7, 15, 15) connect _entries_WIRE_6.gf, _entries_T_84 node _entries_T_85 = bits(_entries_WIRE_7, 16, 16) connect _entries_WIRE_6.pf, _entries_T_85 node _entries_T_86 = bits(_entries_WIRE_7, 17, 17) connect _entries_WIRE_6.ae_stage2, _entries_T_86 node _entries_T_87 = bits(_entries_WIRE_7, 18, 18) connect _entries_WIRE_6.ae_final, _entries_T_87 node _entries_T_88 = bits(_entries_WIRE_7, 19, 19) connect _entries_WIRE_6.ae_ptw, _entries_T_88 node _entries_T_89 = bits(_entries_WIRE_7, 20, 20) connect _entries_WIRE_6.g, _entries_T_89 node _entries_T_90 = bits(_entries_WIRE_7, 21, 21) connect _entries_WIRE_6.u, _entries_T_90 node _entries_T_91 = bits(_entries_WIRE_7, 41, 22) connect _entries_WIRE_6.ppn, _entries_T_91 inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_116 connect entries_barrier_3.clock, clock connect entries_barrier_3.reset, reset connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage connect entries_barrier_3.io.x.c, _entries_WIRE_6.c connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr connect entries_barrier_3.io.x.px, _entries_WIRE_6.px connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2 connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw connect entries_barrier_3.io.x.g, _entries_WIRE_6.g connect entries_barrier_3.io.x.u, _entries_WIRE_6.u connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_9 : UInt<42> connect _entries_WIRE_9, superpage_entries[0].data[0] node _entries_T_92 = bits(_entries_WIRE_9, 0, 0) connect _entries_WIRE_8.fragmented_superpage, _entries_T_92 node _entries_T_93 = bits(_entries_WIRE_9, 1, 1) connect _entries_WIRE_8.c, _entries_T_93 node _entries_T_94 = bits(_entries_WIRE_9, 2, 2) connect _entries_WIRE_8.eff, _entries_T_94 node _entries_T_95 = bits(_entries_WIRE_9, 3, 3) connect _entries_WIRE_8.paa, _entries_T_95 node _entries_T_96 = bits(_entries_WIRE_9, 4, 4) connect _entries_WIRE_8.pal, _entries_T_96 node _entries_T_97 = bits(_entries_WIRE_9, 5, 5) connect _entries_WIRE_8.ppp, _entries_T_97 node _entries_T_98 = bits(_entries_WIRE_9, 6, 6) connect _entries_WIRE_8.pr, _entries_T_98 node _entries_T_99 = bits(_entries_WIRE_9, 7, 7) connect _entries_WIRE_8.px, _entries_T_99 node _entries_T_100 = bits(_entries_WIRE_9, 8, 8) connect _entries_WIRE_8.pw, _entries_T_100 node _entries_T_101 = bits(_entries_WIRE_9, 9, 9) connect _entries_WIRE_8.hr, _entries_T_101 node _entries_T_102 = bits(_entries_WIRE_9, 10, 10) connect _entries_WIRE_8.hx, _entries_T_102 node _entries_T_103 = bits(_entries_WIRE_9, 11, 11) connect _entries_WIRE_8.hw, _entries_T_103 node _entries_T_104 = bits(_entries_WIRE_9, 12, 12) connect _entries_WIRE_8.sr, _entries_T_104 node _entries_T_105 = bits(_entries_WIRE_9, 13, 13) connect _entries_WIRE_8.sx, _entries_T_105 node _entries_T_106 = bits(_entries_WIRE_9, 14, 14) connect _entries_WIRE_8.sw, _entries_T_106 node _entries_T_107 = bits(_entries_WIRE_9, 15, 15) connect _entries_WIRE_8.gf, _entries_T_107 node _entries_T_108 = bits(_entries_WIRE_9, 16, 16) connect _entries_WIRE_8.pf, _entries_T_108 node _entries_T_109 = bits(_entries_WIRE_9, 17, 17) connect _entries_WIRE_8.ae_stage2, _entries_T_109 node _entries_T_110 = bits(_entries_WIRE_9, 18, 18) connect _entries_WIRE_8.ae_final, _entries_T_110 node _entries_T_111 = bits(_entries_WIRE_9, 19, 19) connect _entries_WIRE_8.ae_ptw, _entries_T_111 node _entries_T_112 = bits(_entries_WIRE_9, 20, 20) connect _entries_WIRE_8.g, _entries_T_112 node _entries_T_113 = bits(_entries_WIRE_9, 21, 21) connect _entries_WIRE_8.u, _entries_T_113 node _entries_T_114 = bits(_entries_WIRE_9, 41, 22) connect _entries_WIRE_8.ppn, _entries_T_114 inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_117 connect entries_barrier_4.clock, clock connect entries_barrier_4.reset, reset connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage connect entries_barrier_4.io.x.c, _entries_WIRE_8.c connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr connect entries_barrier_4.io.x.px, _entries_WIRE_8.px connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2 connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw connect entries_barrier_4.io.x.g, _entries_WIRE_8.g connect entries_barrier_4.io.x.u, _entries_WIRE_8.u connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _entries_WIRE_11 : UInt<42> connect _entries_WIRE_11, special_entry.data[0] node _entries_T_115 = bits(_entries_WIRE_11, 0, 0) connect _entries_WIRE_10.fragmented_superpage, _entries_T_115 node _entries_T_116 = bits(_entries_WIRE_11, 1, 1) connect _entries_WIRE_10.c, _entries_T_116 node _entries_T_117 = bits(_entries_WIRE_11, 2, 2) connect _entries_WIRE_10.eff, _entries_T_117 node _entries_T_118 = bits(_entries_WIRE_11, 3, 3) connect _entries_WIRE_10.paa, _entries_T_118 node _entries_T_119 = bits(_entries_WIRE_11, 4, 4) connect _entries_WIRE_10.pal, _entries_T_119 node _entries_T_120 = bits(_entries_WIRE_11, 5, 5) connect _entries_WIRE_10.ppp, _entries_T_120 node _entries_T_121 = bits(_entries_WIRE_11, 6, 6) connect _entries_WIRE_10.pr, _entries_T_121 node _entries_T_122 = bits(_entries_WIRE_11, 7, 7) connect _entries_WIRE_10.px, _entries_T_122 node _entries_T_123 = bits(_entries_WIRE_11, 8, 8) connect _entries_WIRE_10.pw, _entries_T_123 node _entries_T_124 = bits(_entries_WIRE_11, 9, 9) connect _entries_WIRE_10.hr, _entries_T_124 node _entries_T_125 = bits(_entries_WIRE_11, 10, 10) connect _entries_WIRE_10.hx, _entries_T_125 node _entries_T_126 = bits(_entries_WIRE_11, 11, 11) connect _entries_WIRE_10.hw, _entries_T_126 node _entries_T_127 = bits(_entries_WIRE_11, 12, 12) connect _entries_WIRE_10.sr, _entries_T_127 node _entries_T_128 = bits(_entries_WIRE_11, 13, 13) connect _entries_WIRE_10.sx, _entries_T_128 node _entries_T_129 = bits(_entries_WIRE_11, 14, 14) connect _entries_WIRE_10.sw, _entries_T_129 node _entries_T_130 = bits(_entries_WIRE_11, 15, 15) connect _entries_WIRE_10.gf, _entries_T_130 node _entries_T_131 = bits(_entries_WIRE_11, 16, 16) connect _entries_WIRE_10.pf, _entries_T_131 node _entries_T_132 = bits(_entries_WIRE_11, 17, 17) connect _entries_WIRE_10.ae_stage2, _entries_T_132 node _entries_T_133 = bits(_entries_WIRE_11, 18, 18) connect _entries_WIRE_10.ae_final, _entries_T_133 node _entries_T_134 = bits(_entries_WIRE_11, 19, 19) connect _entries_WIRE_10.ae_ptw, _entries_T_134 node _entries_T_135 = bits(_entries_WIRE_11, 20, 20) connect _entries_WIRE_10.g, _entries_T_135 node _entries_T_136 = bits(_entries_WIRE_11, 21, 21) connect _entries_WIRE_10.u, _entries_T_136 node _entries_T_137 = bits(_entries_WIRE_11, 41, 22) connect _entries_WIRE_10.ppn, _entries_T_137 inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_118 connect entries_barrier_5.clock, clock connect entries_barrier_5.reset, reset connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage connect entries_barrier_5.io.x.c, _entries_WIRE_10.c connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr connect entries_barrier_5.io.x.px, _entries_WIRE_10.px connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2 connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw connect entries_barrier_5.io.x.g, _entries_WIRE_10.g connect entries_barrier_5.io.x.u, _entries_WIRE_10.u connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn node _ppn_T = eq(vm_enabled, UInt<1>(0h0)) node ppn_res = shr(entries_barrier_4.io.y.ppn, 18) node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1)) node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0)) node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0)) node _ppn_T_2 = or(_ppn_T_1, entries_barrier_4.io.y.ppn) node _ppn_T_3 = bits(_ppn_T_2, 17, 9) node _ppn_T_4 = cat(ppn_res, _ppn_T_3) node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1)) node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0)) node _ppn_T_6 = or(_ppn_T_5, entries_barrier_4.io.y.ppn) node _ppn_T_7 = bits(_ppn_T_6, 8, 0) node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7) node ppn_res_1 = shr(entries_barrier_5.io.y.ppn, 18) node _ppn_ignore_T_2 = lt(special_entry.level, UInt<1>(0h1)) node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0)) node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0)) node _ppn_T_10 = or(_ppn_T_9, entries_barrier_5.io.y.ppn) node _ppn_T_11 = bits(_ppn_T_10, 17, 9) node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11) node _ppn_ignore_T_3 = lt(special_entry.level, UInt<2>(0h2)) node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h0)) node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0)) node _ppn_T_14 = or(_ppn_T_13, entries_barrier_5.io.y.ppn) node _ppn_T_15 = bits(_ppn_T_14, 8, 0) node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15) node _ppn_T_17 = bits(vpn, 19, 0) node _ppn_T_18 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0)) node _ppn_T_19 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0)) node _ppn_T_20 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0)) node _ppn_T_21 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0)) node _ppn_T_22 = mux(hitsVec_4, _ppn_T_8, UInt<1>(0h0)) node _ppn_T_23 = mux(hitsVec_5, _ppn_T_16, UInt<1>(0h0)) node _ppn_T_24 = mux(_ppn_T, _ppn_T_17, UInt<1>(0h0)) node _ppn_T_25 = or(_ppn_T_18, _ppn_T_19) node _ppn_T_26 = or(_ppn_T_25, _ppn_T_20) node _ppn_T_27 = or(_ppn_T_26, _ppn_T_21) node _ppn_T_28 = or(_ppn_T_27, _ppn_T_22) node _ppn_T_29 = or(_ppn_T_28, _ppn_T_23) node _ppn_T_30 = or(_ppn_T_29, _ppn_T_24) wire ppn : UInt<20> connect ppn, _ppn_T_30 node ptw_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw) node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, entries_barrier.io.y.ae_ptw) node ptw_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw) node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, entries_barrier_3.io.y.ae_ptw) node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo) node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T) node final_ae_array_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final) node final_ae_array_lo = cat(final_ae_array_lo_hi, entries_barrier.io.y.ae_final) node final_ae_array_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final) node final_ae_array_hi = cat(final_ae_array_hi_hi, entries_barrier_3.io.y.ae_final) node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo) node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T) node ptw_pf_array_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf) node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, entries_barrier.io.y.pf) node ptw_pf_array_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf) node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, entries_barrier_3.io.y.pf) node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo) node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T) node ptw_gf_array_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf) node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, entries_barrier.io.y.gf) node ptw_gf_array_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf) node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, entries_barrier_3.io.y.gf) node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo) node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T) node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0)) node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum) node priv_rw_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, entries_barrier.io.y.u) node priv_rw_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, entries_barrier_3.io.y.u) node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo) node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0)) node priv_rw_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, entries_barrier.io.y.u) node priv_rw_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, entries_barrier_3.io.y.u) node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1) node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4) node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0)) node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6) node priv_x_ok_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo = cat(priv_x_ok_lo_hi, entries_barrier.io.y.u) node priv_x_ok_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_hi = cat(priv_x_ok_hi_hi, entries_barrier_3.io.y.u) node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo) node _priv_x_ok_T_1 = not(_priv_x_ok_T) node priv_x_ok_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u) node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, entries_barrier.io.y.u) node priv_x_ok_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u) node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, entries_barrier_3.io.y.u) node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1) node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2) node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<6>(0h3f), UInt<6>(0h0)) node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0)) node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<6>(0h3f), UInt<6>(0h0)) node stage1_bypass_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2) node stage1_bypass_lo = cat(stage1_bypass_lo_hi, entries_barrier.io.y.ae_stage2) node stage1_bypass_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2) node stage1_bypass_hi = cat(stage1_bypass_hi_hi, entries_barrier_3.io.y.ae_stage2) node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo) node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3) node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4) node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0)) node mxr = or(io.ptw.status.mxr, _mxr_T) node r_array_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr) node r_array_lo = cat(r_array_lo_hi, entries_barrier.io.y.sr) node r_array_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr) node r_array_hi = cat(r_array_hi_hi, entries_barrier_3.io.y.sr) node _r_array_T = cat(r_array_hi, r_array_lo) node r_array_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node r_array_lo_1 = cat(r_array_lo_hi_1, entries_barrier.io.y.sx) node r_array_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node r_array_hi_1 = cat(r_array_hi_hi_1, entries_barrier_3.io.y.sx) node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1) node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0)) node _r_array_T_3 = or(_r_array_T, _r_array_T_2) node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3) node _r_array_T_5 = or(_r_array_T_4, stage1_bypass) node r_array = cat(UInt<1>(0h1), _r_array_T_5) node w_array_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw) node w_array_lo = cat(w_array_lo_hi, entries_barrier.io.y.sw) node w_array_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw) node w_array_hi = cat(w_array_hi_hi, entries_barrier_3.io.y.sw) node _w_array_T = cat(w_array_hi, w_array_lo) node _w_array_T_1 = and(priv_rw_ok, _w_array_T) node _w_array_T_2 = or(_w_array_T_1, stage1_bypass) node w_array = cat(UInt<1>(0h1), _w_array_T_2) node x_array_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx) node x_array_lo = cat(x_array_lo_hi, entries_barrier.io.y.sx) node x_array_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx) node x_array_hi = cat(x_array_hi_hi, entries_barrier_3.io.y.sx) node _x_array_T = cat(x_array_hi, x_array_lo) node _x_array_T_1 = and(priv_x_ok, _x_array_T) node _x_array_T_2 = or(_x_array_T_1, stage1_bypass) node x_array = cat(UInt<1>(0h1), _x_array_T_2) node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0)) node stage2_bypass = mux(_stage2_bypass_T, UInt<6>(0h3f), UInt<6>(0h0)) node hr_array_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr) node hr_array_lo = cat(hr_array_lo_hi, entries_barrier.io.y.hr) node hr_array_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr) node hr_array_hi = cat(hr_array_hi_hi, entries_barrier_3.io.y.hr) node _hr_array_T = cat(hr_array_hi, hr_array_lo) node hr_array_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hr_array_lo_1 = cat(hr_array_lo_hi_1, entries_barrier.io.y.hx) node hr_array_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hr_array_hi_1 = cat(hr_array_hi_hi_1, entries_barrier_3.io.y.hx) node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1) node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0)) node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2) node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass) node hr_array = cat(UInt<1>(0h1), _hr_array_T_4) node hw_array_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw) node hw_array_lo = cat(hw_array_lo_hi, entries_barrier.io.y.hw) node hw_array_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw) node hw_array_hi = cat(hw_array_hi_hi, entries_barrier_3.io.y.hw) node _hw_array_T = cat(hw_array_hi, hw_array_lo) node _hw_array_T_1 = or(_hw_array_T, stage2_bypass) node hw_array = cat(UInt<1>(0h1), _hw_array_T_1) node hx_array_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx) node hx_array_lo = cat(hx_array_lo_hi, entries_barrier.io.y.hx) node hx_array_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx) node hx_array_hi = cat(hx_array_hi_hi, entries_barrier_3.io.y.hx) node _hx_array_T = cat(hx_array_hi, hx_array_lo) node _hx_array_T_1 = or(_hx_array_T, stage2_bypass) node hx_array = cat(UInt<1>(0h1), _hx_array_T_1) node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0)) node pr_array_lo = cat(entries_barrier_1.io.y.pr, entries_barrier.io.y.pr) node pr_array_hi_hi = cat(entries_barrier_4.io.y.pr, entries_barrier_3.io.y.pr) node pr_array_hi = cat(pr_array_hi_hi, entries_barrier_2.io.y.pr) node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo) node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1) node _pr_array_T_3 = or(ptw_ae_array, final_ae_array) node _pr_array_T_4 = not(_pr_array_T_3) node pr_array = and(_pr_array_T_2, _pr_array_T_4) node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0)) node pw_array_lo = cat(entries_barrier_1.io.y.pw, entries_barrier.io.y.pw) node pw_array_hi_hi = cat(entries_barrier_4.io.y.pw, entries_barrier_3.io.y.pw) node pw_array_hi = cat(pw_array_hi_hi, entries_barrier_2.io.y.pw) node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo) node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1) node _pw_array_T_3 = or(ptw_ae_array, final_ae_array) node _pw_array_T_4 = not(_pw_array_T_3) node pw_array = and(_pw_array_T_2, _pw_array_T_4) node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0)) node px_array_lo = cat(entries_barrier_1.io.y.px, entries_barrier.io.y.px) node px_array_hi_hi = cat(entries_barrier_4.io.y.px, entries_barrier_3.io.y.px) node px_array_hi = cat(px_array_hi_hi, entries_barrier_2.io.y.px) node _px_array_T_1 = cat(px_array_hi, px_array_lo) node _px_array_T_2 = cat(_px_array_T, _px_array_T_1) node _px_array_T_3 = or(ptw_ae_array, final_ae_array) node _px_array_T_4 = not(_px_array_T_3) node px_array = and(_px_array_T_2, _px_array_T_4) node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0)) node eff_array_lo = cat(entries_barrier_1.io.y.eff, entries_barrier.io.y.eff) node eff_array_hi_hi = cat(entries_barrier_4.io.y.eff, entries_barrier_3.io.y.eff) node eff_array_hi = cat(eff_array_hi_hi, entries_barrier_2.io.y.eff) node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo) node eff_array = cat(_eff_array_T, _eff_array_T_1) node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0)) node c_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) node c_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) node c_array_hi = cat(c_array_hi_hi, entries_barrier_2.io.y.c) node _c_array_T_1 = cat(c_array_hi, c_array_lo) node c_array = cat(_c_array_T, _c_array_T_1) node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0)) node ppp_array_lo = cat(entries_barrier_1.io.y.ppp, entries_barrier.io.y.ppp) node ppp_array_hi_hi = cat(entries_barrier_4.io.y.ppp, entries_barrier_3.io.y.ppp) node ppp_array_hi = cat(ppp_array_hi_hi, entries_barrier_2.io.y.ppp) node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo) node ppp_array = cat(_ppp_array_T, _ppp_array_T_1) node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0)) node paa_array_lo = cat(entries_barrier_1.io.y.paa, entries_barrier.io.y.paa) node paa_array_hi_hi = cat(entries_barrier_4.io.y.paa, entries_barrier_3.io.y.paa) node paa_array_hi = cat(paa_array_hi_hi, entries_barrier_2.io.y.paa) node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo) node paa_array = cat(_paa_array_T, _paa_array_T_1) node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0)) node pal_array_lo = cat(entries_barrier_1.io.y.pal, entries_barrier.io.y.pal) node pal_array_hi_hi = cat(entries_barrier_4.io.y.pal, entries_barrier_3.io.y.pal) node pal_array_hi = cat(pal_array_hi_hi, entries_barrier_2.io.y.pal) node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo) node pal_array = cat(_pal_array_T, _pal_array_T_1) node ppp_array_if_cached = or(ppp_array, c_array) node paa_array_if_cached = or(paa_array, c_array) node pal_array_if_cached = or(pal_array, c_array) node _prefetchable_array_T = and(cacheable, homogeneous) node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1) node prefetchable_array_lo = cat(entries_barrier_1.io.y.c, entries_barrier.io.y.c) node prefetchable_array_hi_hi = cat(entries_barrier_4.io.y.c, entries_barrier_3.io.y.c) node prefetchable_array_hi = cat(prefetchable_array_hi_hi, entries_barrier_2.io.y.c) node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo) node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2) node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size) node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1)) node _misaligned_T_2 = tail(_misaligned_T_1, 1) node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2) node misaligned = orr(_misaligned_T_3) node _bad_va_T = and(vm_enabled, stage1_en) node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000)) node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0)) node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000)) node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3) node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4) node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0)) node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6) node bad_va = and(_bad_va_T, _bad_va_T_7) node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1) node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2) node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1) node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2) node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3) node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6) node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1) node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2) node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3) node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4) node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8) node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0)) node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10)) node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6)) node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1) node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2) node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3) node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8) node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9) node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10) node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15) node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16) node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17) node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18) node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22) node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23) node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10)) node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T) node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1)) node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11)) node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1) node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7)) node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3) node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4)) node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9)) node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha)) node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb)) node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6) node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7) node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8) node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8)) node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc)) node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd)) node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he)) node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf)) node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13) node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14) node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15) node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16) node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20) node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21) node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5)) node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17)) node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1) node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2) node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array) node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0)) node _ae_array_T_1 = not(lrscAllowed) node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0)) node ae_array = or(_ae_array_T, _ae_array_T_2) node _ae_ld_array_T = not(pr_array) node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T) node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0)) node _ae_st_array_T = not(pw_array) node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T) node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0)) node _ae_st_array_T_3 = not(ppp_array_if_cached) node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0)) node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4) node _ae_st_array_T_6 = not(pal_array_if_cached) node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0)) node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7) node _ae_st_array_T_9 = not(paa_array_if_cached) node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0)) node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10) node _must_alloc_array_T = not(ppp_array) node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0)) node _must_alloc_array_T_2 = not(pal_array) node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0)) node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3) node _must_alloc_array_T_5 = not(paa_array) node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0)) node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6) node _must_alloc_array_T_8 = not(UInt<7>(0h0)) node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0)) node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9) node _pf_ld_array_T = mux(cmd_readx, x_array, r_array) node _pf_ld_array_T_1 = not(_pf_ld_array_T) node _pf_ld_array_T_2 = not(ptw_ae_array) node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2) node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array) node _pf_ld_array_T_5 = not(ptw_gf_array) node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5) node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0)) node _pf_st_array_T = not(w_array) node _pf_st_array_T_1 = not(ptw_ae_array) node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1) node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array) node _pf_st_array_T_4 = not(ptw_gf_array) node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4) node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0)) node _pf_inst_array_T = not(x_array) node _pf_inst_array_T_1 = not(ptw_ae_array) node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1) node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array) node _pf_inst_array_T_4 = not(ptw_gf_array) node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4) node _gf_ld_array_T = and(priv_v, cmd_read) node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array) node _gf_ld_array_T_2 = not(_gf_ld_array_T_1) node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array) node _gf_ld_array_T_4 = not(ptw_ae_array) node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4) node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0)) node _gf_st_array_T = and(priv_v, cmd_write_perms) node _gf_st_array_T_1 = not(hw_array) node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array) node _gf_st_array_T_3 = not(ptw_ae_array) node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3) node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0)) node _gf_inst_array_T = not(hx_array) node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array) node _gf_inst_array_T_2 = not(ptw_ae_array) node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2) node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0)) node gpa_hits_need_gpa_mask = or(gf_ld_array, gf_st_array) node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn) node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T) node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<5>(0h1f), UInt<5>(0h0)) node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0)) node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<6>(0h3f), UInt<6>(0h0)) node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4) node _gpa_hits_T = bits(gpa_hits_need_gpa_mask, 5, 0) node _gpa_hits_T_1 = not(_gpa_hits_T) node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1) node tlb_hit_if_not_gpa_miss = orr(real_hits) node _tlb_hit_T = and(real_hits, gpa_hits) node tlb_hit = orr(_tlb_hit_T) node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0)) node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T) node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0)) node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2) node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0)) node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4) regreset state_reg : UInt<3>, clock, reset, UInt<3>(0h0) wire _state_vec_WIRE : UInt<3>[4] connect _state_vec_WIRE[0], UInt<3>(0h0) connect _state_vec_WIRE[1], UInt<3>(0h0) connect _state_vec_WIRE[2], UInt<3>(0h0) connect _state_vec_WIRE[3], UInt<3>(0h0) regreset state_vec : UInt<3>[4], clock, reset, _state_vec_WIRE reg state_reg_1 : UInt<0>, clock node _T_12 = and(io.req.valid, vm_enabled) when _T_12 : node _T_13 = or(sector_hits_0, sector_hits_1) node _T_14 = or(_T_13, sector_hits_2) node _T_15 = or(_T_14, sector_hits_3) when _T_15 : node lo = cat(sector_hits_1, sector_hits_0) node hi = cat(sector_hits_3, sector_hits_2) node _T_16 = cat(hi, lo) node hi_1 = bits(_T_16, 3, 2) node lo_1 = bits(_T_16, 1, 0) node _T_17 = orr(hi_1) node _T_18 = or(hi_1, lo_1) node _T_19 = bits(_T_18, 1, 1) node _T_20 = cat(_T_17, _T_19) node state_vec_touch_way_sized = bits(_T_20, 1, 0) node _state_vec_set_left_older_T = bits(state_vec_touch_way_sized, 1, 1) node state_vec_set_left_older = eq(_state_vec_set_left_older_T, UInt<1>(0h0)) node state_vec_left_subtree_state = bits(state_vec[memIdx], 1, 1) node state_vec_right_subtree_state = bits(state_vec[memIdx], 0, 0) node _state_vec_T = bits(state_vec_touch_way_sized, 0, 0) node _state_vec_T_1 = bits(_state_vec_T, 0, 0) node _state_vec_T_2 = eq(_state_vec_T_1, UInt<1>(0h0)) node _state_vec_T_3 = mux(state_vec_set_left_older, state_vec_left_subtree_state, _state_vec_T_2) node _state_vec_T_4 = bits(state_vec_touch_way_sized, 0, 0) node _state_vec_T_5 = bits(_state_vec_T_4, 0, 0) node _state_vec_T_6 = eq(_state_vec_T_5, UInt<1>(0h0)) node _state_vec_T_7 = mux(state_vec_set_left_older, _state_vec_T_6, state_vec_right_subtree_state) node state_vec_hi = cat(state_vec_set_left_older, _state_vec_T_3) node _state_vec_T_8 = cat(state_vec_hi, _state_vec_T_7) connect state_vec[memIdx], _state_vec_T_8 when superpage_hits_0 : connect state_reg_1, UInt<1>(0h0) node _multipleHits_T = bits(real_hits, 2, 0) node _multipleHits_T_1 = bits(_multipleHits_T, 0, 0) node multipleHits_leftOne = bits(_multipleHits_T_1, 0, 0) node _multipleHits_T_2 = bits(_multipleHits_T, 2, 1) node _multipleHits_T_3 = bits(_multipleHits_T_2, 0, 0) node multipleHits_leftOne_1 = bits(_multipleHits_T_3, 0, 0) node _multipleHits_T_4 = bits(_multipleHits_T_2, 1, 1) node multipleHits_rightOne = bits(_multipleHits_T_4, 0, 0) node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne) node _multipleHits_T_5 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_6 = and(multipleHits_leftOne_1, multipleHits_rightOne) node multipleHits_rightTwo = or(_multipleHits_T_5, _multipleHits_T_6) node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1) node _multipleHits_T_7 = or(UInt<1>(0h0), multipleHits_rightTwo) node _multipleHits_T_8 = and(multipleHits_leftOne, multipleHits_rightOne_1) node multipleHits_leftTwo = or(_multipleHits_T_7, _multipleHits_T_8) node _multipleHits_T_9 = bits(real_hits, 5, 3) node _multipleHits_T_10 = bits(_multipleHits_T_9, 0, 0) node multipleHits_leftOne_3 = bits(_multipleHits_T_10, 0, 0) node _multipleHits_T_11 = bits(_multipleHits_T_9, 2, 1) node _multipleHits_T_12 = bits(_multipleHits_T_11, 0, 0) node multipleHits_leftOne_4 = bits(_multipleHits_T_12, 0, 0) node _multipleHits_T_13 = bits(_multipleHits_T_11, 1, 1) node multipleHits_rightOne_2 = bits(_multipleHits_T_13, 0, 0) node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2) node _multipleHits_T_14 = or(UInt<1>(0h0), UInt<1>(0h0)) node _multipleHits_T_15 = and(multipleHits_leftOne_4, multipleHits_rightOne_2) node multipleHits_rightTwo_1 = or(_multipleHits_T_14, _multipleHits_T_15) node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3) node _multipleHits_T_16 = or(UInt<1>(0h0), multipleHits_rightTwo_1) node _multipleHits_T_17 = and(multipleHits_leftOne_3, multipleHits_rightOne_3) node multipleHits_rightTwo_2 = or(_multipleHits_T_16, _multipleHits_T_17) node _multipleHits_T_18 = or(multipleHits_leftOne_2, multipleHits_rightOne_4) node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2) node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4) node multipleHits = or(_multipleHits_T_19, _multipleHits_T_20) node _io_req_ready_T = eq(state, UInt<2>(0h0)) connect io.req.ready, _io_req_ready_T node _io_resp_pf_ld_T = and(bad_va, cmd_read) node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits) node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1) node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2) connect io.resp.pf.ld, _io_resp_pf_ld_T_3 node _io_resp_pf_st_T = and(bad_va, cmd_write_perms) node _io_resp_pf_st_T_1 = and(pf_st_array, hits) node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1) node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2) connect io.resp.pf.st, _io_resp_pf_st_T_3 node _io_resp_pf_inst_T = and(pf_inst_array, hits) node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T) node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1) connect io.resp.pf.inst, _io_resp_pf_inst_T_2 node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read) node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits) node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1) node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2) connect io.resp.gf.ld, _io_resp_gf_ld_T_3 node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms) node _io_resp_gf_st_T_1 = and(gf_st_array, hits) node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1) node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2) connect io.resp.gf.st, _io_resp_gf_st_T_3 node _io_resp_gf_inst_T = and(gf_inst_array, hits) node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T) node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1) connect io.resp.gf.inst, _io_resp_gf_inst_T_2 node _io_resp_ae_ld_T = and(ae_ld_array, hits) node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T) connect io.resp.ae.ld, _io_resp_ae_ld_T_1 node _io_resp_ae_st_T = and(ae_st_array, hits) node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T) connect io.resp.ae.st, _io_resp_ae_st_T_1 node _io_resp_ae_inst_T = not(px_array) node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits) node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1) connect io.resp.ae.inst, _io_resp_ae_inst_T_2 node _io_resp_ma_ld_T = and(misaligned, cmd_read) connect io.resp.ma.ld, _io_resp_ma_ld_T node _io_resp_ma_st_T = and(misaligned, cmd_write) connect io.resp.ma.st, _io_resp_ma_st_T connect io.resp.ma.inst, UInt<1>(0h0) node _io_resp_cacheable_T = and(c_array, hits) node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T) connect io.resp.cacheable, _io_resp_cacheable_T_1 node _io_resp_must_alloc_T = and(must_alloc_array, hits) node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T) connect io.resp.must_alloc, _io_resp_must_alloc_T_1 node _io_resp_prefetchable_T = and(prefetchable_array, hits) node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T) node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1)) connect io.resp.prefetchable, _io_resp_prefetchable_T_2 node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch) node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss) node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits) connect io.resp.miss, _io_resp_miss_T_2 node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0) node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T) connect io.resp.paddr, _io_resp_paddr_T_1 connect io.resp.size, io.req.bits.size connect io.resp.cmd, io.req.bits.cmd node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte) connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0)) node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn) node _io_resp_gpa_page_T_2 = shr(r_gpa, 12) node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2) node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0) node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0) node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1) node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset) connect io.resp.gpa, _io_resp_gpa_T node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1)) connect io.ptw.req.valid, _io_ptw_req_valid_T node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0)) connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T connect io.ptw.req.bits.bits.addr, r_refill_tag connect io.ptw.req.bits.bits.vstage1, r_vstage1_en connect io.ptw.req.bits.bits.stage2, r_stage2_en connect io.ptw.req.bits.bits.need_gpa, r_need_gpa node _T_21 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_22 = and(_T_21, io.ptw.req.bits.valid) when _T_22 : connect r_gpa_valid, UInt<1>(0h0) connect r_gpa_vpn, r_refill_tag node _T_23 = and(io.req.ready, io.req.valid) node _T_24 = and(_T_23, tlb_miss) when _T_24 : connect state, UInt<2>(0h1) connect r_refill_tag, vpn connect r_need_gpa, tlb_hit_if_not_gpa_miss connect r_vstage1_en, vstage1_en connect r_stage2_en, stage2_en node _r_superpage_repl_addr_T = andr(superpage_entries[0].valid[0]) node _r_superpage_repl_addr_T_1 = not(superpage_entries[0].valid[0]) node _r_superpage_repl_addr_T_2 = bits(_r_superpage_repl_addr_T_1, 0, 0) node _r_superpage_repl_addr_T_3 = mux(_r_superpage_repl_addr_T, UInt<1>(0h0), UInt<1>(0h0)) connect r_superpage_repl_addr, _r_superpage_repl_addr_T_3 node r_sectored_repl_addr_left_subtree_older = bits(state_vec[memIdx], 2, 2) node r_sectored_repl_addr_left_subtree_state = bits(state_vec[memIdx], 1, 1) node r_sectored_repl_addr_right_subtree_state = bits(state_vec[memIdx], 0, 0) node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state, 0, 0) node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0) node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1) node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2) node r_sectored_repl_addr_valids_lo = cat(sectored_entries[memIdx][1].valid[0], sectored_entries[memIdx][0].valid[0]) node r_sectored_repl_addr_valids_hi = cat(sectored_entries[memIdx][3].valid[0], sectored_entries[memIdx][2].valid[0]) node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo) node _r_sectored_repl_addr_T_4 = andr(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_5 = not(r_sectored_repl_addr_valids) node _r_sectored_repl_addr_T_6 = bits(_r_sectored_repl_addr_T_5, 0, 0) node _r_sectored_repl_addr_T_7 = bits(_r_sectored_repl_addr_T_5, 1, 1) node _r_sectored_repl_addr_T_8 = bits(_r_sectored_repl_addr_T_5, 2, 2) node _r_sectored_repl_addr_T_9 = bits(_r_sectored_repl_addr_T_5, 3, 3) node _r_sectored_repl_addr_T_10 = mux(_r_sectored_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _r_sectored_repl_addr_T_11 = mux(_r_sectored_repl_addr_T_7, UInt<1>(0h1), _r_sectored_repl_addr_T_10) node _r_sectored_repl_addr_T_12 = mux(_r_sectored_repl_addr_T_6, UInt<1>(0h0), _r_sectored_repl_addr_T_11) node _r_sectored_repl_addr_T_13 = mux(_r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_12) connect r_sectored_repl_addr, _r_sectored_repl_addr_T_13 node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1) node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2) node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3) connect r_sectored_hit.valid, _r_sectored_hit_valid_T_2 node r_sectored_hit_bits_lo = cat(sector_hits_1, sector_hits_0) node r_sectored_hit_bits_hi = cat(sector_hits_3, sector_hits_2) node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo) node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 3, 2) node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 1, 0) node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1) node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1) node _r_sectored_hit_bits_T_3 = bits(_r_sectored_hit_bits_T_2, 1, 1) node _r_sectored_hit_bits_T_4 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3) connect r_sectored_hit.bits, _r_sectored_hit_bits_T_4 connect r_superpage_hit.valid, superpage_hits_0 connect r_superpage_hit.bits, UInt<1>(0h0) node _T_25 = eq(state, UInt<2>(0h1)) when _T_25 : when io.sfence.valid : connect state, UInt<2>(0h0) when io.ptw.req.ready : node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2)) connect state, _state_T when io.kill : connect state, UInt<2>(0h0) node _T_26 = eq(state, UInt<2>(0h2)) node _T_27 = and(_T_26, io.sfence.valid) when _T_27 : connect state, UInt<2>(0h3) when io.ptw.resp.valid : connect state, UInt<2>(0h0) when io.sfence.valid : node _T_28 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_29 = shr(io.sfence.bits.addr, 12) node _T_30 = eq(_T_29, vpn) node _T_31 = or(_T_28, _T_30) node _T_32 = asUInt(reset) node _T_33 = eq(_T_32, UInt<1>(0h0)) when _T_33 : node _T_34 = eq(_T_31, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf assert(clock, _T_31, UInt<1>(0h1), "") : assert node hv = and(UInt<1>(0h0), io.sfence.bits.hv) node hg = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_35 = eq(hg, UInt<1>(0h0)) node _T_36 = and(_T_35, io.sfence.bits.rs1) when _T_36 : node _T_37 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_38 = shr(_T_37, 0) node _T_39 = eq(_T_38, UInt<1>(0h0)) node _T_40 = eq(sectored_entries[0][0].tag_v, hv) node _T_41 = and(_T_39, _T_40) when _T_41 : wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_1 : UInt<42> connect _WIRE_1, sectored_entries[0][0].data[0] node _T_42 = bits(_WIRE_1, 0, 0) connect _WIRE.fragmented_superpage, _T_42 node _T_43 = bits(_WIRE_1, 1, 1) connect _WIRE.c, _T_43 node _T_44 = bits(_WIRE_1, 2, 2) connect _WIRE.eff, _T_44 node _T_45 = bits(_WIRE_1, 3, 3) connect _WIRE.paa, _T_45 node _T_46 = bits(_WIRE_1, 4, 4) connect _WIRE.pal, _T_46 node _T_47 = bits(_WIRE_1, 5, 5) connect _WIRE.ppp, _T_47 node _T_48 = bits(_WIRE_1, 6, 6) connect _WIRE.pr, _T_48 node _T_49 = bits(_WIRE_1, 7, 7) connect _WIRE.px, _T_49 node _T_50 = bits(_WIRE_1, 8, 8) connect _WIRE.pw, _T_50 node _T_51 = bits(_WIRE_1, 9, 9) connect _WIRE.hr, _T_51 node _T_52 = bits(_WIRE_1, 10, 10) connect _WIRE.hx, _T_52 node _T_53 = bits(_WIRE_1, 11, 11) connect _WIRE.hw, _T_53 node _T_54 = bits(_WIRE_1, 12, 12) connect _WIRE.sr, _T_54 node _T_55 = bits(_WIRE_1, 13, 13) connect _WIRE.sx, _T_55 node _T_56 = bits(_WIRE_1, 14, 14) connect _WIRE.sw, _T_56 node _T_57 = bits(_WIRE_1, 15, 15) connect _WIRE.gf, _T_57 node _T_58 = bits(_WIRE_1, 16, 16) connect _WIRE.pf, _T_58 node _T_59 = bits(_WIRE_1, 17, 17) connect _WIRE.ae_stage2, _T_59 node _T_60 = bits(_WIRE_1, 18, 18) connect _WIRE.ae_final, _T_60 node _T_61 = bits(_WIRE_1, 19, 19) connect _WIRE.ae_ptw, _T_61 node _T_62 = bits(_WIRE_1, 20, 20) connect _WIRE.g, _T_62 node _T_63 = bits(_WIRE_1, 21, 21) connect _WIRE.u, _T_63 node _T_64 = bits(_WIRE_1, 41, 22) connect _WIRE.ppn, _T_64 node _T_65 = eq(sectored_entries[0][0].tag_v, hv) node _T_66 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) when _T_67 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node _T_68 = xor(sectored_entries[0][0].tag_vpn, vpn) node _T_69 = shr(_T_68, 18) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_3 : UInt<42> connect _WIRE_3, sectored_entries[0][0].data[0] node _T_71 = bits(_WIRE_3, 0, 0) connect _WIRE_2.fragmented_superpage, _T_71 node _T_72 = bits(_WIRE_3, 1, 1) connect _WIRE_2.c, _T_72 node _T_73 = bits(_WIRE_3, 2, 2) connect _WIRE_2.eff, _T_73 node _T_74 = bits(_WIRE_3, 3, 3) connect _WIRE_2.paa, _T_74 node _T_75 = bits(_WIRE_3, 4, 4) connect _WIRE_2.pal, _T_75 node _T_76 = bits(_WIRE_3, 5, 5) connect _WIRE_2.ppp, _T_76 node _T_77 = bits(_WIRE_3, 6, 6) connect _WIRE_2.pr, _T_77 node _T_78 = bits(_WIRE_3, 7, 7) connect _WIRE_2.px, _T_78 node _T_79 = bits(_WIRE_3, 8, 8) connect _WIRE_2.pw, _T_79 node _T_80 = bits(_WIRE_3, 9, 9) connect _WIRE_2.hr, _T_80 node _T_81 = bits(_WIRE_3, 10, 10) connect _WIRE_2.hx, _T_81 node _T_82 = bits(_WIRE_3, 11, 11) connect _WIRE_2.hw, _T_82 node _T_83 = bits(_WIRE_3, 12, 12) connect _WIRE_2.sr, _T_83 node _T_84 = bits(_WIRE_3, 13, 13) connect _WIRE_2.sx, _T_84 node _T_85 = bits(_WIRE_3, 14, 14) connect _WIRE_2.sw, _T_85 node _T_86 = bits(_WIRE_3, 15, 15) connect _WIRE_2.gf, _T_86 node _T_87 = bits(_WIRE_3, 16, 16) connect _WIRE_2.pf, _T_87 node _T_88 = bits(_WIRE_3, 17, 17) connect _WIRE_2.ae_stage2, _T_88 node _T_89 = bits(_WIRE_3, 18, 18) connect _WIRE_2.ae_final, _T_89 node _T_90 = bits(_WIRE_3, 19, 19) connect _WIRE_2.ae_ptw, _T_90 node _T_91 = bits(_WIRE_3, 20, 20) connect _WIRE_2.g, _T_91 node _T_92 = bits(_WIRE_3, 21, 21) connect _WIRE_2.u, _T_92 node _T_93 = bits(_WIRE_3, 41, 22) connect _WIRE_2.ppn, _T_93 node _T_94 = eq(sectored_entries[0][0].tag_v, hv) node _T_95 = and(_T_94, _WIRE_2.fragmented_superpage) when _T_95 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) else : node _T_96 = eq(hg, UInt<1>(0h0)) node _T_97 = and(_T_96, io.sfence.bits.rs2) when _T_97 : wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_5 : UInt<42> connect _WIRE_5, sectored_entries[0][0].data[0] node _T_98 = bits(_WIRE_5, 0, 0) connect _WIRE_4.fragmented_superpage, _T_98 node _T_99 = bits(_WIRE_5, 1, 1) connect _WIRE_4.c, _T_99 node _T_100 = bits(_WIRE_5, 2, 2) connect _WIRE_4.eff, _T_100 node _T_101 = bits(_WIRE_5, 3, 3) connect _WIRE_4.paa, _T_101 node _T_102 = bits(_WIRE_5, 4, 4) connect _WIRE_4.pal, _T_102 node _T_103 = bits(_WIRE_5, 5, 5) connect _WIRE_4.ppp, _T_103 node _T_104 = bits(_WIRE_5, 6, 6) connect _WIRE_4.pr, _T_104 node _T_105 = bits(_WIRE_5, 7, 7) connect _WIRE_4.px, _T_105 node _T_106 = bits(_WIRE_5, 8, 8) connect _WIRE_4.pw, _T_106 node _T_107 = bits(_WIRE_5, 9, 9) connect _WIRE_4.hr, _T_107 node _T_108 = bits(_WIRE_5, 10, 10) connect _WIRE_4.hx, _T_108 node _T_109 = bits(_WIRE_5, 11, 11) connect _WIRE_4.hw, _T_109 node _T_110 = bits(_WIRE_5, 12, 12) connect _WIRE_4.sr, _T_110 node _T_111 = bits(_WIRE_5, 13, 13) connect _WIRE_4.sx, _T_111 node _T_112 = bits(_WIRE_5, 14, 14) connect _WIRE_4.sw, _T_112 node _T_113 = bits(_WIRE_5, 15, 15) connect _WIRE_4.gf, _T_113 node _T_114 = bits(_WIRE_5, 16, 16) connect _WIRE_4.pf, _T_114 node _T_115 = bits(_WIRE_5, 17, 17) connect _WIRE_4.ae_stage2, _T_115 node _T_116 = bits(_WIRE_5, 18, 18) connect _WIRE_4.ae_final, _T_116 node _T_117 = bits(_WIRE_5, 19, 19) connect _WIRE_4.ae_ptw, _T_117 node _T_118 = bits(_WIRE_5, 20, 20) connect _WIRE_4.g, _T_118 node _T_119 = bits(_WIRE_5, 21, 21) connect _WIRE_4.u, _T_119 node _T_120 = bits(_WIRE_5, 41, 22) connect _WIRE_4.ppn, _T_120 node _T_121 = eq(sectored_entries[0][0].tag_v, hv) node _T_122 = eq(_WIRE_4.g, UInt<1>(0h0)) node _T_123 = and(_T_121, _T_122) when _T_123 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) else : node _T_124 = or(hv, hg) wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_7 : UInt<42> connect _WIRE_7, sectored_entries[0][0].data[0] node _T_125 = bits(_WIRE_7, 0, 0) connect _WIRE_6.fragmented_superpage, _T_125 node _T_126 = bits(_WIRE_7, 1, 1) connect _WIRE_6.c, _T_126 node _T_127 = bits(_WIRE_7, 2, 2) connect _WIRE_6.eff, _T_127 node _T_128 = bits(_WIRE_7, 3, 3) connect _WIRE_6.paa, _T_128 node _T_129 = bits(_WIRE_7, 4, 4) connect _WIRE_6.pal, _T_129 node _T_130 = bits(_WIRE_7, 5, 5) connect _WIRE_6.ppp, _T_130 node _T_131 = bits(_WIRE_7, 6, 6) connect _WIRE_6.pr, _T_131 node _T_132 = bits(_WIRE_7, 7, 7) connect _WIRE_6.px, _T_132 node _T_133 = bits(_WIRE_7, 8, 8) connect _WIRE_6.pw, _T_133 node _T_134 = bits(_WIRE_7, 9, 9) connect _WIRE_6.hr, _T_134 node _T_135 = bits(_WIRE_7, 10, 10) connect _WIRE_6.hx, _T_135 node _T_136 = bits(_WIRE_7, 11, 11) connect _WIRE_6.hw, _T_136 node _T_137 = bits(_WIRE_7, 12, 12) connect _WIRE_6.sr, _T_137 node _T_138 = bits(_WIRE_7, 13, 13) connect _WIRE_6.sx, _T_138 node _T_139 = bits(_WIRE_7, 14, 14) connect _WIRE_6.sw, _T_139 node _T_140 = bits(_WIRE_7, 15, 15) connect _WIRE_6.gf, _T_140 node _T_141 = bits(_WIRE_7, 16, 16) connect _WIRE_6.pf, _T_141 node _T_142 = bits(_WIRE_7, 17, 17) connect _WIRE_6.ae_stage2, _T_142 node _T_143 = bits(_WIRE_7, 18, 18) connect _WIRE_6.ae_final, _T_143 node _T_144 = bits(_WIRE_7, 19, 19) connect _WIRE_6.ae_ptw, _T_144 node _T_145 = bits(_WIRE_7, 20, 20) connect _WIRE_6.g, _T_145 node _T_146 = bits(_WIRE_7, 21, 21) connect _WIRE_6.u, _T_146 node _T_147 = bits(_WIRE_7, 41, 22) connect _WIRE_6.ppn, _T_147 node _T_148 = eq(sectored_entries[0][0].tag_v, _T_124) when _T_148 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_149 = eq(hg_1, UInt<1>(0h0)) node _T_150 = and(_T_149, io.sfence.bits.rs1) when _T_150 : node _T_151 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_152 = shr(_T_151, 0) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_155 = and(_T_153, _T_154) when _T_155 : wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_9 : UInt<42> connect _WIRE_9, sectored_entries[0][1].data[0] node _T_156 = bits(_WIRE_9, 0, 0) connect _WIRE_8.fragmented_superpage, _T_156 node _T_157 = bits(_WIRE_9, 1, 1) connect _WIRE_8.c, _T_157 node _T_158 = bits(_WIRE_9, 2, 2) connect _WIRE_8.eff, _T_158 node _T_159 = bits(_WIRE_9, 3, 3) connect _WIRE_8.paa, _T_159 node _T_160 = bits(_WIRE_9, 4, 4) connect _WIRE_8.pal, _T_160 node _T_161 = bits(_WIRE_9, 5, 5) connect _WIRE_8.ppp, _T_161 node _T_162 = bits(_WIRE_9, 6, 6) connect _WIRE_8.pr, _T_162 node _T_163 = bits(_WIRE_9, 7, 7) connect _WIRE_8.px, _T_163 node _T_164 = bits(_WIRE_9, 8, 8) connect _WIRE_8.pw, _T_164 node _T_165 = bits(_WIRE_9, 9, 9) connect _WIRE_8.hr, _T_165 node _T_166 = bits(_WIRE_9, 10, 10) connect _WIRE_8.hx, _T_166 node _T_167 = bits(_WIRE_9, 11, 11) connect _WIRE_8.hw, _T_167 node _T_168 = bits(_WIRE_9, 12, 12) connect _WIRE_8.sr, _T_168 node _T_169 = bits(_WIRE_9, 13, 13) connect _WIRE_8.sx, _T_169 node _T_170 = bits(_WIRE_9, 14, 14) connect _WIRE_8.sw, _T_170 node _T_171 = bits(_WIRE_9, 15, 15) connect _WIRE_8.gf, _T_171 node _T_172 = bits(_WIRE_9, 16, 16) connect _WIRE_8.pf, _T_172 node _T_173 = bits(_WIRE_9, 17, 17) connect _WIRE_8.ae_stage2, _T_173 node _T_174 = bits(_WIRE_9, 18, 18) connect _WIRE_8.ae_final, _T_174 node _T_175 = bits(_WIRE_9, 19, 19) connect _WIRE_8.ae_ptw, _T_175 node _T_176 = bits(_WIRE_9, 20, 20) connect _WIRE_8.g, _T_176 node _T_177 = bits(_WIRE_9, 21, 21) connect _WIRE_8.u, _T_177 node _T_178 = bits(_WIRE_9, 41, 22) connect _WIRE_8.ppn, _T_178 node _T_179 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_180 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_181 = and(_T_179, _T_180) when _T_181 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node _T_182 = xor(sectored_entries[0][1].tag_vpn, vpn) node _T_183 = shr(_T_182, 18) node _T_184 = eq(_T_183, UInt<1>(0h0)) when _T_184 : wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_11 : UInt<42> connect _WIRE_11, sectored_entries[0][1].data[0] node _T_185 = bits(_WIRE_11, 0, 0) connect _WIRE_10.fragmented_superpage, _T_185 node _T_186 = bits(_WIRE_11, 1, 1) connect _WIRE_10.c, _T_186 node _T_187 = bits(_WIRE_11, 2, 2) connect _WIRE_10.eff, _T_187 node _T_188 = bits(_WIRE_11, 3, 3) connect _WIRE_10.paa, _T_188 node _T_189 = bits(_WIRE_11, 4, 4) connect _WIRE_10.pal, _T_189 node _T_190 = bits(_WIRE_11, 5, 5) connect _WIRE_10.ppp, _T_190 node _T_191 = bits(_WIRE_11, 6, 6) connect _WIRE_10.pr, _T_191 node _T_192 = bits(_WIRE_11, 7, 7) connect _WIRE_10.px, _T_192 node _T_193 = bits(_WIRE_11, 8, 8) connect _WIRE_10.pw, _T_193 node _T_194 = bits(_WIRE_11, 9, 9) connect _WIRE_10.hr, _T_194 node _T_195 = bits(_WIRE_11, 10, 10) connect _WIRE_10.hx, _T_195 node _T_196 = bits(_WIRE_11, 11, 11) connect _WIRE_10.hw, _T_196 node _T_197 = bits(_WIRE_11, 12, 12) connect _WIRE_10.sr, _T_197 node _T_198 = bits(_WIRE_11, 13, 13) connect _WIRE_10.sx, _T_198 node _T_199 = bits(_WIRE_11, 14, 14) connect _WIRE_10.sw, _T_199 node _T_200 = bits(_WIRE_11, 15, 15) connect _WIRE_10.gf, _T_200 node _T_201 = bits(_WIRE_11, 16, 16) connect _WIRE_10.pf, _T_201 node _T_202 = bits(_WIRE_11, 17, 17) connect _WIRE_10.ae_stage2, _T_202 node _T_203 = bits(_WIRE_11, 18, 18) connect _WIRE_10.ae_final, _T_203 node _T_204 = bits(_WIRE_11, 19, 19) connect _WIRE_10.ae_ptw, _T_204 node _T_205 = bits(_WIRE_11, 20, 20) connect _WIRE_10.g, _T_205 node _T_206 = bits(_WIRE_11, 21, 21) connect _WIRE_10.u, _T_206 node _T_207 = bits(_WIRE_11, 41, 22) connect _WIRE_10.ppn, _T_207 node _T_208 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_209 = and(_T_208, _WIRE_10.fragmented_superpage) when _T_209 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) else : node _T_210 = eq(hg_1, UInt<1>(0h0)) node _T_211 = and(_T_210, io.sfence.bits.rs2) when _T_211 : wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_13 : UInt<42> connect _WIRE_13, sectored_entries[0][1].data[0] node _T_212 = bits(_WIRE_13, 0, 0) connect _WIRE_12.fragmented_superpage, _T_212 node _T_213 = bits(_WIRE_13, 1, 1) connect _WIRE_12.c, _T_213 node _T_214 = bits(_WIRE_13, 2, 2) connect _WIRE_12.eff, _T_214 node _T_215 = bits(_WIRE_13, 3, 3) connect _WIRE_12.paa, _T_215 node _T_216 = bits(_WIRE_13, 4, 4) connect _WIRE_12.pal, _T_216 node _T_217 = bits(_WIRE_13, 5, 5) connect _WIRE_12.ppp, _T_217 node _T_218 = bits(_WIRE_13, 6, 6) connect _WIRE_12.pr, _T_218 node _T_219 = bits(_WIRE_13, 7, 7) connect _WIRE_12.px, _T_219 node _T_220 = bits(_WIRE_13, 8, 8) connect _WIRE_12.pw, _T_220 node _T_221 = bits(_WIRE_13, 9, 9) connect _WIRE_12.hr, _T_221 node _T_222 = bits(_WIRE_13, 10, 10) connect _WIRE_12.hx, _T_222 node _T_223 = bits(_WIRE_13, 11, 11) connect _WIRE_12.hw, _T_223 node _T_224 = bits(_WIRE_13, 12, 12) connect _WIRE_12.sr, _T_224 node _T_225 = bits(_WIRE_13, 13, 13) connect _WIRE_12.sx, _T_225 node _T_226 = bits(_WIRE_13, 14, 14) connect _WIRE_12.sw, _T_226 node _T_227 = bits(_WIRE_13, 15, 15) connect _WIRE_12.gf, _T_227 node _T_228 = bits(_WIRE_13, 16, 16) connect _WIRE_12.pf, _T_228 node _T_229 = bits(_WIRE_13, 17, 17) connect _WIRE_12.ae_stage2, _T_229 node _T_230 = bits(_WIRE_13, 18, 18) connect _WIRE_12.ae_final, _T_230 node _T_231 = bits(_WIRE_13, 19, 19) connect _WIRE_12.ae_ptw, _T_231 node _T_232 = bits(_WIRE_13, 20, 20) connect _WIRE_12.g, _T_232 node _T_233 = bits(_WIRE_13, 21, 21) connect _WIRE_12.u, _T_233 node _T_234 = bits(_WIRE_13, 41, 22) connect _WIRE_12.ppn, _T_234 node _T_235 = eq(sectored_entries[0][1].tag_v, hv_1) node _T_236 = eq(_WIRE_12.g, UInt<1>(0h0)) node _T_237 = and(_T_235, _T_236) when _T_237 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) else : node _T_238 = or(hv_1, hg_1) wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_15 : UInt<42> connect _WIRE_15, sectored_entries[0][1].data[0] node _T_239 = bits(_WIRE_15, 0, 0) connect _WIRE_14.fragmented_superpage, _T_239 node _T_240 = bits(_WIRE_15, 1, 1) connect _WIRE_14.c, _T_240 node _T_241 = bits(_WIRE_15, 2, 2) connect _WIRE_14.eff, _T_241 node _T_242 = bits(_WIRE_15, 3, 3) connect _WIRE_14.paa, _T_242 node _T_243 = bits(_WIRE_15, 4, 4) connect _WIRE_14.pal, _T_243 node _T_244 = bits(_WIRE_15, 5, 5) connect _WIRE_14.ppp, _T_244 node _T_245 = bits(_WIRE_15, 6, 6) connect _WIRE_14.pr, _T_245 node _T_246 = bits(_WIRE_15, 7, 7) connect _WIRE_14.px, _T_246 node _T_247 = bits(_WIRE_15, 8, 8) connect _WIRE_14.pw, _T_247 node _T_248 = bits(_WIRE_15, 9, 9) connect _WIRE_14.hr, _T_248 node _T_249 = bits(_WIRE_15, 10, 10) connect _WIRE_14.hx, _T_249 node _T_250 = bits(_WIRE_15, 11, 11) connect _WIRE_14.hw, _T_250 node _T_251 = bits(_WIRE_15, 12, 12) connect _WIRE_14.sr, _T_251 node _T_252 = bits(_WIRE_15, 13, 13) connect _WIRE_14.sx, _T_252 node _T_253 = bits(_WIRE_15, 14, 14) connect _WIRE_14.sw, _T_253 node _T_254 = bits(_WIRE_15, 15, 15) connect _WIRE_14.gf, _T_254 node _T_255 = bits(_WIRE_15, 16, 16) connect _WIRE_14.pf, _T_255 node _T_256 = bits(_WIRE_15, 17, 17) connect _WIRE_14.ae_stage2, _T_256 node _T_257 = bits(_WIRE_15, 18, 18) connect _WIRE_14.ae_final, _T_257 node _T_258 = bits(_WIRE_15, 19, 19) connect _WIRE_14.ae_ptw, _T_258 node _T_259 = bits(_WIRE_15, 20, 20) connect _WIRE_14.g, _T_259 node _T_260 = bits(_WIRE_15, 21, 21) connect _WIRE_14.u, _T_260 node _T_261 = bits(_WIRE_15, 41, 22) connect _WIRE_14.ppn, _T_261 node _T_262 = eq(sectored_entries[0][1].tag_v, _T_238) when _T_262 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_263 = eq(hg_2, UInt<1>(0h0)) node _T_264 = and(_T_263, io.sfence.bits.rs1) when _T_264 : node _T_265 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_266 = shr(_T_265, 0) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_269 = and(_T_267, _T_268) when _T_269 : wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_17 : UInt<42> connect _WIRE_17, sectored_entries[0][2].data[0] node _T_270 = bits(_WIRE_17, 0, 0) connect _WIRE_16.fragmented_superpage, _T_270 node _T_271 = bits(_WIRE_17, 1, 1) connect _WIRE_16.c, _T_271 node _T_272 = bits(_WIRE_17, 2, 2) connect _WIRE_16.eff, _T_272 node _T_273 = bits(_WIRE_17, 3, 3) connect _WIRE_16.paa, _T_273 node _T_274 = bits(_WIRE_17, 4, 4) connect _WIRE_16.pal, _T_274 node _T_275 = bits(_WIRE_17, 5, 5) connect _WIRE_16.ppp, _T_275 node _T_276 = bits(_WIRE_17, 6, 6) connect _WIRE_16.pr, _T_276 node _T_277 = bits(_WIRE_17, 7, 7) connect _WIRE_16.px, _T_277 node _T_278 = bits(_WIRE_17, 8, 8) connect _WIRE_16.pw, _T_278 node _T_279 = bits(_WIRE_17, 9, 9) connect _WIRE_16.hr, _T_279 node _T_280 = bits(_WIRE_17, 10, 10) connect _WIRE_16.hx, _T_280 node _T_281 = bits(_WIRE_17, 11, 11) connect _WIRE_16.hw, _T_281 node _T_282 = bits(_WIRE_17, 12, 12) connect _WIRE_16.sr, _T_282 node _T_283 = bits(_WIRE_17, 13, 13) connect _WIRE_16.sx, _T_283 node _T_284 = bits(_WIRE_17, 14, 14) connect _WIRE_16.sw, _T_284 node _T_285 = bits(_WIRE_17, 15, 15) connect _WIRE_16.gf, _T_285 node _T_286 = bits(_WIRE_17, 16, 16) connect _WIRE_16.pf, _T_286 node _T_287 = bits(_WIRE_17, 17, 17) connect _WIRE_16.ae_stage2, _T_287 node _T_288 = bits(_WIRE_17, 18, 18) connect _WIRE_16.ae_final, _T_288 node _T_289 = bits(_WIRE_17, 19, 19) connect _WIRE_16.ae_ptw, _T_289 node _T_290 = bits(_WIRE_17, 20, 20) connect _WIRE_16.g, _T_290 node _T_291 = bits(_WIRE_17, 21, 21) connect _WIRE_16.u, _T_291 node _T_292 = bits(_WIRE_17, 41, 22) connect _WIRE_16.ppn, _T_292 node _T_293 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_294 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_295 = and(_T_293, _T_294) when _T_295 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node _T_296 = xor(sectored_entries[0][2].tag_vpn, vpn) node _T_297 = shr(_T_296, 18) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_19 : UInt<42> connect _WIRE_19, sectored_entries[0][2].data[0] node _T_299 = bits(_WIRE_19, 0, 0) connect _WIRE_18.fragmented_superpage, _T_299 node _T_300 = bits(_WIRE_19, 1, 1) connect _WIRE_18.c, _T_300 node _T_301 = bits(_WIRE_19, 2, 2) connect _WIRE_18.eff, _T_301 node _T_302 = bits(_WIRE_19, 3, 3) connect _WIRE_18.paa, _T_302 node _T_303 = bits(_WIRE_19, 4, 4) connect _WIRE_18.pal, _T_303 node _T_304 = bits(_WIRE_19, 5, 5) connect _WIRE_18.ppp, _T_304 node _T_305 = bits(_WIRE_19, 6, 6) connect _WIRE_18.pr, _T_305 node _T_306 = bits(_WIRE_19, 7, 7) connect _WIRE_18.px, _T_306 node _T_307 = bits(_WIRE_19, 8, 8) connect _WIRE_18.pw, _T_307 node _T_308 = bits(_WIRE_19, 9, 9) connect _WIRE_18.hr, _T_308 node _T_309 = bits(_WIRE_19, 10, 10) connect _WIRE_18.hx, _T_309 node _T_310 = bits(_WIRE_19, 11, 11) connect _WIRE_18.hw, _T_310 node _T_311 = bits(_WIRE_19, 12, 12) connect _WIRE_18.sr, _T_311 node _T_312 = bits(_WIRE_19, 13, 13) connect _WIRE_18.sx, _T_312 node _T_313 = bits(_WIRE_19, 14, 14) connect _WIRE_18.sw, _T_313 node _T_314 = bits(_WIRE_19, 15, 15) connect _WIRE_18.gf, _T_314 node _T_315 = bits(_WIRE_19, 16, 16) connect _WIRE_18.pf, _T_315 node _T_316 = bits(_WIRE_19, 17, 17) connect _WIRE_18.ae_stage2, _T_316 node _T_317 = bits(_WIRE_19, 18, 18) connect _WIRE_18.ae_final, _T_317 node _T_318 = bits(_WIRE_19, 19, 19) connect _WIRE_18.ae_ptw, _T_318 node _T_319 = bits(_WIRE_19, 20, 20) connect _WIRE_18.g, _T_319 node _T_320 = bits(_WIRE_19, 21, 21) connect _WIRE_18.u, _T_320 node _T_321 = bits(_WIRE_19, 41, 22) connect _WIRE_18.ppn, _T_321 node _T_322 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_323 = and(_T_322, _WIRE_18.fragmented_superpage) when _T_323 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) else : node _T_324 = eq(hg_2, UInt<1>(0h0)) node _T_325 = and(_T_324, io.sfence.bits.rs2) when _T_325 : wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_21 : UInt<42> connect _WIRE_21, sectored_entries[0][2].data[0] node _T_326 = bits(_WIRE_21, 0, 0) connect _WIRE_20.fragmented_superpage, _T_326 node _T_327 = bits(_WIRE_21, 1, 1) connect _WIRE_20.c, _T_327 node _T_328 = bits(_WIRE_21, 2, 2) connect _WIRE_20.eff, _T_328 node _T_329 = bits(_WIRE_21, 3, 3) connect _WIRE_20.paa, _T_329 node _T_330 = bits(_WIRE_21, 4, 4) connect _WIRE_20.pal, _T_330 node _T_331 = bits(_WIRE_21, 5, 5) connect _WIRE_20.ppp, _T_331 node _T_332 = bits(_WIRE_21, 6, 6) connect _WIRE_20.pr, _T_332 node _T_333 = bits(_WIRE_21, 7, 7) connect _WIRE_20.px, _T_333 node _T_334 = bits(_WIRE_21, 8, 8) connect _WIRE_20.pw, _T_334 node _T_335 = bits(_WIRE_21, 9, 9) connect _WIRE_20.hr, _T_335 node _T_336 = bits(_WIRE_21, 10, 10) connect _WIRE_20.hx, _T_336 node _T_337 = bits(_WIRE_21, 11, 11) connect _WIRE_20.hw, _T_337 node _T_338 = bits(_WIRE_21, 12, 12) connect _WIRE_20.sr, _T_338 node _T_339 = bits(_WIRE_21, 13, 13) connect _WIRE_20.sx, _T_339 node _T_340 = bits(_WIRE_21, 14, 14) connect _WIRE_20.sw, _T_340 node _T_341 = bits(_WIRE_21, 15, 15) connect _WIRE_20.gf, _T_341 node _T_342 = bits(_WIRE_21, 16, 16) connect _WIRE_20.pf, _T_342 node _T_343 = bits(_WIRE_21, 17, 17) connect _WIRE_20.ae_stage2, _T_343 node _T_344 = bits(_WIRE_21, 18, 18) connect _WIRE_20.ae_final, _T_344 node _T_345 = bits(_WIRE_21, 19, 19) connect _WIRE_20.ae_ptw, _T_345 node _T_346 = bits(_WIRE_21, 20, 20) connect _WIRE_20.g, _T_346 node _T_347 = bits(_WIRE_21, 21, 21) connect _WIRE_20.u, _T_347 node _T_348 = bits(_WIRE_21, 41, 22) connect _WIRE_20.ppn, _T_348 node _T_349 = eq(sectored_entries[0][2].tag_v, hv_2) node _T_350 = eq(_WIRE_20.g, UInt<1>(0h0)) node _T_351 = and(_T_349, _T_350) when _T_351 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) else : node _T_352 = or(hv_2, hg_2) wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_23 : UInt<42> connect _WIRE_23, sectored_entries[0][2].data[0] node _T_353 = bits(_WIRE_23, 0, 0) connect _WIRE_22.fragmented_superpage, _T_353 node _T_354 = bits(_WIRE_23, 1, 1) connect _WIRE_22.c, _T_354 node _T_355 = bits(_WIRE_23, 2, 2) connect _WIRE_22.eff, _T_355 node _T_356 = bits(_WIRE_23, 3, 3) connect _WIRE_22.paa, _T_356 node _T_357 = bits(_WIRE_23, 4, 4) connect _WIRE_22.pal, _T_357 node _T_358 = bits(_WIRE_23, 5, 5) connect _WIRE_22.ppp, _T_358 node _T_359 = bits(_WIRE_23, 6, 6) connect _WIRE_22.pr, _T_359 node _T_360 = bits(_WIRE_23, 7, 7) connect _WIRE_22.px, _T_360 node _T_361 = bits(_WIRE_23, 8, 8) connect _WIRE_22.pw, _T_361 node _T_362 = bits(_WIRE_23, 9, 9) connect _WIRE_22.hr, _T_362 node _T_363 = bits(_WIRE_23, 10, 10) connect _WIRE_22.hx, _T_363 node _T_364 = bits(_WIRE_23, 11, 11) connect _WIRE_22.hw, _T_364 node _T_365 = bits(_WIRE_23, 12, 12) connect _WIRE_22.sr, _T_365 node _T_366 = bits(_WIRE_23, 13, 13) connect _WIRE_22.sx, _T_366 node _T_367 = bits(_WIRE_23, 14, 14) connect _WIRE_22.sw, _T_367 node _T_368 = bits(_WIRE_23, 15, 15) connect _WIRE_22.gf, _T_368 node _T_369 = bits(_WIRE_23, 16, 16) connect _WIRE_22.pf, _T_369 node _T_370 = bits(_WIRE_23, 17, 17) connect _WIRE_22.ae_stage2, _T_370 node _T_371 = bits(_WIRE_23, 18, 18) connect _WIRE_22.ae_final, _T_371 node _T_372 = bits(_WIRE_23, 19, 19) connect _WIRE_22.ae_ptw, _T_372 node _T_373 = bits(_WIRE_23, 20, 20) connect _WIRE_22.g, _T_373 node _T_374 = bits(_WIRE_23, 21, 21) connect _WIRE_22.u, _T_374 node _T_375 = bits(_WIRE_23, 41, 22) connect _WIRE_22.ppn, _T_375 node _T_376 = eq(sectored_entries[0][2].tag_v, _T_352) when _T_376 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_377 = eq(hg_3, UInt<1>(0h0)) node _T_378 = and(_T_377, io.sfence.bits.rs1) when _T_378 : node _T_379 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_380 = shr(_T_379, 0) node _T_381 = eq(_T_380, UInt<1>(0h0)) node _T_382 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_383 = and(_T_381, _T_382) when _T_383 : wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_25 : UInt<42> connect _WIRE_25, sectored_entries[0][3].data[0] node _T_384 = bits(_WIRE_25, 0, 0) connect _WIRE_24.fragmented_superpage, _T_384 node _T_385 = bits(_WIRE_25, 1, 1) connect _WIRE_24.c, _T_385 node _T_386 = bits(_WIRE_25, 2, 2) connect _WIRE_24.eff, _T_386 node _T_387 = bits(_WIRE_25, 3, 3) connect _WIRE_24.paa, _T_387 node _T_388 = bits(_WIRE_25, 4, 4) connect _WIRE_24.pal, _T_388 node _T_389 = bits(_WIRE_25, 5, 5) connect _WIRE_24.ppp, _T_389 node _T_390 = bits(_WIRE_25, 6, 6) connect _WIRE_24.pr, _T_390 node _T_391 = bits(_WIRE_25, 7, 7) connect _WIRE_24.px, _T_391 node _T_392 = bits(_WIRE_25, 8, 8) connect _WIRE_24.pw, _T_392 node _T_393 = bits(_WIRE_25, 9, 9) connect _WIRE_24.hr, _T_393 node _T_394 = bits(_WIRE_25, 10, 10) connect _WIRE_24.hx, _T_394 node _T_395 = bits(_WIRE_25, 11, 11) connect _WIRE_24.hw, _T_395 node _T_396 = bits(_WIRE_25, 12, 12) connect _WIRE_24.sr, _T_396 node _T_397 = bits(_WIRE_25, 13, 13) connect _WIRE_24.sx, _T_397 node _T_398 = bits(_WIRE_25, 14, 14) connect _WIRE_24.sw, _T_398 node _T_399 = bits(_WIRE_25, 15, 15) connect _WIRE_24.gf, _T_399 node _T_400 = bits(_WIRE_25, 16, 16) connect _WIRE_24.pf, _T_400 node _T_401 = bits(_WIRE_25, 17, 17) connect _WIRE_24.ae_stage2, _T_401 node _T_402 = bits(_WIRE_25, 18, 18) connect _WIRE_24.ae_final, _T_402 node _T_403 = bits(_WIRE_25, 19, 19) connect _WIRE_24.ae_ptw, _T_403 node _T_404 = bits(_WIRE_25, 20, 20) connect _WIRE_24.g, _T_404 node _T_405 = bits(_WIRE_25, 21, 21) connect _WIRE_24.u, _T_405 node _T_406 = bits(_WIRE_25, 41, 22) connect _WIRE_24.ppn, _T_406 node _T_407 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_408 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_409 = and(_T_407, _T_408) when _T_409 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node _T_410 = xor(sectored_entries[0][3].tag_vpn, vpn) node _T_411 = shr(_T_410, 18) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_27 : UInt<42> connect _WIRE_27, sectored_entries[0][3].data[0] node _T_413 = bits(_WIRE_27, 0, 0) connect _WIRE_26.fragmented_superpage, _T_413 node _T_414 = bits(_WIRE_27, 1, 1) connect _WIRE_26.c, _T_414 node _T_415 = bits(_WIRE_27, 2, 2) connect _WIRE_26.eff, _T_415 node _T_416 = bits(_WIRE_27, 3, 3) connect _WIRE_26.paa, _T_416 node _T_417 = bits(_WIRE_27, 4, 4) connect _WIRE_26.pal, _T_417 node _T_418 = bits(_WIRE_27, 5, 5) connect _WIRE_26.ppp, _T_418 node _T_419 = bits(_WIRE_27, 6, 6) connect _WIRE_26.pr, _T_419 node _T_420 = bits(_WIRE_27, 7, 7) connect _WIRE_26.px, _T_420 node _T_421 = bits(_WIRE_27, 8, 8) connect _WIRE_26.pw, _T_421 node _T_422 = bits(_WIRE_27, 9, 9) connect _WIRE_26.hr, _T_422 node _T_423 = bits(_WIRE_27, 10, 10) connect _WIRE_26.hx, _T_423 node _T_424 = bits(_WIRE_27, 11, 11) connect _WIRE_26.hw, _T_424 node _T_425 = bits(_WIRE_27, 12, 12) connect _WIRE_26.sr, _T_425 node _T_426 = bits(_WIRE_27, 13, 13) connect _WIRE_26.sx, _T_426 node _T_427 = bits(_WIRE_27, 14, 14) connect _WIRE_26.sw, _T_427 node _T_428 = bits(_WIRE_27, 15, 15) connect _WIRE_26.gf, _T_428 node _T_429 = bits(_WIRE_27, 16, 16) connect _WIRE_26.pf, _T_429 node _T_430 = bits(_WIRE_27, 17, 17) connect _WIRE_26.ae_stage2, _T_430 node _T_431 = bits(_WIRE_27, 18, 18) connect _WIRE_26.ae_final, _T_431 node _T_432 = bits(_WIRE_27, 19, 19) connect _WIRE_26.ae_ptw, _T_432 node _T_433 = bits(_WIRE_27, 20, 20) connect _WIRE_26.g, _T_433 node _T_434 = bits(_WIRE_27, 21, 21) connect _WIRE_26.u, _T_434 node _T_435 = bits(_WIRE_27, 41, 22) connect _WIRE_26.ppn, _T_435 node _T_436 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_437 = and(_T_436, _WIRE_26.fragmented_superpage) when _T_437 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) else : node _T_438 = eq(hg_3, UInt<1>(0h0)) node _T_439 = and(_T_438, io.sfence.bits.rs2) when _T_439 : wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_29 : UInt<42> connect _WIRE_29, sectored_entries[0][3].data[0] node _T_440 = bits(_WIRE_29, 0, 0) connect _WIRE_28.fragmented_superpage, _T_440 node _T_441 = bits(_WIRE_29, 1, 1) connect _WIRE_28.c, _T_441 node _T_442 = bits(_WIRE_29, 2, 2) connect _WIRE_28.eff, _T_442 node _T_443 = bits(_WIRE_29, 3, 3) connect _WIRE_28.paa, _T_443 node _T_444 = bits(_WIRE_29, 4, 4) connect _WIRE_28.pal, _T_444 node _T_445 = bits(_WIRE_29, 5, 5) connect _WIRE_28.ppp, _T_445 node _T_446 = bits(_WIRE_29, 6, 6) connect _WIRE_28.pr, _T_446 node _T_447 = bits(_WIRE_29, 7, 7) connect _WIRE_28.px, _T_447 node _T_448 = bits(_WIRE_29, 8, 8) connect _WIRE_28.pw, _T_448 node _T_449 = bits(_WIRE_29, 9, 9) connect _WIRE_28.hr, _T_449 node _T_450 = bits(_WIRE_29, 10, 10) connect _WIRE_28.hx, _T_450 node _T_451 = bits(_WIRE_29, 11, 11) connect _WIRE_28.hw, _T_451 node _T_452 = bits(_WIRE_29, 12, 12) connect _WIRE_28.sr, _T_452 node _T_453 = bits(_WIRE_29, 13, 13) connect _WIRE_28.sx, _T_453 node _T_454 = bits(_WIRE_29, 14, 14) connect _WIRE_28.sw, _T_454 node _T_455 = bits(_WIRE_29, 15, 15) connect _WIRE_28.gf, _T_455 node _T_456 = bits(_WIRE_29, 16, 16) connect _WIRE_28.pf, _T_456 node _T_457 = bits(_WIRE_29, 17, 17) connect _WIRE_28.ae_stage2, _T_457 node _T_458 = bits(_WIRE_29, 18, 18) connect _WIRE_28.ae_final, _T_458 node _T_459 = bits(_WIRE_29, 19, 19) connect _WIRE_28.ae_ptw, _T_459 node _T_460 = bits(_WIRE_29, 20, 20) connect _WIRE_28.g, _T_460 node _T_461 = bits(_WIRE_29, 21, 21) connect _WIRE_28.u, _T_461 node _T_462 = bits(_WIRE_29, 41, 22) connect _WIRE_28.ppn, _T_462 node _T_463 = eq(sectored_entries[0][3].tag_v, hv_3) node _T_464 = eq(_WIRE_28.g, UInt<1>(0h0)) node _T_465 = and(_T_463, _T_464) when _T_465 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) else : node _T_466 = or(hv_3, hg_3) wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_31 : UInt<42> connect _WIRE_31, sectored_entries[0][3].data[0] node _T_467 = bits(_WIRE_31, 0, 0) connect _WIRE_30.fragmented_superpage, _T_467 node _T_468 = bits(_WIRE_31, 1, 1) connect _WIRE_30.c, _T_468 node _T_469 = bits(_WIRE_31, 2, 2) connect _WIRE_30.eff, _T_469 node _T_470 = bits(_WIRE_31, 3, 3) connect _WIRE_30.paa, _T_470 node _T_471 = bits(_WIRE_31, 4, 4) connect _WIRE_30.pal, _T_471 node _T_472 = bits(_WIRE_31, 5, 5) connect _WIRE_30.ppp, _T_472 node _T_473 = bits(_WIRE_31, 6, 6) connect _WIRE_30.pr, _T_473 node _T_474 = bits(_WIRE_31, 7, 7) connect _WIRE_30.px, _T_474 node _T_475 = bits(_WIRE_31, 8, 8) connect _WIRE_30.pw, _T_475 node _T_476 = bits(_WIRE_31, 9, 9) connect _WIRE_30.hr, _T_476 node _T_477 = bits(_WIRE_31, 10, 10) connect _WIRE_30.hx, _T_477 node _T_478 = bits(_WIRE_31, 11, 11) connect _WIRE_30.hw, _T_478 node _T_479 = bits(_WIRE_31, 12, 12) connect _WIRE_30.sr, _T_479 node _T_480 = bits(_WIRE_31, 13, 13) connect _WIRE_30.sx, _T_480 node _T_481 = bits(_WIRE_31, 14, 14) connect _WIRE_30.sw, _T_481 node _T_482 = bits(_WIRE_31, 15, 15) connect _WIRE_30.gf, _T_482 node _T_483 = bits(_WIRE_31, 16, 16) connect _WIRE_30.pf, _T_483 node _T_484 = bits(_WIRE_31, 17, 17) connect _WIRE_30.ae_stage2, _T_484 node _T_485 = bits(_WIRE_31, 18, 18) connect _WIRE_30.ae_final, _T_485 node _T_486 = bits(_WIRE_31, 19, 19) connect _WIRE_30.ae_ptw, _T_486 node _T_487 = bits(_WIRE_31, 20, 20) connect _WIRE_30.g, _T_487 node _T_488 = bits(_WIRE_31, 21, 21) connect _WIRE_30.u, _T_488 node _T_489 = bits(_WIRE_31, 41, 22) connect _WIRE_30.ppn, _T_489 node _T_490 = eq(sectored_entries[0][3].tag_v, _T_466) when _T_490 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_491 = eq(hg_4, UInt<1>(0h0)) node _T_492 = and(_T_491, io.sfence.bits.rs1) when _T_492 : node _T_493 = xor(sectored_entries[1][0].tag_vpn, vpn) node _T_494 = shr(_T_493, 0) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_497 = and(_T_495, _T_496) when _T_497 : wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_33 : UInt<42> connect _WIRE_33, sectored_entries[1][0].data[0] node _T_498 = bits(_WIRE_33, 0, 0) connect _WIRE_32.fragmented_superpage, _T_498 node _T_499 = bits(_WIRE_33, 1, 1) connect _WIRE_32.c, _T_499 node _T_500 = bits(_WIRE_33, 2, 2) connect _WIRE_32.eff, _T_500 node _T_501 = bits(_WIRE_33, 3, 3) connect _WIRE_32.paa, _T_501 node _T_502 = bits(_WIRE_33, 4, 4) connect _WIRE_32.pal, _T_502 node _T_503 = bits(_WIRE_33, 5, 5) connect _WIRE_32.ppp, _T_503 node _T_504 = bits(_WIRE_33, 6, 6) connect _WIRE_32.pr, _T_504 node _T_505 = bits(_WIRE_33, 7, 7) connect _WIRE_32.px, _T_505 node _T_506 = bits(_WIRE_33, 8, 8) connect _WIRE_32.pw, _T_506 node _T_507 = bits(_WIRE_33, 9, 9) connect _WIRE_32.hr, _T_507 node _T_508 = bits(_WIRE_33, 10, 10) connect _WIRE_32.hx, _T_508 node _T_509 = bits(_WIRE_33, 11, 11) connect _WIRE_32.hw, _T_509 node _T_510 = bits(_WIRE_33, 12, 12) connect _WIRE_32.sr, _T_510 node _T_511 = bits(_WIRE_33, 13, 13) connect _WIRE_32.sx, _T_511 node _T_512 = bits(_WIRE_33, 14, 14) connect _WIRE_32.sw, _T_512 node _T_513 = bits(_WIRE_33, 15, 15) connect _WIRE_32.gf, _T_513 node _T_514 = bits(_WIRE_33, 16, 16) connect _WIRE_32.pf, _T_514 node _T_515 = bits(_WIRE_33, 17, 17) connect _WIRE_32.ae_stage2, _T_515 node _T_516 = bits(_WIRE_33, 18, 18) connect _WIRE_32.ae_final, _T_516 node _T_517 = bits(_WIRE_33, 19, 19) connect _WIRE_32.ae_ptw, _T_517 node _T_518 = bits(_WIRE_33, 20, 20) connect _WIRE_32.g, _T_518 node _T_519 = bits(_WIRE_33, 21, 21) connect _WIRE_32.u, _T_519 node _T_520 = bits(_WIRE_33, 41, 22) connect _WIRE_32.ppn, _T_520 node _T_521 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_522 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_523 = and(_T_521, _T_522) when _T_523 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) node _T_524 = xor(sectored_entries[1][0].tag_vpn, vpn) node _T_525 = shr(_T_524, 18) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_35 : UInt<42> connect _WIRE_35, sectored_entries[1][0].data[0] node _T_527 = bits(_WIRE_35, 0, 0) connect _WIRE_34.fragmented_superpage, _T_527 node _T_528 = bits(_WIRE_35, 1, 1) connect _WIRE_34.c, _T_528 node _T_529 = bits(_WIRE_35, 2, 2) connect _WIRE_34.eff, _T_529 node _T_530 = bits(_WIRE_35, 3, 3) connect _WIRE_34.paa, _T_530 node _T_531 = bits(_WIRE_35, 4, 4) connect _WIRE_34.pal, _T_531 node _T_532 = bits(_WIRE_35, 5, 5) connect _WIRE_34.ppp, _T_532 node _T_533 = bits(_WIRE_35, 6, 6) connect _WIRE_34.pr, _T_533 node _T_534 = bits(_WIRE_35, 7, 7) connect _WIRE_34.px, _T_534 node _T_535 = bits(_WIRE_35, 8, 8) connect _WIRE_34.pw, _T_535 node _T_536 = bits(_WIRE_35, 9, 9) connect _WIRE_34.hr, _T_536 node _T_537 = bits(_WIRE_35, 10, 10) connect _WIRE_34.hx, _T_537 node _T_538 = bits(_WIRE_35, 11, 11) connect _WIRE_34.hw, _T_538 node _T_539 = bits(_WIRE_35, 12, 12) connect _WIRE_34.sr, _T_539 node _T_540 = bits(_WIRE_35, 13, 13) connect _WIRE_34.sx, _T_540 node _T_541 = bits(_WIRE_35, 14, 14) connect _WIRE_34.sw, _T_541 node _T_542 = bits(_WIRE_35, 15, 15) connect _WIRE_34.gf, _T_542 node _T_543 = bits(_WIRE_35, 16, 16) connect _WIRE_34.pf, _T_543 node _T_544 = bits(_WIRE_35, 17, 17) connect _WIRE_34.ae_stage2, _T_544 node _T_545 = bits(_WIRE_35, 18, 18) connect _WIRE_34.ae_final, _T_545 node _T_546 = bits(_WIRE_35, 19, 19) connect _WIRE_34.ae_ptw, _T_546 node _T_547 = bits(_WIRE_35, 20, 20) connect _WIRE_34.g, _T_547 node _T_548 = bits(_WIRE_35, 21, 21) connect _WIRE_34.u, _T_548 node _T_549 = bits(_WIRE_35, 41, 22) connect _WIRE_34.ppn, _T_549 node _T_550 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_551 = and(_T_550, _WIRE_34.fragmented_superpage) when _T_551 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) else : node _T_552 = eq(hg_4, UInt<1>(0h0)) node _T_553 = and(_T_552, io.sfence.bits.rs2) when _T_553 : wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_37 : UInt<42> connect _WIRE_37, sectored_entries[1][0].data[0] node _T_554 = bits(_WIRE_37, 0, 0) connect _WIRE_36.fragmented_superpage, _T_554 node _T_555 = bits(_WIRE_37, 1, 1) connect _WIRE_36.c, _T_555 node _T_556 = bits(_WIRE_37, 2, 2) connect _WIRE_36.eff, _T_556 node _T_557 = bits(_WIRE_37, 3, 3) connect _WIRE_36.paa, _T_557 node _T_558 = bits(_WIRE_37, 4, 4) connect _WIRE_36.pal, _T_558 node _T_559 = bits(_WIRE_37, 5, 5) connect _WIRE_36.ppp, _T_559 node _T_560 = bits(_WIRE_37, 6, 6) connect _WIRE_36.pr, _T_560 node _T_561 = bits(_WIRE_37, 7, 7) connect _WIRE_36.px, _T_561 node _T_562 = bits(_WIRE_37, 8, 8) connect _WIRE_36.pw, _T_562 node _T_563 = bits(_WIRE_37, 9, 9) connect _WIRE_36.hr, _T_563 node _T_564 = bits(_WIRE_37, 10, 10) connect _WIRE_36.hx, _T_564 node _T_565 = bits(_WIRE_37, 11, 11) connect _WIRE_36.hw, _T_565 node _T_566 = bits(_WIRE_37, 12, 12) connect _WIRE_36.sr, _T_566 node _T_567 = bits(_WIRE_37, 13, 13) connect _WIRE_36.sx, _T_567 node _T_568 = bits(_WIRE_37, 14, 14) connect _WIRE_36.sw, _T_568 node _T_569 = bits(_WIRE_37, 15, 15) connect _WIRE_36.gf, _T_569 node _T_570 = bits(_WIRE_37, 16, 16) connect _WIRE_36.pf, _T_570 node _T_571 = bits(_WIRE_37, 17, 17) connect _WIRE_36.ae_stage2, _T_571 node _T_572 = bits(_WIRE_37, 18, 18) connect _WIRE_36.ae_final, _T_572 node _T_573 = bits(_WIRE_37, 19, 19) connect _WIRE_36.ae_ptw, _T_573 node _T_574 = bits(_WIRE_37, 20, 20) connect _WIRE_36.g, _T_574 node _T_575 = bits(_WIRE_37, 21, 21) connect _WIRE_36.u, _T_575 node _T_576 = bits(_WIRE_37, 41, 22) connect _WIRE_36.ppn, _T_576 node _T_577 = eq(sectored_entries[1][0].tag_v, hv_4) node _T_578 = eq(_WIRE_36.g, UInt<1>(0h0)) node _T_579 = and(_T_577, _T_578) when _T_579 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) else : node _T_580 = or(hv_4, hg_4) wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_39 : UInt<42> connect _WIRE_39, sectored_entries[1][0].data[0] node _T_581 = bits(_WIRE_39, 0, 0) connect _WIRE_38.fragmented_superpage, _T_581 node _T_582 = bits(_WIRE_39, 1, 1) connect _WIRE_38.c, _T_582 node _T_583 = bits(_WIRE_39, 2, 2) connect _WIRE_38.eff, _T_583 node _T_584 = bits(_WIRE_39, 3, 3) connect _WIRE_38.paa, _T_584 node _T_585 = bits(_WIRE_39, 4, 4) connect _WIRE_38.pal, _T_585 node _T_586 = bits(_WIRE_39, 5, 5) connect _WIRE_38.ppp, _T_586 node _T_587 = bits(_WIRE_39, 6, 6) connect _WIRE_38.pr, _T_587 node _T_588 = bits(_WIRE_39, 7, 7) connect _WIRE_38.px, _T_588 node _T_589 = bits(_WIRE_39, 8, 8) connect _WIRE_38.pw, _T_589 node _T_590 = bits(_WIRE_39, 9, 9) connect _WIRE_38.hr, _T_590 node _T_591 = bits(_WIRE_39, 10, 10) connect _WIRE_38.hx, _T_591 node _T_592 = bits(_WIRE_39, 11, 11) connect _WIRE_38.hw, _T_592 node _T_593 = bits(_WIRE_39, 12, 12) connect _WIRE_38.sr, _T_593 node _T_594 = bits(_WIRE_39, 13, 13) connect _WIRE_38.sx, _T_594 node _T_595 = bits(_WIRE_39, 14, 14) connect _WIRE_38.sw, _T_595 node _T_596 = bits(_WIRE_39, 15, 15) connect _WIRE_38.gf, _T_596 node _T_597 = bits(_WIRE_39, 16, 16) connect _WIRE_38.pf, _T_597 node _T_598 = bits(_WIRE_39, 17, 17) connect _WIRE_38.ae_stage2, _T_598 node _T_599 = bits(_WIRE_39, 18, 18) connect _WIRE_38.ae_final, _T_599 node _T_600 = bits(_WIRE_39, 19, 19) connect _WIRE_38.ae_ptw, _T_600 node _T_601 = bits(_WIRE_39, 20, 20) connect _WIRE_38.g, _T_601 node _T_602 = bits(_WIRE_39, 21, 21) connect _WIRE_38.u, _T_602 node _T_603 = bits(_WIRE_39, 41, 22) connect _WIRE_38.ppn, _T_603 node _T_604 = eq(sectored_entries[1][0].tag_v, _T_580) when _T_604 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_605 = eq(hg_5, UInt<1>(0h0)) node _T_606 = and(_T_605, io.sfence.bits.rs1) when _T_606 : node _T_607 = xor(sectored_entries[1][1].tag_vpn, vpn) node _T_608 = shr(_T_607, 0) node _T_609 = eq(_T_608, UInt<1>(0h0)) node _T_610 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_611 = and(_T_609, _T_610) when _T_611 : wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_41 : UInt<42> connect _WIRE_41, sectored_entries[1][1].data[0] node _T_612 = bits(_WIRE_41, 0, 0) connect _WIRE_40.fragmented_superpage, _T_612 node _T_613 = bits(_WIRE_41, 1, 1) connect _WIRE_40.c, _T_613 node _T_614 = bits(_WIRE_41, 2, 2) connect _WIRE_40.eff, _T_614 node _T_615 = bits(_WIRE_41, 3, 3) connect _WIRE_40.paa, _T_615 node _T_616 = bits(_WIRE_41, 4, 4) connect _WIRE_40.pal, _T_616 node _T_617 = bits(_WIRE_41, 5, 5) connect _WIRE_40.ppp, _T_617 node _T_618 = bits(_WIRE_41, 6, 6) connect _WIRE_40.pr, _T_618 node _T_619 = bits(_WIRE_41, 7, 7) connect _WIRE_40.px, _T_619 node _T_620 = bits(_WIRE_41, 8, 8) connect _WIRE_40.pw, _T_620 node _T_621 = bits(_WIRE_41, 9, 9) connect _WIRE_40.hr, _T_621 node _T_622 = bits(_WIRE_41, 10, 10) connect _WIRE_40.hx, _T_622 node _T_623 = bits(_WIRE_41, 11, 11) connect _WIRE_40.hw, _T_623 node _T_624 = bits(_WIRE_41, 12, 12) connect _WIRE_40.sr, _T_624 node _T_625 = bits(_WIRE_41, 13, 13) connect _WIRE_40.sx, _T_625 node _T_626 = bits(_WIRE_41, 14, 14) connect _WIRE_40.sw, _T_626 node _T_627 = bits(_WIRE_41, 15, 15) connect _WIRE_40.gf, _T_627 node _T_628 = bits(_WIRE_41, 16, 16) connect _WIRE_40.pf, _T_628 node _T_629 = bits(_WIRE_41, 17, 17) connect _WIRE_40.ae_stage2, _T_629 node _T_630 = bits(_WIRE_41, 18, 18) connect _WIRE_40.ae_final, _T_630 node _T_631 = bits(_WIRE_41, 19, 19) connect _WIRE_40.ae_ptw, _T_631 node _T_632 = bits(_WIRE_41, 20, 20) connect _WIRE_40.g, _T_632 node _T_633 = bits(_WIRE_41, 21, 21) connect _WIRE_40.u, _T_633 node _T_634 = bits(_WIRE_41, 41, 22) connect _WIRE_40.ppn, _T_634 node _T_635 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_636 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_637 = and(_T_635, _T_636) when _T_637 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) node _T_638 = xor(sectored_entries[1][1].tag_vpn, vpn) node _T_639 = shr(_T_638, 18) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_43 : UInt<42> connect _WIRE_43, sectored_entries[1][1].data[0] node _T_641 = bits(_WIRE_43, 0, 0) connect _WIRE_42.fragmented_superpage, _T_641 node _T_642 = bits(_WIRE_43, 1, 1) connect _WIRE_42.c, _T_642 node _T_643 = bits(_WIRE_43, 2, 2) connect _WIRE_42.eff, _T_643 node _T_644 = bits(_WIRE_43, 3, 3) connect _WIRE_42.paa, _T_644 node _T_645 = bits(_WIRE_43, 4, 4) connect _WIRE_42.pal, _T_645 node _T_646 = bits(_WIRE_43, 5, 5) connect _WIRE_42.ppp, _T_646 node _T_647 = bits(_WIRE_43, 6, 6) connect _WIRE_42.pr, _T_647 node _T_648 = bits(_WIRE_43, 7, 7) connect _WIRE_42.px, _T_648 node _T_649 = bits(_WIRE_43, 8, 8) connect _WIRE_42.pw, _T_649 node _T_650 = bits(_WIRE_43, 9, 9) connect _WIRE_42.hr, _T_650 node _T_651 = bits(_WIRE_43, 10, 10) connect _WIRE_42.hx, _T_651 node _T_652 = bits(_WIRE_43, 11, 11) connect _WIRE_42.hw, _T_652 node _T_653 = bits(_WIRE_43, 12, 12) connect _WIRE_42.sr, _T_653 node _T_654 = bits(_WIRE_43, 13, 13) connect _WIRE_42.sx, _T_654 node _T_655 = bits(_WIRE_43, 14, 14) connect _WIRE_42.sw, _T_655 node _T_656 = bits(_WIRE_43, 15, 15) connect _WIRE_42.gf, _T_656 node _T_657 = bits(_WIRE_43, 16, 16) connect _WIRE_42.pf, _T_657 node _T_658 = bits(_WIRE_43, 17, 17) connect _WIRE_42.ae_stage2, _T_658 node _T_659 = bits(_WIRE_43, 18, 18) connect _WIRE_42.ae_final, _T_659 node _T_660 = bits(_WIRE_43, 19, 19) connect _WIRE_42.ae_ptw, _T_660 node _T_661 = bits(_WIRE_43, 20, 20) connect _WIRE_42.g, _T_661 node _T_662 = bits(_WIRE_43, 21, 21) connect _WIRE_42.u, _T_662 node _T_663 = bits(_WIRE_43, 41, 22) connect _WIRE_42.ppn, _T_663 node _T_664 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_665 = and(_T_664, _WIRE_42.fragmented_superpage) when _T_665 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) else : node _T_666 = eq(hg_5, UInt<1>(0h0)) node _T_667 = and(_T_666, io.sfence.bits.rs2) when _T_667 : wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_45 : UInt<42> connect _WIRE_45, sectored_entries[1][1].data[0] node _T_668 = bits(_WIRE_45, 0, 0) connect _WIRE_44.fragmented_superpage, _T_668 node _T_669 = bits(_WIRE_45, 1, 1) connect _WIRE_44.c, _T_669 node _T_670 = bits(_WIRE_45, 2, 2) connect _WIRE_44.eff, _T_670 node _T_671 = bits(_WIRE_45, 3, 3) connect _WIRE_44.paa, _T_671 node _T_672 = bits(_WIRE_45, 4, 4) connect _WIRE_44.pal, _T_672 node _T_673 = bits(_WIRE_45, 5, 5) connect _WIRE_44.ppp, _T_673 node _T_674 = bits(_WIRE_45, 6, 6) connect _WIRE_44.pr, _T_674 node _T_675 = bits(_WIRE_45, 7, 7) connect _WIRE_44.px, _T_675 node _T_676 = bits(_WIRE_45, 8, 8) connect _WIRE_44.pw, _T_676 node _T_677 = bits(_WIRE_45, 9, 9) connect _WIRE_44.hr, _T_677 node _T_678 = bits(_WIRE_45, 10, 10) connect _WIRE_44.hx, _T_678 node _T_679 = bits(_WIRE_45, 11, 11) connect _WIRE_44.hw, _T_679 node _T_680 = bits(_WIRE_45, 12, 12) connect _WIRE_44.sr, _T_680 node _T_681 = bits(_WIRE_45, 13, 13) connect _WIRE_44.sx, _T_681 node _T_682 = bits(_WIRE_45, 14, 14) connect _WIRE_44.sw, _T_682 node _T_683 = bits(_WIRE_45, 15, 15) connect _WIRE_44.gf, _T_683 node _T_684 = bits(_WIRE_45, 16, 16) connect _WIRE_44.pf, _T_684 node _T_685 = bits(_WIRE_45, 17, 17) connect _WIRE_44.ae_stage2, _T_685 node _T_686 = bits(_WIRE_45, 18, 18) connect _WIRE_44.ae_final, _T_686 node _T_687 = bits(_WIRE_45, 19, 19) connect _WIRE_44.ae_ptw, _T_687 node _T_688 = bits(_WIRE_45, 20, 20) connect _WIRE_44.g, _T_688 node _T_689 = bits(_WIRE_45, 21, 21) connect _WIRE_44.u, _T_689 node _T_690 = bits(_WIRE_45, 41, 22) connect _WIRE_44.ppn, _T_690 node _T_691 = eq(sectored_entries[1][1].tag_v, hv_5) node _T_692 = eq(_WIRE_44.g, UInt<1>(0h0)) node _T_693 = and(_T_691, _T_692) when _T_693 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) else : node _T_694 = or(hv_5, hg_5) wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_47 : UInt<42> connect _WIRE_47, sectored_entries[1][1].data[0] node _T_695 = bits(_WIRE_47, 0, 0) connect _WIRE_46.fragmented_superpage, _T_695 node _T_696 = bits(_WIRE_47, 1, 1) connect _WIRE_46.c, _T_696 node _T_697 = bits(_WIRE_47, 2, 2) connect _WIRE_46.eff, _T_697 node _T_698 = bits(_WIRE_47, 3, 3) connect _WIRE_46.paa, _T_698 node _T_699 = bits(_WIRE_47, 4, 4) connect _WIRE_46.pal, _T_699 node _T_700 = bits(_WIRE_47, 5, 5) connect _WIRE_46.ppp, _T_700 node _T_701 = bits(_WIRE_47, 6, 6) connect _WIRE_46.pr, _T_701 node _T_702 = bits(_WIRE_47, 7, 7) connect _WIRE_46.px, _T_702 node _T_703 = bits(_WIRE_47, 8, 8) connect _WIRE_46.pw, _T_703 node _T_704 = bits(_WIRE_47, 9, 9) connect _WIRE_46.hr, _T_704 node _T_705 = bits(_WIRE_47, 10, 10) connect _WIRE_46.hx, _T_705 node _T_706 = bits(_WIRE_47, 11, 11) connect _WIRE_46.hw, _T_706 node _T_707 = bits(_WIRE_47, 12, 12) connect _WIRE_46.sr, _T_707 node _T_708 = bits(_WIRE_47, 13, 13) connect _WIRE_46.sx, _T_708 node _T_709 = bits(_WIRE_47, 14, 14) connect _WIRE_46.sw, _T_709 node _T_710 = bits(_WIRE_47, 15, 15) connect _WIRE_46.gf, _T_710 node _T_711 = bits(_WIRE_47, 16, 16) connect _WIRE_46.pf, _T_711 node _T_712 = bits(_WIRE_47, 17, 17) connect _WIRE_46.ae_stage2, _T_712 node _T_713 = bits(_WIRE_47, 18, 18) connect _WIRE_46.ae_final, _T_713 node _T_714 = bits(_WIRE_47, 19, 19) connect _WIRE_46.ae_ptw, _T_714 node _T_715 = bits(_WIRE_47, 20, 20) connect _WIRE_46.g, _T_715 node _T_716 = bits(_WIRE_47, 21, 21) connect _WIRE_46.u, _T_716 node _T_717 = bits(_WIRE_47, 41, 22) connect _WIRE_46.ppn, _T_717 node _T_718 = eq(sectored_entries[1][1].tag_v, _T_694) when _T_718 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_719 = eq(hg_6, UInt<1>(0h0)) node _T_720 = and(_T_719, io.sfence.bits.rs1) when _T_720 : node _T_721 = xor(sectored_entries[1][2].tag_vpn, vpn) node _T_722 = shr(_T_721, 0) node _T_723 = eq(_T_722, UInt<1>(0h0)) node _T_724 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_725 = and(_T_723, _T_724) when _T_725 : wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_49 : UInt<42> connect _WIRE_49, sectored_entries[1][2].data[0] node _T_726 = bits(_WIRE_49, 0, 0) connect _WIRE_48.fragmented_superpage, _T_726 node _T_727 = bits(_WIRE_49, 1, 1) connect _WIRE_48.c, _T_727 node _T_728 = bits(_WIRE_49, 2, 2) connect _WIRE_48.eff, _T_728 node _T_729 = bits(_WIRE_49, 3, 3) connect _WIRE_48.paa, _T_729 node _T_730 = bits(_WIRE_49, 4, 4) connect _WIRE_48.pal, _T_730 node _T_731 = bits(_WIRE_49, 5, 5) connect _WIRE_48.ppp, _T_731 node _T_732 = bits(_WIRE_49, 6, 6) connect _WIRE_48.pr, _T_732 node _T_733 = bits(_WIRE_49, 7, 7) connect _WIRE_48.px, _T_733 node _T_734 = bits(_WIRE_49, 8, 8) connect _WIRE_48.pw, _T_734 node _T_735 = bits(_WIRE_49, 9, 9) connect _WIRE_48.hr, _T_735 node _T_736 = bits(_WIRE_49, 10, 10) connect _WIRE_48.hx, _T_736 node _T_737 = bits(_WIRE_49, 11, 11) connect _WIRE_48.hw, _T_737 node _T_738 = bits(_WIRE_49, 12, 12) connect _WIRE_48.sr, _T_738 node _T_739 = bits(_WIRE_49, 13, 13) connect _WIRE_48.sx, _T_739 node _T_740 = bits(_WIRE_49, 14, 14) connect _WIRE_48.sw, _T_740 node _T_741 = bits(_WIRE_49, 15, 15) connect _WIRE_48.gf, _T_741 node _T_742 = bits(_WIRE_49, 16, 16) connect _WIRE_48.pf, _T_742 node _T_743 = bits(_WIRE_49, 17, 17) connect _WIRE_48.ae_stage2, _T_743 node _T_744 = bits(_WIRE_49, 18, 18) connect _WIRE_48.ae_final, _T_744 node _T_745 = bits(_WIRE_49, 19, 19) connect _WIRE_48.ae_ptw, _T_745 node _T_746 = bits(_WIRE_49, 20, 20) connect _WIRE_48.g, _T_746 node _T_747 = bits(_WIRE_49, 21, 21) connect _WIRE_48.u, _T_747 node _T_748 = bits(_WIRE_49, 41, 22) connect _WIRE_48.ppn, _T_748 node _T_749 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_750 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_751 = and(_T_749, _T_750) when _T_751 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) node _T_752 = xor(sectored_entries[1][2].tag_vpn, vpn) node _T_753 = shr(_T_752, 18) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_51 : UInt<42> connect _WIRE_51, sectored_entries[1][2].data[0] node _T_755 = bits(_WIRE_51, 0, 0) connect _WIRE_50.fragmented_superpage, _T_755 node _T_756 = bits(_WIRE_51, 1, 1) connect _WIRE_50.c, _T_756 node _T_757 = bits(_WIRE_51, 2, 2) connect _WIRE_50.eff, _T_757 node _T_758 = bits(_WIRE_51, 3, 3) connect _WIRE_50.paa, _T_758 node _T_759 = bits(_WIRE_51, 4, 4) connect _WIRE_50.pal, _T_759 node _T_760 = bits(_WIRE_51, 5, 5) connect _WIRE_50.ppp, _T_760 node _T_761 = bits(_WIRE_51, 6, 6) connect _WIRE_50.pr, _T_761 node _T_762 = bits(_WIRE_51, 7, 7) connect _WIRE_50.px, _T_762 node _T_763 = bits(_WIRE_51, 8, 8) connect _WIRE_50.pw, _T_763 node _T_764 = bits(_WIRE_51, 9, 9) connect _WIRE_50.hr, _T_764 node _T_765 = bits(_WIRE_51, 10, 10) connect _WIRE_50.hx, _T_765 node _T_766 = bits(_WIRE_51, 11, 11) connect _WIRE_50.hw, _T_766 node _T_767 = bits(_WIRE_51, 12, 12) connect _WIRE_50.sr, _T_767 node _T_768 = bits(_WIRE_51, 13, 13) connect _WIRE_50.sx, _T_768 node _T_769 = bits(_WIRE_51, 14, 14) connect _WIRE_50.sw, _T_769 node _T_770 = bits(_WIRE_51, 15, 15) connect _WIRE_50.gf, _T_770 node _T_771 = bits(_WIRE_51, 16, 16) connect _WIRE_50.pf, _T_771 node _T_772 = bits(_WIRE_51, 17, 17) connect _WIRE_50.ae_stage2, _T_772 node _T_773 = bits(_WIRE_51, 18, 18) connect _WIRE_50.ae_final, _T_773 node _T_774 = bits(_WIRE_51, 19, 19) connect _WIRE_50.ae_ptw, _T_774 node _T_775 = bits(_WIRE_51, 20, 20) connect _WIRE_50.g, _T_775 node _T_776 = bits(_WIRE_51, 21, 21) connect _WIRE_50.u, _T_776 node _T_777 = bits(_WIRE_51, 41, 22) connect _WIRE_50.ppn, _T_777 node _T_778 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_779 = and(_T_778, _WIRE_50.fragmented_superpage) when _T_779 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) else : node _T_780 = eq(hg_6, UInt<1>(0h0)) node _T_781 = and(_T_780, io.sfence.bits.rs2) when _T_781 : wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_53 : UInt<42> connect _WIRE_53, sectored_entries[1][2].data[0] node _T_782 = bits(_WIRE_53, 0, 0) connect _WIRE_52.fragmented_superpage, _T_782 node _T_783 = bits(_WIRE_53, 1, 1) connect _WIRE_52.c, _T_783 node _T_784 = bits(_WIRE_53, 2, 2) connect _WIRE_52.eff, _T_784 node _T_785 = bits(_WIRE_53, 3, 3) connect _WIRE_52.paa, _T_785 node _T_786 = bits(_WIRE_53, 4, 4) connect _WIRE_52.pal, _T_786 node _T_787 = bits(_WIRE_53, 5, 5) connect _WIRE_52.ppp, _T_787 node _T_788 = bits(_WIRE_53, 6, 6) connect _WIRE_52.pr, _T_788 node _T_789 = bits(_WIRE_53, 7, 7) connect _WIRE_52.px, _T_789 node _T_790 = bits(_WIRE_53, 8, 8) connect _WIRE_52.pw, _T_790 node _T_791 = bits(_WIRE_53, 9, 9) connect _WIRE_52.hr, _T_791 node _T_792 = bits(_WIRE_53, 10, 10) connect _WIRE_52.hx, _T_792 node _T_793 = bits(_WIRE_53, 11, 11) connect _WIRE_52.hw, _T_793 node _T_794 = bits(_WIRE_53, 12, 12) connect _WIRE_52.sr, _T_794 node _T_795 = bits(_WIRE_53, 13, 13) connect _WIRE_52.sx, _T_795 node _T_796 = bits(_WIRE_53, 14, 14) connect _WIRE_52.sw, _T_796 node _T_797 = bits(_WIRE_53, 15, 15) connect _WIRE_52.gf, _T_797 node _T_798 = bits(_WIRE_53, 16, 16) connect _WIRE_52.pf, _T_798 node _T_799 = bits(_WIRE_53, 17, 17) connect _WIRE_52.ae_stage2, _T_799 node _T_800 = bits(_WIRE_53, 18, 18) connect _WIRE_52.ae_final, _T_800 node _T_801 = bits(_WIRE_53, 19, 19) connect _WIRE_52.ae_ptw, _T_801 node _T_802 = bits(_WIRE_53, 20, 20) connect _WIRE_52.g, _T_802 node _T_803 = bits(_WIRE_53, 21, 21) connect _WIRE_52.u, _T_803 node _T_804 = bits(_WIRE_53, 41, 22) connect _WIRE_52.ppn, _T_804 node _T_805 = eq(sectored_entries[1][2].tag_v, hv_6) node _T_806 = eq(_WIRE_52.g, UInt<1>(0h0)) node _T_807 = and(_T_805, _T_806) when _T_807 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) else : node _T_808 = or(hv_6, hg_6) wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_55 : UInt<42> connect _WIRE_55, sectored_entries[1][2].data[0] node _T_809 = bits(_WIRE_55, 0, 0) connect _WIRE_54.fragmented_superpage, _T_809 node _T_810 = bits(_WIRE_55, 1, 1) connect _WIRE_54.c, _T_810 node _T_811 = bits(_WIRE_55, 2, 2) connect _WIRE_54.eff, _T_811 node _T_812 = bits(_WIRE_55, 3, 3) connect _WIRE_54.paa, _T_812 node _T_813 = bits(_WIRE_55, 4, 4) connect _WIRE_54.pal, _T_813 node _T_814 = bits(_WIRE_55, 5, 5) connect _WIRE_54.ppp, _T_814 node _T_815 = bits(_WIRE_55, 6, 6) connect _WIRE_54.pr, _T_815 node _T_816 = bits(_WIRE_55, 7, 7) connect _WIRE_54.px, _T_816 node _T_817 = bits(_WIRE_55, 8, 8) connect _WIRE_54.pw, _T_817 node _T_818 = bits(_WIRE_55, 9, 9) connect _WIRE_54.hr, _T_818 node _T_819 = bits(_WIRE_55, 10, 10) connect _WIRE_54.hx, _T_819 node _T_820 = bits(_WIRE_55, 11, 11) connect _WIRE_54.hw, _T_820 node _T_821 = bits(_WIRE_55, 12, 12) connect _WIRE_54.sr, _T_821 node _T_822 = bits(_WIRE_55, 13, 13) connect _WIRE_54.sx, _T_822 node _T_823 = bits(_WIRE_55, 14, 14) connect _WIRE_54.sw, _T_823 node _T_824 = bits(_WIRE_55, 15, 15) connect _WIRE_54.gf, _T_824 node _T_825 = bits(_WIRE_55, 16, 16) connect _WIRE_54.pf, _T_825 node _T_826 = bits(_WIRE_55, 17, 17) connect _WIRE_54.ae_stage2, _T_826 node _T_827 = bits(_WIRE_55, 18, 18) connect _WIRE_54.ae_final, _T_827 node _T_828 = bits(_WIRE_55, 19, 19) connect _WIRE_54.ae_ptw, _T_828 node _T_829 = bits(_WIRE_55, 20, 20) connect _WIRE_54.g, _T_829 node _T_830 = bits(_WIRE_55, 21, 21) connect _WIRE_54.u, _T_830 node _T_831 = bits(_WIRE_55, 41, 22) connect _WIRE_54.ppn, _T_831 node _T_832 = eq(sectored_entries[1][2].tag_v, _T_808) when _T_832 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_833 = eq(hg_7, UInt<1>(0h0)) node _T_834 = and(_T_833, io.sfence.bits.rs1) when _T_834 : node _T_835 = xor(sectored_entries[1][3].tag_vpn, vpn) node _T_836 = shr(_T_835, 0) node _T_837 = eq(_T_836, UInt<1>(0h0)) node _T_838 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_839 = and(_T_837, _T_838) when _T_839 : wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_57 : UInt<42> connect _WIRE_57, sectored_entries[1][3].data[0] node _T_840 = bits(_WIRE_57, 0, 0) connect _WIRE_56.fragmented_superpage, _T_840 node _T_841 = bits(_WIRE_57, 1, 1) connect _WIRE_56.c, _T_841 node _T_842 = bits(_WIRE_57, 2, 2) connect _WIRE_56.eff, _T_842 node _T_843 = bits(_WIRE_57, 3, 3) connect _WIRE_56.paa, _T_843 node _T_844 = bits(_WIRE_57, 4, 4) connect _WIRE_56.pal, _T_844 node _T_845 = bits(_WIRE_57, 5, 5) connect _WIRE_56.ppp, _T_845 node _T_846 = bits(_WIRE_57, 6, 6) connect _WIRE_56.pr, _T_846 node _T_847 = bits(_WIRE_57, 7, 7) connect _WIRE_56.px, _T_847 node _T_848 = bits(_WIRE_57, 8, 8) connect _WIRE_56.pw, _T_848 node _T_849 = bits(_WIRE_57, 9, 9) connect _WIRE_56.hr, _T_849 node _T_850 = bits(_WIRE_57, 10, 10) connect _WIRE_56.hx, _T_850 node _T_851 = bits(_WIRE_57, 11, 11) connect _WIRE_56.hw, _T_851 node _T_852 = bits(_WIRE_57, 12, 12) connect _WIRE_56.sr, _T_852 node _T_853 = bits(_WIRE_57, 13, 13) connect _WIRE_56.sx, _T_853 node _T_854 = bits(_WIRE_57, 14, 14) connect _WIRE_56.sw, _T_854 node _T_855 = bits(_WIRE_57, 15, 15) connect _WIRE_56.gf, _T_855 node _T_856 = bits(_WIRE_57, 16, 16) connect _WIRE_56.pf, _T_856 node _T_857 = bits(_WIRE_57, 17, 17) connect _WIRE_56.ae_stage2, _T_857 node _T_858 = bits(_WIRE_57, 18, 18) connect _WIRE_56.ae_final, _T_858 node _T_859 = bits(_WIRE_57, 19, 19) connect _WIRE_56.ae_ptw, _T_859 node _T_860 = bits(_WIRE_57, 20, 20) connect _WIRE_56.g, _T_860 node _T_861 = bits(_WIRE_57, 21, 21) connect _WIRE_56.u, _T_861 node _T_862 = bits(_WIRE_57, 41, 22) connect _WIRE_56.ppn, _T_862 node _T_863 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_864 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_865 = and(_T_863, _T_864) when _T_865 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) node _T_866 = xor(sectored_entries[1][3].tag_vpn, vpn) node _T_867 = shr(_T_866, 18) node _T_868 = eq(_T_867, UInt<1>(0h0)) when _T_868 : wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_59 : UInt<42> connect _WIRE_59, sectored_entries[1][3].data[0] node _T_869 = bits(_WIRE_59, 0, 0) connect _WIRE_58.fragmented_superpage, _T_869 node _T_870 = bits(_WIRE_59, 1, 1) connect _WIRE_58.c, _T_870 node _T_871 = bits(_WIRE_59, 2, 2) connect _WIRE_58.eff, _T_871 node _T_872 = bits(_WIRE_59, 3, 3) connect _WIRE_58.paa, _T_872 node _T_873 = bits(_WIRE_59, 4, 4) connect _WIRE_58.pal, _T_873 node _T_874 = bits(_WIRE_59, 5, 5) connect _WIRE_58.ppp, _T_874 node _T_875 = bits(_WIRE_59, 6, 6) connect _WIRE_58.pr, _T_875 node _T_876 = bits(_WIRE_59, 7, 7) connect _WIRE_58.px, _T_876 node _T_877 = bits(_WIRE_59, 8, 8) connect _WIRE_58.pw, _T_877 node _T_878 = bits(_WIRE_59, 9, 9) connect _WIRE_58.hr, _T_878 node _T_879 = bits(_WIRE_59, 10, 10) connect _WIRE_58.hx, _T_879 node _T_880 = bits(_WIRE_59, 11, 11) connect _WIRE_58.hw, _T_880 node _T_881 = bits(_WIRE_59, 12, 12) connect _WIRE_58.sr, _T_881 node _T_882 = bits(_WIRE_59, 13, 13) connect _WIRE_58.sx, _T_882 node _T_883 = bits(_WIRE_59, 14, 14) connect _WIRE_58.sw, _T_883 node _T_884 = bits(_WIRE_59, 15, 15) connect _WIRE_58.gf, _T_884 node _T_885 = bits(_WIRE_59, 16, 16) connect _WIRE_58.pf, _T_885 node _T_886 = bits(_WIRE_59, 17, 17) connect _WIRE_58.ae_stage2, _T_886 node _T_887 = bits(_WIRE_59, 18, 18) connect _WIRE_58.ae_final, _T_887 node _T_888 = bits(_WIRE_59, 19, 19) connect _WIRE_58.ae_ptw, _T_888 node _T_889 = bits(_WIRE_59, 20, 20) connect _WIRE_58.g, _T_889 node _T_890 = bits(_WIRE_59, 21, 21) connect _WIRE_58.u, _T_890 node _T_891 = bits(_WIRE_59, 41, 22) connect _WIRE_58.ppn, _T_891 node _T_892 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_893 = and(_T_892, _WIRE_58.fragmented_superpage) when _T_893 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) else : node _T_894 = eq(hg_7, UInt<1>(0h0)) node _T_895 = and(_T_894, io.sfence.bits.rs2) when _T_895 : wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_61 : UInt<42> connect _WIRE_61, sectored_entries[1][3].data[0] node _T_896 = bits(_WIRE_61, 0, 0) connect _WIRE_60.fragmented_superpage, _T_896 node _T_897 = bits(_WIRE_61, 1, 1) connect _WIRE_60.c, _T_897 node _T_898 = bits(_WIRE_61, 2, 2) connect _WIRE_60.eff, _T_898 node _T_899 = bits(_WIRE_61, 3, 3) connect _WIRE_60.paa, _T_899 node _T_900 = bits(_WIRE_61, 4, 4) connect _WIRE_60.pal, _T_900 node _T_901 = bits(_WIRE_61, 5, 5) connect _WIRE_60.ppp, _T_901 node _T_902 = bits(_WIRE_61, 6, 6) connect _WIRE_60.pr, _T_902 node _T_903 = bits(_WIRE_61, 7, 7) connect _WIRE_60.px, _T_903 node _T_904 = bits(_WIRE_61, 8, 8) connect _WIRE_60.pw, _T_904 node _T_905 = bits(_WIRE_61, 9, 9) connect _WIRE_60.hr, _T_905 node _T_906 = bits(_WIRE_61, 10, 10) connect _WIRE_60.hx, _T_906 node _T_907 = bits(_WIRE_61, 11, 11) connect _WIRE_60.hw, _T_907 node _T_908 = bits(_WIRE_61, 12, 12) connect _WIRE_60.sr, _T_908 node _T_909 = bits(_WIRE_61, 13, 13) connect _WIRE_60.sx, _T_909 node _T_910 = bits(_WIRE_61, 14, 14) connect _WIRE_60.sw, _T_910 node _T_911 = bits(_WIRE_61, 15, 15) connect _WIRE_60.gf, _T_911 node _T_912 = bits(_WIRE_61, 16, 16) connect _WIRE_60.pf, _T_912 node _T_913 = bits(_WIRE_61, 17, 17) connect _WIRE_60.ae_stage2, _T_913 node _T_914 = bits(_WIRE_61, 18, 18) connect _WIRE_60.ae_final, _T_914 node _T_915 = bits(_WIRE_61, 19, 19) connect _WIRE_60.ae_ptw, _T_915 node _T_916 = bits(_WIRE_61, 20, 20) connect _WIRE_60.g, _T_916 node _T_917 = bits(_WIRE_61, 21, 21) connect _WIRE_60.u, _T_917 node _T_918 = bits(_WIRE_61, 41, 22) connect _WIRE_60.ppn, _T_918 node _T_919 = eq(sectored_entries[1][3].tag_v, hv_7) node _T_920 = eq(_WIRE_60.g, UInt<1>(0h0)) node _T_921 = and(_T_919, _T_920) when _T_921 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) else : node _T_922 = or(hv_7, hg_7) wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_63 : UInt<42> connect _WIRE_63, sectored_entries[1][3].data[0] node _T_923 = bits(_WIRE_63, 0, 0) connect _WIRE_62.fragmented_superpage, _T_923 node _T_924 = bits(_WIRE_63, 1, 1) connect _WIRE_62.c, _T_924 node _T_925 = bits(_WIRE_63, 2, 2) connect _WIRE_62.eff, _T_925 node _T_926 = bits(_WIRE_63, 3, 3) connect _WIRE_62.paa, _T_926 node _T_927 = bits(_WIRE_63, 4, 4) connect _WIRE_62.pal, _T_927 node _T_928 = bits(_WIRE_63, 5, 5) connect _WIRE_62.ppp, _T_928 node _T_929 = bits(_WIRE_63, 6, 6) connect _WIRE_62.pr, _T_929 node _T_930 = bits(_WIRE_63, 7, 7) connect _WIRE_62.px, _T_930 node _T_931 = bits(_WIRE_63, 8, 8) connect _WIRE_62.pw, _T_931 node _T_932 = bits(_WIRE_63, 9, 9) connect _WIRE_62.hr, _T_932 node _T_933 = bits(_WIRE_63, 10, 10) connect _WIRE_62.hx, _T_933 node _T_934 = bits(_WIRE_63, 11, 11) connect _WIRE_62.hw, _T_934 node _T_935 = bits(_WIRE_63, 12, 12) connect _WIRE_62.sr, _T_935 node _T_936 = bits(_WIRE_63, 13, 13) connect _WIRE_62.sx, _T_936 node _T_937 = bits(_WIRE_63, 14, 14) connect _WIRE_62.sw, _T_937 node _T_938 = bits(_WIRE_63, 15, 15) connect _WIRE_62.gf, _T_938 node _T_939 = bits(_WIRE_63, 16, 16) connect _WIRE_62.pf, _T_939 node _T_940 = bits(_WIRE_63, 17, 17) connect _WIRE_62.ae_stage2, _T_940 node _T_941 = bits(_WIRE_63, 18, 18) connect _WIRE_62.ae_final, _T_941 node _T_942 = bits(_WIRE_63, 19, 19) connect _WIRE_62.ae_ptw, _T_942 node _T_943 = bits(_WIRE_63, 20, 20) connect _WIRE_62.g, _T_943 node _T_944 = bits(_WIRE_63, 21, 21) connect _WIRE_62.u, _T_944 node _T_945 = bits(_WIRE_63, 41, 22) connect _WIRE_62.ppn, _T_945 node _T_946 = eq(sectored_entries[1][3].tag_v, _T_922) when _T_946 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_947 = eq(hg_8, UInt<1>(0h0)) node _T_948 = and(_T_947, io.sfence.bits.rs1) when _T_948 : node _T_949 = xor(sectored_entries[2][0].tag_vpn, vpn) node _T_950 = shr(_T_949, 0) node _T_951 = eq(_T_950, UInt<1>(0h0)) node _T_952 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_953 = and(_T_951, _T_952) when _T_953 : wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_65 : UInt<42> connect _WIRE_65, sectored_entries[2][0].data[0] node _T_954 = bits(_WIRE_65, 0, 0) connect _WIRE_64.fragmented_superpage, _T_954 node _T_955 = bits(_WIRE_65, 1, 1) connect _WIRE_64.c, _T_955 node _T_956 = bits(_WIRE_65, 2, 2) connect _WIRE_64.eff, _T_956 node _T_957 = bits(_WIRE_65, 3, 3) connect _WIRE_64.paa, _T_957 node _T_958 = bits(_WIRE_65, 4, 4) connect _WIRE_64.pal, _T_958 node _T_959 = bits(_WIRE_65, 5, 5) connect _WIRE_64.ppp, _T_959 node _T_960 = bits(_WIRE_65, 6, 6) connect _WIRE_64.pr, _T_960 node _T_961 = bits(_WIRE_65, 7, 7) connect _WIRE_64.px, _T_961 node _T_962 = bits(_WIRE_65, 8, 8) connect _WIRE_64.pw, _T_962 node _T_963 = bits(_WIRE_65, 9, 9) connect _WIRE_64.hr, _T_963 node _T_964 = bits(_WIRE_65, 10, 10) connect _WIRE_64.hx, _T_964 node _T_965 = bits(_WIRE_65, 11, 11) connect _WIRE_64.hw, _T_965 node _T_966 = bits(_WIRE_65, 12, 12) connect _WIRE_64.sr, _T_966 node _T_967 = bits(_WIRE_65, 13, 13) connect _WIRE_64.sx, _T_967 node _T_968 = bits(_WIRE_65, 14, 14) connect _WIRE_64.sw, _T_968 node _T_969 = bits(_WIRE_65, 15, 15) connect _WIRE_64.gf, _T_969 node _T_970 = bits(_WIRE_65, 16, 16) connect _WIRE_64.pf, _T_970 node _T_971 = bits(_WIRE_65, 17, 17) connect _WIRE_64.ae_stage2, _T_971 node _T_972 = bits(_WIRE_65, 18, 18) connect _WIRE_64.ae_final, _T_972 node _T_973 = bits(_WIRE_65, 19, 19) connect _WIRE_64.ae_ptw, _T_973 node _T_974 = bits(_WIRE_65, 20, 20) connect _WIRE_64.g, _T_974 node _T_975 = bits(_WIRE_65, 21, 21) connect _WIRE_64.u, _T_975 node _T_976 = bits(_WIRE_65, 41, 22) connect _WIRE_64.ppn, _T_976 node _T_977 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_978 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_979 = and(_T_977, _T_978) when _T_979 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) node _T_980 = xor(sectored_entries[2][0].tag_vpn, vpn) node _T_981 = shr(_T_980, 18) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_67 : UInt<42> connect _WIRE_67, sectored_entries[2][0].data[0] node _T_983 = bits(_WIRE_67, 0, 0) connect _WIRE_66.fragmented_superpage, _T_983 node _T_984 = bits(_WIRE_67, 1, 1) connect _WIRE_66.c, _T_984 node _T_985 = bits(_WIRE_67, 2, 2) connect _WIRE_66.eff, _T_985 node _T_986 = bits(_WIRE_67, 3, 3) connect _WIRE_66.paa, _T_986 node _T_987 = bits(_WIRE_67, 4, 4) connect _WIRE_66.pal, _T_987 node _T_988 = bits(_WIRE_67, 5, 5) connect _WIRE_66.ppp, _T_988 node _T_989 = bits(_WIRE_67, 6, 6) connect _WIRE_66.pr, _T_989 node _T_990 = bits(_WIRE_67, 7, 7) connect _WIRE_66.px, _T_990 node _T_991 = bits(_WIRE_67, 8, 8) connect _WIRE_66.pw, _T_991 node _T_992 = bits(_WIRE_67, 9, 9) connect _WIRE_66.hr, _T_992 node _T_993 = bits(_WIRE_67, 10, 10) connect _WIRE_66.hx, _T_993 node _T_994 = bits(_WIRE_67, 11, 11) connect _WIRE_66.hw, _T_994 node _T_995 = bits(_WIRE_67, 12, 12) connect _WIRE_66.sr, _T_995 node _T_996 = bits(_WIRE_67, 13, 13) connect _WIRE_66.sx, _T_996 node _T_997 = bits(_WIRE_67, 14, 14) connect _WIRE_66.sw, _T_997 node _T_998 = bits(_WIRE_67, 15, 15) connect _WIRE_66.gf, _T_998 node _T_999 = bits(_WIRE_67, 16, 16) connect _WIRE_66.pf, _T_999 node _T_1000 = bits(_WIRE_67, 17, 17) connect _WIRE_66.ae_stage2, _T_1000 node _T_1001 = bits(_WIRE_67, 18, 18) connect _WIRE_66.ae_final, _T_1001 node _T_1002 = bits(_WIRE_67, 19, 19) connect _WIRE_66.ae_ptw, _T_1002 node _T_1003 = bits(_WIRE_67, 20, 20) connect _WIRE_66.g, _T_1003 node _T_1004 = bits(_WIRE_67, 21, 21) connect _WIRE_66.u, _T_1004 node _T_1005 = bits(_WIRE_67, 41, 22) connect _WIRE_66.ppn, _T_1005 node _T_1006 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_1007 = and(_T_1006, _WIRE_66.fragmented_superpage) when _T_1007 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) else : node _T_1008 = eq(hg_8, UInt<1>(0h0)) node _T_1009 = and(_T_1008, io.sfence.bits.rs2) when _T_1009 : wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_69 : UInt<42> connect _WIRE_69, sectored_entries[2][0].data[0] node _T_1010 = bits(_WIRE_69, 0, 0) connect _WIRE_68.fragmented_superpage, _T_1010 node _T_1011 = bits(_WIRE_69, 1, 1) connect _WIRE_68.c, _T_1011 node _T_1012 = bits(_WIRE_69, 2, 2) connect _WIRE_68.eff, _T_1012 node _T_1013 = bits(_WIRE_69, 3, 3) connect _WIRE_68.paa, _T_1013 node _T_1014 = bits(_WIRE_69, 4, 4) connect _WIRE_68.pal, _T_1014 node _T_1015 = bits(_WIRE_69, 5, 5) connect _WIRE_68.ppp, _T_1015 node _T_1016 = bits(_WIRE_69, 6, 6) connect _WIRE_68.pr, _T_1016 node _T_1017 = bits(_WIRE_69, 7, 7) connect _WIRE_68.px, _T_1017 node _T_1018 = bits(_WIRE_69, 8, 8) connect _WIRE_68.pw, _T_1018 node _T_1019 = bits(_WIRE_69, 9, 9) connect _WIRE_68.hr, _T_1019 node _T_1020 = bits(_WIRE_69, 10, 10) connect _WIRE_68.hx, _T_1020 node _T_1021 = bits(_WIRE_69, 11, 11) connect _WIRE_68.hw, _T_1021 node _T_1022 = bits(_WIRE_69, 12, 12) connect _WIRE_68.sr, _T_1022 node _T_1023 = bits(_WIRE_69, 13, 13) connect _WIRE_68.sx, _T_1023 node _T_1024 = bits(_WIRE_69, 14, 14) connect _WIRE_68.sw, _T_1024 node _T_1025 = bits(_WIRE_69, 15, 15) connect _WIRE_68.gf, _T_1025 node _T_1026 = bits(_WIRE_69, 16, 16) connect _WIRE_68.pf, _T_1026 node _T_1027 = bits(_WIRE_69, 17, 17) connect _WIRE_68.ae_stage2, _T_1027 node _T_1028 = bits(_WIRE_69, 18, 18) connect _WIRE_68.ae_final, _T_1028 node _T_1029 = bits(_WIRE_69, 19, 19) connect _WIRE_68.ae_ptw, _T_1029 node _T_1030 = bits(_WIRE_69, 20, 20) connect _WIRE_68.g, _T_1030 node _T_1031 = bits(_WIRE_69, 21, 21) connect _WIRE_68.u, _T_1031 node _T_1032 = bits(_WIRE_69, 41, 22) connect _WIRE_68.ppn, _T_1032 node _T_1033 = eq(sectored_entries[2][0].tag_v, hv_8) node _T_1034 = eq(_WIRE_68.g, UInt<1>(0h0)) node _T_1035 = and(_T_1033, _T_1034) when _T_1035 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) else : node _T_1036 = or(hv_8, hg_8) wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_71 : UInt<42> connect _WIRE_71, sectored_entries[2][0].data[0] node _T_1037 = bits(_WIRE_71, 0, 0) connect _WIRE_70.fragmented_superpage, _T_1037 node _T_1038 = bits(_WIRE_71, 1, 1) connect _WIRE_70.c, _T_1038 node _T_1039 = bits(_WIRE_71, 2, 2) connect _WIRE_70.eff, _T_1039 node _T_1040 = bits(_WIRE_71, 3, 3) connect _WIRE_70.paa, _T_1040 node _T_1041 = bits(_WIRE_71, 4, 4) connect _WIRE_70.pal, _T_1041 node _T_1042 = bits(_WIRE_71, 5, 5) connect _WIRE_70.ppp, _T_1042 node _T_1043 = bits(_WIRE_71, 6, 6) connect _WIRE_70.pr, _T_1043 node _T_1044 = bits(_WIRE_71, 7, 7) connect _WIRE_70.px, _T_1044 node _T_1045 = bits(_WIRE_71, 8, 8) connect _WIRE_70.pw, _T_1045 node _T_1046 = bits(_WIRE_71, 9, 9) connect _WIRE_70.hr, _T_1046 node _T_1047 = bits(_WIRE_71, 10, 10) connect _WIRE_70.hx, _T_1047 node _T_1048 = bits(_WIRE_71, 11, 11) connect _WIRE_70.hw, _T_1048 node _T_1049 = bits(_WIRE_71, 12, 12) connect _WIRE_70.sr, _T_1049 node _T_1050 = bits(_WIRE_71, 13, 13) connect _WIRE_70.sx, _T_1050 node _T_1051 = bits(_WIRE_71, 14, 14) connect _WIRE_70.sw, _T_1051 node _T_1052 = bits(_WIRE_71, 15, 15) connect _WIRE_70.gf, _T_1052 node _T_1053 = bits(_WIRE_71, 16, 16) connect _WIRE_70.pf, _T_1053 node _T_1054 = bits(_WIRE_71, 17, 17) connect _WIRE_70.ae_stage2, _T_1054 node _T_1055 = bits(_WIRE_71, 18, 18) connect _WIRE_70.ae_final, _T_1055 node _T_1056 = bits(_WIRE_71, 19, 19) connect _WIRE_70.ae_ptw, _T_1056 node _T_1057 = bits(_WIRE_71, 20, 20) connect _WIRE_70.g, _T_1057 node _T_1058 = bits(_WIRE_71, 21, 21) connect _WIRE_70.u, _T_1058 node _T_1059 = bits(_WIRE_71, 41, 22) connect _WIRE_70.ppn, _T_1059 node _T_1060 = eq(sectored_entries[2][0].tag_v, _T_1036) when _T_1060 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1061 = eq(hg_9, UInt<1>(0h0)) node _T_1062 = and(_T_1061, io.sfence.bits.rs1) when _T_1062 : node _T_1063 = xor(sectored_entries[2][1].tag_vpn, vpn) node _T_1064 = shr(_T_1063, 0) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) node _T_1066 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1067 = and(_T_1065, _T_1066) when _T_1067 : wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_73 : UInt<42> connect _WIRE_73, sectored_entries[2][1].data[0] node _T_1068 = bits(_WIRE_73, 0, 0) connect _WIRE_72.fragmented_superpage, _T_1068 node _T_1069 = bits(_WIRE_73, 1, 1) connect _WIRE_72.c, _T_1069 node _T_1070 = bits(_WIRE_73, 2, 2) connect _WIRE_72.eff, _T_1070 node _T_1071 = bits(_WIRE_73, 3, 3) connect _WIRE_72.paa, _T_1071 node _T_1072 = bits(_WIRE_73, 4, 4) connect _WIRE_72.pal, _T_1072 node _T_1073 = bits(_WIRE_73, 5, 5) connect _WIRE_72.ppp, _T_1073 node _T_1074 = bits(_WIRE_73, 6, 6) connect _WIRE_72.pr, _T_1074 node _T_1075 = bits(_WIRE_73, 7, 7) connect _WIRE_72.px, _T_1075 node _T_1076 = bits(_WIRE_73, 8, 8) connect _WIRE_72.pw, _T_1076 node _T_1077 = bits(_WIRE_73, 9, 9) connect _WIRE_72.hr, _T_1077 node _T_1078 = bits(_WIRE_73, 10, 10) connect _WIRE_72.hx, _T_1078 node _T_1079 = bits(_WIRE_73, 11, 11) connect _WIRE_72.hw, _T_1079 node _T_1080 = bits(_WIRE_73, 12, 12) connect _WIRE_72.sr, _T_1080 node _T_1081 = bits(_WIRE_73, 13, 13) connect _WIRE_72.sx, _T_1081 node _T_1082 = bits(_WIRE_73, 14, 14) connect _WIRE_72.sw, _T_1082 node _T_1083 = bits(_WIRE_73, 15, 15) connect _WIRE_72.gf, _T_1083 node _T_1084 = bits(_WIRE_73, 16, 16) connect _WIRE_72.pf, _T_1084 node _T_1085 = bits(_WIRE_73, 17, 17) connect _WIRE_72.ae_stage2, _T_1085 node _T_1086 = bits(_WIRE_73, 18, 18) connect _WIRE_72.ae_final, _T_1086 node _T_1087 = bits(_WIRE_73, 19, 19) connect _WIRE_72.ae_ptw, _T_1087 node _T_1088 = bits(_WIRE_73, 20, 20) connect _WIRE_72.g, _T_1088 node _T_1089 = bits(_WIRE_73, 21, 21) connect _WIRE_72.u, _T_1089 node _T_1090 = bits(_WIRE_73, 41, 22) connect _WIRE_72.ppn, _T_1090 node _T_1091 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1092 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1093 = and(_T_1091, _T_1092) when _T_1093 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) node _T_1094 = xor(sectored_entries[2][1].tag_vpn, vpn) node _T_1095 = shr(_T_1094, 18) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_75 : UInt<42> connect _WIRE_75, sectored_entries[2][1].data[0] node _T_1097 = bits(_WIRE_75, 0, 0) connect _WIRE_74.fragmented_superpage, _T_1097 node _T_1098 = bits(_WIRE_75, 1, 1) connect _WIRE_74.c, _T_1098 node _T_1099 = bits(_WIRE_75, 2, 2) connect _WIRE_74.eff, _T_1099 node _T_1100 = bits(_WIRE_75, 3, 3) connect _WIRE_74.paa, _T_1100 node _T_1101 = bits(_WIRE_75, 4, 4) connect _WIRE_74.pal, _T_1101 node _T_1102 = bits(_WIRE_75, 5, 5) connect _WIRE_74.ppp, _T_1102 node _T_1103 = bits(_WIRE_75, 6, 6) connect _WIRE_74.pr, _T_1103 node _T_1104 = bits(_WIRE_75, 7, 7) connect _WIRE_74.px, _T_1104 node _T_1105 = bits(_WIRE_75, 8, 8) connect _WIRE_74.pw, _T_1105 node _T_1106 = bits(_WIRE_75, 9, 9) connect _WIRE_74.hr, _T_1106 node _T_1107 = bits(_WIRE_75, 10, 10) connect _WIRE_74.hx, _T_1107 node _T_1108 = bits(_WIRE_75, 11, 11) connect _WIRE_74.hw, _T_1108 node _T_1109 = bits(_WIRE_75, 12, 12) connect _WIRE_74.sr, _T_1109 node _T_1110 = bits(_WIRE_75, 13, 13) connect _WIRE_74.sx, _T_1110 node _T_1111 = bits(_WIRE_75, 14, 14) connect _WIRE_74.sw, _T_1111 node _T_1112 = bits(_WIRE_75, 15, 15) connect _WIRE_74.gf, _T_1112 node _T_1113 = bits(_WIRE_75, 16, 16) connect _WIRE_74.pf, _T_1113 node _T_1114 = bits(_WIRE_75, 17, 17) connect _WIRE_74.ae_stage2, _T_1114 node _T_1115 = bits(_WIRE_75, 18, 18) connect _WIRE_74.ae_final, _T_1115 node _T_1116 = bits(_WIRE_75, 19, 19) connect _WIRE_74.ae_ptw, _T_1116 node _T_1117 = bits(_WIRE_75, 20, 20) connect _WIRE_74.g, _T_1117 node _T_1118 = bits(_WIRE_75, 21, 21) connect _WIRE_74.u, _T_1118 node _T_1119 = bits(_WIRE_75, 41, 22) connect _WIRE_74.ppn, _T_1119 node _T_1120 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1121 = and(_T_1120, _WIRE_74.fragmented_superpage) when _T_1121 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) else : node _T_1122 = eq(hg_9, UInt<1>(0h0)) node _T_1123 = and(_T_1122, io.sfence.bits.rs2) when _T_1123 : wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_77 : UInt<42> connect _WIRE_77, sectored_entries[2][1].data[0] node _T_1124 = bits(_WIRE_77, 0, 0) connect _WIRE_76.fragmented_superpage, _T_1124 node _T_1125 = bits(_WIRE_77, 1, 1) connect _WIRE_76.c, _T_1125 node _T_1126 = bits(_WIRE_77, 2, 2) connect _WIRE_76.eff, _T_1126 node _T_1127 = bits(_WIRE_77, 3, 3) connect _WIRE_76.paa, _T_1127 node _T_1128 = bits(_WIRE_77, 4, 4) connect _WIRE_76.pal, _T_1128 node _T_1129 = bits(_WIRE_77, 5, 5) connect _WIRE_76.ppp, _T_1129 node _T_1130 = bits(_WIRE_77, 6, 6) connect _WIRE_76.pr, _T_1130 node _T_1131 = bits(_WIRE_77, 7, 7) connect _WIRE_76.px, _T_1131 node _T_1132 = bits(_WIRE_77, 8, 8) connect _WIRE_76.pw, _T_1132 node _T_1133 = bits(_WIRE_77, 9, 9) connect _WIRE_76.hr, _T_1133 node _T_1134 = bits(_WIRE_77, 10, 10) connect _WIRE_76.hx, _T_1134 node _T_1135 = bits(_WIRE_77, 11, 11) connect _WIRE_76.hw, _T_1135 node _T_1136 = bits(_WIRE_77, 12, 12) connect _WIRE_76.sr, _T_1136 node _T_1137 = bits(_WIRE_77, 13, 13) connect _WIRE_76.sx, _T_1137 node _T_1138 = bits(_WIRE_77, 14, 14) connect _WIRE_76.sw, _T_1138 node _T_1139 = bits(_WIRE_77, 15, 15) connect _WIRE_76.gf, _T_1139 node _T_1140 = bits(_WIRE_77, 16, 16) connect _WIRE_76.pf, _T_1140 node _T_1141 = bits(_WIRE_77, 17, 17) connect _WIRE_76.ae_stage2, _T_1141 node _T_1142 = bits(_WIRE_77, 18, 18) connect _WIRE_76.ae_final, _T_1142 node _T_1143 = bits(_WIRE_77, 19, 19) connect _WIRE_76.ae_ptw, _T_1143 node _T_1144 = bits(_WIRE_77, 20, 20) connect _WIRE_76.g, _T_1144 node _T_1145 = bits(_WIRE_77, 21, 21) connect _WIRE_76.u, _T_1145 node _T_1146 = bits(_WIRE_77, 41, 22) connect _WIRE_76.ppn, _T_1146 node _T_1147 = eq(sectored_entries[2][1].tag_v, hv_9) node _T_1148 = eq(_WIRE_76.g, UInt<1>(0h0)) node _T_1149 = and(_T_1147, _T_1148) when _T_1149 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) else : node _T_1150 = or(hv_9, hg_9) wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_79 : UInt<42> connect _WIRE_79, sectored_entries[2][1].data[0] node _T_1151 = bits(_WIRE_79, 0, 0) connect _WIRE_78.fragmented_superpage, _T_1151 node _T_1152 = bits(_WIRE_79, 1, 1) connect _WIRE_78.c, _T_1152 node _T_1153 = bits(_WIRE_79, 2, 2) connect _WIRE_78.eff, _T_1153 node _T_1154 = bits(_WIRE_79, 3, 3) connect _WIRE_78.paa, _T_1154 node _T_1155 = bits(_WIRE_79, 4, 4) connect _WIRE_78.pal, _T_1155 node _T_1156 = bits(_WIRE_79, 5, 5) connect _WIRE_78.ppp, _T_1156 node _T_1157 = bits(_WIRE_79, 6, 6) connect _WIRE_78.pr, _T_1157 node _T_1158 = bits(_WIRE_79, 7, 7) connect _WIRE_78.px, _T_1158 node _T_1159 = bits(_WIRE_79, 8, 8) connect _WIRE_78.pw, _T_1159 node _T_1160 = bits(_WIRE_79, 9, 9) connect _WIRE_78.hr, _T_1160 node _T_1161 = bits(_WIRE_79, 10, 10) connect _WIRE_78.hx, _T_1161 node _T_1162 = bits(_WIRE_79, 11, 11) connect _WIRE_78.hw, _T_1162 node _T_1163 = bits(_WIRE_79, 12, 12) connect _WIRE_78.sr, _T_1163 node _T_1164 = bits(_WIRE_79, 13, 13) connect _WIRE_78.sx, _T_1164 node _T_1165 = bits(_WIRE_79, 14, 14) connect _WIRE_78.sw, _T_1165 node _T_1166 = bits(_WIRE_79, 15, 15) connect _WIRE_78.gf, _T_1166 node _T_1167 = bits(_WIRE_79, 16, 16) connect _WIRE_78.pf, _T_1167 node _T_1168 = bits(_WIRE_79, 17, 17) connect _WIRE_78.ae_stage2, _T_1168 node _T_1169 = bits(_WIRE_79, 18, 18) connect _WIRE_78.ae_final, _T_1169 node _T_1170 = bits(_WIRE_79, 19, 19) connect _WIRE_78.ae_ptw, _T_1170 node _T_1171 = bits(_WIRE_79, 20, 20) connect _WIRE_78.g, _T_1171 node _T_1172 = bits(_WIRE_79, 21, 21) connect _WIRE_78.u, _T_1172 node _T_1173 = bits(_WIRE_79, 41, 22) connect _WIRE_78.ppn, _T_1173 node _T_1174 = eq(sectored_entries[2][1].tag_v, _T_1150) when _T_1174 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1175 = eq(hg_10, UInt<1>(0h0)) node _T_1176 = and(_T_1175, io.sfence.bits.rs1) when _T_1176 : node _T_1177 = xor(sectored_entries[2][2].tag_vpn, vpn) node _T_1178 = shr(_T_1177, 0) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) node _T_1180 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1181 = and(_T_1179, _T_1180) when _T_1181 : wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_81 : UInt<42> connect _WIRE_81, sectored_entries[2][2].data[0] node _T_1182 = bits(_WIRE_81, 0, 0) connect _WIRE_80.fragmented_superpage, _T_1182 node _T_1183 = bits(_WIRE_81, 1, 1) connect _WIRE_80.c, _T_1183 node _T_1184 = bits(_WIRE_81, 2, 2) connect _WIRE_80.eff, _T_1184 node _T_1185 = bits(_WIRE_81, 3, 3) connect _WIRE_80.paa, _T_1185 node _T_1186 = bits(_WIRE_81, 4, 4) connect _WIRE_80.pal, _T_1186 node _T_1187 = bits(_WIRE_81, 5, 5) connect _WIRE_80.ppp, _T_1187 node _T_1188 = bits(_WIRE_81, 6, 6) connect _WIRE_80.pr, _T_1188 node _T_1189 = bits(_WIRE_81, 7, 7) connect _WIRE_80.px, _T_1189 node _T_1190 = bits(_WIRE_81, 8, 8) connect _WIRE_80.pw, _T_1190 node _T_1191 = bits(_WIRE_81, 9, 9) connect _WIRE_80.hr, _T_1191 node _T_1192 = bits(_WIRE_81, 10, 10) connect _WIRE_80.hx, _T_1192 node _T_1193 = bits(_WIRE_81, 11, 11) connect _WIRE_80.hw, _T_1193 node _T_1194 = bits(_WIRE_81, 12, 12) connect _WIRE_80.sr, _T_1194 node _T_1195 = bits(_WIRE_81, 13, 13) connect _WIRE_80.sx, _T_1195 node _T_1196 = bits(_WIRE_81, 14, 14) connect _WIRE_80.sw, _T_1196 node _T_1197 = bits(_WIRE_81, 15, 15) connect _WIRE_80.gf, _T_1197 node _T_1198 = bits(_WIRE_81, 16, 16) connect _WIRE_80.pf, _T_1198 node _T_1199 = bits(_WIRE_81, 17, 17) connect _WIRE_80.ae_stage2, _T_1199 node _T_1200 = bits(_WIRE_81, 18, 18) connect _WIRE_80.ae_final, _T_1200 node _T_1201 = bits(_WIRE_81, 19, 19) connect _WIRE_80.ae_ptw, _T_1201 node _T_1202 = bits(_WIRE_81, 20, 20) connect _WIRE_80.g, _T_1202 node _T_1203 = bits(_WIRE_81, 21, 21) connect _WIRE_80.u, _T_1203 node _T_1204 = bits(_WIRE_81, 41, 22) connect _WIRE_80.ppn, _T_1204 node _T_1205 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1206 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1207 = and(_T_1205, _T_1206) when _T_1207 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) node _T_1208 = xor(sectored_entries[2][2].tag_vpn, vpn) node _T_1209 = shr(_T_1208, 18) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_83 : UInt<42> connect _WIRE_83, sectored_entries[2][2].data[0] node _T_1211 = bits(_WIRE_83, 0, 0) connect _WIRE_82.fragmented_superpage, _T_1211 node _T_1212 = bits(_WIRE_83, 1, 1) connect _WIRE_82.c, _T_1212 node _T_1213 = bits(_WIRE_83, 2, 2) connect _WIRE_82.eff, _T_1213 node _T_1214 = bits(_WIRE_83, 3, 3) connect _WIRE_82.paa, _T_1214 node _T_1215 = bits(_WIRE_83, 4, 4) connect _WIRE_82.pal, _T_1215 node _T_1216 = bits(_WIRE_83, 5, 5) connect _WIRE_82.ppp, _T_1216 node _T_1217 = bits(_WIRE_83, 6, 6) connect _WIRE_82.pr, _T_1217 node _T_1218 = bits(_WIRE_83, 7, 7) connect _WIRE_82.px, _T_1218 node _T_1219 = bits(_WIRE_83, 8, 8) connect _WIRE_82.pw, _T_1219 node _T_1220 = bits(_WIRE_83, 9, 9) connect _WIRE_82.hr, _T_1220 node _T_1221 = bits(_WIRE_83, 10, 10) connect _WIRE_82.hx, _T_1221 node _T_1222 = bits(_WIRE_83, 11, 11) connect _WIRE_82.hw, _T_1222 node _T_1223 = bits(_WIRE_83, 12, 12) connect _WIRE_82.sr, _T_1223 node _T_1224 = bits(_WIRE_83, 13, 13) connect _WIRE_82.sx, _T_1224 node _T_1225 = bits(_WIRE_83, 14, 14) connect _WIRE_82.sw, _T_1225 node _T_1226 = bits(_WIRE_83, 15, 15) connect _WIRE_82.gf, _T_1226 node _T_1227 = bits(_WIRE_83, 16, 16) connect _WIRE_82.pf, _T_1227 node _T_1228 = bits(_WIRE_83, 17, 17) connect _WIRE_82.ae_stage2, _T_1228 node _T_1229 = bits(_WIRE_83, 18, 18) connect _WIRE_82.ae_final, _T_1229 node _T_1230 = bits(_WIRE_83, 19, 19) connect _WIRE_82.ae_ptw, _T_1230 node _T_1231 = bits(_WIRE_83, 20, 20) connect _WIRE_82.g, _T_1231 node _T_1232 = bits(_WIRE_83, 21, 21) connect _WIRE_82.u, _T_1232 node _T_1233 = bits(_WIRE_83, 41, 22) connect _WIRE_82.ppn, _T_1233 node _T_1234 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1235 = and(_T_1234, _WIRE_82.fragmented_superpage) when _T_1235 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) else : node _T_1236 = eq(hg_10, UInt<1>(0h0)) node _T_1237 = and(_T_1236, io.sfence.bits.rs2) when _T_1237 : wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_85 : UInt<42> connect _WIRE_85, sectored_entries[2][2].data[0] node _T_1238 = bits(_WIRE_85, 0, 0) connect _WIRE_84.fragmented_superpage, _T_1238 node _T_1239 = bits(_WIRE_85, 1, 1) connect _WIRE_84.c, _T_1239 node _T_1240 = bits(_WIRE_85, 2, 2) connect _WIRE_84.eff, _T_1240 node _T_1241 = bits(_WIRE_85, 3, 3) connect _WIRE_84.paa, _T_1241 node _T_1242 = bits(_WIRE_85, 4, 4) connect _WIRE_84.pal, _T_1242 node _T_1243 = bits(_WIRE_85, 5, 5) connect _WIRE_84.ppp, _T_1243 node _T_1244 = bits(_WIRE_85, 6, 6) connect _WIRE_84.pr, _T_1244 node _T_1245 = bits(_WIRE_85, 7, 7) connect _WIRE_84.px, _T_1245 node _T_1246 = bits(_WIRE_85, 8, 8) connect _WIRE_84.pw, _T_1246 node _T_1247 = bits(_WIRE_85, 9, 9) connect _WIRE_84.hr, _T_1247 node _T_1248 = bits(_WIRE_85, 10, 10) connect _WIRE_84.hx, _T_1248 node _T_1249 = bits(_WIRE_85, 11, 11) connect _WIRE_84.hw, _T_1249 node _T_1250 = bits(_WIRE_85, 12, 12) connect _WIRE_84.sr, _T_1250 node _T_1251 = bits(_WIRE_85, 13, 13) connect _WIRE_84.sx, _T_1251 node _T_1252 = bits(_WIRE_85, 14, 14) connect _WIRE_84.sw, _T_1252 node _T_1253 = bits(_WIRE_85, 15, 15) connect _WIRE_84.gf, _T_1253 node _T_1254 = bits(_WIRE_85, 16, 16) connect _WIRE_84.pf, _T_1254 node _T_1255 = bits(_WIRE_85, 17, 17) connect _WIRE_84.ae_stage2, _T_1255 node _T_1256 = bits(_WIRE_85, 18, 18) connect _WIRE_84.ae_final, _T_1256 node _T_1257 = bits(_WIRE_85, 19, 19) connect _WIRE_84.ae_ptw, _T_1257 node _T_1258 = bits(_WIRE_85, 20, 20) connect _WIRE_84.g, _T_1258 node _T_1259 = bits(_WIRE_85, 21, 21) connect _WIRE_84.u, _T_1259 node _T_1260 = bits(_WIRE_85, 41, 22) connect _WIRE_84.ppn, _T_1260 node _T_1261 = eq(sectored_entries[2][2].tag_v, hv_10) node _T_1262 = eq(_WIRE_84.g, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) else : node _T_1264 = or(hv_10, hg_10) wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_87 : UInt<42> connect _WIRE_87, sectored_entries[2][2].data[0] node _T_1265 = bits(_WIRE_87, 0, 0) connect _WIRE_86.fragmented_superpage, _T_1265 node _T_1266 = bits(_WIRE_87, 1, 1) connect _WIRE_86.c, _T_1266 node _T_1267 = bits(_WIRE_87, 2, 2) connect _WIRE_86.eff, _T_1267 node _T_1268 = bits(_WIRE_87, 3, 3) connect _WIRE_86.paa, _T_1268 node _T_1269 = bits(_WIRE_87, 4, 4) connect _WIRE_86.pal, _T_1269 node _T_1270 = bits(_WIRE_87, 5, 5) connect _WIRE_86.ppp, _T_1270 node _T_1271 = bits(_WIRE_87, 6, 6) connect _WIRE_86.pr, _T_1271 node _T_1272 = bits(_WIRE_87, 7, 7) connect _WIRE_86.px, _T_1272 node _T_1273 = bits(_WIRE_87, 8, 8) connect _WIRE_86.pw, _T_1273 node _T_1274 = bits(_WIRE_87, 9, 9) connect _WIRE_86.hr, _T_1274 node _T_1275 = bits(_WIRE_87, 10, 10) connect _WIRE_86.hx, _T_1275 node _T_1276 = bits(_WIRE_87, 11, 11) connect _WIRE_86.hw, _T_1276 node _T_1277 = bits(_WIRE_87, 12, 12) connect _WIRE_86.sr, _T_1277 node _T_1278 = bits(_WIRE_87, 13, 13) connect _WIRE_86.sx, _T_1278 node _T_1279 = bits(_WIRE_87, 14, 14) connect _WIRE_86.sw, _T_1279 node _T_1280 = bits(_WIRE_87, 15, 15) connect _WIRE_86.gf, _T_1280 node _T_1281 = bits(_WIRE_87, 16, 16) connect _WIRE_86.pf, _T_1281 node _T_1282 = bits(_WIRE_87, 17, 17) connect _WIRE_86.ae_stage2, _T_1282 node _T_1283 = bits(_WIRE_87, 18, 18) connect _WIRE_86.ae_final, _T_1283 node _T_1284 = bits(_WIRE_87, 19, 19) connect _WIRE_86.ae_ptw, _T_1284 node _T_1285 = bits(_WIRE_87, 20, 20) connect _WIRE_86.g, _T_1285 node _T_1286 = bits(_WIRE_87, 21, 21) connect _WIRE_86.u, _T_1286 node _T_1287 = bits(_WIRE_87, 41, 22) connect _WIRE_86.ppn, _T_1287 node _T_1288 = eq(sectored_entries[2][2].tag_v, _T_1264) when _T_1288 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1289 = eq(hg_11, UInt<1>(0h0)) node _T_1290 = and(_T_1289, io.sfence.bits.rs1) when _T_1290 : node _T_1291 = xor(sectored_entries[2][3].tag_vpn, vpn) node _T_1292 = shr(_T_1291, 0) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) node _T_1294 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1295 = and(_T_1293, _T_1294) when _T_1295 : wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_89 : UInt<42> connect _WIRE_89, sectored_entries[2][3].data[0] node _T_1296 = bits(_WIRE_89, 0, 0) connect _WIRE_88.fragmented_superpage, _T_1296 node _T_1297 = bits(_WIRE_89, 1, 1) connect _WIRE_88.c, _T_1297 node _T_1298 = bits(_WIRE_89, 2, 2) connect _WIRE_88.eff, _T_1298 node _T_1299 = bits(_WIRE_89, 3, 3) connect _WIRE_88.paa, _T_1299 node _T_1300 = bits(_WIRE_89, 4, 4) connect _WIRE_88.pal, _T_1300 node _T_1301 = bits(_WIRE_89, 5, 5) connect _WIRE_88.ppp, _T_1301 node _T_1302 = bits(_WIRE_89, 6, 6) connect _WIRE_88.pr, _T_1302 node _T_1303 = bits(_WIRE_89, 7, 7) connect _WIRE_88.px, _T_1303 node _T_1304 = bits(_WIRE_89, 8, 8) connect _WIRE_88.pw, _T_1304 node _T_1305 = bits(_WIRE_89, 9, 9) connect _WIRE_88.hr, _T_1305 node _T_1306 = bits(_WIRE_89, 10, 10) connect _WIRE_88.hx, _T_1306 node _T_1307 = bits(_WIRE_89, 11, 11) connect _WIRE_88.hw, _T_1307 node _T_1308 = bits(_WIRE_89, 12, 12) connect _WIRE_88.sr, _T_1308 node _T_1309 = bits(_WIRE_89, 13, 13) connect _WIRE_88.sx, _T_1309 node _T_1310 = bits(_WIRE_89, 14, 14) connect _WIRE_88.sw, _T_1310 node _T_1311 = bits(_WIRE_89, 15, 15) connect _WIRE_88.gf, _T_1311 node _T_1312 = bits(_WIRE_89, 16, 16) connect _WIRE_88.pf, _T_1312 node _T_1313 = bits(_WIRE_89, 17, 17) connect _WIRE_88.ae_stage2, _T_1313 node _T_1314 = bits(_WIRE_89, 18, 18) connect _WIRE_88.ae_final, _T_1314 node _T_1315 = bits(_WIRE_89, 19, 19) connect _WIRE_88.ae_ptw, _T_1315 node _T_1316 = bits(_WIRE_89, 20, 20) connect _WIRE_88.g, _T_1316 node _T_1317 = bits(_WIRE_89, 21, 21) connect _WIRE_88.u, _T_1317 node _T_1318 = bits(_WIRE_89, 41, 22) connect _WIRE_88.ppn, _T_1318 node _T_1319 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1320 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1321 = and(_T_1319, _T_1320) when _T_1321 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) node _T_1322 = xor(sectored_entries[2][3].tag_vpn, vpn) node _T_1323 = shr(_T_1322, 18) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_91 : UInt<42> connect _WIRE_91, sectored_entries[2][3].data[0] node _T_1325 = bits(_WIRE_91, 0, 0) connect _WIRE_90.fragmented_superpage, _T_1325 node _T_1326 = bits(_WIRE_91, 1, 1) connect _WIRE_90.c, _T_1326 node _T_1327 = bits(_WIRE_91, 2, 2) connect _WIRE_90.eff, _T_1327 node _T_1328 = bits(_WIRE_91, 3, 3) connect _WIRE_90.paa, _T_1328 node _T_1329 = bits(_WIRE_91, 4, 4) connect _WIRE_90.pal, _T_1329 node _T_1330 = bits(_WIRE_91, 5, 5) connect _WIRE_90.ppp, _T_1330 node _T_1331 = bits(_WIRE_91, 6, 6) connect _WIRE_90.pr, _T_1331 node _T_1332 = bits(_WIRE_91, 7, 7) connect _WIRE_90.px, _T_1332 node _T_1333 = bits(_WIRE_91, 8, 8) connect _WIRE_90.pw, _T_1333 node _T_1334 = bits(_WIRE_91, 9, 9) connect _WIRE_90.hr, _T_1334 node _T_1335 = bits(_WIRE_91, 10, 10) connect _WIRE_90.hx, _T_1335 node _T_1336 = bits(_WIRE_91, 11, 11) connect _WIRE_90.hw, _T_1336 node _T_1337 = bits(_WIRE_91, 12, 12) connect _WIRE_90.sr, _T_1337 node _T_1338 = bits(_WIRE_91, 13, 13) connect _WIRE_90.sx, _T_1338 node _T_1339 = bits(_WIRE_91, 14, 14) connect _WIRE_90.sw, _T_1339 node _T_1340 = bits(_WIRE_91, 15, 15) connect _WIRE_90.gf, _T_1340 node _T_1341 = bits(_WIRE_91, 16, 16) connect _WIRE_90.pf, _T_1341 node _T_1342 = bits(_WIRE_91, 17, 17) connect _WIRE_90.ae_stage2, _T_1342 node _T_1343 = bits(_WIRE_91, 18, 18) connect _WIRE_90.ae_final, _T_1343 node _T_1344 = bits(_WIRE_91, 19, 19) connect _WIRE_90.ae_ptw, _T_1344 node _T_1345 = bits(_WIRE_91, 20, 20) connect _WIRE_90.g, _T_1345 node _T_1346 = bits(_WIRE_91, 21, 21) connect _WIRE_90.u, _T_1346 node _T_1347 = bits(_WIRE_91, 41, 22) connect _WIRE_90.ppn, _T_1347 node _T_1348 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1349 = and(_T_1348, _WIRE_90.fragmented_superpage) when _T_1349 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) else : node _T_1350 = eq(hg_11, UInt<1>(0h0)) node _T_1351 = and(_T_1350, io.sfence.bits.rs2) when _T_1351 : wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_93 : UInt<42> connect _WIRE_93, sectored_entries[2][3].data[0] node _T_1352 = bits(_WIRE_93, 0, 0) connect _WIRE_92.fragmented_superpage, _T_1352 node _T_1353 = bits(_WIRE_93, 1, 1) connect _WIRE_92.c, _T_1353 node _T_1354 = bits(_WIRE_93, 2, 2) connect _WIRE_92.eff, _T_1354 node _T_1355 = bits(_WIRE_93, 3, 3) connect _WIRE_92.paa, _T_1355 node _T_1356 = bits(_WIRE_93, 4, 4) connect _WIRE_92.pal, _T_1356 node _T_1357 = bits(_WIRE_93, 5, 5) connect _WIRE_92.ppp, _T_1357 node _T_1358 = bits(_WIRE_93, 6, 6) connect _WIRE_92.pr, _T_1358 node _T_1359 = bits(_WIRE_93, 7, 7) connect _WIRE_92.px, _T_1359 node _T_1360 = bits(_WIRE_93, 8, 8) connect _WIRE_92.pw, _T_1360 node _T_1361 = bits(_WIRE_93, 9, 9) connect _WIRE_92.hr, _T_1361 node _T_1362 = bits(_WIRE_93, 10, 10) connect _WIRE_92.hx, _T_1362 node _T_1363 = bits(_WIRE_93, 11, 11) connect _WIRE_92.hw, _T_1363 node _T_1364 = bits(_WIRE_93, 12, 12) connect _WIRE_92.sr, _T_1364 node _T_1365 = bits(_WIRE_93, 13, 13) connect _WIRE_92.sx, _T_1365 node _T_1366 = bits(_WIRE_93, 14, 14) connect _WIRE_92.sw, _T_1366 node _T_1367 = bits(_WIRE_93, 15, 15) connect _WIRE_92.gf, _T_1367 node _T_1368 = bits(_WIRE_93, 16, 16) connect _WIRE_92.pf, _T_1368 node _T_1369 = bits(_WIRE_93, 17, 17) connect _WIRE_92.ae_stage2, _T_1369 node _T_1370 = bits(_WIRE_93, 18, 18) connect _WIRE_92.ae_final, _T_1370 node _T_1371 = bits(_WIRE_93, 19, 19) connect _WIRE_92.ae_ptw, _T_1371 node _T_1372 = bits(_WIRE_93, 20, 20) connect _WIRE_92.g, _T_1372 node _T_1373 = bits(_WIRE_93, 21, 21) connect _WIRE_92.u, _T_1373 node _T_1374 = bits(_WIRE_93, 41, 22) connect _WIRE_92.ppn, _T_1374 node _T_1375 = eq(sectored_entries[2][3].tag_v, hv_11) node _T_1376 = eq(_WIRE_92.g, UInt<1>(0h0)) node _T_1377 = and(_T_1375, _T_1376) when _T_1377 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) else : node _T_1378 = or(hv_11, hg_11) wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_95 : UInt<42> connect _WIRE_95, sectored_entries[2][3].data[0] node _T_1379 = bits(_WIRE_95, 0, 0) connect _WIRE_94.fragmented_superpage, _T_1379 node _T_1380 = bits(_WIRE_95, 1, 1) connect _WIRE_94.c, _T_1380 node _T_1381 = bits(_WIRE_95, 2, 2) connect _WIRE_94.eff, _T_1381 node _T_1382 = bits(_WIRE_95, 3, 3) connect _WIRE_94.paa, _T_1382 node _T_1383 = bits(_WIRE_95, 4, 4) connect _WIRE_94.pal, _T_1383 node _T_1384 = bits(_WIRE_95, 5, 5) connect _WIRE_94.ppp, _T_1384 node _T_1385 = bits(_WIRE_95, 6, 6) connect _WIRE_94.pr, _T_1385 node _T_1386 = bits(_WIRE_95, 7, 7) connect _WIRE_94.px, _T_1386 node _T_1387 = bits(_WIRE_95, 8, 8) connect _WIRE_94.pw, _T_1387 node _T_1388 = bits(_WIRE_95, 9, 9) connect _WIRE_94.hr, _T_1388 node _T_1389 = bits(_WIRE_95, 10, 10) connect _WIRE_94.hx, _T_1389 node _T_1390 = bits(_WIRE_95, 11, 11) connect _WIRE_94.hw, _T_1390 node _T_1391 = bits(_WIRE_95, 12, 12) connect _WIRE_94.sr, _T_1391 node _T_1392 = bits(_WIRE_95, 13, 13) connect _WIRE_94.sx, _T_1392 node _T_1393 = bits(_WIRE_95, 14, 14) connect _WIRE_94.sw, _T_1393 node _T_1394 = bits(_WIRE_95, 15, 15) connect _WIRE_94.gf, _T_1394 node _T_1395 = bits(_WIRE_95, 16, 16) connect _WIRE_94.pf, _T_1395 node _T_1396 = bits(_WIRE_95, 17, 17) connect _WIRE_94.ae_stage2, _T_1396 node _T_1397 = bits(_WIRE_95, 18, 18) connect _WIRE_94.ae_final, _T_1397 node _T_1398 = bits(_WIRE_95, 19, 19) connect _WIRE_94.ae_ptw, _T_1398 node _T_1399 = bits(_WIRE_95, 20, 20) connect _WIRE_94.g, _T_1399 node _T_1400 = bits(_WIRE_95, 21, 21) connect _WIRE_94.u, _T_1400 node _T_1401 = bits(_WIRE_95, 41, 22) connect _WIRE_94.ppn, _T_1401 node _T_1402 = eq(sectored_entries[2][3].tag_v, _T_1378) when _T_1402 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1403 = eq(hg_12, UInt<1>(0h0)) node _T_1404 = and(_T_1403, io.sfence.bits.rs1) when _T_1404 : node _T_1405 = xor(sectored_entries[3][0].tag_vpn, vpn) node _T_1406 = shr(_T_1405, 0) node _T_1407 = eq(_T_1406, UInt<1>(0h0)) node _T_1408 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1409 = and(_T_1407, _T_1408) when _T_1409 : wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_97 : UInt<42> connect _WIRE_97, sectored_entries[3][0].data[0] node _T_1410 = bits(_WIRE_97, 0, 0) connect _WIRE_96.fragmented_superpage, _T_1410 node _T_1411 = bits(_WIRE_97, 1, 1) connect _WIRE_96.c, _T_1411 node _T_1412 = bits(_WIRE_97, 2, 2) connect _WIRE_96.eff, _T_1412 node _T_1413 = bits(_WIRE_97, 3, 3) connect _WIRE_96.paa, _T_1413 node _T_1414 = bits(_WIRE_97, 4, 4) connect _WIRE_96.pal, _T_1414 node _T_1415 = bits(_WIRE_97, 5, 5) connect _WIRE_96.ppp, _T_1415 node _T_1416 = bits(_WIRE_97, 6, 6) connect _WIRE_96.pr, _T_1416 node _T_1417 = bits(_WIRE_97, 7, 7) connect _WIRE_96.px, _T_1417 node _T_1418 = bits(_WIRE_97, 8, 8) connect _WIRE_96.pw, _T_1418 node _T_1419 = bits(_WIRE_97, 9, 9) connect _WIRE_96.hr, _T_1419 node _T_1420 = bits(_WIRE_97, 10, 10) connect _WIRE_96.hx, _T_1420 node _T_1421 = bits(_WIRE_97, 11, 11) connect _WIRE_96.hw, _T_1421 node _T_1422 = bits(_WIRE_97, 12, 12) connect _WIRE_96.sr, _T_1422 node _T_1423 = bits(_WIRE_97, 13, 13) connect _WIRE_96.sx, _T_1423 node _T_1424 = bits(_WIRE_97, 14, 14) connect _WIRE_96.sw, _T_1424 node _T_1425 = bits(_WIRE_97, 15, 15) connect _WIRE_96.gf, _T_1425 node _T_1426 = bits(_WIRE_97, 16, 16) connect _WIRE_96.pf, _T_1426 node _T_1427 = bits(_WIRE_97, 17, 17) connect _WIRE_96.ae_stage2, _T_1427 node _T_1428 = bits(_WIRE_97, 18, 18) connect _WIRE_96.ae_final, _T_1428 node _T_1429 = bits(_WIRE_97, 19, 19) connect _WIRE_96.ae_ptw, _T_1429 node _T_1430 = bits(_WIRE_97, 20, 20) connect _WIRE_96.g, _T_1430 node _T_1431 = bits(_WIRE_97, 21, 21) connect _WIRE_96.u, _T_1431 node _T_1432 = bits(_WIRE_97, 41, 22) connect _WIRE_96.ppn, _T_1432 node _T_1433 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1434 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1435 = and(_T_1433, _T_1434) when _T_1435 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) node _T_1436 = xor(sectored_entries[3][0].tag_vpn, vpn) node _T_1437 = shr(_T_1436, 18) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) when _T_1438 : wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_99 : UInt<42> connect _WIRE_99, sectored_entries[3][0].data[0] node _T_1439 = bits(_WIRE_99, 0, 0) connect _WIRE_98.fragmented_superpage, _T_1439 node _T_1440 = bits(_WIRE_99, 1, 1) connect _WIRE_98.c, _T_1440 node _T_1441 = bits(_WIRE_99, 2, 2) connect _WIRE_98.eff, _T_1441 node _T_1442 = bits(_WIRE_99, 3, 3) connect _WIRE_98.paa, _T_1442 node _T_1443 = bits(_WIRE_99, 4, 4) connect _WIRE_98.pal, _T_1443 node _T_1444 = bits(_WIRE_99, 5, 5) connect _WIRE_98.ppp, _T_1444 node _T_1445 = bits(_WIRE_99, 6, 6) connect _WIRE_98.pr, _T_1445 node _T_1446 = bits(_WIRE_99, 7, 7) connect _WIRE_98.px, _T_1446 node _T_1447 = bits(_WIRE_99, 8, 8) connect _WIRE_98.pw, _T_1447 node _T_1448 = bits(_WIRE_99, 9, 9) connect _WIRE_98.hr, _T_1448 node _T_1449 = bits(_WIRE_99, 10, 10) connect _WIRE_98.hx, _T_1449 node _T_1450 = bits(_WIRE_99, 11, 11) connect _WIRE_98.hw, _T_1450 node _T_1451 = bits(_WIRE_99, 12, 12) connect _WIRE_98.sr, _T_1451 node _T_1452 = bits(_WIRE_99, 13, 13) connect _WIRE_98.sx, _T_1452 node _T_1453 = bits(_WIRE_99, 14, 14) connect _WIRE_98.sw, _T_1453 node _T_1454 = bits(_WIRE_99, 15, 15) connect _WIRE_98.gf, _T_1454 node _T_1455 = bits(_WIRE_99, 16, 16) connect _WIRE_98.pf, _T_1455 node _T_1456 = bits(_WIRE_99, 17, 17) connect _WIRE_98.ae_stage2, _T_1456 node _T_1457 = bits(_WIRE_99, 18, 18) connect _WIRE_98.ae_final, _T_1457 node _T_1458 = bits(_WIRE_99, 19, 19) connect _WIRE_98.ae_ptw, _T_1458 node _T_1459 = bits(_WIRE_99, 20, 20) connect _WIRE_98.g, _T_1459 node _T_1460 = bits(_WIRE_99, 21, 21) connect _WIRE_98.u, _T_1460 node _T_1461 = bits(_WIRE_99, 41, 22) connect _WIRE_98.ppn, _T_1461 node _T_1462 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1463 = and(_T_1462, _WIRE_98.fragmented_superpage) when _T_1463 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) else : node _T_1464 = eq(hg_12, UInt<1>(0h0)) node _T_1465 = and(_T_1464, io.sfence.bits.rs2) when _T_1465 : wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_101 : UInt<42> connect _WIRE_101, sectored_entries[3][0].data[0] node _T_1466 = bits(_WIRE_101, 0, 0) connect _WIRE_100.fragmented_superpage, _T_1466 node _T_1467 = bits(_WIRE_101, 1, 1) connect _WIRE_100.c, _T_1467 node _T_1468 = bits(_WIRE_101, 2, 2) connect _WIRE_100.eff, _T_1468 node _T_1469 = bits(_WIRE_101, 3, 3) connect _WIRE_100.paa, _T_1469 node _T_1470 = bits(_WIRE_101, 4, 4) connect _WIRE_100.pal, _T_1470 node _T_1471 = bits(_WIRE_101, 5, 5) connect _WIRE_100.ppp, _T_1471 node _T_1472 = bits(_WIRE_101, 6, 6) connect _WIRE_100.pr, _T_1472 node _T_1473 = bits(_WIRE_101, 7, 7) connect _WIRE_100.px, _T_1473 node _T_1474 = bits(_WIRE_101, 8, 8) connect _WIRE_100.pw, _T_1474 node _T_1475 = bits(_WIRE_101, 9, 9) connect _WIRE_100.hr, _T_1475 node _T_1476 = bits(_WIRE_101, 10, 10) connect _WIRE_100.hx, _T_1476 node _T_1477 = bits(_WIRE_101, 11, 11) connect _WIRE_100.hw, _T_1477 node _T_1478 = bits(_WIRE_101, 12, 12) connect _WIRE_100.sr, _T_1478 node _T_1479 = bits(_WIRE_101, 13, 13) connect _WIRE_100.sx, _T_1479 node _T_1480 = bits(_WIRE_101, 14, 14) connect _WIRE_100.sw, _T_1480 node _T_1481 = bits(_WIRE_101, 15, 15) connect _WIRE_100.gf, _T_1481 node _T_1482 = bits(_WIRE_101, 16, 16) connect _WIRE_100.pf, _T_1482 node _T_1483 = bits(_WIRE_101, 17, 17) connect _WIRE_100.ae_stage2, _T_1483 node _T_1484 = bits(_WIRE_101, 18, 18) connect _WIRE_100.ae_final, _T_1484 node _T_1485 = bits(_WIRE_101, 19, 19) connect _WIRE_100.ae_ptw, _T_1485 node _T_1486 = bits(_WIRE_101, 20, 20) connect _WIRE_100.g, _T_1486 node _T_1487 = bits(_WIRE_101, 21, 21) connect _WIRE_100.u, _T_1487 node _T_1488 = bits(_WIRE_101, 41, 22) connect _WIRE_100.ppn, _T_1488 node _T_1489 = eq(sectored_entries[3][0].tag_v, hv_12) node _T_1490 = eq(_WIRE_100.g, UInt<1>(0h0)) node _T_1491 = and(_T_1489, _T_1490) when _T_1491 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) else : node _T_1492 = or(hv_12, hg_12) wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_103 : UInt<42> connect _WIRE_103, sectored_entries[3][0].data[0] node _T_1493 = bits(_WIRE_103, 0, 0) connect _WIRE_102.fragmented_superpage, _T_1493 node _T_1494 = bits(_WIRE_103, 1, 1) connect _WIRE_102.c, _T_1494 node _T_1495 = bits(_WIRE_103, 2, 2) connect _WIRE_102.eff, _T_1495 node _T_1496 = bits(_WIRE_103, 3, 3) connect _WIRE_102.paa, _T_1496 node _T_1497 = bits(_WIRE_103, 4, 4) connect _WIRE_102.pal, _T_1497 node _T_1498 = bits(_WIRE_103, 5, 5) connect _WIRE_102.ppp, _T_1498 node _T_1499 = bits(_WIRE_103, 6, 6) connect _WIRE_102.pr, _T_1499 node _T_1500 = bits(_WIRE_103, 7, 7) connect _WIRE_102.px, _T_1500 node _T_1501 = bits(_WIRE_103, 8, 8) connect _WIRE_102.pw, _T_1501 node _T_1502 = bits(_WIRE_103, 9, 9) connect _WIRE_102.hr, _T_1502 node _T_1503 = bits(_WIRE_103, 10, 10) connect _WIRE_102.hx, _T_1503 node _T_1504 = bits(_WIRE_103, 11, 11) connect _WIRE_102.hw, _T_1504 node _T_1505 = bits(_WIRE_103, 12, 12) connect _WIRE_102.sr, _T_1505 node _T_1506 = bits(_WIRE_103, 13, 13) connect _WIRE_102.sx, _T_1506 node _T_1507 = bits(_WIRE_103, 14, 14) connect _WIRE_102.sw, _T_1507 node _T_1508 = bits(_WIRE_103, 15, 15) connect _WIRE_102.gf, _T_1508 node _T_1509 = bits(_WIRE_103, 16, 16) connect _WIRE_102.pf, _T_1509 node _T_1510 = bits(_WIRE_103, 17, 17) connect _WIRE_102.ae_stage2, _T_1510 node _T_1511 = bits(_WIRE_103, 18, 18) connect _WIRE_102.ae_final, _T_1511 node _T_1512 = bits(_WIRE_103, 19, 19) connect _WIRE_102.ae_ptw, _T_1512 node _T_1513 = bits(_WIRE_103, 20, 20) connect _WIRE_102.g, _T_1513 node _T_1514 = bits(_WIRE_103, 21, 21) connect _WIRE_102.u, _T_1514 node _T_1515 = bits(_WIRE_103, 41, 22) connect _WIRE_102.ppn, _T_1515 node _T_1516 = eq(sectored_entries[3][0].tag_v, _T_1492) when _T_1516 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) node hv_13 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_13 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1517 = eq(hg_13, UInt<1>(0h0)) node _T_1518 = and(_T_1517, io.sfence.bits.rs1) when _T_1518 : node _T_1519 = xor(sectored_entries[3][1].tag_vpn, vpn) node _T_1520 = shr(_T_1519, 0) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) node _T_1522 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1523 = and(_T_1521, _T_1522) when _T_1523 : wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_105 : UInt<42> connect _WIRE_105, sectored_entries[3][1].data[0] node _T_1524 = bits(_WIRE_105, 0, 0) connect _WIRE_104.fragmented_superpage, _T_1524 node _T_1525 = bits(_WIRE_105, 1, 1) connect _WIRE_104.c, _T_1525 node _T_1526 = bits(_WIRE_105, 2, 2) connect _WIRE_104.eff, _T_1526 node _T_1527 = bits(_WIRE_105, 3, 3) connect _WIRE_104.paa, _T_1527 node _T_1528 = bits(_WIRE_105, 4, 4) connect _WIRE_104.pal, _T_1528 node _T_1529 = bits(_WIRE_105, 5, 5) connect _WIRE_104.ppp, _T_1529 node _T_1530 = bits(_WIRE_105, 6, 6) connect _WIRE_104.pr, _T_1530 node _T_1531 = bits(_WIRE_105, 7, 7) connect _WIRE_104.px, _T_1531 node _T_1532 = bits(_WIRE_105, 8, 8) connect _WIRE_104.pw, _T_1532 node _T_1533 = bits(_WIRE_105, 9, 9) connect _WIRE_104.hr, _T_1533 node _T_1534 = bits(_WIRE_105, 10, 10) connect _WIRE_104.hx, _T_1534 node _T_1535 = bits(_WIRE_105, 11, 11) connect _WIRE_104.hw, _T_1535 node _T_1536 = bits(_WIRE_105, 12, 12) connect _WIRE_104.sr, _T_1536 node _T_1537 = bits(_WIRE_105, 13, 13) connect _WIRE_104.sx, _T_1537 node _T_1538 = bits(_WIRE_105, 14, 14) connect _WIRE_104.sw, _T_1538 node _T_1539 = bits(_WIRE_105, 15, 15) connect _WIRE_104.gf, _T_1539 node _T_1540 = bits(_WIRE_105, 16, 16) connect _WIRE_104.pf, _T_1540 node _T_1541 = bits(_WIRE_105, 17, 17) connect _WIRE_104.ae_stage2, _T_1541 node _T_1542 = bits(_WIRE_105, 18, 18) connect _WIRE_104.ae_final, _T_1542 node _T_1543 = bits(_WIRE_105, 19, 19) connect _WIRE_104.ae_ptw, _T_1543 node _T_1544 = bits(_WIRE_105, 20, 20) connect _WIRE_104.g, _T_1544 node _T_1545 = bits(_WIRE_105, 21, 21) connect _WIRE_104.u, _T_1545 node _T_1546 = bits(_WIRE_105, 41, 22) connect _WIRE_104.ppn, _T_1546 node _T_1547 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1548 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1549 = and(_T_1547, _T_1548) when _T_1549 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) node _T_1550 = xor(sectored_entries[3][1].tag_vpn, vpn) node _T_1551 = shr(_T_1550, 18) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_107 : UInt<42> connect _WIRE_107, sectored_entries[3][1].data[0] node _T_1553 = bits(_WIRE_107, 0, 0) connect _WIRE_106.fragmented_superpage, _T_1553 node _T_1554 = bits(_WIRE_107, 1, 1) connect _WIRE_106.c, _T_1554 node _T_1555 = bits(_WIRE_107, 2, 2) connect _WIRE_106.eff, _T_1555 node _T_1556 = bits(_WIRE_107, 3, 3) connect _WIRE_106.paa, _T_1556 node _T_1557 = bits(_WIRE_107, 4, 4) connect _WIRE_106.pal, _T_1557 node _T_1558 = bits(_WIRE_107, 5, 5) connect _WIRE_106.ppp, _T_1558 node _T_1559 = bits(_WIRE_107, 6, 6) connect _WIRE_106.pr, _T_1559 node _T_1560 = bits(_WIRE_107, 7, 7) connect _WIRE_106.px, _T_1560 node _T_1561 = bits(_WIRE_107, 8, 8) connect _WIRE_106.pw, _T_1561 node _T_1562 = bits(_WIRE_107, 9, 9) connect _WIRE_106.hr, _T_1562 node _T_1563 = bits(_WIRE_107, 10, 10) connect _WIRE_106.hx, _T_1563 node _T_1564 = bits(_WIRE_107, 11, 11) connect _WIRE_106.hw, _T_1564 node _T_1565 = bits(_WIRE_107, 12, 12) connect _WIRE_106.sr, _T_1565 node _T_1566 = bits(_WIRE_107, 13, 13) connect _WIRE_106.sx, _T_1566 node _T_1567 = bits(_WIRE_107, 14, 14) connect _WIRE_106.sw, _T_1567 node _T_1568 = bits(_WIRE_107, 15, 15) connect _WIRE_106.gf, _T_1568 node _T_1569 = bits(_WIRE_107, 16, 16) connect _WIRE_106.pf, _T_1569 node _T_1570 = bits(_WIRE_107, 17, 17) connect _WIRE_106.ae_stage2, _T_1570 node _T_1571 = bits(_WIRE_107, 18, 18) connect _WIRE_106.ae_final, _T_1571 node _T_1572 = bits(_WIRE_107, 19, 19) connect _WIRE_106.ae_ptw, _T_1572 node _T_1573 = bits(_WIRE_107, 20, 20) connect _WIRE_106.g, _T_1573 node _T_1574 = bits(_WIRE_107, 21, 21) connect _WIRE_106.u, _T_1574 node _T_1575 = bits(_WIRE_107, 41, 22) connect _WIRE_106.ppn, _T_1575 node _T_1576 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1577 = and(_T_1576, _WIRE_106.fragmented_superpage) when _T_1577 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) else : node _T_1578 = eq(hg_13, UInt<1>(0h0)) node _T_1579 = and(_T_1578, io.sfence.bits.rs2) when _T_1579 : wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_109 : UInt<42> connect _WIRE_109, sectored_entries[3][1].data[0] node _T_1580 = bits(_WIRE_109, 0, 0) connect _WIRE_108.fragmented_superpage, _T_1580 node _T_1581 = bits(_WIRE_109, 1, 1) connect _WIRE_108.c, _T_1581 node _T_1582 = bits(_WIRE_109, 2, 2) connect _WIRE_108.eff, _T_1582 node _T_1583 = bits(_WIRE_109, 3, 3) connect _WIRE_108.paa, _T_1583 node _T_1584 = bits(_WIRE_109, 4, 4) connect _WIRE_108.pal, _T_1584 node _T_1585 = bits(_WIRE_109, 5, 5) connect _WIRE_108.ppp, _T_1585 node _T_1586 = bits(_WIRE_109, 6, 6) connect _WIRE_108.pr, _T_1586 node _T_1587 = bits(_WIRE_109, 7, 7) connect _WIRE_108.px, _T_1587 node _T_1588 = bits(_WIRE_109, 8, 8) connect _WIRE_108.pw, _T_1588 node _T_1589 = bits(_WIRE_109, 9, 9) connect _WIRE_108.hr, _T_1589 node _T_1590 = bits(_WIRE_109, 10, 10) connect _WIRE_108.hx, _T_1590 node _T_1591 = bits(_WIRE_109, 11, 11) connect _WIRE_108.hw, _T_1591 node _T_1592 = bits(_WIRE_109, 12, 12) connect _WIRE_108.sr, _T_1592 node _T_1593 = bits(_WIRE_109, 13, 13) connect _WIRE_108.sx, _T_1593 node _T_1594 = bits(_WIRE_109, 14, 14) connect _WIRE_108.sw, _T_1594 node _T_1595 = bits(_WIRE_109, 15, 15) connect _WIRE_108.gf, _T_1595 node _T_1596 = bits(_WIRE_109, 16, 16) connect _WIRE_108.pf, _T_1596 node _T_1597 = bits(_WIRE_109, 17, 17) connect _WIRE_108.ae_stage2, _T_1597 node _T_1598 = bits(_WIRE_109, 18, 18) connect _WIRE_108.ae_final, _T_1598 node _T_1599 = bits(_WIRE_109, 19, 19) connect _WIRE_108.ae_ptw, _T_1599 node _T_1600 = bits(_WIRE_109, 20, 20) connect _WIRE_108.g, _T_1600 node _T_1601 = bits(_WIRE_109, 21, 21) connect _WIRE_108.u, _T_1601 node _T_1602 = bits(_WIRE_109, 41, 22) connect _WIRE_108.ppn, _T_1602 node _T_1603 = eq(sectored_entries[3][1].tag_v, hv_13) node _T_1604 = eq(_WIRE_108.g, UInt<1>(0h0)) node _T_1605 = and(_T_1603, _T_1604) when _T_1605 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) else : node _T_1606 = or(hv_13, hg_13) wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_111 : UInt<42> connect _WIRE_111, sectored_entries[3][1].data[0] node _T_1607 = bits(_WIRE_111, 0, 0) connect _WIRE_110.fragmented_superpage, _T_1607 node _T_1608 = bits(_WIRE_111, 1, 1) connect _WIRE_110.c, _T_1608 node _T_1609 = bits(_WIRE_111, 2, 2) connect _WIRE_110.eff, _T_1609 node _T_1610 = bits(_WIRE_111, 3, 3) connect _WIRE_110.paa, _T_1610 node _T_1611 = bits(_WIRE_111, 4, 4) connect _WIRE_110.pal, _T_1611 node _T_1612 = bits(_WIRE_111, 5, 5) connect _WIRE_110.ppp, _T_1612 node _T_1613 = bits(_WIRE_111, 6, 6) connect _WIRE_110.pr, _T_1613 node _T_1614 = bits(_WIRE_111, 7, 7) connect _WIRE_110.px, _T_1614 node _T_1615 = bits(_WIRE_111, 8, 8) connect _WIRE_110.pw, _T_1615 node _T_1616 = bits(_WIRE_111, 9, 9) connect _WIRE_110.hr, _T_1616 node _T_1617 = bits(_WIRE_111, 10, 10) connect _WIRE_110.hx, _T_1617 node _T_1618 = bits(_WIRE_111, 11, 11) connect _WIRE_110.hw, _T_1618 node _T_1619 = bits(_WIRE_111, 12, 12) connect _WIRE_110.sr, _T_1619 node _T_1620 = bits(_WIRE_111, 13, 13) connect _WIRE_110.sx, _T_1620 node _T_1621 = bits(_WIRE_111, 14, 14) connect _WIRE_110.sw, _T_1621 node _T_1622 = bits(_WIRE_111, 15, 15) connect _WIRE_110.gf, _T_1622 node _T_1623 = bits(_WIRE_111, 16, 16) connect _WIRE_110.pf, _T_1623 node _T_1624 = bits(_WIRE_111, 17, 17) connect _WIRE_110.ae_stage2, _T_1624 node _T_1625 = bits(_WIRE_111, 18, 18) connect _WIRE_110.ae_final, _T_1625 node _T_1626 = bits(_WIRE_111, 19, 19) connect _WIRE_110.ae_ptw, _T_1626 node _T_1627 = bits(_WIRE_111, 20, 20) connect _WIRE_110.g, _T_1627 node _T_1628 = bits(_WIRE_111, 21, 21) connect _WIRE_110.u, _T_1628 node _T_1629 = bits(_WIRE_111, 41, 22) connect _WIRE_110.ppn, _T_1629 node _T_1630 = eq(sectored_entries[3][1].tag_v, _T_1606) when _T_1630 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) node hv_14 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_14 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1631 = eq(hg_14, UInt<1>(0h0)) node _T_1632 = and(_T_1631, io.sfence.bits.rs1) when _T_1632 : node _T_1633 = xor(sectored_entries[3][2].tag_vpn, vpn) node _T_1634 = shr(_T_1633, 0) node _T_1635 = eq(_T_1634, UInt<1>(0h0)) node _T_1636 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1637 = and(_T_1635, _T_1636) when _T_1637 : wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_113 : UInt<42> connect _WIRE_113, sectored_entries[3][2].data[0] node _T_1638 = bits(_WIRE_113, 0, 0) connect _WIRE_112.fragmented_superpage, _T_1638 node _T_1639 = bits(_WIRE_113, 1, 1) connect _WIRE_112.c, _T_1639 node _T_1640 = bits(_WIRE_113, 2, 2) connect _WIRE_112.eff, _T_1640 node _T_1641 = bits(_WIRE_113, 3, 3) connect _WIRE_112.paa, _T_1641 node _T_1642 = bits(_WIRE_113, 4, 4) connect _WIRE_112.pal, _T_1642 node _T_1643 = bits(_WIRE_113, 5, 5) connect _WIRE_112.ppp, _T_1643 node _T_1644 = bits(_WIRE_113, 6, 6) connect _WIRE_112.pr, _T_1644 node _T_1645 = bits(_WIRE_113, 7, 7) connect _WIRE_112.px, _T_1645 node _T_1646 = bits(_WIRE_113, 8, 8) connect _WIRE_112.pw, _T_1646 node _T_1647 = bits(_WIRE_113, 9, 9) connect _WIRE_112.hr, _T_1647 node _T_1648 = bits(_WIRE_113, 10, 10) connect _WIRE_112.hx, _T_1648 node _T_1649 = bits(_WIRE_113, 11, 11) connect _WIRE_112.hw, _T_1649 node _T_1650 = bits(_WIRE_113, 12, 12) connect _WIRE_112.sr, _T_1650 node _T_1651 = bits(_WIRE_113, 13, 13) connect _WIRE_112.sx, _T_1651 node _T_1652 = bits(_WIRE_113, 14, 14) connect _WIRE_112.sw, _T_1652 node _T_1653 = bits(_WIRE_113, 15, 15) connect _WIRE_112.gf, _T_1653 node _T_1654 = bits(_WIRE_113, 16, 16) connect _WIRE_112.pf, _T_1654 node _T_1655 = bits(_WIRE_113, 17, 17) connect _WIRE_112.ae_stage2, _T_1655 node _T_1656 = bits(_WIRE_113, 18, 18) connect _WIRE_112.ae_final, _T_1656 node _T_1657 = bits(_WIRE_113, 19, 19) connect _WIRE_112.ae_ptw, _T_1657 node _T_1658 = bits(_WIRE_113, 20, 20) connect _WIRE_112.g, _T_1658 node _T_1659 = bits(_WIRE_113, 21, 21) connect _WIRE_112.u, _T_1659 node _T_1660 = bits(_WIRE_113, 41, 22) connect _WIRE_112.ppn, _T_1660 node _T_1661 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1662 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1663 = and(_T_1661, _T_1662) when _T_1663 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) node _T_1664 = xor(sectored_entries[3][2].tag_vpn, vpn) node _T_1665 = shr(_T_1664, 18) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_115 : UInt<42> connect _WIRE_115, sectored_entries[3][2].data[0] node _T_1667 = bits(_WIRE_115, 0, 0) connect _WIRE_114.fragmented_superpage, _T_1667 node _T_1668 = bits(_WIRE_115, 1, 1) connect _WIRE_114.c, _T_1668 node _T_1669 = bits(_WIRE_115, 2, 2) connect _WIRE_114.eff, _T_1669 node _T_1670 = bits(_WIRE_115, 3, 3) connect _WIRE_114.paa, _T_1670 node _T_1671 = bits(_WIRE_115, 4, 4) connect _WIRE_114.pal, _T_1671 node _T_1672 = bits(_WIRE_115, 5, 5) connect _WIRE_114.ppp, _T_1672 node _T_1673 = bits(_WIRE_115, 6, 6) connect _WIRE_114.pr, _T_1673 node _T_1674 = bits(_WIRE_115, 7, 7) connect _WIRE_114.px, _T_1674 node _T_1675 = bits(_WIRE_115, 8, 8) connect _WIRE_114.pw, _T_1675 node _T_1676 = bits(_WIRE_115, 9, 9) connect _WIRE_114.hr, _T_1676 node _T_1677 = bits(_WIRE_115, 10, 10) connect _WIRE_114.hx, _T_1677 node _T_1678 = bits(_WIRE_115, 11, 11) connect _WIRE_114.hw, _T_1678 node _T_1679 = bits(_WIRE_115, 12, 12) connect _WIRE_114.sr, _T_1679 node _T_1680 = bits(_WIRE_115, 13, 13) connect _WIRE_114.sx, _T_1680 node _T_1681 = bits(_WIRE_115, 14, 14) connect _WIRE_114.sw, _T_1681 node _T_1682 = bits(_WIRE_115, 15, 15) connect _WIRE_114.gf, _T_1682 node _T_1683 = bits(_WIRE_115, 16, 16) connect _WIRE_114.pf, _T_1683 node _T_1684 = bits(_WIRE_115, 17, 17) connect _WIRE_114.ae_stage2, _T_1684 node _T_1685 = bits(_WIRE_115, 18, 18) connect _WIRE_114.ae_final, _T_1685 node _T_1686 = bits(_WIRE_115, 19, 19) connect _WIRE_114.ae_ptw, _T_1686 node _T_1687 = bits(_WIRE_115, 20, 20) connect _WIRE_114.g, _T_1687 node _T_1688 = bits(_WIRE_115, 21, 21) connect _WIRE_114.u, _T_1688 node _T_1689 = bits(_WIRE_115, 41, 22) connect _WIRE_114.ppn, _T_1689 node _T_1690 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1691 = and(_T_1690, _WIRE_114.fragmented_superpage) when _T_1691 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) else : node _T_1692 = eq(hg_14, UInt<1>(0h0)) node _T_1693 = and(_T_1692, io.sfence.bits.rs2) when _T_1693 : wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_117 : UInt<42> connect _WIRE_117, sectored_entries[3][2].data[0] node _T_1694 = bits(_WIRE_117, 0, 0) connect _WIRE_116.fragmented_superpage, _T_1694 node _T_1695 = bits(_WIRE_117, 1, 1) connect _WIRE_116.c, _T_1695 node _T_1696 = bits(_WIRE_117, 2, 2) connect _WIRE_116.eff, _T_1696 node _T_1697 = bits(_WIRE_117, 3, 3) connect _WIRE_116.paa, _T_1697 node _T_1698 = bits(_WIRE_117, 4, 4) connect _WIRE_116.pal, _T_1698 node _T_1699 = bits(_WIRE_117, 5, 5) connect _WIRE_116.ppp, _T_1699 node _T_1700 = bits(_WIRE_117, 6, 6) connect _WIRE_116.pr, _T_1700 node _T_1701 = bits(_WIRE_117, 7, 7) connect _WIRE_116.px, _T_1701 node _T_1702 = bits(_WIRE_117, 8, 8) connect _WIRE_116.pw, _T_1702 node _T_1703 = bits(_WIRE_117, 9, 9) connect _WIRE_116.hr, _T_1703 node _T_1704 = bits(_WIRE_117, 10, 10) connect _WIRE_116.hx, _T_1704 node _T_1705 = bits(_WIRE_117, 11, 11) connect _WIRE_116.hw, _T_1705 node _T_1706 = bits(_WIRE_117, 12, 12) connect _WIRE_116.sr, _T_1706 node _T_1707 = bits(_WIRE_117, 13, 13) connect _WIRE_116.sx, _T_1707 node _T_1708 = bits(_WIRE_117, 14, 14) connect _WIRE_116.sw, _T_1708 node _T_1709 = bits(_WIRE_117, 15, 15) connect _WIRE_116.gf, _T_1709 node _T_1710 = bits(_WIRE_117, 16, 16) connect _WIRE_116.pf, _T_1710 node _T_1711 = bits(_WIRE_117, 17, 17) connect _WIRE_116.ae_stage2, _T_1711 node _T_1712 = bits(_WIRE_117, 18, 18) connect _WIRE_116.ae_final, _T_1712 node _T_1713 = bits(_WIRE_117, 19, 19) connect _WIRE_116.ae_ptw, _T_1713 node _T_1714 = bits(_WIRE_117, 20, 20) connect _WIRE_116.g, _T_1714 node _T_1715 = bits(_WIRE_117, 21, 21) connect _WIRE_116.u, _T_1715 node _T_1716 = bits(_WIRE_117, 41, 22) connect _WIRE_116.ppn, _T_1716 node _T_1717 = eq(sectored_entries[3][2].tag_v, hv_14) node _T_1718 = eq(_WIRE_116.g, UInt<1>(0h0)) node _T_1719 = and(_T_1717, _T_1718) when _T_1719 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) else : node _T_1720 = or(hv_14, hg_14) wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_119 : UInt<42> connect _WIRE_119, sectored_entries[3][2].data[0] node _T_1721 = bits(_WIRE_119, 0, 0) connect _WIRE_118.fragmented_superpage, _T_1721 node _T_1722 = bits(_WIRE_119, 1, 1) connect _WIRE_118.c, _T_1722 node _T_1723 = bits(_WIRE_119, 2, 2) connect _WIRE_118.eff, _T_1723 node _T_1724 = bits(_WIRE_119, 3, 3) connect _WIRE_118.paa, _T_1724 node _T_1725 = bits(_WIRE_119, 4, 4) connect _WIRE_118.pal, _T_1725 node _T_1726 = bits(_WIRE_119, 5, 5) connect _WIRE_118.ppp, _T_1726 node _T_1727 = bits(_WIRE_119, 6, 6) connect _WIRE_118.pr, _T_1727 node _T_1728 = bits(_WIRE_119, 7, 7) connect _WIRE_118.px, _T_1728 node _T_1729 = bits(_WIRE_119, 8, 8) connect _WIRE_118.pw, _T_1729 node _T_1730 = bits(_WIRE_119, 9, 9) connect _WIRE_118.hr, _T_1730 node _T_1731 = bits(_WIRE_119, 10, 10) connect _WIRE_118.hx, _T_1731 node _T_1732 = bits(_WIRE_119, 11, 11) connect _WIRE_118.hw, _T_1732 node _T_1733 = bits(_WIRE_119, 12, 12) connect _WIRE_118.sr, _T_1733 node _T_1734 = bits(_WIRE_119, 13, 13) connect _WIRE_118.sx, _T_1734 node _T_1735 = bits(_WIRE_119, 14, 14) connect _WIRE_118.sw, _T_1735 node _T_1736 = bits(_WIRE_119, 15, 15) connect _WIRE_118.gf, _T_1736 node _T_1737 = bits(_WIRE_119, 16, 16) connect _WIRE_118.pf, _T_1737 node _T_1738 = bits(_WIRE_119, 17, 17) connect _WIRE_118.ae_stage2, _T_1738 node _T_1739 = bits(_WIRE_119, 18, 18) connect _WIRE_118.ae_final, _T_1739 node _T_1740 = bits(_WIRE_119, 19, 19) connect _WIRE_118.ae_ptw, _T_1740 node _T_1741 = bits(_WIRE_119, 20, 20) connect _WIRE_118.g, _T_1741 node _T_1742 = bits(_WIRE_119, 21, 21) connect _WIRE_118.u, _T_1742 node _T_1743 = bits(_WIRE_119, 41, 22) connect _WIRE_118.ppn, _T_1743 node _T_1744 = eq(sectored_entries[3][2].tag_v, _T_1720) when _T_1744 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) node hv_15 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_15 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1745 = eq(hg_15, UInt<1>(0h0)) node _T_1746 = and(_T_1745, io.sfence.bits.rs1) when _T_1746 : node _T_1747 = xor(sectored_entries[3][3].tag_vpn, vpn) node _T_1748 = shr(_T_1747, 0) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1751 = and(_T_1749, _T_1750) when _T_1751 : wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_121 : UInt<42> connect _WIRE_121, sectored_entries[3][3].data[0] node _T_1752 = bits(_WIRE_121, 0, 0) connect _WIRE_120.fragmented_superpage, _T_1752 node _T_1753 = bits(_WIRE_121, 1, 1) connect _WIRE_120.c, _T_1753 node _T_1754 = bits(_WIRE_121, 2, 2) connect _WIRE_120.eff, _T_1754 node _T_1755 = bits(_WIRE_121, 3, 3) connect _WIRE_120.paa, _T_1755 node _T_1756 = bits(_WIRE_121, 4, 4) connect _WIRE_120.pal, _T_1756 node _T_1757 = bits(_WIRE_121, 5, 5) connect _WIRE_120.ppp, _T_1757 node _T_1758 = bits(_WIRE_121, 6, 6) connect _WIRE_120.pr, _T_1758 node _T_1759 = bits(_WIRE_121, 7, 7) connect _WIRE_120.px, _T_1759 node _T_1760 = bits(_WIRE_121, 8, 8) connect _WIRE_120.pw, _T_1760 node _T_1761 = bits(_WIRE_121, 9, 9) connect _WIRE_120.hr, _T_1761 node _T_1762 = bits(_WIRE_121, 10, 10) connect _WIRE_120.hx, _T_1762 node _T_1763 = bits(_WIRE_121, 11, 11) connect _WIRE_120.hw, _T_1763 node _T_1764 = bits(_WIRE_121, 12, 12) connect _WIRE_120.sr, _T_1764 node _T_1765 = bits(_WIRE_121, 13, 13) connect _WIRE_120.sx, _T_1765 node _T_1766 = bits(_WIRE_121, 14, 14) connect _WIRE_120.sw, _T_1766 node _T_1767 = bits(_WIRE_121, 15, 15) connect _WIRE_120.gf, _T_1767 node _T_1768 = bits(_WIRE_121, 16, 16) connect _WIRE_120.pf, _T_1768 node _T_1769 = bits(_WIRE_121, 17, 17) connect _WIRE_120.ae_stage2, _T_1769 node _T_1770 = bits(_WIRE_121, 18, 18) connect _WIRE_120.ae_final, _T_1770 node _T_1771 = bits(_WIRE_121, 19, 19) connect _WIRE_120.ae_ptw, _T_1771 node _T_1772 = bits(_WIRE_121, 20, 20) connect _WIRE_120.g, _T_1772 node _T_1773 = bits(_WIRE_121, 21, 21) connect _WIRE_120.u, _T_1773 node _T_1774 = bits(_WIRE_121, 41, 22) connect _WIRE_120.ppn, _T_1774 node _T_1775 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1776 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_1777 = and(_T_1775, _T_1776) when _T_1777 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) node _T_1778 = xor(sectored_entries[3][3].tag_vpn, vpn) node _T_1779 = shr(_T_1778, 18) node _T_1780 = eq(_T_1779, UInt<1>(0h0)) when _T_1780 : wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_123 : UInt<42> connect _WIRE_123, sectored_entries[3][3].data[0] node _T_1781 = bits(_WIRE_123, 0, 0) connect _WIRE_122.fragmented_superpage, _T_1781 node _T_1782 = bits(_WIRE_123, 1, 1) connect _WIRE_122.c, _T_1782 node _T_1783 = bits(_WIRE_123, 2, 2) connect _WIRE_122.eff, _T_1783 node _T_1784 = bits(_WIRE_123, 3, 3) connect _WIRE_122.paa, _T_1784 node _T_1785 = bits(_WIRE_123, 4, 4) connect _WIRE_122.pal, _T_1785 node _T_1786 = bits(_WIRE_123, 5, 5) connect _WIRE_122.ppp, _T_1786 node _T_1787 = bits(_WIRE_123, 6, 6) connect _WIRE_122.pr, _T_1787 node _T_1788 = bits(_WIRE_123, 7, 7) connect _WIRE_122.px, _T_1788 node _T_1789 = bits(_WIRE_123, 8, 8) connect _WIRE_122.pw, _T_1789 node _T_1790 = bits(_WIRE_123, 9, 9) connect _WIRE_122.hr, _T_1790 node _T_1791 = bits(_WIRE_123, 10, 10) connect _WIRE_122.hx, _T_1791 node _T_1792 = bits(_WIRE_123, 11, 11) connect _WIRE_122.hw, _T_1792 node _T_1793 = bits(_WIRE_123, 12, 12) connect _WIRE_122.sr, _T_1793 node _T_1794 = bits(_WIRE_123, 13, 13) connect _WIRE_122.sx, _T_1794 node _T_1795 = bits(_WIRE_123, 14, 14) connect _WIRE_122.sw, _T_1795 node _T_1796 = bits(_WIRE_123, 15, 15) connect _WIRE_122.gf, _T_1796 node _T_1797 = bits(_WIRE_123, 16, 16) connect _WIRE_122.pf, _T_1797 node _T_1798 = bits(_WIRE_123, 17, 17) connect _WIRE_122.ae_stage2, _T_1798 node _T_1799 = bits(_WIRE_123, 18, 18) connect _WIRE_122.ae_final, _T_1799 node _T_1800 = bits(_WIRE_123, 19, 19) connect _WIRE_122.ae_ptw, _T_1800 node _T_1801 = bits(_WIRE_123, 20, 20) connect _WIRE_122.g, _T_1801 node _T_1802 = bits(_WIRE_123, 21, 21) connect _WIRE_122.u, _T_1802 node _T_1803 = bits(_WIRE_123, 41, 22) connect _WIRE_122.ppn, _T_1803 node _T_1804 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1805 = and(_T_1804, _WIRE_122.fragmented_superpage) when _T_1805 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) else : node _T_1806 = eq(hg_15, UInt<1>(0h0)) node _T_1807 = and(_T_1806, io.sfence.bits.rs2) when _T_1807 : wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_125 : UInt<42> connect _WIRE_125, sectored_entries[3][3].data[0] node _T_1808 = bits(_WIRE_125, 0, 0) connect _WIRE_124.fragmented_superpage, _T_1808 node _T_1809 = bits(_WIRE_125, 1, 1) connect _WIRE_124.c, _T_1809 node _T_1810 = bits(_WIRE_125, 2, 2) connect _WIRE_124.eff, _T_1810 node _T_1811 = bits(_WIRE_125, 3, 3) connect _WIRE_124.paa, _T_1811 node _T_1812 = bits(_WIRE_125, 4, 4) connect _WIRE_124.pal, _T_1812 node _T_1813 = bits(_WIRE_125, 5, 5) connect _WIRE_124.ppp, _T_1813 node _T_1814 = bits(_WIRE_125, 6, 6) connect _WIRE_124.pr, _T_1814 node _T_1815 = bits(_WIRE_125, 7, 7) connect _WIRE_124.px, _T_1815 node _T_1816 = bits(_WIRE_125, 8, 8) connect _WIRE_124.pw, _T_1816 node _T_1817 = bits(_WIRE_125, 9, 9) connect _WIRE_124.hr, _T_1817 node _T_1818 = bits(_WIRE_125, 10, 10) connect _WIRE_124.hx, _T_1818 node _T_1819 = bits(_WIRE_125, 11, 11) connect _WIRE_124.hw, _T_1819 node _T_1820 = bits(_WIRE_125, 12, 12) connect _WIRE_124.sr, _T_1820 node _T_1821 = bits(_WIRE_125, 13, 13) connect _WIRE_124.sx, _T_1821 node _T_1822 = bits(_WIRE_125, 14, 14) connect _WIRE_124.sw, _T_1822 node _T_1823 = bits(_WIRE_125, 15, 15) connect _WIRE_124.gf, _T_1823 node _T_1824 = bits(_WIRE_125, 16, 16) connect _WIRE_124.pf, _T_1824 node _T_1825 = bits(_WIRE_125, 17, 17) connect _WIRE_124.ae_stage2, _T_1825 node _T_1826 = bits(_WIRE_125, 18, 18) connect _WIRE_124.ae_final, _T_1826 node _T_1827 = bits(_WIRE_125, 19, 19) connect _WIRE_124.ae_ptw, _T_1827 node _T_1828 = bits(_WIRE_125, 20, 20) connect _WIRE_124.g, _T_1828 node _T_1829 = bits(_WIRE_125, 21, 21) connect _WIRE_124.u, _T_1829 node _T_1830 = bits(_WIRE_125, 41, 22) connect _WIRE_124.ppn, _T_1830 node _T_1831 = eq(sectored_entries[3][3].tag_v, hv_15) node _T_1832 = eq(_WIRE_124.g, UInt<1>(0h0)) node _T_1833 = and(_T_1831, _T_1832) when _T_1833 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) else : node _T_1834 = or(hv_15, hg_15) wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_127 : UInt<42> connect _WIRE_127, sectored_entries[3][3].data[0] node _T_1835 = bits(_WIRE_127, 0, 0) connect _WIRE_126.fragmented_superpage, _T_1835 node _T_1836 = bits(_WIRE_127, 1, 1) connect _WIRE_126.c, _T_1836 node _T_1837 = bits(_WIRE_127, 2, 2) connect _WIRE_126.eff, _T_1837 node _T_1838 = bits(_WIRE_127, 3, 3) connect _WIRE_126.paa, _T_1838 node _T_1839 = bits(_WIRE_127, 4, 4) connect _WIRE_126.pal, _T_1839 node _T_1840 = bits(_WIRE_127, 5, 5) connect _WIRE_126.ppp, _T_1840 node _T_1841 = bits(_WIRE_127, 6, 6) connect _WIRE_126.pr, _T_1841 node _T_1842 = bits(_WIRE_127, 7, 7) connect _WIRE_126.px, _T_1842 node _T_1843 = bits(_WIRE_127, 8, 8) connect _WIRE_126.pw, _T_1843 node _T_1844 = bits(_WIRE_127, 9, 9) connect _WIRE_126.hr, _T_1844 node _T_1845 = bits(_WIRE_127, 10, 10) connect _WIRE_126.hx, _T_1845 node _T_1846 = bits(_WIRE_127, 11, 11) connect _WIRE_126.hw, _T_1846 node _T_1847 = bits(_WIRE_127, 12, 12) connect _WIRE_126.sr, _T_1847 node _T_1848 = bits(_WIRE_127, 13, 13) connect _WIRE_126.sx, _T_1848 node _T_1849 = bits(_WIRE_127, 14, 14) connect _WIRE_126.sw, _T_1849 node _T_1850 = bits(_WIRE_127, 15, 15) connect _WIRE_126.gf, _T_1850 node _T_1851 = bits(_WIRE_127, 16, 16) connect _WIRE_126.pf, _T_1851 node _T_1852 = bits(_WIRE_127, 17, 17) connect _WIRE_126.ae_stage2, _T_1852 node _T_1853 = bits(_WIRE_127, 18, 18) connect _WIRE_126.ae_final, _T_1853 node _T_1854 = bits(_WIRE_127, 19, 19) connect _WIRE_126.ae_ptw, _T_1854 node _T_1855 = bits(_WIRE_127, 20, 20) connect _WIRE_126.g, _T_1855 node _T_1856 = bits(_WIRE_127, 21, 21) connect _WIRE_126.u, _T_1856 node _T_1857 = bits(_WIRE_127, 41, 22) connect _WIRE_126.ppn, _T_1857 node _T_1858 = eq(sectored_entries[3][3].tag_v, _T_1834) when _T_1858 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) node hv_16 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_16 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1859 = eq(hg_16, UInt<1>(0h0)) node _T_1860 = and(_T_1859, io.sfence.bits.rs1) when _T_1860 : node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_16) node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T) node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0)) node ignore = or(_ignore_T, UInt<1>(0h0)) node _T_1861 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1862 = bits(_T_1861, 26, 18) node _T_1863 = eq(_T_1862, UInt<1>(0h0)) node _T_1864 = or(ignore, _T_1863) node _T_1865 = and(tagMatch, _T_1864) node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1)) node ignore_1 = or(_ignore_T_1, UInt<1>(0h0)) node _T_1866 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1867 = bits(_T_1866, 17, 9) node _T_1868 = eq(_T_1867, UInt<1>(0h0)) node _T_1869 = or(ignore_1, _T_1868) node _T_1870 = and(_T_1865, _T_1869) node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2)) node ignore_2 = or(_ignore_T_2, UInt<1>(0h1)) node _T_1871 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1872 = bits(_T_1871, 8, 0) node _T_1873 = eq(_T_1872, UInt<1>(0h0)) node _T_1874 = or(ignore_2, _T_1873) node _T_1875 = and(_T_1870, _T_1874) when _T_1875 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node _T_1876 = xor(superpage_entries[0].tag_vpn, vpn) node _T_1877 = shr(_T_1876, 18) node _T_1878 = eq(_T_1877, UInt<1>(0h0)) when _T_1878 : wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_129 : UInt<42> connect _WIRE_129, superpage_entries[0].data[0] node _T_1879 = bits(_WIRE_129, 0, 0) connect _WIRE_128.fragmented_superpage, _T_1879 node _T_1880 = bits(_WIRE_129, 1, 1) connect _WIRE_128.c, _T_1880 node _T_1881 = bits(_WIRE_129, 2, 2) connect _WIRE_128.eff, _T_1881 node _T_1882 = bits(_WIRE_129, 3, 3) connect _WIRE_128.paa, _T_1882 node _T_1883 = bits(_WIRE_129, 4, 4) connect _WIRE_128.pal, _T_1883 node _T_1884 = bits(_WIRE_129, 5, 5) connect _WIRE_128.ppp, _T_1884 node _T_1885 = bits(_WIRE_129, 6, 6) connect _WIRE_128.pr, _T_1885 node _T_1886 = bits(_WIRE_129, 7, 7) connect _WIRE_128.px, _T_1886 node _T_1887 = bits(_WIRE_129, 8, 8) connect _WIRE_128.pw, _T_1887 node _T_1888 = bits(_WIRE_129, 9, 9) connect _WIRE_128.hr, _T_1888 node _T_1889 = bits(_WIRE_129, 10, 10) connect _WIRE_128.hx, _T_1889 node _T_1890 = bits(_WIRE_129, 11, 11) connect _WIRE_128.hw, _T_1890 node _T_1891 = bits(_WIRE_129, 12, 12) connect _WIRE_128.sr, _T_1891 node _T_1892 = bits(_WIRE_129, 13, 13) connect _WIRE_128.sx, _T_1892 node _T_1893 = bits(_WIRE_129, 14, 14) connect _WIRE_128.sw, _T_1893 node _T_1894 = bits(_WIRE_129, 15, 15) connect _WIRE_128.gf, _T_1894 node _T_1895 = bits(_WIRE_129, 16, 16) connect _WIRE_128.pf, _T_1895 node _T_1896 = bits(_WIRE_129, 17, 17) connect _WIRE_128.ae_stage2, _T_1896 node _T_1897 = bits(_WIRE_129, 18, 18) connect _WIRE_128.ae_final, _T_1897 node _T_1898 = bits(_WIRE_129, 19, 19) connect _WIRE_128.ae_ptw, _T_1898 node _T_1899 = bits(_WIRE_129, 20, 20) connect _WIRE_128.g, _T_1899 node _T_1900 = bits(_WIRE_129, 21, 21) connect _WIRE_128.u, _T_1900 node _T_1901 = bits(_WIRE_129, 41, 22) connect _WIRE_128.ppn, _T_1901 node _T_1902 = eq(superpage_entries[0].tag_v, hv_16) node _T_1903 = and(_T_1902, _WIRE_128.fragmented_superpage) when _T_1903 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_1904 = eq(hg_16, UInt<1>(0h0)) node _T_1905 = and(_T_1904, io.sfence.bits.rs2) when _T_1905 : wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_131 : UInt<42> connect _WIRE_131, superpage_entries[0].data[0] node _T_1906 = bits(_WIRE_131, 0, 0) connect _WIRE_130.fragmented_superpage, _T_1906 node _T_1907 = bits(_WIRE_131, 1, 1) connect _WIRE_130.c, _T_1907 node _T_1908 = bits(_WIRE_131, 2, 2) connect _WIRE_130.eff, _T_1908 node _T_1909 = bits(_WIRE_131, 3, 3) connect _WIRE_130.paa, _T_1909 node _T_1910 = bits(_WIRE_131, 4, 4) connect _WIRE_130.pal, _T_1910 node _T_1911 = bits(_WIRE_131, 5, 5) connect _WIRE_130.ppp, _T_1911 node _T_1912 = bits(_WIRE_131, 6, 6) connect _WIRE_130.pr, _T_1912 node _T_1913 = bits(_WIRE_131, 7, 7) connect _WIRE_130.px, _T_1913 node _T_1914 = bits(_WIRE_131, 8, 8) connect _WIRE_130.pw, _T_1914 node _T_1915 = bits(_WIRE_131, 9, 9) connect _WIRE_130.hr, _T_1915 node _T_1916 = bits(_WIRE_131, 10, 10) connect _WIRE_130.hx, _T_1916 node _T_1917 = bits(_WIRE_131, 11, 11) connect _WIRE_130.hw, _T_1917 node _T_1918 = bits(_WIRE_131, 12, 12) connect _WIRE_130.sr, _T_1918 node _T_1919 = bits(_WIRE_131, 13, 13) connect _WIRE_130.sx, _T_1919 node _T_1920 = bits(_WIRE_131, 14, 14) connect _WIRE_130.sw, _T_1920 node _T_1921 = bits(_WIRE_131, 15, 15) connect _WIRE_130.gf, _T_1921 node _T_1922 = bits(_WIRE_131, 16, 16) connect _WIRE_130.pf, _T_1922 node _T_1923 = bits(_WIRE_131, 17, 17) connect _WIRE_130.ae_stage2, _T_1923 node _T_1924 = bits(_WIRE_131, 18, 18) connect _WIRE_130.ae_final, _T_1924 node _T_1925 = bits(_WIRE_131, 19, 19) connect _WIRE_130.ae_ptw, _T_1925 node _T_1926 = bits(_WIRE_131, 20, 20) connect _WIRE_130.g, _T_1926 node _T_1927 = bits(_WIRE_131, 21, 21) connect _WIRE_130.u, _T_1927 node _T_1928 = bits(_WIRE_131, 41, 22) connect _WIRE_130.ppn, _T_1928 node _T_1929 = eq(superpage_entries[0].tag_v, hv_16) node _T_1930 = eq(_WIRE_130.g, UInt<1>(0h0)) node _T_1931 = and(_T_1929, _T_1930) when _T_1931 : connect superpage_entries[0].valid[0], UInt<1>(0h0) else : node _T_1932 = or(hv_16, hg_16) wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_133 : UInt<42> connect _WIRE_133, superpage_entries[0].data[0] node _T_1933 = bits(_WIRE_133, 0, 0) connect _WIRE_132.fragmented_superpage, _T_1933 node _T_1934 = bits(_WIRE_133, 1, 1) connect _WIRE_132.c, _T_1934 node _T_1935 = bits(_WIRE_133, 2, 2) connect _WIRE_132.eff, _T_1935 node _T_1936 = bits(_WIRE_133, 3, 3) connect _WIRE_132.paa, _T_1936 node _T_1937 = bits(_WIRE_133, 4, 4) connect _WIRE_132.pal, _T_1937 node _T_1938 = bits(_WIRE_133, 5, 5) connect _WIRE_132.ppp, _T_1938 node _T_1939 = bits(_WIRE_133, 6, 6) connect _WIRE_132.pr, _T_1939 node _T_1940 = bits(_WIRE_133, 7, 7) connect _WIRE_132.px, _T_1940 node _T_1941 = bits(_WIRE_133, 8, 8) connect _WIRE_132.pw, _T_1941 node _T_1942 = bits(_WIRE_133, 9, 9) connect _WIRE_132.hr, _T_1942 node _T_1943 = bits(_WIRE_133, 10, 10) connect _WIRE_132.hx, _T_1943 node _T_1944 = bits(_WIRE_133, 11, 11) connect _WIRE_132.hw, _T_1944 node _T_1945 = bits(_WIRE_133, 12, 12) connect _WIRE_132.sr, _T_1945 node _T_1946 = bits(_WIRE_133, 13, 13) connect _WIRE_132.sx, _T_1946 node _T_1947 = bits(_WIRE_133, 14, 14) connect _WIRE_132.sw, _T_1947 node _T_1948 = bits(_WIRE_133, 15, 15) connect _WIRE_132.gf, _T_1948 node _T_1949 = bits(_WIRE_133, 16, 16) connect _WIRE_132.pf, _T_1949 node _T_1950 = bits(_WIRE_133, 17, 17) connect _WIRE_132.ae_stage2, _T_1950 node _T_1951 = bits(_WIRE_133, 18, 18) connect _WIRE_132.ae_final, _T_1951 node _T_1952 = bits(_WIRE_133, 19, 19) connect _WIRE_132.ae_ptw, _T_1952 node _T_1953 = bits(_WIRE_133, 20, 20) connect _WIRE_132.g, _T_1953 node _T_1954 = bits(_WIRE_133, 21, 21) connect _WIRE_132.u, _T_1954 node _T_1955 = bits(_WIRE_133, 41, 22) connect _WIRE_132.ppn, _T_1955 node _T_1956 = eq(superpage_entries[0].tag_v, _T_1932) when _T_1956 : connect superpage_entries[0].valid[0], UInt<1>(0h0) node hv_17 = and(UInt<1>(0h0), io.sfence.bits.hv) node hg_17 = and(UInt<1>(0h0), io.sfence.bits.hg) node _T_1957 = eq(hg_17, UInt<1>(0h0)) node _T_1958 = and(_T_1957, io.sfence.bits.rs1) when _T_1958 : node _tagMatch_T_1 = eq(special_entry.tag_v, hv_17) node tagMatch_1 = and(special_entry.valid[0], _tagMatch_T_1) node _ignore_T_3 = lt(special_entry.level, UInt<1>(0h0)) node ignore_3 = or(_ignore_T_3, UInt<1>(0h0)) node _T_1959 = xor(special_entry.tag_vpn, vpn) node _T_1960 = bits(_T_1959, 26, 18) node _T_1961 = eq(_T_1960, UInt<1>(0h0)) node _T_1962 = or(ignore_3, _T_1961) node _T_1963 = and(tagMatch_1, _T_1962) node _ignore_T_4 = lt(special_entry.level, UInt<1>(0h1)) node ignore_4 = or(_ignore_T_4, UInt<1>(0h0)) node _T_1964 = xor(special_entry.tag_vpn, vpn) node _T_1965 = bits(_T_1964, 17, 9) node _T_1966 = eq(_T_1965, UInt<1>(0h0)) node _T_1967 = or(ignore_4, _T_1966) node _T_1968 = and(_T_1963, _T_1967) node _ignore_T_5 = lt(special_entry.level, UInt<2>(0h2)) node ignore_5 = or(_ignore_T_5, UInt<1>(0h0)) node _T_1969 = xor(special_entry.tag_vpn, vpn) node _T_1970 = bits(_T_1969, 8, 0) node _T_1971 = eq(_T_1970, UInt<1>(0h0)) node _T_1972 = or(ignore_5, _T_1971) node _T_1973 = and(_T_1968, _T_1972) when _T_1973 : connect special_entry.valid[0], UInt<1>(0h0) node _T_1974 = xor(special_entry.tag_vpn, vpn) node _T_1975 = shr(_T_1974, 18) node _T_1976 = eq(_T_1975, UInt<1>(0h0)) when _T_1976 : wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_135 : UInt<42> connect _WIRE_135, special_entry.data[0] node _T_1977 = bits(_WIRE_135, 0, 0) connect _WIRE_134.fragmented_superpage, _T_1977 node _T_1978 = bits(_WIRE_135, 1, 1) connect _WIRE_134.c, _T_1978 node _T_1979 = bits(_WIRE_135, 2, 2) connect _WIRE_134.eff, _T_1979 node _T_1980 = bits(_WIRE_135, 3, 3) connect _WIRE_134.paa, _T_1980 node _T_1981 = bits(_WIRE_135, 4, 4) connect _WIRE_134.pal, _T_1981 node _T_1982 = bits(_WIRE_135, 5, 5) connect _WIRE_134.ppp, _T_1982 node _T_1983 = bits(_WIRE_135, 6, 6) connect _WIRE_134.pr, _T_1983 node _T_1984 = bits(_WIRE_135, 7, 7) connect _WIRE_134.px, _T_1984 node _T_1985 = bits(_WIRE_135, 8, 8) connect _WIRE_134.pw, _T_1985 node _T_1986 = bits(_WIRE_135, 9, 9) connect _WIRE_134.hr, _T_1986 node _T_1987 = bits(_WIRE_135, 10, 10) connect _WIRE_134.hx, _T_1987 node _T_1988 = bits(_WIRE_135, 11, 11) connect _WIRE_134.hw, _T_1988 node _T_1989 = bits(_WIRE_135, 12, 12) connect _WIRE_134.sr, _T_1989 node _T_1990 = bits(_WIRE_135, 13, 13) connect _WIRE_134.sx, _T_1990 node _T_1991 = bits(_WIRE_135, 14, 14) connect _WIRE_134.sw, _T_1991 node _T_1992 = bits(_WIRE_135, 15, 15) connect _WIRE_134.gf, _T_1992 node _T_1993 = bits(_WIRE_135, 16, 16) connect _WIRE_134.pf, _T_1993 node _T_1994 = bits(_WIRE_135, 17, 17) connect _WIRE_134.ae_stage2, _T_1994 node _T_1995 = bits(_WIRE_135, 18, 18) connect _WIRE_134.ae_final, _T_1995 node _T_1996 = bits(_WIRE_135, 19, 19) connect _WIRE_134.ae_ptw, _T_1996 node _T_1997 = bits(_WIRE_135, 20, 20) connect _WIRE_134.g, _T_1997 node _T_1998 = bits(_WIRE_135, 21, 21) connect _WIRE_134.u, _T_1998 node _T_1999 = bits(_WIRE_135, 41, 22) connect _WIRE_134.ppn, _T_1999 node _T_2000 = eq(special_entry.tag_v, hv_17) node _T_2001 = and(_T_2000, _WIRE_134.fragmented_superpage) when _T_2001 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_2002 = eq(hg_17, UInt<1>(0h0)) node _T_2003 = and(_T_2002, io.sfence.bits.rs2) when _T_2003 : wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_137 : UInt<42> connect _WIRE_137, special_entry.data[0] node _T_2004 = bits(_WIRE_137, 0, 0) connect _WIRE_136.fragmented_superpage, _T_2004 node _T_2005 = bits(_WIRE_137, 1, 1) connect _WIRE_136.c, _T_2005 node _T_2006 = bits(_WIRE_137, 2, 2) connect _WIRE_136.eff, _T_2006 node _T_2007 = bits(_WIRE_137, 3, 3) connect _WIRE_136.paa, _T_2007 node _T_2008 = bits(_WIRE_137, 4, 4) connect _WIRE_136.pal, _T_2008 node _T_2009 = bits(_WIRE_137, 5, 5) connect _WIRE_136.ppp, _T_2009 node _T_2010 = bits(_WIRE_137, 6, 6) connect _WIRE_136.pr, _T_2010 node _T_2011 = bits(_WIRE_137, 7, 7) connect _WIRE_136.px, _T_2011 node _T_2012 = bits(_WIRE_137, 8, 8) connect _WIRE_136.pw, _T_2012 node _T_2013 = bits(_WIRE_137, 9, 9) connect _WIRE_136.hr, _T_2013 node _T_2014 = bits(_WIRE_137, 10, 10) connect _WIRE_136.hx, _T_2014 node _T_2015 = bits(_WIRE_137, 11, 11) connect _WIRE_136.hw, _T_2015 node _T_2016 = bits(_WIRE_137, 12, 12) connect _WIRE_136.sr, _T_2016 node _T_2017 = bits(_WIRE_137, 13, 13) connect _WIRE_136.sx, _T_2017 node _T_2018 = bits(_WIRE_137, 14, 14) connect _WIRE_136.sw, _T_2018 node _T_2019 = bits(_WIRE_137, 15, 15) connect _WIRE_136.gf, _T_2019 node _T_2020 = bits(_WIRE_137, 16, 16) connect _WIRE_136.pf, _T_2020 node _T_2021 = bits(_WIRE_137, 17, 17) connect _WIRE_136.ae_stage2, _T_2021 node _T_2022 = bits(_WIRE_137, 18, 18) connect _WIRE_136.ae_final, _T_2022 node _T_2023 = bits(_WIRE_137, 19, 19) connect _WIRE_136.ae_ptw, _T_2023 node _T_2024 = bits(_WIRE_137, 20, 20) connect _WIRE_136.g, _T_2024 node _T_2025 = bits(_WIRE_137, 21, 21) connect _WIRE_136.u, _T_2025 node _T_2026 = bits(_WIRE_137, 41, 22) connect _WIRE_136.ppn, _T_2026 node _T_2027 = eq(special_entry.tag_v, hv_17) node _T_2028 = eq(_WIRE_136.g, UInt<1>(0h0)) node _T_2029 = and(_T_2027, _T_2028) when _T_2029 : connect special_entry.valid[0], UInt<1>(0h0) else : node _T_2030 = or(hv_17, hg_17) wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_139 : UInt<42> connect _WIRE_139, special_entry.data[0] node _T_2031 = bits(_WIRE_139, 0, 0) connect _WIRE_138.fragmented_superpage, _T_2031 node _T_2032 = bits(_WIRE_139, 1, 1) connect _WIRE_138.c, _T_2032 node _T_2033 = bits(_WIRE_139, 2, 2) connect _WIRE_138.eff, _T_2033 node _T_2034 = bits(_WIRE_139, 3, 3) connect _WIRE_138.paa, _T_2034 node _T_2035 = bits(_WIRE_139, 4, 4) connect _WIRE_138.pal, _T_2035 node _T_2036 = bits(_WIRE_139, 5, 5) connect _WIRE_138.ppp, _T_2036 node _T_2037 = bits(_WIRE_139, 6, 6) connect _WIRE_138.pr, _T_2037 node _T_2038 = bits(_WIRE_139, 7, 7) connect _WIRE_138.px, _T_2038 node _T_2039 = bits(_WIRE_139, 8, 8) connect _WIRE_138.pw, _T_2039 node _T_2040 = bits(_WIRE_139, 9, 9) connect _WIRE_138.hr, _T_2040 node _T_2041 = bits(_WIRE_139, 10, 10) connect _WIRE_138.hx, _T_2041 node _T_2042 = bits(_WIRE_139, 11, 11) connect _WIRE_138.hw, _T_2042 node _T_2043 = bits(_WIRE_139, 12, 12) connect _WIRE_138.sr, _T_2043 node _T_2044 = bits(_WIRE_139, 13, 13) connect _WIRE_138.sx, _T_2044 node _T_2045 = bits(_WIRE_139, 14, 14) connect _WIRE_138.sw, _T_2045 node _T_2046 = bits(_WIRE_139, 15, 15) connect _WIRE_138.gf, _T_2046 node _T_2047 = bits(_WIRE_139, 16, 16) connect _WIRE_138.pf, _T_2047 node _T_2048 = bits(_WIRE_139, 17, 17) connect _WIRE_138.ae_stage2, _T_2048 node _T_2049 = bits(_WIRE_139, 18, 18) connect _WIRE_138.ae_final, _T_2049 node _T_2050 = bits(_WIRE_139, 19, 19) connect _WIRE_138.ae_ptw, _T_2050 node _T_2051 = bits(_WIRE_139, 20, 20) connect _WIRE_138.g, _T_2051 node _T_2052 = bits(_WIRE_139, 21, 21) connect _WIRE_138.u, _T_2052 node _T_2053 = bits(_WIRE_139, 41, 22) connect _WIRE_138.ppn, _T_2053 node _T_2054 = eq(special_entry.tag_v, _T_2030) when _T_2054 : connect special_entry.valid[0], UInt<1>(0h0) node _T_2055 = and(io.req.ready, io.req.valid) node _T_2056 = and(_T_2055, vsatp_mode_mismatch) when _T_2056 : wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_141 : UInt<42> connect _WIRE_141, sectored_entries[0][0].data[0] node _T_2057 = bits(_WIRE_141, 0, 0) connect _WIRE_140.fragmented_superpage, _T_2057 node _T_2058 = bits(_WIRE_141, 1, 1) connect _WIRE_140.c, _T_2058 node _T_2059 = bits(_WIRE_141, 2, 2) connect _WIRE_140.eff, _T_2059 node _T_2060 = bits(_WIRE_141, 3, 3) connect _WIRE_140.paa, _T_2060 node _T_2061 = bits(_WIRE_141, 4, 4) connect _WIRE_140.pal, _T_2061 node _T_2062 = bits(_WIRE_141, 5, 5) connect _WIRE_140.ppp, _T_2062 node _T_2063 = bits(_WIRE_141, 6, 6) connect _WIRE_140.pr, _T_2063 node _T_2064 = bits(_WIRE_141, 7, 7) connect _WIRE_140.px, _T_2064 node _T_2065 = bits(_WIRE_141, 8, 8) connect _WIRE_140.pw, _T_2065 node _T_2066 = bits(_WIRE_141, 9, 9) connect _WIRE_140.hr, _T_2066 node _T_2067 = bits(_WIRE_141, 10, 10) connect _WIRE_140.hx, _T_2067 node _T_2068 = bits(_WIRE_141, 11, 11) connect _WIRE_140.hw, _T_2068 node _T_2069 = bits(_WIRE_141, 12, 12) connect _WIRE_140.sr, _T_2069 node _T_2070 = bits(_WIRE_141, 13, 13) connect _WIRE_140.sx, _T_2070 node _T_2071 = bits(_WIRE_141, 14, 14) connect _WIRE_140.sw, _T_2071 node _T_2072 = bits(_WIRE_141, 15, 15) connect _WIRE_140.gf, _T_2072 node _T_2073 = bits(_WIRE_141, 16, 16) connect _WIRE_140.pf, _T_2073 node _T_2074 = bits(_WIRE_141, 17, 17) connect _WIRE_140.ae_stage2, _T_2074 node _T_2075 = bits(_WIRE_141, 18, 18) connect _WIRE_140.ae_final, _T_2075 node _T_2076 = bits(_WIRE_141, 19, 19) connect _WIRE_140.ae_ptw, _T_2076 node _T_2077 = bits(_WIRE_141, 20, 20) connect _WIRE_140.g, _T_2077 node _T_2078 = bits(_WIRE_141, 21, 21) connect _WIRE_140.u, _T_2078 node _T_2079 = bits(_WIRE_141, 41, 22) connect _WIRE_140.ppn, _T_2079 node _T_2080 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1)) when _T_2080 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_143 : UInt<42> connect _WIRE_143, sectored_entries[0][1].data[0] node _T_2081 = bits(_WIRE_143, 0, 0) connect _WIRE_142.fragmented_superpage, _T_2081 node _T_2082 = bits(_WIRE_143, 1, 1) connect _WIRE_142.c, _T_2082 node _T_2083 = bits(_WIRE_143, 2, 2) connect _WIRE_142.eff, _T_2083 node _T_2084 = bits(_WIRE_143, 3, 3) connect _WIRE_142.paa, _T_2084 node _T_2085 = bits(_WIRE_143, 4, 4) connect _WIRE_142.pal, _T_2085 node _T_2086 = bits(_WIRE_143, 5, 5) connect _WIRE_142.ppp, _T_2086 node _T_2087 = bits(_WIRE_143, 6, 6) connect _WIRE_142.pr, _T_2087 node _T_2088 = bits(_WIRE_143, 7, 7) connect _WIRE_142.px, _T_2088 node _T_2089 = bits(_WIRE_143, 8, 8) connect _WIRE_142.pw, _T_2089 node _T_2090 = bits(_WIRE_143, 9, 9) connect _WIRE_142.hr, _T_2090 node _T_2091 = bits(_WIRE_143, 10, 10) connect _WIRE_142.hx, _T_2091 node _T_2092 = bits(_WIRE_143, 11, 11) connect _WIRE_142.hw, _T_2092 node _T_2093 = bits(_WIRE_143, 12, 12) connect _WIRE_142.sr, _T_2093 node _T_2094 = bits(_WIRE_143, 13, 13) connect _WIRE_142.sx, _T_2094 node _T_2095 = bits(_WIRE_143, 14, 14) connect _WIRE_142.sw, _T_2095 node _T_2096 = bits(_WIRE_143, 15, 15) connect _WIRE_142.gf, _T_2096 node _T_2097 = bits(_WIRE_143, 16, 16) connect _WIRE_142.pf, _T_2097 node _T_2098 = bits(_WIRE_143, 17, 17) connect _WIRE_142.ae_stage2, _T_2098 node _T_2099 = bits(_WIRE_143, 18, 18) connect _WIRE_142.ae_final, _T_2099 node _T_2100 = bits(_WIRE_143, 19, 19) connect _WIRE_142.ae_ptw, _T_2100 node _T_2101 = bits(_WIRE_143, 20, 20) connect _WIRE_142.g, _T_2101 node _T_2102 = bits(_WIRE_143, 21, 21) connect _WIRE_142.u, _T_2102 node _T_2103 = bits(_WIRE_143, 41, 22) connect _WIRE_142.ppn, _T_2103 node _T_2104 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1)) when _T_2104 : connect sectored_entries[0][1].valid[0], UInt<1>(0h0) wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_145 : UInt<42> connect _WIRE_145, sectored_entries[0][2].data[0] node _T_2105 = bits(_WIRE_145, 0, 0) connect _WIRE_144.fragmented_superpage, _T_2105 node _T_2106 = bits(_WIRE_145, 1, 1) connect _WIRE_144.c, _T_2106 node _T_2107 = bits(_WIRE_145, 2, 2) connect _WIRE_144.eff, _T_2107 node _T_2108 = bits(_WIRE_145, 3, 3) connect _WIRE_144.paa, _T_2108 node _T_2109 = bits(_WIRE_145, 4, 4) connect _WIRE_144.pal, _T_2109 node _T_2110 = bits(_WIRE_145, 5, 5) connect _WIRE_144.ppp, _T_2110 node _T_2111 = bits(_WIRE_145, 6, 6) connect _WIRE_144.pr, _T_2111 node _T_2112 = bits(_WIRE_145, 7, 7) connect _WIRE_144.px, _T_2112 node _T_2113 = bits(_WIRE_145, 8, 8) connect _WIRE_144.pw, _T_2113 node _T_2114 = bits(_WIRE_145, 9, 9) connect _WIRE_144.hr, _T_2114 node _T_2115 = bits(_WIRE_145, 10, 10) connect _WIRE_144.hx, _T_2115 node _T_2116 = bits(_WIRE_145, 11, 11) connect _WIRE_144.hw, _T_2116 node _T_2117 = bits(_WIRE_145, 12, 12) connect _WIRE_144.sr, _T_2117 node _T_2118 = bits(_WIRE_145, 13, 13) connect _WIRE_144.sx, _T_2118 node _T_2119 = bits(_WIRE_145, 14, 14) connect _WIRE_144.sw, _T_2119 node _T_2120 = bits(_WIRE_145, 15, 15) connect _WIRE_144.gf, _T_2120 node _T_2121 = bits(_WIRE_145, 16, 16) connect _WIRE_144.pf, _T_2121 node _T_2122 = bits(_WIRE_145, 17, 17) connect _WIRE_144.ae_stage2, _T_2122 node _T_2123 = bits(_WIRE_145, 18, 18) connect _WIRE_144.ae_final, _T_2123 node _T_2124 = bits(_WIRE_145, 19, 19) connect _WIRE_144.ae_ptw, _T_2124 node _T_2125 = bits(_WIRE_145, 20, 20) connect _WIRE_144.g, _T_2125 node _T_2126 = bits(_WIRE_145, 21, 21) connect _WIRE_144.u, _T_2126 node _T_2127 = bits(_WIRE_145, 41, 22) connect _WIRE_144.ppn, _T_2127 node _T_2128 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1)) when _T_2128 : connect sectored_entries[0][2].valid[0], UInt<1>(0h0) wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_147 : UInt<42> connect _WIRE_147, sectored_entries[0][3].data[0] node _T_2129 = bits(_WIRE_147, 0, 0) connect _WIRE_146.fragmented_superpage, _T_2129 node _T_2130 = bits(_WIRE_147, 1, 1) connect _WIRE_146.c, _T_2130 node _T_2131 = bits(_WIRE_147, 2, 2) connect _WIRE_146.eff, _T_2131 node _T_2132 = bits(_WIRE_147, 3, 3) connect _WIRE_146.paa, _T_2132 node _T_2133 = bits(_WIRE_147, 4, 4) connect _WIRE_146.pal, _T_2133 node _T_2134 = bits(_WIRE_147, 5, 5) connect _WIRE_146.ppp, _T_2134 node _T_2135 = bits(_WIRE_147, 6, 6) connect _WIRE_146.pr, _T_2135 node _T_2136 = bits(_WIRE_147, 7, 7) connect _WIRE_146.px, _T_2136 node _T_2137 = bits(_WIRE_147, 8, 8) connect _WIRE_146.pw, _T_2137 node _T_2138 = bits(_WIRE_147, 9, 9) connect _WIRE_146.hr, _T_2138 node _T_2139 = bits(_WIRE_147, 10, 10) connect _WIRE_146.hx, _T_2139 node _T_2140 = bits(_WIRE_147, 11, 11) connect _WIRE_146.hw, _T_2140 node _T_2141 = bits(_WIRE_147, 12, 12) connect _WIRE_146.sr, _T_2141 node _T_2142 = bits(_WIRE_147, 13, 13) connect _WIRE_146.sx, _T_2142 node _T_2143 = bits(_WIRE_147, 14, 14) connect _WIRE_146.sw, _T_2143 node _T_2144 = bits(_WIRE_147, 15, 15) connect _WIRE_146.gf, _T_2144 node _T_2145 = bits(_WIRE_147, 16, 16) connect _WIRE_146.pf, _T_2145 node _T_2146 = bits(_WIRE_147, 17, 17) connect _WIRE_146.ae_stage2, _T_2146 node _T_2147 = bits(_WIRE_147, 18, 18) connect _WIRE_146.ae_final, _T_2147 node _T_2148 = bits(_WIRE_147, 19, 19) connect _WIRE_146.ae_ptw, _T_2148 node _T_2149 = bits(_WIRE_147, 20, 20) connect _WIRE_146.g, _T_2149 node _T_2150 = bits(_WIRE_147, 21, 21) connect _WIRE_146.u, _T_2150 node _T_2151 = bits(_WIRE_147, 41, 22) connect _WIRE_146.ppn, _T_2151 node _T_2152 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1)) when _T_2152 : connect sectored_entries[0][3].valid[0], UInt<1>(0h0) wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_149 : UInt<42> connect _WIRE_149, sectored_entries[1][0].data[0] node _T_2153 = bits(_WIRE_149, 0, 0) connect _WIRE_148.fragmented_superpage, _T_2153 node _T_2154 = bits(_WIRE_149, 1, 1) connect _WIRE_148.c, _T_2154 node _T_2155 = bits(_WIRE_149, 2, 2) connect _WIRE_148.eff, _T_2155 node _T_2156 = bits(_WIRE_149, 3, 3) connect _WIRE_148.paa, _T_2156 node _T_2157 = bits(_WIRE_149, 4, 4) connect _WIRE_148.pal, _T_2157 node _T_2158 = bits(_WIRE_149, 5, 5) connect _WIRE_148.ppp, _T_2158 node _T_2159 = bits(_WIRE_149, 6, 6) connect _WIRE_148.pr, _T_2159 node _T_2160 = bits(_WIRE_149, 7, 7) connect _WIRE_148.px, _T_2160 node _T_2161 = bits(_WIRE_149, 8, 8) connect _WIRE_148.pw, _T_2161 node _T_2162 = bits(_WIRE_149, 9, 9) connect _WIRE_148.hr, _T_2162 node _T_2163 = bits(_WIRE_149, 10, 10) connect _WIRE_148.hx, _T_2163 node _T_2164 = bits(_WIRE_149, 11, 11) connect _WIRE_148.hw, _T_2164 node _T_2165 = bits(_WIRE_149, 12, 12) connect _WIRE_148.sr, _T_2165 node _T_2166 = bits(_WIRE_149, 13, 13) connect _WIRE_148.sx, _T_2166 node _T_2167 = bits(_WIRE_149, 14, 14) connect _WIRE_148.sw, _T_2167 node _T_2168 = bits(_WIRE_149, 15, 15) connect _WIRE_148.gf, _T_2168 node _T_2169 = bits(_WIRE_149, 16, 16) connect _WIRE_148.pf, _T_2169 node _T_2170 = bits(_WIRE_149, 17, 17) connect _WIRE_148.ae_stage2, _T_2170 node _T_2171 = bits(_WIRE_149, 18, 18) connect _WIRE_148.ae_final, _T_2171 node _T_2172 = bits(_WIRE_149, 19, 19) connect _WIRE_148.ae_ptw, _T_2172 node _T_2173 = bits(_WIRE_149, 20, 20) connect _WIRE_148.g, _T_2173 node _T_2174 = bits(_WIRE_149, 21, 21) connect _WIRE_148.u, _T_2174 node _T_2175 = bits(_WIRE_149, 41, 22) connect _WIRE_148.ppn, _T_2175 node _T_2176 = eq(sectored_entries[1][0].tag_v, UInt<1>(0h1)) when _T_2176 : connect sectored_entries[1][0].valid[0], UInt<1>(0h0) wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_151 : UInt<42> connect _WIRE_151, sectored_entries[1][1].data[0] node _T_2177 = bits(_WIRE_151, 0, 0) connect _WIRE_150.fragmented_superpage, _T_2177 node _T_2178 = bits(_WIRE_151, 1, 1) connect _WIRE_150.c, _T_2178 node _T_2179 = bits(_WIRE_151, 2, 2) connect _WIRE_150.eff, _T_2179 node _T_2180 = bits(_WIRE_151, 3, 3) connect _WIRE_150.paa, _T_2180 node _T_2181 = bits(_WIRE_151, 4, 4) connect _WIRE_150.pal, _T_2181 node _T_2182 = bits(_WIRE_151, 5, 5) connect _WIRE_150.ppp, _T_2182 node _T_2183 = bits(_WIRE_151, 6, 6) connect _WIRE_150.pr, _T_2183 node _T_2184 = bits(_WIRE_151, 7, 7) connect _WIRE_150.px, _T_2184 node _T_2185 = bits(_WIRE_151, 8, 8) connect _WIRE_150.pw, _T_2185 node _T_2186 = bits(_WIRE_151, 9, 9) connect _WIRE_150.hr, _T_2186 node _T_2187 = bits(_WIRE_151, 10, 10) connect _WIRE_150.hx, _T_2187 node _T_2188 = bits(_WIRE_151, 11, 11) connect _WIRE_150.hw, _T_2188 node _T_2189 = bits(_WIRE_151, 12, 12) connect _WIRE_150.sr, _T_2189 node _T_2190 = bits(_WIRE_151, 13, 13) connect _WIRE_150.sx, _T_2190 node _T_2191 = bits(_WIRE_151, 14, 14) connect _WIRE_150.sw, _T_2191 node _T_2192 = bits(_WIRE_151, 15, 15) connect _WIRE_150.gf, _T_2192 node _T_2193 = bits(_WIRE_151, 16, 16) connect _WIRE_150.pf, _T_2193 node _T_2194 = bits(_WIRE_151, 17, 17) connect _WIRE_150.ae_stage2, _T_2194 node _T_2195 = bits(_WIRE_151, 18, 18) connect _WIRE_150.ae_final, _T_2195 node _T_2196 = bits(_WIRE_151, 19, 19) connect _WIRE_150.ae_ptw, _T_2196 node _T_2197 = bits(_WIRE_151, 20, 20) connect _WIRE_150.g, _T_2197 node _T_2198 = bits(_WIRE_151, 21, 21) connect _WIRE_150.u, _T_2198 node _T_2199 = bits(_WIRE_151, 41, 22) connect _WIRE_150.ppn, _T_2199 node _T_2200 = eq(sectored_entries[1][1].tag_v, UInt<1>(0h1)) when _T_2200 : connect sectored_entries[1][1].valid[0], UInt<1>(0h0) wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_153 : UInt<42> connect _WIRE_153, sectored_entries[1][2].data[0] node _T_2201 = bits(_WIRE_153, 0, 0) connect _WIRE_152.fragmented_superpage, _T_2201 node _T_2202 = bits(_WIRE_153, 1, 1) connect _WIRE_152.c, _T_2202 node _T_2203 = bits(_WIRE_153, 2, 2) connect _WIRE_152.eff, _T_2203 node _T_2204 = bits(_WIRE_153, 3, 3) connect _WIRE_152.paa, _T_2204 node _T_2205 = bits(_WIRE_153, 4, 4) connect _WIRE_152.pal, _T_2205 node _T_2206 = bits(_WIRE_153, 5, 5) connect _WIRE_152.ppp, _T_2206 node _T_2207 = bits(_WIRE_153, 6, 6) connect _WIRE_152.pr, _T_2207 node _T_2208 = bits(_WIRE_153, 7, 7) connect _WIRE_152.px, _T_2208 node _T_2209 = bits(_WIRE_153, 8, 8) connect _WIRE_152.pw, _T_2209 node _T_2210 = bits(_WIRE_153, 9, 9) connect _WIRE_152.hr, _T_2210 node _T_2211 = bits(_WIRE_153, 10, 10) connect _WIRE_152.hx, _T_2211 node _T_2212 = bits(_WIRE_153, 11, 11) connect _WIRE_152.hw, _T_2212 node _T_2213 = bits(_WIRE_153, 12, 12) connect _WIRE_152.sr, _T_2213 node _T_2214 = bits(_WIRE_153, 13, 13) connect _WIRE_152.sx, _T_2214 node _T_2215 = bits(_WIRE_153, 14, 14) connect _WIRE_152.sw, _T_2215 node _T_2216 = bits(_WIRE_153, 15, 15) connect _WIRE_152.gf, _T_2216 node _T_2217 = bits(_WIRE_153, 16, 16) connect _WIRE_152.pf, _T_2217 node _T_2218 = bits(_WIRE_153, 17, 17) connect _WIRE_152.ae_stage2, _T_2218 node _T_2219 = bits(_WIRE_153, 18, 18) connect _WIRE_152.ae_final, _T_2219 node _T_2220 = bits(_WIRE_153, 19, 19) connect _WIRE_152.ae_ptw, _T_2220 node _T_2221 = bits(_WIRE_153, 20, 20) connect _WIRE_152.g, _T_2221 node _T_2222 = bits(_WIRE_153, 21, 21) connect _WIRE_152.u, _T_2222 node _T_2223 = bits(_WIRE_153, 41, 22) connect _WIRE_152.ppn, _T_2223 node _T_2224 = eq(sectored_entries[1][2].tag_v, UInt<1>(0h1)) when _T_2224 : connect sectored_entries[1][2].valid[0], UInt<1>(0h0) wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_155 : UInt<42> connect _WIRE_155, sectored_entries[1][3].data[0] node _T_2225 = bits(_WIRE_155, 0, 0) connect _WIRE_154.fragmented_superpage, _T_2225 node _T_2226 = bits(_WIRE_155, 1, 1) connect _WIRE_154.c, _T_2226 node _T_2227 = bits(_WIRE_155, 2, 2) connect _WIRE_154.eff, _T_2227 node _T_2228 = bits(_WIRE_155, 3, 3) connect _WIRE_154.paa, _T_2228 node _T_2229 = bits(_WIRE_155, 4, 4) connect _WIRE_154.pal, _T_2229 node _T_2230 = bits(_WIRE_155, 5, 5) connect _WIRE_154.ppp, _T_2230 node _T_2231 = bits(_WIRE_155, 6, 6) connect _WIRE_154.pr, _T_2231 node _T_2232 = bits(_WIRE_155, 7, 7) connect _WIRE_154.px, _T_2232 node _T_2233 = bits(_WIRE_155, 8, 8) connect _WIRE_154.pw, _T_2233 node _T_2234 = bits(_WIRE_155, 9, 9) connect _WIRE_154.hr, _T_2234 node _T_2235 = bits(_WIRE_155, 10, 10) connect _WIRE_154.hx, _T_2235 node _T_2236 = bits(_WIRE_155, 11, 11) connect _WIRE_154.hw, _T_2236 node _T_2237 = bits(_WIRE_155, 12, 12) connect _WIRE_154.sr, _T_2237 node _T_2238 = bits(_WIRE_155, 13, 13) connect _WIRE_154.sx, _T_2238 node _T_2239 = bits(_WIRE_155, 14, 14) connect _WIRE_154.sw, _T_2239 node _T_2240 = bits(_WIRE_155, 15, 15) connect _WIRE_154.gf, _T_2240 node _T_2241 = bits(_WIRE_155, 16, 16) connect _WIRE_154.pf, _T_2241 node _T_2242 = bits(_WIRE_155, 17, 17) connect _WIRE_154.ae_stage2, _T_2242 node _T_2243 = bits(_WIRE_155, 18, 18) connect _WIRE_154.ae_final, _T_2243 node _T_2244 = bits(_WIRE_155, 19, 19) connect _WIRE_154.ae_ptw, _T_2244 node _T_2245 = bits(_WIRE_155, 20, 20) connect _WIRE_154.g, _T_2245 node _T_2246 = bits(_WIRE_155, 21, 21) connect _WIRE_154.u, _T_2246 node _T_2247 = bits(_WIRE_155, 41, 22) connect _WIRE_154.ppn, _T_2247 node _T_2248 = eq(sectored_entries[1][3].tag_v, UInt<1>(0h1)) when _T_2248 : connect sectored_entries[1][3].valid[0], UInt<1>(0h0) wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_157 : UInt<42> connect _WIRE_157, sectored_entries[2][0].data[0] node _T_2249 = bits(_WIRE_157, 0, 0) connect _WIRE_156.fragmented_superpage, _T_2249 node _T_2250 = bits(_WIRE_157, 1, 1) connect _WIRE_156.c, _T_2250 node _T_2251 = bits(_WIRE_157, 2, 2) connect _WIRE_156.eff, _T_2251 node _T_2252 = bits(_WIRE_157, 3, 3) connect _WIRE_156.paa, _T_2252 node _T_2253 = bits(_WIRE_157, 4, 4) connect _WIRE_156.pal, _T_2253 node _T_2254 = bits(_WIRE_157, 5, 5) connect _WIRE_156.ppp, _T_2254 node _T_2255 = bits(_WIRE_157, 6, 6) connect _WIRE_156.pr, _T_2255 node _T_2256 = bits(_WIRE_157, 7, 7) connect _WIRE_156.px, _T_2256 node _T_2257 = bits(_WIRE_157, 8, 8) connect _WIRE_156.pw, _T_2257 node _T_2258 = bits(_WIRE_157, 9, 9) connect _WIRE_156.hr, _T_2258 node _T_2259 = bits(_WIRE_157, 10, 10) connect _WIRE_156.hx, _T_2259 node _T_2260 = bits(_WIRE_157, 11, 11) connect _WIRE_156.hw, _T_2260 node _T_2261 = bits(_WIRE_157, 12, 12) connect _WIRE_156.sr, _T_2261 node _T_2262 = bits(_WIRE_157, 13, 13) connect _WIRE_156.sx, _T_2262 node _T_2263 = bits(_WIRE_157, 14, 14) connect _WIRE_156.sw, _T_2263 node _T_2264 = bits(_WIRE_157, 15, 15) connect _WIRE_156.gf, _T_2264 node _T_2265 = bits(_WIRE_157, 16, 16) connect _WIRE_156.pf, _T_2265 node _T_2266 = bits(_WIRE_157, 17, 17) connect _WIRE_156.ae_stage2, _T_2266 node _T_2267 = bits(_WIRE_157, 18, 18) connect _WIRE_156.ae_final, _T_2267 node _T_2268 = bits(_WIRE_157, 19, 19) connect _WIRE_156.ae_ptw, _T_2268 node _T_2269 = bits(_WIRE_157, 20, 20) connect _WIRE_156.g, _T_2269 node _T_2270 = bits(_WIRE_157, 21, 21) connect _WIRE_156.u, _T_2270 node _T_2271 = bits(_WIRE_157, 41, 22) connect _WIRE_156.ppn, _T_2271 node _T_2272 = eq(sectored_entries[2][0].tag_v, UInt<1>(0h1)) when _T_2272 : connect sectored_entries[2][0].valid[0], UInt<1>(0h0) wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_159 : UInt<42> connect _WIRE_159, sectored_entries[2][1].data[0] node _T_2273 = bits(_WIRE_159, 0, 0) connect _WIRE_158.fragmented_superpage, _T_2273 node _T_2274 = bits(_WIRE_159, 1, 1) connect _WIRE_158.c, _T_2274 node _T_2275 = bits(_WIRE_159, 2, 2) connect _WIRE_158.eff, _T_2275 node _T_2276 = bits(_WIRE_159, 3, 3) connect _WIRE_158.paa, _T_2276 node _T_2277 = bits(_WIRE_159, 4, 4) connect _WIRE_158.pal, _T_2277 node _T_2278 = bits(_WIRE_159, 5, 5) connect _WIRE_158.ppp, _T_2278 node _T_2279 = bits(_WIRE_159, 6, 6) connect _WIRE_158.pr, _T_2279 node _T_2280 = bits(_WIRE_159, 7, 7) connect _WIRE_158.px, _T_2280 node _T_2281 = bits(_WIRE_159, 8, 8) connect _WIRE_158.pw, _T_2281 node _T_2282 = bits(_WIRE_159, 9, 9) connect _WIRE_158.hr, _T_2282 node _T_2283 = bits(_WIRE_159, 10, 10) connect _WIRE_158.hx, _T_2283 node _T_2284 = bits(_WIRE_159, 11, 11) connect _WIRE_158.hw, _T_2284 node _T_2285 = bits(_WIRE_159, 12, 12) connect _WIRE_158.sr, _T_2285 node _T_2286 = bits(_WIRE_159, 13, 13) connect _WIRE_158.sx, _T_2286 node _T_2287 = bits(_WIRE_159, 14, 14) connect _WIRE_158.sw, _T_2287 node _T_2288 = bits(_WIRE_159, 15, 15) connect _WIRE_158.gf, _T_2288 node _T_2289 = bits(_WIRE_159, 16, 16) connect _WIRE_158.pf, _T_2289 node _T_2290 = bits(_WIRE_159, 17, 17) connect _WIRE_158.ae_stage2, _T_2290 node _T_2291 = bits(_WIRE_159, 18, 18) connect _WIRE_158.ae_final, _T_2291 node _T_2292 = bits(_WIRE_159, 19, 19) connect _WIRE_158.ae_ptw, _T_2292 node _T_2293 = bits(_WIRE_159, 20, 20) connect _WIRE_158.g, _T_2293 node _T_2294 = bits(_WIRE_159, 21, 21) connect _WIRE_158.u, _T_2294 node _T_2295 = bits(_WIRE_159, 41, 22) connect _WIRE_158.ppn, _T_2295 node _T_2296 = eq(sectored_entries[2][1].tag_v, UInt<1>(0h1)) when _T_2296 : connect sectored_entries[2][1].valid[0], UInt<1>(0h0) wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_161 : UInt<42> connect _WIRE_161, sectored_entries[2][2].data[0] node _T_2297 = bits(_WIRE_161, 0, 0) connect _WIRE_160.fragmented_superpage, _T_2297 node _T_2298 = bits(_WIRE_161, 1, 1) connect _WIRE_160.c, _T_2298 node _T_2299 = bits(_WIRE_161, 2, 2) connect _WIRE_160.eff, _T_2299 node _T_2300 = bits(_WIRE_161, 3, 3) connect _WIRE_160.paa, _T_2300 node _T_2301 = bits(_WIRE_161, 4, 4) connect _WIRE_160.pal, _T_2301 node _T_2302 = bits(_WIRE_161, 5, 5) connect _WIRE_160.ppp, _T_2302 node _T_2303 = bits(_WIRE_161, 6, 6) connect _WIRE_160.pr, _T_2303 node _T_2304 = bits(_WIRE_161, 7, 7) connect _WIRE_160.px, _T_2304 node _T_2305 = bits(_WIRE_161, 8, 8) connect _WIRE_160.pw, _T_2305 node _T_2306 = bits(_WIRE_161, 9, 9) connect _WIRE_160.hr, _T_2306 node _T_2307 = bits(_WIRE_161, 10, 10) connect _WIRE_160.hx, _T_2307 node _T_2308 = bits(_WIRE_161, 11, 11) connect _WIRE_160.hw, _T_2308 node _T_2309 = bits(_WIRE_161, 12, 12) connect _WIRE_160.sr, _T_2309 node _T_2310 = bits(_WIRE_161, 13, 13) connect _WIRE_160.sx, _T_2310 node _T_2311 = bits(_WIRE_161, 14, 14) connect _WIRE_160.sw, _T_2311 node _T_2312 = bits(_WIRE_161, 15, 15) connect _WIRE_160.gf, _T_2312 node _T_2313 = bits(_WIRE_161, 16, 16) connect _WIRE_160.pf, _T_2313 node _T_2314 = bits(_WIRE_161, 17, 17) connect _WIRE_160.ae_stage2, _T_2314 node _T_2315 = bits(_WIRE_161, 18, 18) connect _WIRE_160.ae_final, _T_2315 node _T_2316 = bits(_WIRE_161, 19, 19) connect _WIRE_160.ae_ptw, _T_2316 node _T_2317 = bits(_WIRE_161, 20, 20) connect _WIRE_160.g, _T_2317 node _T_2318 = bits(_WIRE_161, 21, 21) connect _WIRE_160.u, _T_2318 node _T_2319 = bits(_WIRE_161, 41, 22) connect _WIRE_160.ppn, _T_2319 node _T_2320 = eq(sectored_entries[2][2].tag_v, UInt<1>(0h1)) when _T_2320 : connect sectored_entries[2][2].valid[0], UInt<1>(0h0) wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_163 : UInt<42> connect _WIRE_163, sectored_entries[2][3].data[0] node _T_2321 = bits(_WIRE_163, 0, 0) connect _WIRE_162.fragmented_superpage, _T_2321 node _T_2322 = bits(_WIRE_163, 1, 1) connect _WIRE_162.c, _T_2322 node _T_2323 = bits(_WIRE_163, 2, 2) connect _WIRE_162.eff, _T_2323 node _T_2324 = bits(_WIRE_163, 3, 3) connect _WIRE_162.paa, _T_2324 node _T_2325 = bits(_WIRE_163, 4, 4) connect _WIRE_162.pal, _T_2325 node _T_2326 = bits(_WIRE_163, 5, 5) connect _WIRE_162.ppp, _T_2326 node _T_2327 = bits(_WIRE_163, 6, 6) connect _WIRE_162.pr, _T_2327 node _T_2328 = bits(_WIRE_163, 7, 7) connect _WIRE_162.px, _T_2328 node _T_2329 = bits(_WIRE_163, 8, 8) connect _WIRE_162.pw, _T_2329 node _T_2330 = bits(_WIRE_163, 9, 9) connect _WIRE_162.hr, _T_2330 node _T_2331 = bits(_WIRE_163, 10, 10) connect _WIRE_162.hx, _T_2331 node _T_2332 = bits(_WIRE_163, 11, 11) connect _WIRE_162.hw, _T_2332 node _T_2333 = bits(_WIRE_163, 12, 12) connect _WIRE_162.sr, _T_2333 node _T_2334 = bits(_WIRE_163, 13, 13) connect _WIRE_162.sx, _T_2334 node _T_2335 = bits(_WIRE_163, 14, 14) connect _WIRE_162.sw, _T_2335 node _T_2336 = bits(_WIRE_163, 15, 15) connect _WIRE_162.gf, _T_2336 node _T_2337 = bits(_WIRE_163, 16, 16) connect _WIRE_162.pf, _T_2337 node _T_2338 = bits(_WIRE_163, 17, 17) connect _WIRE_162.ae_stage2, _T_2338 node _T_2339 = bits(_WIRE_163, 18, 18) connect _WIRE_162.ae_final, _T_2339 node _T_2340 = bits(_WIRE_163, 19, 19) connect _WIRE_162.ae_ptw, _T_2340 node _T_2341 = bits(_WIRE_163, 20, 20) connect _WIRE_162.g, _T_2341 node _T_2342 = bits(_WIRE_163, 21, 21) connect _WIRE_162.u, _T_2342 node _T_2343 = bits(_WIRE_163, 41, 22) connect _WIRE_162.ppn, _T_2343 node _T_2344 = eq(sectored_entries[2][3].tag_v, UInt<1>(0h1)) when _T_2344 : connect sectored_entries[2][3].valid[0], UInt<1>(0h0) wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_165 : UInt<42> connect _WIRE_165, sectored_entries[3][0].data[0] node _T_2345 = bits(_WIRE_165, 0, 0) connect _WIRE_164.fragmented_superpage, _T_2345 node _T_2346 = bits(_WIRE_165, 1, 1) connect _WIRE_164.c, _T_2346 node _T_2347 = bits(_WIRE_165, 2, 2) connect _WIRE_164.eff, _T_2347 node _T_2348 = bits(_WIRE_165, 3, 3) connect _WIRE_164.paa, _T_2348 node _T_2349 = bits(_WIRE_165, 4, 4) connect _WIRE_164.pal, _T_2349 node _T_2350 = bits(_WIRE_165, 5, 5) connect _WIRE_164.ppp, _T_2350 node _T_2351 = bits(_WIRE_165, 6, 6) connect _WIRE_164.pr, _T_2351 node _T_2352 = bits(_WIRE_165, 7, 7) connect _WIRE_164.px, _T_2352 node _T_2353 = bits(_WIRE_165, 8, 8) connect _WIRE_164.pw, _T_2353 node _T_2354 = bits(_WIRE_165, 9, 9) connect _WIRE_164.hr, _T_2354 node _T_2355 = bits(_WIRE_165, 10, 10) connect _WIRE_164.hx, _T_2355 node _T_2356 = bits(_WIRE_165, 11, 11) connect _WIRE_164.hw, _T_2356 node _T_2357 = bits(_WIRE_165, 12, 12) connect _WIRE_164.sr, _T_2357 node _T_2358 = bits(_WIRE_165, 13, 13) connect _WIRE_164.sx, _T_2358 node _T_2359 = bits(_WIRE_165, 14, 14) connect _WIRE_164.sw, _T_2359 node _T_2360 = bits(_WIRE_165, 15, 15) connect _WIRE_164.gf, _T_2360 node _T_2361 = bits(_WIRE_165, 16, 16) connect _WIRE_164.pf, _T_2361 node _T_2362 = bits(_WIRE_165, 17, 17) connect _WIRE_164.ae_stage2, _T_2362 node _T_2363 = bits(_WIRE_165, 18, 18) connect _WIRE_164.ae_final, _T_2363 node _T_2364 = bits(_WIRE_165, 19, 19) connect _WIRE_164.ae_ptw, _T_2364 node _T_2365 = bits(_WIRE_165, 20, 20) connect _WIRE_164.g, _T_2365 node _T_2366 = bits(_WIRE_165, 21, 21) connect _WIRE_164.u, _T_2366 node _T_2367 = bits(_WIRE_165, 41, 22) connect _WIRE_164.ppn, _T_2367 node _T_2368 = eq(sectored_entries[3][0].tag_v, UInt<1>(0h1)) when _T_2368 : connect sectored_entries[3][0].valid[0], UInt<1>(0h0) wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_167 : UInt<42> connect _WIRE_167, sectored_entries[3][1].data[0] node _T_2369 = bits(_WIRE_167, 0, 0) connect _WIRE_166.fragmented_superpage, _T_2369 node _T_2370 = bits(_WIRE_167, 1, 1) connect _WIRE_166.c, _T_2370 node _T_2371 = bits(_WIRE_167, 2, 2) connect _WIRE_166.eff, _T_2371 node _T_2372 = bits(_WIRE_167, 3, 3) connect _WIRE_166.paa, _T_2372 node _T_2373 = bits(_WIRE_167, 4, 4) connect _WIRE_166.pal, _T_2373 node _T_2374 = bits(_WIRE_167, 5, 5) connect _WIRE_166.ppp, _T_2374 node _T_2375 = bits(_WIRE_167, 6, 6) connect _WIRE_166.pr, _T_2375 node _T_2376 = bits(_WIRE_167, 7, 7) connect _WIRE_166.px, _T_2376 node _T_2377 = bits(_WIRE_167, 8, 8) connect _WIRE_166.pw, _T_2377 node _T_2378 = bits(_WIRE_167, 9, 9) connect _WIRE_166.hr, _T_2378 node _T_2379 = bits(_WIRE_167, 10, 10) connect _WIRE_166.hx, _T_2379 node _T_2380 = bits(_WIRE_167, 11, 11) connect _WIRE_166.hw, _T_2380 node _T_2381 = bits(_WIRE_167, 12, 12) connect _WIRE_166.sr, _T_2381 node _T_2382 = bits(_WIRE_167, 13, 13) connect _WIRE_166.sx, _T_2382 node _T_2383 = bits(_WIRE_167, 14, 14) connect _WIRE_166.sw, _T_2383 node _T_2384 = bits(_WIRE_167, 15, 15) connect _WIRE_166.gf, _T_2384 node _T_2385 = bits(_WIRE_167, 16, 16) connect _WIRE_166.pf, _T_2385 node _T_2386 = bits(_WIRE_167, 17, 17) connect _WIRE_166.ae_stage2, _T_2386 node _T_2387 = bits(_WIRE_167, 18, 18) connect _WIRE_166.ae_final, _T_2387 node _T_2388 = bits(_WIRE_167, 19, 19) connect _WIRE_166.ae_ptw, _T_2388 node _T_2389 = bits(_WIRE_167, 20, 20) connect _WIRE_166.g, _T_2389 node _T_2390 = bits(_WIRE_167, 21, 21) connect _WIRE_166.u, _T_2390 node _T_2391 = bits(_WIRE_167, 41, 22) connect _WIRE_166.ppn, _T_2391 node _T_2392 = eq(sectored_entries[3][1].tag_v, UInt<1>(0h1)) when _T_2392 : connect sectored_entries[3][1].valid[0], UInt<1>(0h0) wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_169 : UInt<42> connect _WIRE_169, sectored_entries[3][2].data[0] node _T_2393 = bits(_WIRE_169, 0, 0) connect _WIRE_168.fragmented_superpage, _T_2393 node _T_2394 = bits(_WIRE_169, 1, 1) connect _WIRE_168.c, _T_2394 node _T_2395 = bits(_WIRE_169, 2, 2) connect _WIRE_168.eff, _T_2395 node _T_2396 = bits(_WIRE_169, 3, 3) connect _WIRE_168.paa, _T_2396 node _T_2397 = bits(_WIRE_169, 4, 4) connect _WIRE_168.pal, _T_2397 node _T_2398 = bits(_WIRE_169, 5, 5) connect _WIRE_168.ppp, _T_2398 node _T_2399 = bits(_WIRE_169, 6, 6) connect _WIRE_168.pr, _T_2399 node _T_2400 = bits(_WIRE_169, 7, 7) connect _WIRE_168.px, _T_2400 node _T_2401 = bits(_WIRE_169, 8, 8) connect _WIRE_168.pw, _T_2401 node _T_2402 = bits(_WIRE_169, 9, 9) connect _WIRE_168.hr, _T_2402 node _T_2403 = bits(_WIRE_169, 10, 10) connect _WIRE_168.hx, _T_2403 node _T_2404 = bits(_WIRE_169, 11, 11) connect _WIRE_168.hw, _T_2404 node _T_2405 = bits(_WIRE_169, 12, 12) connect _WIRE_168.sr, _T_2405 node _T_2406 = bits(_WIRE_169, 13, 13) connect _WIRE_168.sx, _T_2406 node _T_2407 = bits(_WIRE_169, 14, 14) connect _WIRE_168.sw, _T_2407 node _T_2408 = bits(_WIRE_169, 15, 15) connect _WIRE_168.gf, _T_2408 node _T_2409 = bits(_WIRE_169, 16, 16) connect _WIRE_168.pf, _T_2409 node _T_2410 = bits(_WIRE_169, 17, 17) connect _WIRE_168.ae_stage2, _T_2410 node _T_2411 = bits(_WIRE_169, 18, 18) connect _WIRE_168.ae_final, _T_2411 node _T_2412 = bits(_WIRE_169, 19, 19) connect _WIRE_168.ae_ptw, _T_2412 node _T_2413 = bits(_WIRE_169, 20, 20) connect _WIRE_168.g, _T_2413 node _T_2414 = bits(_WIRE_169, 21, 21) connect _WIRE_168.u, _T_2414 node _T_2415 = bits(_WIRE_169, 41, 22) connect _WIRE_168.ppn, _T_2415 node _T_2416 = eq(sectored_entries[3][2].tag_v, UInt<1>(0h1)) when _T_2416 : connect sectored_entries[3][2].valid[0], UInt<1>(0h0) wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_171 : UInt<42> connect _WIRE_171, sectored_entries[3][3].data[0] node _T_2417 = bits(_WIRE_171, 0, 0) connect _WIRE_170.fragmented_superpage, _T_2417 node _T_2418 = bits(_WIRE_171, 1, 1) connect _WIRE_170.c, _T_2418 node _T_2419 = bits(_WIRE_171, 2, 2) connect _WIRE_170.eff, _T_2419 node _T_2420 = bits(_WIRE_171, 3, 3) connect _WIRE_170.paa, _T_2420 node _T_2421 = bits(_WIRE_171, 4, 4) connect _WIRE_170.pal, _T_2421 node _T_2422 = bits(_WIRE_171, 5, 5) connect _WIRE_170.ppp, _T_2422 node _T_2423 = bits(_WIRE_171, 6, 6) connect _WIRE_170.pr, _T_2423 node _T_2424 = bits(_WIRE_171, 7, 7) connect _WIRE_170.px, _T_2424 node _T_2425 = bits(_WIRE_171, 8, 8) connect _WIRE_170.pw, _T_2425 node _T_2426 = bits(_WIRE_171, 9, 9) connect _WIRE_170.hr, _T_2426 node _T_2427 = bits(_WIRE_171, 10, 10) connect _WIRE_170.hx, _T_2427 node _T_2428 = bits(_WIRE_171, 11, 11) connect _WIRE_170.hw, _T_2428 node _T_2429 = bits(_WIRE_171, 12, 12) connect _WIRE_170.sr, _T_2429 node _T_2430 = bits(_WIRE_171, 13, 13) connect _WIRE_170.sx, _T_2430 node _T_2431 = bits(_WIRE_171, 14, 14) connect _WIRE_170.sw, _T_2431 node _T_2432 = bits(_WIRE_171, 15, 15) connect _WIRE_170.gf, _T_2432 node _T_2433 = bits(_WIRE_171, 16, 16) connect _WIRE_170.pf, _T_2433 node _T_2434 = bits(_WIRE_171, 17, 17) connect _WIRE_170.ae_stage2, _T_2434 node _T_2435 = bits(_WIRE_171, 18, 18) connect _WIRE_170.ae_final, _T_2435 node _T_2436 = bits(_WIRE_171, 19, 19) connect _WIRE_170.ae_ptw, _T_2436 node _T_2437 = bits(_WIRE_171, 20, 20) connect _WIRE_170.g, _T_2437 node _T_2438 = bits(_WIRE_171, 21, 21) connect _WIRE_170.u, _T_2438 node _T_2439 = bits(_WIRE_171, 41, 22) connect _WIRE_170.ppn, _T_2439 node _T_2440 = eq(sectored_entries[3][3].tag_v, UInt<1>(0h1)) when _T_2440 : connect sectored_entries[3][3].valid[0], UInt<1>(0h0) wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_173 : UInt<42> connect _WIRE_173, superpage_entries[0].data[0] node _T_2441 = bits(_WIRE_173, 0, 0) connect _WIRE_172.fragmented_superpage, _T_2441 node _T_2442 = bits(_WIRE_173, 1, 1) connect _WIRE_172.c, _T_2442 node _T_2443 = bits(_WIRE_173, 2, 2) connect _WIRE_172.eff, _T_2443 node _T_2444 = bits(_WIRE_173, 3, 3) connect _WIRE_172.paa, _T_2444 node _T_2445 = bits(_WIRE_173, 4, 4) connect _WIRE_172.pal, _T_2445 node _T_2446 = bits(_WIRE_173, 5, 5) connect _WIRE_172.ppp, _T_2446 node _T_2447 = bits(_WIRE_173, 6, 6) connect _WIRE_172.pr, _T_2447 node _T_2448 = bits(_WIRE_173, 7, 7) connect _WIRE_172.px, _T_2448 node _T_2449 = bits(_WIRE_173, 8, 8) connect _WIRE_172.pw, _T_2449 node _T_2450 = bits(_WIRE_173, 9, 9) connect _WIRE_172.hr, _T_2450 node _T_2451 = bits(_WIRE_173, 10, 10) connect _WIRE_172.hx, _T_2451 node _T_2452 = bits(_WIRE_173, 11, 11) connect _WIRE_172.hw, _T_2452 node _T_2453 = bits(_WIRE_173, 12, 12) connect _WIRE_172.sr, _T_2453 node _T_2454 = bits(_WIRE_173, 13, 13) connect _WIRE_172.sx, _T_2454 node _T_2455 = bits(_WIRE_173, 14, 14) connect _WIRE_172.sw, _T_2455 node _T_2456 = bits(_WIRE_173, 15, 15) connect _WIRE_172.gf, _T_2456 node _T_2457 = bits(_WIRE_173, 16, 16) connect _WIRE_172.pf, _T_2457 node _T_2458 = bits(_WIRE_173, 17, 17) connect _WIRE_172.ae_stage2, _T_2458 node _T_2459 = bits(_WIRE_173, 18, 18) connect _WIRE_172.ae_final, _T_2459 node _T_2460 = bits(_WIRE_173, 19, 19) connect _WIRE_172.ae_ptw, _T_2460 node _T_2461 = bits(_WIRE_173, 20, 20) connect _WIRE_172.g, _T_2461 node _T_2462 = bits(_WIRE_173, 21, 21) connect _WIRE_172.u, _T_2462 node _T_2463 = bits(_WIRE_173, 41, 22) connect _WIRE_172.ppn, _T_2463 node _T_2464 = eq(superpage_entries[0].tag_v, UInt<1>(0h1)) when _T_2464 : connect superpage_entries[0].valid[0], UInt<1>(0h0) wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>} wire _WIRE_175 : UInt<42> connect _WIRE_175, special_entry.data[0] node _T_2465 = bits(_WIRE_175, 0, 0) connect _WIRE_174.fragmented_superpage, _T_2465 node _T_2466 = bits(_WIRE_175, 1, 1) connect _WIRE_174.c, _T_2466 node _T_2467 = bits(_WIRE_175, 2, 2) connect _WIRE_174.eff, _T_2467 node _T_2468 = bits(_WIRE_175, 3, 3) connect _WIRE_174.paa, _T_2468 node _T_2469 = bits(_WIRE_175, 4, 4) connect _WIRE_174.pal, _T_2469 node _T_2470 = bits(_WIRE_175, 5, 5) connect _WIRE_174.ppp, _T_2470 node _T_2471 = bits(_WIRE_175, 6, 6) connect _WIRE_174.pr, _T_2471 node _T_2472 = bits(_WIRE_175, 7, 7) connect _WIRE_174.px, _T_2472 node _T_2473 = bits(_WIRE_175, 8, 8) connect _WIRE_174.pw, _T_2473 node _T_2474 = bits(_WIRE_175, 9, 9) connect _WIRE_174.hr, _T_2474 node _T_2475 = bits(_WIRE_175, 10, 10) connect _WIRE_174.hx, _T_2475 node _T_2476 = bits(_WIRE_175, 11, 11) connect _WIRE_174.hw, _T_2476 node _T_2477 = bits(_WIRE_175, 12, 12) connect _WIRE_174.sr, _T_2477 node _T_2478 = bits(_WIRE_175, 13, 13) connect _WIRE_174.sx, _T_2478 node _T_2479 = bits(_WIRE_175, 14, 14) connect _WIRE_174.sw, _T_2479 node _T_2480 = bits(_WIRE_175, 15, 15) connect _WIRE_174.gf, _T_2480 node _T_2481 = bits(_WIRE_175, 16, 16) connect _WIRE_174.pf, _T_2481 node _T_2482 = bits(_WIRE_175, 17, 17) connect _WIRE_174.ae_stage2, _T_2482 node _T_2483 = bits(_WIRE_175, 18, 18) connect _WIRE_174.ae_final, _T_2483 node _T_2484 = bits(_WIRE_175, 19, 19) connect _WIRE_174.ae_ptw, _T_2484 node _T_2485 = bits(_WIRE_175, 20, 20) connect _WIRE_174.g, _T_2485 node _T_2486 = bits(_WIRE_175, 21, 21) connect _WIRE_174.u, _T_2486 node _T_2487 = bits(_WIRE_175, 41, 22) connect _WIRE_174.ppn, _T_2487 node _T_2488 = eq(special_entry.tag_v, UInt<1>(0h1)) when _T_2488 : connect special_entry.valid[0], UInt<1>(0h0) connect v_entries_use_stage1, vstage1_en node _T_2489 = asUInt(reset) node _T_2490 = or(multipleHits, _T_2489) when _T_2490 : connect sectored_entries[0][0].valid[0], UInt<1>(0h0) connect sectored_entries[0][1].valid[0], UInt<1>(0h0) connect sectored_entries[0][2].valid[0], UInt<1>(0h0) connect sectored_entries[0][3].valid[0], UInt<1>(0h0) connect sectored_entries[1][0].valid[0], UInt<1>(0h0) connect sectored_entries[1][1].valid[0], UInt<1>(0h0) connect sectored_entries[1][2].valid[0], UInt<1>(0h0) connect sectored_entries[1][3].valid[0], UInt<1>(0h0) connect sectored_entries[2][0].valid[0], UInt<1>(0h0) connect sectored_entries[2][1].valid[0], UInt<1>(0h0) connect sectored_entries[2][2].valid[0], UInt<1>(0h0) connect sectored_entries[2][3].valid[0], UInt<1>(0h0) connect sectored_entries[3][0].valid[0], UInt<1>(0h0) connect sectored_entries[3][1].valid[0], UInt<1>(0h0) connect sectored_entries[3][2].valid[0], UInt<1>(0h0) connect sectored_entries[3][3].valid[0], UInt<1>(0h0) connect superpage_entries[0].valid[0], UInt<1>(0h0) connect special_entry.valid[0], UInt<1>(0h0) node _T_2491 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_2492 = eq(io.ptw.req.ready, UInt<1>(0h0)) node _T_2493 = and(io.ptw.req.valid, _T_2492) node _T_2494 = eq(state, UInt<2>(0h3)) node _T_2495 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_2496 = and(io.sfence.valid, _T_2495) node _T_2497 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_2498 = and(_T_2496, _T_2497) node _T_2499 = eq(io.sfence.bits.rs1, UInt<1>(0h0)) node _T_2500 = and(io.sfence.valid, _T_2499) node _T_2501 = and(_T_2500, io.sfence.bits.rs2) node _T_2502 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_2503 = eq(io.sfence.bits.rs2, UInt<1>(0h0)) node _T_2504 = and(_T_2502, _T_2503) node _T_2505 = and(io.sfence.valid, io.sfence.bits.rs1) node _T_2506 = and(_T_2505, io.sfence.bits.rs2)	module DTLB_14( // @[TLB.scala:318:7] input clock, // @[TLB.scala:318:7] input reset, // @[TLB.scala:318:7] output io_req_ready, // @[TLB.scala:320:14] input io_req_valid, // @[TLB.scala:320:14] input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14] input [1:0] io_req_bits_size, // @[TLB.scala:320:14] input [4:0] io_req_bits_cmd, // @[TLB.scala:320:14] output io_resp_miss, // @[TLB.scala:320:14] output [31:0] io_resp_paddr, // @[TLB.scala:320:14] input io_sfence_valid, // @[TLB.scala:320:14] input io_ptw_req_ready, // @[TLB.scala:320:14] output io_ptw_req_valid, // @[TLB.scala:320:14] output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14] output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14] input io_ptw_resp_valid, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14] input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14] input io_ptw_resp_bits_pf, // @[TLB.scala:320:14] input io_ptw_resp_bits_gf, // @[TLB.scala:320:14] input io_ptw_resp_bits_hr, // @[TLB.scala:320:14] input io_ptw_resp_bits_hw, // @[TLB.scala:320:14] input io_ptw_resp_bits_hx, // @[TLB.scala:320:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14] input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14] input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14] input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14] input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14] input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14] input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14] input io_ptw_status_debug, // @[TLB.scala:320:14] input io_ptw_status_cease, // @[TLB.scala:320:14] input io_ptw_status_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_status_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14] input io_ptw_status_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14] input io_ptw_status_v, // @[TLB.scala:320:14] input io_ptw_status_sd, // @[TLB.scala:320:14] input [22:0] io_ptw_status_zero2, // @[TLB.scala:320:14] input io_ptw_status_mpv, // @[TLB.scala:320:14] input io_ptw_status_gva, // @[TLB.scala:320:14] input io_ptw_status_mbe, // @[TLB.scala:320:14] input io_ptw_status_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_status_sxl, // @[TLB.scala:320:14] input [1:0] io_ptw_status_uxl, // @[TLB.scala:320:14] input io_ptw_status_sd_rv32, // @[TLB.scala:320:14] input [7:0] io_ptw_status_zero1, // @[TLB.scala:320:14] input io_ptw_status_tsr, // @[TLB.scala:320:14] input io_ptw_status_tw, // @[TLB.scala:320:14] input io_ptw_status_tvm, // @[TLB.scala:320:14] input io_ptw_status_mxr, // @[TLB.scala:320:14] input io_ptw_status_sum, // @[TLB.scala:320:14] input io_ptw_status_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_status_xs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_status_vs, // @[TLB.scala:320:14] input io_ptw_status_spp, // @[TLB.scala:320:14] input io_ptw_status_mpie, // @[TLB.scala:320:14] input io_ptw_status_ube, // @[TLB.scala:320:14] input io_ptw_status_spie, // @[TLB.scala:320:14] input io_ptw_status_upie, // @[TLB.scala:320:14] input io_ptw_status_mie, // @[TLB.scala:320:14] input io_ptw_status_hie, // @[TLB.scala:320:14] input io_ptw_status_sie, // @[TLB.scala:320:14] input io_ptw_status_uie, // @[TLB.scala:320:14] input io_ptw_hstatus_spvp, // @[TLB.scala:320:14] input io_ptw_hstatus_spv, // @[TLB.scala:320:14] input io_ptw_hstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_debug, // @[TLB.scala:320:14] input io_ptw_gstatus_cease, // @[TLB.scala:320:14] input io_ptw_gstatus_wfi, // @[TLB.scala:320:14] input [31:0] io_ptw_gstatus_isa, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_dprv, // @[TLB.scala:320:14] input io_ptw_gstatus_dv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_prv, // @[TLB.scala:320:14] input io_ptw_gstatus_v, // @[TLB.scala:320:14] input [22:0] io_ptw_gstatus_zero2, // @[TLB.scala:320:14] input io_ptw_gstatus_mpv, // @[TLB.scala:320:14] input io_ptw_gstatus_gva, // @[TLB.scala:320:14] input io_ptw_gstatus_mbe, // @[TLB.scala:320:14] input io_ptw_gstatus_sbe, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_sxl, // @[TLB.scala:320:14] input [7:0] io_ptw_gstatus_zero1, // @[TLB.scala:320:14] input io_ptw_gstatus_tsr, // @[TLB.scala:320:14] input io_ptw_gstatus_tw, // @[TLB.scala:320:14] input io_ptw_gstatus_tvm, // @[TLB.scala:320:14] input io_ptw_gstatus_mxr, // @[TLB.scala:320:14] input io_ptw_gstatus_sum, // @[TLB.scala:320:14] input io_ptw_gstatus_mprv, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_fs, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_mpp, // @[TLB.scala:320:14] input [1:0] io_ptw_gstatus_vs, // @[TLB.scala:320:14] input io_ptw_gstatus_spp, // @[TLB.scala:320:14] input io_ptw_gstatus_mpie, // @[TLB.scala:320:14] input io_ptw_gstatus_ube, // @[TLB.scala:320:14] input io_ptw_gstatus_spie, // @[TLB.scala:320:14] input io_ptw_gstatus_upie, // @[TLB.scala:320:14] input io_ptw_gstatus_mie, // @[TLB.scala:320:14] input io_ptw_gstatus_hie, // @[TLB.scala:320:14] input io_ptw_gstatus_sie, // @[TLB.scala:320:14] input io_ptw_gstatus_uie, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14] input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14] input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14] input [31:0] io_ptw_pmp_7_mask, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_0_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_1_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_2_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_ren, // @[TLB.scala:320:14] input io_ptw_customCSRs_csrs_3_wen, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[TLB.scala:320:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[TLB.scala:320:14] ); wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_4_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_3_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_2_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_1_io_y_c; // @[package.scala:267:25] wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25] wire _entries_barrier_io_y_u; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _entries_barrier_io_y_pf; // @[package.scala:267:25] wire _entries_barrier_io_y_gf; // @[package.scala:267:25] wire _entries_barrier_io_y_sw; // @[package.scala:267:25] wire _entries_barrier_io_y_sx; // @[package.scala:267:25] wire _entries_barrier_io_y_sr; // @[package.scala:267:25] wire _entries_barrier_io_y_hw; // @[package.scala:267:25] wire _entries_barrier_io_y_hx; // @[package.scala:267:25] wire _entries_barrier_io_y_hr; // @[package.scala:267:25] wire _entries_barrier_io_y_pw; // @[package.scala:267:25] wire _entries_barrier_io_y_px; // @[package.scala:267:25] wire _entries_barrier_io_y_pr; // @[package.scala:267:25] wire _entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _entries_barrier_io_y_pal; // @[package.scala:267:25] wire _entries_barrier_io_y_paa; // @[package.scala:267:25] wire _entries_barrier_io_y_eff; // @[package.scala:267:25] wire _entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_io_resp_eff; // @[TLB.scala:422:19] wire _pmp_io_r; // @[TLB.scala:416:19] wire _pmp_io_w; // @[TLB.scala:416:19] wire _pmp_io_x; // @[TLB.scala:416:19] wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7] wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7] wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[TLB.scala:318:7] wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[TLB.scala:318:7] wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7] wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[TLB.scala:318:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7] wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[TLB.scala:318:7] wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[TLB.scala:318:7] wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[TLB.scala:318:7] wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[TLB.scala:318:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[TLB.scala:318:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7] wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[TLB.scala:318:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7] wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[TLB.scala:318:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7] wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[TLB.scala:318:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7] wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[TLB.scala:318:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[TLB.scala:318:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[TLB.scala:318:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[TLB.scala:318:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[TLB.scala:318:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[TLB.scala:318:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[TLB.scala:318:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[TLB.scala:318:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[TLB.scala:318:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[TLB.scala:318:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[TLB.scala:318:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[TLB.scala:318:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[TLB.scala:318:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[TLB.scala:318:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[TLB.scala:318:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[TLB.scala:318:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[TLB.scala:318:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[TLB.scala:318:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[TLB.scala:318:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[TLB.scala:318:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[TLB.scala:318:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[TLB.scala:318:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[TLB.scala:318:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[TLB.scala:318:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[TLB.scala:318:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[TLB.scala:318:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[TLB.scala:318:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[TLB.scala:318:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[TLB.scala:318:7] wire [6:0] hr_array = 7'h7F; // @[TLB.scala:524:21] wire [6:0] hw_array = 7'h7F; // @[TLB.scala:525:21] wire [6:0] hx_array = 7'h7F; // @[TLB.scala:526:21] wire [6:0] _must_alloc_array_T_8 = 7'h7F; // @[TLB.scala:596:19] wire [6:0] _gf_ld_array_T_1 = 7'h7F; // @[TLB.scala:600:50] wire [5:0] stage2_bypass = 6'h3F; // @[TLB.scala:523:27] wire [5:0] _hr_array_T_4 = 6'h3F; // @[TLB.scala:524:111] wire [5:0] _hw_array_T_1 = 6'h3F; // @[TLB.scala:525:55] wire [5:0] _hx_array_T_1 = 6'h3F; // @[TLB.scala:526:55] wire [5:0] _gpa_hits_hit_mask_T_4 = 6'h3F; // @[TLB.scala:606:88] wire [5:0] gpa_hits_hit_mask = 6'h3F; // @[TLB.scala:606:82] wire [5:0] _gpa_hits_T_1 = 6'h3F; // @[TLB.scala:607:16] wire [5:0] gpa_hits = 6'h3F; // @[TLB.scala:607:14] wire [2:0] _state_vec_WIRE_0 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_1 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_2 = 3'h0; // @[Replacement.scala:305:25] wire [2:0] _state_vec_WIRE_3 = 3'h0; // @[Replacement.scala:305:25] wire [6:0] _gf_ld_array_T_2 = 7'h0; // @[TLB.scala:600:46] wire [6:0] gf_ld_array = 7'h0; // @[TLB.scala:600:24] wire [6:0] _gf_st_array_T_1 = 7'h0; // @[TLB.scala:601:53] wire [6:0] gf_st_array = 7'h0; // @[TLB.scala:601:24] wire [6:0] _gf_inst_array_T = 7'h0; // @[TLB.scala:602:36] wire [6:0] gf_inst_array = 7'h0; // @[TLB.scala:602:26] wire [6:0] gpa_hits_need_gpa_mask = 7'h0; // @[TLB.scala:605:73] wire [6:0] _io_resp_gf_ld_T_1 = 7'h0; // @[TLB.scala:637:58] wire [6:0] _io_resp_gf_st_T_1 = 7'h0; // @[TLB.scala:638:65] wire [6:0] _io_resp_gf_inst_T = 7'h0; // @[TLB.scala:639:48] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[TLB.scala:318:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[TLB.scala:318:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[TLB.scala:318:7] wire [38:0] io_sfence_bits_addr = 39'h0; // @[TLB.scala:318:7, :320:14] wire [1:0] io_ptw_gstatus_xs = 2'h3; // @[TLB.scala:318:7] wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd = 1'h1; // @[TLB.scala:318:7] wire priv_uses_vm = 1'h1; // @[TLB.scala:372:27] wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64] wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81] wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire _hitsVec_T_37 = 1'h1; // @[TLB.scala:183:40] wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire _priv_rw_ok_T = 1'h1; // @[TLB.scala:513:24] wire _priv_rw_ok_T_1 = 1'h1; // @[TLB.scala:513:32] wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire ignore_2 = 1'h1; // @[TLB.scala:182:34] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7] wire [5:0] _priv_rw_ok_T_6 = 6'h0; // @[TLB.scala:513:75] wire [5:0] _stage1_bypass_T = 6'h0; // @[TLB.scala:517:27] wire [5:0] stage1_bypass = 6'h0; // @[TLB.scala:517:61] wire [5:0] _gpa_hits_T = 6'h0; // @[TLB.scala:607:30] wire [1:0] io_req_bits_prv = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7, :320:14] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7, :320:14] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire [15:0] satp_asid = 16'h0; // @[TLB.scala:318:7, :320:14, :373:17] wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7] wire io_req_bits_v = 1'h0; // @[TLB.scala:318:7] wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7] wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7] wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs1 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_rs2 = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_asid = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hv = 1'h0; // @[TLB.scala:318:7] wire io_sfence_bits_hg = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[TLB.scala:318:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[TLB.scala:318:7] wire io_kill = 1'h0; // @[TLB.scala:318:7] wire priv_v = 1'h0; // @[TLB.scala:369:34] wire priv_s = 1'h0; // @[TLB.scala:370:20] wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire vstage1_en = 1'h0; // @[TLB.scala:376:48] wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire stage2_en = 1'h0; // @[TLB.scala:378:48] wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire refill_v = 1'h0; // @[TLB.scala:448:33] wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire _waddr_T = 1'h0; // @[TLB.scala:477:45] wire _mxr_T = 1'h0; // @[TLB.scala:518:36] wire cmd_readx = 1'h0; // @[TLB.scala:575:37] wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:183:37] wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:183:37] wire _io_req_ready_T; // @[TLB.scala:631:25] wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire _r_superpage_repl_addr_T_3 = 1'h0; // @[TLB.scala:757:8] wire hv = 1'h0; // @[TLB.scala:721:36] wire hg = 1'h0; // @[TLB.scala:722:36] wire hv_1 = 1'h0; // @[TLB.scala:721:36] wire hg_1 = 1'h0; // @[TLB.scala:722:36] wire hv_2 = 1'h0; // @[TLB.scala:721:36] wire hg_2 = 1'h0; // @[TLB.scala:722:36] wire hv_3 = 1'h0; // @[TLB.scala:721:36] wire hg_3 = 1'h0; // @[TLB.scala:722:36] wire hv_4 = 1'h0; // @[TLB.scala:721:36] wire hg_4 = 1'h0; // @[TLB.scala:722:36] wire hv_5 = 1'h0; // @[TLB.scala:721:36] wire hg_5 = 1'h0; // @[TLB.scala:722:36] wire hv_6 = 1'h0; // @[TLB.scala:721:36] wire hg_6 = 1'h0; // @[TLB.scala:722:36] wire hv_7 = 1'h0; // @[TLB.scala:721:36] wire hg_7 = 1'h0; // @[TLB.scala:722:36] wire hv_8 = 1'h0; // @[TLB.scala:721:36] wire hg_8 = 1'h0; // @[TLB.scala:722:36] wire hv_9 = 1'h0; // @[TLB.scala:721:36] wire hg_9 = 1'h0; // @[TLB.scala:722:36] wire hv_10 = 1'h0; // @[TLB.scala:721:36] wire hg_10 = 1'h0; // @[TLB.scala:722:36] wire hv_11 = 1'h0; // @[TLB.scala:721:36] wire hg_11 = 1'h0; // @[TLB.scala:722:36] wire hv_12 = 1'h0; // @[TLB.scala:721:36] wire hg_12 = 1'h0; // @[TLB.scala:722:36] wire hv_13 = 1'h0; // @[TLB.scala:721:36] wire hg_13 = 1'h0; // @[TLB.scala:722:36] wire hv_14 = 1'h0; // @[TLB.scala:721:36] wire hg_14 = 1'h0; // @[TLB.scala:722:36] wire hv_15 = 1'h0; // @[TLB.scala:721:36] wire hg_15 = 1'h0; // @[TLB.scala:722:36] wire hv_16 = 1'h0; // @[TLB.scala:721:36] wire hg_16 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T = 1'h0; // @[TLB.scala:182:28] wire ignore = 1'h0; // @[TLB.scala:182:34] wire hv_17 = 1'h0; // @[TLB.scala:721:36] wire hg_17 = 1'h0; // @[TLB.scala:722:36] wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire ignore_3 = 1'h0; // @[TLB.scala:182:34] wire [1:0] io_resp_size = io_req_bits_size_0; // @[TLB.scala:318:7] wire [4:0] io_resp_cmd = io_req_bits_cmd_0; // @[TLB.scala:318:7] wire _io_resp_miss_T_2; // @[TLB.scala:651:64] wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8] wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire _io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire _io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire _io_resp_ma_ld_T; // @[TLB.scala:645:31] wire _io_resp_ma_st_T; // @[TLB.scala:646:31] wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire _io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire _io_ptw_req_valid_T; // @[TLB.scala:662:29] wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29] wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24] wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24] wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24] wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24] wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13] wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17] wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17] wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31] wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16] wire io_req_ready_0; // @[TLB.scala:318:7] wire io_resp_pf_ld; // @[TLB.scala:318:7] wire io_resp_pf_st; // @[TLB.scala:318:7] wire io_resp_pf_inst; // @[TLB.scala:318:7] wire io_resp_ae_ld; // @[TLB.scala:318:7] wire io_resp_ae_st; // @[TLB.scala:318:7] wire io_resp_ae_inst; // @[TLB.scala:318:7] wire io_resp_ma_ld; // @[TLB.scala:318:7] wire io_resp_ma_st; // @[TLB.scala:318:7] wire io_resp_miss_0; // @[TLB.scala:318:7] wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7] wire [39:0] io_resp_gpa; // @[TLB.scala:318:7] wire io_resp_cacheable; // @[TLB.scala:318:7] wire io_resp_must_alloc; // @[TLB.scala:318:7] wire io_resp_prefetchable; // @[TLB.scala:318:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] wire io_ptw_req_valid_0; // @[TLB.scala:318:7] wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30] wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30] wire [1:0] memIdx = vpn[1:0]; // @[package.scala:163:13] reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_1_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_1_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_1_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_1_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_1_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_2_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_2_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_2_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_2_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_2_3_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_0_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_0_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_0_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_0_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_0_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_1_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_1_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_1_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_1_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_1_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_2_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_2_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_2_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_2_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_2_valid_0; // @[TLB.scala:339:29] reg [1:0] sectored_entries_3_3_level; // @[TLB.scala:339:29] reg [26:0] sectored_entries_3_3_tag_vpn; // @[TLB.scala:339:29] reg sectored_entries_3_3_tag_v; // @[TLB.scala:339:29] reg [41:0] sectored_entries_3_3_data_0; // @[TLB.scala:339:29] reg sectored_entries_3_3_valid_0; // @[TLB.scala:339:29] reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30] reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30] reg superpage_entries_0_tag_v; // @[TLB.scala:341:30] reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30] wire [41:0] _entries_WIRE_9 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30] reg superpage_entries_0_valid_0; // @[TLB.scala:341:30] wire _r_superpage_repl_addr_T = superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:16] reg [1:0] special_entry_level; // @[TLB.scala:346:56] reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56] reg special_entry_tag_v; // @[TLB.scala:346:56] reg [41:0] special_entry_data_0; // @[TLB.scala:346:56] wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] wire [41:0] _entries_WIRE_11 = special_entry_data_0; // @[TLB.scala:170:77, :346:56] reg special_entry_valid_0; // @[TLB.scala:346:56] reg [1:0] state; // @[TLB.scala:352:22] reg [26:0] r_refill_tag; // @[TLB.scala:354:25] assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25] reg [1:0] r_sectored_repl_addr; // @[TLB.scala:356:33] reg r_sectored_hit_valid; // @[TLB.scala:357:27] reg [1:0] r_sectored_hit_bits; // @[TLB.scala:357:27] reg r_superpage_hit_valid; // @[TLB.scala:358:28] reg r_need_gpa; // @[TLB.scala:361:23] assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23] reg r_gpa_valid; // @[TLB.scala:362:24] reg [38:0] r_gpa; // @[TLB.scala:363:18] reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22] reg r_gpa_is_pte; // @[TLB.scala:365:25] wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41] wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}] wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31] wire _vm_enabled_T_1 = _vm_enabled_T; // @[TLB.scala:399:{31,45}] wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}] wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32] wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29] wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44] wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24] wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52] wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29] wire _T_25 = state == 2'h1; // @[package.scala:16:47] wire _invalidate_refill_T; // @[package.scala:16:47] assign _invalidate_refill_T = _T_25; // @[package.scala:16:47] assign _io_ptw_req_valid_T = _T_25; // @[package.scala:16:47] wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47] wire _invalidate_refill_T_2 = _invalidate_refill_T \| _invalidate_refill_T_1; // @[package.scala:16:47, :81:59] wire invalidate_refill = _invalidate_refill_T_2 \| io_sfence_valid_0; // @[package.scala:81:59] wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77] wire _mpu_ppn_T_22; // @[TLB.scala:170:77] wire _mpu_ppn_T_21; // @[TLB.scala:170:77] wire _mpu_ppn_T_20; // @[TLB.scala:170:77] wire _mpu_ppn_T_19; // @[TLB.scala:170:77] wire _mpu_ppn_T_18; // @[TLB.scala:170:77] wire _mpu_ppn_T_17; // @[TLB.scala:170:77] wire _mpu_ppn_T_16; // @[TLB.scala:170:77] wire _mpu_ppn_T_15; // @[TLB.scala:170:77] wire _mpu_ppn_T_14; // @[TLB.scala:170:77] wire _mpu_ppn_T_13; // @[TLB.scala:170:77] wire _mpu_ppn_T_12; // @[TLB.scala:170:77] wire _mpu_ppn_T_11; // @[TLB.scala:170:77] wire _mpu_ppn_T_10; // @[TLB.scala:170:77] wire _mpu_ppn_T_9; // @[TLB.scala:170:77] wire _mpu_ppn_T_8; // @[TLB.scala:170:77] wire _mpu_ppn_T_7; // @[TLB.scala:170:77] wire _mpu_ppn_T_6; // @[TLB.scala:170:77] wire _mpu_ppn_T_5; // @[TLB.scala:170:77] wire _mpu_ppn_T_4; // @[TLB.scala:170:77] wire _mpu_ppn_T_3; // @[TLB.scala:170:77] wire _mpu_ppn_T_2; // @[TLB.scala:170:77] wire _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77] assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77] assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77] assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77] assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77] assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77] assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77] assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77] assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77] assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77] assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77] assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77] assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77] assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77] assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77] assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77] assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77] assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77] assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77] assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77] assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77] assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77] assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56] wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28] assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28] wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire _ppn_ignore_T_2; // @[TLB.scala:197:28] assign _ppn_ignore_T_2 = _GEN; // @[TLB.scala:197:28] wire _ignore_T_4; // @[TLB.scala:182:28] assign _ignore_T_4 = _GEN; // @[TLB.scala:182:28, :197:28] wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}] wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] \| _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146] wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}] wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20] wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52] wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46] wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82] wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25] wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}] wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, 2'h0}; // @[TLB.scala:318:7, :415:103] wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}] wire cacheable; // @[TLB.scala:425:41] wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46] wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31] assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31] assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46] wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31] assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31] assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31] assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31] assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31] assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46] wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46] wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46] wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46] wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31] assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31] assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31] assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46] wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46] wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46] wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31] assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31] assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31] assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46] wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_51 = _homogeneous_T_50 \| _homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_52 = _homogeneous_T_51 \| _homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_53 = _homogeneous_T_52 \| _homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_54 = _homogeneous_T_53 \| _homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_55 = _homogeneous_T_54 \| _homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_56 = _homogeneous_T_55 \| _homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_57 = _homogeneous_T_56 \| _homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire _homogeneous_T_58 = _homogeneous_T_57 \| _homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire homogeneous = _homogeneous_T_58 \| _homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46] wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46] wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46] wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46] wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46] wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46] wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_93 = _homogeneous_T_92 \| _homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_94 = _homogeneous_T_93 \| _homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_95 = _homogeneous_T_94 \| _homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire _homogeneous_T_96 = _homogeneous_T_95 \| _homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46] wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46] wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_108 = _homogeneous_T_107 \| _homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46] wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46] wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39] wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}] wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}] wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24] wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}] wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24] wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}] wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24] wire [3:0][26:0] _GEN_4 = {{sectored_entries_3_0_tag_vpn}, {sectored_entries_2_0_tag_vpn}, {sectored_entries_1_0_tag_vpn}, {sectored_entries_0_0_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_5 = {{sectored_entries_3_0_tag_v}, {sectored_entries_2_0_tag_v}, {sectored_entries_1_0_tag_v}, {sectored_entries_0_0_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_6 = {{sectored_entries_3_0_data_0}, {sectored_entries_2_0_data_0}, {sectored_entries_1_0_data_0}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_1 = _GEN_6[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_7 = {{sectored_entries_3_0_valid_0}, {sectored_entries_2_0_valid_0}, {sectored_entries_1_0_valid_0}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_8 = {{sectored_entries_3_1_tag_vpn}, {sectored_entries_2_1_tag_vpn}, {sectored_entries_1_1_tag_vpn}, {sectored_entries_0_1_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_9 = {{sectored_entries_3_1_tag_v}, {sectored_entries_2_1_tag_v}, {sectored_entries_1_1_tag_v}, {sectored_entries_0_1_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_10 = {{sectored_entries_3_1_data_0}, {sectored_entries_2_1_data_0}, {sectored_entries_1_1_data_0}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_3 = _GEN_10[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_11 = {{sectored_entries_3_1_valid_0}, {sectored_entries_2_1_valid_0}, {sectored_entries_1_1_valid_0}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_12 = {{sectored_entries_3_2_tag_vpn}, {sectored_entries_2_2_tag_vpn}, {sectored_entries_1_2_tag_vpn}, {sectored_entries_0_2_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_13 = {{sectored_entries_3_2_tag_v}, {sectored_entries_2_2_tag_v}, {sectored_entries_1_2_tag_v}, {sectored_entries_0_2_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_14 = {{sectored_entries_3_2_data_0}, {sectored_entries_2_2_data_0}, {sectored_entries_1_2_data_0}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_5 = _GEN_14[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_15 = {{sectored_entries_3_2_valid_0}, {sectored_entries_2_2_valid_0}, {sectored_entries_1_2_valid_0}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [3:0][26:0] _GEN_16 = {{sectored_entries_3_3_tag_vpn}, {sectored_entries_2_3_tag_vpn}, {sectored_entries_1_3_tag_vpn}, {sectored_entries_0_3_tag_vpn}}; // @[TLB.scala:174:61, :339:29] wire [3:0] _GEN_17 = {{sectored_entries_3_3_tag_v}, {sectored_entries_2_3_tag_v}, {sectored_entries_1_3_tag_v}, {sectored_entries_0_3_tag_v}}; // @[TLB.scala:174:61, :339:29] wire [3:0][41:0] _GEN_18 = {{sectored_entries_3_3_data_0}, {sectored_entries_2_3_data_0}, {sectored_entries_1_3_data_0}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:174:61, :339:29] wire [41:0] _entries_WIRE_7 = _GEN_18[memIdx]; // @[package.scala:163:13] wire [3:0] _GEN_19 = {{sectored_entries_3_3_valid_0}, {sectored_entries_2_3_valid_0}, {sectored_entries_1_3_valid_0}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:174:61, :339:29] wire [26:0] _GEN_20 = _GEN_4[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T; // @[TLB.scala:174:61] assign _sector_hits_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T; // @[TLB.scala:174:61] assign _hitsVec_T = _GEN_20; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_1 = _sector_hits_T; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_2 = _sector_hits_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_4 = _sector_hits_T_2 & _sector_hits_T_3; // @[TLB.scala:174:{86,95,105}] wire sector_hits_0 = _GEN_7[memIdx] & _sector_hits_T_4; // @[package.scala:163:13] wire [26:0] _GEN_21 = _GEN_8[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_5; // @[TLB.scala:174:61] assign _sector_hits_T_5 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61] assign _hitsVec_T_6 = _GEN_21; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_6 = _sector_hits_T_5; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_7 = _sector_hits_T_6 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_8 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_9 = _sector_hits_T_7 & _sector_hits_T_8; // @[TLB.scala:174:{86,95,105}] wire sector_hits_1 = _GEN_11[memIdx] & _sector_hits_T_9; // @[package.scala:163:13] wire [26:0] _GEN_22 = _GEN_12[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_10; // @[TLB.scala:174:61] assign _sector_hits_T_10 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61] assign _hitsVec_T_12 = _GEN_22; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_11 = _sector_hits_T_10; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_12 = _sector_hits_T_11 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_13 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_14 = _sector_hits_T_12 & _sector_hits_T_13; // @[TLB.scala:174:{86,95,105}] wire sector_hits_2 = _GEN_15[memIdx] & _sector_hits_T_14; // @[package.scala:163:13] wire [26:0] _GEN_23 = _GEN_16[memIdx] ^ vpn; // @[package.scala:163:13] wire [26:0] _sector_hits_T_15; // @[TLB.scala:174:61] assign _sector_hits_T_15 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61] assign _hitsVec_T_18 = _GEN_23; // @[TLB.scala:174:61] wire [26:0] _sector_hits_T_16 = _sector_hits_T_15; // @[TLB.scala:174:{61,68}] wire _sector_hits_T_17 = _sector_hits_T_16 == 27'h0; // @[TLB.scala:174:{68,86}] wire _sector_hits_T_18 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _sector_hits_T_19 = _sector_hits_T_17 & _sector_hits_T_18; // @[TLB.scala:174:{86,95,105}] wire sector_hits_3 = _GEN_19[memIdx] & _sector_hits_T_19; // @[package.scala:163:13] wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [26:0] _T_1876 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30] wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52] assign _superpage_hits_T = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52] assign _superpage_hits_T_5 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52] assign _superpage_hits_T_10 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_24; // @[TLB.scala:183:52] assign _hitsVec_T_24 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_29; // @[TLB.scala:183:52] assign _hitsVec_T_29 = _T_1876; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_34; // @[TLB.scala:183:52] assign _hitsVec_T_34 = _T_1876; // @[TLB.scala:183:52] wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}] wire _GEN_24 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30] wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28] assign _superpage_hits_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28] assign _hitsVec_ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire _ppn_ignore_T; // @[TLB.scala:197:28] assign _ppn_ignore_T = _GEN_24; // @[TLB.scala:182:28, :197:28] wire _ignore_T_1; // @[TLB.scala:182:28] assign _ignore_T_1 = _GEN_24; // @[TLB.scala:182:28] wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _superpage_hits_T_8 = superpage_hits_ignore_1 \| _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}] wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29] wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire [26:0] _hitsVec_T_1 = _hitsVec_T; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_2 = _hitsVec_T_1 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_3 = ~_GEN_5[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_5 = _GEN_7[memIdx] & _hitsVec_T_4; // @[package.scala:163:13] wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_7 = _hitsVec_T_6; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_8 = _hitsVec_T_7 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_9 = ~_GEN_9[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_11 = _GEN_11[memIdx] & _hitsVec_T_10; // @[package.scala:163:13] wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_13 = _hitsVec_T_12; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_14 = _hitsVec_T_13 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_15 = ~_GEN_13[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_17 = _GEN_15[memIdx] & _hitsVec_T_16; // @[package.scala:163:13] wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44] wire [26:0] _hitsVec_T_19 = _hitsVec_T_18; // @[TLB.scala:174:{61,68}] wire _hitsVec_T_20 = _hitsVec_T_19 == 27'h0; // @[TLB.scala:174:{68,86}] wire _hitsVec_T_21 = ~_GEN_17[memIdx]; // @[package.scala:163:13] wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire _hitsVec_T_23 = _GEN_19[memIdx] & _hitsVec_T_22; // @[package.scala:163:13] wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44] wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire [8:0] _hitsVec_T_25 = _hitsVec_T_24[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_26 = _hitsVec_T_25 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_27 = _hitsVec_T_26; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_28 = hitsVec_tagMatch & _hitsVec_T_27; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_30 = _hitsVec_T_29[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_31 = _hitsVec_T_30 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_32 = hitsVec_ignore_1 \| _hitsVec_T_31; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_33 = _hitsVec_T_28 & _hitsVec_T_32; // @[TLB.scala:183:{29,40}] wire _hitsVec_T_38 = _hitsVec_T_33; // @[TLB.scala:183:29] wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire [8:0] _hitsVec_T_35 = _hitsVec_T_34[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_36 = _hitsVec_T_35 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire hitsVec_4 = vm_enabled & _hitsVec_T_38; // @[TLB.scala:183:29, :399:61, :440:44] wire _hitsVec_tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire hitsVec_tagMatch_1 = special_entry_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire [26:0] _T_1974 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56] wire [26:0] _hitsVec_T_39; // @[TLB.scala:183:52] assign _hitsVec_T_39 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_44; // @[TLB.scala:183:52] assign _hitsVec_T_44 = _T_1974; // @[TLB.scala:183:52] wire [26:0] _hitsVec_T_49; // @[TLB.scala:183:52] assign _hitsVec_T_49 = _T_1974; // @[TLB.scala:183:52] wire [8:0] _hitsVec_T_40 = _hitsVec_T_39[26:18]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_41 = _hitsVec_T_40 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_42 = _hitsVec_T_41; // @[TLB.scala:183:{40,79}] wire _hitsVec_T_43 = hitsVec_tagMatch_1 & _hitsVec_T_42; // @[TLB.scala:178:33, :183:{29,40}] wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_45 = _hitsVec_T_44[17:9]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_46 = _hitsVec_T_45 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_47 = hitsVec_ignore_4 \| _hitsVec_T_46; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_48 = _hitsVec_T_43 & _hitsVec_T_47; // @[TLB.scala:183:{29,40}] wire _hitsVec_ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire hitsVec_ignore_5 = _hitsVec_ignore_T_5; // @[TLB.scala:182:{28,34}] wire [8:0] _hitsVec_T_50 = _hitsVec_T_49[8:0]; // @[TLB.scala:183:{52,58}] wire _hitsVec_T_51 = _hitsVec_T_50 == 9'h0; // @[TLB.scala:183:{58,79}, :318:7, :320:14] wire _hitsVec_T_52 = hitsVec_ignore_5 \| _hitsVec_T_51; // @[TLB.scala:182:34, :183:{40,79}] wire _hitsVec_T_53 = _hitsVec_T_48 & _hitsVec_T_52; // @[TLB.scala:183:{29,40}] wire hitsVec_5 = vm_enabled & _hitsVec_T_53; // @[TLB.scala:183:29, :399:61, :440:44] wire [1:0] real_hits_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27] wire [2:0] real_hits_lo = {real_hits_lo_hi, hitsVec_0}; // @[package.scala:45:27] wire [1:0] real_hits_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27] wire [2:0] real_hits_hi = {real_hits_hi_hi, hitsVec_3}; // @[package.scala:45:27] wire [5:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27] wire [5:0] _tlb_hit_T = real_hits; // @[package.scala:45:27] wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18] wire [6:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27] wire _newEntry_g_T; // @[TLB.scala:453:25] wire _newEntry_sw_T_6; // @[PTW.scala:151:40] wire _newEntry_sx_T_5; // @[PTW.scala:153:35] wire _newEntry_sr_T_5; // @[PTW.scala:149:35] wire newEntry_g; // @[TLB.scala:449:24] wire newEntry_sw; // @[TLB.scala:449:24] wire newEntry_sx; // @[TLB.scala:449:24] wire newEntry_sr; // @[TLB.scala:449:24] wire newEntry_ppp; // @[TLB.scala:449:24] wire newEntry_pal; // @[TLB.scala:449:24] wire newEntry_paa; // @[TLB.scala:449:24] wire newEntry_eff; // @[TLB.scala:449:24] assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25] assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25] wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53] wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7] wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sr_T_1; // @[TLB.scala:318:7] wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7] wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7] assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24] wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7] wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sw_T_1; // @[TLB.scala:318:7] wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7] wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7] assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24] wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7] wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7] wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 \| _newEntry_sx_T_1; // @[TLB.scala:318:7] wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7] wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7] assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7] assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24] wire [1:0] _GEN_25 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_lo = _GEN_25; // @[TLB.scala:217:24] wire [1:0] _GEN_26 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_lo_hi_hi = _GEN_26; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_27 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_lo_hi = _GEN_27; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_28 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_lo_hi_hi_hi = _GEN_28; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_29 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_lo_hi = _GEN_29; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [1:0] _GEN_30 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_lo_hi_hi = _GEN_30; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [1:0] _GEN_31 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24] wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [1:0] sectored_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_lo_hi = _GEN_31; // @[TLB.scala:217:24] wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [20:0] _GEN_32 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24] wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign special_entry_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_0_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_1_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_2_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [20:0] sectored_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24] assign sectored_entries_3_data_0_hi_hi_hi_hi = _GEN_32; // @[TLB.scala:217:24] wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24] wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13] wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [1:0] r_memIdx = r_refill_tag[1:0]; // @[package.scala:163:13] wire [1:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22] wire [2:0] sectored_entries_0_data_0_lo_lo_hi = {sectored_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_0_data_0_lo_lo = {sectored_entries_0_data_0_lo_lo_hi, sectored_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_lo_hi_lo = {sectored_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_lo_hi_hi = {sectored_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_lo_hi = {sectored_entries_0_data_0_lo_hi_hi, sectored_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_0_data_0_lo = {sectored_entries_0_data_0_lo_hi, sectored_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_lo_lo = {sectored_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_0_data_0_hi_lo_hi = {sectored_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_0_data_0_hi_lo = {sectored_entries_0_data_0_hi_lo_hi, sectored_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_0_data_0_hi_hi_lo = {sectored_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_0_data_0_hi_hi_hi = {sectored_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_0_data_0_hi_hi = {sectored_entries_0_data_0_hi_hi_hi, sectored_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_0_data_0_hi = {sectored_entries_0_data_0_hi_hi, sectored_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_0_data_0_T = {sectored_entries_0_data_0_hi, sectored_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_lo_hi = {sectored_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_1_data_0_lo_lo = {sectored_entries_1_data_0_lo_lo_hi, sectored_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_lo_hi_lo = {sectored_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_lo_hi_hi = {sectored_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_lo_hi = {sectored_entries_1_data_0_lo_hi_hi, sectored_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_1_data_0_lo = {sectored_entries_1_data_0_lo_hi, sectored_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_lo_lo = {sectored_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_1_data_0_hi_lo_hi = {sectored_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_1_data_0_hi_lo = {sectored_entries_1_data_0_hi_lo_hi, sectored_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_1_data_0_hi_hi_lo = {sectored_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_1_data_0_hi_hi_hi = {sectored_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_1_data_0_hi_hi = {sectored_entries_1_data_0_hi_hi_hi, sectored_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_1_data_0_hi = {sectored_entries_1_data_0_hi_hi, sectored_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_1_data_0_T = {sectored_entries_1_data_0_hi, sectored_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_lo_hi = {sectored_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_2_data_0_lo_lo = {sectored_entries_2_data_0_lo_lo_hi, sectored_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_lo_hi_lo = {sectored_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_lo_hi_hi = {sectored_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_lo_hi = {sectored_entries_2_data_0_lo_hi_hi, sectored_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_2_data_0_lo = {sectored_entries_2_data_0_lo_hi, sectored_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_lo_lo = {sectored_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_2_data_0_hi_lo_hi = {sectored_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_2_data_0_hi_lo = {sectored_entries_2_data_0_hi_lo_hi, sectored_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_2_data_0_hi_hi_lo = {sectored_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_2_data_0_hi_hi_hi = {sectored_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_2_data_0_hi_hi = {sectored_entries_2_data_0_hi_hi_hi, sectored_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_2_data_0_hi = {sectored_entries_2_data_0_hi_hi, sectored_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_2_data_0_T = {sectored_entries_2_data_0_hi, sectored_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_lo_hi = {sectored_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] sectored_entries_3_data_0_lo_lo = {sectored_entries_3_data_0_lo_lo_hi, sectored_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_lo_hi_lo = {sectored_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_lo_hi_hi = {sectored_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_lo_hi = {sectored_entries_3_data_0_lo_hi_hi, sectored_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] sectored_entries_3_data_0_lo = {sectored_entries_3_data_0_lo_hi, sectored_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_lo_lo = {sectored_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24] wire [2:0] sectored_entries_3_data_0_hi_lo_hi = {sectored_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24] wire [5:0] sectored_entries_3_data_0_hi_lo = {sectored_entries_3_data_0_hi_lo_hi, sectored_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24] wire [2:0] sectored_entries_3_data_0_hi_hi_lo = {sectored_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24] wire [21:0] sectored_entries_3_data_0_hi_hi_hi = {sectored_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24] wire [24:0] sectored_entries_3_data_0_hi_hi = {sectored_entries_3_data_0_hi_hi_hi, sectored_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24] wire [30:0] sectored_entries_3_data_0_hi = {sectored_entries_3_data_0_hi_hi, sectored_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24] wire [41:0] _sectored_entries_3_data_0_T = {sectored_entries_3_data_0_hi, sectored_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [19:0] _entries_T_22; // @[TLB.scala:170:77] wire _entries_T_21; // @[TLB.scala:170:77] wire _entries_T_20; // @[TLB.scala:170:77] wire _entries_T_19; // @[TLB.scala:170:77] wire _entries_T_18; // @[TLB.scala:170:77] wire _entries_T_17; // @[TLB.scala:170:77] wire _entries_T_16; // @[TLB.scala:170:77] wire _entries_T_15; // @[TLB.scala:170:77] wire _entries_T_14; // @[TLB.scala:170:77] wire _entries_T_13; // @[TLB.scala:170:77] wire _entries_T_12; // @[TLB.scala:170:77] wire _entries_T_11; // @[TLB.scala:170:77] wire _entries_T_10; // @[TLB.scala:170:77] wire _entries_T_9; // @[TLB.scala:170:77] wire _entries_T_8; // @[TLB.scala:170:77] wire _entries_T_7; // @[TLB.scala:170:77] wire _entries_T_6; // @[TLB.scala:170:77] wire _entries_T_5; // @[TLB.scala:170:77] wire _entries_T_4; // @[TLB.scala:170:77] wire _entries_T_3; // @[TLB.scala:170:77] wire _entries_T_2; // @[TLB.scala:170:77] wire _entries_T_1; // @[TLB.scala:170:77] wire _entries_T; // @[TLB.scala:170:77] assign _entries_T = _entries_WIRE_1[0]; // @[TLB.scala:170:77] wire _entries_WIRE_fragmented_superpage = _entries_T; // @[TLB.scala:170:77] assign _entries_T_1 = _entries_WIRE_1[1]; // @[TLB.scala:170:77] wire _entries_WIRE_c = _entries_T_1; // @[TLB.scala:170:77] assign _entries_T_2 = _entries_WIRE_1[2]; // @[TLB.scala:170:77] wire _entries_WIRE_eff = _entries_T_2; // @[TLB.scala:170:77] assign _entries_T_3 = _entries_WIRE_1[3]; // @[TLB.scala:170:77] wire _entries_WIRE_paa = _entries_T_3; // @[TLB.scala:170:77] assign _entries_T_4 = _entries_WIRE_1[4]; // @[TLB.scala:170:77] wire _entries_WIRE_pal = _entries_T_4; // @[TLB.scala:170:77] assign _entries_T_5 = _entries_WIRE_1[5]; // @[TLB.scala:170:77] wire _entries_WIRE_ppp = _entries_T_5; // @[TLB.scala:170:77] assign _entries_T_6 = _entries_WIRE_1[6]; // @[TLB.scala:170:77] wire _entries_WIRE_pr = _entries_T_6; // @[TLB.scala:170:77] assign _entries_T_7 = _entries_WIRE_1[7]; // @[TLB.scala:170:77] wire _entries_WIRE_px = _entries_T_7; // @[TLB.scala:170:77] assign _entries_T_8 = _entries_WIRE_1[8]; // @[TLB.scala:170:77] wire _entries_WIRE_pw = _entries_T_8; // @[TLB.scala:170:77] assign _entries_T_9 = _entries_WIRE_1[9]; // @[TLB.scala:170:77] wire _entries_WIRE_hr = _entries_T_9; // @[TLB.scala:170:77] assign _entries_T_10 = _entries_WIRE_1[10]; // @[TLB.scala:170:77] wire _entries_WIRE_hx = _entries_T_10; // @[TLB.scala:170:77] assign _entries_T_11 = _entries_WIRE_1[11]; // @[TLB.scala:170:77] wire _entries_WIRE_hw = _entries_T_11; // @[TLB.scala:170:77] assign _entries_T_12 = _entries_WIRE_1[12]; // @[TLB.scala:170:77] wire _entries_WIRE_sr = _entries_T_12; // @[TLB.scala:170:77] assign _entries_T_13 = _entries_WIRE_1[13]; // @[TLB.scala:170:77] wire _entries_WIRE_sx = _entries_T_13; // @[TLB.scala:170:77] assign _entries_T_14 = _entries_WIRE_1[14]; // @[TLB.scala:170:77] wire _entries_WIRE_sw = _entries_T_14; // @[TLB.scala:170:77] assign _entries_T_15 = _entries_WIRE_1[15]; // @[TLB.scala:170:77] wire _entries_WIRE_gf = _entries_T_15; // @[TLB.scala:170:77] assign _entries_T_16 = _entries_WIRE_1[16]; // @[TLB.scala:170:77] wire _entries_WIRE_pf = _entries_T_16; // @[TLB.scala:170:77] assign _entries_T_17 = _entries_WIRE_1[17]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_stage2 = _entries_T_17; // @[TLB.scala:170:77] assign _entries_T_18 = _entries_WIRE_1[18]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_final = _entries_T_18; // @[TLB.scala:170:77] assign _entries_T_19 = _entries_WIRE_1[19]; // @[TLB.scala:170:77] wire _entries_WIRE_ae_ptw = _entries_T_19; // @[TLB.scala:170:77] assign _entries_T_20 = _entries_WIRE_1[20]; // @[TLB.scala:170:77] wire _entries_WIRE_g = _entries_T_20; // @[TLB.scala:170:77] assign _entries_T_21 = _entries_WIRE_1[21]; // @[TLB.scala:170:77] wire _entries_WIRE_u = _entries_T_21; // @[TLB.scala:170:77] assign _entries_T_22 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_ppn = _entries_T_22; // @[TLB.scala:170:77] wire [19:0] _entries_T_45; // @[TLB.scala:170:77] wire _entries_T_44; // @[TLB.scala:170:77] wire _entries_T_43; // @[TLB.scala:170:77] wire _entries_T_42; // @[TLB.scala:170:77] wire _entries_T_41; // @[TLB.scala:170:77] wire _entries_T_40; // @[TLB.scala:170:77] wire _entries_T_39; // @[TLB.scala:170:77] wire _entries_T_38; // @[TLB.scala:170:77] wire _entries_T_37; // @[TLB.scala:170:77] wire _entries_T_36; // @[TLB.scala:170:77] wire _entries_T_35; // @[TLB.scala:170:77] wire _entries_T_34; // @[TLB.scala:170:77] wire _entries_T_33; // @[TLB.scala:170:77] wire _entries_T_32; // @[TLB.scala:170:77] wire _entries_T_31; // @[TLB.scala:170:77] wire _entries_T_30; // @[TLB.scala:170:77] wire _entries_T_29; // @[TLB.scala:170:77] wire _entries_T_28; // @[TLB.scala:170:77] wire _entries_T_27; // @[TLB.scala:170:77] wire _entries_T_26; // @[TLB.scala:170:77] wire _entries_T_25; // @[TLB.scala:170:77] wire _entries_T_24; // @[TLB.scala:170:77] wire _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_23 = _entries_WIRE_3[0]; // @[TLB.scala:170:77] wire _entries_WIRE_2_fragmented_superpage = _entries_T_23; // @[TLB.scala:170:77] assign _entries_T_24 = _entries_WIRE_3[1]; // @[TLB.scala:170:77] wire _entries_WIRE_2_c = _entries_T_24; // @[TLB.scala:170:77] assign _entries_T_25 = _entries_WIRE_3[2]; // @[TLB.scala:170:77] wire _entries_WIRE_2_eff = _entries_T_25; // @[TLB.scala:170:77] assign _entries_T_26 = _entries_WIRE_3[3]; // @[TLB.scala:170:77] wire _entries_WIRE_2_paa = _entries_T_26; // @[TLB.scala:170:77] assign _entries_T_27 = _entries_WIRE_3[4]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pal = _entries_T_27; // @[TLB.scala:170:77] assign _entries_T_28 = _entries_WIRE_3[5]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ppp = _entries_T_28; // @[TLB.scala:170:77] assign _entries_T_29 = _entries_WIRE_3[6]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pr = _entries_T_29; // @[TLB.scala:170:77] assign _entries_T_30 = _entries_WIRE_3[7]; // @[TLB.scala:170:77] wire _entries_WIRE_2_px = _entries_T_30; // @[TLB.scala:170:77] assign _entries_T_31 = _entries_WIRE_3[8]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pw = _entries_T_31; // @[TLB.scala:170:77] assign _entries_T_32 = _entries_WIRE_3[9]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hr = _entries_T_32; // @[TLB.scala:170:77] assign _entries_T_33 = _entries_WIRE_3[10]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hx = _entries_T_33; // @[TLB.scala:170:77] assign _entries_T_34 = _entries_WIRE_3[11]; // @[TLB.scala:170:77] wire _entries_WIRE_2_hw = _entries_T_34; // @[TLB.scala:170:77] assign _entries_T_35 = _entries_WIRE_3[12]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sr = _entries_T_35; // @[TLB.scala:170:77] assign _entries_T_36 = _entries_WIRE_3[13]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sx = _entries_T_36; // @[TLB.scala:170:77] assign _entries_T_37 = _entries_WIRE_3[14]; // @[TLB.scala:170:77] wire _entries_WIRE_2_sw = _entries_T_37; // @[TLB.scala:170:77] assign _entries_T_38 = _entries_WIRE_3[15]; // @[TLB.scala:170:77] wire _entries_WIRE_2_gf = _entries_T_38; // @[TLB.scala:170:77] assign _entries_T_39 = _entries_WIRE_3[16]; // @[TLB.scala:170:77] wire _entries_WIRE_2_pf = _entries_T_39; // @[TLB.scala:170:77] assign _entries_T_40 = _entries_WIRE_3[17]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_stage2 = _entries_T_40; // @[TLB.scala:170:77] assign _entries_T_41 = _entries_WIRE_3[18]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_final = _entries_T_41; // @[TLB.scala:170:77] assign _entries_T_42 = _entries_WIRE_3[19]; // @[TLB.scala:170:77] wire _entries_WIRE_2_ae_ptw = _entries_T_42; // @[TLB.scala:170:77] assign _entries_T_43 = _entries_WIRE_3[20]; // @[TLB.scala:170:77] wire _entries_WIRE_2_g = _entries_T_43; // @[TLB.scala:170:77] assign _entries_T_44 = _entries_WIRE_3[21]; // @[TLB.scala:170:77] wire _entries_WIRE_2_u = _entries_T_44; // @[TLB.scala:170:77] assign _entries_T_45 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_2_ppn = _entries_T_45; // @[TLB.scala:170:77] wire [19:0] _entries_T_68; // @[TLB.scala:170:77] wire _entries_T_67; // @[TLB.scala:170:77] wire _entries_T_66; // @[TLB.scala:170:77] wire _entries_T_65; // @[TLB.scala:170:77] wire _entries_T_64; // @[TLB.scala:170:77] wire _entries_T_63; // @[TLB.scala:170:77] wire _entries_T_62; // @[TLB.scala:170:77] wire _entries_T_61; // @[TLB.scala:170:77] wire _entries_T_60; // @[TLB.scala:170:77] wire _entries_T_59; // @[TLB.scala:170:77] wire _entries_T_58; // @[TLB.scala:170:77] wire _entries_T_57; // @[TLB.scala:170:77] wire _entries_T_56; // @[TLB.scala:170:77] wire _entries_T_55; // @[TLB.scala:170:77] wire _entries_T_54; // @[TLB.scala:170:77] wire _entries_T_53; // @[TLB.scala:170:77] wire _entries_T_52; // @[TLB.scala:170:77] wire _entries_T_51; // @[TLB.scala:170:77] wire _entries_T_50; // @[TLB.scala:170:77] wire _entries_T_49; // @[TLB.scala:170:77] wire _entries_T_48; // @[TLB.scala:170:77] wire _entries_T_47; // @[TLB.scala:170:77] wire _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_46 = _entries_WIRE_5[0]; // @[TLB.scala:170:77] wire _entries_WIRE_4_fragmented_superpage = _entries_T_46; // @[TLB.scala:170:77] assign _entries_T_47 = _entries_WIRE_5[1]; // @[TLB.scala:170:77] wire _entries_WIRE_4_c = _entries_T_47; // @[TLB.scala:170:77] assign _entries_T_48 = _entries_WIRE_5[2]; // @[TLB.scala:170:77] wire _entries_WIRE_4_eff = _entries_T_48; // @[TLB.scala:170:77] assign _entries_T_49 = _entries_WIRE_5[3]; // @[TLB.scala:170:77] wire _entries_WIRE_4_paa = _entries_T_49; // @[TLB.scala:170:77] assign _entries_T_50 = _entries_WIRE_5[4]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pal = _entries_T_50; // @[TLB.scala:170:77] assign _entries_T_51 = _entries_WIRE_5[5]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ppp = _entries_T_51; // @[TLB.scala:170:77] assign _entries_T_52 = _entries_WIRE_5[6]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pr = _entries_T_52; // @[TLB.scala:170:77] assign _entries_T_53 = _entries_WIRE_5[7]; // @[TLB.scala:170:77] wire _entries_WIRE_4_px = _entries_T_53; // @[TLB.scala:170:77] assign _entries_T_54 = _entries_WIRE_5[8]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pw = _entries_T_54; // @[TLB.scala:170:77] assign _entries_T_55 = _entries_WIRE_5[9]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hr = _entries_T_55; // @[TLB.scala:170:77] assign _entries_T_56 = _entries_WIRE_5[10]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hx = _entries_T_56; // @[TLB.scala:170:77] assign _entries_T_57 = _entries_WIRE_5[11]; // @[TLB.scala:170:77] wire _entries_WIRE_4_hw = _entries_T_57; // @[TLB.scala:170:77] assign _entries_T_58 = _entries_WIRE_5[12]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sr = _entries_T_58; // @[TLB.scala:170:77] assign _entries_T_59 = _entries_WIRE_5[13]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sx = _entries_T_59; // @[TLB.scala:170:77] assign _entries_T_60 = _entries_WIRE_5[14]; // @[TLB.scala:170:77] wire _entries_WIRE_4_sw = _entries_T_60; // @[TLB.scala:170:77] assign _entries_T_61 = _entries_WIRE_5[15]; // @[TLB.scala:170:77] wire _entries_WIRE_4_gf = _entries_T_61; // @[TLB.scala:170:77] assign _entries_T_62 = _entries_WIRE_5[16]; // @[TLB.scala:170:77] wire _entries_WIRE_4_pf = _entries_T_62; // @[TLB.scala:170:77] assign _entries_T_63 = _entries_WIRE_5[17]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_stage2 = _entries_T_63; // @[TLB.scala:170:77] assign _entries_T_64 = _entries_WIRE_5[18]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_final = _entries_T_64; // @[TLB.scala:170:77] assign _entries_T_65 = _entries_WIRE_5[19]; // @[TLB.scala:170:77] wire _entries_WIRE_4_ae_ptw = _entries_T_65; // @[TLB.scala:170:77] assign _entries_T_66 = _entries_WIRE_5[20]; // @[TLB.scala:170:77] wire _entries_WIRE_4_g = _entries_T_66; // @[TLB.scala:170:77] assign _entries_T_67 = _entries_WIRE_5[21]; // @[TLB.scala:170:77] wire _entries_WIRE_4_u = _entries_T_67; // @[TLB.scala:170:77] assign _entries_T_68 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_4_ppn = _entries_T_68; // @[TLB.scala:170:77] wire [19:0] _entries_T_91; // @[TLB.scala:170:77] wire _entries_T_90; // @[TLB.scala:170:77] wire _entries_T_89; // @[TLB.scala:170:77] wire _entries_T_88; // @[TLB.scala:170:77] wire _entries_T_87; // @[TLB.scala:170:77] wire _entries_T_86; // @[TLB.scala:170:77] wire _entries_T_85; // @[TLB.scala:170:77] wire _entries_T_84; // @[TLB.scala:170:77] wire _entries_T_83; // @[TLB.scala:170:77] wire _entries_T_82; // @[TLB.scala:170:77] wire _entries_T_81; // @[TLB.scala:170:77] wire _entries_T_80; // @[TLB.scala:170:77] wire _entries_T_79; // @[TLB.scala:170:77] wire _entries_T_78; // @[TLB.scala:170:77] wire _entries_T_77; // @[TLB.scala:170:77] wire _entries_T_76; // @[TLB.scala:170:77] wire _entries_T_75; // @[TLB.scala:170:77] wire _entries_T_74; // @[TLB.scala:170:77] wire _entries_T_73; // @[TLB.scala:170:77] wire _entries_T_72; // @[TLB.scala:170:77] wire _entries_T_71; // @[TLB.scala:170:77] wire _entries_T_70; // @[TLB.scala:170:77] wire _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_69 = _entries_WIRE_7[0]; // @[TLB.scala:170:77] wire _entries_WIRE_6_fragmented_superpage = _entries_T_69; // @[TLB.scala:170:77] assign _entries_T_70 = _entries_WIRE_7[1]; // @[TLB.scala:170:77] wire _entries_WIRE_6_c = _entries_T_70; // @[TLB.scala:170:77] assign _entries_T_71 = _entries_WIRE_7[2]; // @[TLB.scala:170:77] wire _entries_WIRE_6_eff = _entries_T_71; // @[TLB.scala:170:77] assign _entries_T_72 = _entries_WIRE_7[3]; // @[TLB.scala:170:77] wire _entries_WIRE_6_paa = _entries_T_72; // @[TLB.scala:170:77] assign _entries_T_73 = _entries_WIRE_7[4]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pal = _entries_T_73; // @[TLB.scala:170:77] assign _entries_T_74 = _entries_WIRE_7[5]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ppp = _entries_T_74; // @[TLB.scala:170:77] assign _entries_T_75 = _entries_WIRE_7[6]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pr = _entries_T_75; // @[TLB.scala:170:77] assign _entries_T_76 = _entries_WIRE_7[7]; // @[TLB.scala:170:77] wire _entries_WIRE_6_px = _entries_T_76; // @[TLB.scala:170:77] assign _entries_T_77 = _entries_WIRE_7[8]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pw = _entries_T_77; // @[TLB.scala:170:77] assign _entries_T_78 = _entries_WIRE_7[9]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hr = _entries_T_78; // @[TLB.scala:170:77] assign _entries_T_79 = _entries_WIRE_7[10]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hx = _entries_T_79; // @[TLB.scala:170:77] assign _entries_T_80 = _entries_WIRE_7[11]; // @[TLB.scala:170:77] wire _entries_WIRE_6_hw = _entries_T_80; // @[TLB.scala:170:77] assign _entries_T_81 = _entries_WIRE_7[12]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sr = _entries_T_81; // @[TLB.scala:170:77] assign _entries_T_82 = _entries_WIRE_7[13]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sx = _entries_T_82; // @[TLB.scala:170:77] assign _entries_T_83 = _entries_WIRE_7[14]; // @[TLB.scala:170:77] wire _entries_WIRE_6_sw = _entries_T_83; // @[TLB.scala:170:77] assign _entries_T_84 = _entries_WIRE_7[15]; // @[TLB.scala:170:77] wire _entries_WIRE_6_gf = _entries_T_84; // @[TLB.scala:170:77] assign _entries_T_85 = _entries_WIRE_7[16]; // @[TLB.scala:170:77] wire _entries_WIRE_6_pf = _entries_T_85; // @[TLB.scala:170:77] assign _entries_T_86 = _entries_WIRE_7[17]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_stage2 = _entries_T_86; // @[TLB.scala:170:77] assign _entries_T_87 = _entries_WIRE_7[18]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_final = _entries_T_87; // @[TLB.scala:170:77] assign _entries_T_88 = _entries_WIRE_7[19]; // @[TLB.scala:170:77] wire _entries_WIRE_6_ae_ptw = _entries_T_88; // @[TLB.scala:170:77] assign _entries_T_89 = _entries_WIRE_7[20]; // @[TLB.scala:170:77] wire _entries_WIRE_6_g = _entries_T_89; // @[TLB.scala:170:77] assign _entries_T_90 = _entries_WIRE_7[21]; // @[TLB.scala:170:77] wire _entries_WIRE_6_u = _entries_T_90; // @[TLB.scala:170:77] assign _entries_T_91 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_6_ppn = _entries_T_91; // @[TLB.scala:170:77] wire [19:0] _entries_T_114; // @[TLB.scala:170:77] wire _entries_T_113; // @[TLB.scala:170:77] wire _entries_T_112; // @[TLB.scala:170:77] wire _entries_T_111; // @[TLB.scala:170:77] wire _entries_T_110; // @[TLB.scala:170:77] wire _entries_T_109; // @[TLB.scala:170:77] wire _entries_T_108; // @[TLB.scala:170:77] wire _entries_T_107; // @[TLB.scala:170:77] wire _entries_T_106; // @[TLB.scala:170:77] wire _entries_T_105; // @[TLB.scala:170:77] wire _entries_T_104; // @[TLB.scala:170:77] wire _entries_T_103; // @[TLB.scala:170:77] wire _entries_T_102; // @[TLB.scala:170:77] wire _entries_T_101; // @[TLB.scala:170:77] wire _entries_T_100; // @[TLB.scala:170:77] wire _entries_T_99; // @[TLB.scala:170:77] wire _entries_T_98; // @[TLB.scala:170:77] wire _entries_T_97; // @[TLB.scala:170:77] wire _entries_T_96; // @[TLB.scala:170:77] wire _entries_T_95; // @[TLB.scala:170:77] wire _entries_T_94; // @[TLB.scala:170:77] wire _entries_T_93; // @[TLB.scala:170:77] wire _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_92 = _entries_WIRE_9[0]; // @[TLB.scala:170:77] wire _entries_WIRE_8_fragmented_superpage = _entries_T_92; // @[TLB.scala:170:77] assign _entries_T_93 = _entries_WIRE_9[1]; // @[TLB.scala:170:77] wire _entries_WIRE_8_c = _entries_T_93; // @[TLB.scala:170:77] assign _entries_T_94 = _entries_WIRE_9[2]; // @[TLB.scala:170:77] wire _entries_WIRE_8_eff = _entries_T_94; // @[TLB.scala:170:77] assign _entries_T_95 = _entries_WIRE_9[3]; // @[TLB.scala:170:77] wire _entries_WIRE_8_paa = _entries_T_95; // @[TLB.scala:170:77] assign _entries_T_96 = _entries_WIRE_9[4]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pal = _entries_T_96; // @[TLB.scala:170:77] assign _entries_T_97 = _entries_WIRE_9[5]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ppp = _entries_T_97; // @[TLB.scala:170:77] assign _entries_T_98 = _entries_WIRE_9[6]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pr = _entries_T_98; // @[TLB.scala:170:77] assign _entries_T_99 = _entries_WIRE_9[7]; // @[TLB.scala:170:77] wire _entries_WIRE_8_px = _entries_T_99; // @[TLB.scala:170:77] assign _entries_T_100 = _entries_WIRE_9[8]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pw = _entries_T_100; // @[TLB.scala:170:77] assign _entries_T_101 = _entries_WIRE_9[9]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hr = _entries_T_101; // @[TLB.scala:170:77] assign _entries_T_102 = _entries_WIRE_9[10]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hx = _entries_T_102; // @[TLB.scala:170:77] assign _entries_T_103 = _entries_WIRE_9[11]; // @[TLB.scala:170:77] wire _entries_WIRE_8_hw = _entries_T_103; // @[TLB.scala:170:77] assign _entries_T_104 = _entries_WIRE_9[12]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sr = _entries_T_104; // @[TLB.scala:170:77] assign _entries_T_105 = _entries_WIRE_9[13]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sx = _entries_T_105; // @[TLB.scala:170:77] assign _entries_T_106 = _entries_WIRE_9[14]; // @[TLB.scala:170:77] wire _entries_WIRE_8_sw = _entries_T_106; // @[TLB.scala:170:77] assign _entries_T_107 = _entries_WIRE_9[15]; // @[TLB.scala:170:77] wire _entries_WIRE_8_gf = _entries_T_107; // @[TLB.scala:170:77] assign _entries_T_108 = _entries_WIRE_9[16]; // @[TLB.scala:170:77] wire _entries_WIRE_8_pf = _entries_T_108; // @[TLB.scala:170:77] assign _entries_T_109 = _entries_WIRE_9[17]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_stage2 = _entries_T_109; // @[TLB.scala:170:77] assign _entries_T_110 = _entries_WIRE_9[18]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_final = _entries_T_110; // @[TLB.scala:170:77] assign _entries_T_111 = _entries_WIRE_9[19]; // @[TLB.scala:170:77] wire _entries_WIRE_8_ae_ptw = _entries_T_111; // @[TLB.scala:170:77] assign _entries_T_112 = _entries_WIRE_9[20]; // @[TLB.scala:170:77] wire _entries_WIRE_8_g = _entries_T_112; // @[TLB.scala:170:77] assign _entries_T_113 = _entries_WIRE_9[21]; // @[TLB.scala:170:77] wire _entries_WIRE_8_u = _entries_T_113; // @[TLB.scala:170:77] assign _entries_T_114 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_8_ppn = _entries_T_114; // @[TLB.scala:170:77] wire [19:0] _entries_T_137; // @[TLB.scala:170:77] wire _entries_T_136; // @[TLB.scala:170:77] wire _entries_T_135; // @[TLB.scala:170:77] wire _entries_T_134; // @[TLB.scala:170:77] wire _entries_T_133; // @[TLB.scala:170:77] wire _entries_T_132; // @[TLB.scala:170:77] wire _entries_T_131; // @[TLB.scala:170:77] wire _entries_T_130; // @[TLB.scala:170:77] wire _entries_T_129; // @[TLB.scala:170:77] wire _entries_T_128; // @[TLB.scala:170:77] wire _entries_T_127; // @[TLB.scala:170:77] wire _entries_T_126; // @[TLB.scala:170:77] wire _entries_T_125; // @[TLB.scala:170:77] wire _entries_T_124; // @[TLB.scala:170:77] wire _entries_T_123; // @[TLB.scala:170:77] wire _entries_T_122; // @[TLB.scala:170:77] wire _entries_T_121; // @[TLB.scala:170:77] wire _entries_T_120; // @[TLB.scala:170:77] wire _entries_T_119; // @[TLB.scala:170:77] wire _entries_T_118; // @[TLB.scala:170:77] wire _entries_T_117; // @[TLB.scala:170:77] wire _entries_T_116; // @[TLB.scala:170:77] wire _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_115 = _entries_WIRE_11[0]; // @[TLB.scala:170:77] wire _entries_WIRE_10_fragmented_superpage = _entries_T_115; // @[TLB.scala:170:77] assign _entries_T_116 = _entries_WIRE_11[1]; // @[TLB.scala:170:77] wire _entries_WIRE_10_c = _entries_T_116; // @[TLB.scala:170:77] assign _entries_T_117 = _entries_WIRE_11[2]; // @[TLB.scala:170:77] wire _entries_WIRE_10_eff = _entries_T_117; // @[TLB.scala:170:77] assign _entries_T_118 = _entries_WIRE_11[3]; // @[TLB.scala:170:77] wire _entries_WIRE_10_paa = _entries_T_118; // @[TLB.scala:170:77] assign _entries_T_119 = _entries_WIRE_11[4]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pal = _entries_T_119; // @[TLB.scala:170:77] assign _entries_T_120 = _entries_WIRE_11[5]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ppp = _entries_T_120; // @[TLB.scala:170:77] assign _entries_T_121 = _entries_WIRE_11[6]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pr = _entries_T_121; // @[TLB.scala:170:77] assign _entries_T_122 = _entries_WIRE_11[7]; // @[TLB.scala:170:77] wire _entries_WIRE_10_px = _entries_T_122; // @[TLB.scala:170:77] assign _entries_T_123 = _entries_WIRE_11[8]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pw = _entries_T_123; // @[TLB.scala:170:77] assign _entries_T_124 = _entries_WIRE_11[9]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hr = _entries_T_124; // @[TLB.scala:170:77] assign _entries_T_125 = _entries_WIRE_11[10]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hx = _entries_T_125; // @[TLB.scala:170:77] assign _entries_T_126 = _entries_WIRE_11[11]; // @[TLB.scala:170:77] wire _entries_WIRE_10_hw = _entries_T_126; // @[TLB.scala:170:77] assign _entries_T_127 = _entries_WIRE_11[12]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sr = _entries_T_127; // @[TLB.scala:170:77] assign _entries_T_128 = _entries_WIRE_11[13]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sx = _entries_T_128; // @[TLB.scala:170:77] assign _entries_T_129 = _entries_WIRE_11[14]; // @[TLB.scala:170:77] wire _entries_WIRE_10_sw = _entries_T_129; // @[TLB.scala:170:77] assign _entries_T_130 = _entries_WIRE_11[15]; // @[TLB.scala:170:77] wire _entries_WIRE_10_gf = _entries_T_130; // @[TLB.scala:170:77] assign _entries_T_131 = _entries_WIRE_11[16]; // @[TLB.scala:170:77] wire _entries_WIRE_10_pf = _entries_T_131; // @[TLB.scala:170:77] assign _entries_T_132 = _entries_WIRE_11[17]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_stage2 = _entries_T_132; // @[TLB.scala:170:77] assign _entries_T_133 = _entries_WIRE_11[18]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_final = _entries_T_133; // @[TLB.scala:170:77] assign _entries_T_134 = _entries_WIRE_11[19]; // @[TLB.scala:170:77] wire _entries_WIRE_10_ae_ptw = _entries_T_134; // @[TLB.scala:170:77] assign _entries_T_135 = _entries_WIRE_11[20]; // @[TLB.scala:170:77] wire _entries_WIRE_10_g = _entries_T_135; // @[TLB.scala:170:77] assign _entries_T_136 = _entries_WIRE_11[21]; // @[TLB.scala:170:77] wire _entries_WIRE_10_u = _entries_T_136; // @[TLB.scala:170:77] assign _entries_T_137 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] _entries_WIRE_10_ppn = _entries_T_137; // @[TLB.scala:170:77] wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30] wire [1:0] ppn_res = _entries_barrier_4_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30] wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] \| _entries_barrier_4_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] ppn_res_1 = _entries_barrier_5_io_y_ppn[19:18]; // @[package.scala:267:25] wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire _ppn_ignore_T_3 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56] wire ppn_ignore_3 = _ppn_ignore_T_3; // @[TLB.scala:197:{28,34}] wire [26:0] _ppn_T_13 = ppn_ignore_3 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] \| _entries_barrier_5_io_y_ppn}; // @[package.scala:267:25] wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [19:0] _ppn_T_17 = vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] _ppn_T_18 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_19 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_20 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_21 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_22 = hitsVec_4 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_23 = hitsVec_5 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_24 = _ppn_T ? _ppn_T_17 : 20'h0; // @[Mux.scala:30:73] wire [19:0] _ppn_T_25 = _ppn_T_18 \| _ppn_T_19; // @[Mux.scala:30:73] wire [19:0] _ppn_T_26 = _ppn_T_25 \| _ppn_T_20; // @[Mux.scala:30:73] wire [19:0] _ppn_T_27 = _ppn_T_26 \| _ppn_T_21; // @[Mux.scala:30:73] wire [19:0] _ppn_T_28 = _ppn_T_27 \| _ppn_T_22; // @[Mux.scala:30:73] wire [19:0] _ppn_T_29 = _ppn_T_28 \| _ppn_T_23; // @[Mux.scala:30:73] wire [19:0] _ppn_T_30 = _ppn_T_29 \| _ppn_T_24; // @[Mux.scala:30:73] wire [19:0] ppn = _ppn_T_30; // @[Mux.scala:30:73] wire [1:0] ptw_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] final_ae_array_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_lo = {final_ae_array_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] final_ae_array_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] final_ae_array_hi = {final_ae_array_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27] wire [6:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27] wire [1:0] ptw_pf_array_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_pf_array_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] ptw_gf_array_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] ptw_gf_array_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27] wire [6:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27] wire [6:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [6:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [6:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire [1:0] _GEN_33 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_lo_hi; // @[package.scala:45:27] assign priv_rw_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_rw_ok_lo_hi_1; // @[package.scala:45:27] assign priv_rw_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi; // @[package.scala:45:27] assign priv_x_ok_lo_hi = _GEN_33; // @[package.scala:45:27] wire [1:0] priv_x_ok_lo_hi_1; // @[package.scala:45:27] assign priv_x_ok_lo_hi_1 = _GEN_33; // @[package.scala:45:27] wire [2:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_34 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] priv_rw_ok_hi_hi; // @[package.scala:45:27] assign priv_rw_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_rw_ok_hi_hi_1; // @[package.scala:45:27] assign priv_rw_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi; // @[package.scala:45:27] assign priv_x_ok_hi_hi = _GEN_34; // @[package.scala:45:27] wire [1:0] priv_x_ok_hi_hi_1; // @[package.scala:45:27] assign priv_x_ok_hi_hi_1 = _GEN_34; // @[package.scala:45:27] wire [2:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27] wire [5:0] priv_rw_ok = _priv_rw_ok_T_3; // @[TLB.scala:513:{23,70}] wire [2:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [5:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo = {priv_x_ok_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi = {priv_x_ok_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27] wire [5:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27] wire [2:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27] wire [5:0] priv_x_ok = _priv_x_ok_T_2; // @[package.scala:45:27] wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83] wire [5:0] _stage1_bypass_T_2 = {6{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}] wire [1:0] stage1_bypass_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_lo = {stage1_bypass_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] stage1_bypass_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] stage1_bypass_hi = {stage1_bypass_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27] wire [5:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 \| _stage1_bypass_T_3; // @[package.scala:45:27] wire [1:0] r_array_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_lo = {r_array_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] r_array_hi = {r_array_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_35 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_lo_hi_1; // @[package.scala:45:27] assign r_array_lo_hi_1 = _GEN_35; // @[package.scala:45:27] wire [1:0] x_array_lo_hi; // @[package.scala:45:27] assign x_array_lo_hi = _GEN_35; // @[package.scala:45:27] wire [2:0] r_array_lo_1 = {r_array_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_36 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] r_array_hi_hi_1; // @[package.scala:45:27] assign r_array_hi_hi_1 = _GEN_36; // @[package.scala:45:27] wire [1:0] x_array_hi_hi; // @[package.scala:45:27] assign x_array_hi_hi = _GEN_36; // @[package.scala:45:27] wire [2:0] r_array_hi_1 = {r_array_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27] wire [5:0] _r_array_T_2 = mxr ? _r_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _r_array_T_3 = _r_array_T \| _r_array_T_2; // @[package.scala:45:27] wire [5:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [5:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}] wire [6:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [6:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] w_array_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_lo = {w_array_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] w_array_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] w_array_hi = {w_array_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27] wire [5:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27] wire [5:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}] wire [6:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] x_array_lo = {x_array_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] x_array_hi = {x_array_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27] wire [5:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27] wire [5:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}] wire [6:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] hr_array_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_lo = {hr_array_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] hr_array_hi = {hr_array_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27] wire [1:0] _GEN_37 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_lo_hi_1; // @[package.scala:45:27] assign hr_array_lo_hi_1 = _GEN_37; // @[package.scala:45:27] wire [1:0] hx_array_lo_hi; // @[package.scala:45:27] assign hx_array_lo_hi = _GEN_37; // @[package.scala:45:27] wire [2:0] hr_array_lo_1 = {hr_array_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_38 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] hr_array_hi_hi_1; // @[package.scala:45:27] assign hr_array_hi_hi_1 = _GEN_38; // @[package.scala:45:27] wire [1:0] hx_array_hi_hi; // @[package.scala:45:27] assign hx_array_hi_hi = _GEN_38; // @[package.scala:45:27] wire [2:0] hr_array_hi_1 = {hr_array_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27] wire [5:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 6'h0; // @[package.scala:45:27] wire [5:0] _hr_array_T_3 = _hr_array_T \| _hr_array_T_2; // @[package.scala:45:27] wire [1:0] hw_array_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_lo = {hw_array_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] hw_array_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] hw_array_hi = {hw_array_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27] wire [2:0] hx_array_lo = {hx_array_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] hx_array_hi = {hx_array_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27] wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26] wire [1:0] pr_array_lo = {_entries_barrier_1_io_y_pr, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pr_array_hi_hi = {_entries_barrier_4_io_y_pr, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pr_array_hi = {pr_array_hi_hi, _entries_barrier_2_io_y_pr}; // @[package.scala:45:27, :267:25] wire [4:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27] wire [6:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27] wire [6:0] _GEN_39 = ptw_ae_array \| final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [6:0] _pr_array_T_3; // @[TLB.scala:529:104] assign _pr_array_T_3 = _GEN_39; // @[TLB.scala:529:104] wire [6:0] _pw_array_T_3; // @[TLB.scala:531:104] assign _pw_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :531:104] wire [6:0] _px_array_T_3; // @[TLB.scala:533:104] assign _px_array_T_3 = _GEN_39; // @[TLB.scala:529:104, :533:104] wire [6:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [6:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26] wire [1:0] pw_array_lo = {_entries_barrier_1_io_y_pw, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pw_array_hi_hi = {_entries_barrier_4_io_y_pw, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pw_array_hi = {pw_array_hi_hi, _entries_barrier_2_io_y_pw}; // @[package.scala:45:27, :267:25] wire [4:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27] wire [6:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27] wire [6:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [6:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26] wire [1:0] px_array_lo = {_entries_barrier_1_io_y_px, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] px_array_hi_hi = {_entries_barrier_4_io_y_px, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] px_array_hi = {px_array_hi_hi, _entries_barrier_2_io_y_px}; // @[package.scala:45:27, :267:25] wire [4:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27] wire [6:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27] wire [6:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}] wire [6:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] eff_array_lo = {_entries_barrier_1_io_y_eff, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] eff_array_hi_hi = {_entries_barrier_4_io_y_eff, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] eff_array_hi = {eff_array_hi_hi, _entries_barrier_2_io_y_eff}; // @[package.scala:45:27, :267:25] wire [4:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27] wire [6:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27] wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_40 = {_entries_barrier_1_io_y_c, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_lo; // @[package.scala:45:27] assign c_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] prefetchable_array_lo; // @[package.scala:45:27] assign prefetchable_array_lo = _GEN_40; // @[package.scala:45:27] wire [1:0] _GEN_41 = {_entries_barrier_4_io_y_c, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] c_array_hi_hi; // @[package.scala:45:27] assign c_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [1:0] prefetchable_array_hi_hi; // @[package.scala:45:27] assign prefetchable_array_hi_hi = _GEN_41; // @[package.scala:45:27] wire [2:0] c_array_hi = {c_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27] wire [6:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27] wire [6:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] ppp_array_lo = {_entries_barrier_1_io_y_ppp, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] ppp_array_hi_hi = {_entries_barrier_4_io_y_ppp, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] ppp_array_hi = {ppp_array_hi_hi, _entries_barrier_2_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [4:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27] wire [6:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] paa_array_lo = {_entries_barrier_1_io_y_paa, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] paa_array_hi_hi = {_entries_barrier_4_io_y_paa, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] paa_array_hi = {paa_array_hi_hi, _entries_barrier_2_io_y_paa}; // @[package.scala:45:27, :267:25] wire [4:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27] wire [6:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27] wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pal_array_lo = {_entries_barrier_1_io_y_pal, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pal_array_hi_hi = {_entries_barrier_4_io_y_pal, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pal_array_hi = {pal_array_hi_hi, _entries_barrier_2_io_y_pal}; // @[package.scala:45:27, :267:25] wire [4:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27] wire [6:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27] wire [6:0] ppp_array_if_cached = ppp_array \| c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [6:0] paa_array_if_cached = paa_array \| c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [6:0] pal_array_if_cached = pal_array \| c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] prefetchable_array_hi = {prefetchable_array_hi_hi, _entries_barrier_2_io_y_c}; // @[package.scala:45:27, :267:25] wire [4:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27] wire [6:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size_0; // @[OneHot.scala:58:35] wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] _misaligned_T_3 = {36'h0, io_req_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[TLB.scala:318:7, :550:{39,69}] wire misaligned = \|_misaligned_T_3; // @[TLB.scala:550:{39,77}] wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21] wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43] wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:550:77, :559:43, :560:51] wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}] wire _bad_va_T_5 = _bad_va_T_2 \| _bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}] wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}] wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}] wire _GEN_42 = io_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _cmd_lrsc_T; // @[package.scala:16:47] assign _cmd_lrsc_T = _GEN_42; // @[package.scala:16:47] wire _cmd_read_T_2; // @[package.scala:16:47] assign _cmd_read_T_2 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = io_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _cmd_lrsc_T_1; // @[package.scala:16:47] assign _cmd_lrsc_T_1 = _GEN_43; // @[package.scala:16:47] wire _cmd_read_T_3; // @[package.scala:16:47] assign _cmd_read_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_write_T_3; // @[Consts.scala:90:66] assign _cmd_write_T_3 = _GEN_43; // @[package.scala:16:47] wire _cmd_lrsc_T_2 = _cmd_lrsc_T \| _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire cmd_lrsc = _cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_44 = io_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _cmd_amo_logical_T; // @[package.scala:16:47] assign _cmd_amo_logical_T = _GEN_44; // @[package.scala:16:47] wire _cmd_read_T_7; // @[package.scala:16:47] assign _cmd_read_T_7 = _GEN_44; // @[package.scala:16:47] wire _cmd_write_T_5; // @[package.scala:16:47] assign _cmd_write_T_5 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = io_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _cmd_amo_logical_T_1; // @[package.scala:16:47] assign _cmd_amo_logical_T_1 = _GEN_45; // @[package.scala:16:47] wire _cmd_read_T_8; // @[package.scala:16:47] assign _cmd_read_T_8 = _GEN_45; // @[package.scala:16:47] wire _cmd_write_T_6; // @[package.scala:16:47] assign _cmd_write_T_6 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = io_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _cmd_amo_logical_T_2; // @[package.scala:16:47] assign _cmd_amo_logical_T_2 = _GEN_46; // @[package.scala:16:47] wire _cmd_read_T_9; // @[package.scala:16:47] assign _cmd_read_T_9 = _GEN_46; // @[package.scala:16:47] wire _cmd_write_T_7; // @[package.scala:16:47] assign _cmd_write_T_7 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = io_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _cmd_amo_logical_T_3; // @[package.scala:16:47] assign _cmd_amo_logical_T_3 = _GEN_47; // @[package.scala:16:47] wire _cmd_read_T_10; // @[package.scala:16:47] assign _cmd_read_T_10 = _GEN_47; // @[package.scala:16:47] wire _cmd_write_T_8; // @[package.scala:16:47] assign _cmd_write_T_8 = _GEN_47; // @[package.scala:16:47] wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T \| _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 \| _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 \| _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire cmd_amo_logical = _cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_48 = io_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T = _GEN_48; // @[package.scala:16:47] wire _cmd_read_T_14; // @[package.scala:16:47] assign _cmd_read_T_14 = _GEN_48; // @[package.scala:16:47] wire _cmd_write_T_12; // @[package.scala:16:47] assign _cmd_write_T_12 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = io_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_1 = _GEN_49; // @[package.scala:16:47] wire _cmd_read_T_15; // @[package.scala:16:47] assign _cmd_read_T_15 = _GEN_49; // @[package.scala:16:47] wire _cmd_write_T_13; // @[package.scala:16:47] assign _cmd_write_T_13 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = io_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_2 = _GEN_50; // @[package.scala:16:47] wire _cmd_read_T_16; // @[package.scala:16:47] assign _cmd_read_T_16 = _GEN_50; // @[package.scala:16:47] wire _cmd_write_T_14; // @[package.scala:16:47] assign _cmd_write_T_14 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = io_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_3 = _GEN_51; // @[package.scala:16:47] wire _cmd_read_T_17; // @[package.scala:16:47] assign _cmd_read_T_17 = _GEN_51; // @[package.scala:16:47] wire _cmd_write_T_15; // @[package.scala:16:47] assign _cmd_write_T_15 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = io_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign _cmd_amo_arithmetic_T_4 = _GEN_52; // @[package.scala:16:47] wire _cmd_read_T_18; // @[package.scala:16:47] assign _cmd_read_T_18 = _GEN_52; // @[package.scala:16:47] wire _cmd_write_T_16; // @[package.scala:16:47] assign _cmd_write_T_16 = _GEN_52; // @[package.scala:16:47] wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T \| _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 \| _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 \| _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 \| _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire cmd_amo_arithmetic = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_53 = io_req_bits_cmd_0 == 5'h11; // @[TLB.scala:318:7, :573:41] wire cmd_put_partial; // @[TLB.scala:573:41] assign cmd_put_partial = _GEN_53; // @[TLB.scala:573:41] wire _cmd_write_T_1; // @[Consts.scala:90:49] assign _cmd_write_T_1 = _GEN_53; // @[TLB.scala:573:41] wire _cmd_read_T = io_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _GEN_54 = io_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _cmd_read_T_1; // @[package.scala:16:47] assign _cmd_read_T_1 = _GEN_54; // @[package.scala:16:47] wire _cmd_readx_T; // @[TLB.scala:575:56] assign _cmd_readx_T = _GEN_54; // @[package.scala:16:47] wire _cmd_read_T_4 = _cmd_read_T \| _cmd_read_T_1; // @[package.scala:16:47, :81:59] wire _cmd_read_T_5 = _cmd_read_T_4 \| _cmd_read_T_2; // @[package.scala:16:47, :81:59] wire _cmd_read_T_6 = _cmd_read_T_5 \| _cmd_read_T_3; // @[package.scala:16:47, :81:59] wire _cmd_read_T_11 = _cmd_read_T_7 \| _cmd_read_T_8; // @[package.scala:16:47, :81:59] wire _cmd_read_T_12 = _cmd_read_T_11 \| _cmd_read_T_9; // @[package.scala:16:47, :81:59] wire _cmd_read_T_13 = _cmd_read_T_12 \| _cmd_read_T_10; // @[package.scala:16:47, :81:59] wire _cmd_read_T_19 = _cmd_read_T_14 \| _cmd_read_T_15; // @[package.scala:16:47, :81:59] wire _cmd_read_T_20 = _cmd_read_T_19 \| _cmd_read_T_16; // @[package.scala:16:47, :81:59] wire _cmd_read_T_21 = _cmd_read_T_20 \| _cmd_read_T_17; // @[package.scala:16:47, :81:59] wire _cmd_read_T_22 = _cmd_read_T_21 \| _cmd_read_T_18; // @[package.scala:16:47, :81:59] wire _cmd_read_T_23 = _cmd_read_T_13 \| _cmd_read_T_22; // @[package.scala:81:59] wire cmd_read = _cmd_read_T_6 \| _cmd_read_T_23; // @[package.scala:81:59] wire _cmd_write_T = io_req_bits_cmd_0 == 5'h1; // @[TLB.scala:318:7] wire _cmd_write_T_2 = _cmd_write_T \| _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _cmd_write_T_4 = _cmd_write_T_2 \| _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _cmd_write_T_9 = _cmd_write_T_5 \| _cmd_write_T_6; // @[package.scala:16:47, :81:59] wire _cmd_write_T_10 = _cmd_write_T_9 \| _cmd_write_T_7; // @[package.scala:16:47, :81:59] wire _cmd_write_T_11 = _cmd_write_T_10 \| _cmd_write_T_8; // @[package.scala:16:47, :81:59] wire _cmd_write_T_17 = _cmd_write_T_12 \| _cmd_write_T_13; // @[package.scala:16:47, :81:59] wire _cmd_write_T_18 = _cmd_write_T_17 \| _cmd_write_T_14; // @[package.scala:16:47, :81:59] wire _cmd_write_T_19 = _cmd_write_T_18 \| _cmd_write_T_15; // @[package.scala:16:47, :81:59] wire _cmd_write_T_20 = _cmd_write_T_19 \| _cmd_write_T_16; // @[package.scala:16:47, :81:59] wire _cmd_write_T_21 = _cmd_write_T_11 \| _cmd_write_T_20; // @[package.scala:81:59] wire cmd_write = _cmd_write_T_4 \| _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _cmd_write_perms_T = io_req_bits_cmd_0 == 5'h5; // @[package.scala:16:47] wire _cmd_write_perms_T_1 = io_req_bits_cmd_0 == 5'h17; // @[package.scala:16:47] wire _cmd_write_perms_T_2 = _cmd_write_perms_T \| _cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire cmd_write_perms = cmd_write \| _cmd_write_perms_T_2; // @[package.scala:81:59] wire [6:0] _ae_array_T = misaligned ? eff_array : 7'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [6:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [6:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 7'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [6:0] ae_array = _ae_array_T \| _ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46] wire [6:0] _ae_ld_array_T_1 = ae_array \| _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [6:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 7'h0; // @[TLB.scala:586:{24,44}] wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37] wire [6:0] _ae_st_array_T_1 = ae_array \| _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [6:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 7'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [6:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [6:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [6:0] _ae_st_array_T_5 = _ae_st_array_T_2 \| _ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [6:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [6:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_6 : 7'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [6:0] _ae_st_array_T_8 = _ae_st_array_T_5 \| _ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [6:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [6:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_9 : 7'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [6:0] ae_st_array = _ae_st_array_T_8 \| _ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [6:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26] wire [6:0] _must_alloc_array_T_1 = cmd_put_partial ? _must_alloc_array_T : 7'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [6:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26] wire [6:0] _must_alloc_array_T_3 = cmd_amo_logical ? _must_alloc_array_T_2 : 7'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [6:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 \| _must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [6:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29] wire [6:0] _must_alloc_array_T_6 = cmd_amo_arithmetic ? _must_alloc_array_T_5 : 7'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [6:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 \| _must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [6:0] _must_alloc_array_T_9 = {7{cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [6:0] must_alloc_array = _must_alloc_array_T_7 \| _must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [6:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [6:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [6:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [6:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 \| ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [6:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [6:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [6:0] pf_ld_array = cmd_read ? _pf_ld_array_T_6 : 7'h0; // @[TLB.scala:597:{24,104}] wire [6:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44] wire [6:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [6:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [6:0] _pf_st_array_T_3 = _pf_st_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [6:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [6:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [6:0] pf_st_array = cmd_write_perms ? _pf_st_array_T_5 : 7'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [6:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25] wire [6:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [6:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [6:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 \| ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [6:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [6:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [6:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [6:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [6:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [6:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [6:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [6:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73] wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}] wire [4:0] _gpa_hits_hit_mask_T_2 = {5{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}] wire tlb_hit_if_not_gpa_miss = \|real_hits; // @[package.scala:45:27] wire tlb_hit = \|_tlb_hit_T; // @[TLB.scala:611:{28,40}] wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56] wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}] wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67] wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}] reg [2:0] state_vec_0; // @[Replacement.scala:305:17] reg [2:0] state_vec_1; // @[Replacement.scala:305:17] reg [2:0] state_vec_2; // @[Replacement.scala:305:17] reg [2:0] state_vec_3; // @[Replacement.scala:305:17] wire [1:0] _GEN_55 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45] wire [1:0] lo; // @[OneHot.scala:21:45] assign lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_lo; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_lo = _GEN_55; // @[OneHot.scala:21:45] wire [1:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18] wire [1:0] _GEN_56 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45] wire [1:0] hi; // @[OneHot.scala:21:45] assign hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi; // @[OneHot.scala:21:45] assign r_sectored_hit_bits_hi = _GEN_56; // @[OneHot.scala:21:45] wire [1:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18] wire [1:0] state_vec_touch_way_sized = {\|hi_1, hi_1[1] \| lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_vec_set_left_older_T = state_vec_touch_way_sized[1]; // @[package.scala:163:13] wire state_vec_set_left_older = ~_state_vec_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [3:0][2:0] _GEN_57 = {{state_vec_3}, {state_vec_2}, {state_vec_1}, {state_vec_0}}; // @[package.scala:163:13] wire state_vec_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire r_sectored_repl_addr_left_subtree_state = _GEN_57[memIdx][1]; // @[package.scala:163:13] wire state_vec_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire r_sectored_repl_addr_right_subtree_state = _GEN_57[memIdx][0]; // @[package.scala:163:13] wire _state_vec_T = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_4 = state_vec_touch_way_sized[0]; // @[package.scala:163:13] wire _state_vec_T_1 = _state_vec_T; // @[package.scala:163:13] wire _state_vec_T_2 = ~_state_vec_T_1; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_3 = state_vec_set_left_older ? state_vec_left_subtree_state : _state_vec_T_2; // @[package.scala:163:13] wire _state_vec_T_5 = _state_vec_T_4; // @[Replacement.scala:207:62, :218:17] wire _state_vec_T_6 = ~_state_vec_T_5; // @[Replacement.scala:218:{7,17}] wire _state_vec_T_7 = state_vec_set_left_older ? _state_vec_T_6 : state_vec_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_vec_hi = {state_vec_set_left_older, _state_vec_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_vec_T_8 = {state_vec_hi, _state_vec_T_7}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _multipleHits_T = real_hits[2:0]; // @[package.scala:45:27] wire _multipleHits_T_1 = _multipleHits_T[0]; // @[Misc.scala:181:37] wire multipleHits_leftOne = _multipleHits_T_1; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_2 = _multipleHits_T[2:1]; // @[Misc.scala:181:37, :182:39] wire _multipleHits_T_3 = _multipleHits_T_2[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_1 = _multipleHits_T_3; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_4 = _multipleHits_T_2[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne = _multipleHits_T_4; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_1 = multipleHits_leftOne_1 \| multipleHits_rightOne; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_6 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo = _multipleHits_T_6; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_7 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}] wire multipleHits_leftOne_2 = multipleHits_leftOne \| multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_8 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_leftTwo = _multipleHits_T_7 \| _multipleHits_T_8; // @[Misc.scala:183:{37,49,61}] wire [2:0] _multipleHits_T_9 = real_hits[5:3]; // @[package.scala:45:27] wire _multipleHits_T_10 = _multipleHits_T_9[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_3 = _multipleHits_T_10; // @[Misc.scala:178:18, :181:37] wire [1:0] _multipleHits_T_11 = _multipleHits_T_9[2:1]; // @[Misc.scala:182:39] wire _multipleHits_T_12 = _multipleHits_T_11[0]; // @[Misc.scala:181:37, :182:39] wire multipleHits_leftOne_4 = _multipleHits_T_12; // @[Misc.scala:178:18, :181:37] wire _multipleHits_T_13 = _multipleHits_T_11[1]; // @[Misc.scala:182:39] wire multipleHits_rightOne_2 = _multipleHits_T_13; // @[Misc.scala:178:18, :182:39] wire multipleHits_rightOne_3 = multipleHits_leftOne_4 \| multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_15 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61] wire multipleHits_rightTwo_1 = _multipleHits_T_15; // @[Misc.scala:183:{49,61}] wire _multipleHits_T_16 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}] wire multipleHits_rightOne_4 = multipleHits_leftOne_3 \| multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16] wire _multipleHits_T_17 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}] wire multipleHits_rightTwo_2 = _multipleHits_T_16 \| _multipleHits_T_17; // @[Misc.scala:183:{37,49,61}] wire _multipleHits_T_18 = multipleHits_leftOne_2 \| multipleHits_rightOne_4; // @[Misc.scala:183:16] wire _multipleHits_T_19 = multipleHits_leftTwo \| multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}] wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}] wire multipleHits = _multipleHits_T_19 \| _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}] assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25] assign io_req_ready_0 = _io_req_ready_T; // @[TLB.scala:318:7, :631:25] wire _io_resp_pf_ld_T = bad_va & cmd_read; // @[TLB.scala:568:34, :633:28] wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57] wire _io_resp_pf_ld_T_2 = \|_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T \| _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}] assign io_resp_pf_ld = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41] wire _io_resp_pf_st_T = bad_va & cmd_write_perms; // @[TLB.scala:568:34, :577:35, :634:28] wire [6:0] _io_resp_pf_st_T_1 = pf_st_array & hits; // @[TLB.scala:442:17, :598:24, :634:64] wire _io_resp_pf_st_T_2 = \|_io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign _io_resp_pf_st_T_3 = _io_resp_pf_st_T \| _io_resp_pf_st_T_2; // @[TLB.scala:634:{28,48,72}] assign io_resp_pf_st = _io_resp_pf_st_T_3; // @[TLB.scala:318:7, :634:48] wire [6:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47] wire _io_resp_pf_inst_T_1 = \|_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign _io_resp_pf_inst_T_2 = bad_va \| _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}] assign io_resp_pf_inst = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29] wire [6:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33] assign _io_resp_ae_ld_T_1 = \|_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign io_resp_ae_ld = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41] wire [6:0] _io_resp_ae_st_T = ae_st_array & hits; // @[TLB.scala:442:17, :590:53, :642:33] assign _io_resp_ae_st_T_1 = \|_io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign io_resp_ae_st = _io_resp_ae_st_T_1; // @[TLB.scala:318:7, :642:41] wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23] wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}] assign _io_resp_ae_inst_T_2 = \|_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign io_resp_ae_inst = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41] assign _io_resp_ma_ld_T = misaligned & cmd_read; // @[TLB.scala:550:77, :645:31] assign io_resp_ma_ld = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31] assign _io_resp_ma_st_T = misaligned & cmd_write; // @[TLB.scala:550:77, :646:31] assign io_resp_ma_st = _io_resp_ma_st_T; // @[TLB.scala:318:7, :646:31] wire [6:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33] assign _io_resp_cacheable_T_1 = \|_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign io_resp_cacheable = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41] wire [6:0] _io_resp_must_alloc_T = must_alloc_array & hits; // @[TLB.scala:442:17, :595:46, :649:43] assign _io_resp_must_alloc_T_1 = \|_io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign io_resp_must_alloc = _io_resp_must_alloc_T_1; // @[TLB.scala:318:7, :649:51] wire [6:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47] wire _io_resp_prefetchable_T_1 = \|_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign io_resp_prefetchable = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59] wire _io_resp_miss_T_1 = _io_resp_miss_T \| tlb_miss; // @[TLB.scala:613:64, :651:{29,52}] assign _io_resp_miss_T_2 = _io_resp_miss_T_1 \| multipleHits; // @[Misc.scala:183:49] assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64] assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73] assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23] wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58] wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47] wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign io_resp_gpa = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8] assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29] wire _r_superpage_repl_addr_T_1 = ~superpage_entries_0_valid_0; // @[TLB.scala:341:30, :757:43] wire _r_superpage_repl_addr_T_2 = _r_superpage_repl_addr_T_1; // @[OneHot.scala:48:45] wire r_sectored_repl_addr_left_subtree_older = _GEN_57[memIdx][2]; // @[package.scala:163:13] wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state; // @[package.scala:163:13] wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12] wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] r_sectored_repl_addr_valids_lo = {_GEN_11[memIdx], _GEN_7[memIdx]}; // @[package.scala:45:27, :163:13] wire [1:0] r_sectored_repl_addr_valids_hi = {_GEN_19[memIdx], _GEN_15[memIdx]}; // @[package.scala:45:27, :163:13] wire [3:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_4 = &r_sectored_repl_addr_valids; // @[package.scala:45:27] wire [3:0] _r_sectored_repl_addr_T_5 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27] wire _r_sectored_repl_addr_T_6 = _r_sectored_repl_addr_T_5[0]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_7 = _r_sectored_repl_addr_T_5[1]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_8 = _r_sectored_repl_addr_T_5[2]; // @[OneHot.scala:48:45] wire _r_sectored_repl_addr_T_9 = _r_sectored_repl_addr_T_5[3]; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_10 = {1'h1, ~_r_sectored_repl_addr_T_8}; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_11 = _r_sectored_repl_addr_T_7 ? 2'h1 : _r_sectored_repl_addr_T_10; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_6 ? 2'h0 : _r_sectored_repl_addr_T_11; // @[OneHot.scala:48:45] wire [1:0] _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_4 ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_12; // @[Mux.scala:50:70] wire _r_sectored_hit_valid_T = sector_hits_0 \| sector_hits_1; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T \| sector_hits_2; // @[package.scala:81:59] wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 \| sector_hits_3; // @[package.scala:81:59] wire [3:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45] wire [1:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18] wire [1:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18] wire _r_sectored_hit_bits_T_1 = \|r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14] wire [1:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 \| r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire _r_sectored_hit_bits_T_3 = _r_sectored_hit_bits_T_2[1]; // @[OneHot.scala:32:28] wire [1:0] _r_sectored_hit_bits_T_4 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}] wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] wire _tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30] wire tagMatch = superpage_entries_0_valid_0 & _tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30] wire ignore_1 = _ignore_T_1; // @[TLB.scala:182:{28,34}] wire _ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30] wire _tagMatch_T_1 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56] wire tagMatch_1 = special_entry_valid_0 & _tagMatch_T_1; // @[TLB.scala:178:{33,43}, :346:56] wire ignore_4 = _ignore_T_4; // @[TLB.scala:182:{28,34}] wire _ignore_T_5 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56] wire ignore_5 = _ignore_T_5; // @[TLB.scala:182:{28,34}] wire _T_12 = io_req_valid_0 & vm_enabled; // @[TLB.scala:318:7, :399:61, :617:22] wire _T_15 = sector_hits_0 \| sector_hits_1 \| sector_hits_2 \| sector_hits_3; // @[package.scala:81:59] wire _GEN_58 = do_refill & ~io_ptw_resp_bits_homogeneous_0; // @[TLB.scala:211:18, :318:7, :346:56, :408:29, :446:20, :474:{39,70}] wire _GEN_59 = ~do_refill \| ~io_ptw_resp_bits_homogeneous_0 \| io_ptw_resp_bits_level_0[1]; // @[TLB.scala:318:7, :341:30, :408:29, :446:20, :474:70, :476:{40,58}] wire _T_4 = waddr_1 == 2'h0; // @[TLB.scala:485:22, :486:75] wire _GEN_60 = r_memIdx == 2'h0; // @[package.scala:163:13] wire _GEN_61 = r_memIdx == 2'h1; // @[package.scala:163:13] wire _GEN_62 = r_memIdx == 2'h2; // @[package.scala:163:13] wire _GEN_63 = ~io_ptw_resp_bits_homogeneous_0 \| ~(io_ptw_resp_bits_level_0[1]); // @[TLB.scala:318:7, :339:29, :474:{39,70}, :476:{40,58}, :486:84] wire _GEN_64 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_65 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_66 = ~do_refill \| _GEN_63 \| ~(_T_4 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_67 = ~do_refill \| _GEN_63 \| ~(_T_4 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_68 = invalidate_refill & _GEN_60; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_69 = ~do_refill \| _GEN_63 \| ~_T_4; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_70 = invalidate_refill & _GEN_61; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_71 = invalidate_refill & _GEN_62; // @[TLB.scala:216:16, :220:46, :410:88, :489:34] wire _GEN_72 = invalidate_refill & (&r_memIdx); // @[package.scala:163:13] wire _T_6 = waddr_1 == 2'h1; // @[TLB.scala:197:28, :485:22, :486:75] wire _GEN_73 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_74 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_75 = ~do_refill \| _GEN_63 \| ~(_T_6 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_76 = ~do_refill \| _GEN_63 \| ~(_T_6 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_77 = ~do_refill \| _GEN_63 \| ~_T_6; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _T_8 = waddr_1 == 2'h2; // @[TLB.scala:485:22, :486:75] wire _GEN_78 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_79 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_80 = ~do_refill \| _GEN_63 \| ~(_T_8 & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_81 = ~do_refill \| _GEN_63 \| ~(_T_8 & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_82 = ~do_refill \| _GEN_63 \| ~_T_8; // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :486:{75,84}] wire _GEN_83 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_60); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_84 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_61); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_85 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & _GEN_62); // @[TLB.scala:211:18, :220:46, :339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _GEN_86 = ~do_refill \| _GEN_63 \| ~((&waddr_1) & (&r_memIdx)); // @[package.scala:163:13] wire _GEN_87 = ~do_refill \| _GEN_63 \| ~(&waddr_1); // @[TLB.scala:339:29, :341:30, :408:29, :446:20, :474:70, :476:58, :485:22, :486:{75,84}] wire _T_2491 = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] wire _T_24 = io_req_ready_0 & io_req_valid_0 & tlb_miss; // @[Decoupled.scala:51:35] wire _T_2490 = multipleHits \| reset; // @[Misc.scala:183:49] always @(posedge clock) begin // @[TLB.scala:318:7] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_0_tag_v <= _GEN_64 & sectored_entries_0_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_64) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_0_tag_v) & (_GEN_69 ? sectored_entries_0_0_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_1_tag_v <= _GEN_73 & sectored_entries_0_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_73) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_1_tag_v) & (_GEN_77 ? sectored_entries_0_1_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_2_tag_v <= _GEN_78 & sectored_entries_0_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_78) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_2_tag_v) & (_GEN_82 ? sectored_entries_0_2_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_0_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_0_3_tag_v <= _GEN_83 & sectored_entries_0_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_83) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_0_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_0_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_0_3_tag_v) & (_GEN_87 ? sectored_entries_0_3_valid_0 : ~_GEN_68 & (_GEN_60 \| ~(~r_sectored_hit_valid & _GEN_60) & sectored_entries_0_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_0_tag_v <= _GEN_65 & sectored_entries_1_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_65) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_0_tag_v) & (_GEN_69 ? sectored_entries_1_0_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_1_tag_v <= _GEN_74 & sectored_entries_1_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_74) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_1_tag_v) & (_GEN_77 ? sectored_entries_1_1_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_2_tag_v <= _GEN_79 & sectored_entries_1_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_79) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_2_tag_v) & (_GEN_82 ? sectored_entries_1_2_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_1_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_1_3_tag_v <= _GEN_84 & sectored_entries_1_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_84) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_1_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_1_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_1_3_tag_v) & (_GEN_87 ? sectored_entries_1_3_valid_0 : ~_GEN_70 & (_GEN_61 \| ~(~r_sectored_hit_valid & _GEN_61) & sectored_entries_1_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_0_tag_v <= _GEN_66 & sectored_entries_2_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_66) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_0_tag_v) & (_GEN_69 ? sectored_entries_2_0_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_0_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_1_tag_v <= _GEN_75 & sectored_entries_2_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_75) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_1_tag_v) & (_GEN_77 ? sectored_entries_2_1_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_1_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_2_tag_v <= _GEN_80 & sectored_entries_2_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_80) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_2_tag_v) & (_GEN_82 ? sectored_entries_2_2_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_2_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_2_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_2_3_tag_v <= _GEN_85 & sectored_entries_2_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_85) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_2_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_2_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_2_3_tag_v) & (_GEN_87 ? sectored_entries_2_3_valid_0 : ~_GEN_71 & (_GEN_62 \| ~(~r_sectored_hit_valid & _GEN_62) & sectored_entries_2_3_valid_0)); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :339:29, :357:27, :446:20, :474:70, :476:58, :486:84, :487:{15,38}, :489:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_0_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_0_tag_v <= _GEN_67 & sectored_entries_3_0_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_67) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_0_data_0 <= _sectored_entries_0_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_0_tag_v) & (_GEN_69 ? sectored_entries_3_0_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_0_valid_0)); // @[package.scala:163:13] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_1_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_1_tag_v <= _GEN_76 & sectored_entries_3_1_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_76) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_1_data_0 <= _sectored_entries_1_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_1_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_1_tag_v) & (_GEN_77 ? sectored_entries_3_1_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_1_valid_0)); // @[package.scala:163:13] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_2_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_2_tag_v <= _GEN_81 & sectored_entries_3_2_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_81) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_2_data_0 <= _sectored_entries_2_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_2_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_2_tag_v) & (_GEN_82 ? sectored_entries_3_2_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_2_valid_0)); // @[package.scala:163:13] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_level <= 2'h0; // @[TLB.scala:339:29] sectored_entries_3_3_tag_vpn <= r_refill_tag; // @[TLB.scala:339:29, :354:25] end sectored_entries_3_3_tag_v <= _GEN_86 & sectored_entries_3_3_tag_v; // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] if (_GEN_86) begin // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] end else // @[TLB.scala:339:29, :446:20, :474:70, :476:58, :486:84] sectored_entries_3_3_data_0 <= _sectored_entries_3_data_0_T; // @[TLB.scala:217:24, :339:29] sectored_entries_3_3_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~sectored_entries_3_3_tag_v) & (_GEN_87 ? sectored_entries_3_3_valid_0 : ~_GEN_72 & ((&r_memIdx) \| ~(~r_sectored_hit_valid & (&r_memIdx)) & sectored_entries_3_3_valid_0)); // @[package.scala:163:13] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_level <= {1'h0, _superpage_entries_0_level_T}; // @[package.scala:163:13] superpage_entries_0_tag_vpn <= r_refill_tag; // @[TLB.scala:341:30, :354:25] end superpage_entries_0_tag_v <= _GEN_59 & superpage_entries_0_tag_v; // @[TLB.scala:341:30, :446:20, :474:70, :476:58] if (_GEN_59) begin // @[TLB.scala:341:30, :446:20, :474:70, :476:58] end else // @[TLB.scala:341:30, :446:20, :474:70, :476:58] superpage_entries_0_data_0 <= _superpage_entries_0_data_0_T; // @[TLB.scala:217:24, :341:30] superpage_entries_0_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~superpage_entries_0_tag_v) & (_GEN_59 ? superpage_entries_0_valid_0 : ~invalidate_refill); // @[TLB.scala:216:16, :220:46, :223:{19,32,36}, :318:7, :341:30, :410:88, :446:20, :474:70, :476:58, :480:34, :718:19, :723:42, :728:46, :732:{24,41}] if (_GEN_58) begin // @[TLB.scala:211:18, :346:56, :446:20, :474:70] special_entry_level <= _special_entry_level_T; // @[package.scala:163:13] special_entry_tag_vpn <= r_refill_tag; // @[TLB.scala:346:56, :354:25] special_entry_data_0 <= _special_entry_data_0_T; // @[TLB.scala:217:24, :346:56] end special_entry_tag_v <= ~_GEN_58 & special_entry_tag_v; // @[TLB.scala:211:18, :212:16, :346:56, :446:20, :474:70] special_entry_valid_0 <= ~(_T_2490 \| io_sfence_valid_0 & ~special_entry_tag_v) & (_GEN_58 \| special_entry_valid_0); // @[TLB.scala:211:18, :216:16, :220:46, :223:{19,32,36}, :318:7, :346:56, :446:20, :474:70, :718:19, :723:42, :728:46, :732:{24,41}] if (_T_24) begin // @[Decoupled.scala:51:35] r_refill_tag <= vpn; // @[TLB.scala:335:30, :354:25] r_sectored_repl_addr <= _r_sectored_repl_addr_T_13; // @[TLB.scala:356:33, :757:8] r_sectored_hit_valid <= _r_sectored_hit_valid_T_2; // @[package.scala:81:59] r_sectored_hit_bits <= _r_sectored_hit_bits_T_4; // @[OneHot.scala:32:10] r_superpage_hit_valid <= superpage_hits_0; // @[TLB.scala:183:29, :358:28] r_need_gpa <= tlb_hit_if_not_gpa_miss; // @[TLB.scala:361:23, :610:43] end r_gpa_valid <= ~_T_2491 & (do_refill ? io_ptw_resp_bits_gpa_valid_0 : r_gpa_valid); // @[Decoupled.scala:51:35] if (do_refill) begin // @[TLB.scala:408:29] r_gpa <= io_ptw_resp_bits_gpa_bits_0; // @[TLB.scala:318:7, :363:18] r_gpa_is_pte <= io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :365:25] end if (_T_2491) // @[Decoupled.scala:51:35] r_gpa_vpn <= r_refill_tag; // @[TLB.scala:354:25, :364:22] if (reset) begin // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] state_vec_0 <= 3'h0; // @[Replacement.scala:305:17] state_vec_1 <= 3'h0; // @[Replacement.scala:305:17] state_vec_2 <= 3'h0; // @[Replacement.scala:305:17] state_vec_3 <= 3'h0; // @[Replacement.scala:305:17] end else begin // @[TLB.scala:318:7] if (io_ptw_resp_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (state == 2'h2 & io_sfence_valid_0) // @[TLB.scala:318:7, :352:22, :709:{17,28}] state <= 2'h3; // @[TLB.scala:352:22] else if (_T_25) begin // @[package.scala:16:47] if (io_ptw_req_ready_0) // @[TLB.scala:318:7] state <= _state_T; // @[TLB.scala:352:22, :704:45] else if (io_sfence_valid_0) // @[TLB.scala:318:7] state <= 2'h0; // @[TLB.scala:352:22] else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] end else if (_T_24) // @[Decoupled.scala:51:35] state <= 2'h1; // @[TLB.scala:197:28, :352:22] if (_T_12 & _T_15 & memIdx == 2'h0) // @[package.scala:81:59, :163:13] state_vec_0 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h1) // @[package.scala:81:59, :163:13] state_vec_1 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & memIdx == 2'h2) // @[package.scala:81:59, :163:13] state_vec_2 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] if (_T_12 & _T_15 & (&memIdx)) // @[package.scala:81:59, :163:13] state_vec_3 <= _state_vec_T_8; // @[Replacement.scala:202:12, :305:17] end always @(posedge) OptimizationBarrier_TLBEntryData_112 mpu_ppn_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_mpu_ppn_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_mpu_ppn_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_mpu_ppn_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_mpu_ppn_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_mpu_ppn_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_mpu_ppn_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_mpu_ppn_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_mpu_ppn_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_mpu_ppn_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_mpu_ppn_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_mpu_ppn_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_mpu_ppn_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_mpu_ppn_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_mpu_ppn_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_mpu_ppn_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_mpu_ppn_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_mpu_ppn_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_mpu_ppn_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_mpu_ppn_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_mpu_ppn_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_mpu_ppn_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_mpu_ppn_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_mpu_ppn_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_mpu_ppn_barrier_io_y_ppn) ); // @[package.scala:267:25] PMPChecker_s3_14 pmp ( // @[TLB.scala:416:19] .clock (clock), .reset (reset), .io_prv (mpu_priv[1:0]), // @[TLB.scala:415:27, :420:14] .io_pmp_0_cfg_l (io_ptw_pmp_0_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_a (io_ptw_pmp_0_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_x (io_ptw_pmp_0_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_w (io_ptw_pmp_0_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_0_cfg_r (io_ptw_pmp_0_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_0_addr (io_ptw_pmp_0_addr_0), // @[TLB.scala:318:7] .io_pmp_0_mask (io_ptw_pmp_0_mask_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_l (io_ptw_pmp_1_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_a (io_ptw_pmp_1_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_x (io_ptw_pmp_1_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_w (io_ptw_pmp_1_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_1_cfg_r (io_ptw_pmp_1_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_1_addr (io_ptw_pmp_1_addr_0), // @[TLB.scala:318:7] .io_pmp_1_mask (io_ptw_pmp_1_mask_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_l (io_ptw_pmp_2_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_a (io_ptw_pmp_2_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_x (io_ptw_pmp_2_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_w (io_ptw_pmp_2_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_2_cfg_r (io_ptw_pmp_2_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_2_addr (io_ptw_pmp_2_addr_0), // @[TLB.scala:318:7] .io_pmp_2_mask (io_ptw_pmp_2_mask_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_l (io_ptw_pmp_3_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_a (io_ptw_pmp_3_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_x (io_ptw_pmp_3_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_w (io_ptw_pmp_3_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_3_cfg_r (io_ptw_pmp_3_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_3_addr (io_ptw_pmp_3_addr_0), // @[TLB.scala:318:7] .io_pmp_3_mask (io_ptw_pmp_3_mask_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_l (io_ptw_pmp_4_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_a (io_ptw_pmp_4_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_x (io_ptw_pmp_4_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_w (io_ptw_pmp_4_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_4_cfg_r (io_ptw_pmp_4_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_4_addr (io_ptw_pmp_4_addr_0), // @[TLB.scala:318:7] .io_pmp_4_mask (io_ptw_pmp_4_mask_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_l (io_ptw_pmp_5_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_a (io_ptw_pmp_5_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_x (io_ptw_pmp_5_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_w (io_ptw_pmp_5_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_5_cfg_r (io_ptw_pmp_5_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_5_addr (io_ptw_pmp_5_addr_0), // @[TLB.scala:318:7] .io_pmp_5_mask (io_ptw_pmp_5_mask_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_l (io_ptw_pmp_6_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_a (io_ptw_pmp_6_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_x (io_ptw_pmp_6_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_w (io_ptw_pmp_6_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_6_cfg_r (io_ptw_pmp_6_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_6_addr (io_ptw_pmp_6_addr_0), // @[TLB.scala:318:7] .io_pmp_6_mask (io_ptw_pmp_6_mask_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_l (io_ptw_pmp_7_cfg_l_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_a (io_ptw_pmp_7_cfg_a_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_x (io_ptw_pmp_7_cfg_x_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_w (io_ptw_pmp_7_cfg_w_0), // @[TLB.scala:318:7] .io_pmp_7_cfg_r (io_ptw_pmp_7_cfg_r_0), // @[TLB.scala:318:7] .io_pmp_7_addr (io_ptw_pmp_7_addr_0), // @[TLB.scala:318:7] .io_pmp_7_mask (io_ptw_pmp_7_mask_0), // @[TLB.scala:318:7] .io_addr (mpu_physaddr[31:0]), // @[TLB.scala:414:25, :417:15] .io_size (io_req_bits_size_0), // @[TLB.scala:318:7] .io_r (_pmp_io_r), .io_w (_pmp_io_w), .io_x (_pmp_io_x) ); // @[TLB.scala:416:19] PMAChecker_14 pma ( // @[TLB.scala:422:19] .clock (clock), .reset (reset), .io_paddr (mpu_physaddr), // @[TLB.scala:414:25] .io_resp_cacheable (cacheable), .io_resp_r (_pma_io_resp_r), .io_resp_w (_pma_io_resp_w), .io_resp_pp (_pma_io_resp_pp), .io_resp_al (_pma_io_resp_al), .io_resp_aa (_pma_io_resp_aa), .io_resp_x (_pma_io_resp_x), .io_resp_eff (_pma_io_resp_eff) ); // @[TLB.scala:422:19] assign newEntry_ppp = _pma_io_resp_pp; // @[TLB.scala:422:19, :449:24] assign newEntry_pal = _pma_io_resp_al; // @[TLB.scala:422:19, :449:24] assign newEntry_paa = _pma_io_resp_aa; // @[TLB.scala:422:19, :449:24] assign newEntry_eff = _pma_io_resp_eff; // @[TLB.scala:422:19, :449:24] OptimizationBarrier_TLBEntryData_113 entries_barrier ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_io_y_ppn), .io_y_u (_entries_barrier_io_y_u), .io_y_ae_ptw (_entries_barrier_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_io_y_ae_stage2), .io_y_pf (_entries_barrier_io_y_pf), .io_y_gf (_entries_barrier_io_y_gf), .io_y_sw (_entries_barrier_io_y_sw), .io_y_sx (_entries_barrier_io_y_sx), .io_y_sr (_entries_barrier_io_y_sr), .io_y_hw (_entries_barrier_io_y_hw), .io_y_hx (_entries_barrier_io_y_hx), .io_y_hr (_entries_barrier_io_y_hr), .io_y_pw (_entries_barrier_io_y_pw), .io_y_px (_entries_barrier_io_y_px), .io_y_pr (_entries_barrier_io_y_pr), .io_y_ppp (_entries_barrier_io_y_ppp), .io_y_pal (_entries_barrier_io_y_pal), .io_y_paa (_entries_barrier_io_y_paa), .io_y_eff (_entries_barrier_io_y_eff), .io_y_c (_entries_barrier_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_114 entries_barrier_1 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_2_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_2_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_2_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_2_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_2_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_2_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_2_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_2_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_2_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_2_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_2_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_2_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_2_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_2_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_2_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_2_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_2_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_2_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_2_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_2_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_2_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_2_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_1_io_y_ppn), .io_y_u (_entries_barrier_1_io_y_u), .io_y_ae_ptw (_entries_barrier_1_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_1_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_1_io_y_ae_stage2), .io_y_pf (_entries_barrier_1_io_y_pf), .io_y_gf (_entries_barrier_1_io_y_gf), .io_y_sw (_entries_barrier_1_io_y_sw), .io_y_sx (_entries_barrier_1_io_y_sx), .io_y_sr (_entries_barrier_1_io_y_sr), .io_y_hw (_entries_barrier_1_io_y_hw), .io_y_hx (_entries_barrier_1_io_y_hx), .io_y_hr (_entries_barrier_1_io_y_hr), .io_y_pw (_entries_barrier_1_io_y_pw), .io_y_px (_entries_barrier_1_io_y_px), .io_y_pr (_entries_barrier_1_io_y_pr), .io_y_ppp (_entries_barrier_1_io_y_ppp), .io_y_pal (_entries_barrier_1_io_y_pal), .io_y_paa (_entries_barrier_1_io_y_paa), .io_y_eff (_entries_barrier_1_io_y_eff), .io_y_c (_entries_barrier_1_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_115 entries_barrier_2 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_4_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_4_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_4_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_4_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_4_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_4_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_4_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_4_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_4_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_4_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_4_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_4_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_4_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_4_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_4_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_4_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_4_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_4_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_4_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_4_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_4_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_4_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_2_io_y_ppn), .io_y_u (_entries_barrier_2_io_y_u), .io_y_ae_ptw (_entries_barrier_2_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_2_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_2_io_y_ae_stage2), .io_y_pf (_entries_barrier_2_io_y_pf), .io_y_gf (_entries_barrier_2_io_y_gf), .io_y_sw (_entries_barrier_2_io_y_sw), .io_y_sx (_entries_barrier_2_io_y_sx), .io_y_sr (_entries_barrier_2_io_y_sr), .io_y_hw (_entries_barrier_2_io_y_hw), .io_y_hx (_entries_barrier_2_io_y_hx), .io_y_hr (_entries_barrier_2_io_y_hr), .io_y_pw (_entries_barrier_2_io_y_pw), .io_y_px (_entries_barrier_2_io_y_px), .io_y_pr (_entries_barrier_2_io_y_pr), .io_y_ppp (_entries_barrier_2_io_y_ppp), .io_y_pal (_entries_barrier_2_io_y_pal), .io_y_paa (_entries_barrier_2_io_y_paa), .io_y_eff (_entries_barrier_2_io_y_eff), .io_y_c (_entries_barrier_2_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_116 entries_barrier_3 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_6_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_6_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_6_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_6_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_6_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_6_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_6_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_6_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_6_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_6_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_6_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_6_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_6_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_6_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_6_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_6_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_6_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_6_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_6_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_6_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_6_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_6_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_3_io_y_ppn), .io_y_u (_entries_barrier_3_io_y_u), .io_y_ae_ptw (_entries_barrier_3_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_3_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_3_io_y_ae_stage2), .io_y_pf (_entries_barrier_3_io_y_pf), .io_y_gf (_entries_barrier_3_io_y_gf), .io_y_sw (_entries_barrier_3_io_y_sw), .io_y_sx (_entries_barrier_3_io_y_sx), .io_y_sr (_entries_barrier_3_io_y_sr), .io_y_hw (_entries_barrier_3_io_y_hw), .io_y_hx (_entries_barrier_3_io_y_hx), .io_y_hr (_entries_barrier_3_io_y_hr), .io_y_pw (_entries_barrier_3_io_y_pw), .io_y_px (_entries_barrier_3_io_y_px), .io_y_pr (_entries_barrier_3_io_y_pr), .io_y_ppp (_entries_barrier_3_io_y_ppp), .io_y_pal (_entries_barrier_3_io_y_pal), .io_y_paa (_entries_barrier_3_io_y_paa), .io_y_eff (_entries_barrier_3_io_y_eff), .io_y_c (_entries_barrier_3_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_117 entries_barrier_4 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_8_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_8_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_8_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_8_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_8_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_8_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_8_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_8_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_8_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_8_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_8_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_8_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_8_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_8_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_8_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_8_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_8_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_8_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_8_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_8_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_8_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_8_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_4_io_y_ppn), .io_y_u (_entries_barrier_4_io_y_u), .io_y_ae_ptw (_entries_barrier_4_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_4_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_4_io_y_ae_stage2), .io_y_pf (_entries_barrier_4_io_y_pf), .io_y_gf (_entries_barrier_4_io_y_gf), .io_y_sw (_entries_barrier_4_io_y_sw), .io_y_sx (_entries_barrier_4_io_y_sx), .io_y_sr (_entries_barrier_4_io_y_sr), .io_y_hw (_entries_barrier_4_io_y_hw), .io_y_hx (_entries_barrier_4_io_y_hx), .io_y_hr (_entries_barrier_4_io_y_hr), .io_y_pw (_entries_barrier_4_io_y_pw), .io_y_px (_entries_barrier_4_io_y_px), .io_y_pr (_entries_barrier_4_io_y_pr), .io_y_ppp (_entries_barrier_4_io_y_ppp), .io_y_pal (_entries_barrier_4_io_y_pal), .io_y_paa (_entries_barrier_4_io_y_paa), .io_y_eff (_entries_barrier_4_io_y_eff), .io_y_c (_entries_barrier_4_io_y_c) ); // @[package.scala:267:25] OptimizationBarrier_TLBEntryData_118 entries_barrier_5 ( // @[package.scala:267:25] .clock (clock), .reset (reset), .io_x_ppn (_entries_WIRE_10_ppn), // @[TLB.scala:170:77] .io_x_u (_entries_WIRE_10_u), // @[TLB.scala:170:77] .io_x_g (_entries_WIRE_10_g), // @[TLB.scala:170:77] .io_x_ae_ptw (_entries_WIRE_10_ae_ptw), // @[TLB.scala:170:77] .io_x_ae_final (_entries_WIRE_10_ae_final), // @[TLB.scala:170:77] .io_x_ae_stage2 (_entries_WIRE_10_ae_stage2), // @[TLB.scala:170:77] .io_x_pf (_entries_WIRE_10_pf), // @[TLB.scala:170:77] .io_x_gf (_entries_WIRE_10_gf), // @[TLB.scala:170:77] .io_x_sw (_entries_WIRE_10_sw), // @[TLB.scala:170:77] .io_x_sx (_entries_WIRE_10_sx), // @[TLB.scala:170:77] .io_x_sr (_entries_WIRE_10_sr), // @[TLB.scala:170:77] .io_x_hw (_entries_WIRE_10_hw), // @[TLB.scala:170:77] .io_x_hx (_entries_WIRE_10_hx), // @[TLB.scala:170:77] .io_x_hr (_entries_WIRE_10_hr), // @[TLB.scala:170:77] .io_x_pw (_entries_WIRE_10_pw), // @[TLB.scala:170:77] .io_x_px (_entries_WIRE_10_px), // @[TLB.scala:170:77] .io_x_pr (_entries_WIRE_10_pr), // @[TLB.scala:170:77] .io_x_ppp (_entries_WIRE_10_ppp), // @[TLB.scala:170:77] .io_x_pal (_entries_WIRE_10_pal), // @[TLB.scala:170:77] .io_x_paa (_entries_WIRE_10_paa), // @[TLB.scala:170:77] .io_x_eff (_entries_WIRE_10_eff), // @[TLB.scala:170:77] .io_x_c (_entries_WIRE_10_c), // @[TLB.scala:170:77] .io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[TLB.scala:170:77] .io_y_ppn (_entries_barrier_5_io_y_ppn), .io_y_u (_entries_barrier_5_io_y_u), .io_y_ae_ptw (_entries_barrier_5_io_y_ae_ptw), .io_y_ae_final (_entries_barrier_5_io_y_ae_final), .io_y_ae_stage2 (_entries_barrier_5_io_y_ae_stage2), .io_y_pf (_entries_barrier_5_io_y_pf), .io_y_gf (_entries_barrier_5_io_y_gf), .io_y_sw (_entries_barrier_5_io_y_sw), .io_y_sx (_entries_barrier_5_io_y_sx), .io_y_sr (_entries_barrier_5_io_y_sr), .io_y_hw (_entries_barrier_5_io_y_hw), .io_y_hx (_entries_barrier_5_io_y_hx), .io_y_hr (_entries_barrier_5_io_y_hr) ); // @[package.scala:267:25] assign io_req_ready = io_req_ready_0; // @[TLB.scala:318:7] assign io_resp_miss = io_resp_miss_0; // @[TLB.scala:318:7] assign io_resp_paddr = io_resp_paddr_0; // @[TLB.scala:318:7] assign io_ptw_req_valid = io_ptw_req_valid_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7] assign io_ptw_req_bits_bits_need_gpa = io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_239 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip	module PriorityQueueStage_239( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_121 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_121( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_200 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_368 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0	module AsyncResetSynchronizerShiftReg_w1_d3_i0_200( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_368 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ClockCrossingReg_w116 : input clock : Clock input reset : Reset output io : { flip d : UInt<116>, q : UInt<116>, flip en : UInt<1>} reg cdc_reg : UInt<116>, clock when io.en : connect cdc_reg, io.d connect io.q, cdc_reg	module ClockCrossingReg_w116( // @[SynchronizerReg.scala:191:7] input clock, // @[SynchronizerReg.scala:191:7] input reset, // @[SynchronizerReg.scala:191:7] input [115:0] io_d, // @[SynchronizerReg.scala:195:14] output [115:0] io_q, // @[SynchronizerReg.scala:195:14] input io_en // @[SynchronizerReg.scala:195:14] ); wire [115:0] io_d_0 = io_d; // @[SynchronizerReg.scala:191:7] wire io_en_0 = io_en; // @[SynchronizerReg.scala:191:7] wire [115:0] io_q_0; // @[SynchronizerReg.scala:191:7] reg [115:0] cdc_reg; // @[SynchronizerReg.scala:201:76] assign io_q_0 = cdc_reg; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge clock) begin // @[SynchronizerReg.scala:191:7] if (io_en_0) // @[SynchronizerReg.scala:191:7] cdc_reg <= io_d_0; // @[SynchronizerReg.scala:191:7, :201:76] always @(posedge) assign io_q = io_q_0; // @[SynchronizerReg.scala:191:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_211 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg	module PE_211( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i32_e8_s24_2 : output io : { flip signedIn : UInt<1>, flip in : UInt<32>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 31, 31) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<32>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 31, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2) node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3) node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4) node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5) node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6) node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7) node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8) node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9) node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10) node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11) node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12) node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13) node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14) node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15) node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16) node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17) node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18) node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19) node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20) node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21) node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22) node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23) node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24) node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25) node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26) node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27) node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28) node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29) node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30) node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31) node _intAsRawFloat_adjustedNormDist_T_32 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<5>(0h1e), UInt<5>(0h1f)) node _intAsRawFloat_adjustedNormDist_T_33 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_32) node _intAsRawFloat_adjustedNormDist_T_34 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_33) node _intAsRawFloat_adjustedNormDist_T_35 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_34) node _intAsRawFloat_adjustedNormDist_T_36 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_35) node _intAsRawFloat_adjustedNormDist_T_37 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_36) node _intAsRawFloat_adjustedNormDist_T_38 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_37) node _intAsRawFloat_adjustedNormDist_T_39 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_38) node _intAsRawFloat_adjustedNormDist_T_40 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_39) node _intAsRawFloat_adjustedNormDist_T_41 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_40) node _intAsRawFloat_adjustedNormDist_T_42 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_41) node _intAsRawFloat_adjustedNormDist_T_43 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_42) node _intAsRawFloat_adjustedNormDist_T_44 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_43) node _intAsRawFloat_adjustedNormDist_T_45 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_44) node _intAsRawFloat_adjustedNormDist_T_46 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_45) node _intAsRawFloat_adjustedNormDist_T_47 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_46) node _intAsRawFloat_adjustedNormDist_T_48 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_47) node _intAsRawFloat_adjustedNormDist_T_49 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_48) node _intAsRawFloat_adjustedNormDist_T_50 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_49) node _intAsRawFloat_adjustedNormDist_T_51 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_50) node _intAsRawFloat_adjustedNormDist_T_52 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_51) node _intAsRawFloat_adjustedNormDist_T_53 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_52) node _intAsRawFloat_adjustedNormDist_T_54 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_53) node _intAsRawFloat_adjustedNormDist_T_55 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_54) node _intAsRawFloat_adjustedNormDist_T_56 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_55) node _intAsRawFloat_adjustedNormDist_T_57 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_56) node _intAsRawFloat_adjustedNormDist_T_58 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_57) node _intAsRawFloat_adjustedNormDist_T_59 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_58) node _intAsRawFloat_adjustedNormDist_T_60 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_59) node _intAsRawFloat_adjustedNormDist_T_61 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_60) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_61) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 31, 0) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<8>, sig : UInt<33>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 31, 31) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 4, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_2 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags	module INToRecFN_i32_e8_s24_2( // @[INToRecFN.scala:43:7] input [31:0] io_in, // @[INToRecFN.scala:46:16] output [32:0] io_out // @[INToRecFN.scala:46:16] ); wire [31:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_signedIn = 1'h1; // @[INToRecFN.scala:43:7] wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7] wire [32:0] io_out_0; // @[INToRecFN.scala:43:7] wire [4:0] io_exceptionFlags; // @[INToRecFN.scala:43:7] wire _intAsRawFloat_sign_T = io_in_0[31]; // @[rawFloatFromIN.scala:51:34] wire intAsRawFloat_sign = _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}] wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23] wire [32:0] _intAsRawFloat_absIn_T = 33'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31] wire [31:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[31:0]; // @[rawFloatFromIN.scala:52:31] wire [31:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}] wire [63:0] _intAsRawFloat_extAbsIn_T = {32'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44] wire [31:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[31:0]; // @[rawFloatFromIN.scala:53:{44,53}] wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53] wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53] wire [4:0] _intAsRawFloat_adjustedNormDist_T_32 = {4'hF, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_33 = _intAsRawFloat_adjustedNormDist_T_2 ? 5'h1D : _intAsRawFloat_adjustedNormDist_T_32; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_34 = _intAsRawFloat_adjustedNormDist_T_3 ? 5'h1C : _intAsRawFloat_adjustedNormDist_T_33; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_35 = _intAsRawFloat_adjustedNormDist_T_4 ? 5'h1B : _intAsRawFloat_adjustedNormDist_T_34; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_36 = _intAsRawFloat_adjustedNormDist_T_5 ? 5'h1A : _intAsRawFloat_adjustedNormDist_T_35; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_37 = _intAsRawFloat_adjustedNormDist_T_6 ? 5'h19 : _intAsRawFloat_adjustedNormDist_T_36; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_38 = _intAsRawFloat_adjustedNormDist_T_7 ? 5'h18 : _intAsRawFloat_adjustedNormDist_T_37; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_39 = _intAsRawFloat_adjustedNormDist_T_8 ? 5'h17 : _intAsRawFloat_adjustedNormDist_T_38; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_40 = _intAsRawFloat_adjustedNormDist_T_9 ? 5'h16 : _intAsRawFloat_adjustedNormDist_T_39; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_41 = _intAsRawFloat_adjustedNormDist_T_10 ? 5'h15 : _intAsRawFloat_adjustedNormDist_T_40; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_42 = _intAsRawFloat_adjustedNormDist_T_11 ? 5'h14 : _intAsRawFloat_adjustedNormDist_T_41; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_43 = _intAsRawFloat_adjustedNormDist_T_12 ? 5'h13 : _intAsRawFloat_adjustedNormDist_T_42; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_44 = _intAsRawFloat_adjustedNormDist_T_13 ? 5'h12 : _intAsRawFloat_adjustedNormDist_T_43; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_45 = _intAsRawFloat_adjustedNormDist_T_14 ? 5'h11 : _intAsRawFloat_adjustedNormDist_T_44; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_46 = _intAsRawFloat_adjustedNormDist_T_15 ? 5'h10 : _intAsRawFloat_adjustedNormDist_T_45; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_47 = _intAsRawFloat_adjustedNormDist_T_16 ? 5'hF : _intAsRawFloat_adjustedNormDist_T_46; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_48 = _intAsRawFloat_adjustedNormDist_T_17 ? 5'hE : _intAsRawFloat_adjustedNormDist_T_47; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_49 = _intAsRawFloat_adjustedNormDist_T_18 ? 5'hD : _intAsRawFloat_adjustedNormDist_T_48; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_50 = _intAsRawFloat_adjustedNormDist_T_19 ? 5'hC : _intAsRawFloat_adjustedNormDist_T_49; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_51 = _intAsRawFloat_adjustedNormDist_T_20 ? 5'hB : _intAsRawFloat_adjustedNormDist_T_50; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_52 = _intAsRawFloat_adjustedNormDist_T_21 ? 5'hA : _intAsRawFloat_adjustedNormDist_T_51; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_53 = _intAsRawFloat_adjustedNormDist_T_22 ? 5'h9 : _intAsRawFloat_adjustedNormDist_T_52; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_54 = _intAsRawFloat_adjustedNormDist_T_23 ? 5'h8 : _intAsRawFloat_adjustedNormDist_T_53; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_55 = _intAsRawFloat_adjustedNormDist_T_24 ? 5'h7 : _intAsRawFloat_adjustedNormDist_T_54; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_56 = _intAsRawFloat_adjustedNormDist_T_25 ? 5'h6 : _intAsRawFloat_adjustedNormDist_T_55; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_57 = _intAsRawFloat_adjustedNormDist_T_26 ? 5'h5 : _intAsRawFloat_adjustedNormDist_T_56; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_58 = _intAsRawFloat_adjustedNormDist_T_27 ? 5'h4 : _intAsRawFloat_adjustedNormDist_T_57; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_59 = _intAsRawFloat_adjustedNormDist_T_28 ? 5'h3 : _intAsRawFloat_adjustedNormDist_T_58; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_60 = _intAsRawFloat_adjustedNormDist_T_29 ? 5'h2 : _intAsRawFloat_adjustedNormDist_T_59; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_adjustedNormDist_T_61 = _intAsRawFloat_adjustedNormDist_T_30 ? 5'h1 : _intAsRawFloat_adjustedNormDist_T_60; // @[Mux.scala:50:70] wire [4:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_31 ? 5'h0 : _intAsRawFloat_adjustedNormDist_T_61; // @[Mux.scala:50:70] wire [4:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [62:0] _intAsRawFloat_sig_T = {31'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70] wire [31:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[31:0]; // @[rawFloatFromIN.scala:56:{22,41}] wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23] wire [7:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72] wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23] wire [7:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23] wire [32:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[31]; // @[rawFloatFromIN.scala:56:41, :62:28] assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}] assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23] wire [4:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}] wire [6:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}] assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}] assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72] assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20] RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_2 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15] .io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23] .io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23] .io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23] .io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[INToRecFN.scala:60:15] assign io_out = io_out_0; // @[INToRecFN.scala:43:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_24 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_37 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE	module AsyncValidSync_24( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_37 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RegisterRead_2 : input clock : Clock input reset : Reset output io : { flip iss_valids : UInt<1>[1], flip iss_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], flip rf_read_ports : { flip addr : UInt<7>, data : UInt<65>}[3], flip prf_read_ports : { flip addr : UInt<5>, data : UInt<1>}[1], flip bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0], flip pred_bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<1>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0], exe_reqs : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}[1], flip kill : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}} wire rrd_valids : UInt<1>[1] wire rrd_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1] wire _exe_reg_valids_WIRE : UInt<1>[1] connect _exe_reg_valids_WIRE[0], UInt<1>(0h0) regreset exe_reg_valids : UInt<1>[1], clock, reset, _exe_reg_valids_WIRE reg exe_reg_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], clock reg exe_reg_rs1_data : UInt<65>[1], clock reg exe_reg_rs2_data : UInt<65>[1], clock reg exe_reg_rs3_data : UInt<65>[1], clock reg exe_reg_pred_data : UInt<1>[1], clock inst rrd_decode_unit of RegisterReadDecode_5 connect rrd_decode_unit.clock, clock connect rrd_decode_unit.reset, reset connect rrd_decode_unit.io.iss_valid, io.iss_valids[0] connect rrd_decode_unit.io.iss_uop.debug_tsrc, io.iss_uops[0].debug_tsrc connect rrd_decode_unit.io.iss_uop.debug_fsrc, io.iss_uops[0].debug_fsrc connect rrd_decode_unit.io.iss_uop.bp_xcpt_if, io.iss_uops[0].bp_xcpt_if connect rrd_decode_unit.io.iss_uop.bp_debug_if, io.iss_uops[0].bp_debug_if connect rrd_decode_unit.io.iss_uop.xcpt_ma_if, io.iss_uops[0].xcpt_ma_if connect rrd_decode_unit.io.iss_uop.xcpt_ae_if, io.iss_uops[0].xcpt_ae_if connect rrd_decode_unit.io.iss_uop.xcpt_pf_if, io.iss_uops[0].xcpt_pf_if connect rrd_decode_unit.io.iss_uop.fp_single, io.iss_uops[0].fp_single connect rrd_decode_unit.io.iss_uop.fp_val, io.iss_uops[0].fp_val connect rrd_decode_unit.io.iss_uop.frs3_en, io.iss_uops[0].frs3_en connect rrd_decode_unit.io.iss_uop.lrs2_rtype, io.iss_uops[0].lrs2_rtype connect rrd_decode_unit.io.iss_uop.lrs1_rtype, io.iss_uops[0].lrs1_rtype connect rrd_decode_unit.io.iss_uop.dst_rtype, io.iss_uops[0].dst_rtype connect rrd_decode_unit.io.iss_uop.ldst_val, io.iss_uops[0].ldst_val connect rrd_decode_unit.io.iss_uop.lrs3, io.iss_uops[0].lrs3 connect rrd_decode_unit.io.iss_uop.lrs2, io.iss_uops[0].lrs2 connect rrd_decode_unit.io.iss_uop.lrs1, io.iss_uops[0].lrs1 connect rrd_decode_unit.io.iss_uop.ldst, io.iss_uops[0].ldst connect rrd_decode_unit.io.iss_uop.ldst_is_rs1, io.iss_uops[0].ldst_is_rs1 connect rrd_decode_unit.io.iss_uop.flush_on_commit, io.iss_uops[0].flush_on_commit connect rrd_decode_unit.io.iss_uop.is_unique, io.iss_uops[0].is_unique connect rrd_decode_unit.io.iss_uop.is_sys_pc2epc, io.iss_uops[0].is_sys_pc2epc connect rrd_decode_unit.io.iss_uop.uses_stq, io.iss_uops[0].uses_stq connect rrd_decode_unit.io.iss_uop.uses_ldq, io.iss_uops[0].uses_ldq connect rrd_decode_unit.io.iss_uop.is_amo, io.iss_uops[0].is_amo connect rrd_decode_unit.io.iss_uop.is_fencei, io.iss_uops[0].is_fencei connect rrd_decode_unit.io.iss_uop.is_fence, io.iss_uops[0].is_fence connect rrd_decode_unit.io.iss_uop.mem_signed, io.iss_uops[0].mem_signed connect rrd_decode_unit.io.iss_uop.mem_size, io.iss_uops[0].mem_size connect rrd_decode_unit.io.iss_uop.mem_cmd, io.iss_uops[0].mem_cmd connect rrd_decode_unit.io.iss_uop.bypassable, io.iss_uops[0].bypassable connect rrd_decode_unit.io.iss_uop.exc_cause, io.iss_uops[0].exc_cause connect rrd_decode_unit.io.iss_uop.exception, io.iss_uops[0].exception connect rrd_decode_unit.io.iss_uop.stale_pdst, io.iss_uops[0].stale_pdst connect rrd_decode_unit.io.iss_uop.ppred_busy, io.iss_uops[0].ppred_busy connect rrd_decode_unit.io.iss_uop.prs3_busy, io.iss_uops[0].prs3_busy connect rrd_decode_unit.io.iss_uop.prs2_busy, io.iss_uops[0].prs2_busy connect rrd_decode_unit.io.iss_uop.prs1_busy, io.iss_uops[0].prs1_busy connect rrd_decode_unit.io.iss_uop.ppred, io.iss_uops[0].ppred connect rrd_decode_unit.io.iss_uop.prs3, io.iss_uops[0].prs3 connect rrd_decode_unit.io.iss_uop.prs2, io.iss_uops[0].prs2 connect rrd_decode_unit.io.iss_uop.prs1, io.iss_uops[0].prs1 connect rrd_decode_unit.io.iss_uop.pdst, io.iss_uops[0].pdst connect rrd_decode_unit.io.iss_uop.rxq_idx, io.iss_uops[0].rxq_idx connect rrd_decode_unit.io.iss_uop.stq_idx, io.iss_uops[0].stq_idx connect rrd_decode_unit.io.iss_uop.ldq_idx, io.iss_uops[0].ldq_idx connect rrd_decode_unit.io.iss_uop.rob_idx, io.iss_uops[0].rob_idx connect rrd_decode_unit.io.iss_uop.csr_addr, io.iss_uops[0].csr_addr connect rrd_decode_unit.io.iss_uop.imm_packed, io.iss_uops[0].imm_packed connect rrd_decode_unit.io.iss_uop.taken, io.iss_uops[0].taken connect rrd_decode_unit.io.iss_uop.pc_lob, io.iss_uops[0].pc_lob connect rrd_decode_unit.io.iss_uop.edge_inst, io.iss_uops[0].edge_inst connect rrd_decode_unit.io.iss_uop.ftq_idx, io.iss_uops[0].ftq_idx connect rrd_decode_unit.io.iss_uop.br_tag, io.iss_uops[0].br_tag connect rrd_decode_unit.io.iss_uop.br_mask, io.iss_uops[0].br_mask connect rrd_decode_unit.io.iss_uop.is_sfb, io.iss_uops[0].is_sfb connect rrd_decode_unit.io.iss_uop.is_jal, io.iss_uops[0].is_jal connect rrd_decode_unit.io.iss_uop.is_jalr, io.iss_uops[0].is_jalr connect rrd_decode_unit.io.iss_uop.is_br, io.iss_uops[0].is_br connect rrd_decode_unit.io.iss_uop.iw_p2_poisoned, io.iss_uops[0].iw_p2_poisoned connect rrd_decode_unit.io.iss_uop.iw_p1_poisoned, io.iss_uops[0].iw_p1_poisoned connect rrd_decode_unit.io.iss_uop.iw_state, io.iss_uops[0].iw_state connect rrd_decode_unit.io.iss_uop.ctrl.is_std, io.iss_uops[0].ctrl.is_std connect rrd_decode_unit.io.iss_uop.ctrl.is_sta, io.iss_uops[0].ctrl.is_sta connect rrd_decode_unit.io.iss_uop.ctrl.is_load, io.iss_uops[0].ctrl.is_load connect rrd_decode_unit.io.iss_uop.ctrl.csr_cmd, io.iss_uops[0].ctrl.csr_cmd connect rrd_decode_unit.io.iss_uop.ctrl.fcn_dw, io.iss_uops[0].ctrl.fcn_dw connect rrd_decode_unit.io.iss_uop.ctrl.op_fcn, io.iss_uops[0].ctrl.op_fcn connect rrd_decode_unit.io.iss_uop.ctrl.imm_sel, io.iss_uops[0].ctrl.imm_sel connect rrd_decode_unit.io.iss_uop.ctrl.op2_sel, io.iss_uops[0].ctrl.op2_sel connect rrd_decode_unit.io.iss_uop.ctrl.op1_sel, io.iss_uops[0].ctrl.op1_sel connect rrd_decode_unit.io.iss_uop.ctrl.br_type, io.iss_uops[0].ctrl.br_type connect rrd_decode_unit.io.iss_uop.fu_code, io.iss_uops[0].fu_code connect rrd_decode_unit.io.iss_uop.iq_type, io.iss_uops[0].iq_type connect rrd_decode_unit.io.iss_uop.debug_pc, io.iss_uops[0].debug_pc connect rrd_decode_unit.io.iss_uop.is_rvc, io.iss_uops[0].is_rvc connect rrd_decode_unit.io.iss_uop.debug_inst, io.iss_uops[0].debug_inst connect rrd_decode_unit.io.iss_uop.inst, io.iss_uops[0].inst connect rrd_decode_unit.io.iss_uop.uopc, io.iss_uops[0].uopc node _rrd_valids_0_T = and(io.brupdate.b1.mispredict_mask, rrd_decode_unit.io.rrd_uop.br_mask) node _rrd_valids_0_T_1 = neq(_rrd_valids_0_T, UInt<1>(0h0)) node _rrd_valids_0_T_2 = eq(_rrd_valids_0_T_1, UInt<1>(0h0)) node _rrd_valids_0_T_3 = and(rrd_decode_unit.io.rrd_valid, _rrd_valids_0_T_2) reg rrd_valids_0_REG : UInt<1>, clock connect rrd_valids_0_REG, _rrd_valids_0_T_3 connect rrd_valids[0], rrd_valids_0_REG wire rrd_uops_0_newuop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} connect rrd_uops_0_newuop, rrd_decode_unit.io.rrd_uop node _rrd_uops_0_newuop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _rrd_uops_0_newuop_br_mask_T_1 = and(rrd_decode_unit.io.rrd_uop.br_mask, _rrd_uops_0_newuop_br_mask_T) connect rrd_uops_0_newuop.br_mask, _rrd_uops_0_newuop_br_mask_T_1 reg rrd_uops_0_REG : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock connect rrd_uops_0_REG, rrd_uops_0_newuop connect rrd_uops[0], rrd_uops_0_REG wire rrd_rs1_data : UInt<65>[1] wire rrd_rs2_data : UInt<65>[1] wire rrd_rs3_data : UInt<65>[1] wire rrd_pred_data : UInt<1>[1] invalidate rrd_rs1_data[0] invalidate rrd_rs2_data[0] invalidate rrd_rs3_data[0] invalidate rrd_pred_data[0] invalidate io.prf_read_ports[0].data invalidate io.prf_read_ports[0].addr connect io.rf_read_ports[0].addr, io.iss_uops[0].prs1 connect io.rf_read_ports[1].addr, io.iss_uops[0].prs2 connect io.rf_read_ports[2].addr, io.iss_uops[0].prs3 node _rrd_rs1_data_0_T = eq(io.iss_uops[0].prs1, UInt<1>(0h0)) reg rrd_rs1_data_0_REG : UInt<1>, clock connect rrd_rs1_data_0_REG, _rrd_rs1_data_0_T node _rrd_rs1_data_0_T_1 = mux(rrd_rs1_data_0_REG, UInt<1>(0h0), io.rf_read_ports[0].data) connect rrd_rs1_data[0], _rrd_rs1_data_0_T_1 node _rrd_rs2_data_0_T = eq(io.iss_uops[0].prs2, UInt<1>(0h0)) reg rrd_rs2_data_0_REG : UInt<1>, clock connect rrd_rs2_data_0_REG, _rrd_rs2_data_0_T node _rrd_rs2_data_0_T_1 = mux(rrd_rs2_data_0_REG, UInt<1>(0h0), io.rf_read_ports[1].data) connect rrd_rs2_data[0], _rrd_rs2_data_0_T_1 node _rrd_rs3_data_0_T = eq(io.iss_uops[0].prs3, UInt<1>(0h0)) reg rrd_rs3_data_0_REG : UInt<1>, clock connect rrd_rs3_data_0_REG, _rrd_rs3_data_0_T node _rrd_rs3_data_0_T_1 = mux(rrd_rs3_data_0_REG, UInt<1>(0h0), io.rf_read_ports[2].data) connect rrd_rs3_data[0], _rrd_rs3_data_0_T_1 node _rrd_kill_T = and(io.brupdate.b1.mispredict_mask, rrd_uops[0].br_mask) node _rrd_kill_T_1 = neq(_rrd_kill_T, UInt<1>(0h0)) node rrd_kill = or(io.kill, _rrd_kill_T_1) node _exe_reg_valids_0_T = mux(rrd_kill, UInt<1>(0h0), rrd_valids[0]) connect exe_reg_valids[0], _exe_reg_valids_0_T wire exe_reg_uops_0_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate exe_reg_uops_0_uop.debug_tsrc invalidate exe_reg_uops_0_uop.debug_fsrc invalidate exe_reg_uops_0_uop.bp_xcpt_if invalidate exe_reg_uops_0_uop.bp_debug_if invalidate exe_reg_uops_0_uop.xcpt_ma_if invalidate exe_reg_uops_0_uop.xcpt_ae_if invalidate exe_reg_uops_0_uop.xcpt_pf_if invalidate exe_reg_uops_0_uop.fp_single invalidate exe_reg_uops_0_uop.fp_val invalidate exe_reg_uops_0_uop.frs3_en invalidate exe_reg_uops_0_uop.lrs2_rtype invalidate exe_reg_uops_0_uop.lrs1_rtype invalidate exe_reg_uops_0_uop.dst_rtype invalidate exe_reg_uops_0_uop.ldst_val invalidate exe_reg_uops_0_uop.lrs3 invalidate exe_reg_uops_0_uop.lrs2 invalidate exe_reg_uops_0_uop.lrs1 invalidate exe_reg_uops_0_uop.ldst invalidate exe_reg_uops_0_uop.ldst_is_rs1 invalidate exe_reg_uops_0_uop.flush_on_commit invalidate exe_reg_uops_0_uop.is_unique invalidate exe_reg_uops_0_uop.is_sys_pc2epc invalidate exe_reg_uops_0_uop.uses_stq invalidate exe_reg_uops_0_uop.uses_ldq invalidate exe_reg_uops_0_uop.is_amo invalidate exe_reg_uops_0_uop.is_fencei invalidate exe_reg_uops_0_uop.is_fence invalidate exe_reg_uops_0_uop.mem_signed invalidate exe_reg_uops_0_uop.mem_size invalidate exe_reg_uops_0_uop.mem_cmd invalidate exe_reg_uops_0_uop.bypassable invalidate exe_reg_uops_0_uop.exc_cause invalidate exe_reg_uops_0_uop.exception invalidate exe_reg_uops_0_uop.stale_pdst invalidate exe_reg_uops_0_uop.ppred_busy invalidate exe_reg_uops_0_uop.prs3_busy invalidate exe_reg_uops_0_uop.prs2_busy invalidate exe_reg_uops_0_uop.prs1_busy invalidate exe_reg_uops_0_uop.ppred invalidate exe_reg_uops_0_uop.prs3 invalidate exe_reg_uops_0_uop.prs2 invalidate exe_reg_uops_0_uop.prs1 invalidate exe_reg_uops_0_uop.pdst invalidate exe_reg_uops_0_uop.rxq_idx invalidate exe_reg_uops_0_uop.stq_idx invalidate exe_reg_uops_0_uop.ldq_idx invalidate exe_reg_uops_0_uop.rob_idx invalidate exe_reg_uops_0_uop.csr_addr invalidate exe_reg_uops_0_uop.imm_packed invalidate exe_reg_uops_0_uop.taken invalidate exe_reg_uops_0_uop.pc_lob invalidate exe_reg_uops_0_uop.edge_inst invalidate exe_reg_uops_0_uop.ftq_idx invalidate exe_reg_uops_0_uop.br_tag invalidate exe_reg_uops_0_uop.br_mask invalidate exe_reg_uops_0_uop.is_sfb invalidate exe_reg_uops_0_uop.is_jal invalidate exe_reg_uops_0_uop.is_jalr invalidate exe_reg_uops_0_uop.is_br invalidate exe_reg_uops_0_uop.iw_p2_poisoned invalidate exe_reg_uops_0_uop.iw_p1_poisoned invalidate exe_reg_uops_0_uop.iw_state invalidate exe_reg_uops_0_uop.ctrl.is_std invalidate exe_reg_uops_0_uop.ctrl.is_sta invalidate exe_reg_uops_0_uop.ctrl.is_load invalidate exe_reg_uops_0_uop.ctrl.csr_cmd invalidate exe_reg_uops_0_uop.ctrl.fcn_dw invalidate exe_reg_uops_0_uop.ctrl.op_fcn invalidate exe_reg_uops_0_uop.ctrl.imm_sel invalidate exe_reg_uops_0_uop.ctrl.op2_sel invalidate exe_reg_uops_0_uop.ctrl.op1_sel invalidate exe_reg_uops_0_uop.ctrl.br_type invalidate exe_reg_uops_0_uop.fu_code invalidate exe_reg_uops_0_uop.iq_type invalidate exe_reg_uops_0_uop.debug_pc invalidate exe_reg_uops_0_uop.is_rvc invalidate exe_reg_uops_0_uop.debug_inst invalidate exe_reg_uops_0_uop.inst invalidate exe_reg_uops_0_uop.uopc connect exe_reg_uops_0_uop.uopc, UInt<7>(0h0) connect exe_reg_uops_0_uop.bypassable, UInt<1>(0h0) connect exe_reg_uops_0_uop.fp_val, UInt<1>(0h0) connect exe_reg_uops_0_uop.uses_stq, UInt<1>(0h0) connect exe_reg_uops_0_uop.uses_ldq, UInt<1>(0h0) connect exe_reg_uops_0_uop.pdst, UInt<1>(0h0) connect exe_reg_uops_0_uop.dst_rtype, UInt<2>(0h2) wire exe_reg_uops_0_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate exe_reg_uops_0_cs.is_std invalidate exe_reg_uops_0_cs.is_sta invalidate exe_reg_uops_0_cs.is_load invalidate exe_reg_uops_0_cs.csr_cmd invalidate exe_reg_uops_0_cs.fcn_dw invalidate exe_reg_uops_0_cs.op_fcn invalidate exe_reg_uops_0_cs.imm_sel invalidate exe_reg_uops_0_cs.op2_sel invalidate exe_reg_uops_0_cs.op1_sel invalidate exe_reg_uops_0_cs.br_type connect exe_reg_uops_0_cs.br_type, UInt<4>(0h0) connect exe_reg_uops_0_cs.csr_cmd, UInt<3>(0h0) connect exe_reg_uops_0_cs.is_load, UInt<1>(0h0) connect exe_reg_uops_0_cs.is_sta, UInt<1>(0h0) connect exe_reg_uops_0_cs.is_std, UInt<1>(0h0) connect exe_reg_uops_0_uop.ctrl, exe_reg_uops_0_cs node _exe_reg_uops_0_T = mux(rrd_kill, exe_reg_uops_0_uop, rrd_uops[0]) connect exe_reg_uops[0], _exe_reg_uops_0_T node _exe_reg_uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _exe_reg_uops_0_br_mask_T_1 = and(rrd_uops[0].br_mask, _exe_reg_uops_0_br_mask_T) connect exe_reg_uops[0].br_mask, _exe_reg_uops_0_br_mask_T_1 wire bypassed_rs1_data : UInt<65>[1] wire bypassed_rs2_data : UInt<65>[1] wire bypassed_pred_data : UInt<1>[1] invalidate bypassed_pred_data[0] node _bypassed_rs1_data_0_T = mux(UInt<1>(0h0), UInt<65>(0h0), rrd_rs1_data[0]) connect bypassed_rs1_data[0], _bypassed_rs1_data_0_T node _bypassed_rs2_data_0_T = mux(UInt<1>(0h0), UInt<65>(0h0), rrd_rs2_data[0]) connect bypassed_rs2_data[0], _bypassed_rs2_data_0_T connect exe_reg_rs1_data[0], bypassed_rs1_data[0] connect exe_reg_rs2_data[0], bypassed_rs2_data[0] connect exe_reg_rs3_data[0], rrd_rs3_data[0] connect io.exe_reqs[0].valid, exe_reg_valids[0] invalidate io.exe_reqs[0].bits.kill invalidate io.exe_reqs[0].bits.pred_data invalidate io.exe_reqs[0].bits.rs3_data invalidate io.exe_reqs[0].bits.rs2_data invalidate io.exe_reqs[0].bits.rs1_data invalidate io.exe_reqs[0].bits.uop.debug_tsrc invalidate io.exe_reqs[0].bits.uop.debug_fsrc invalidate io.exe_reqs[0].bits.uop.bp_xcpt_if invalidate io.exe_reqs[0].bits.uop.bp_debug_if invalidate io.exe_reqs[0].bits.uop.xcpt_ma_if invalidate io.exe_reqs[0].bits.uop.xcpt_ae_if invalidate io.exe_reqs[0].bits.uop.xcpt_pf_if invalidate io.exe_reqs[0].bits.uop.fp_single invalidate io.exe_reqs[0].bits.uop.fp_val invalidate io.exe_reqs[0].bits.uop.frs3_en invalidate io.exe_reqs[0].bits.uop.lrs2_rtype invalidate io.exe_reqs[0].bits.uop.lrs1_rtype invalidate io.exe_reqs[0].bits.uop.dst_rtype invalidate io.exe_reqs[0].bits.uop.ldst_val invalidate io.exe_reqs[0].bits.uop.lrs3 invalidate io.exe_reqs[0].bits.uop.lrs2 invalidate io.exe_reqs[0].bits.uop.lrs1 invalidate io.exe_reqs[0].bits.uop.ldst invalidate io.exe_reqs[0].bits.uop.ldst_is_rs1 invalidate io.exe_reqs[0].bits.uop.flush_on_commit invalidate io.exe_reqs[0].bits.uop.is_unique invalidate io.exe_reqs[0].bits.uop.is_sys_pc2epc invalidate io.exe_reqs[0].bits.uop.uses_stq invalidate io.exe_reqs[0].bits.uop.uses_ldq invalidate io.exe_reqs[0].bits.uop.is_amo invalidate io.exe_reqs[0].bits.uop.is_fencei invalidate io.exe_reqs[0].bits.uop.is_fence invalidate io.exe_reqs[0].bits.uop.mem_signed invalidate io.exe_reqs[0].bits.uop.mem_size invalidate io.exe_reqs[0].bits.uop.mem_cmd invalidate io.exe_reqs[0].bits.uop.bypassable invalidate io.exe_reqs[0].bits.uop.exc_cause invalidate io.exe_reqs[0].bits.uop.exception invalidate io.exe_reqs[0].bits.uop.stale_pdst invalidate io.exe_reqs[0].bits.uop.ppred_busy invalidate io.exe_reqs[0].bits.uop.prs3_busy invalidate io.exe_reqs[0].bits.uop.prs2_busy invalidate io.exe_reqs[0].bits.uop.prs1_busy invalidate io.exe_reqs[0].bits.uop.ppred invalidate io.exe_reqs[0].bits.uop.prs3 invalidate io.exe_reqs[0].bits.uop.prs2 invalidate io.exe_reqs[0].bits.uop.prs1 invalidate io.exe_reqs[0].bits.uop.pdst invalidate io.exe_reqs[0].bits.uop.rxq_idx invalidate io.exe_reqs[0].bits.uop.stq_idx invalidate io.exe_reqs[0].bits.uop.ldq_idx invalidate io.exe_reqs[0].bits.uop.rob_idx invalidate io.exe_reqs[0].bits.uop.csr_addr invalidate io.exe_reqs[0].bits.uop.imm_packed invalidate io.exe_reqs[0].bits.uop.taken invalidate io.exe_reqs[0].bits.uop.pc_lob invalidate io.exe_reqs[0].bits.uop.edge_inst invalidate io.exe_reqs[0].bits.uop.ftq_idx invalidate io.exe_reqs[0].bits.uop.br_tag invalidate io.exe_reqs[0].bits.uop.br_mask invalidate io.exe_reqs[0].bits.uop.is_sfb invalidate io.exe_reqs[0].bits.uop.is_jal invalidate io.exe_reqs[0].bits.uop.is_jalr invalidate io.exe_reqs[0].bits.uop.is_br invalidate io.exe_reqs[0].bits.uop.iw_p2_poisoned invalidate io.exe_reqs[0].bits.uop.iw_p1_poisoned invalidate io.exe_reqs[0].bits.uop.iw_state invalidate io.exe_reqs[0].bits.uop.ctrl.is_std invalidate io.exe_reqs[0].bits.uop.ctrl.is_sta invalidate io.exe_reqs[0].bits.uop.ctrl.is_load invalidate io.exe_reqs[0].bits.uop.ctrl.csr_cmd invalidate io.exe_reqs[0].bits.uop.ctrl.fcn_dw invalidate io.exe_reqs[0].bits.uop.ctrl.op_fcn invalidate io.exe_reqs[0].bits.uop.ctrl.imm_sel invalidate io.exe_reqs[0].bits.uop.ctrl.op2_sel invalidate io.exe_reqs[0].bits.uop.ctrl.op1_sel invalidate io.exe_reqs[0].bits.uop.ctrl.br_type invalidate io.exe_reqs[0].bits.uop.fu_code invalidate io.exe_reqs[0].bits.uop.iq_type invalidate io.exe_reqs[0].bits.uop.debug_pc invalidate io.exe_reqs[0].bits.uop.is_rvc invalidate io.exe_reqs[0].bits.uop.debug_inst invalidate io.exe_reqs[0].bits.uop.inst invalidate io.exe_reqs[0].bits.uop.uopc connect io.exe_reqs[0].bits.uop, exe_reg_uops[0] connect io.exe_reqs[0].bits.rs1_data, exe_reg_rs1_data[0] connect io.exe_reqs[0].bits.rs2_data, exe_reg_rs2_data[0] connect io.exe_reqs[0].bits.rs3_data, exe_reg_rs3_data[0]	module RegisterRead_2( // @[register-read.scala:34:7] input clock, // @[register-read.scala:34:7] input reset, // @[register-read.scala:34:7] input io_iss_valids_0, // @[register-read.scala:47:14] input [6:0] io_iss_uops_0_uopc, // @[register-read.scala:47:14] input [31:0] io_iss_uops_0_inst, // @[register-read.scala:47:14] input [31:0] io_iss_uops_0_debug_inst, // @[register-read.scala:47:14] input io_iss_uops_0_is_rvc, // @[register-read.scala:47:14] input [39:0] io_iss_uops_0_debug_pc, // @[register-read.scala:47:14] input [2:0] io_iss_uops_0_iq_type, // @[register-read.scala:47:14] input [9:0] io_iss_uops_0_fu_code, // @[register-read.scala:47:14] input [3:0] io_iss_uops_0_ctrl_br_type, // @[register-read.scala:47:14] input [1:0] io_iss_uops_0_ctrl_op1_sel, // @[register-read.scala:47:14] input [2:0] io_iss_uops_0_ctrl_op2_sel, // @[register-read.scala:47:14] input [2:0] io_iss_uops_0_ctrl_imm_sel, // @[register-read.scala:47:14] input [4:0] io_iss_uops_0_ctrl_op_fcn, // @[register-read.scala:47:14] input io_iss_uops_0_ctrl_fcn_dw, // @[register-read.scala:47:14] input [2:0] io_iss_uops_0_ctrl_csr_cmd, // @[register-read.scala:47:14] input io_iss_uops_0_ctrl_is_load, // @[register-read.scala:47:14] input io_iss_uops_0_ctrl_is_sta, // @[register-read.scala:47:14] input io_iss_uops_0_ctrl_is_std, // @[register-read.scala:47:14] input [1:0] io_iss_uops_0_iw_state, // @[register-read.scala:47:14] input io_iss_uops_0_is_br, // @[register-read.scala:47:14] input io_iss_uops_0_is_jalr, // @[register-read.scala:47:14] input io_iss_uops_0_is_jal, // @[register-read.scala:47:14] input io_iss_uops_0_is_sfb, // @[register-read.scala:47:14] input [15:0] io_iss_uops_0_br_mask, // @[register-read.scala:47:14] input [3:0] io_iss_uops_0_br_tag, // @[register-read.scala:47:14] input [4:0] io_iss_uops_0_ftq_idx, // @[register-read.scala:47:14] input io_iss_uops_0_edge_inst, // @[register-read.scala:47:14] input [5:0] io_iss_uops_0_pc_lob, // @[register-read.scala:47:14] input io_iss_uops_0_taken, // @[register-read.scala:47:14] input [19:0] io_iss_uops_0_imm_packed, // @[register-read.scala:47:14] input [11:0] io_iss_uops_0_csr_addr, // @[register-read.scala:47:14] input [6:0] io_iss_uops_0_rob_idx, // @[register-read.scala:47:14] input [4:0] io_iss_uops_0_ldq_idx, // @[register-read.scala:47:14] input [4:0] io_iss_uops_0_stq_idx, // @[register-read.scala:47:14] input [1:0] io_iss_uops_0_rxq_idx, // @[register-read.scala:47:14] input [6:0] io_iss_uops_0_pdst, // @[register-read.scala:47:14] input [6:0] io_iss_uops_0_prs1, // @[register-read.scala:47:14] input [6:0] io_iss_uops_0_prs2, // @[register-read.scala:47:14] input [6:0] io_iss_uops_0_prs3, // @[register-read.scala:47:14] input [4:0] io_iss_uops_0_ppred, // @[register-read.scala:47:14] input io_iss_uops_0_prs1_busy, // @[register-read.scala:47:14] input io_iss_uops_0_prs2_busy, // @[register-read.scala:47:14] input io_iss_uops_0_prs3_busy, // @[register-read.scala:47:14] input io_iss_uops_0_ppred_busy, // @[register-read.scala:47:14] input [6:0] io_iss_uops_0_stale_pdst, // @[register-read.scala:47:14] input io_iss_uops_0_exception, // @[register-read.scala:47:14] input [63:0] io_iss_uops_0_exc_cause, // @[register-read.scala:47:14] input io_iss_uops_0_bypassable, // @[register-read.scala:47:14] input [4:0] io_iss_uops_0_mem_cmd, // @[register-read.scala:47:14] input [1:0] io_iss_uops_0_mem_size, // @[register-read.scala:47:14] input io_iss_uops_0_mem_signed, // @[register-read.scala:47:14] input io_iss_uops_0_is_fence, // @[register-read.scala:47:14] input io_iss_uops_0_is_fencei, // @[register-read.scala:47:14] input io_iss_uops_0_is_amo, // @[register-read.scala:47:14] input io_iss_uops_0_uses_ldq, // @[register-read.scala:47:14] input io_iss_uops_0_uses_stq, // @[register-read.scala:47:14] input io_iss_uops_0_is_sys_pc2epc, // @[register-read.scala:47:14] input io_iss_uops_0_is_unique, // @[register-read.scala:47:14] input io_iss_uops_0_flush_on_commit, // @[register-read.scala:47:14] input io_iss_uops_0_ldst_is_rs1, // @[register-read.scala:47:14] input [5:0] io_iss_uops_0_ldst, // @[register-read.scala:47:14] input [5:0] io_iss_uops_0_lrs1, // @[register-read.scala:47:14] input [5:0] io_iss_uops_0_lrs2, // @[register-read.scala:47:14] input [5:0] io_iss_uops_0_lrs3, // @[register-read.scala:47:14] input io_iss_uops_0_ldst_val, // @[register-read.scala:47:14] input [1:0] io_iss_uops_0_dst_rtype, // @[register-read.scala:47:14] input [1:0] io_iss_uops_0_lrs1_rtype, // @[register-read.scala:47:14] input [1:0] io_iss_uops_0_lrs2_rtype, // @[register-read.scala:47:14] input io_iss_uops_0_frs3_en, // @[register-read.scala:47:14] input io_iss_uops_0_fp_val, // @[register-read.scala:47:14] input io_iss_uops_0_fp_single, // @[register-read.scala:47:14] input io_iss_uops_0_xcpt_pf_if, // @[register-read.scala:47:14] input io_iss_uops_0_xcpt_ae_if, // @[register-read.scala:47:14] input io_iss_uops_0_xcpt_ma_if, // @[register-read.scala:47:14] input io_iss_uops_0_bp_debug_if, // @[register-read.scala:47:14] input io_iss_uops_0_bp_xcpt_if, // @[register-read.scala:47:14] input [1:0] io_iss_uops_0_debug_fsrc, // @[register-read.scala:47:14] input [1:0] io_iss_uops_0_debug_tsrc, // @[register-read.scala:47:14] output [6:0] io_rf_read_ports_0_addr, // @[register-read.scala:47:14] input [64:0] io_rf_read_ports_0_data, // @[register-read.scala:47:14] output [6:0] io_rf_read_ports_1_addr, // @[register-read.scala:47:14] input [64:0] io_rf_read_ports_1_data, // @[register-read.scala:47:14] output [6:0] io_rf_read_ports_2_addr, // @[register-read.scala:47:14] input [64:0] io_rf_read_ports_2_data, // @[register-read.scala:47:14] output io_exe_reqs_0_valid, // @[register-read.scala:47:14] output [6:0] io_exe_reqs_0_bits_uop_uopc, // @[register-read.scala:47:14] output [31:0] io_exe_reqs_0_bits_uop_inst, // @[register-read.scala:47:14] output [31:0] io_exe_reqs_0_bits_uop_debug_inst, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_is_rvc, // @[register-read.scala:47:14] output [39:0] io_exe_reqs_0_bits_uop_debug_pc, // @[register-read.scala:47:14] output [2:0] io_exe_reqs_0_bits_uop_iq_type, // @[register-read.scala:47:14] output [9:0] io_exe_reqs_0_bits_uop_fu_code, // @[register-read.scala:47:14] output [3:0] io_exe_reqs_0_bits_uop_ctrl_br_type, // @[register-read.scala:47:14] output [1:0] io_exe_reqs_0_bits_uop_ctrl_op1_sel, // @[register-read.scala:47:14] output [2:0] io_exe_reqs_0_bits_uop_ctrl_op2_sel, // @[register-read.scala:47:14] output [2:0] io_exe_reqs_0_bits_uop_ctrl_imm_sel, // @[register-read.scala:47:14] output [4:0] io_exe_reqs_0_bits_uop_ctrl_op_fcn, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_ctrl_fcn_dw, // @[register-read.scala:47:14] output [2:0] io_exe_reqs_0_bits_uop_ctrl_csr_cmd, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_ctrl_is_load, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_ctrl_is_sta, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_ctrl_is_std, // @[register-read.scala:47:14] output [1:0] io_exe_reqs_0_bits_uop_iw_state, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_iw_p1_poisoned, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_iw_p2_poisoned, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_is_br, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_is_jalr, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_is_jal, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_is_sfb, // @[register-read.scala:47:14] output [15:0] io_exe_reqs_0_bits_uop_br_mask, // @[register-read.scala:47:14] output [3:0] io_exe_reqs_0_bits_uop_br_tag, // @[register-read.scala:47:14] output [4:0] io_exe_reqs_0_bits_uop_ftq_idx, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_edge_inst, // @[register-read.scala:47:14] output [5:0] io_exe_reqs_0_bits_uop_pc_lob, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_taken, // @[register-read.scala:47:14] output [19:0] io_exe_reqs_0_bits_uop_imm_packed, // @[register-read.scala:47:14] output [11:0] io_exe_reqs_0_bits_uop_csr_addr, // @[register-read.scala:47:14] output [6:0] io_exe_reqs_0_bits_uop_rob_idx, // @[register-read.scala:47:14] output [4:0] io_exe_reqs_0_bits_uop_ldq_idx, // @[register-read.scala:47:14] output [4:0] io_exe_reqs_0_bits_uop_stq_idx, // @[register-read.scala:47:14] output [1:0] io_exe_reqs_0_bits_uop_rxq_idx, // @[register-read.scala:47:14] output [6:0] io_exe_reqs_0_bits_uop_pdst, // @[register-read.scala:47:14] output [6:0] io_exe_reqs_0_bits_uop_prs1, // @[register-read.scala:47:14] output [6:0] io_exe_reqs_0_bits_uop_prs2, // @[register-read.scala:47:14] output [6:0] io_exe_reqs_0_bits_uop_prs3, // @[register-read.scala:47:14] output [4:0] io_exe_reqs_0_bits_uop_ppred, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_prs1_busy, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_prs2_busy, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_prs3_busy, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_ppred_busy, // @[register-read.scala:47:14] output [6:0] io_exe_reqs_0_bits_uop_stale_pdst, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_exception, // @[register-read.scala:47:14] output [63:0] io_exe_reqs_0_bits_uop_exc_cause, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_bypassable, // @[register-read.scala:47:14] output [4:0] io_exe_reqs_0_bits_uop_mem_cmd, // @[register-read.scala:47:14] output [1:0] io_exe_reqs_0_bits_uop_mem_size, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_mem_signed, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_is_fence, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_is_fencei, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_is_amo, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_uses_ldq, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_uses_stq, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_is_sys_pc2epc, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_is_unique, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_flush_on_commit, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_ldst_is_rs1, // @[register-read.scala:47:14] output [5:0] io_exe_reqs_0_bits_uop_ldst, // @[register-read.scala:47:14] output [5:0] io_exe_reqs_0_bits_uop_lrs1, // @[register-read.scala:47:14] output [5:0] io_exe_reqs_0_bits_uop_lrs2, // @[register-read.scala:47:14] output [5:0] io_exe_reqs_0_bits_uop_lrs3, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_ldst_val, // @[register-read.scala:47:14] output [1:0] io_exe_reqs_0_bits_uop_dst_rtype, // @[register-read.scala:47:14] output [1:0] io_exe_reqs_0_bits_uop_lrs1_rtype, // @[register-read.scala:47:14] output [1:0] io_exe_reqs_0_bits_uop_lrs2_rtype, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_frs3_en, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_fp_val, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_fp_single, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_xcpt_pf_if, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_xcpt_ae_if, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_xcpt_ma_if, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_bp_debug_if, // @[register-read.scala:47:14] output io_exe_reqs_0_bits_uop_bp_xcpt_if, // @[register-read.scala:47:14] output [1:0] io_exe_reqs_0_bits_uop_debug_fsrc, // @[register-read.scala:47:14] output [1:0] io_exe_reqs_0_bits_uop_debug_tsrc, // @[register-read.scala:47:14] output [64:0] io_exe_reqs_0_bits_rs1_data, // @[register-read.scala:47:14] output [64:0] io_exe_reqs_0_bits_rs2_data, // @[register-read.scala:47:14] output [64:0] io_exe_reqs_0_bits_rs3_data, // @[register-read.scala:47:14] input io_kill, // @[register-read.scala:47:14] input [15:0] io_brupdate_b1_resolve_mask, // @[register-read.scala:47:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[register-read.scala:47:14] input [6:0] io_brupdate_b2_uop_uopc, // @[register-read.scala:47:14] input [31:0] io_brupdate_b2_uop_inst, // @[register-read.scala:47:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[register-read.scala:47:14] input io_brupdate_b2_uop_is_rvc, // @[register-read.scala:47:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[register-read.scala:47:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[register-read.scala:47:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[register-read.scala:47:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[register-read.scala:47:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[register-read.scala:47:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[register-read.scala:47:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[register-read.scala:47:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[register-read.scala:47:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[register-read.scala:47:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[register-read.scala:47:14] input io_brupdate_b2_uop_ctrl_is_load, // @[register-read.scala:47:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[register-read.scala:47:14] input io_brupdate_b2_uop_ctrl_is_std, // @[register-read.scala:47:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[register-read.scala:47:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[register-read.scala:47:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[register-read.scala:47:14] input io_brupdate_b2_uop_is_br, // @[register-read.scala:47:14] input io_brupdate_b2_uop_is_jalr, // @[register-read.scala:47:14] input io_brupdate_b2_uop_is_jal, // @[register-read.scala:47:14] input io_brupdate_b2_uop_is_sfb, // @[register-read.scala:47:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[register-read.scala:47:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[register-read.scala:47:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[register-read.scala:47:14] input io_brupdate_b2_uop_edge_inst, // @[register-read.scala:47:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[register-read.scala:47:14] input io_brupdate_b2_uop_taken, // @[register-read.scala:47:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[register-read.scala:47:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[register-read.scala:47:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[register-read.scala:47:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[register-read.scala:47:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[register-read.scala:47:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[register-read.scala:47:14] input [6:0] io_brupdate_b2_uop_pdst, // @[register-read.scala:47:14] input [6:0] io_brupdate_b2_uop_prs1, // @[register-read.scala:47:14] input [6:0] io_brupdate_b2_uop_prs2, // @[register-read.scala:47:14] input [6:0] io_brupdate_b2_uop_prs3, // @[register-read.scala:47:14] input [4:0] io_brupdate_b2_uop_ppred, // @[register-read.scala:47:14] input io_brupdate_b2_uop_prs1_busy, // @[register-read.scala:47:14] input io_brupdate_b2_uop_prs2_busy, // @[register-read.scala:47:14] input io_brupdate_b2_uop_prs3_busy, // @[register-read.scala:47:14] input io_brupdate_b2_uop_ppred_busy, // @[register-read.scala:47:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[register-read.scala:47:14] input io_brupdate_b2_uop_exception, // @[register-read.scala:47:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[register-read.scala:47:14] input io_brupdate_b2_uop_bypassable, // @[register-read.scala:47:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[register-read.scala:47:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[register-read.scala:47:14] input io_brupdate_b2_uop_mem_signed, // @[register-read.scala:47:14] input io_brupdate_b2_uop_is_fence, // @[register-read.scala:47:14] input io_brupdate_b2_uop_is_fencei, // @[register-read.scala:47:14] input io_brupdate_b2_uop_is_amo, // @[register-read.scala:47:14] input io_brupdate_b2_uop_uses_ldq, // @[register-read.scala:47:14] input io_brupdate_b2_uop_uses_stq, // @[register-read.scala:47:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[register-read.scala:47:14] input io_brupdate_b2_uop_is_unique, // @[register-read.scala:47:14] input io_brupdate_b2_uop_flush_on_commit, // @[register-read.scala:47:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[register-read.scala:47:14] input [5:0] io_brupdate_b2_uop_ldst, // @[register-read.scala:47:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[register-read.scala:47:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[register-read.scala:47:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[register-read.scala:47:14] input io_brupdate_b2_uop_ldst_val, // @[register-read.scala:47:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[register-read.scala:47:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[register-read.scala:47:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[register-read.scala:47:14] input io_brupdate_b2_uop_frs3_en, // @[register-read.scala:47:14] input io_brupdate_b2_uop_fp_val, // @[register-read.scala:47:14] input io_brupdate_b2_uop_fp_single, // @[register-read.scala:47:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[register-read.scala:47:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[register-read.scala:47:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[register-read.scala:47:14] input io_brupdate_b2_uop_bp_debug_if, // @[register-read.scala:47:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[register-read.scala:47:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[register-read.scala:47:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[register-read.scala:47:14] input io_brupdate_b2_valid, // @[register-read.scala:47:14] input io_brupdate_b2_mispredict, // @[register-read.scala:47:14] input io_brupdate_b2_taken, // @[register-read.scala:47:14] input [2:0] io_brupdate_b2_cfi_type, // @[register-read.scala:47:14] input [1:0] io_brupdate_b2_pc_sel, // @[register-read.scala:47:14] input [39:0] io_brupdate_b2_jalr_target, // @[register-read.scala:47:14] input [20:0] io_brupdate_b2_target_offset // @[register-read.scala:47:14] ); wire _rrd_decode_unit_io_rrd_valid; // @[register-read.scala:80:33] wire [15:0] _rrd_decode_unit_io_rrd_uop_br_mask; // @[register-read.scala:80:33] wire io_iss_valids_0_0 = io_iss_valids_0; // @[register-read.scala:34:7] wire [6:0] io_iss_uops_0_uopc_0 = io_iss_uops_0_uopc; // @[register-read.scala:34:7] wire [31:0] io_iss_uops_0_inst_0 = io_iss_uops_0_inst; // @[register-read.scala:34:7] wire [31:0] io_iss_uops_0_debug_inst_0 = io_iss_uops_0_debug_inst; // @[register-read.scala:34:7] wire io_iss_uops_0_is_rvc_0 = io_iss_uops_0_is_rvc; // @[register-read.scala:34:7] wire [39:0] io_iss_uops_0_debug_pc_0 = io_iss_uops_0_debug_pc; // @[register-read.scala:34:7] wire [2:0] io_iss_uops_0_iq_type_0 = io_iss_uops_0_iq_type; // @[register-read.scala:34:7] wire [9:0] io_iss_uops_0_fu_code_0 = io_iss_uops_0_fu_code; // @[register-read.scala:34:7] wire [3:0] io_iss_uops_0_ctrl_br_type_0 = io_iss_uops_0_ctrl_br_type; // @[register-read.scala:34:7] wire [1:0] io_iss_uops_0_ctrl_op1_sel_0 = io_iss_uops_0_ctrl_op1_sel; // @[register-read.scala:34:7] wire [2:0] io_iss_uops_0_ctrl_op2_sel_0 = io_iss_uops_0_ctrl_op2_sel; // @[register-read.scala:34:7] wire [2:0] io_iss_uops_0_ctrl_imm_sel_0 = io_iss_uops_0_ctrl_imm_sel; // @[register-read.scala:34:7] wire [4:0] io_iss_uops_0_ctrl_op_fcn_0 = io_iss_uops_0_ctrl_op_fcn; // @[register-read.scala:34:7] wire io_iss_uops_0_ctrl_fcn_dw_0 = io_iss_uops_0_ctrl_fcn_dw; // @[register-read.scala:34:7] wire [2:0] io_iss_uops_0_ctrl_csr_cmd_0 = io_iss_uops_0_ctrl_csr_cmd; // @[register-read.scala:34:7] wire io_iss_uops_0_ctrl_is_load_0 = io_iss_uops_0_ctrl_is_load; // @[register-read.scala:34:7] wire io_iss_uops_0_ctrl_is_sta_0 = io_iss_uops_0_ctrl_is_sta; // @[register-read.scala:34:7] wire io_iss_uops_0_ctrl_is_std_0 = io_iss_uops_0_ctrl_is_std; // @[register-read.scala:34:7] wire [1:0] io_iss_uops_0_iw_state_0 = io_iss_uops_0_iw_state; // @[register-read.scala:34:7] wire io_iss_uops_0_is_br_0 = io_iss_uops_0_is_br; // @[register-read.scala:34:7] wire io_iss_uops_0_is_jalr_0 = io_iss_uops_0_is_jalr; // @[register-read.scala:34:7] wire io_iss_uops_0_is_jal_0 = io_iss_uops_0_is_jal; // @[register-read.scala:34:7] wire io_iss_uops_0_is_sfb_0 = io_iss_uops_0_is_sfb; // @[register-read.scala:34:7] wire [15:0] io_iss_uops_0_br_mask_0 = io_iss_uops_0_br_mask; // @[register-read.scala:34:7] wire [3:0] io_iss_uops_0_br_tag_0 = io_iss_uops_0_br_tag; // @[register-read.scala:34:7] wire [4:0] io_iss_uops_0_ftq_idx_0 = io_iss_uops_0_ftq_idx; // @[register-read.scala:34:7] wire io_iss_uops_0_edge_inst_0 = io_iss_uops_0_edge_inst; // @[register-read.scala:34:7] wire [5:0] io_iss_uops_0_pc_lob_0 = io_iss_uops_0_pc_lob; // @[register-read.scala:34:7] wire io_iss_uops_0_taken_0 = io_iss_uops_0_taken; // @[register-read.scala:34:7] wire [19:0] io_iss_uops_0_imm_packed_0 = io_iss_uops_0_imm_packed; // @[register-read.scala:34:7] wire [11:0] io_iss_uops_0_csr_addr_0 = io_iss_uops_0_csr_addr; // @[register-read.scala:34:7] wire [6:0] io_iss_uops_0_rob_idx_0 = io_iss_uops_0_rob_idx; // @[register-read.scala:34:7] wire [4:0] io_iss_uops_0_ldq_idx_0 = io_iss_uops_0_ldq_idx; // @[register-read.scala:34:7] wire [4:0] io_iss_uops_0_stq_idx_0 = io_iss_uops_0_stq_idx; // @[register-read.scala:34:7] wire [1:0] io_iss_uops_0_rxq_idx_0 = io_iss_uops_0_rxq_idx; // @[register-read.scala:34:7] wire [6:0] io_iss_uops_0_pdst_0 = io_iss_uops_0_pdst; // @[register-read.scala:34:7] wire [6:0] io_iss_uops_0_prs1_0 = io_iss_uops_0_prs1; // @[register-read.scala:34:7] wire [6:0] io_iss_uops_0_prs2_0 = io_iss_uops_0_prs2; // @[register-read.scala:34:7] wire [6:0] io_iss_uops_0_prs3_0 = io_iss_uops_0_prs3; // @[register-read.scala:34:7] wire [4:0] io_iss_uops_0_ppred_0 = io_iss_uops_0_ppred; // @[register-read.scala:34:7] wire io_iss_uops_0_prs1_busy_0 = io_iss_uops_0_prs1_busy; // @[register-read.scala:34:7] wire io_iss_uops_0_prs2_busy_0 = io_iss_uops_0_prs2_busy; // @[register-read.scala:34:7] wire io_iss_uops_0_prs3_busy_0 = io_iss_uops_0_prs3_busy; // @[register-read.scala:34:7] wire io_iss_uops_0_ppred_busy_0 = io_iss_uops_0_ppred_busy; // @[register-read.scala:34:7] wire [6:0] io_iss_uops_0_stale_pdst_0 = io_iss_uops_0_stale_pdst; // @[register-read.scala:34:7] wire io_iss_uops_0_exception_0 = io_iss_uops_0_exception; // @[register-read.scala:34:7] wire [63:0] io_iss_uops_0_exc_cause_0 = io_iss_uops_0_exc_cause; // @[register-read.scala:34:7] wire io_iss_uops_0_bypassable_0 = io_iss_uops_0_bypassable; // @[register-read.scala:34:7] wire [4:0] io_iss_uops_0_mem_cmd_0 = io_iss_uops_0_mem_cmd; // @[register-read.scala:34:7] wire [1:0] io_iss_uops_0_mem_size_0 = io_iss_uops_0_mem_size; // @[register-read.scala:34:7] wire io_iss_uops_0_mem_signed_0 = io_iss_uops_0_mem_signed; // @[register-read.scala:34:7] wire io_iss_uops_0_is_fence_0 = io_iss_uops_0_is_fence; // @[register-read.scala:34:7] wire io_iss_uops_0_is_fencei_0 = io_iss_uops_0_is_fencei; // @[register-read.scala:34:7] wire io_iss_uops_0_is_amo_0 = io_iss_uops_0_is_amo; // @[register-read.scala:34:7] wire io_iss_uops_0_uses_ldq_0 = io_iss_uops_0_uses_ldq; // @[register-read.scala:34:7] wire io_iss_uops_0_uses_stq_0 = io_iss_uops_0_uses_stq; // @[register-read.scala:34:7] wire io_iss_uops_0_is_sys_pc2epc_0 = io_iss_uops_0_is_sys_pc2epc; // @[register-read.scala:34:7] wire io_iss_uops_0_is_unique_0 = io_iss_uops_0_is_unique; // @[register-read.scala:34:7] wire io_iss_uops_0_flush_on_commit_0 = io_iss_uops_0_flush_on_commit; // @[register-read.scala:34:7] wire io_iss_uops_0_ldst_is_rs1_0 = io_iss_uops_0_ldst_is_rs1; // @[register-read.scala:34:7] wire [5:0] io_iss_uops_0_ldst_0 = io_iss_uops_0_ldst; // @[register-read.scala:34:7] wire [5:0] io_iss_uops_0_lrs1_0 = io_iss_uops_0_lrs1; // @[register-read.scala:34:7] wire [5:0] io_iss_uops_0_lrs2_0 = io_iss_uops_0_lrs2; // @[register-read.scala:34:7] wire [5:0] io_iss_uops_0_lrs3_0 = io_iss_uops_0_lrs3; // @[register-read.scala:34:7] wire io_iss_uops_0_ldst_val_0 = io_iss_uops_0_ldst_val; // @[register-read.scala:34:7] wire [1:0] io_iss_uops_0_dst_rtype_0 = io_iss_uops_0_dst_rtype; // @[register-read.scala:34:7] wire [1:0] io_iss_uops_0_lrs1_rtype_0 = io_iss_uops_0_lrs1_rtype; // @[register-read.scala:34:7] wire [1:0] io_iss_uops_0_lrs2_rtype_0 = io_iss_uops_0_lrs2_rtype; // @[register-read.scala:34:7] wire io_iss_uops_0_frs3_en_0 = io_iss_uops_0_frs3_en; // @[register-read.scala:34:7] wire io_iss_uops_0_fp_val_0 = io_iss_uops_0_fp_val; // @[register-read.scala:34:7] wire io_iss_uops_0_fp_single_0 = io_iss_uops_0_fp_single; // @[register-read.scala:34:7] wire io_iss_uops_0_xcpt_pf_if_0 = io_iss_uops_0_xcpt_pf_if; // @[register-read.scala:34:7] wire io_iss_uops_0_xcpt_ae_if_0 = io_iss_uops_0_xcpt_ae_if; // @[register-read.scala:34:7] wire io_iss_uops_0_xcpt_ma_if_0 = io_iss_uops_0_xcpt_ma_if; // @[register-read.scala:34:7] wire io_iss_uops_0_bp_debug_if_0 = io_iss_uops_0_bp_debug_if; // @[register-read.scala:34:7] wire io_iss_uops_0_bp_xcpt_if_0 = io_iss_uops_0_bp_xcpt_if; // @[register-read.scala:34:7] wire [1:0] io_iss_uops_0_debug_fsrc_0 = io_iss_uops_0_debug_fsrc; // @[register-read.scala:34:7] wire [1:0] io_iss_uops_0_debug_tsrc_0 = io_iss_uops_0_debug_tsrc; // @[register-read.scala:34:7] wire [64:0] io_rf_read_ports_0_data_0 = io_rf_read_ports_0_data; // @[register-read.scala:34:7] wire [64:0] io_rf_read_ports_1_data_0 = io_rf_read_ports_1_data; // @[register-read.scala:34:7] wire [64:0] io_rf_read_ports_2_data_0 = io_rf_read_ports_2_data; // @[register-read.scala:34:7] wire io_kill_0 = io_kill; // @[register-read.scala:34:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[register-read.scala:34:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[register-read.scala:34:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[register-read.scala:34:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[register-read.scala:34:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[register-read.scala:34:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[register-read.scala:34:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[register-read.scala:34:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[register-read.scala:34:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[register-read.scala:34:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[register-read.scala:34:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[register-read.scala:34:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[register-read.scala:34:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[register-read.scala:34:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[register-read.scala:34:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[register-read.scala:34:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[register-read.scala:34:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[register-read.scala:34:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[register-read.scala:34:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[register-read.scala:34:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[register-read.scala:34:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[register-read.scala:34:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[register-read.scala:34:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[register-read.scala:34:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[register-read.scala:34:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[register-read.scala:34:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[register-read.scala:34:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[register-read.scala:34:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[register-read.scala:34:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[register-read.scala:34:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[register-read.scala:34:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[register-read.scala:34:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[register-read.scala:34:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[register-read.scala:34:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[register-read.scala:34:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[register-read.scala:34:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[register-read.scala:34:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[register-read.scala:34:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[register-read.scala:34:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[register-read.scala:34:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[register-read.scala:34:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[register-read.scala:34:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[register-read.scala:34:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[register-read.scala:34:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[register-read.scala:34:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[register-read.scala:34:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[register-read.scala:34:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[register-read.scala:34:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[register-read.scala:34:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[register-read.scala:34:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[register-read.scala:34:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[register-read.scala:34:7] wire [31:0] exe_reg_uops_0_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] exe_reg_uops_0_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [39:0] exe_reg_uops_0_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [9:0] exe_reg_uops_0_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [15:0] exe_reg_uops_0_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [19:0] exe_reg_uops_0_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [11:0] exe_reg_uops_0_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [6:0] exe_reg_uops_0_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_reg_uops_0_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_reg_uops_0_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_reg_uops_0_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_reg_uops_0_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_reg_uops_0_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] exe_reg_uops_0_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire [63:0] exe_reg_uops_0_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [5:0] exe_reg_uops_0_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_reg_uops_0_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_reg_uops_0_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_reg_uops_0_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] exe_reg_uops_0_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [1:0] exe_reg_uops_0_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [3:0] exe_reg_uops_0_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_reg_uops_0_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] exe_reg_uops_0_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] exe_reg_uops_0_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_reg_uops_0_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_reg_uops_0_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_reg_uops_0_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_reg_uops_0_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_reg_uops_0_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_reg_uops_0_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_reg_uops_0_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] exe_reg_uops_0_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] exe_reg_uops_0_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_reg_uops_0_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_reg_uops_0_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_reg_uops_0_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] exe_reg_uops_0_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_reg_uops_0_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] exe_reg_uops_0_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] io_prf_read_ports_0_addr = 5'h0; // @[register-read.scala:34:7] wire [4:0] exe_reg_uops_0_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_reg_uops_0_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_reg_uops_0_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_reg_uops_0_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_reg_uops_0_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_reg_uops_0_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] exe_reg_uops_0_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire io_iss_uops_0_iw_p1_poisoned = 1'h0; // @[register-read.scala:34:7] wire io_iss_uops_0_iw_p2_poisoned = 1'h0; // @[register-read.scala:34:7] wire io_prf_read_ports_0_data = 1'h0; // @[register-read.scala:34:7] wire io_exe_reqs_0_ready = 1'h0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_pred_data = 1'h0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_kill = 1'h0; // @[register-read.scala:34:7] wire _exe_reg_valids_WIRE_0 = 1'h0; // @[register-read.scala:69:41] wire rrd_uops_0_newuop_iw_p1_poisoned = 1'h0; // @[util.scala:73:26] wire rrd_uops_0_newuop_iw_p2_poisoned = 1'h0; // @[util.scala:73:26] wire rrd_pred_data_0 = 1'h0; // @[register-read.scala:97:28] wire exe_reg_uops_0_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_is_br = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_taken = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_exception = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire exe_reg_uops_0_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire exe_reg_uops_0_cs_is_load = 1'h0; // @[consts.scala:279:18] wire exe_reg_uops_0_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire exe_reg_uops_0_cs_is_std = 1'h0; // @[consts.scala:279:18] wire bypassed_pred_data_0 = 1'h0; // @[register-read.scala:154:32] wire [6:0] io_rf_read_ports_0_addr_0 = io_iss_uops_0_prs1_0; // @[register-read.scala:34:7] wire [6:0] io_rf_read_ports_1_addr_0 = io_iss_uops_0_prs2_0; // @[register-read.scala:34:7] wire [6:0] io_rf_read_ports_2_addr_0 = io_iss_uops_0_prs3_0; // @[register-read.scala:34:7] wire [3:0] io_exe_reqs_0_bits_uop_ctrl_br_type_0; // @[register-read.scala:34:7] wire [1:0] io_exe_reqs_0_bits_uop_ctrl_op1_sel_0; // @[register-read.scala:34:7] wire [2:0] io_exe_reqs_0_bits_uop_ctrl_op2_sel_0; // @[register-read.scala:34:7] wire [2:0] io_exe_reqs_0_bits_uop_ctrl_imm_sel_0; // @[register-read.scala:34:7] wire [4:0] io_exe_reqs_0_bits_uop_ctrl_op_fcn_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_ctrl_fcn_dw_0; // @[register-read.scala:34:7] wire [2:0] io_exe_reqs_0_bits_uop_ctrl_csr_cmd_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_ctrl_is_load_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_ctrl_is_sta_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_ctrl_is_std_0; // @[register-read.scala:34:7] wire [6:0] io_exe_reqs_0_bits_uop_uopc_0; // @[register-read.scala:34:7] wire [31:0] io_exe_reqs_0_bits_uop_inst_0; // @[register-read.scala:34:7] wire [31:0] io_exe_reqs_0_bits_uop_debug_inst_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_is_rvc_0; // @[register-read.scala:34:7] wire [39:0] io_exe_reqs_0_bits_uop_debug_pc_0; // @[register-read.scala:34:7] wire [2:0] io_exe_reqs_0_bits_uop_iq_type_0; // @[register-read.scala:34:7] wire [9:0] io_exe_reqs_0_bits_uop_fu_code_0; // @[register-read.scala:34:7] wire [1:0] io_exe_reqs_0_bits_uop_iw_state_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_iw_p1_poisoned_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_iw_p2_poisoned_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_is_br_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_is_jalr_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_is_jal_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_is_sfb_0; // @[register-read.scala:34:7] wire [15:0] io_exe_reqs_0_bits_uop_br_mask_0; // @[register-read.scala:34:7] wire [3:0] io_exe_reqs_0_bits_uop_br_tag_0; // @[register-read.scala:34:7] wire [4:0] io_exe_reqs_0_bits_uop_ftq_idx_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_edge_inst_0; // @[register-read.scala:34:7] wire [5:0] io_exe_reqs_0_bits_uop_pc_lob_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_taken_0; // @[register-read.scala:34:7] wire [19:0] io_exe_reqs_0_bits_uop_imm_packed_0; // @[register-read.scala:34:7] wire [11:0] io_exe_reqs_0_bits_uop_csr_addr_0; // @[register-read.scala:34:7] wire [6:0] io_exe_reqs_0_bits_uop_rob_idx_0; // @[register-read.scala:34:7] wire [4:0] io_exe_reqs_0_bits_uop_ldq_idx_0; // @[register-read.scala:34:7] wire [4:0] io_exe_reqs_0_bits_uop_stq_idx_0; // @[register-read.scala:34:7] wire [1:0] io_exe_reqs_0_bits_uop_rxq_idx_0; // @[register-read.scala:34:7] wire [6:0] io_exe_reqs_0_bits_uop_pdst_0; // @[register-read.scala:34:7] wire [6:0] io_exe_reqs_0_bits_uop_prs1_0; // @[register-read.scala:34:7] wire [6:0] io_exe_reqs_0_bits_uop_prs2_0; // @[register-read.scala:34:7] wire [6:0] io_exe_reqs_0_bits_uop_prs3_0; // @[register-read.scala:34:7] wire [4:0] io_exe_reqs_0_bits_uop_ppred_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_prs1_busy_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_prs2_busy_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_prs3_busy_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_ppred_busy_0; // @[register-read.scala:34:7] wire [6:0] io_exe_reqs_0_bits_uop_stale_pdst_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_exception_0; // @[register-read.scala:34:7] wire [63:0] io_exe_reqs_0_bits_uop_exc_cause_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_bypassable_0; // @[register-read.scala:34:7] wire [4:0] io_exe_reqs_0_bits_uop_mem_cmd_0; // @[register-read.scala:34:7] wire [1:0] io_exe_reqs_0_bits_uop_mem_size_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_mem_signed_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_is_fence_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_is_fencei_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_is_amo_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_uses_ldq_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_uses_stq_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_is_sys_pc2epc_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_is_unique_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_flush_on_commit_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_ldst_is_rs1_0; // @[register-read.scala:34:7] wire [5:0] io_exe_reqs_0_bits_uop_ldst_0; // @[register-read.scala:34:7] wire [5:0] io_exe_reqs_0_bits_uop_lrs1_0; // @[register-read.scala:34:7] wire [5:0] io_exe_reqs_0_bits_uop_lrs2_0; // @[register-read.scala:34:7] wire [5:0] io_exe_reqs_0_bits_uop_lrs3_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_ldst_val_0; // @[register-read.scala:34:7] wire [1:0] io_exe_reqs_0_bits_uop_dst_rtype_0; // @[register-read.scala:34:7] wire [1:0] io_exe_reqs_0_bits_uop_lrs1_rtype_0; // @[register-read.scala:34:7] wire [1:0] io_exe_reqs_0_bits_uop_lrs2_rtype_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_frs3_en_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_fp_val_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_fp_single_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_xcpt_pf_if_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_xcpt_ae_if_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_xcpt_ma_if_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_bp_debug_if_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_bits_uop_bp_xcpt_if_0; // @[register-read.scala:34:7] wire [1:0] io_exe_reqs_0_bits_uop_debug_fsrc_0; // @[register-read.scala:34:7] wire [1:0] io_exe_reqs_0_bits_uop_debug_tsrc_0; // @[register-read.scala:34:7] wire [64:0] io_exe_reqs_0_bits_rs1_data_0; // @[register-read.scala:34:7] wire [64:0] io_exe_reqs_0_bits_rs2_data_0; // @[register-read.scala:34:7] wire [64:0] io_exe_reqs_0_bits_rs3_data_0; // @[register-read.scala:34:7] wire io_exe_reqs_0_valid_0; // @[register-read.scala:34:7] wire rrd_valids_0; // @[register-read.scala:66:30] wire [3:0] rrd_uops_0_ctrl_br_type; // @[register-read.scala:67:30] wire [1:0] rrd_uops_0_ctrl_op1_sel; // @[register-read.scala:67:30] wire [2:0] rrd_uops_0_ctrl_op2_sel; // @[register-read.scala:67:30] wire [2:0] rrd_uops_0_ctrl_imm_sel; // @[register-read.scala:67:30] wire [4:0] rrd_uops_0_ctrl_op_fcn; // @[register-read.scala:67:30] wire rrd_uops_0_ctrl_fcn_dw; // @[register-read.scala:67:30] wire [2:0] rrd_uops_0_ctrl_csr_cmd; // @[register-read.scala:67:30] wire rrd_uops_0_ctrl_is_load; // @[register-read.scala:67:30] wire rrd_uops_0_ctrl_is_sta; // @[register-read.scala:67:30] wire rrd_uops_0_ctrl_is_std; // @[register-read.scala:67:30] wire [6:0] rrd_uops_0_uopc; // @[register-read.scala:67:30] wire [31:0] rrd_uops_0_inst; // @[register-read.scala:67:30] wire [31:0] rrd_uops_0_debug_inst; // @[register-read.scala:67:30] wire rrd_uops_0_is_rvc; // @[register-read.scala:67:30] wire [39:0] rrd_uops_0_debug_pc; // @[register-read.scala:67:30] wire [2:0] rrd_uops_0_iq_type; // @[register-read.scala:67:30] wire [9:0] rrd_uops_0_fu_code; // @[register-read.scala:67:30] wire [1:0] rrd_uops_0_iw_state; // @[register-read.scala:67:30] wire rrd_uops_0_iw_p1_poisoned; // @[register-read.scala:67:30] wire rrd_uops_0_iw_p2_poisoned; // @[register-read.scala:67:30] wire rrd_uops_0_is_br; // @[register-read.scala:67:30] wire rrd_uops_0_is_jalr; // @[register-read.scala:67:30] wire rrd_uops_0_is_jal; // @[register-read.scala:67:30] wire rrd_uops_0_is_sfb; // @[register-read.scala:67:30] wire [15:0] rrd_uops_0_br_mask; // @[register-read.scala:67:30] wire [3:0] rrd_uops_0_br_tag; // @[register-read.scala:67:30] wire [4:0] rrd_uops_0_ftq_idx; // @[register-read.scala:67:30] wire rrd_uops_0_edge_inst; // @[register-read.scala:67:30] wire [5:0] rrd_uops_0_pc_lob; // @[register-read.scala:67:30] wire rrd_uops_0_taken; // @[register-read.scala:67:30] wire [19:0] rrd_uops_0_imm_packed; // @[register-read.scala:67:30] wire [11:0] rrd_uops_0_csr_addr; // @[register-read.scala:67:30] wire [6:0] rrd_uops_0_rob_idx; // @[register-read.scala:67:30] wire [4:0] rrd_uops_0_ldq_idx; // @[register-read.scala:67:30] wire [4:0] rrd_uops_0_stq_idx; // @[register-read.scala:67:30] wire [1:0] rrd_uops_0_rxq_idx; // @[register-read.scala:67:30] wire [6:0] rrd_uops_0_pdst; // @[register-read.scala:67:30] wire [6:0] rrd_uops_0_prs1; // @[register-read.scala:67:30] wire [6:0] rrd_uops_0_prs2; // @[register-read.scala:67:30] wire [6:0] rrd_uops_0_prs3; // @[register-read.scala:67:30] wire [4:0] rrd_uops_0_ppred; // @[register-read.scala:67:30] wire rrd_uops_0_prs1_busy; // @[register-read.scala:67:30] wire rrd_uops_0_prs2_busy; // @[register-read.scala:67:30] wire rrd_uops_0_prs3_busy; // @[register-read.scala:67:30] wire rrd_uops_0_ppred_busy; // @[register-read.scala:67:30] wire [6:0] rrd_uops_0_stale_pdst; // @[register-read.scala:67:30] wire rrd_uops_0_exception; // @[register-read.scala:67:30] wire [63:0] rrd_uops_0_exc_cause; // @[register-read.scala:67:30] wire rrd_uops_0_bypassable; // @[register-read.scala:67:30] wire [4:0] rrd_uops_0_mem_cmd; // @[register-read.scala:67:30] wire [1:0] rrd_uops_0_mem_size; // @[register-read.scala:67:30] wire rrd_uops_0_mem_signed; // @[register-read.scala:67:30] wire rrd_uops_0_is_fence; // @[register-read.scala:67:30] wire rrd_uops_0_is_fencei; // @[register-read.scala:67:30] wire rrd_uops_0_is_amo; // @[register-read.scala:67:30] wire rrd_uops_0_uses_ldq; // @[register-read.scala:67:30] wire rrd_uops_0_uses_stq; // @[register-read.scala:67:30] wire rrd_uops_0_is_sys_pc2epc; // @[register-read.scala:67:30] wire rrd_uops_0_is_unique; // @[register-read.scala:67:30] wire rrd_uops_0_flush_on_commit; // @[register-read.scala:67:30] wire rrd_uops_0_ldst_is_rs1; // @[register-read.scala:67:30] wire [5:0] rrd_uops_0_ldst; // @[register-read.scala:67:30] wire [5:0] rrd_uops_0_lrs1; // @[register-read.scala:67:30] wire [5:0] rrd_uops_0_lrs2; // @[register-read.scala:67:30] wire [5:0] rrd_uops_0_lrs3; // @[register-read.scala:67:30] wire rrd_uops_0_ldst_val; // @[register-read.scala:67:30] wire [1:0] rrd_uops_0_dst_rtype; // @[register-read.scala:67:30] wire [1:0] rrd_uops_0_lrs1_rtype; // @[register-read.scala:67:30] wire [1:0] rrd_uops_0_lrs2_rtype; // @[register-read.scala:67:30] wire rrd_uops_0_frs3_en; // @[register-read.scala:67:30] wire rrd_uops_0_fp_val; // @[register-read.scala:67:30] wire rrd_uops_0_fp_single; // @[register-read.scala:67:30] wire rrd_uops_0_xcpt_pf_if; // @[register-read.scala:67:30] wire rrd_uops_0_xcpt_ae_if; // @[register-read.scala:67:30] wire rrd_uops_0_xcpt_ma_if; // @[register-read.scala:67:30] wire rrd_uops_0_bp_debug_if; // @[register-read.scala:67:30] wire rrd_uops_0_bp_xcpt_if; // @[register-read.scala:67:30] wire [1:0] rrd_uops_0_debug_fsrc; // @[register-read.scala:67:30] wire [1:0] rrd_uops_0_debug_tsrc; // @[register-read.scala:67:30] reg exe_reg_valids_0; // @[register-read.scala:69:33] assign io_exe_reqs_0_valid_0 = exe_reg_valids_0; // @[register-read.scala:34:7, :69:33] reg [6:0] exe_reg_uops_0_uopc; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_uopc_0 = exe_reg_uops_0_uopc; // @[register-read.scala:34:7, :70:29] reg [31:0] exe_reg_uops_0_inst; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_inst_0 = exe_reg_uops_0_inst; // @[register-read.scala:34:7, :70:29] reg [31:0] exe_reg_uops_0_debug_inst; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_debug_inst_0 = exe_reg_uops_0_debug_inst; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_is_rvc; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_is_rvc_0 = exe_reg_uops_0_is_rvc; // @[register-read.scala:34:7, :70:29] reg [39:0] exe_reg_uops_0_debug_pc; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_debug_pc_0 = exe_reg_uops_0_debug_pc; // @[register-read.scala:34:7, :70:29] reg [2:0] exe_reg_uops_0_iq_type; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_iq_type_0 = exe_reg_uops_0_iq_type; // @[register-read.scala:34:7, :70:29] reg [9:0] exe_reg_uops_0_fu_code; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_fu_code_0 = exe_reg_uops_0_fu_code; // @[register-read.scala:34:7, :70:29] reg [3:0] exe_reg_uops_0_ctrl_br_type; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ctrl_br_type_0 = exe_reg_uops_0_ctrl_br_type; // @[register-read.scala:34:7, :70:29] reg [1:0] exe_reg_uops_0_ctrl_op1_sel; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ctrl_op1_sel_0 = exe_reg_uops_0_ctrl_op1_sel; // @[register-read.scala:34:7, :70:29] reg [2:0] exe_reg_uops_0_ctrl_op2_sel; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ctrl_op2_sel_0 = exe_reg_uops_0_ctrl_op2_sel; // @[register-read.scala:34:7, :70:29] reg [2:0] exe_reg_uops_0_ctrl_imm_sel; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ctrl_imm_sel_0 = exe_reg_uops_0_ctrl_imm_sel; // @[register-read.scala:34:7, :70:29] reg [4:0] exe_reg_uops_0_ctrl_op_fcn; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ctrl_op_fcn_0 = exe_reg_uops_0_ctrl_op_fcn; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_ctrl_fcn_dw; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ctrl_fcn_dw_0 = exe_reg_uops_0_ctrl_fcn_dw; // @[register-read.scala:34:7, :70:29] reg [2:0] exe_reg_uops_0_ctrl_csr_cmd; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ctrl_csr_cmd_0 = exe_reg_uops_0_ctrl_csr_cmd; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_ctrl_is_load; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ctrl_is_load_0 = exe_reg_uops_0_ctrl_is_load; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_ctrl_is_sta; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ctrl_is_sta_0 = exe_reg_uops_0_ctrl_is_sta; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_ctrl_is_std; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ctrl_is_std_0 = exe_reg_uops_0_ctrl_is_std; // @[register-read.scala:34:7, :70:29] reg [1:0] exe_reg_uops_0_iw_state; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_iw_state_0 = exe_reg_uops_0_iw_state; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_iw_p1_poisoned; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_iw_p1_poisoned_0 = exe_reg_uops_0_iw_p1_poisoned; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_iw_p2_poisoned; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_iw_p2_poisoned_0 = exe_reg_uops_0_iw_p2_poisoned; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_is_br; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_is_br_0 = exe_reg_uops_0_is_br; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_is_jalr; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_is_jalr_0 = exe_reg_uops_0_is_jalr; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_is_jal; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_is_jal_0 = exe_reg_uops_0_is_jal; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_is_sfb; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_is_sfb_0 = exe_reg_uops_0_is_sfb; // @[register-read.scala:34:7, :70:29] reg [15:0] exe_reg_uops_0_br_mask; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_br_mask_0 = exe_reg_uops_0_br_mask; // @[register-read.scala:34:7, :70:29] reg [3:0] exe_reg_uops_0_br_tag; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_br_tag_0 = exe_reg_uops_0_br_tag; // @[register-read.scala:34:7, :70:29] reg [4:0] exe_reg_uops_0_ftq_idx; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ftq_idx_0 = exe_reg_uops_0_ftq_idx; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_edge_inst; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_edge_inst_0 = exe_reg_uops_0_edge_inst; // @[register-read.scala:34:7, :70:29] reg [5:0] exe_reg_uops_0_pc_lob; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_pc_lob_0 = exe_reg_uops_0_pc_lob; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_taken; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_taken_0 = exe_reg_uops_0_taken; // @[register-read.scala:34:7, :70:29] reg [19:0] exe_reg_uops_0_imm_packed; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_imm_packed_0 = exe_reg_uops_0_imm_packed; // @[register-read.scala:34:7, :70:29] reg [11:0] exe_reg_uops_0_csr_addr; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_csr_addr_0 = exe_reg_uops_0_csr_addr; // @[register-read.scala:34:7, :70:29] reg [6:0] exe_reg_uops_0_rob_idx; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_rob_idx_0 = exe_reg_uops_0_rob_idx; // @[register-read.scala:34:7, :70:29] reg [4:0] exe_reg_uops_0_ldq_idx; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ldq_idx_0 = exe_reg_uops_0_ldq_idx; // @[register-read.scala:34:7, :70:29] reg [4:0] exe_reg_uops_0_stq_idx; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_stq_idx_0 = exe_reg_uops_0_stq_idx; // @[register-read.scala:34:7, :70:29] reg [1:0] exe_reg_uops_0_rxq_idx; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_rxq_idx_0 = exe_reg_uops_0_rxq_idx; // @[register-read.scala:34:7, :70:29] reg [6:0] exe_reg_uops_0_pdst; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_pdst_0 = exe_reg_uops_0_pdst; // @[register-read.scala:34:7, :70:29] reg [6:0] exe_reg_uops_0_prs1; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_prs1_0 = exe_reg_uops_0_prs1; // @[register-read.scala:34:7, :70:29] reg [6:0] exe_reg_uops_0_prs2; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_prs2_0 = exe_reg_uops_0_prs2; // @[register-read.scala:34:7, :70:29] reg [6:0] exe_reg_uops_0_prs3; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_prs3_0 = exe_reg_uops_0_prs3; // @[register-read.scala:34:7, :70:29] reg [4:0] exe_reg_uops_0_ppred; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ppred_0 = exe_reg_uops_0_ppred; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_prs1_busy; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_prs1_busy_0 = exe_reg_uops_0_prs1_busy; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_prs2_busy; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_prs2_busy_0 = exe_reg_uops_0_prs2_busy; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_prs3_busy; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_prs3_busy_0 = exe_reg_uops_0_prs3_busy; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_ppred_busy; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ppred_busy_0 = exe_reg_uops_0_ppred_busy; // @[register-read.scala:34:7, :70:29] reg [6:0] exe_reg_uops_0_stale_pdst; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_stale_pdst_0 = exe_reg_uops_0_stale_pdst; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_exception; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_exception_0 = exe_reg_uops_0_exception; // @[register-read.scala:34:7, :70:29] reg [63:0] exe_reg_uops_0_exc_cause; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_exc_cause_0 = exe_reg_uops_0_exc_cause; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_bypassable; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_bypassable_0 = exe_reg_uops_0_bypassable; // @[register-read.scala:34:7, :70:29] reg [4:0] exe_reg_uops_0_mem_cmd; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_mem_cmd_0 = exe_reg_uops_0_mem_cmd; // @[register-read.scala:34:7, :70:29] reg [1:0] exe_reg_uops_0_mem_size; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_mem_size_0 = exe_reg_uops_0_mem_size; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_mem_signed; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_mem_signed_0 = exe_reg_uops_0_mem_signed; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_is_fence; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_is_fence_0 = exe_reg_uops_0_is_fence; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_is_fencei; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_is_fencei_0 = exe_reg_uops_0_is_fencei; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_is_amo; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_is_amo_0 = exe_reg_uops_0_is_amo; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_uses_ldq; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_uses_ldq_0 = exe_reg_uops_0_uses_ldq; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_uses_stq; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_uses_stq_0 = exe_reg_uops_0_uses_stq; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_is_sys_pc2epc; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_is_sys_pc2epc_0 = exe_reg_uops_0_is_sys_pc2epc; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_is_unique; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_is_unique_0 = exe_reg_uops_0_is_unique; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_flush_on_commit; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_flush_on_commit_0 = exe_reg_uops_0_flush_on_commit; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_ldst_is_rs1; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ldst_is_rs1_0 = exe_reg_uops_0_ldst_is_rs1; // @[register-read.scala:34:7, :70:29] reg [5:0] exe_reg_uops_0_ldst; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ldst_0 = exe_reg_uops_0_ldst; // @[register-read.scala:34:7, :70:29] reg [5:0] exe_reg_uops_0_lrs1; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_lrs1_0 = exe_reg_uops_0_lrs1; // @[register-read.scala:34:7, :70:29] reg [5:0] exe_reg_uops_0_lrs2; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_lrs2_0 = exe_reg_uops_0_lrs2; // @[register-read.scala:34:7, :70:29] reg [5:0] exe_reg_uops_0_lrs3; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_lrs3_0 = exe_reg_uops_0_lrs3; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_ldst_val; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_ldst_val_0 = exe_reg_uops_0_ldst_val; // @[register-read.scala:34:7, :70:29] reg [1:0] exe_reg_uops_0_dst_rtype; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_dst_rtype_0 = exe_reg_uops_0_dst_rtype; // @[register-read.scala:34:7, :70:29] reg [1:0] exe_reg_uops_0_lrs1_rtype; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_lrs1_rtype_0 = exe_reg_uops_0_lrs1_rtype; // @[register-read.scala:34:7, :70:29] reg [1:0] exe_reg_uops_0_lrs2_rtype; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_lrs2_rtype_0 = exe_reg_uops_0_lrs2_rtype; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_frs3_en; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_frs3_en_0 = exe_reg_uops_0_frs3_en; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_fp_val; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_fp_val_0 = exe_reg_uops_0_fp_val; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_fp_single; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_fp_single_0 = exe_reg_uops_0_fp_single; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_xcpt_pf_if; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_xcpt_pf_if_0 = exe_reg_uops_0_xcpt_pf_if; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_xcpt_ae_if; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_xcpt_ae_if_0 = exe_reg_uops_0_xcpt_ae_if; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_xcpt_ma_if; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_xcpt_ma_if_0 = exe_reg_uops_0_xcpt_ma_if; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_bp_debug_if; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_bp_debug_if_0 = exe_reg_uops_0_bp_debug_if; // @[register-read.scala:34:7, :70:29] reg exe_reg_uops_0_bp_xcpt_if; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_bp_xcpt_if_0 = exe_reg_uops_0_bp_xcpt_if; // @[register-read.scala:34:7, :70:29] reg [1:0] exe_reg_uops_0_debug_fsrc; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_debug_fsrc_0 = exe_reg_uops_0_debug_fsrc; // @[register-read.scala:34:7, :70:29] reg [1:0] exe_reg_uops_0_debug_tsrc; // @[register-read.scala:70:29] assign io_exe_reqs_0_bits_uop_debug_tsrc_0 = exe_reg_uops_0_debug_tsrc; // @[register-read.scala:34:7, :70:29] reg [64:0] exe_reg_rs1_data_0; // @[register-read.scala:71:29] assign io_exe_reqs_0_bits_rs1_data_0 = exe_reg_rs1_data_0; // @[register-read.scala:34:7, :71:29] reg [64:0] exe_reg_rs2_data_0; // @[register-read.scala:72:29] assign io_exe_reqs_0_bits_rs2_data_0 = exe_reg_rs2_data_0; // @[register-read.scala:34:7, :72:29] reg [64:0] exe_reg_rs3_data_0; // @[register-read.scala:73:29] assign io_exe_reqs_0_bits_rs3_data_0 = exe_reg_rs3_data_0; // @[register-read.scala:34:7, :73:29] wire [15:0] _rrd_valids_0_T = io_brupdate_b1_mispredict_mask_0 & _rrd_decode_unit_io_rrd_uop_br_mask; // @[util.scala:118:51] wire _rrd_valids_0_T_1 = \|_rrd_valids_0_T; // @[util.scala:118:{51,59}] wire _rrd_valids_0_T_2 = ~_rrd_valids_0_T_1; // @[util.scala:118:59] wire _rrd_valids_0_T_3 = _rrd_decode_unit_io_rrd_valid & _rrd_valids_0_T_2; // @[register-read.scala:80:33, :84:59, :85:17] reg rrd_valids_0_REG; // @[register-read.scala:84:29] assign rrd_valids_0 = rrd_valids_0_REG; // @[register-read.scala:66:30, :84:29] wire [15:0] _rrd_uops_0_newuop_br_mask_T_1; // @[util.scala:74:35] wire [3:0] rrd_uops_0_newuop_ctrl_br_type; // @[util.scala:73:26] wire [1:0] rrd_uops_0_newuop_ctrl_op1_sel; // @[util.scala:73:26] wire [2:0] rrd_uops_0_newuop_ctrl_op2_sel; // @[util.scala:73:26] wire [2:0] rrd_uops_0_newuop_ctrl_imm_sel; // @[util.scala:73:26] wire [4:0] rrd_uops_0_newuop_ctrl_op_fcn; // @[util.scala:73:26] wire rrd_uops_0_newuop_ctrl_fcn_dw; // @[util.scala:73:26] wire [2:0] rrd_uops_0_newuop_ctrl_csr_cmd; // @[util.scala:73:26] wire rrd_uops_0_newuop_ctrl_is_load; // @[util.scala:73:26] wire rrd_uops_0_newuop_ctrl_is_sta; // @[util.scala:73:26] wire rrd_uops_0_newuop_ctrl_is_std; // @[util.scala:73:26] wire [6:0] rrd_uops_0_newuop_uopc; // @[util.scala:73:26] wire [31:0] rrd_uops_0_newuop_inst; // @[util.scala:73:26] wire [31:0] rrd_uops_0_newuop_debug_inst; // @[util.scala:73:26] wire rrd_uops_0_newuop_is_rvc; // @[util.scala:73:26] wire [39:0] rrd_uops_0_newuop_debug_pc; // @[util.scala:73:26] wire [2:0] rrd_uops_0_newuop_iq_type; // @[util.scala:73:26] wire [9:0] rrd_uops_0_newuop_fu_code; // @[util.scala:73:26] wire [1:0] rrd_uops_0_newuop_iw_state; // @[util.scala:73:26] wire rrd_uops_0_newuop_is_br; // @[util.scala:73:26] wire rrd_uops_0_newuop_is_jalr; // @[util.scala:73:26] wire rrd_uops_0_newuop_is_jal; // @[util.scala:73:26] wire rrd_uops_0_newuop_is_sfb; // @[util.scala:73:26] wire [15:0] rrd_uops_0_newuop_br_mask; // @[util.scala:73:26] wire [3:0] rrd_uops_0_newuop_br_tag; // @[util.scala:73:26] wire [4:0] rrd_uops_0_newuop_ftq_idx; // @[util.scala:73:26] wire rrd_uops_0_newuop_edge_inst; // @[util.scala:73:26] wire [5:0] rrd_uops_0_newuop_pc_lob; // @[util.scala:73:26] wire rrd_uops_0_newuop_taken; // @[util.scala:73:26] wire [19:0] rrd_uops_0_newuop_imm_packed; // @[util.scala:73:26] wire [11:0] rrd_uops_0_newuop_csr_addr; // @[util.scala:73:26] wire [6:0] rrd_uops_0_newuop_rob_idx; // @[util.scala:73:26] wire [4:0] rrd_uops_0_newuop_ldq_idx; // @[util.scala:73:26] wire [4:0] rrd_uops_0_newuop_stq_idx; // @[util.scala:73:26] wire [1:0] rrd_uops_0_newuop_rxq_idx; // @[util.scala:73:26] wire [6:0] rrd_uops_0_newuop_pdst; // @[util.scala:73:26] wire [6:0] rrd_uops_0_newuop_prs1; // @[util.scala:73:26] wire [6:0] rrd_uops_0_newuop_prs2; // @[util.scala:73:26] wire [6:0] rrd_uops_0_newuop_prs3; // @[util.scala:73:26] wire [4:0] rrd_uops_0_newuop_ppred; // @[util.scala:73:26] wire rrd_uops_0_newuop_prs1_busy; // @[util.scala:73:26] wire rrd_uops_0_newuop_prs2_busy; // @[util.scala:73:26] wire rrd_uops_0_newuop_prs3_busy; // @[util.scala:73:26] wire rrd_uops_0_newuop_ppred_busy; // @[util.scala:73:26] wire [6:0] rrd_uops_0_newuop_stale_pdst; // @[util.scala:73:26] wire rrd_uops_0_newuop_exception; // @[util.scala:73:26] wire [63:0] rrd_uops_0_newuop_exc_cause; // @[util.scala:73:26] wire rrd_uops_0_newuop_bypassable; // @[util.scala:73:26] wire [4:0] rrd_uops_0_newuop_mem_cmd; // @[util.scala:73:26] wire [1:0] rrd_uops_0_newuop_mem_size; // @[util.scala:73:26] wire rrd_uops_0_newuop_mem_signed; // @[util.scala:73:26] wire rrd_uops_0_newuop_is_fence; // @[util.scala:73:26] wire rrd_uops_0_newuop_is_fencei; // @[util.scala:73:26] wire rrd_uops_0_newuop_is_amo; // @[util.scala:73:26] wire rrd_uops_0_newuop_uses_ldq; // @[util.scala:73:26] wire rrd_uops_0_newuop_uses_stq; // @[util.scala:73:26] wire rrd_uops_0_newuop_is_sys_pc2epc; // @[util.scala:73:26] wire rrd_uops_0_newuop_is_unique; // @[util.scala:73:26] wire rrd_uops_0_newuop_flush_on_commit; // @[util.scala:73:26] wire rrd_uops_0_newuop_ldst_is_rs1; // @[util.scala:73:26] wire [5:0] rrd_uops_0_newuop_ldst; // @[util.scala:73:26] wire [5:0] rrd_uops_0_newuop_lrs1; // @[util.scala:73:26] wire [5:0] rrd_uops_0_newuop_lrs2; // @[util.scala:73:26] wire [5:0] rrd_uops_0_newuop_lrs3; // @[util.scala:73:26] wire rrd_uops_0_newuop_ldst_val; // @[util.scala:73:26] wire [1:0] rrd_uops_0_newuop_dst_rtype; // @[util.scala:73:26] wire [1:0] rrd_uops_0_newuop_lrs1_rtype; // @[util.scala:73:26] wire [1:0] rrd_uops_0_newuop_lrs2_rtype; // @[util.scala:73:26] wire rrd_uops_0_newuop_frs3_en; // @[util.scala:73:26] wire rrd_uops_0_newuop_fp_val; // @[util.scala:73:26] wire rrd_uops_0_newuop_fp_single; // @[util.scala:73:26] wire rrd_uops_0_newuop_xcpt_pf_if; // @[util.scala:73:26] wire rrd_uops_0_newuop_xcpt_ae_if; // @[util.scala:73:26] wire rrd_uops_0_newuop_xcpt_ma_if; // @[util.scala:73:26] wire rrd_uops_0_newuop_bp_debug_if; // @[util.scala:73:26] wire rrd_uops_0_newuop_bp_xcpt_if; // @[util.scala:73:26] wire [1:0] rrd_uops_0_newuop_debug_fsrc; // @[util.scala:73:26] wire [1:0] rrd_uops_0_newuop_debug_tsrc; // @[util.scala:73:26] wire [15:0] _rrd_uops_0_newuop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:74:37] assign _rrd_uops_0_newuop_br_mask_T_1 = _rrd_decode_unit_io_rrd_uop_br_mask & _rrd_uops_0_newuop_br_mask_T; // @[util.scala:74:{35,37}] assign rrd_uops_0_newuop_br_mask = _rrd_uops_0_newuop_br_mask_T_1; // @[util.scala:73:26, :74:35] reg [6:0] rrd_uops_0_REG_uopc; // @[register-read.scala:86:29] assign rrd_uops_0_uopc = rrd_uops_0_REG_uopc; // @[register-read.scala:67:30, :86:29] reg [31:0] rrd_uops_0_REG_inst; // @[register-read.scala:86:29] assign rrd_uops_0_inst = rrd_uops_0_REG_inst; // @[register-read.scala:67:30, :86:29] reg [31:0] rrd_uops_0_REG_debug_inst; // @[register-read.scala:86:29] assign rrd_uops_0_debug_inst = rrd_uops_0_REG_debug_inst; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_is_rvc; // @[register-read.scala:86:29] assign rrd_uops_0_is_rvc = rrd_uops_0_REG_is_rvc; // @[register-read.scala:67:30, :86:29] reg [39:0] rrd_uops_0_REG_debug_pc; // @[register-read.scala:86:29] assign rrd_uops_0_debug_pc = rrd_uops_0_REG_debug_pc; // @[register-read.scala:67:30, :86:29] reg [2:0] rrd_uops_0_REG_iq_type; // @[register-read.scala:86:29] assign rrd_uops_0_iq_type = rrd_uops_0_REG_iq_type; // @[register-read.scala:67:30, :86:29] reg [9:0] rrd_uops_0_REG_fu_code; // @[register-read.scala:86:29] assign rrd_uops_0_fu_code = rrd_uops_0_REG_fu_code; // @[register-read.scala:67:30, :86:29] reg [3:0] rrd_uops_0_REG_ctrl_br_type; // @[register-read.scala:86:29] assign rrd_uops_0_ctrl_br_type = rrd_uops_0_REG_ctrl_br_type; // @[register-read.scala:67:30, :86:29] reg [1:0] rrd_uops_0_REG_ctrl_op1_sel; // @[register-read.scala:86:29] assign rrd_uops_0_ctrl_op1_sel = rrd_uops_0_REG_ctrl_op1_sel; // @[register-read.scala:67:30, :86:29] reg [2:0] rrd_uops_0_REG_ctrl_op2_sel; // @[register-read.scala:86:29] assign rrd_uops_0_ctrl_op2_sel = rrd_uops_0_REG_ctrl_op2_sel; // @[register-read.scala:67:30, :86:29] reg [2:0] rrd_uops_0_REG_ctrl_imm_sel; // @[register-read.scala:86:29] assign rrd_uops_0_ctrl_imm_sel = rrd_uops_0_REG_ctrl_imm_sel; // @[register-read.scala:67:30, :86:29] reg [4:0] rrd_uops_0_REG_ctrl_op_fcn; // @[register-read.scala:86:29] assign rrd_uops_0_ctrl_op_fcn = rrd_uops_0_REG_ctrl_op_fcn; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_ctrl_fcn_dw; // @[register-read.scala:86:29] assign rrd_uops_0_ctrl_fcn_dw = rrd_uops_0_REG_ctrl_fcn_dw; // @[register-read.scala:67:30, :86:29] reg [2:0] rrd_uops_0_REG_ctrl_csr_cmd; // @[register-read.scala:86:29] assign rrd_uops_0_ctrl_csr_cmd = rrd_uops_0_REG_ctrl_csr_cmd; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_ctrl_is_load; // @[register-read.scala:86:29] assign rrd_uops_0_ctrl_is_load = rrd_uops_0_REG_ctrl_is_load; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_ctrl_is_sta; // @[register-read.scala:86:29] assign rrd_uops_0_ctrl_is_sta = rrd_uops_0_REG_ctrl_is_sta; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_ctrl_is_std; // @[register-read.scala:86:29] assign rrd_uops_0_ctrl_is_std = rrd_uops_0_REG_ctrl_is_std; // @[register-read.scala:67:30, :86:29] reg [1:0] rrd_uops_0_REG_iw_state; // @[register-read.scala:86:29] assign rrd_uops_0_iw_state = rrd_uops_0_REG_iw_state; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_iw_p1_poisoned; // @[register-read.scala:86:29] assign rrd_uops_0_iw_p1_poisoned = rrd_uops_0_REG_iw_p1_poisoned; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_iw_p2_poisoned; // @[register-read.scala:86:29] assign rrd_uops_0_iw_p2_poisoned = rrd_uops_0_REG_iw_p2_poisoned; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_is_br; // @[register-read.scala:86:29] assign rrd_uops_0_is_br = rrd_uops_0_REG_is_br; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_is_jalr; // @[register-read.scala:86:29] assign rrd_uops_0_is_jalr = rrd_uops_0_REG_is_jalr; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_is_jal; // @[register-read.scala:86:29] assign rrd_uops_0_is_jal = rrd_uops_0_REG_is_jal; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_is_sfb; // @[register-read.scala:86:29] assign rrd_uops_0_is_sfb = rrd_uops_0_REG_is_sfb; // @[register-read.scala:67:30, :86:29] reg [15:0] rrd_uops_0_REG_br_mask; // @[register-read.scala:86:29] assign rrd_uops_0_br_mask = rrd_uops_0_REG_br_mask; // @[register-read.scala:67:30, :86:29] reg [3:0] rrd_uops_0_REG_br_tag; // @[register-read.scala:86:29] assign rrd_uops_0_br_tag = rrd_uops_0_REG_br_tag; // @[register-read.scala:67:30, :86:29] reg [4:0] rrd_uops_0_REG_ftq_idx; // @[register-read.scala:86:29] assign rrd_uops_0_ftq_idx = rrd_uops_0_REG_ftq_idx; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_edge_inst; // @[register-read.scala:86:29] assign rrd_uops_0_edge_inst = rrd_uops_0_REG_edge_inst; // @[register-read.scala:67:30, :86:29] reg [5:0] rrd_uops_0_REG_pc_lob; // @[register-read.scala:86:29] assign rrd_uops_0_pc_lob = rrd_uops_0_REG_pc_lob; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_taken; // @[register-read.scala:86:29] assign rrd_uops_0_taken = rrd_uops_0_REG_taken; // @[register-read.scala:67:30, :86:29] reg [19:0] rrd_uops_0_REG_imm_packed; // @[register-read.scala:86:29] assign rrd_uops_0_imm_packed = rrd_uops_0_REG_imm_packed; // @[register-read.scala:67:30, :86:29] reg [11:0] rrd_uops_0_REG_csr_addr; // @[register-read.scala:86:29] assign rrd_uops_0_csr_addr = rrd_uops_0_REG_csr_addr; // @[register-read.scala:67:30, :86:29] reg [6:0] rrd_uops_0_REG_rob_idx; // @[register-read.scala:86:29] assign rrd_uops_0_rob_idx = rrd_uops_0_REG_rob_idx; // @[register-read.scala:67:30, :86:29] reg [4:0] rrd_uops_0_REG_ldq_idx; // @[register-read.scala:86:29] assign rrd_uops_0_ldq_idx = rrd_uops_0_REG_ldq_idx; // @[register-read.scala:67:30, :86:29] reg [4:0] rrd_uops_0_REG_stq_idx; // @[register-read.scala:86:29] assign rrd_uops_0_stq_idx = rrd_uops_0_REG_stq_idx; // @[register-read.scala:67:30, :86:29] reg [1:0] rrd_uops_0_REG_rxq_idx; // @[register-read.scala:86:29] assign rrd_uops_0_rxq_idx = rrd_uops_0_REG_rxq_idx; // @[register-read.scala:67:30, :86:29] reg [6:0] rrd_uops_0_REG_pdst; // @[register-read.scala:86:29] assign rrd_uops_0_pdst = rrd_uops_0_REG_pdst; // @[register-read.scala:67:30, :86:29] reg [6:0] rrd_uops_0_REG_prs1; // @[register-read.scala:86:29] assign rrd_uops_0_prs1 = rrd_uops_0_REG_prs1; // @[register-read.scala:67:30, :86:29] reg [6:0] rrd_uops_0_REG_prs2; // @[register-read.scala:86:29] assign rrd_uops_0_prs2 = rrd_uops_0_REG_prs2; // @[register-read.scala:67:30, :86:29] reg [6:0] rrd_uops_0_REG_prs3; // @[register-read.scala:86:29] assign rrd_uops_0_prs3 = rrd_uops_0_REG_prs3; // @[register-read.scala:67:30, :86:29] reg [4:0] rrd_uops_0_REG_ppred; // @[register-read.scala:86:29] assign rrd_uops_0_ppred = rrd_uops_0_REG_ppred; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_prs1_busy; // @[register-read.scala:86:29] assign rrd_uops_0_prs1_busy = rrd_uops_0_REG_prs1_busy; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_prs2_busy; // @[register-read.scala:86:29] assign rrd_uops_0_prs2_busy = rrd_uops_0_REG_prs2_busy; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_prs3_busy; // @[register-read.scala:86:29] assign rrd_uops_0_prs3_busy = rrd_uops_0_REG_prs3_busy; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_ppred_busy; // @[register-read.scala:86:29] assign rrd_uops_0_ppred_busy = rrd_uops_0_REG_ppred_busy; // @[register-read.scala:67:30, :86:29] reg [6:0] rrd_uops_0_REG_stale_pdst; // @[register-read.scala:86:29] assign rrd_uops_0_stale_pdst = rrd_uops_0_REG_stale_pdst; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_exception; // @[register-read.scala:86:29] assign rrd_uops_0_exception = rrd_uops_0_REG_exception; // @[register-read.scala:67:30, :86:29] reg [63:0] rrd_uops_0_REG_exc_cause; // @[register-read.scala:86:29] assign rrd_uops_0_exc_cause = rrd_uops_0_REG_exc_cause; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_bypassable; // @[register-read.scala:86:29] assign rrd_uops_0_bypassable = rrd_uops_0_REG_bypassable; // @[register-read.scala:67:30, :86:29] reg [4:0] rrd_uops_0_REG_mem_cmd; // @[register-read.scala:86:29] assign rrd_uops_0_mem_cmd = rrd_uops_0_REG_mem_cmd; // @[register-read.scala:67:30, :86:29] reg [1:0] rrd_uops_0_REG_mem_size; // @[register-read.scala:86:29] assign rrd_uops_0_mem_size = rrd_uops_0_REG_mem_size; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_mem_signed; // @[register-read.scala:86:29] assign rrd_uops_0_mem_signed = rrd_uops_0_REG_mem_signed; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_is_fence; // @[register-read.scala:86:29] assign rrd_uops_0_is_fence = rrd_uops_0_REG_is_fence; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_is_fencei; // @[register-read.scala:86:29] assign rrd_uops_0_is_fencei = rrd_uops_0_REG_is_fencei; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_is_amo; // @[register-read.scala:86:29] assign rrd_uops_0_is_amo = rrd_uops_0_REG_is_amo; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_uses_ldq; // @[register-read.scala:86:29] assign rrd_uops_0_uses_ldq = rrd_uops_0_REG_uses_ldq; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_uses_stq; // @[register-read.scala:86:29] assign rrd_uops_0_uses_stq = rrd_uops_0_REG_uses_stq; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_is_sys_pc2epc; // @[register-read.scala:86:29] assign rrd_uops_0_is_sys_pc2epc = rrd_uops_0_REG_is_sys_pc2epc; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_is_unique; // @[register-read.scala:86:29] assign rrd_uops_0_is_unique = rrd_uops_0_REG_is_unique; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_flush_on_commit; // @[register-read.scala:86:29] assign rrd_uops_0_flush_on_commit = rrd_uops_0_REG_flush_on_commit; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_ldst_is_rs1; // @[register-read.scala:86:29] assign rrd_uops_0_ldst_is_rs1 = rrd_uops_0_REG_ldst_is_rs1; // @[register-read.scala:67:30, :86:29] reg [5:0] rrd_uops_0_REG_ldst; // @[register-read.scala:86:29] assign rrd_uops_0_ldst = rrd_uops_0_REG_ldst; // @[register-read.scala:67:30, :86:29] reg [5:0] rrd_uops_0_REG_lrs1; // @[register-read.scala:86:29] assign rrd_uops_0_lrs1 = rrd_uops_0_REG_lrs1; // @[register-read.scala:67:30, :86:29] reg [5:0] rrd_uops_0_REG_lrs2; // @[register-read.scala:86:29] assign rrd_uops_0_lrs2 = rrd_uops_0_REG_lrs2; // @[register-read.scala:67:30, :86:29] reg [5:0] rrd_uops_0_REG_lrs3; // @[register-read.scala:86:29] assign rrd_uops_0_lrs3 = rrd_uops_0_REG_lrs3; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_ldst_val; // @[register-read.scala:86:29] assign rrd_uops_0_ldst_val = rrd_uops_0_REG_ldst_val; // @[register-read.scala:67:30, :86:29] reg [1:0] rrd_uops_0_REG_dst_rtype; // @[register-read.scala:86:29] assign rrd_uops_0_dst_rtype = rrd_uops_0_REG_dst_rtype; // @[register-read.scala:67:30, :86:29] reg [1:0] rrd_uops_0_REG_lrs1_rtype; // @[register-read.scala:86:29] assign rrd_uops_0_lrs1_rtype = rrd_uops_0_REG_lrs1_rtype; // @[register-read.scala:67:30, :86:29] reg [1:0] rrd_uops_0_REG_lrs2_rtype; // @[register-read.scala:86:29] assign rrd_uops_0_lrs2_rtype = rrd_uops_0_REG_lrs2_rtype; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_frs3_en; // @[register-read.scala:86:29] assign rrd_uops_0_frs3_en = rrd_uops_0_REG_frs3_en; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_fp_val; // @[register-read.scala:86:29] assign rrd_uops_0_fp_val = rrd_uops_0_REG_fp_val; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_fp_single; // @[register-read.scala:86:29] assign rrd_uops_0_fp_single = rrd_uops_0_REG_fp_single; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_xcpt_pf_if; // @[register-read.scala:86:29] assign rrd_uops_0_xcpt_pf_if = rrd_uops_0_REG_xcpt_pf_if; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_xcpt_ae_if; // @[register-read.scala:86:29] assign rrd_uops_0_xcpt_ae_if = rrd_uops_0_REG_xcpt_ae_if; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_xcpt_ma_if; // @[register-read.scala:86:29] assign rrd_uops_0_xcpt_ma_if = rrd_uops_0_REG_xcpt_ma_if; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_bp_debug_if; // @[register-read.scala:86:29] assign rrd_uops_0_bp_debug_if = rrd_uops_0_REG_bp_debug_if; // @[register-read.scala:67:30, :86:29] reg rrd_uops_0_REG_bp_xcpt_if; // @[register-read.scala:86:29] assign rrd_uops_0_bp_xcpt_if = rrd_uops_0_REG_bp_xcpt_if; // @[register-read.scala:67:30, :86:29] reg [1:0] rrd_uops_0_REG_debug_fsrc; // @[register-read.scala:86:29] assign rrd_uops_0_debug_fsrc = rrd_uops_0_REG_debug_fsrc; // @[register-read.scala:67:30, :86:29] reg [1:0] rrd_uops_0_REG_debug_tsrc; // @[register-read.scala:86:29] assign rrd_uops_0_debug_tsrc = rrd_uops_0_REG_debug_tsrc; // @[register-read.scala:67:30, :86:29] wire [64:0] _rrd_rs1_data_0_T_1; // @[register-read.scala:124:49] wire [64:0] rrd_rs1_data_0; // @[register-read.scala:94:28] wire [64:0] _bypassed_rs1_data_0_T = rrd_rs1_data_0; // @[Mux.scala:126:16] wire [64:0] _rrd_rs2_data_0_T_1; // @[register-read.scala:125:49] wire [64:0] rrd_rs2_data_0; // @[register-read.scala:95:28] wire [64:0] _bypassed_rs2_data_0_T = rrd_rs2_data_0; // @[Mux.scala:126:16] wire [64:0] _rrd_rs3_data_0_T_1; // @[register-read.scala:126:49] wire [64:0] rrd_rs3_data_0; // @[register-read.scala:96:28] wire _rrd_rs1_data_0_T = io_iss_uops_0_prs1_0 == 7'h0; // @[register-read.scala:34:7, :124:67] reg rrd_rs1_data_0_REG; // @[register-read.scala:124:57] assign _rrd_rs1_data_0_T_1 = rrd_rs1_data_0_REG ? 65'h0 : io_rf_read_ports_0_data_0; // @[register-read.scala:34:7, :124:{49,57}] assign rrd_rs1_data_0 = _rrd_rs1_data_0_T_1; // @[register-read.scala:94:28, :124:49] wire _rrd_rs2_data_0_T = io_iss_uops_0_prs2_0 == 7'h0; // @[register-read.scala:34:7, :125:67] reg rrd_rs2_data_0_REG; // @[register-read.scala:125:57] assign _rrd_rs2_data_0_T_1 = rrd_rs2_data_0_REG ? 65'h0 : io_rf_read_ports_1_data_0; // @[register-read.scala:34:7, :125:{49,57}] assign rrd_rs2_data_0 = _rrd_rs2_data_0_T_1; // @[register-read.scala:95:28, :125:49] wire _rrd_rs3_data_0_T = io_iss_uops_0_prs3_0 == 7'h0; // @[register-read.scala:34:7, :126:67] reg rrd_rs3_data_0_REG; // @[register-read.scala:126:57] assign _rrd_rs3_data_0_T_1 = rrd_rs3_data_0_REG ? 65'h0 : io_rf_read_ports_2_data_0; // @[register-read.scala:34:7, :126:{49,57}] assign rrd_rs3_data_0 = _rrd_rs3_data_0_T_1; // @[register-read.scala:96:28, :126:49] wire [15:0] _rrd_kill_T = io_brupdate_b1_mispredict_mask_0 & rrd_uops_0_br_mask; // @[util.scala:118:51] wire _rrd_kill_T_1 = \|_rrd_kill_T; // @[util.scala:118:{51,59}] wire rrd_kill = io_kill_0 \| _rrd_kill_T_1; // @[util.scala:118:59] wire _exe_reg_valids_0_T = ~rrd_kill & rrd_valids_0; // @[register-read.scala:66:30, :130:28, :132:29] wire [6:0] _exe_reg_uops_0_T_uopc = rrd_kill ? 7'h0 : rrd_uops_0_uopc; // @[register-read.scala:67:30, :130:28, :134:29] wire [31:0] _exe_reg_uops_0_T_inst = rrd_kill ? 32'h0 : rrd_uops_0_inst; // @[register-read.scala:67:30, :130:28, :134:29] wire [31:0] _exe_reg_uops_0_T_debug_inst = rrd_kill ? 32'h0 : rrd_uops_0_debug_inst; // @[register-read.scala:67:30, :130:28, :134:29] wire _exe_reg_uops_0_T_is_rvc = ~rrd_kill & rrd_uops_0_is_rvc; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire [39:0] _exe_reg_uops_0_T_debug_pc = rrd_kill ? 40'h0 : rrd_uops_0_debug_pc; // @[register-read.scala:67:30, :130:28, :134:29] wire [2:0] _exe_reg_uops_0_T_iq_type = rrd_kill ? 3'h0 : rrd_uops_0_iq_type; // @[register-read.scala:67:30, :130:28, :134:29] wire [9:0] _exe_reg_uops_0_T_fu_code = rrd_kill ? 10'h0 : rrd_uops_0_fu_code; // @[register-read.scala:67:30, :130:28, :134:29] wire [3:0] _exe_reg_uops_0_T_ctrl_br_type = rrd_kill ? 4'h0 : rrd_uops_0_ctrl_br_type; // @[register-read.scala:67:30, :130:28, :134:29] wire [1:0] _exe_reg_uops_0_T_ctrl_op1_sel = rrd_kill ? 2'h0 : rrd_uops_0_ctrl_op1_sel; // @[register-read.scala:67:30, :130:28, :134:29] wire [2:0] _exe_reg_uops_0_T_ctrl_op2_sel = rrd_kill ? 3'h0 : rrd_uops_0_ctrl_op2_sel; // @[register-read.scala:67:30, :130:28, :134:29] wire [2:0] _exe_reg_uops_0_T_ctrl_imm_sel = rrd_kill ? 3'h0 : rrd_uops_0_ctrl_imm_sel; // @[register-read.scala:67:30, :130:28, :134:29] wire [4:0] _exe_reg_uops_0_T_ctrl_op_fcn = rrd_kill ? 5'h0 : rrd_uops_0_ctrl_op_fcn; // @[register-read.scala:67:30, :130:28, :134:29] wire _exe_reg_uops_0_T_ctrl_fcn_dw = ~rrd_kill & rrd_uops_0_ctrl_fcn_dw; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire [2:0] _exe_reg_uops_0_T_ctrl_csr_cmd = rrd_kill ? 3'h0 : rrd_uops_0_ctrl_csr_cmd; // @[register-read.scala:67:30, :130:28, :134:29] wire _exe_reg_uops_0_T_ctrl_is_load = ~rrd_kill & rrd_uops_0_ctrl_is_load; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_ctrl_is_sta = ~rrd_kill & rrd_uops_0_ctrl_is_sta; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_ctrl_is_std = ~rrd_kill & rrd_uops_0_ctrl_is_std; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire [1:0] _exe_reg_uops_0_T_iw_state = rrd_kill ? 2'h0 : rrd_uops_0_iw_state; // @[register-read.scala:67:30, :130:28, :134:29] wire _exe_reg_uops_0_T_iw_p1_poisoned = ~rrd_kill & rrd_uops_0_iw_p1_poisoned; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_iw_p2_poisoned = ~rrd_kill & rrd_uops_0_iw_p2_poisoned; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_is_br = ~rrd_kill & rrd_uops_0_is_br; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_is_jalr = ~rrd_kill & rrd_uops_0_is_jalr; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_is_jal = ~rrd_kill & rrd_uops_0_is_jal; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_is_sfb = ~rrd_kill & rrd_uops_0_is_sfb; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire [15:0] _exe_reg_uops_0_T_br_mask = rrd_kill ? 16'h0 : rrd_uops_0_br_mask; // @[register-read.scala:67:30, :130:28, :134:29] wire [3:0] _exe_reg_uops_0_T_br_tag = rrd_kill ? 4'h0 : rrd_uops_0_br_tag; // @[register-read.scala:67:30, :130:28, :134:29] wire [4:0] _exe_reg_uops_0_T_ftq_idx = rrd_kill ? 5'h0 : rrd_uops_0_ftq_idx; // @[register-read.scala:67:30, :130:28, :134:29] wire _exe_reg_uops_0_T_edge_inst = ~rrd_kill & rrd_uops_0_edge_inst; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire [5:0] _exe_reg_uops_0_T_pc_lob = rrd_kill ? 6'h0 : rrd_uops_0_pc_lob; // @[register-read.scala:67:30, :130:28, :134:29] wire _exe_reg_uops_0_T_taken = ~rrd_kill & rrd_uops_0_taken; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire [19:0] _exe_reg_uops_0_T_imm_packed = rrd_kill ? 20'h0 : rrd_uops_0_imm_packed; // @[register-read.scala:67:30, :130:28, :134:29] wire [11:0] _exe_reg_uops_0_T_csr_addr = rrd_kill ? 12'h0 : rrd_uops_0_csr_addr; // @[register-read.scala:67:30, :130:28, :134:29] wire [6:0] _exe_reg_uops_0_T_rob_idx = rrd_kill ? 7'h0 : rrd_uops_0_rob_idx; // @[register-read.scala:67:30, :130:28, :134:29] wire [4:0] _exe_reg_uops_0_T_ldq_idx = rrd_kill ? 5'h0 : rrd_uops_0_ldq_idx; // @[register-read.scala:67:30, :130:28, :134:29] wire [4:0] _exe_reg_uops_0_T_stq_idx = rrd_kill ? 5'h0 : rrd_uops_0_stq_idx; // @[register-read.scala:67:30, :130:28, :134:29] wire [1:0] _exe_reg_uops_0_T_rxq_idx = rrd_kill ? 2'h0 : rrd_uops_0_rxq_idx; // @[register-read.scala:67:30, :130:28, :134:29] wire [6:0] _exe_reg_uops_0_T_pdst = rrd_kill ? 7'h0 : rrd_uops_0_pdst; // @[register-read.scala:67:30, :130:28, :134:29] wire [6:0] _exe_reg_uops_0_T_prs1 = rrd_kill ? 7'h0 : rrd_uops_0_prs1; // @[register-read.scala:67:30, :130:28, :134:29] wire [6:0] _exe_reg_uops_0_T_prs2 = rrd_kill ? 7'h0 : rrd_uops_0_prs2; // @[register-read.scala:67:30, :130:28, :134:29] wire [6:0] _exe_reg_uops_0_T_prs3 = rrd_kill ? 7'h0 : rrd_uops_0_prs3; // @[register-read.scala:67:30, :130:28, :134:29] wire [4:0] _exe_reg_uops_0_T_ppred = rrd_kill ? 5'h0 : rrd_uops_0_ppred; // @[register-read.scala:67:30, :130:28, :134:29] wire _exe_reg_uops_0_T_prs1_busy = ~rrd_kill & rrd_uops_0_prs1_busy; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_prs2_busy = ~rrd_kill & rrd_uops_0_prs2_busy; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_prs3_busy = ~rrd_kill & rrd_uops_0_prs3_busy; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_ppred_busy = ~rrd_kill & rrd_uops_0_ppred_busy; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire [6:0] _exe_reg_uops_0_T_stale_pdst = rrd_kill ? 7'h0 : rrd_uops_0_stale_pdst; // @[register-read.scala:67:30, :130:28, :134:29] wire _exe_reg_uops_0_T_exception = ~rrd_kill & rrd_uops_0_exception; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire [63:0] _exe_reg_uops_0_T_exc_cause = rrd_kill ? 64'h0 : rrd_uops_0_exc_cause; // @[register-read.scala:67:30, :130:28, :134:29] wire _exe_reg_uops_0_T_bypassable = ~rrd_kill & rrd_uops_0_bypassable; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire [4:0] _exe_reg_uops_0_T_mem_cmd = rrd_kill ? 5'h0 : rrd_uops_0_mem_cmd; // @[register-read.scala:67:30, :130:28, :134:29] wire [1:0] _exe_reg_uops_0_T_mem_size = rrd_kill ? 2'h0 : rrd_uops_0_mem_size; // @[register-read.scala:67:30, :130:28, :134:29] wire _exe_reg_uops_0_T_mem_signed = ~rrd_kill & rrd_uops_0_mem_signed; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_is_fence = ~rrd_kill & rrd_uops_0_is_fence; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_is_fencei = ~rrd_kill & rrd_uops_0_is_fencei; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_is_amo = ~rrd_kill & rrd_uops_0_is_amo; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_uses_ldq = ~rrd_kill & rrd_uops_0_uses_ldq; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_uses_stq = ~rrd_kill & rrd_uops_0_uses_stq; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_is_sys_pc2epc = ~rrd_kill & rrd_uops_0_is_sys_pc2epc; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_is_unique = ~rrd_kill & rrd_uops_0_is_unique; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_flush_on_commit = ~rrd_kill & rrd_uops_0_flush_on_commit; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_ldst_is_rs1 = ~rrd_kill & rrd_uops_0_ldst_is_rs1; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire [5:0] _exe_reg_uops_0_T_ldst = rrd_kill ? 6'h0 : rrd_uops_0_ldst; // @[register-read.scala:67:30, :130:28, :134:29] wire [5:0] _exe_reg_uops_0_T_lrs1 = rrd_kill ? 6'h0 : rrd_uops_0_lrs1; // @[register-read.scala:67:30, :130:28, :134:29] wire [5:0] _exe_reg_uops_0_T_lrs2 = rrd_kill ? 6'h0 : rrd_uops_0_lrs2; // @[register-read.scala:67:30, :130:28, :134:29] wire [5:0] _exe_reg_uops_0_T_lrs3 = rrd_kill ? 6'h0 : rrd_uops_0_lrs3; // @[register-read.scala:67:30, :130:28, :134:29] wire _exe_reg_uops_0_T_ldst_val = ~rrd_kill & rrd_uops_0_ldst_val; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire [1:0] _exe_reg_uops_0_T_dst_rtype = rrd_kill ? 2'h2 : rrd_uops_0_dst_rtype; // @[register-read.scala:67:30, :130:28, :134:29] wire [1:0] _exe_reg_uops_0_T_lrs1_rtype = rrd_kill ? 2'h0 : rrd_uops_0_lrs1_rtype; // @[register-read.scala:67:30, :130:28, :134:29] wire [1:0] _exe_reg_uops_0_T_lrs2_rtype = rrd_kill ? 2'h0 : rrd_uops_0_lrs2_rtype; // @[register-read.scala:67:30, :130:28, :134:29] wire _exe_reg_uops_0_T_frs3_en = ~rrd_kill & rrd_uops_0_frs3_en; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_fp_val = ~rrd_kill & rrd_uops_0_fp_val; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_fp_single = ~rrd_kill & rrd_uops_0_fp_single; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_xcpt_pf_if = ~rrd_kill & rrd_uops_0_xcpt_pf_if; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_xcpt_ae_if = ~rrd_kill & rrd_uops_0_xcpt_ae_if; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_xcpt_ma_if = ~rrd_kill & rrd_uops_0_xcpt_ma_if; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_bp_debug_if = ~rrd_kill & rrd_uops_0_bp_debug_if; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire _exe_reg_uops_0_T_bp_xcpt_if = ~rrd_kill & rrd_uops_0_bp_xcpt_if; // @[register-read.scala:67:30, :130:28, :132:29, :134:29] wire [1:0] _exe_reg_uops_0_T_debug_fsrc = rrd_kill ? 2'h0 : rrd_uops_0_debug_fsrc; // @[register-read.scala:67:30, :130:28, :134:29] wire [1:0] _exe_reg_uops_0_T_debug_tsrc = rrd_kill ? 2'h0 : rrd_uops_0_debug_tsrc; // @[register-read.scala:67:30, :130:28, :134:29] wire [15:0] _exe_reg_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:74:37, :85:27] wire [15:0] _exe_reg_uops_0_br_mask_T_1 = rrd_uops_0_br_mask & _exe_reg_uops_0_br_mask_T; // @[util.scala:85:{25,27}] wire [64:0] bypassed_rs1_data_0; // @[register-read.scala:152:31] wire [64:0] bypassed_rs2_data_0; // @[register-read.scala:153:31] assign bypassed_rs1_data_0 = _bypassed_rs1_data_0_T; // @[Mux.scala:126:16] assign bypassed_rs2_data_0 = _bypassed_rs2_data_0_T; // @[Mux.scala:126:16] always @(posedge clock) begin // @[register-read.scala:34:7] if (reset) // @[register-read.scala:34:7] exe_reg_valids_0 <= 1'h0; // @[register-read.scala:69:33] else // @[register-read.scala:34:7] exe_reg_valids_0 <= _exe_reg_valids_0_T; // @[register-read.scala:69:33, :132:29] exe_reg_uops_0_uopc <= _exe_reg_uops_0_T_uopc; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_inst <= _exe_reg_uops_0_T_inst; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_debug_inst <= _exe_reg_uops_0_T_debug_inst; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_is_rvc <= _exe_reg_uops_0_T_is_rvc; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_debug_pc <= _exe_reg_uops_0_T_debug_pc; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_iq_type <= _exe_reg_uops_0_T_iq_type; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_fu_code <= _exe_reg_uops_0_T_fu_code; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ctrl_br_type <= _exe_reg_uops_0_T_ctrl_br_type; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ctrl_op1_sel <= _exe_reg_uops_0_T_ctrl_op1_sel; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ctrl_op2_sel <= _exe_reg_uops_0_T_ctrl_op2_sel; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ctrl_imm_sel <= _exe_reg_uops_0_T_ctrl_imm_sel; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ctrl_op_fcn <= _exe_reg_uops_0_T_ctrl_op_fcn; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ctrl_fcn_dw <= _exe_reg_uops_0_T_ctrl_fcn_dw; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ctrl_csr_cmd <= _exe_reg_uops_0_T_ctrl_csr_cmd; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ctrl_is_load <= _exe_reg_uops_0_T_ctrl_is_load; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ctrl_is_sta <= _exe_reg_uops_0_T_ctrl_is_sta; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ctrl_is_std <= _exe_reg_uops_0_T_ctrl_is_std; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_iw_state <= _exe_reg_uops_0_T_iw_state; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_iw_p1_poisoned <= _exe_reg_uops_0_T_iw_p1_poisoned; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_iw_p2_poisoned <= _exe_reg_uops_0_T_iw_p2_poisoned; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_is_br <= _exe_reg_uops_0_T_is_br; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_is_jalr <= _exe_reg_uops_0_T_is_jalr; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_is_jal <= _exe_reg_uops_0_T_is_jal; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_is_sfb <= _exe_reg_uops_0_T_is_sfb; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_br_mask <= _exe_reg_uops_0_br_mask_T_1; // @[util.scala:85:25] exe_reg_uops_0_br_tag <= _exe_reg_uops_0_T_br_tag; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ftq_idx <= _exe_reg_uops_0_T_ftq_idx; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_edge_inst <= _exe_reg_uops_0_T_edge_inst; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_pc_lob <= _exe_reg_uops_0_T_pc_lob; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_taken <= _exe_reg_uops_0_T_taken; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_imm_packed <= _exe_reg_uops_0_T_imm_packed; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_csr_addr <= _exe_reg_uops_0_T_csr_addr; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_rob_idx <= _exe_reg_uops_0_T_rob_idx; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ldq_idx <= _exe_reg_uops_0_T_ldq_idx; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_stq_idx <= _exe_reg_uops_0_T_stq_idx; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_rxq_idx <= _exe_reg_uops_0_T_rxq_idx; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_pdst <= _exe_reg_uops_0_T_pdst; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_prs1 <= _exe_reg_uops_0_T_prs1; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_prs2 <= _exe_reg_uops_0_T_prs2; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_prs3 <= _exe_reg_uops_0_T_prs3; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ppred <= _exe_reg_uops_0_T_ppred; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_prs1_busy <= _exe_reg_uops_0_T_prs1_busy; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_prs2_busy <= _exe_reg_uops_0_T_prs2_busy; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_prs3_busy <= _exe_reg_uops_0_T_prs3_busy; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ppred_busy <= _exe_reg_uops_0_T_ppred_busy; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_stale_pdst <= _exe_reg_uops_0_T_stale_pdst; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_exception <= _exe_reg_uops_0_T_exception; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_exc_cause <= _exe_reg_uops_0_T_exc_cause; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_bypassable <= _exe_reg_uops_0_T_bypassable; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_mem_cmd <= _exe_reg_uops_0_T_mem_cmd; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_mem_size <= _exe_reg_uops_0_T_mem_size; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_mem_signed <= _exe_reg_uops_0_T_mem_signed; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_is_fence <= _exe_reg_uops_0_T_is_fence; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_is_fencei <= _exe_reg_uops_0_T_is_fencei; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_is_amo <= _exe_reg_uops_0_T_is_amo; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_uses_ldq <= _exe_reg_uops_0_T_uses_ldq; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_uses_stq <= _exe_reg_uops_0_T_uses_stq; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_is_sys_pc2epc <= _exe_reg_uops_0_T_is_sys_pc2epc; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_is_unique <= _exe_reg_uops_0_T_is_unique; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_flush_on_commit <= _exe_reg_uops_0_T_flush_on_commit; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ldst_is_rs1 <= _exe_reg_uops_0_T_ldst_is_rs1; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ldst <= _exe_reg_uops_0_T_ldst; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_lrs1 <= _exe_reg_uops_0_T_lrs1; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_lrs2 <= _exe_reg_uops_0_T_lrs2; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_lrs3 <= _exe_reg_uops_0_T_lrs3; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_ldst_val <= _exe_reg_uops_0_T_ldst_val; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_dst_rtype <= _exe_reg_uops_0_T_dst_rtype; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_lrs1_rtype <= _exe_reg_uops_0_T_lrs1_rtype; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_lrs2_rtype <= _exe_reg_uops_0_T_lrs2_rtype; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_frs3_en <= _exe_reg_uops_0_T_frs3_en; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_fp_val <= _exe_reg_uops_0_T_fp_val; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_fp_single <= _exe_reg_uops_0_T_fp_single; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_xcpt_pf_if <= _exe_reg_uops_0_T_xcpt_pf_if; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_xcpt_ae_if <= _exe_reg_uops_0_T_xcpt_ae_if; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_xcpt_ma_if <= _exe_reg_uops_0_T_xcpt_ma_if; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_bp_debug_if <= _exe_reg_uops_0_T_bp_debug_if; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_bp_xcpt_if <= _exe_reg_uops_0_T_bp_xcpt_if; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_debug_fsrc <= _exe_reg_uops_0_T_debug_fsrc; // @[register-read.scala:70:29, :134:29] exe_reg_uops_0_debug_tsrc <= _exe_reg_uops_0_T_debug_tsrc; // @[register-read.scala:70:29, :134:29] exe_reg_rs1_data_0 <= bypassed_rs1_data_0; // @[register-read.scala:71:29, :152:31] exe_reg_rs2_data_0 <= bypassed_rs2_data_0; // @[register-read.scala:72:29, :153:31] exe_reg_rs3_data_0 <= rrd_rs3_data_0; // @[register-read.scala:73:29, :96:28] rrd_valids_0_REG <= _rrd_valids_0_T_3; // @[register-read.scala:84:{29,59}] rrd_uops_0_REG_uopc <= rrd_uops_0_newuop_uopc; // @[util.scala:73:26] rrd_uops_0_REG_inst <= rrd_uops_0_newuop_inst; // @[util.scala:73:26] rrd_uops_0_REG_debug_inst <= rrd_uops_0_newuop_debug_inst; // @[util.scala:73:26] rrd_uops_0_REG_is_rvc <= rrd_uops_0_newuop_is_rvc; // @[util.scala:73:26] rrd_uops_0_REG_debug_pc <= rrd_uops_0_newuop_debug_pc; // @[util.scala:73:26] rrd_uops_0_REG_iq_type <= rrd_uops_0_newuop_iq_type; // @[util.scala:73:26] rrd_uops_0_REG_fu_code <= rrd_uops_0_newuop_fu_code; // @[util.scala:73:26] rrd_uops_0_REG_ctrl_br_type <= rrd_uops_0_newuop_ctrl_br_type; // @[util.scala:73:26] rrd_uops_0_REG_ctrl_op1_sel <= rrd_uops_0_newuop_ctrl_op1_sel; // @[util.scala:73:26] rrd_uops_0_REG_ctrl_op2_sel <= rrd_uops_0_newuop_ctrl_op2_sel; // @[util.scala:73:26] rrd_uops_0_REG_ctrl_imm_sel <= rrd_uops_0_newuop_ctrl_imm_sel; // @[util.scala:73:26] rrd_uops_0_REG_ctrl_op_fcn <= rrd_uops_0_newuop_ctrl_op_fcn; // @[util.scala:73:26] rrd_uops_0_REG_ctrl_fcn_dw <= rrd_uops_0_newuop_ctrl_fcn_dw; // @[util.scala:73:26] rrd_uops_0_REG_ctrl_csr_cmd <= rrd_uops_0_newuop_ctrl_csr_cmd; // @[util.scala:73:26] rrd_uops_0_REG_ctrl_is_load <= rrd_uops_0_newuop_ctrl_is_load; // @[util.scala:73:26] rrd_uops_0_REG_ctrl_is_sta <= rrd_uops_0_newuop_ctrl_is_sta; // @[util.scala:73:26] rrd_uops_0_REG_ctrl_is_std <= rrd_uops_0_newuop_ctrl_is_std; // @[util.scala:73:26] rrd_uops_0_REG_iw_state <= rrd_uops_0_newuop_iw_state; // @[util.scala:73:26] rrd_uops_0_REG_iw_p1_poisoned <= 1'h0; // @[register-read.scala:86:29] rrd_uops_0_REG_iw_p2_poisoned <= 1'h0; // @[register-read.scala:86:29] rrd_uops_0_REG_is_br <= rrd_uops_0_newuop_is_br; // @[util.scala:73:26] rrd_uops_0_REG_is_jalr <= rrd_uops_0_newuop_is_jalr; // @[util.scala:73:26] rrd_uops_0_REG_is_jal <= rrd_uops_0_newuop_is_jal; // @[util.scala:73:26] rrd_uops_0_REG_is_sfb <= rrd_uops_0_newuop_is_sfb; // @[util.scala:73:26] rrd_uops_0_REG_br_mask <= rrd_uops_0_newuop_br_mask; // @[util.scala:73:26] rrd_uops_0_REG_br_tag <= rrd_uops_0_newuop_br_tag; // @[util.scala:73:26] rrd_uops_0_REG_ftq_idx <= rrd_uops_0_newuop_ftq_idx; // @[util.scala:73:26] rrd_uops_0_REG_edge_inst <= rrd_uops_0_newuop_edge_inst; // @[util.scala:73:26] rrd_uops_0_REG_pc_lob <= rrd_uops_0_newuop_pc_lob; // @[util.scala:73:26] rrd_uops_0_REG_taken <= rrd_uops_0_newuop_taken; // @[util.scala:73:26] rrd_uops_0_REG_imm_packed <= rrd_uops_0_newuop_imm_packed; // @[util.scala:73:26] rrd_uops_0_REG_csr_addr <= rrd_uops_0_newuop_csr_addr; // @[util.scala:73:26] rrd_uops_0_REG_rob_idx <= rrd_uops_0_newuop_rob_idx; // @[util.scala:73:26] rrd_uops_0_REG_ldq_idx <= rrd_uops_0_newuop_ldq_idx; // @[util.scala:73:26] rrd_uops_0_REG_stq_idx <= rrd_uops_0_newuop_stq_idx; // @[util.scala:73:26] rrd_uops_0_REG_rxq_idx <= rrd_uops_0_newuop_rxq_idx; // @[util.scala:73:26] rrd_uops_0_REG_pdst <= rrd_uops_0_newuop_pdst; // @[util.scala:73:26] rrd_uops_0_REG_prs1 <= rrd_uops_0_newuop_prs1; // @[util.scala:73:26] rrd_uops_0_REG_prs2 <= rrd_uops_0_newuop_prs2; // @[util.scala:73:26] rrd_uops_0_REG_prs3 <= rrd_uops_0_newuop_prs3; // @[util.scala:73:26] rrd_uops_0_REG_ppred <= rrd_uops_0_newuop_ppred; // @[util.scala:73:26] rrd_uops_0_REG_prs1_busy <= rrd_uops_0_newuop_prs1_busy; // @[util.scala:73:26] rrd_uops_0_REG_prs2_busy <= rrd_uops_0_newuop_prs2_busy; // @[util.scala:73:26] rrd_uops_0_REG_prs3_busy <= rrd_uops_0_newuop_prs3_busy; // @[util.scala:73:26] rrd_uops_0_REG_ppred_busy <= rrd_uops_0_newuop_ppred_busy; // @[util.scala:73:26] rrd_uops_0_REG_stale_pdst <= rrd_uops_0_newuop_stale_pdst; // @[util.scala:73:26] rrd_uops_0_REG_exception <= rrd_uops_0_newuop_exception; // @[util.scala:73:26] rrd_uops_0_REG_exc_cause <= rrd_uops_0_newuop_exc_cause; // @[util.scala:73:26] rrd_uops_0_REG_bypassable <= rrd_uops_0_newuop_bypassable; // @[util.scala:73:26] rrd_uops_0_REG_mem_cmd <= rrd_uops_0_newuop_mem_cmd; // @[util.scala:73:26] rrd_uops_0_REG_mem_size <= rrd_uops_0_newuop_mem_size; // @[util.scala:73:26] rrd_uops_0_REG_mem_signed <= rrd_uops_0_newuop_mem_signed; // @[util.scala:73:26] rrd_uops_0_REG_is_fence <= rrd_uops_0_newuop_is_fence; // @[util.scala:73:26] rrd_uops_0_REG_is_fencei <= rrd_uops_0_newuop_is_fencei; // @[util.scala:73:26] rrd_uops_0_REG_is_amo <= rrd_uops_0_newuop_is_amo; // @[util.scala:73:26] rrd_uops_0_REG_uses_ldq <= rrd_uops_0_newuop_uses_ldq; // @[util.scala:73:26] rrd_uops_0_REG_uses_stq <= rrd_uops_0_newuop_uses_stq; // @[util.scala:73:26] rrd_uops_0_REG_is_sys_pc2epc <= rrd_uops_0_newuop_is_sys_pc2epc; // @[util.scala:73:26] rrd_uops_0_REG_is_unique <= rrd_uops_0_newuop_is_unique; // @[util.scala:73:26] rrd_uops_0_REG_flush_on_commit <= rrd_uops_0_newuop_flush_on_commit; // @[util.scala:73:26] rrd_uops_0_REG_ldst_is_rs1 <= rrd_uops_0_newuop_ldst_is_rs1; // @[util.scala:73:26] rrd_uops_0_REG_ldst <= rrd_uops_0_newuop_ldst; // @[util.scala:73:26] rrd_uops_0_REG_lrs1 <= rrd_uops_0_newuop_lrs1; // @[util.scala:73:26] rrd_uops_0_REG_lrs2 <= rrd_uops_0_newuop_lrs2; // @[util.scala:73:26] rrd_uops_0_REG_lrs3 <= rrd_uops_0_newuop_lrs3; // @[util.scala:73:26] rrd_uops_0_REG_ldst_val <= rrd_uops_0_newuop_ldst_val; // @[util.scala:73:26] rrd_uops_0_REG_dst_rtype <= rrd_uops_0_newuop_dst_rtype; // @[util.scala:73:26] rrd_uops_0_REG_lrs1_rtype <= rrd_uops_0_newuop_lrs1_rtype; // @[util.scala:73:26] rrd_uops_0_REG_lrs2_rtype <= rrd_uops_0_newuop_lrs2_rtype; // @[util.scala:73:26] rrd_uops_0_REG_frs3_en <= rrd_uops_0_newuop_frs3_en; // @[util.scala:73:26] rrd_uops_0_REG_fp_val <= rrd_uops_0_newuop_fp_val; // @[util.scala:73:26] rrd_uops_0_REG_fp_single <= rrd_uops_0_newuop_fp_single; // @[util.scala:73:26] rrd_uops_0_REG_xcpt_pf_if <= rrd_uops_0_newuop_xcpt_pf_if; // @[util.scala:73:26] rrd_uops_0_REG_xcpt_ae_if <= rrd_uops_0_newuop_xcpt_ae_if; // @[util.scala:73:26] rrd_uops_0_REG_xcpt_ma_if <= rrd_uops_0_newuop_xcpt_ma_if; // @[util.scala:73:26] rrd_uops_0_REG_bp_debug_if <= rrd_uops_0_newuop_bp_debug_if; // @[util.scala:73:26] rrd_uops_0_REG_bp_xcpt_if <= rrd_uops_0_newuop_bp_xcpt_if; // @[util.scala:73:26] rrd_uops_0_REG_debug_fsrc <= rrd_uops_0_newuop_debug_fsrc; // @[util.scala:73:26] rrd_uops_0_REG_debug_tsrc <= rrd_uops_0_newuop_debug_tsrc; // @[util.scala:73:26] rrd_rs1_data_0_REG <= _rrd_rs1_data_0_T; // @[register-read.scala:124:{57,67}] rrd_rs2_data_0_REG <= _rrd_rs2_data_0_T; // @[register-read.scala:125:{57,67}] rrd_rs3_data_0_REG <= _rrd_rs3_data_0_T; // @[register-read.scala:126:{57,67}] always @(posedge) RegisterReadDecode_5 rrd_decode_unit ( // @[register-read.scala:80:33] .clock (clock), .reset (reset), .io_iss_valid (io_iss_valids_0_0), // @[register-read.scala:34:7] .io_iss_uop_uopc (io_iss_uops_0_uopc_0), // @[register-read.scala:34:7] .io_iss_uop_inst (io_iss_uops_0_inst_0), // @[register-read.scala:34:7] .io_iss_uop_debug_inst (io_iss_uops_0_debug_inst_0), // @[register-read.scala:34:7] .io_iss_uop_is_rvc (io_iss_uops_0_is_rvc_0), // @[register-read.scala:34:7] .io_iss_uop_debug_pc (io_iss_uops_0_debug_pc_0), // @[register-read.scala:34:7] .io_iss_uop_iq_type (io_iss_uops_0_iq_type_0), // @[register-read.scala:34:7] .io_iss_uop_fu_code (io_iss_uops_0_fu_code_0), // @[register-read.scala:34:7] .io_iss_uop_ctrl_br_type (io_iss_uops_0_ctrl_br_type_0), // @[register-read.scala:34:7] .io_iss_uop_ctrl_op1_sel (io_iss_uops_0_ctrl_op1_sel_0), // @[register-read.scala:34:7] .io_iss_uop_ctrl_op2_sel (io_iss_uops_0_ctrl_op2_sel_0), // @[register-read.scala:34:7] .io_iss_uop_ctrl_imm_sel (io_iss_uops_0_ctrl_imm_sel_0), // @[register-read.scala:34:7] .io_iss_uop_ctrl_op_fcn (io_iss_uops_0_ctrl_op_fcn_0), // @[register-read.scala:34:7] .io_iss_uop_ctrl_fcn_dw (io_iss_uops_0_ctrl_fcn_dw_0), // @[register-read.scala:34:7] .io_iss_uop_ctrl_csr_cmd (io_iss_uops_0_ctrl_csr_cmd_0), // @[register-read.scala:34:7] .io_iss_uop_ctrl_is_load (io_iss_uops_0_ctrl_is_load_0), // @[register-read.scala:34:7] .io_iss_uop_ctrl_is_sta (io_iss_uops_0_ctrl_is_sta_0), // @[register-read.scala:34:7] .io_iss_uop_ctrl_is_std (io_iss_uops_0_ctrl_is_std_0), // @[register-read.scala:34:7] .io_iss_uop_iw_state (io_iss_uops_0_iw_state_0), // @[register-read.scala:34:7] .io_iss_uop_is_br (io_iss_uops_0_is_br_0), // @[register-read.scala:34:7] .io_iss_uop_is_jalr (io_iss_uops_0_is_jalr_0), // @[register-read.scala:34:7] .io_iss_uop_is_jal (io_iss_uops_0_is_jal_0), // @[register-read.scala:34:7] .io_iss_uop_is_sfb (io_iss_uops_0_is_sfb_0), // @[register-read.scala:34:7] .io_iss_uop_br_mask (io_iss_uops_0_br_mask_0), // @[register-read.scala:34:7] .io_iss_uop_br_tag (io_iss_uops_0_br_tag_0), // @[register-read.scala:34:7] .io_iss_uop_ftq_idx (io_iss_uops_0_ftq_idx_0), // @[register-read.scala:34:7] .io_iss_uop_edge_inst (io_iss_uops_0_edge_inst_0), // @[register-read.scala:34:7] .io_iss_uop_pc_lob (io_iss_uops_0_pc_lob_0), // @[register-read.scala:34:7] .io_iss_uop_taken (io_iss_uops_0_taken_0), // @[register-read.scala:34:7] .io_iss_uop_imm_packed (io_iss_uops_0_imm_packed_0), // @[register-read.scala:34:7] .io_iss_uop_csr_addr (io_iss_uops_0_csr_addr_0), // @[register-read.scala:34:7] .io_iss_uop_rob_idx (io_iss_uops_0_rob_idx_0), // @[register-read.scala:34:7] .io_iss_uop_ldq_idx (io_iss_uops_0_ldq_idx_0), // @[register-read.scala:34:7] .io_iss_uop_stq_idx (io_iss_uops_0_stq_idx_0), // @[register-read.scala:34:7] .io_iss_uop_rxq_idx (io_iss_uops_0_rxq_idx_0), // @[register-read.scala:34:7] .io_iss_uop_pdst (io_iss_uops_0_pdst_0), // @[register-read.scala:34:7] .io_iss_uop_prs1 (io_iss_uops_0_prs1_0), // @[register-read.scala:34:7] .io_iss_uop_prs2 (io_iss_uops_0_prs2_0), // @[register-read.scala:34:7] .io_iss_uop_prs3 (io_iss_uops_0_prs3_0), // @[register-read.scala:34:7] .io_iss_uop_ppred (io_iss_uops_0_ppred_0), // @[register-read.scala:34:7] .io_iss_uop_prs1_busy (io_iss_uops_0_prs1_busy_0), // @[register-read.scala:34:7] .io_iss_uop_prs2_busy (io_iss_uops_0_prs2_busy_0), // @[register-read.scala:34:7] .io_iss_uop_prs3_busy (io_iss_uops_0_prs3_busy_0), // @[register-read.scala:34:7] .io_iss_uop_ppred_busy (io_iss_uops_0_ppred_busy_0), // @[register-read.scala:34:7] .io_iss_uop_stale_pdst (io_iss_uops_0_stale_pdst_0), // @[register-read.scala:34:7] .io_iss_uop_exception (io_iss_uops_0_exception_0), // @[register-read.scala:34:7] .io_iss_uop_exc_cause (io_iss_uops_0_exc_cause_0), // @[register-read.scala:34:7] .io_iss_uop_bypassable (io_iss_uops_0_bypassable_0), // @[register-read.scala:34:7] .io_iss_uop_mem_cmd (io_iss_uops_0_mem_cmd_0), // @[register-read.scala:34:7] .io_iss_uop_mem_size (io_iss_uops_0_mem_size_0), // @[register-read.scala:34:7] .io_iss_uop_mem_signed (io_iss_uops_0_mem_signed_0), // @[register-read.scala:34:7] .io_iss_uop_is_fence (io_iss_uops_0_is_fence_0), // @[register-read.scala:34:7] .io_iss_uop_is_fencei (io_iss_uops_0_is_fencei_0), // @[register-read.scala:34:7] .io_iss_uop_is_amo (io_iss_uops_0_is_amo_0), // @[register-read.scala:34:7] .io_iss_uop_uses_ldq (io_iss_uops_0_uses_ldq_0), // @[register-read.scala:34:7] .io_iss_uop_uses_stq (io_iss_uops_0_uses_stq_0), // @[register-read.scala:34:7] .io_iss_uop_is_sys_pc2epc (io_iss_uops_0_is_sys_pc2epc_0), // @[register-read.scala:34:7] .io_iss_uop_is_unique (io_iss_uops_0_is_unique_0), // @[register-read.scala:34:7] .io_iss_uop_flush_on_commit (io_iss_uops_0_flush_on_commit_0), // @[register-read.scala:34:7] .io_iss_uop_ldst_is_rs1 (io_iss_uops_0_ldst_is_rs1_0), // @[register-read.scala:34:7] .io_iss_uop_ldst (io_iss_uops_0_ldst_0), // @[register-read.scala:34:7] .io_iss_uop_lrs1 (io_iss_uops_0_lrs1_0), // @[register-read.scala:34:7] .io_iss_uop_lrs2 (io_iss_uops_0_lrs2_0), // @[register-read.scala:34:7] .io_iss_uop_lrs3 (io_iss_uops_0_lrs3_0), // @[register-read.scala:34:7] .io_iss_uop_ldst_val (io_iss_uops_0_ldst_val_0), // @[register-read.scala:34:7] .io_iss_uop_dst_rtype (io_iss_uops_0_dst_rtype_0), // @[register-read.scala:34:7] .io_iss_uop_lrs1_rtype (io_iss_uops_0_lrs1_rtype_0), // @[register-read.scala:34:7] .io_iss_uop_lrs2_rtype (io_iss_uops_0_lrs2_rtype_0), // @[register-read.scala:34:7] .io_iss_uop_frs3_en (io_iss_uops_0_frs3_en_0), // @[register-read.scala:34:7] .io_iss_uop_fp_val (io_iss_uops_0_fp_val_0), // @[register-read.scala:34:7] .io_iss_uop_fp_single (io_iss_uops_0_fp_single_0), // @[register-read.scala:34:7] .io_iss_uop_xcpt_pf_if (io_iss_uops_0_xcpt_pf_if_0), // @[register-read.scala:34:7] .io_iss_uop_xcpt_ae_if (io_iss_uops_0_xcpt_ae_if_0), // @[register-read.scala:34:7] .io_iss_uop_xcpt_ma_if (io_iss_uops_0_xcpt_ma_if_0), // @[register-read.scala:34:7] .io_iss_uop_bp_debug_if (io_iss_uops_0_bp_debug_if_0), // @[register-read.scala:34:7] .io_iss_uop_bp_xcpt_if (io_iss_uops_0_bp_xcpt_if_0), // @[register-read.scala:34:7] .io_iss_uop_debug_fsrc (io_iss_uops_0_debug_fsrc_0), // @[register-read.scala:34:7] .io_iss_uop_debug_tsrc (io_iss_uops_0_debug_tsrc_0), // @[register-read.scala:34:7] .io_rrd_valid (_rrd_decode_unit_io_rrd_valid), .io_rrd_uop_uopc (rrd_uops_0_newuop_uopc), .io_rrd_uop_inst (rrd_uops_0_newuop_inst), .io_rrd_uop_debug_inst (rrd_uops_0_newuop_debug_inst), .io_rrd_uop_is_rvc (rrd_uops_0_newuop_is_rvc), .io_rrd_uop_debug_pc (rrd_uops_0_newuop_debug_pc), .io_rrd_uop_iq_type (rrd_uops_0_newuop_iq_type), .io_rrd_uop_fu_code (rrd_uops_0_newuop_fu_code), .io_rrd_uop_ctrl_br_type (rrd_uops_0_newuop_ctrl_br_type), .io_rrd_uop_ctrl_op1_sel (rrd_uops_0_newuop_ctrl_op1_sel), .io_rrd_uop_ctrl_op2_sel (rrd_uops_0_newuop_ctrl_op2_sel), .io_rrd_uop_ctrl_imm_sel (rrd_uops_0_newuop_ctrl_imm_sel), .io_rrd_uop_ctrl_op_fcn (rrd_uops_0_newuop_ctrl_op_fcn), .io_rrd_uop_ctrl_fcn_dw (rrd_uops_0_newuop_ctrl_fcn_dw), .io_rrd_uop_ctrl_csr_cmd (rrd_uops_0_newuop_ctrl_csr_cmd), .io_rrd_uop_ctrl_is_load (rrd_uops_0_newuop_ctrl_is_load), .io_rrd_uop_ctrl_is_sta (rrd_uops_0_newuop_ctrl_is_sta), .io_rrd_uop_ctrl_is_std (rrd_uops_0_newuop_ctrl_is_std), .io_rrd_uop_iw_state (rrd_uops_0_newuop_iw_state), .io_rrd_uop_is_br (rrd_uops_0_newuop_is_br), .io_rrd_uop_is_jalr (rrd_uops_0_newuop_is_jalr), .io_rrd_uop_is_jal (rrd_uops_0_newuop_is_jal), .io_rrd_uop_is_sfb (rrd_uops_0_newuop_is_sfb), .io_rrd_uop_br_mask (_rrd_decode_unit_io_rrd_uop_br_mask), .io_rrd_uop_br_tag (rrd_uops_0_newuop_br_tag), .io_rrd_uop_ftq_idx (rrd_uops_0_newuop_ftq_idx), .io_rrd_uop_edge_inst (rrd_uops_0_newuop_edge_inst), .io_rrd_uop_pc_lob (rrd_uops_0_newuop_pc_lob), .io_rrd_uop_taken (rrd_uops_0_newuop_taken), .io_rrd_uop_imm_packed (rrd_uops_0_newuop_imm_packed), .io_rrd_uop_csr_addr (rrd_uops_0_newuop_csr_addr), .io_rrd_uop_rob_idx (rrd_uops_0_newuop_rob_idx), .io_rrd_uop_ldq_idx (rrd_uops_0_newuop_ldq_idx), .io_rrd_uop_stq_idx (rrd_uops_0_newuop_stq_idx), .io_rrd_uop_rxq_idx (rrd_uops_0_newuop_rxq_idx), .io_rrd_uop_pdst (rrd_uops_0_newuop_pdst), .io_rrd_uop_prs1 (rrd_uops_0_newuop_prs1), .io_rrd_uop_prs2 (rrd_uops_0_newuop_prs2), .io_rrd_uop_prs3 (rrd_uops_0_newuop_prs3), .io_rrd_uop_ppred (rrd_uops_0_newuop_ppred), .io_rrd_uop_prs1_busy (rrd_uops_0_newuop_prs1_busy), .io_rrd_uop_prs2_busy (rrd_uops_0_newuop_prs2_busy), .io_rrd_uop_prs3_busy (rrd_uops_0_newuop_prs3_busy), .io_rrd_uop_ppred_busy (rrd_uops_0_newuop_ppred_busy), .io_rrd_uop_stale_pdst (rrd_uops_0_newuop_stale_pdst), .io_rrd_uop_exception (rrd_uops_0_newuop_exception), .io_rrd_uop_exc_cause (rrd_uops_0_newuop_exc_cause), .io_rrd_uop_bypassable (rrd_uops_0_newuop_bypassable), .io_rrd_uop_mem_cmd (rrd_uops_0_newuop_mem_cmd), .io_rrd_uop_mem_size (rrd_uops_0_newuop_mem_size), .io_rrd_uop_mem_signed (rrd_uops_0_newuop_mem_signed), .io_rrd_uop_is_fence (rrd_uops_0_newuop_is_fence), .io_rrd_uop_is_fencei (rrd_uops_0_newuop_is_fencei), .io_rrd_uop_is_amo (rrd_uops_0_newuop_is_amo), .io_rrd_uop_uses_ldq (rrd_uops_0_newuop_uses_ldq), .io_rrd_uop_uses_stq (rrd_uops_0_newuop_uses_stq), .io_rrd_uop_is_sys_pc2epc (rrd_uops_0_newuop_is_sys_pc2epc), .io_rrd_uop_is_unique (rrd_uops_0_newuop_is_unique), .io_rrd_uop_flush_on_commit (rrd_uops_0_newuop_flush_on_commit), .io_rrd_uop_ldst_is_rs1 (rrd_uops_0_newuop_ldst_is_rs1), .io_rrd_uop_ldst (rrd_uops_0_newuop_ldst), .io_rrd_uop_lrs1 (rrd_uops_0_newuop_lrs1), .io_rrd_uop_lrs2 (rrd_uops_0_newuop_lrs2), .io_rrd_uop_lrs3 (rrd_uops_0_newuop_lrs3), .io_rrd_uop_ldst_val (rrd_uops_0_newuop_ldst_val), .io_rrd_uop_dst_rtype (rrd_uops_0_newuop_dst_rtype), .io_rrd_uop_lrs1_rtype (rrd_uops_0_newuop_lrs1_rtype), .io_rrd_uop_lrs2_rtype (rrd_uops_0_newuop_lrs2_rtype), .io_rrd_uop_frs3_en (rrd_uops_0_newuop_frs3_en), .io_rrd_uop_fp_val (rrd_uops_0_newuop_fp_val), .io_rrd_uop_fp_single (rrd_uops_0_newuop_fp_single), .io_rrd_uop_xcpt_pf_if (rrd_uops_0_newuop_xcpt_pf_if), .io_rrd_uop_xcpt_ae_if (rrd_uops_0_newuop_xcpt_ae_if), .io_rrd_uop_xcpt_ma_if (rrd_uops_0_newuop_xcpt_ma_if), .io_rrd_uop_bp_debug_if (rrd_uops_0_newuop_bp_debug_if), .io_rrd_uop_bp_xcpt_if (rrd_uops_0_newuop_bp_xcpt_if), .io_rrd_uop_debug_fsrc (rrd_uops_0_newuop_debug_fsrc), .io_rrd_uop_debug_tsrc (rrd_uops_0_newuop_debug_tsrc) ); // @[register-read.scala:80:33] assign io_rf_read_ports_0_addr = io_rf_read_ports_0_addr_0; // @[register-read.scala:34:7] assign io_rf_read_ports_1_addr = io_rf_read_ports_1_addr_0; // @[register-read.scala:34:7] assign io_rf_read_ports_2_addr = io_rf_read_ports_2_addr_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_valid = io_exe_reqs_0_valid_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_uopc = io_exe_reqs_0_bits_uop_uopc_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_inst = io_exe_reqs_0_bits_uop_inst_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_debug_inst = io_exe_reqs_0_bits_uop_debug_inst_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_is_rvc = io_exe_reqs_0_bits_uop_is_rvc_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_debug_pc = io_exe_reqs_0_bits_uop_debug_pc_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_iq_type = io_exe_reqs_0_bits_uop_iq_type_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_fu_code = io_exe_reqs_0_bits_uop_fu_code_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ctrl_br_type = io_exe_reqs_0_bits_uop_ctrl_br_type_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ctrl_op1_sel = io_exe_reqs_0_bits_uop_ctrl_op1_sel_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ctrl_op2_sel = io_exe_reqs_0_bits_uop_ctrl_op2_sel_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ctrl_imm_sel = io_exe_reqs_0_bits_uop_ctrl_imm_sel_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ctrl_op_fcn = io_exe_reqs_0_bits_uop_ctrl_op_fcn_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ctrl_fcn_dw = io_exe_reqs_0_bits_uop_ctrl_fcn_dw_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ctrl_csr_cmd = io_exe_reqs_0_bits_uop_ctrl_csr_cmd_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ctrl_is_load = io_exe_reqs_0_bits_uop_ctrl_is_load_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ctrl_is_sta = io_exe_reqs_0_bits_uop_ctrl_is_sta_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ctrl_is_std = io_exe_reqs_0_bits_uop_ctrl_is_std_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_iw_state = io_exe_reqs_0_bits_uop_iw_state_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_iw_p1_poisoned = io_exe_reqs_0_bits_uop_iw_p1_poisoned_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_iw_p2_poisoned = io_exe_reqs_0_bits_uop_iw_p2_poisoned_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_is_br = io_exe_reqs_0_bits_uop_is_br_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_is_jalr = io_exe_reqs_0_bits_uop_is_jalr_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_is_jal = io_exe_reqs_0_bits_uop_is_jal_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_is_sfb = io_exe_reqs_0_bits_uop_is_sfb_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_br_mask = io_exe_reqs_0_bits_uop_br_mask_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_br_tag = io_exe_reqs_0_bits_uop_br_tag_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ftq_idx = io_exe_reqs_0_bits_uop_ftq_idx_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_edge_inst = io_exe_reqs_0_bits_uop_edge_inst_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_pc_lob = io_exe_reqs_0_bits_uop_pc_lob_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_taken = io_exe_reqs_0_bits_uop_taken_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_imm_packed = io_exe_reqs_0_bits_uop_imm_packed_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_csr_addr = io_exe_reqs_0_bits_uop_csr_addr_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_rob_idx = io_exe_reqs_0_bits_uop_rob_idx_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ldq_idx = io_exe_reqs_0_bits_uop_ldq_idx_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_stq_idx = io_exe_reqs_0_bits_uop_stq_idx_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_rxq_idx = io_exe_reqs_0_bits_uop_rxq_idx_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_pdst = io_exe_reqs_0_bits_uop_pdst_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_prs1 = io_exe_reqs_0_bits_uop_prs1_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_prs2 = io_exe_reqs_0_bits_uop_prs2_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_prs3 = io_exe_reqs_0_bits_uop_prs3_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ppred = io_exe_reqs_0_bits_uop_ppred_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_prs1_busy = io_exe_reqs_0_bits_uop_prs1_busy_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_prs2_busy = io_exe_reqs_0_bits_uop_prs2_busy_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_prs3_busy = io_exe_reqs_0_bits_uop_prs3_busy_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ppred_busy = io_exe_reqs_0_bits_uop_ppred_busy_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_stale_pdst = io_exe_reqs_0_bits_uop_stale_pdst_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_exception = io_exe_reqs_0_bits_uop_exception_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_exc_cause = io_exe_reqs_0_bits_uop_exc_cause_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_bypassable = io_exe_reqs_0_bits_uop_bypassable_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_mem_cmd = io_exe_reqs_0_bits_uop_mem_cmd_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_mem_size = io_exe_reqs_0_bits_uop_mem_size_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_mem_signed = io_exe_reqs_0_bits_uop_mem_signed_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_is_fence = io_exe_reqs_0_bits_uop_is_fence_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_is_fencei = io_exe_reqs_0_bits_uop_is_fencei_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_is_amo = io_exe_reqs_0_bits_uop_is_amo_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_uses_ldq = io_exe_reqs_0_bits_uop_uses_ldq_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_uses_stq = io_exe_reqs_0_bits_uop_uses_stq_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_is_sys_pc2epc = io_exe_reqs_0_bits_uop_is_sys_pc2epc_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_is_unique = io_exe_reqs_0_bits_uop_is_unique_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_flush_on_commit = io_exe_reqs_0_bits_uop_flush_on_commit_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ldst_is_rs1 = io_exe_reqs_0_bits_uop_ldst_is_rs1_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ldst = io_exe_reqs_0_bits_uop_ldst_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_lrs1 = io_exe_reqs_0_bits_uop_lrs1_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_lrs2 = io_exe_reqs_0_bits_uop_lrs2_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_lrs3 = io_exe_reqs_0_bits_uop_lrs3_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_ldst_val = io_exe_reqs_0_bits_uop_ldst_val_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_dst_rtype = io_exe_reqs_0_bits_uop_dst_rtype_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_lrs1_rtype = io_exe_reqs_0_bits_uop_lrs1_rtype_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_lrs2_rtype = io_exe_reqs_0_bits_uop_lrs2_rtype_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_frs3_en = io_exe_reqs_0_bits_uop_frs3_en_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_fp_val = io_exe_reqs_0_bits_uop_fp_val_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_fp_single = io_exe_reqs_0_bits_uop_fp_single_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_xcpt_pf_if = io_exe_reqs_0_bits_uop_xcpt_pf_if_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_xcpt_ae_if = io_exe_reqs_0_bits_uop_xcpt_ae_if_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_xcpt_ma_if = io_exe_reqs_0_bits_uop_xcpt_ma_if_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_bp_debug_if = io_exe_reqs_0_bits_uop_bp_debug_if_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_bp_xcpt_if = io_exe_reqs_0_bits_uop_bp_xcpt_if_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_debug_fsrc = io_exe_reqs_0_bits_uop_debug_fsrc_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_uop_debug_tsrc = io_exe_reqs_0_bits_uop_debug_tsrc_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_rs1_data = io_exe_reqs_0_bits_rs1_data_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_rs2_data = io_exe_reqs_0_bits_rs2_data_0; // @[register-read.scala:34:7] assign io_exe_reqs_0_bits_rs3_data = io_exe_reqs_0_bits_rs3_data_0; // @[register-read.scala:34:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_8 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_8( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire _common_underflow_T_7 = io_detectTininess_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :222:49] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T \| _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire _GEN = roundingMode_near_even \| roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 \| _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} \| _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 \| _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_7 & _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:{49,77}, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T \| roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire _pegMinNonzeroMagOut_T_1 = roundMagUp \| roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18] wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}] wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14] wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16] wire [8:0] _expOut_T_15 = _expOut_T_13 \| _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16] wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [8:0] _expOut_T_17 = _expOut_T_15 \| _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [22:0] fractOut = _fractOut_T_3 \| _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DigitalTop : output auto : { flip chipyard_prcictrl_domain_reset_setter_clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, mbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}, cbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}} output psd : { } output resetctrl : { flip hartIsInReset : UInt<1>[1]} output debug : { flip clock : Clock, flip reset : Reset, systemjtag : { flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, flip reset : Reset, flip mfr_id : UInt<11>, flip part_number : UInt<16>, flip version : UInt<4>}, ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>} output mem_tl : { } output mem_axi4 : { `0` : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}} output mmio_axi4 : { } input l2_frontend_bus_axi4 : { } input custom_boot : UInt<1> output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock} output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>} output uart_0 : { txd : UInt<1>, flip rxd : UInt<1>} output nic : { clock : Clock, bits : { flip in : { valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}, out : { valid : UInt<1>, bits : { data : UInt<64>, keep : UInt<8>, last : UInt<1>}}, flip macAddr : UInt<48>, flip rlimit : { inc : UInt<8>, period : UInt<8>, size : UInt<8>}, flip pauser : { threshold : UInt<16>, quanta : UInt<16>, refresh : UInt<16>}}} output clock_tap : Clock input interrupts : UInt<0> wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset inst ibus of ClockSinkDomain inst sbus of SystemBus inst pbus of PeripheryBus_pbus inst fbus of FrontBus inst cbus of PeripheryBus_cbus inst mbus of MemoryBus inst coh_wrapper of CoherenceManagerWrapper inst tile_prci_domain of TilePRCIDomain inst xbar of IntXbar_i1_o1 inst xbar_1 of IntXbar_i1_o1_1 inst xbar_2 of IntXbar_i1_o1_2 inst tileHartIdNexusNode of BundleBridgeNexus_UInt1_1 inst broadcast of BundleBridgeNexus_UInt32_1 inst clint_domain of CLINTClockSinkDomain inst plic_domain of PLICClockSinkDomain inst tlDM of TLDebugModule inst debugCustomXbarOpt of DebugCustomXbar inst nexus of BundleBridgeNexus_TraceBundle inst nexus_1 of BundleBridgeNexus_TraceCoreInterface inst bootrom_domain of BootROMClockSinkDomain inst bank of ScratchpadBank inst serial_tl_domain of SerialTL0ClockSinkDomain inst uartClockDomainWrapper of TLUARTClockSinkDomain inst intsink of IntSyncSyncCrossingSink_n1x1_5 inst icenic_domain of ClockSinkDomain_1 inst chipyard_prcictrl_domain of ChipyardPRCICtrlClockSinkDomain inst aggregator of ClockGroupAggregator_allClocks inst clockNamePrefixer of ClockGroupParameterModifier inst frequencySpecifier of ClockGroupParameterModifier_1 inst clockGroupCombiner of ClockGroupCombiner inst clockTapNode of ClockGroup_6 inst globalNoCDomain of ClockSinkDomain_2 inst reRoCCManagerIdNexusNode of BundleBridgeNexus_NoOutput_8 wire allClockGroupsNodeOut : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeOut.member.sbus_0.reset invalidate allClockGroupsNodeOut.member.sbus_0.clock invalidate allClockGroupsNodeOut.member.sbus_1.reset invalidate allClockGroupsNodeOut.member.sbus_1.clock wire x1_allClockGroupsNodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut.member.pbus_0.reset invalidate x1_allClockGroupsNodeOut.member.pbus_0.clock wire x1_allClockGroupsNodeOut_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.clock wire x1_allClockGroupsNodeOut_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.clock wire x1_allClockGroupsNodeOut_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.clock wire x1_allClockGroupsNodeOut_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.clock wire allClockGroupsNodeIn : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}} invalidate allClockGroupsNodeIn.member.sbus_0.reset invalidate allClockGroupsNodeIn.member.sbus_0.clock invalidate allClockGroupsNodeIn.member.sbus_1.reset invalidate allClockGroupsNodeIn.member.sbus_1.clock wire x1_allClockGroupsNodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn.member.pbus_0.reset invalidate x1_allClockGroupsNodeIn.member.pbus_0.clock wire x1_allClockGroupsNodeIn_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.reset invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.clock wire x1_allClockGroupsNodeIn_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.reset invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.clock wire x1_allClockGroupsNodeIn_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.reset invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.clock wire x1_allClockGroupsNodeIn_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}} invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.reset invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.clock connect allClockGroupsNodeOut, allClockGroupsNodeIn connect x1_allClockGroupsNodeOut, x1_allClockGroupsNodeIn connect x1_allClockGroupsNodeOut_1, x1_allClockGroupsNodeIn_1 connect x1_allClockGroupsNodeOut_2, x1_allClockGroupsNodeIn_2 connect x1_allClockGroupsNodeOut_3, x1_allClockGroupsNodeIn_3 connect x1_allClockGroupsNodeOut_4, x1_allClockGroupsNodeIn_4 wire tileHaltSinkNodeIn : UInt<1>[1] invalidate tileHaltSinkNodeIn[0] wire tileWFISinkNodeIn : UInt<1>[1] invalidate tileWFISinkNodeIn[0] wire tileCeaseSinkNodeIn : UInt<1>[1] invalidate tileCeaseSinkNodeIn[0] wire domainIn : { clock : Clock, reset : Reset} invalidate domainIn.reset invalidate domainIn.clock wire debugNodesOut : { sync : UInt<1>[1]} invalidate debugNodesOut.sync[0] wire debugNodesIn : { sync : UInt<1>[1]} invalidate debugNodesIn.sync[0] connect debugNodesOut, debugNodesIn wire traceCoreNodesIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>} invalidate traceCoreNodesIn.cause invalidate traceCoreNodesIn.tval invalidate traceCoreNodesIn.priv invalidate traceCoreNodesIn.group[0].ilastsize invalidate traceCoreNodesIn.group[0].itype invalidate traceCoreNodesIn.group[0].iaddr invalidate traceCoreNodesIn.group[0].iretire wire traceNodesIn : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[3], time : UInt<64>, custom : { rob_empty : UInt<1>}} invalidate traceNodesIn.custom.rob_empty invalidate traceNodesIn.time invalidate traceNodesIn.insns[0].tval invalidate traceNodesIn.insns[0].cause invalidate traceNodesIn.insns[0].interrupt invalidate traceNodesIn.insns[0].exception invalidate traceNodesIn.insns[0].priv invalidate traceNodesIn.insns[0].insn invalidate traceNodesIn.insns[0].iaddr invalidate traceNodesIn.insns[0].valid invalidate traceNodesIn.insns[1].tval invalidate traceNodesIn.insns[1].cause invalidate traceNodesIn.insns[1].interrupt invalidate traceNodesIn.insns[1].exception invalidate traceNodesIn.insns[1].priv invalidate traceNodesIn.insns[1].insn invalidate traceNodesIn.insns[1].iaddr invalidate traceNodesIn.insns[1].valid invalidate traceNodesIn.insns[2].tval invalidate traceNodesIn.insns[2].cause invalidate traceNodesIn.insns[2].interrupt invalidate traceNodesIn.insns[2].exception invalidate traceNodesIn.insns[2].priv invalidate traceNodesIn.insns[2].insn invalidate traceNodesIn.insns[2].iaddr invalidate traceNodesIn.insns[2].valid wire memAXI4NodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}} invalidate memAXI4NodeIn.r.bits.last invalidate memAXI4NodeIn.r.bits.resp invalidate memAXI4NodeIn.r.bits.data invalidate memAXI4NodeIn.r.bits.id invalidate memAXI4NodeIn.r.valid invalidate memAXI4NodeIn.r.ready invalidate memAXI4NodeIn.ar.bits.qos invalidate memAXI4NodeIn.ar.bits.prot invalidate memAXI4NodeIn.ar.bits.cache invalidate memAXI4NodeIn.ar.bits.lock invalidate memAXI4NodeIn.ar.bits.burst invalidate memAXI4NodeIn.ar.bits.size invalidate memAXI4NodeIn.ar.bits.len invalidate memAXI4NodeIn.ar.bits.addr invalidate memAXI4NodeIn.ar.bits.id invalidate memAXI4NodeIn.ar.valid invalidate memAXI4NodeIn.ar.ready invalidate memAXI4NodeIn.b.bits.resp invalidate memAXI4NodeIn.b.bits.id invalidate memAXI4NodeIn.b.valid invalidate memAXI4NodeIn.b.ready invalidate memAXI4NodeIn.w.bits.last invalidate memAXI4NodeIn.w.bits.strb invalidate memAXI4NodeIn.w.bits.data invalidate memAXI4NodeIn.w.valid invalidate memAXI4NodeIn.w.ready invalidate memAXI4NodeIn.aw.bits.qos invalidate memAXI4NodeIn.aw.bits.prot invalidate memAXI4NodeIn.aw.bits.cache invalidate memAXI4NodeIn.aw.bits.lock invalidate memAXI4NodeIn.aw.bits.burst invalidate memAXI4NodeIn.aw.bits.size invalidate memAXI4NodeIn.aw.bits.len invalidate memAXI4NodeIn.aw.bits.addr invalidate memAXI4NodeIn.aw.bits.id invalidate memAXI4NodeIn.aw.valid invalidate memAXI4NodeIn.aw.ready wire bootROMResetVectorSourceNodeOut : UInt<32> invalidate bootROMResetVectorSourceNodeOut wire intXingOut : { sync : UInt<1>[1]} invalidate intXingOut.sync[0] wire intXingIn : { sync : UInt<1>[1]} invalidate intXingIn.sync[0] connect intXingOut, intXingIn wire ioNodeIn : { txd : UInt<1>, flip rxd : UInt<1>} invalidate ioNodeIn.rxd invalidate ioNodeIn.txd wire clockTapIn : { clock : Clock, reset : Reset} invalidate clockTapIn.reset invalidate clockTapIn.clock connect plic_domain.auto.plic_int_in[0], ibus.auto.int_bus_anon_out[0] connect plic_domain.auto.plic_int_in[1], ibus.auto.int_bus_anon_out[1] connect plic_domain.auto.plic_int_in[2], ibus.auto.int_bus_anon_out[2] connect sbus.auto.sbus_clock_groups_in, allClockGroupsNodeOut connect pbus.auto.pbus_clock_groups_in, x1_allClockGroupsNodeOut connect fbus.auto.fbus_clock_groups_in, x1_allClockGroupsNodeOut_1 connect mbus.auto.mbus_clock_groups_in, x1_allClockGroupsNodeOut_2 connect cbus.auto.cbus_clock_groups_in, x1_allClockGroupsNodeOut_3 connect clockTapNode.auto.in, x1_allClockGroupsNodeOut_4 connect coh_wrapper.auto.coh_clock_groups_in, sbus.auto.sbus_clock_groups_out connect ibus.auto.clock_in, sbus.auto.fixedClockNode_anon_out_0 connect tile_prci_domain.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_1 connect globalNoCDomain.auto.clock_in, sbus.auto.fixedClockNode_anon_out_2 connect uartClockDomainWrapper.auto.clock_in, pbus.auto.fixedClockNode_anon_out_0 connect icenic_domain.auto.clock_in, pbus.auto.fixedClockNode_anon_out_1 connect serial_tl_domain.auto.clock_in, fbus.auto.fixedClockNode_anon_out connect clint_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_0 connect plic_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_1 connect domainIn, cbus.auto.fixedClockNode_anon_out_2 connect bootrom_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_3 connect chipyard_prcictrl_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_4 connect bank.auto.clock_in, mbus.auto.fixedClockNode_anon_out_0 connect coh_wrapper.auto.l2_ctrls_ctrl_in, cbus.auto.coupler_to_l2_ctrl_buffer_out connect cbus.auto.bus_xing_in, sbus.auto.coupler_to_bus_named_cbus_bus_xing_out connect pbus.auto.bus_xing_in, cbus.auto.coupler_to_bus_named_pbus_bus_xing_out connect sbus.auto.coupler_from_bus_named_fbus_bus_xing_in, fbus.auto.bus_xing_out connect coh_wrapper.auto.coherent_jbar_anon_in, sbus.auto.coupler_to_bus_named_coh_widget_anon_out connect mbus.auto.bus_xing_in, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out connect nexus.auto.in, tile_prci_domain.auto.element_reset_domain_boom_tile_trace_source_out connect nexus_1.auto.in, tile_prci_domain.auto.element_reset_domain_boom_tile_trace_core_source_out connect tileHaltSinkNodeIn, xbar.auto.anon_out connect tileWFISinkNodeIn, xbar_1.auto.anon_out connect tileCeaseSinkNodeIn, xbar_2.auto.anon_out connect tile_prci_domain.auto.element_reset_domain_boom_tile_hartid_in, tileHartIdNexusNode.auto.out connect tile_prci_domain.auto.element_reset_domain_boom_tile_reset_vector_in, broadcast.auto.out connect clint_domain.auto.clint_in, cbus.auto.coupler_to_clint_fragmenter_anon_out connect plic_domain.auto.plic_in, cbus.auto.coupler_to_plic_fragmenter_anon_out connect debugNodesIn, tlDM.auto.dmOuter_int_out connect fbus.auto.coupler_from_debug_sb_widget_anon_in, tlDM.auto.dmInner_dmInner_sb2tlOpt_out connect tlDM.auto.dmInner_dmInner_tl_in, cbus.auto.coupler_to_debug_fragmenter_anon_out connect tlDM.auto.dmInner_dmInner_custom_in, debugCustomXbarOpt.auto.out connect tile_prci_domain.auto.intsink_in.sync[0], debugNodesOut.sync[0] connect sbus.auto.coupler_from_boom_tile_tl_master_clock_xing_in, tile_prci_domain.auto.tl_master_clock_xing_out connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out.sync[1] connect tile_prci_domain.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_0.sync[0] connect tile_prci_domain.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_1.sync[0] connect xbar.auto.anon_in[0], tile_prci_domain.auto.intsink_out_0[0] connect xbar_1.auto.anon_in[0], tile_prci_domain.auto.intsink_out_1[0] connect xbar_2.auto.anon_in[0], tile_prci_domain.auto.intsink_out_2[0] connect traceNodesIn, nexus.auto.out connect traceCoreNodesIn, nexus_1.auto.out connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.r, memAXI4NodeIn.r connect memAXI4NodeIn.ar.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.bits connect memAXI4NodeIn.ar.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.ready, memAXI4NodeIn.ar.ready connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.b, memAXI4NodeIn.b connect memAXI4NodeIn.w.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.bits connect memAXI4NodeIn.w.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.ready, memAXI4NodeIn.w.ready connect memAXI4NodeIn.aw.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.bits connect memAXI4NodeIn.aw.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.valid connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.ready, memAXI4NodeIn.aw.ready connect broadcast.auto.in, bootROMResetVectorSourceNodeOut connect bootrom_domain.auto.bootrom_in, cbus.auto.coupler_to_bootrom_fragmenter_anon_out connect bank.auto.xbar_anon_in, mbus.auto.buffer_out connect fbus.auto.coupler_from_port_named_serial_tl_0_in_buffer_in, serial_tl_domain.auto.serdesser_client_out connect uartClockDomainWrapper.auto.uart_0_io_out.rxd, ioNodeIn.rxd connect ioNodeIn.txd, uartClockDomainWrapper.auto.uart_0_io_out.txd connect uartClockDomainWrapper.auto.uart_0_control_xing_in, pbus.auto.coupler_to_device_named_uart_0_control_xing_out connect ibus.auto.int_bus_anon_in_0[0], intsink.auto.out[0] connect intsink.auto.in.sync[0], intXingOut.sync[0] connect intXingIn, uartClockDomainWrapper.auto.uart_0_int_xing_out connect fbus.auto.coupler_from_IceNIC_tl_in_0, icenic_domain.auto.icenic_dma_out_0 connect fbus.auto.coupler_from_IceNIC_tl_in_1, icenic_domain.auto.icenic_dma_out_1 connect ibus.auto.int_bus_anon_in_1[0], icenic_domain.auto.icenic_intsink_out[0] connect ibus.auto.int_bus_anon_in_1[1], icenic_domain.auto.icenic_intsink_out[1] connect icenic_domain.auto.icenic_mmio_in, pbus.auto.coupler_to_IceNIC_fragmenter_anon_out connect chipyard_prcictrl_domain.auto.xbar_anon_in, cbus.auto.coupler_to_prci_ctrl_fixer_anon_out connect clockNamePrefixer.auto.clock_name_prefixer_in_0, aggregator.auto.out_0 connect clockNamePrefixer.auto.clock_name_prefixer_in_1, aggregator.auto.out_1 connect clockNamePrefixer.auto.clock_name_prefixer_in_2, aggregator.auto.out_2 connect clockNamePrefixer.auto.clock_name_prefixer_in_3, aggregator.auto.out_3 connect clockNamePrefixer.auto.clock_name_prefixer_in_4, aggregator.auto.out_4 connect clockNamePrefixer.auto.clock_name_prefixer_in_5, aggregator.auto.out_5 connect allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_0 connect x1_allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_1 connect x1_allClockGroupsNodeIn_1, clockNamePrefixer.auto.clock_name_prefixer_out_2 connect x1_allClockGroupsNodeIn_2, clockNamePrefixer.auto.clock_name_prefixer_out_3 connect x1_allClockGroupsNodeIn_3, clockNamePrefixer.auto.clock_name_prefixer_out_4 connect x1_allClockGroupsNodeIn_4, clockNamePrefixer.auto.clock_name_prefixer_out_5 connect aggregator.auto.in, frequencySpecifier.auto.frequency_specifier_out connect frequencySpecifier.auto.frequency_specifier_in, clockGroupCombiner.auto.clock_group_combiner_out connect clockGroupCombiner.auto.clock_group_combiner_in, chipyard_prcictrl_domain.auto.resetSynchronizer_out connect clockTapIn, clockTapNode.auto.out connect auto.cbus_fixedClockNode_anon_out, cbus.auto.fixedClockNode_anon_out_5 connect auto.mbus_fixedClockNode_anon_out, mbus.auto.fixedClockNode_anon_out_1 connect chipyard_prcictrl_domain.auto.reset_setter_clock_in, auto.chipyard_prcictrl_domain_reset_setter_clock_in connect tlDM.io.tl_reset, domainIn.reset connect tlDM.io.tl_clock, domainIn.clock connect tlDM.io.hartIsInReset[0], resetctrl.hartIsInReset[0] connect tlDM.io.debug_reset, debug.reset connect tlDM.io.debug_clock, debug.clock connect debug.ndreset, tlDM.io.ctrl.ndreset connect debug.dmactive, tlDM.io.ctrl.dmactive connect tlDM.io.ctrl.dmactiveAck, debug.dmactiveAck connect tlDM.io.ctrl.debugUnavail[0], UInt<1>(0h0) inst dtm of DebugTransportModuleJTAG connect dtm.io.jtag, debug.systemjtag.jtag connect dtm.io.jtag_clock, debug.systemjtag.jtag.TCK connect dtm.io.jtag_reset, debug.systemjtag.reset connect dtm.io.jtag_mfr_id, debug.systemjtag.mfr_id connect dtm.io.jtag_part_number, debug.systemjtag.part_number connect dtm.io.jtag_version, debug.systemjtag.version connect dtm.rf_reset, debug.systemjtag.reset connect tlDM.io.dmi.dmi, dtm.io.dmi connect tlDM.io.dmi.dmiClock, debug.systemjtag.jtag.TCK connect tlDM.io.dmi.dmiReset, debug.systemjtag.reset connect mem_axi4.`0`, memAXI4NodeIn connect bootROMResetVectorSourceNodeOut, UInt<17>(0h10000) connect cbus.custom_boot, custom_boot connect serial_tl_domain.serial_tl_0.clock_in, serial_tl_0.clock_in connect serial_tl_0.out.bits, serial_tl_domain.serial_tl_0.out.bits connect serial_tl_0.out.valid, serial_tl_domain.serial_tl_0.out.valid connect serial_tl_domain.serial_tl_0.out.ready, serial_tl_0.out.ready connect serial_tl_domain.serial_tl_0.in, serial_tl_0.in connect serial_tl_0_debug, serial_tl_domain.serial_tl_0_debug connect uart_0, ioNodeIn connect icenic_domain.nic.pauser, nic.bits.pauser connect icenic_domain.nic.rlimit, nic.bits.rlimit connect icenic_domain.nic.macAddr, nic.bits.macAddr connect nic.bits.out, icenic_domain.nic.out connect icenic_domain.nic.in, nic.bits.in connect nic.clock, icenic_domain.clock connect clock_tap, clockTapIn.clock regreset int_rtc_tick_c_value : UInt<10>, clint_domain.clock, clint_domain.reset, UInt<10>(0h0) wire int_rtc_tick : UInt<1> connect int_rtc_tick, UInt<1>(0h0) when UInt<1>(0h1) : node int_rtc_tick_wrap_wrap = eq(int_rtc_tick_c_value, UInt<10>(0h3e7)) node _int_rtc_tick_wrap_value_T = add(int_rtc_tick_c_value, UInt<1>(0h1)) node _int_rtc_tick_wrap_value_T_1 = tail(_int_rtc_tick_wrap_value_T, 1) connect int_rtc_tick_c_value, _int_rtc_tick_wrap_value_T_1 when int_rtc_tick_wrap_wrap : connect int_rtc_tick_c_value, UInt<1>(0h0) connect int_rtc_tick, int_rtc_tick_wrap_wrap connect clint_domain.tick, int_rtc_tick extmodule GenericDigitalInIOCell : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell extmodule GenericDigitalOutIOCell : output pad : UInt<1> input o : UInt<1> input oe : UInt<1> defname = GenericDigitalOutIOCell extmodule GenericDigitalInIOCell_1 : input pad : UInt<1> output i : UInt<1> input ie : UInt<1> defname = GenericDigitalInIOCell	module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output nic_clock, // @[NIC.scala:574:24] input nic_bits_in_valid, // @[NIC.scala:574:24] input [63:0] nic_bits_in_bits_data, // @[NIC.scala:574:24] input [7:0] nic_bits_in_bits_keep, // @[NIC.scala:574:24] input nic_bits_in_bits_last, // @[NIC.scala:574:24] output nic_bits_out_valid, // @[NIC.scala:574:24] output [63:0] nic_bits_out_bits_data, // @[NIC.scala:574:24] output [7:0] nic_bits_out_bits_keep, // @[NIC.scala:574:24] output nic_bits_out_bits_last, // @[NIC.scala:574:24] input [47:0] nic_bits_macAddr, // @[NIC.scala:574:24] input [7:0] nic_bits_rlimit_inc, // @[NIC.scala:574:24] input [7:0] nic_bits_rlimit_period, // @[NIC.scala:574:24] input [7:0] nic_bits_rlimit_size, // @[NIC.scala:574:24] input [15:0] nic_bits_pauser_threshold, // @[NIC.scala:574:24] input [15:0] nic_bits_pauser_quanta, // @[NIC.scala:574:24] input [15:0] nic_bits_pauser_refresh, // @[NIC.scala:574:24] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire [63:0] nexus_auto_out_time; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_custom_rob_empty; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_time; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_custom_rob_empty; // @[BundleBridgeNexus.scala:20:9] wire ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [7:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _icenic_domain_auto_icenic_dma_out_1_a_valid; // @[BusWrapper.scala:89:28] wire [2:0] _icenic_domain_auto_icenic_dma_out_1_a_bits_opcode; // @[BusWrapper.scala:89:28] wire [3:0] _icenic_domain_auto_icenic_dma_out_1_a_bits_size; // @[BusWrapper.scala:89:28] wire [2:0] _icenic_domain_auto_icenic_dma_out_1_a_bits_source; // @[BusWrapper.scala:89:28] wire [31:0] _icenic_domain_auto_icenic_dma_out_1_a_bits_address; // @[BusWrapper.scala:89:28] wire [7:0] _icenic_domain_auto_icenic_dma_out_1_a_bits_mask; // @[BusWrapper.scala:89:28] wire [63:0] _icenic_domain_auto_icenic_dma_out_1_a_bits_data; // @[BusWrapper.scala:89:28] wire _icenic_domain_auto_icenic_dma_out_1_d_ready; // @[BusWrapper.scala:89:28] wire _icenic_domain_auto_icenic_dma_out_0_a_valid; // @[BusWrapper.scala:89:28] wire [3:0] _icenic_domain_auto_icenic_dma_out_0_a_bits_size; // @[BusWrapper.scala:89:28] wire [2:0] _icenic_domain_auto_icenic_dma_out_0_a_bits_source; // @[BusWrapper.scala:89:28] wire [31:0] _icenic_domain_auto_icenic_dma_out_0_a_bits_address; // @[BusWrapper.scala:89:28] wire [7:0] _icenic_domain_auto_icenic_dma_out_0_a_bits_mask; // @[BusWrapper.scala:89:28] wire _icenic_domain_auto_icenic_mmio_in_a_ready; // @[BusWrapper.scala:89:28] wire _icenic_domain_auto_icenic_mmio_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _icenic_domain_auto_icenic_mmio_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _icenic_domain_auto_icenic_mmio_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _icenic_domain_auto_icenic_mmio_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _icenic_domain_auto_icenic_mmio_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [11:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_serial_tl_0_debug_ser_busy; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_serial_tl_0_debug_des_busy; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [4:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [11:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [15:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [127:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [4:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [127:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [11:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26] wire [4:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _fbus_auto_coupler_from_IceNIC_tl_in_1_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_IceNIC_tl_in_1_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_size; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_source; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_IceNIC_tl_in_0_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_IceNIC_tl_in_0_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_size; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_source; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [5:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26] wire [15:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26] wire [127:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26] wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_2_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_2_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26] wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock; // @[DigitalTop.scala:47:7] wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset; // @[DigitalTop.scala:47:7] wire resetctrl_hartIsInReset_0_0 = resetctrl_hartIsInReset_0; // @[DigitalTop.scala:47:7] wire debug_clock_0 = debug_clock; // @[DigitalTop.scala:47:7] wire debug_reset_0 = debug_reset; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TCK_0 = debug_systemjtag_jtag_TCK; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TMS_0 = debug_systemjtag_jtag_TMS; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDI_0 = debug_systemjtag_jtag_TDI; // @[DigitalTop.scala:47:7] wire debug_systemjtag_reset_0 = debug_systemjtag_reset; // @[DigitalTop.scala:47:7] wire debug_dmactiveAck_0 = debug_dmactiveAck; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_ready_0 = mem_axi4_0_aw_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_ready_0 = mem_axi4_0_w_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_b_valid_0 = mem_axi4_0_b_valid; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_b_bits_id_0 = mem_axi4_0_b_bits_id; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_b_bits_resp_0 = mem_axi4_0_b_bits_resp; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_ready_0 = mem_axi4_0_ar_ready; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_valid_0 = mem_axi4_0_r_valid; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_r_bits_id_0 = mem_axi4_0_r_bits_id; // @[DigitalTop.scala:47:7] wire [63:0] mem_axi4_0_r_bits_data_0 = mem_axi4_0_r_bits_data; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_r_bits_resp_0 = mem_axi4_0_r_bits_resp; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_bits_last_0 = mem_axi4_0_r_bits_last; // @[DigitalTop.scala:47:7] wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[DigitalTop.scala:47:7] wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[DigitalTop.scala:47:7] wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[DigitalTop.scala:47:7] wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[DigitalTop.scala:47:7] wire uart_0_rxd_0 = uart_0_rxd; // @[DigitalTop.scala:47:7] wire nic_bits_in_valid_0 = nic_bits_in_valid; // @[DigitalTop.scala:47:7] wire [63:0] nic_bits_in_bits_data_0 = nic_bits_in_bits_data; // @[DigitalTop.scala:47:7] wire [7:0] nic_bits_in_bits_keep_0 = nic_bits_in_bits_keep; // @[DigitalTop.scala:47:7] wire nic_bits_in_bits_last_0 = nic_bits_in_bits_last; // @[DigitalTop.scala:47:7] wire [47:0] nic_bits_macAddr_0 = nic_bits_macAddr; // @[DigitalTop.scala:47:7] wire [7:0] nic_bits_rlimit_inc_0 = nic_bits_rlimit_inc; // @[DigitalTop.scala:47:7] wire [7:0] nic_bits_rlimit_period_0 = nic_bits_rlimit_period; // @[DigitalTop.scala:47:7] wire [7:0] nic_bits_rlimit_size_0 = nic_bits_rlimit_size; // @[DigitalTop.scala:47:7] wire [15:0] nic_bits_pauser_threshold_0 = nic_bits_pauser_threshold; // @[DigitalTop.scala:47:7] wire [15:0] nic_bits_pauser_quanta_0 = nic_bits_pauser_quanta; // @[DigitalTop.scala:47:7] wire [15:0] nic_bits_pauser_refresh_0 = nic_bits_pauser_refresh; // @[DigitalTop.scala:47:7] wire [10:0] debug_systemjtag_mfr_id = 11'h0; // @[DigitalTop.scala:47:7] wire [15:0] debug_systemjtag_part_number = 16'h0; // @[DigitalTop.scala:47:7] wire [3:0] debug_systemjtag_version = 4'h0; // @[DigitalTop.scala:47:7] wire [3:0] nexus_1_auto_in_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_in_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_out_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_auto_out_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9] wire [3:0] nexus_1_nodeIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] nexus_1_nodeIn_priv = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] nexus_1_nodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] nexus_1_nodeOut_priv = 4'h0; // @[MixedNode.scala:542:17] wire [3:0] traceCoreNodesIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17] wire [3:0] traceCoreNodesIn_priv = 4'h0; // @[MixedNode.scala:551:17] wire [31:0] broadcast_auto_in = 32'h10000; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_auto_out = 32'h10000; // @[BundleBridgeNexus.scala:20:9] wire [31:0] broadcast_nodeIn = 32'h10000; // @[MixedNode.scala:551:17] wire [31:0] broadcast_nodeOut = 32'h10000; // @[MixedNode.scala:542:17] wire [31:0] bootROMResetVectorSourceNodeOut = 32'h10000; // @[MixedNode.scala:542:17] wire [39:0] nexus_auto_in_insns_0_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_0_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_1_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_1_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_2_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_in_insns_2_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_0_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_0_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_1_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_1_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_2_iaddr = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_auto_out_insns_2_tval = 40'h0; // @[BundleBridgeNexus.scala:20:9] wire [39:0] nexus_nodeIn_insns_0_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_0_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_1_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_1_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_2_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeIn_insns_2_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] nexus_nodeOut_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_2_iaddr = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] nexus_nodeOut_insns_2_tval = 40'h0; // @[MixedNode.scala:542:17] wire [39:0] traceNodesIn_insns_0_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_0_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_1_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_1_tval = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_2_iaddr = 40'h0; // @[MixedNode.scala:551:17] wire [39:0] traceNodesIn_insns_2_tval = 40'h0; // @[MixedNode.scala:551:17] wire [63:0] nexus_auto_in_insns_0_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_insns_1_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_in_insns_2_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_out_insns_0_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_out_insns_1_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_auto_out_insns_2_cause = 64'h0; // @[BundleBridgeNexus.scala:20:9] wire [63:0] nexus_nodeIn_insns_0_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_insns_1_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_insns_2_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeOut_insns_0_cause = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] nexus_nodeOut_insns_1_cause = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] nexus_nodeOut_insns_2_cause = 64'h0; // @[MixedNode.scala:542:17] wire [63:0] traceNodesIn_insns_0_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] traceNodesIn_insns_1_cause = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] traceNodesIn_insns_2_cause = 64'h0; // @[MixedNode.scala:551:17] wire [2:0] nexus_auto_in_insns_0_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_in_insns_1_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_in_insns_2_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_out_insns_0_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_out_insns_1_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_auto_out_insns_2_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9] wire [2:0] nexus_nodeIn_insns_0_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeIn_insns_1_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeIn_insns_2_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nexus_nodeOut_insns_0_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nexus_nodeOut_insns_1_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nexus_nodeOut_insns_2_priv = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] traceNodesIn_insns_0_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] traceNodesIn_insns_1_priv = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] traceNodesIn_insns_2_priv = 3'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_auto_in_insns_0_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_in_insns_1_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_in_insns_2_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_out_insns_0_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_out_insns_1_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_auto_out_insns_2_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_nodeIn_insns_0_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeIn_insns_1_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeIn_insns_2_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_nodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_nodeOut_insns_1_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_nodeOut_insns_2_insn = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_auto_in_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_in_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_in_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_auto_out_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9] wire [31:0] nexus_1_nodeIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeIn_tval = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeIn_cause = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] nexus_1_nodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_nodeOut_tval = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nexus_1_nodeOut_cause = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] traceCoreNodesIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceCoreNodesIn_tval = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceCoreNodesIn_cause = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceNodesIn_insns_0_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceNodesIn_insns_1_insn = 32'h0; // @[MixedNode.scala:551:17] wire [31:0] traceNodesIn_insns_2_insn = 32'h0; // @[MixedNode.scala:551:17] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire ibus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_auto_in_insns_0_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_0_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_1_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_1_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_1_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_2_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_2_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_in_insns_2_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_0_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_1_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_1_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_1_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_2_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_2_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_auto_out_insns_2_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_nodeIn_insns_0_valid = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_exception = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_0_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_1_valid = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_1_exception = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_1_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_2_valid = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_2_exception = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeIn_insns_2_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire nexus_nodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_1_valid = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_1_exception = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_1_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_2_valid = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_2_exception = 1'h0; // @[MixedNode.scala:542:17] wire nexus_nodeOut_insns_2_interrupt = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_auto_in_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_in_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_out_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_auto_out_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9] wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nexus_1_nodeIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17] wire nexus_1_nodeIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17] wire nexus_1_nodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17] wire nexus_1_nodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17] wire clockNamePrefixer_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockNamePrefixer_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockNamePrefixer__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire frequencySpecifier_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire frequencySpecifier_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire frequencySpecifier__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockTapNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockTapNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockTapNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire tileHaltSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire tileWFISinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire tileCeaseSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreNodesIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17] wire traceCoreNodesIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_0_valid = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_0_exception = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_0_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_1_valid = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_1_exception = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_1_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_2_valid = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_2_exception = 1'h0; // @[MixedNode.scala:551:17] wire traceNodesIn_insns_2_interrupt = 1'h0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_ready = mem_axi4_0_aw_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17] wire [31:0] memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_ready = mem_axi4_0_w_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17] wire [63:0] memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_b_valid = mem_axi4_0_b_valid_0; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_b_bits_id = mem_axi4_0_b_bits_id_0; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_b_bits_resp = mem_axi4_0_b_bits_resp_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_ready = mem_axi4_0_ar_ready_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17] wire [31:0] memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17] wire [7:0] memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17] wire [2:0] memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_valid = mem_axi4_0_r_valid_0; // @[MixedNode.scala:551:17] wire [3:0] memAXI4NodeIn_r_bits_id = mem_axi4_0_r_bits_id_0; // @[MixedNode.scala:551:17] wire [63:0] memAXI4NodeIn_r_bits_data = mem_axi4_0_r_bits_data_0; // @[MixedNode.scala:551:17] wire [1:0] memAXI4NodeIn_r_bits_resp = mem_axi4_0_r_bits_resp_0; // @[MixedNode.scala:551:17] wire memAXI4NodeIn_r_bits_last = mem_axi4_0_r_bits_last_0; // @[MixedNode.scala:551:17] wire ioNodeIn_txd; // @[MixedNode.scala:551:17] wire ioNodeIn_rxd = uart_0_rxd_0; // @[MixedNode.scala:551:17] wire auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] wire auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] wire auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] wire auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7] wire debug_systemjtag_jtag_TDO_driven; // @[DigitalTop.scala:47:7] wire debug_ndreset; // @[DigitalTop.scala:47:7] wire debug_dmactive_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7] wire [31:0] mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7] wire [63:0] mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7] wire [31:0] mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7] wire [7:0] mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7] wire [1:0] mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7] wire [2:0] mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7] wire [3:0] mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7] wire mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7] wire serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7] wire [31:0] serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7] wire serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7] wire uart_0_txd_0; // @[DigitalTop.scala:47:7] wire [63:0] nic_bits_out_bits_data_0; // @[DigitalTop.scala:47:7] wire [7:0] nic_bits_out_bits_keep_0; // @[DigitalTop.scala:47:7] wire nic_bits_out_bits_last_0; // @[DigitalTop.scala:47:7] wire nic_bits_out_valid_0; // @[DigitalTop.scala:47:7] wire nic_clock_0; // @[DigitalTop.scala:47:7] wire clockTapIn_clock; // @[MixedNode.scala:551:17] wire ibus_clockNodeIn_clock = ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_in_1_0; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_in_1_1; // @[ClockDomain.scala:14:9] wire ibus_clockNodeIn_reset = ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_in_0_0; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_out_0; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_out_1; // @[ClockDomain.scala:14:9] wire ibus_auto_int_bus_anon_out_2; // @[ClockDomain.scala:14:9] wire ibus_childClock; // @[LazyModuleImp.scala:155:31] wire ibus_childReset; // @[LazyModuleImp.scala:158:31] assign ibus_childClock = ibus_clockNodeIn_clock; // @[MixedNode.scala:551:17] assign ibus_childReset = ibus_clockNodeIn_reset; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeIn_time = nexus_auto_in_time; // @[MixedNode.scala:551:17] wire nexus_nodeIn_custom_rob_empty = nexus_auto_in_custom_rob_empty; // @[MixedNode.scala:551:17] wire [63:0] nexus_nodeOut_time; // @[MixedNode.scala:542:17] wire nexus_nodeOut_custom_rob_empty; // @[MixedNode.scala:542:17] wire [63:0] traceNodesIn_time = nexus_auto_out_time; // @[MixedNode.scala:551:17] wire traceNodesIn_custom_rob_empty = nexus_auto_out_custom_rob_empty; // @[MixedNode.scala:551:17] assign nexus_nodeOut_time = nexus_nodeIn_time; // @[MixedNode.scala:542:17, :551:17] assign nexus_nodeOut_custom_rob_empty = nexus_nodeIn_custom_rob_empty; // @[MixedNode.scala:542:17, :551:17] assign nexus_auto_out_time = nexus_nodeOut_time; // @[MixedNode.scala:542:17] assign nexus_auto_out_custom_rob_empty = nexus_nodeOut_custom_rob_empty; // @[MixedNode.scala:542:17] wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_3_member_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_3_member_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_2_member_mbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_2_member_mbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_1_member_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_1_member_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_member_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeIn_member_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_1_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_1_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset; // @[MixedNode.scala:551:17] wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeIn_member_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[MixedNode.scala:551:17] wire allClockGroupsNodeIn_member_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[MixedNode.scala:551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_3_member_mbus_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_4_member_cbus_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_clockNamePrefixerIn_5_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_1_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_mbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_cbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_clock = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] assign clockNamePrefixer_auto_clock_name_prefixer_out_5_member_clockTapNode_clock_tap_reset = clockNamePrefixer_x1_clockNamePrefixerOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[MixedNode.scala:551:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17] wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25] wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_mbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_1_reset; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17] assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17] wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock = clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] wire x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17] wire clockTapNode_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset = clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] wire clockTapNode_nodeOut_reset; // @[MixedNode.scala:542:17] assign clockTapIn_clock = clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockTapIn_reset = clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_out_clock = clockTapNode_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_out_reset = clockTapNode_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockTapNode_nodeOut_clock = clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign clockTapNode_nodeOut_reset = clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] wire allClockGroupsNodeOut_member_sbus_1_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_1_reset; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17] wire allClockGroupsNodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_2_member_mbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_2_member_mbus_0_reset; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_3_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire x1_allClockGroupsNodeOut_3_member_cbus_0_reset; // @[MixedNode.scala:542:17] assign clockTapNode_auto_in_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9] assign clockTapNode_auto_in_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9] assign allClockGroupsNodeOut_member_sbus_1_clock = allClockGroupsNodeIn_member_sbus_1_clock; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_1_reset = allClockGroupsNodeIn_member_sbus_1_reset; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_0_clock = allClockGroupsNodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign allClockGroupsNodeOut_member_sbus_0_reset = allClockGroupsNodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_member_pbus_0_clock = x1_allClockGroupsNodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_member_pbus_0_reset = x1_allClockGroupsNodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_1_member_fbus_0_clock = x1_allClockGroupsNodeIn_1_member_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_1_member_fbus_0_reset = x1_allClockGroupsNodeIn_1_member_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_2_member_mbus_0_clock = x1_allClockGroupsNodeIn_2_member_mbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_2_member_mbus_0_reset = x1_allClockGroupsNodeIn_2_member_mbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_3_member_cbus_0_clock = x1_allClockGroupsNodeIn_3_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_3_member_cbus_0_reset = x1_allClockGroupsNodeIn_3_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17] assign x1_allClockGroupsNodeOut_4_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeIn_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17] wire domainIn_clock; // @[MixedNode.scala:551:17] wire domainIn_reset; // @[MixedNode.scala:551:17] wire debugNodesIn_sync_0; // @[MixedNode.scala:551:17] wire debugNodesOut_sync_0; // @[MixedNode.scala:542:17] assign debugNodesOut_sync_0 = debugNodesIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign mem_axi4_0_aw_valid_0 = memAXI4NodeIn_aw_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_id_0 = memAXI4NodeIn_aw_bits_id; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_addr_0 = memAXI4NodeIn_aw_bits_addr; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_len_0 = memAXI4NodeIn_aw_bits_len; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_size_0 = memAXI4NodeIn_aw_bits_size; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_burst_0 = memAXI4NodeIn_aw_bits_burst; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_lock_0 = memAXI4NodeIn_aw_bits_lock; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_cache_0 = memAXI4NodeIn_aw_bits_cache; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_prot_0 = memAXI4NodeIn_aw_bits_prot; // @[MixedNode.scala:551:17] assign mem_axi4_0_aw_bits_qos_0 = memAXI4NodeIn_aw_bits_qos; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_valid_0 = memAXI4NodeIn_w_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_data_0 = memAXI4NodeIn_w_bits_data; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_strb_0 = memAXI4NodeIn_w_bits_strb; // @[MixedNode.scala:551:17] assign mem_axi4_0_w_bits_last_0 = memAXI4NodeIn_w_bits_last; // @[MixedNode.scala:551:17] assign mem_axi4_0_b_ready_0 = memAXI4NodeIn_b_ready; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_valid_0 = memAXI4NodeIn_ar_valid; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_id_0 = memAXI4NodeIn_ar_bits_id; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_addr_0 = memAXI4NodeIn_ar_bits_addr; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_len_0 = memAXI4NodeIn_ar_bits_len; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_size_0 = memAXI4NodeIn_ar_bits_size; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_burst_0 = memAXI4NodeIn_ar_bits_burst; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_lock_0 = memAXI4NodeIn_ar_bits_lock; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_cache_0 = memAXI4NodeIn_ar_bits_cache; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_prot_0 = memAXI4NodeIn_ar_bits_prot; // @[MixedNode.scala:551:17] assign mem_axi4_0_ar_bits_qos_0 = memAXI4NodeIn_ar_bits_qos; // @[MixedNode.scala:551:17] assign mem_axi4_0_r_ready_0 = memAXI4NodeIn_r_ready; // @[MixedNode.scala:551:17] wire intXingIn_sync_0; // @[MixedNode.scala:551:17] wire intXingOut_sync_0; // @[MixedNode.scala:542:17] assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign uart_0_txd_0 = ioNodeIn_txd; // @[MixedNode.scala:551:17] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24] wire int_rtc_tick; // @[Counter.scala:117:24] assign int_rtc_tick_wrap_wrap = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] assign int_rtc_tick = int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24, :117:24] wire [10:0] _int_rtc_tick_wrap_value_T = {1'h0, int_rtc_tick_c_value} + 11'h1; // @[Counter.scala:61:40, :77:24] wire [9:0] _int_rtc_tick_wrap_value_T_1 = _int_rtc_tick_wrap_value_T[9:0]; // @[Counter.scala:77:24] always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick_wrap_wrap ? 10'h0 : _int_rtc_tick_wrap_value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge) IntXbar_i2_o1 ibus_int_bus ( // @[InterruptBus.scala:19:27] .auto_anon_in_1_0 (ibus_auto_int_bus_anon_in_1_0), // @[ClockDomain.scala:14:9] .auto_anon_in_1_1 (ibus_auto_int_bus_anon_in_1_1), // @[ClockDomain.scala:14:9] .auto_anon_in_0_0 (ibus_auto_int_bus_anon_in_0_0), // @[ClockDomain.scala:14:9] .auto_anon_out_0 (ibus_auto_int_bus_anon_out_0), .auto_anon_out_1 (ibus_auto_int_bus_anon_out_1), .auto_anon_out_2 (ibus_auto_int_bus_anon_out_2) ); // @[InterruptBus.scala:19:27] SystemBus sbus ( // @[SystemBus.scala:31:26] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_b_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_c_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt), .auto_coupler_from_boom_tile_tl_master_clock_xing_in_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_e_valid), // @[HasTiles.scala:163:38] .auto_coupler_from_boom_tile_tl_master_clock_xing_in_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink), // @[HasTiles.scala:163:38] .auto_coupler_to_bus_named_coh_widget_anon_out_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), .auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), .auto_coupler_to_bus_named_coh_widget_anon_out_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), .auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), .auto_coupler_to_bus_named_coh_widget_anon_out_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), .auto_coupler_to_bus_named_coh_widget_anon_out_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_coh_widget_anon_out_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), .auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), .auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), .auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid (_fbus_auto_bus_xing_out_a_valid), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready (_fbus_auto_bus_xing_out_d_ready), // @[FrontBus.scala:23:26] .auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), .auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready (_cbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid (_cbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_fixedClockNode_anon_out_2_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), .auto_fixedClockNode_anon_out_2_reset (_sbus_auto_fixedClockNode_anon_out_2_reset), .auto_fixedClockNode_anon_out_1_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_sbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (ibus_auto_clock_in_clock), .auto_fixedClockNode_anon_out_0_reset (ibus_auto_clock_in_reset), .auto_sbus_clock_groups_in_member_sbus_1_clock (allClockGroupsNodeOut_member_sbus_1_clock), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_1_reset (allClockGroupsNodeOut_member_sbus_1_reset), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_0_clock (allClockGroupsNodeOut_member_sbus_0_clock), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_in_member_sbus_0_reset (allClockGroupsNodeOut_member_sbus_0_reset), // @[MixedNode.scala:542:17] .auto_sbus_clock_groups_out_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), .auto_sbus_clock_groups_out_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) ); // @[SystemBus.scala:31:26] PeripheryBus_pbus pbus ( // @[PeripheryBus.scala:37:26] .auto_coupler_to_IceNIC_fragmenter_anon_out_a_ready (_icenic_domain_auto_icenic_mmio_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_IceNIC_fragmenter_anon_out_a_valid (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_valid), .auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_opcode (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_param (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_param), .auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_size (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_size), .auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_source (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_source), .auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_address (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_address), .auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_mask (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_data (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_data), .auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_corrupt (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_IceNIC_fragmenter_anon_out_d_ready (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_d_ready), .auto_coupler_to_IceNIC_fragmenter_anon_out_d_valid (_icenic_domain_auto_icenic_mmio_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_IceNIC_fragmenter_anon_out_d_bits_opcode (_icenic_domain_auto_icenic_mmio_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_IceNIC_fragmenter_anon_out_d_bits_size (_icenic_domain_auto_icenic_mmio_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_IceNIC_fragmenter_anon_out_d_bits_source (_icenic_domain_auto_icenic_mmio_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_IceNIC_fragmenter_anon_out_d_bits_data (_icenic_domain_auto_icenic_mmio_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_device_named_uart_0_control_xing_out_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), .auto_coupler_to_device_named_uart_0_control_xing_out_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), .auto_coupler_to_device_named_uart_0_control_xing_out_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), // @[UART.scala:270:44] .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), // @[UART.scala:270:44] .auto_fixedClockNode_anon_out_1_clock (_pbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_pbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (_pbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_pbus_auto_fixedClockNode_anon_out_0_reset), .auto_pbus_clock_groups_in_member_pbus_0_clock (x1_allClockGroupsNodeOut_member_pbus_0_clock), // @[MixedNode.scala:542:17] .auto_pbus_clock_groups_in_member_pbus_0_reset (x1_allClockGroupsNodeOut_member_pbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_pbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_bus_xing_in_d_valid (_pbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt) ); // @[PeripheryBus.scala:37:26] FrontBus fbus ( // @[FrontBus.scala:23:26] .auto_coupler_from_IceNIC_tl_in_1_a_ready (_fbus_auto_coupler_from_IceNIC_tl_in_1_a_ready), .auto_coupler_from_IceNIC_tl_in_1_a_valid (_icenic_domain_auto_icenic_dma_out_1_a_valid), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_1_a_bits_opcode (_icenic_domain_auto_icenic_dma_out_1_a_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_1_a_bits_size (_icenic_domain_auto_icenic_dma_out_1_a_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_1_a_bits_source (_icenic_domain_auto_icenic_dma_out_1_a_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_1_a_bits_address (_icenic_domain_auto_icenic_dma_out_1_a_bits_address), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_1_a_bits_mask (_icenic_domain_auto_icenic_dma_out_1_a_bits_mask), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_1_a_bits_data (_icenic_domain_auto_icenic_dma_out_1_a_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_1_d_ready (_icenic_domain_auto_icenic_dma_out_1_d_ready), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_1_d_valid (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_valid), .auto_coupler_from_IceNIC_tl_in_1_d_bits_opcode (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_opcode), .auto_coupler_from_IceNIC_tl_in_1_d_bits_param (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_param), .auto_coupler_from_IceNIC_tl_in_1_d_bits_size (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_size), .auto_coupler_from_IceNIC_tl_in_1_d_bits_source (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_source), .auto_coupler_from_IceNIC_tl_in_1_d_bits_sink (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_sink), .auto_coupler_from_IceNIC_tl_in_1_d_bits_denied (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_denied), .auto_coupler_from_IceNIC_tl_in_1_d_bits_data (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_data), .auto_coupler_from_IceNIC_tl_in_1_d_bits_corrupt (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_corrupt), .auto_coupler_from_IceNIC_tl_in_0_a_ready (_fbus_auto_coupler_from_IceNIC_tl_in_0_a_ready), .auto_coupler_from_IceNIC_tl_in_0_a_valid (_icenic_domain_auto_icenic_dma_out_0_a_valid), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_0_a_bits_size (_icenic_domain_auto_icenic_dma_out_0_a_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_0_a_bits_source (_icenic_domain_auto_icenic_dma_out_0_a_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_0_a_bits_address (_icenic_domain_auto_icenic_dma_out_0_a_bits_address), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_0_a_bits_mask (_icenic_domain_auto_icenic_dma_out_0_a_bits_mask), // @[BusWrapper.scala:89:28] .auto_coupler_from_IceNIC_tl_in_0_d_valid (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_valid), .auto_coupler_from_IceNIC_tl_in_0_d_bits_opcode (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_opcode), .auto_coupler_from_IceNIC_tl_in_0_d_bits_param (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_param), .auto_coupler_from_IceNIC_tl_in_0_d_bits_size (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_size), .auto_coupler_from_IceNIC_tl_in_0_d_bits_source (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_source), .auto_coupler_from_IceNIC_tl_in_0_d_bits_sink (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_sink), .auto_coupler_from_IceNIC_tl_in_0_d_bits_denied (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_denied), .auto_coupler_from_IceNIC_tl_in_0_d_bits_data (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_data), .auto_coupler_from_IceNIC_tl_in_0_d_bits_corrupt (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_corrupt), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), // @[PeripheryTLSerial.scala:116:38] .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), .auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), .auto_coupler_from_debug_sb_widget_anon_in_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), .auto_coupler_from_debug_sb_widget_anon_in_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), // @[Periphery.scala:88:26] .auto_coupler_from_debug_sb_widget_anon_in_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), .auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), .auto_fixedClockNode_anon_out_clock (_fbus_auto_fixedClockNode_anon_out_clock), .auto_fixedClockNode_anon_out_reset (_fbus_auto_fixedClockNode_anon_out_reset), .auto_fbus_clock_groups_in_member_fbus_0_clock (x1_allClockGroupsNodeOut_1_member_fbus_0_clock), // @[MixedNode.scala:542:17] .auto_fbus_clock_groups_in_member_fbus_0_reset (x1_allClockGroupsNodeOut_1_member_fbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_out_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), // @[SystemBus.scala:31:26] .auto_bus_xing_out_a_valid (_fbus_auto_bus_xing_out_a_valid), .auto_bus_xing_out_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), .auto_bus_xing_out_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), .auto_bus_xing_out_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), .auto_bus_xing_out_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), .auto_bus_xing_out_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), .auto_bus_xing_out_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), .auto_bus_xing_out_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), .auto_bus_xing_out_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), .auto_bus_xing_out_d_ready (_fbus_auto_bus_xing_out_d_ready), .auto_bus_xing_out_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), // @[SystemBus.scala:31:26] .auto_bus_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt) // @[SystemBus.scala:31:26] ); // @[FrontBus.scala:23:26] PeripheryBus_cbus cbus ( // @[PeripheryBus.scala:37:26] .auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), .auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), .auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), .auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), .auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_bootrom_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), .auto_coupler_to_bootrom_fragmenter_anon_out_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_debug_fragmenter_anon_out_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), .auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_debug_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), .auto_coupler_to_debug_fragmenter_anon_out_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), // @[Periphery.scala:88:26] .auto_coupler_to_debug_fragmenter_anon_out_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), // @[Periphery.scala:88:26] .auto_coupler_to_plic_fragmenter_anon_out_a_ready (_plic_domain_auto_plic_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), .auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_plic_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), .auto_coupler_to_plic_fragmenter_anon_out_d_valid (_plic_domain_auto_plic_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_plic_fragmenter_anon_out_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_a_ready (_clint_domain_auto_clint_in_a_ready), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), .auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), .auto_coupler_to_clint_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), .auto_coupler_to_clint_fragmenter_anon_out_d_valid (_clint_domain_auto_clint_in_d_valid), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), // @[BusWrapper.scala:89:28] .auto_coupler_to_clint_fragmenter_anon_out_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), // @[BusWrapper.scala:89:28] .auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready (_pbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid (_pbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26] .auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_coupler_to_l2_ctrl_buffer_out_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), .auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), .auto_coupler_to_l2_ctrl_buffer_out_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), .auto_coupler_to_l2_ctrl_buffer_out_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_l2_ctrl_buffer_out_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_fixedClockNode_anon_out_5_clock (auto_cbus_fixedClockNode_anon_out_clock_0), .auto_fixedClockNode_anon_out_5_reset (auto_cbus_fixedClockNode_anon_out_reset_0), .auto_fixedClockNode_anon_out_4_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), .auto_fixedClockNode_anon_out_4_reset (_cbus_auto_fixedClockNode_anon_out_4_reset), .auto_fixedClockNode_anon_out_3_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), .auto_fixedClockNode_anon_out_3_reset (_cbus_auto_fixedClockNode_anon_out_3_reset), .auto_fixedClockNode_anon_out_2_clock (domainIn_clock), .auto_fixedClockNode_anon_out_2_reset (domainIn_reset), .auto_fixedClockNode_anon_out_1_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), .auto_fixedClockNode_anon_out_1_reset (_cbus_auto_fixedClockNode_anon_out_1_reset), .auto_fixedClockNode_anon_out_0_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), .auto_cbus_clock_groups_in_member_cbus_0_clock (x1_allClockGroupsNodeOut_3_member_cbus_0_clock), // @[MixedNode.scala:542:17] .auto_cbus_clock_groups_in_member_cbus_0_reset (x1_allClockGroupsNodeOut_3_member_cbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_cbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), // @[SystemBus.scala:31:26] .auto_bus_xing_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), // @[SystemBus.scala:31:26] .auto_bus_xing_in_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), // @[SystemBus.scala:31:26] .auto_bus_xing_in_d_valid (_cbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), .custom_boot (custom_boot) ); // @[PeripheryBus.scala:37:26] MemoryBus mbus ( // @[MemoryBus.scala:30:26] .auto_buffer_out_a_ready (_bank_auto_xbar_anon_in_a_ready), // @[Scratchpad.scala:65:28] .auto_buffer_out_a_valid (_mbus_auto_buffer_out_a_valid), .auto_buffer_out_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), .auto_buffer_out_a_bits_param (_mbus_auto_buffer_out_a_bits_param), .auto_buffer_out_a_bits_size (_mbus_auto_buffer_out_a_bits_size), .auto_buffer_out_a_bits_source (_mbus_auto_buffer_out_a_bits_source), .auto_buffer_out_a_bits_address (_mbus_auto_buffer_out_a_bits_address), .auto_buffer_out_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), .auto_buffer_out_a_bits_data (_mbus_auto_buffer_out_a_bits_data), .auto_buffer_out_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), .auto_buffer_out_d_ready (_mbus_auto_buffer_out_d_ready), .auto_buffer_out_d_valid (_bank_auto_xbar_anon_in_d_valid), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), // @[Scratchpad.scala:65:28] .auto_buffer_out_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), // @[Scratchpad.scala:65:28] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready (memAXI4NodeIn_aw_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid (memAXI4NodeIn_aw_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id (memAXI4NodeIn_aw_bits_id), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr (memAXI4NodeIn_aw_bits_addr), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len (memAXI4NodeIn_aw_bits_len), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size (memAXI4NodeIn_aw_bits_size), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst (memAXI4NodeIn_aw_bits_burst), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock (memAXI4NodeIn_aw_bits_lock), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache (memAXI4NodeIn_aw_bits_cache), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot (memAXI4NodeIn_aw_bits_prot), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos (memAXI4NodeIn_aw_bits_qos), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready (memAXI4NodeIn_w_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid (memAXI4NodeIn_w_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data (memAXI4NodeIn_w_bits_data), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb (memAXI4NodeIn_w_bits_strb), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last (memAXI4NodeIn_w_bits_last), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready (memAXI4NodeIn_b_ready), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid (memAXI4NodeIn_b_valid), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id (memAXI4NodeIn_b_bits_id), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp (memAXI4NodeIn_b_bits_resp), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready (memAXI4NodeIn_ar_ready), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid (memAXI4NodeIn_ar_valid), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id (memAXI4NodeIn_ar_bits_id), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr (memAXI4NodeIn_ar_bits_addr), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len (memAXI4NodeIn_ar_bits_len), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size (memAXI4NodeIn_ar_bits_size), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst (memAXI4NodeIn_ar_bits_burst), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock (memAXI4NodeIn_ar_bits_lock), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache (memAXI4NodeIn_ar_bits_cache), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot (memAXI4NodeIn_ar_bits_prot), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos (memAXI4NodeIn_ar_bits_qos), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready (memAXI4NodeIn_r_ready), .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid (memAXI4NodeIn_r_valid), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id (memAXI4NodeIn_r_bits_id), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data (memAXI4NodeIn_r_bits_data), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp (memAXI4NodeIn_r_bits_resp), // @[MixedNode.scala:551:17] .auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last (memAXI4NodeIn_r_bits_last), // @[MixedNode.scala:551:17] .auto_fixedClockNode_anon_out_1_clock (auto_mbus_fixedClockNode_anon_out_clock_0), .auto_fixedClockNode_anon_out_1_reset (auto_mbus_fixedClockNode_anon_out_reset_0), .auto_fixedClockNode_anon_out_0_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), .auto_fixedClockNode_anon_out_0_reset (_mbus_auto_fixedClockNode_anon_out_0_reset), .auto_mbus_clock_groups_in_member_mbus_0_clock (x1_allClockGroupsNodeOut_2_member_mbus_0_clock), // @[MixedNode.scala:542:17] .auto_mbus_clock_groups_in_member_mbus_0_reset (x1_allClockGroupsNodeOut_2_member_mbus_0_reset), // @[MixedNode.scala:542:17] .auto_bus_xing_in_a_ready (_mbus_auto_bus_xing_in_a_ready), .auto_bus_xing_in_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), // @[BankedCoherenceParams.scala:56:31] .auto_bus_xing_in_d_valid (_mbus_auto_bus_xing_in_d_valid), .auto_bus_xing_in_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), .auto_bus_xing_in_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), .auto_bus_xing_in_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), .auto_bus_xing_in_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), .auto_bus_xing_in_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), .auto_bus_xing_in_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), .auto_bus_xing_in_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), .auto_bus_xing_in_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt) ); // @[MemoryBus.scala:30:26] CoherenceManagerWrapper coh_wrapper ( // @[BankedCoherenceParams.scala:56:31] .auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready (_mbus_auto_bus_xing_in_a_ready), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data), .auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt), .auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready (_coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready), .auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid (_mbus_auto_bus_xing_in_d_valid), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode (_mbus_auto_bus_xing_in_d_bits_opcode), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param (_mbus_auto_bus_xing_in_d_bits_param), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size (_mbus_auto_bus_xing_in_d_bits_size), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source (_mbus_auto_bus_xing_in_d_bits_source), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink (_mbus_auto_bus_xing_in_d_bits_sink), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied (_mbus_auto_bus_xing_in_d_bits_denied), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data (_mbus_auto_bus_xing_in_d_bits_data), // @[MemoryBus.scala:30:26] .auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt (_mbus_auto_bus_xing_in_d_bits_corrupt), // @[MemoryBus.scala:30:26] .auto_coherent_jbar_anon_in_a_ready (_coh_wrapper_auto_coherent_jbar_anon_in_a_ready), .auto_coherent_jbar_anon_in_a_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_b_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_b_valid (_coh_wrapper_auto_coherent_jbar_anon_in_b_valid), .auto_coherent_jbar_anon_in_b_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param), .auto_coherent_jbar_anon_in_b_bits_address (_coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address), .auto_coherent_jbar_anon_in_c_ready (_coh_wrapper_auto_coherent_jbar_anon_in_c_ready), .auto_coherent_jbar_anon_in_c_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_opcode (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_param (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_size (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_source (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_address (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_data (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_c_bits_corrupt (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_d_ready (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_d_valid (_coh_wrapper_auto_coherent_jbar_anon_in_d_valid), .auto_coherent_jbar_anon_in_d_bits_opcode (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode), .auto_coherent_jbar_anon_in_d_bits_param (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param), .auto_coherent_jbar_anon_in_d_bits_size (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size), .auto_coherent_jbar_anon_in_d_bits_source (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source), .auto_coherent_jbar_anon_in_d_bits_sink (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink), .auto_coherent_jbar_anon_in_d_bits_denied (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied), .auto_coherent_jbar_anon_in_d_bits_data (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data), .auto_coherent_jbar_anon_in_d_bits_corrupt (_coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt), .auto_coherent_jbar_anon_in_e_valid (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid), // @[SystemBus.scala:31:26] .auto_coherent_jbar_anon_in_e_bits_sink (_sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink), // @[SystemBus.scala:31:26] .auto_l2_ctrls_ctrl_in_a_ready (_coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready), .auto_l2_ctrls_ctrl_in_a_valid (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_opcode (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_param (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_size (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_source (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_address (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_mask (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_data (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_a_bits_corrupt (_cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_d_ready (_cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_l2_ctrls_ctrl_in_d_valid (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid), .auto_l2_ctrls_ctrl_in_d_bits_opcode (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode), .auto_l2_ctrls_ctrl_in_d_bits_size (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size), .auto_l2_ctrls_ctrl_in_d_bits_source (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source), .auto_l2_ctrls_ctrl_in_d_bits_data (_coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data), .auto_coh_clock_groups_in_member_coh_0_clock (_sbus_auto_sbus_clock_groups_out_member_coh_0_clock), // @[SystemBus.scala:31:26] .auto_coh_clock_groups_in_member_coh_0_reset (_sbus_auto_sbus_clock_groups_out_member_coh_0_reset) // @[SystemBus.scala:31:26] ); // @[BankedCoherenceParams.scala:56:31] TilePRCIDomain tile_prci_domain ( // @[HasTiles.scala:163:38] .auto_intsink_in_sync_0 (debugNodesOut_sync_0), // @[MixedNode.scala:542:17] .auto_element_reset_domain_boom_tile_trace_source_out_time (nexus_auto_in_time), .auto_element_reset_domain_boom_tile_trace_source_out_custom_rob_empty (nexus_auto_in_custom_rob_empty), .auto_element_reset_domain_boom_tile_hartid_in (_tileHartIdNexusNode_auto_out), // @[HasTiles.scala:75:39] .auto_int_in_clock_xing_in_2_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_0_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), // @[BusWrapper.scala:89:28] .auto_int_in_clock_xing_in_0_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), // @[BusWrapper.scala:89:28] .auto_tl_master_clock_xing_out_a_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_a_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid), .auto_tl_master_clock_xing_out_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode), .auto_tl_master_clock_xing_out_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param), .auto_tl_master_clock_xing_out_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size), .auto_tl_master_clock_xing_out_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source), .auto_tl_master_clock_xing_out_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address), .auto_tl_master_clock_xing_out_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask), .auto_tl_master_clock_xing_out_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data), .auto_tl_master_clock_xing_out_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt), .auto_tl_master_clock_xing_out_b_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_b_ready), .auto_tl_master_clock_xing_out_b_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_b_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_b_bits_address (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_b_bits_address), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_c_ready (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_c_ready), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_c_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_c_valid), .auto_tl_master_clock_xing_out_c_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode), .auto_tl_master_clock_xing_out_c_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param), .auto_tl_master_clock_xing_out_c_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size), .auto_tl_master_clock_xing_out_c_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source), .auto_tl_master_clock_xing_out_c_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address), .auto_tl_master_clock_xing_out_c_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data), .auto_tl_master_clock_xing_out_c_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt), .auto_tl_master_clock_xing_out_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready), .auto_tl_master_clock_xing_out_d_valid (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_valid), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_opcode (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_param (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_param), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_size (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_size), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_source (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_source), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_sink (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_sink), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_denied (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_denied), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_data (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_data), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_boom_tile_tl_master_clock_xing_in_d_bits_corrupt), // @[SystemBus.scala:31:26] .auto_tl_master_clock_xing_out_e_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_e_valid), .auto_tl_master_clock_xing_out_e_bits_sink (_tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink), .auto_tap_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), // @[SystemBus.scala:31:26] .auto_tap_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_1_reset) // @[SystemBus.scala:31:26] ); // @[HasTiles.scala:163:38] IntXbar_i1_o1 xbar (); // @[Xbar.scala:52:26] IntXbar_i1_o1_1 xbar_1 (); // @[Xbar.scala:52:26] IntXbar_i1_o1_2 xbar_2 (); // @[Xbar.scala:52:26] BundleBridgeNexus_UInt1_1 tileHartIdNexusNode ( // @[HasTiles.scala:75:39] .auto_out (_tileHartIdNexusNode_auto_out) ); // @[HasTiles.scala:75:39] CLINTClockSinkDomain clint_domain ( // @[BusWrapper.scala:89:28] .auto_clint_in_a_ready (_clint_domain_auto_clint_in_a_ready), .auto_clint_in_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_clint_in_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_clint_in_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_clint_in_d_valid (_clint_domain_auto_clint_in_d_valid), .auto_clint_in_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), .auto_clint_in_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), .auto_clint_in_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), .auto_clint_in_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), .auto_int_in_clock_xing_out_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), .auto_int_in_clock_xing_out_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), // @[PeripheryBus.scala:37:26] .tick (int_rtc_tick), // @[Counter.scala:117:24] .clock (_clint_domain_clock), .reset (_clint_domain_reset) ); // @[BusWrapper.scala:89:28] PLICClockSinkDomain plic_domain ( // @[BusWrapper.scala:89:28] .auto_plic_int_in_0 (ibus_auto_int_bus_anon_out_0), // @[ClockDomain.scala:14:9] .auto_plic_int_in_1 (ibus_auto_int_bus_anon_out_1), // @[ClockDomain.scala:14:9] .auto_plic_int_in_2 (ibus_auto_int_bus_anon_out_2), // @[ClockDomain.scala:14:9] .auto_plic_in_a_ready (_plic_domain_auto_plic_in_a_ready), .auto_plic_in_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_plic_in_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_plic_in_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_plic_in_d_valid (_plic_domain_auto_plic_in_d_valid), .auto_plic_in_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), .auto_plic_in_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), .auto_plic_in_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), .auto_plic_in_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), .auto_int_in_clock_xing_out_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_1_sync_0), .auto_int_in_clock_xing_out_0_sync_0 (_plic_domain_auto_int_in_clock_xing_out_0_sync_0), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_1_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] TLDebugModule tlDM ( // @[Periphery.scala:88:26] .auto_dmInner_dmInner_sb2tlOpt_out_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), .auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), .auto_dmInner_dmInner_sb2tlOpt_out_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), .auto_dmInner_dmInner_sb2tlOpt_out_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_dmInner_dmInner_tl_in_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), .auto_dmInner_dmInner_tl_in_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_dmInner_dmInner_tl_in_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), .auto_dmInner_dmInner_tl_in_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), .auto_dmInner_dmInner_tl_in_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), .auto_dmInner_dmInner_tl_in_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), .auto_dmInner_dmInner_tl_in_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), .auto_dmOuter_int_out_sync_0 (debugNodesIn_sync_0), .io_debug_clock (debug_clock_0), // @[DigitalTop.scala:47:7] .io_debug_reset (debug_reset_0), // @[DigitalTop.scala:47:7] .io_tl_clock (domainIn_clock), // @[MixedNode.scala:551:17] .io_tl_reset (domainIn_reset), // @[MixedNode.scala:551:17] .io_ctrl_ndreset (debug_ndreset), .io_ctrl_dmactive (debug_dmactive_0), .io_ctrl_dmactiveAck (debug_dmactiveAck_0), // @[DigitalTop.scala:47:7] .io_dmi_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), .io_dmi_dmi_req_valid (_dtm_io_dmi_req_valid), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), // @[Periphery.scala:166:21] .io_dmi_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), // @[Periphery.scala:166:21] .io_dmi_dmi_resp_ready (_dtm_io_dmi_resp_ready), // @[Periphery.scala:166:21] .io_dmi_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), .io_dmi_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), .io_dmi_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), .io_dmi_dmiClock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_dmi_dmiReset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7] .io_hartIsInReset_0 (resetctrl_hartIsInReset_0_0) // @[DigitalTop.scala:47:7] ); // @[Periphery.scala:88:26] DebugCustomXbar debugCustomXbarOpt (); // @[Periphery.scala:80:75] BootROMClockSinkDomain bootrom_domain ( // @[BusWrapper.scala:89:28] .auto_bootrom_in_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), .auto_bootrom_in_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_bootrom_in_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), .auto_bootrom_in_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), .auto_bootrom_in_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), .auto_bootrom_in_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_3_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] ScratchpadBank bank ( // @[Scratchpad.scala:65:28] .auto_xbar_anon_in_a_ready (_bank_auto_xbar_anon_in_a_ready), .auto_xbar_anon_in_a_valid (_mbus_auto_buffer_out_a_valid), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_opcode (_mbus_auto_buffer_out_a_bits_opcode), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_param (_mbus_auto_buffer_out_a_bits_param), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_size (_mbus_auto_buffer_out_a_bits_size), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_source (_mbus_auto_buffer_out_a_bits_source), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_address (_mbus_auto_buffer_out_a_bits_address), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_mask (_mbus_auto_buffer_out_a_bits_mask), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_data (_mbus_auto_buffer_out_a_bits_data), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_a_bits_corrupt (_mbus_auto_buffer_out_a_bits_corrupt), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_d_ready (_mbus_auto_buffer_out_d_ready), // @[MemoryBus.scala:30:26] .auto_xbar_anon_in_d_valid (_bank_auto_xbar_anon_in_d_valid), .auto_xbar_anon_in_d_bits_opcode (_bank_auto_xbar_anon_in_d_bits_opcode), .auto_xbar_anon_in_d_bits_param (_bank_auto_xbar_anon_in_d_bits_param), .auto_xbar_anon_in_d_bits_size (_bank_auto_xbar_anon_in_d_bits_size), .auto_xbar_anon_in_d_bits_source (_bank_auto_xbar_anon_in_d_bits_source), .auto_xbar_anon_in_d_bits_sink (_bank_auto_xbar_anon_in_d_bits_sink), .auto_xbar_anon_in_d_bits_denied (_bank_auto_xbar_anon_in_d_bits_denied), .auto_xbar_anon_in_d_bits_data (_bank_auto_xbar_anon_in_d_bits_data), .auto_xbar_anon_in_d_bits_corrupt (_bank_auto_xbar_anon_in_d_bits_corrupt), .auto_clock_in_clock (_mbus_auto_fixedClockNode_anon_out_0_clock), // @[MemoryBus.scala:30:26] .auto_clock_in_reset (_mbus_auto_fixedClockNode_anon_out_0_reset) // @[MemoryBus.scala:30:26] ); // @[Scratchpad.scala:65:28] SerialTL0ClockSinkDomain serial_tl_domain ( // @[PeripheryTLSerial.scala:116:38] .auto_serdesser_client_out_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), .auto_serdesser_client_out_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), .auto_serdesser_client_out_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), .auto_serdesser_client_out_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), .auto_serdesser_client_out_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), .auto_serdesser_client_out_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), .auto_serdesser_client_out_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), .auto_serdesser_client_out_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), .auto_serdesser_client_out_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), .auto_serdesser_client_out_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), .auto_serdesser_client_out_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), // @[FrontBus.scala:23:26] .auto_serdesser_client_out_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_clock_in_clock (_fbus_auto_fixedClockNode_anon_out_clock), // @[FrontBus.scala:23:26] .auto_clock_in_reset (_fbus_auto_fixedClockNode_anon_out_reset), // @[FrontBus.scala:23:26] .serial_tl_0_in_ready (serial_tl_0_in_ready_0), .serial_tl_0_in_valid (serial_tl_0_in_valid_0), // @[DigitalTop.scala:47:7] .serial_tl_0_in_bits_phit (serial_tl_0_in_bits_phit_0), // @[DigitalTop.scala:47:7] .serial_tl_0_out_ready (serial_tl_0_out_ready_0), // @[DigitalTop.scala:47:7] .serial_tl_0_out_valid (serial_tl_0_out_valid_0), .serial_tl_0_out_bits_phit (serial_tl_0_out_bits_phit_0), .serial_tl_0_clock_in (serial_tl_0_clock_in_0), // @[DigitalTop.scala:47:7] .serial_tl_0_debug_ser_busy (_serial_tl_domain_serial_tl_0_debug_ser_busy), .serial_tl_0_debug_des_busy (_serial_tl_domain_serial_tl_0_debug_des_busy) ); // @[PeripheryTLSerial.scala:116:38] TLUARTClockSinkDomain uartClockDomainWrapper ( // @[UART.scala:270:44] .auto_uart_0_int_xing_out_sync_0 (intXingIn_sync_0), .auto_uart_0_control_xing_in_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), .auto_uart_0_control_xing_in_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_uart_0_control_xing_in_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), .auto_uart_0_control_xing_in_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), .auto_uart_0_control_xing_in_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), .auto_uart_0_control_xing_in_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), .auto_uart_0_control_xing_in_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), .auto_uart_0_io_out_txd (ioNodeIn_txd), .auto_uart_0_io_out_rxd (ioNodeIn_rxd), // @[MixedNode.scala:551:17] .auto_clock_in_clock (_pbus_auto_fixedClockNode_anon_out_0_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_pbus_auto_fixedClockNode_anon_out_0_reset) // @[PeripheryBus.scala:37:26] ); // @[UART.scala:270:44] IntSyncSyncCrossingSink_n1x1_5 intsink ( // @[Crossing.scala:109:29] .auto_in_sync_0 (intXingOut_sync_0), // @[MixedNode.scala:542:17] .auto_out_0 (ibus_auto_int_bus_anon_in_0_0) ); // @[Crossing.scala:109:29] ClockSinkDomain_1 icenic_domain ( // @[BusWrapper.scala:89:28] .auto_icenic_intsink_out_0 (ibus_auto_int_bus_anon_in_1_0), .auto_icenic_intsink_out_1 (ibus_auto_int_bus_anon_in_1_1), .auto_icenic_dma_out_1_a_ready (_fbus_auto_coupler_from_IceNIC_tl_in_1_a_ready), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_1_a_valid (_icenic_domain_auto_icenic_dma_out_1_a_valid), .auto_icenic_dma_out_1_a_bits_opcode (_icenic_domain_auto_icenic_dma_out_1_a_bits_opcode), .auto_icenic_dma_out_1_a_bits_size (_icenic_domain_auto_icenic_dma_out_1_a_bits_size), .auto_icenic_dma_out_1_a_bits_source (_icenic_domain_auto_icenic_dma_out_1_a_bits_source), .auto_icenic_dma_out_1_a_bits_address (_icenic_domain_auto_icenic_dma_out_1_a_bits_address), .auto_icenic_dma_out_1_a_bits_mask (_icenic_domain_auto_icenic_dma_out_1_a_bits_mask), .auto_icenic_dma_out_1_a_bits_data (_icenic_domain_auto_icenic_dma_out_1_a_bits_data), .auto_icenic_dma_out_1_d_ready (_icenic_domain_auto_icenic_dma_out_1_d_ready), .auto_icenic_dma_out_1_d_valid (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_valid), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_1_d_bits_opcode (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_1_d_bits_param (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_param), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_1_d_bits_size (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_size), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_1_d_bits_source (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_source), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_1_d_bits_sink (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_sink), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_1_d_bits_denied (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_denied), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_1_d_bits_data (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_data), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_1_d_bits_corrupt (_fbus_auto_coupler_from_IceNIC_tl_in_1_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_0_a_ready (_fbus_auto_coupler_from_IceNIC_tl_in_0_a_ready), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_0_a_valid (_icenic_domain_auto_icenic_dma_out_0_a_valid), .auto_icenic_dma_out_0_a_bits_size (_icenic_domain_auto_icenic_dma_out_0_a_bits_size), .auto_icenic_dma_out_0_a_bits_source (_icenic_domain_auto_icenic_dma_out_0_a_bits_source), .auto_icenic_dma_out_0_a_bits_address (_icenic_domain_auto_icenic_dma_out_0_a_bits_address), .auto_icenic_dma_out_0_a_bits_mask (_icenic_domain_auto_icenic_dma_out_0_a_bits_mask), .auto_icenic_dma_out_0_d_valid (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_valid), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_0_d_bits_opcode (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_opcode), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_0_d_bits_param (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_param), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_0_d_bits_size (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_size), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_0_d_bits_source (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_source), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_0_d_bits_sink (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_sink), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_0_d_bits_denied (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_denied), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_0_d_bits_data (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_data), // @[FrontBus.scala:23:26] .auto_icenic_dma_out_0_d_bits_corrupt (_fbus_auto_coupler_from_IceNIC_tl_in_0_d_bits_corrupt), // @[FrontBus.scala:23:26] .auto_icenic_mmio_in_a_ready (_icenic_domain_auto_icenic_mmio_in_a_ready), .auto_icenic_mmio_in_a_valid (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_icenic_mmio_in_a_bits_opcode (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_icenic_mmio_in_a_bits_param (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_icenic_mmio_in_a_bits_size (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_icenic_mmio_in_a_bits_source (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_icenic_mmio_in_a_bits_address (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_icenic_mmio_in_a_bits_mask (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_icenic_mmio_in_a_bits_data (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_icenic_mmio_in_a_bits_corrupt (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_icenic_mmio_in_d_ready (_pbus_auto_coupler_to_IceNIC_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_icenic_mmio_in_d_valid (_icenic_domain_auto_icenic_mmio_in_d_valid), .auto_icenic_mmio_in_d_bits_opcode (_icenic_domain_auto_icenic_mmio_in_d_bits_opcode), .auto_icenic_mmio_in_d_bits_size (_icenic_domain_auto_icenic_mmio_in_d_bits_size), .auto_icenic_mmio_in_d_bits_source (_icenic_domain_auto_icenic_mmio_in_d_bits_source), .auto_icenic_mmio_in_d_bits_data (_icenic_domain_auto_icenic_mmio_in_d_bits_data), .auto_clock_in_clock (_pbus_auto_fixedClockNode_anon_out_1_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_pbus_auto_fixedClockNode_anon_out_1_reset), // @[PeripheryBus.scala:37:26] .nic_in_valid (nic_bits_in_valid_0), // @[DigitalTop.scala:47:7] .nic_in_bits_data (nic_bits_in_bits_data_0), // @[DigitalTop.scala:47:7] .nic_in_bits_keep (nic_bits_in_bits_keep_0), // @[DigitalTop.scala:47:7] .nic_in_bits_last (nic_bits_in_bits_last_0), // @[DigitalTop.scala:47:7] .nic_out_valid (nic_bits_out_valid_0), .nic_out_bits_data (nic_bits_out_bits_data_0), .nic_out_bits_keep (nic_bits_out_bits_keep_0), .nic_out_bits_last (nic_bits_out_bits_last_0), .nic_macAddr (nic_bits_macAddr_0), // @[DigitalTop.scala:47:7] .nic_rlimit_inc (nic_bits_rlimit_inc_0), // @[DigitalTop.scala:47:7] .nic_rlimit_period (nic_bits_rlimit_period_0), // @[DigitalTop.scala:47:7] .nic_rlimit_size (nic_bits_rlimit_size_0), // @[DigitalTop.scala:47:7] .nic_pauser_threshold (nic_bits_pauser_threshold_0), // @[DigitalTop.scala:47:7] .nic_pauser_quanta (nic_bits_pauser_quanta_0), // @[DigitalTop.scala:47:7] .nic_pauser_refresh (nic_bits_pauser_refresh_0), // @[DigitalTop.scala:47:7] .clock (nic_clock_0) ); // @[BusWrapper.scala:89:28] ChipyardPRCICtrlClockSinkDomain chipyard_prcictrl_domain ( // @[BusWrapper.scala:89:28] .auto_reset_setter_clock_in_member_allClocks_uncore_clock (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[DigitalTop.scala:47:7] .auto_reset_setter_clock_in_member_allClocks_uncore_reset (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[DigitalTop.scala:47:7] .auto_resetSynchronizer_out_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), .auto_resetSynchronizer_out_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), .auto_xbar_anon_in_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), .auto_xbar_anon_in_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), // @[PeripheryBus.scala:37:26] .auto_xbar_anon_in_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), .auto_xbar_anon_in_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), .auto_xbar_anon_in_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), .auto_xbar_anon_in_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), .auto_xbar_anon_in_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), .auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), // @[PeripheryBus.scala:37:26] .auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_4_reset) // @[PeripheryBus.scala:37:26] ); // @[BusWrapper.scala:89:28] ClockGroupAggregator_allClocks aggregator ( // @[HasChipyardPRCI.scala:51:30] .auto_in_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_mbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_1_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25] .auto_in_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25] .auto_out_5_member_clockTapNode_clockTapNode_clock_tap_clock (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_clock), .auto_out_5_member_clockTapNode_clockTapNode_clock_tap_reset (clockNamePrefixer_auto_clock_name_prefixer_in_5_member_clockTapNode_clockTapNode_clock_tap_reset), .auto_out_4_member_cbus_cbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_clock), .auto_out_4_member_cbus_cbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_cbus_cbus_0_reset), .auto_out_3_member_mbus_mbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_clock), .auto_out_3_member_mbus_mbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_mbus_mbus_0_reset), .auto_out_2_member_fbus_fbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock), .auto_out_2_member_fbus_fbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset), .auto_out_1_member_pbus_pbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock), .auto_out_1_member_pbus_pbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset), .auto_out_0_member_sbus_sbus_1_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_clock), .auto_out_0_member_sbus_sbus_1_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_1_reset), .auto_out_0_member_sbus_sbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock), .auto_out_0_member_sbus_sbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset) ); // @[HasChipyardPRCI.scala:51:30] ClockGroupCombiner clockGroupCombiner ( // @[ClockGroupCombiner.scala:19:15] .auto_clock_group_combiner_in_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), // @[BusWrapper.scala:89:28] .auto_clock_group_combiner_in_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), // @[BusWrapper.scala:89:28] .auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock), .auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset), .auto_clock_group_combiner_out_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_mbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_mbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_mbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset), .auto_clock_group_combiner_out_member_allClocks_sbus_1_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_clock), .auto_clock_group_combiner_out_member_allClocks_sbus_1_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_1_reset), .auto_clock_group_combiner_out_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock), .auto_clock_group_combiner_out_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset) ); // @[ClockGroupCombiner.scala:19:15] ClockSinkDomain_2 globalNoCDomain ( // @[GlobalNoC.scala:45:40] .auto_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), // @[SystemBus.scala:31:26] .auto_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_2_reset) // @[SystemBus.scala:31:26] ); // @[GlobalNoC.scala:45:40] BundleBridgeNexus_NoOutput_8 reRoCCManagerIdNexusNode (); // @[Integration.scala:34:44] DebugTransportModuleJTAG dtm ( // @[Periphery.scala:166:21] .io_jtag_clock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_jtag_reset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7] .io_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), // @[Periphery.scala:88:26] .io_dmi_req_valid (_dtm_io_dmi_req_valid), .io_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), .io_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), .io_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), .io_dmi_resp_ready (_dtm_io_dmi_resp_ready), .io_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), // @[Periphery.scala:88:26] .io_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), // @[Periphery.scala:88:26] .io_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), // @[Periphery.scala:88:26] .io_jtag_TCK (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7] .io_jtag_TMS (debug_systemjtag_jtag_TMS_0), // @[DigitalTop.scala:47:7] .io_jtag_TDI (debug_systemjtag_jtag_TDI_0), // @[DigitalTop.scala:47:7] .io_jtag_TDO_data (debug_systemjtag_jtag_TDO_data_0), .io_jtag_TDO_driven (debug_systemjtag_jtag_TDO_driven), .rf_reset (debug_systemjtag_reset_0) // @[DigitalTop.scala:47:7] ); // @[Periphery.scala:166:21] assign auto_mbus_fixedClockNode_anon_out_clock = auto_mbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] assign auto_mbus_fixedClockNode_anon_out_reset = auto_mbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] assign auto_cbus_fixedClockNode_anon_out_clock = auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7] assign auto_cbus_fixedClockNode_anon_out_reset = auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7] assign debug_systemjtag_jtag_TDO_data = debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7] assign debug_dmactive = debug_dmactive_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_valid = mem_axi4_0_aw_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_id = mem_axi4_0_aw_bits_id_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_addr = mem_axi4_0_aw_bits_addr_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_len = mem_axi4_0_aw_bits_len_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_size = mem_axi4_0_aw_bits_size_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_burst = mem_axi4_0_aw_bits_burst_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_lock = mem_axi4_0_aw_bits_lock_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_cache = mem_axi4_0_aw_bits_cache_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_prot = mem_axi4_0_aw_bits_prot_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_aw_bits_qos = mem_axi4_0_aw_bits_qos_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_valid = mem_axi4_0_w_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_data = mem_axi4_0_w_bits_data_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_strb = mem_axi4_0_w_bits_strb_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_w_bits_last = mem_axi4_0_w_bits_last_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_b_ready = mem_axi4_0_b_ready_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_valid = mem_axi4_0_ar_valid_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_id = mem_axi4_0_ar_bits_id_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_addr = mem_axi4_0_ar_bits_addr_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_len = mem_axi4_0_ar_bits_len_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_size = mem_axi4_0_ar_bits_size_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_burst = mem_axi4_0_ar_bits_burst_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_lock = mem_axi4_0_ar_bits_lock_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_cache = mem_axi4_0_ar_bits_cache_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_prot = mem_axi4_0_ar_bits_prot_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_ar_bits_qos = mem_axi4_0_ar_bits_qos_0; // @[DigitalTop.scala:47:7] assign mem_axi4_0_r_ready = mem_axi4_0_r_ready_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_in_ready = serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_out_valid = serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7] assign serial_tl_0_out_bits_phit = serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7] assign uart_0_txd = uart_0_txd_0; // @[DigitalTop.scala:47:7] assign nic_clock = nic_clock_0; // @[DigitalTop.scala:47:7] assign nic_bits_out_valid = nic_bits_out_valid_0; // @[DigitalTop.scala:47:7] assign nic_bits_out_bits_data = nic_bits_out_bits_data_0; // @[DigitalTop.scala:47:7] assign nic_bits_out_bits_keep = nic_bits_out_bits_keep_0; // @[DigitalTop.scala:47:7] assign nic_bits_out_bits_last = nic_bits_out_bits_last_0; // @[DigitalTop.scala:47:7] assign clock_tap = clockTapIn_clock; // @[MixedNode.scala:551:17] endmodule
Generate the Verilog code corresponding to this FIRRTL code module FPU : input clock : Clock input reset : Reset output io : { flip req : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, fcsr_rm : UInt<3>}}, resp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}} inst dfma of FPUFMAPipe_l4_f64 connect dfma.clock, clock connect dfma.reset, reset node _dfma_io_in_valid_T = and(io.req.valid, io.req.bits.uop.fp_ctrl.fma) node _dfma_io_in_valid_T_1 = eq(io.req.bits.uop.fp_ctrl.typeTagOut, UInt<1>(0h1)) node _dfma_io_in_valid_T_2 = and(_dfma_io_in_valid_T, _dfma_io_in_valid_T_1) connect dfma.io.in.valid, _dfma_io_in_valid_T_2 wire dfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect dfma_io_in_bits_req.vec, io.req.bits.uop.fp_ctrl.vec connect dfma_io_in_bits_req.wflags, io.req.bits.uop.fp_ctrl.wflags connect dfma_io_in_bits_req.sqrt, io.req.bits.uop.fp_ctrl.sqrt connect dfma_io_in_bits_req.div, io.req.bits.uop.fp_ctrl.div connect dfma_io_in_bits_req.fma, io.req.bits.uop.fp_ctrl.fma connect dfma_io_in_bits_req.fastpipe, io.req.bits.uop.fp_ctrl.fastpipe connect dfma_io_in_bits_req.toint, io.req.bits.uop.fp_ctrl.toint connect dfma_io_in_bits_req.fromint, io.req.bits.uop.fp_ctrl.fromint connect dfma_io_in_bits_req.typeTagOut, io.req.bits.uop.fp_ctrl.typeTagOut connect dfma_io_in_bits_req.typeTagIn, io.req.bits.uop.fp_ctrl.typeTagIn connect dfma_io_in_bits_req.swap23, io.req.bits.uop.fp_ctrl.swap23 connect dfma_io_in_bits_req.swap12, io.req.bits.uop.fp_ctrl.swap12 connect dfma_io_in_bits_req.ren3, io.req.bits.uop.fp_ctrl.ren3 connect dfma_io_in_bits_req.ren2, io.req.bits.uop.fp_ctrl.ren2 connect dfma_io_in_bits_req.ren1, io.req.bits.uop.fp_ctrl.ren1 connect dfma_io_in_bits_req.wen, io.req.bits.uop.fp_ctrl.wen connect dfma_io_in_bits_req.ldst, io.req.bits.uop.fp_ctrl.ldst connect dfma_io_in_bits_req.rm, io.req.bits.uop.fp_rm node _dfma_io_in_bits_req_in1_prev_unswizzled_T = bits(io.req.bits.rs1_data, 31, 31) node _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(io.req.bits.rs1_data, 52, 52) node _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(io.req.bits.rs1_data, 30, 0) node dfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1) node dfma_io_in_bits_req_in1_prev_unswizzled = cat(dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2) node dfma_io_in_bits_req_in1_prev_prev_sign = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 32, 32) node dfma_io_in_bits_req_in1_prev_prev_fractIn = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 22, 0) node dfma_io_in_bits_req_in1_prev_prev_expIn = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in1_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in1_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in1_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in1_prev_prev_expOut_T, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in1_prev_prev_expOut = mux(_dfma_io_in_bits_req_in1_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in1_prev_prev_hi = cat(dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut) node dfma_io_in_bits_req_in1_floats_0 = cat(dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut) node _dfma_io_in_bits_req_in1_prev_isbox_T = bits(io.req.bits.rs1_data, 64, 60) node dfma_io_in_bits_req_in1_prev_isbox = andr(_dfma_io_in_bits_req_in1_prev_isbox_T) node dfma_io_in_bits_req_in1_oks_0 = and(dfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node _dfma_io_in_bits_req_in1_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _dfma_io_in_bits_req_in1_T_1 = or(io.req.bits.rs1_data, _dfma_io_in_bits_req_in1_T) connect dfma_io_in_bits_req.in1, _dfma_io_in_bits_req_in1_T_1 node _dfma_io_in_bits_req_in2_prev_unswizzled_T = bits(io.req.bits.rs2_data, 31, 31) node _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(io.req.bits.rs2_data, 52, 52) node _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(io.req.bits.rs2_data, 30, 0) node dfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1) node dfma_io_in_bits_req_in2_prev_unswizzled = cat(dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2) node dfma_io_in_bits_req_in2_prev_prev_sign = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 32, 32) node dfma_io_in_bits_req_in2_prev_prev_fractIn = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 22, 0) node dfma_io_in_bits_req_in2_prev_prev_expIn = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in2_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in2_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in2_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in2_prev_prev_expOut_T, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in2_prev_prev_expOut = mux(_dfma_io_in_bits_req_in2_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in2_prev_prev_hi = cat(dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut) node dfma_io_in_bits_req_in2_floats_0 = cat(dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut) node _dfma_io_in_bits_req_in2_prev_isbox_T = bits(io.req.bits.rs2_data, 64, 60) node dfma_io_in_bits_req_in2_prev_isbox = andr(_dfma_io_in_bits_req_in2_prev_isbox_T) node dfma_io_in_bits_req_in2_oks_0 = and(dfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node _dfma_io_in_bits_req_in2_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _dfma_io_in_bits_req_in2_T_1 = or(io.req.bits.rs2_data, _dfma_io_in_bits_req_in2_T) connect dfma_io_in_bits_req.in2, _dfma_io_in_bits_req_in2_T_1 node _dfma_io_in_bits_req_in3_prev_unswizzled_T = bits(io.req.bits.rs3_data, 31, 31) node _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(io.req.bits.rs3_data, 52, 52) node _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(io.req.bits.rs3_data, 30, 0) node dfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1) node dfma_io_in_bits_req_in3_prev_unswizzled = cat(dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2) node dfma_io_in_bits_req_in3_prev_prev_sign = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 32, 32) node dfma_io_in_bits_req_in3_prev_prev_fractIn = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 22, 0) node dfma_io_in_bits_req_in3_prev_prev_expIn = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in3_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in3_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in3_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in3_prev_prev_expOut_T, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in3_prev_prev_expOut = mux(_dfma_io_in_bits_req_in3_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in3_prev_prev_hi = cat(dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut) node dfma_io_in_bits_req_in3_floats_0 = cat(dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut) node _dfma_io_in_bits_req_in3_prev_isbox_T = bits(io.req.bits.rs3_data, 64, 60) node dfma_io_in_bits_req_in3_prev_isbox = andr(_dfma_io_in_bits_req_in3_prev_isbox_T) node dfma_io_in_bits_req_in3_oks_0 = and(dfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node _dfma_io_in_bits_req_in3_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _dfma_io_in_bits_req_in3_T_1 = or(io.req.bits.rs3_data, _dfma_io_in_bits_req_in3_T) connect dfma_io_in_bits_req.in3, _dfma_io_in_bits_req_in3_T_1 when io.req.bits.uop.fp_ctrl.swap23 : connect dfma_io_in_bits_req.in3, dfma_io_in_bits_req.in2 connect dfma_io_in_bits_req.typ, io.req.bits.uop.fp_typ node _dfma_io_in_bits_req_fmt_T = eq(io.req.bits.uop.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _dfma_io_in_bits_req_fmt_T_1 = mux(_dfma_io_in_bits_req_fmt_T, UInt<1>(0h0), UInt<1>(0h1)) connect dfma_io_in_bits_req.fmt, _dfma_io_in_bits_req_fmt_T_1 node _dfma_io_in_bits_T = eq(io.req.bits.uop.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _dfma_io_in_bits_T_1 = and(io.req.bits.uop.fp_ctrl.toint, _dfma_io_in_bits_T) node _dfma_io_in_bits_T_2 = eq(io.req.bits.uop.fp_ctrl.wflags, UInt<1>(0h0)) node _dfma_io_in_bits_T_3 = and(_dfma_io_in_bits_T_1, _dfma_io_in_bits_T_2) when _dfma_io_in_bits_T_3 : connect dfma_io_in_bits_req.fmt, UInt<1>(0h0) connect dfma_io_in_bits_req.fmaCmd, io.req.bits.uop.fcn_op connect dfma.io.in.bits.in3, dfma_io_in_bits_req.in3 connect dfma.io.in.bits.in2, dfma_io_in_bits_req.in2 connect dfma.io.in.bits.in1, dfma_io_in_bits_req.in1 connect dfma.io.in.bits.fmt, dfma_io_in_bits_req.fmt connect dfma.io.in.bits.typ, dfma_io_in_bits_req.typ connect dfma.io.in.bits.fmaCmd, dfma_io_in_bits_req.fmaCmd connect dfma.io.in.bits.rm, dfma_io_in_bits_req.rm connect dfma.io.in.bits.vec, dfma_io_in_bits_req.vec connect dfma.io.in.bits.wflags, dfma_io_in_bits_req.wflags connect dfma.io.in.bits.sqrt, dfma_io_in_bits_req.sqrt connect dfma.io.in.bits.div, dfma_io_in_bits_req.div connect dfma.io.in.bits.fma, dfma_io_in_bits_req.fma connect dfma.io.in.bits.fastpipe, dfma_io_in_bits_req.fastpipe connect dfma.io.in.bits.toint, dfma_io_in_bits_req.toint connect dfma.io.in.bits.fromint, dfma_io_in_bits_req.fromint connect dfma.io.in.bits.typeTagOut, dfma_io_in_bits_req.typeTagOut connect dfma.io.in.bits.typeTagIn, dfma_io_in_bits_req.typeTagIn connect dfma.io.in.bits.swap23, dfma_io_in_bits_req.swap23 connect dfma.io.in.bits.swap12, dfma_io_in_bits_req.swap12 connect dfma.io.in.bits.ren3, dfma_io_in_bits_req.ren3 connect dfma.io.in.bits.ren2, dfma_io_in_bits_req.ren2 connect dfma.io.in.bits.ren1, dfma_io_in_bits_req.ren1 connect dfma.io.in.bits.wen, dfma_io_in_bits_req.wen connect dfma.io.in.bits.ldst, dfma_io_in_bits_req.ldst inst sfma of FPUFMAPipe_l4_f32 connect sfma.clock, clock connect sfma.reset, reset node _sfma_io_in_valid_T = and(io.req.valid, io.req.bits.uop.fp_ctrl.fma) node _sfma_io_in_valid_T_1 = eq(io.req.bits.uop.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _sfma_io_in_valid_T_2 = and(_sfma_io_in_valid_T, _sfma_io_in_valid_T_1) connect sfma.io.in.valid, _sfma_io_in_valid_T_2 wire sfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect sfma_io_in_bits_req.vec, io.req.bits.uop.fp_ctrl.vec connect sfma_io_in_bits_req.wflags, io.req.bits.uop.fp_ctrl.wflags connect sfma_io_in_bits_req.sqrt, io.req.bits.uop.fp_ctrl.sqrt connect sfma_io_in_bits_req.div, io.req.bits.uop.fp_ctrl.div connect sfma_io_in_bits_req.fma, io.req.bits.uop.fp_ctrl.fma connect sfma_io_in_bits_req.fastpipe, io.req.bits.uop.fp_ctrl.fastpipe connect sfma_io_in_bits_req.toint, io.req.bits.uop.fp_ctrl.toint connect sfma_io_in_bits_req.fromint, io.req.bits.uop.fp_ctrl.fromint connect sfma_io_in_bits_req.typeTagOut, io.req.bits.uop.fp_ctrl.typeTagOut connect sfma_io_in_bits_req.typeTagIn, io.req.bits.uop.fp_ctrl.typeTagIn connect sfma_io_in_bits_req.swap23, io.req.bits.uop.fp_ctrl.swap23 connect sfma_io_in_bits_req.swap12, io.req.bits.uop.fp_ctrl.swap12 connect sfma_io_in_bits_req.ren3, io.req.bits.uop.fp_ctrl.ren3 connect sfma_io_in_bits_req.ren2, io.req.bits.uop.fp_ctrl.ren2 connect sfma_io_in_bits_req.ren1, io.req.bits.uop.fp_ctrl.ren1 connect sfma_io_in_bits_req.wen, io.req.bits.uop.fp_ctrl.wen connect sfma_io_in_bits_req.ldst, io.req.bits.uop.fp_ctrl.ldst connect sfma_io_in_bits_req.rm, io.req.bits.uop.fp_rm node _sfma_io_in_bits_req_in1_prev_unswizzled_T = bits(io.req.bits.rs1_data, 31, 31) node _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(io.req.bits.rs1_data, 52, 52) node _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(io.req.bits.rs1_data, 30, 0) node sfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1) node sfma_io_in_bits_req_in1_floats_0 = cat(sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2) node _sfma_io_in_bits_req_in1_prev_isbox_T = bits(io.req.bits.rs1_data, 64, 60) node sfma_io_in_bits_req_in1_prev_isbox = andr(_sfma_io_in_bits_req_in1_prev_isbox_T) node sfma_io_in_bits_req_in1_oks_0 = and(sfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node sfma_io_in_bits_req_in1_sign = bits(io.req.bits.rs1_data, 64, 64) node sfma_io_in_bits_req_in1_fractIn = bits(io.req.bits.rs1_data, 51, 0) node sfma_io_in_bits_req_in1_expIn = bits(io.req.bits.rs1_data, 63, 52) node _sfma_io_in_bits_req_in1_fractOut_T = shl(sfma_io_in_bits_req_in1_fractIn, 24) node sfma_io_in_bits_req_in1_fractOut = shr(_sfma_io_in_bits_req_in1_fractOut_T, 53) node sfma_io_in_bits_req_in1_expOut_expCode = bits(sfma_io_in_bits_req_in1_expIn, 11, 9) node _sfma_io_in_bits_req_in1_expOut_commonCase_T = add(sfma_io_in_bits_req_in1_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in1_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in1_expOut_commonCase_T_1, UInt<12>(0h800)) node sfma_io_in_bits_req_in1_expOut_commonCase = tail(_sfma_io_in_bits_req_in1_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in1_expOut_T = eq(sfma_io_in_bits_req_in1_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in1_expOut_T_1 = geq(sfma_io_in_bits_req_in1_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in1_expOut_T_2 = or(_sfma_io_in_bits_req_in1_expOut_T, _sfma_io_in_bits_req_in1_expOut_T_1) node _sfma_io_in_bits_req_in1_expOut_T_3 = bits(sfma_io_in_bits_req_in1_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in1_expOut_T_4 = cat(sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3) node _sfma_io_in_bits_req_in1_expOut_T_5 = bits(sfma_io_in_bits_req_in1_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in1_expOut = mux(_sfma_io_in_bits_req_in1_expOut_T_2, _sfma_io_in_bits_req_in1_expOut_T_4, _sfma_io_in_bits_req_in1_expOut_T_5) node sfma_io_in_bits_req_in1_hi = cat(sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut) node sfma_io_in_bits_req_in1_floats_1 = cat(sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut) node _sfma_io_in_bits_req_in1_T = mux(sfma_io_in_bits_req_in1_oks_0, UInt<1>(0h0), UInt<33>(0he0400000)) node _sfma_io_in_bits_req_in1_T_1 = or(sfma_io_in_bits_req_in1_floats_0, _sfma_io_in_bits_req_in1_T) connect sfma_io_in_bits_req.in1, _sfma_io_in_bits_req_in1_T_1 node _sfma_io_in_bits_req_in2_prev_unswizzled_T = bits(io.req.bits.rs2_data, 31, 31) node _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(io.req.bits.rs2_data, 52, 52) node _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(io.req.bits.rs2_data, 30, 0) node sfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1) node sfma_io_in_bits_req_in2_floats_0 = cat(sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2) node _sfma_io_in_bits_req_in2_prev_isbox_T = bits(io.req.bits.rs2_data, 64, 60) node sfma_io_in_bits_req_in2_prev_isbox = andr(_sfma_io_in_bits_req_in2_prev_isbox_T) node sfma_io_in_bits_req_in2_oks_0 = and(sfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node sfma_io_in_bits_req_in2_sign = bits(io.req.bits.rs2_data, 64, 64) node sfma_io_in_bits_req_in2_fractIn = bits(io.req.bits.rs2_data, 51, 0) node sfma_io_in_bits_req_in2_expIn = bits(io.req.bits.rs2_data, 63, 52) node _sfma_io_in_bits_req_in2_fractOut_T = shl(sfma_io_in_bits_req_in2_fractIn, 24) node sfma_io_in_bits_req_in2_fractOut = shr(_sfma_io_in_bits_req_in2_fractOut_T, 53) node sfma_io_in_bits_req_in2_expOut_expCode = bits(sfma_io_in_bits_req_in2_expIn, 11, 9) node _sfma_io_in_bits_req_in2_expOut_commonCase_T = add(sfma_io_in_bits_req_in2_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in2_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in2_expOut_commonCase_T_1, UInt<12>(0h800)) node sfma_io_in_bits_req_in2_expOut_commonCase = tail(_sfma_io_in_bits_req_in2_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in2_expOut_T = eq(sfma_io_in_bits_req_in2_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in2_expOut_T_1 = geq(sfma_io_in_bits_req_in2_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in2_expOut_T_2 = or(_sfma_io_in_bits_req_in2_expOut_T, _sfma_io_in_bits_req_in2_expOut_T_1) node _sfma_io_in_bits_req_in2_expOut_T_3 = bits(sfma_io_in_bits_req_in2_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in2_expOut_T_4 = cat(sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3) node _sfma_io_in_bits_req_in2_expOut_T_5 = bits(sfma_io_in_bits_req_in2_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in2_expOut = mux(_sfma_io_in_bits_req_in2_expOut_T_2, _sfma_io_in_bits_req_in2_expOut_T_4, _sfma_io_in_bits_req_in2_expOut_T_5) node sfma_io_in_bits_req_in2_hi = cat(sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut) node sfma_io_in_bits_req_in2_floats_1 = cat(sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut) node _sfma_io_in_bits_req_in2_T = mux(sfma_io_in_bits_req_in2_oks_0, UInt<1>(0h0), UInt<33>(0he0400000)) node _sfma_io_in_bits_req_in2_T_1 = or(sfma_io_in_bits_req_in2_floats_0, _sfma_io_in_bits_req_in2_T) connect sfma_io_in_bits_req.in2, _sfma_io_in_bits_req_in2_T_1 node _sfma_io_in_bits_req_in3_prev_unswizzled_T = bits(io.req.bits.rs3_data, 31, 31) node _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(io.req.bits.rs3_data, 52, 52) node _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(io.req.bits.rs3_data, 30, 0) node sfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1) node sfma_io_in_bits_req_in3_floats_0 = cat(sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2) node _sfma_io_in_bits_req_in3_prev_isbox_T = bits(io.req.bits.rs3_data, 64, 60) node sfma_io_in_bits_req_in3_prev_isbox = andr(_sfma_io_in_bits_req_in3_prev_isbox_T) node sfma_io_in_bits_req_in3_oks_0 = and(sfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node sfma_io_in_bits_req_in3_sign = bits(io.req.bits.rs3_data, 64, 64) node sfma_io_in_bits_req_in3_fractIn = bits(io.req.bits.rs3_data, 51, 0) node sfma_io_in_bits_req_in3_expIn = bits(io.req.bits.rs3_data, 63, 52) node _sfma_io_in_bits_req_in3_fractOut_T = shl(sfma_io_in_bits_req_in3_fractIn, 24) node sfma_io_in_bits_req_in3_fractOut = shr(_sfma_io_in_bits_req_in3_fractOut_T, 53) node sfma_io_in_bits_req_in3_expOut_expCode = bits(sfma_io_in_bits_req_in3_expIn, 11, 9) node _sfma_io_in_bits_req_in3_expOut_commonCase_T = add(sfma_io_in_bits_req_in3_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in3_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in3_expOut_commonCase_T_1, UInt<12>(0h800)) node sfma_io_in_bits_req_in3_expOut_commonCase = tail(_sfma_io_in_bits_req_in3_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in3_expOut_T = eq(sfma_io_in_bits_req_in3_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in3_expOut_T_1 = geq(sfma_io_in_bits_req_in3_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in3_expOut_T_2 = or(_sfma_io_in_bits_req_in3_expOut_T, _sfma_io_in_bits_req_in3_expOut_T_1) node _sfma_io_in_bits_req_in3_expOut_T_3 = bits(sfma_io_in_bits_req_in3_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in3_expOut_T_4 = cat(sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3) node _sfma_io_in_bits_req_in3_expOut_T_5 = bits(sfma_io_in_bits_req_in3_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in3_expOut = mux(_sfma_io_in_bits_req_in3_expOut_T_2, _sfma_io_in_bits_req_in3_expOut_T_4, _sfma_io_in_bits_req_in3_expOut_T_5) node sfma_io_in_bits_req_in3_hi = cat(sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut) node sfma_io_in_bits_req_in3_floats_1 = cat(sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut) node _sfma_io_in_bits_req_in3_T = mux(sfma_io_in_bits_req_in3_oks_0, UInt<1>(0h0), UInt<33>(0he0400000)) node _sfma_io_in_bits_req_in3_T_1 = or(sfma_io_in_bits_req_in3_floats_0, _sfma_io_in_bits_req_in3_T) connect sfma_io_in_bits_req.in3, _sfma_io_in_bits_req_in3_T_1 when io.req.bits.uop.fp_ctrl.swap23 : connect sfma_io_in_bits_req.in3, sfma_io_in_bits_req.in2 connect sfma_io_in_bits_req.typ, io.req.bits.uop.fp_typ node _sfma_io_in_bits_req_fmt_T = eq(io.req.bits.uop.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _sfma_io_in_bits_req_fmt_T_1 = mux(_sfma_io_in_bits_req_fmt_T, UInt<1>(0h0), UInt<1>(0h1)) connect sfma_io_in_bits_req.fmt, _sfma_io_in_bits_req_fmt_T_1 node _sfma_io_in_bits_T = eq(io.req.bits.uop.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _sfma_io_in_bits_T_1 = and(io.req.bits.uop.fp_ctrl.toint, _sfma_io_in_bits_T) node _sfma_io_in_bits_T_2 = eq(io.req.bits.uop.fp_ctrl.wflags, UInt<1>(0h0)) node _sfma_io_in_bits_T_3 = and(_sfma_io_in_bits_T_1, _sfma_io_in_bits_T_2) when _sfma_io_in_bits_T_3 : connect sfma_io_in_bits_req.fmt, UInt<1>(0h0) connect sfma_io_in_bits_req.fmaCmd, io.req.bits.uop.fcn_op connect sfma.io.in.bits.in3, sfma_io_in_bits_req.in3 connect sfma.io.in.bits.in2, sfma_io_in_bits_req.in2 connect sfma.io.in.bits.in1, sfma_io_in_bits_req.in1 connect sfma.io.in.bits.fmt, sfma_io_in_bits_req.fmt connect sfma.io.in.bits.typ, sfma_io_in_bits_req.typ connect sfma.io.in.bits.fmaCmd, sfma_io_in_bits_req.fmaCmd connect sfma.io.in.bits.rm, sfma_io_in_bits_req.rm connect sfma.io.in.bits.vec, sfma_io_in_bits_req.vec connect sfma.io.in.bits.wflags, sfma_io_in_bits_req.wflags connect sfma.io.in.bits.sqrt, sfma_io_in_bits_req.sqrt connect sfma.io.in.bits.div, sfma_io_in_bits_req.div connect sfma.io.in.bits.fma, sfma_io_in_bits_req.fma connect sfma.io.in.bits.fastpipe, sfma_io_in_bits_req.fastpipe connect sfma.io.in.bits.toint, sfma_io_in_bits_req.toint connect sfma.io.in.bits.fromint, sfma_io_in_bits_req.fromint connect sfma.io.in.bits.typeTagOut, sfma_io_in_bits_req.typeTagOut connect sfma.io.in.bits.typeTagIn, sfma_io_in_bits_req.typeTagIn connect sfma.io.in.bits.swap23, sfma_io_in_bits_req.swap23 connect sfma.io.in.bits.swap12, sfma_io_in_bits_req.swap12 connect sfma.io.in.bits.ren3, sfma_io_in_bits_req.ren3 connect sfma.io.in.bits.ren2, sfma_io_in_bits_req.ren2 connect sfma.io.in.bits.ren1, sfma_io_in_bits_req.ren1 connect sfma.io.in.bits.wen, sfma_io_in_bits_req.wen connect sfma.io.in.bits.ldst, sfma_io_in_bits_req.ldst inst fpiu of FPToInt connect fpiu.clock, clock connect fpiu.reset, reset node _fpiu_io_in_valid_T = and(io.req.bits.uop.fp_ctrl.fastpipe, io.req.bits.uop.fp_ctrl.wflags) node _fpiu_io_in_valid_T_1 = or(io.req.bits.uop.fp_ctrl.toint, _fpiu_io_in_valid_T) node _fpiu_io_in_valid_T_2 = and(io.req.valid, _fpiu_io_in_valid_T_1) connect fpiu.io.in.valid, _fpiu_io_in_valid_T_2 wire fpiu_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect fpiu_io_in_bits_req.vec, io.req.bits.uop.fp_ctrl.vec connect fpiu_io_in_bits_req.wflags, io.req.bits.uop.fp_ctrl.wflags connect fpiu_io_in_bits_req.sqrt, io.req.bits.uop.fp_ctrl.sqrt connect fpiu_io_in_bits_req.div, io.req.bits.uop.fp_ctrl.div connect fpiu_io_in_bits_req.fma, io.req.bits.uop.fp_ctrl.fma connect fpiu_io_in_bits_req.fastpipe, io.req.bits.uop.fp_ctrl.fastpipe connect fpiu_io_in_bits_req.toint, io.req.bits.uop.fp_ctrl.toint connect fpiu_io_in_bits_req.fromint, io.req.bits.uop.fp_ctrl.fromint connect fpiu_io_in_bits_req.typeTagOut, io.req.bits.uop.fp_ctrl.typeTagOut connect fpiu_io_in_bits_req.typeTagIn, io.req.bits.uop.fp_ctrl.typeTagIn connect fpiu_io_in_bits_req.swap23, io.req.bits.uop.fp_ctrl.swap23 connect fpiu_io_in_bits_req.swap12, io.req.bits.uop.fp_ctrl.swap12 connect fpiu_io_in_bits_req.ren3, io.req.bits.uop.fp_ctrl.ren3 connect fpiu_io_in_bits_req.ren2, io.req.bits.uop.fp_ctrl.ren2 connect fpiu_io_in_bits_req.ren1, io.req.bits.uop.fp_ctrl.ren1 connect fpiu_io_in_bits_req.wen, io.req.bits.uop.fp_ctrl.wen connect fpiu_io_in_bits_req.ldst, io.req.bits.uop.fp_ctrl.ldst connect fpiu_io_in_bits_req.rm, io.req.bits.uop.fp_rm node _fpiu_io_in_bits_req_in1_prev_unswizzled_T = bits(io.req.bits.rs1_data, 31, 31) node _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(io.req.bits.rs1_data, 52, 52) node _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(io.req.bits.rs1_data, 30, 0) node fpiu_io_in_bits_req_in1_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in1_prev_unswizzled = cat(fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2) node fpiu_io_in_bits_req_in1_prev_prev_sign = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 32, 32) node fpiu_io_in_bits_req_in1_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 22, 0) node fpiu_io_in_bits_req_in1_prev_prev_expIn = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in1_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in1_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in1_prev_prev_expOut_T, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in1_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in1_prev_prev_hi = cat(fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut) node fpiu_io_in_bits_req_in1_floats_0 = cat(fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut) node _fpiu_io_in_bits_req_in1_prev_isbox_T = bits(io.req.bits.rs1_data, 64, 60) node fpiu_io_in_bits_req_in1_prev_isbox = andr(_fpiu_io_in_bits_req_in1_prev_isbox_T) node fpiu_io_in_bits_req_in1_oks_0 = and(fpiu_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in1_truncIdx_T = or(io.req.bits.uop.fp_ctrl.typeTagIn, UInt<1>(0h0)) node fpiu_io_in_bits_req_in1_truncIdx = bits(_fpiu_io_in_bits_req_in1_truncIdx_T, 0, 0) node _fpiu_io_in_bits_req_in1_T = eq(fpiu_io_in_bits_req_in1_truncIdx, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in1_T_1 = mux(_fpiu_io_in_bits_req_in1_T, UInt<1>(0h1), fpiu_io_in_bits_req_in1_oks_0) node _fpiu_io_in_bits_req_in1_truncIdx_T_1 = or(io.req.bits.uop.fp_ctrl.typeTagIn, UInt<1>(0h0)) node fpiu_io_in_bits_req_in1_truncIdx_1 = bits(_fpiu_io_in_bits_req_in1_truncIdx_T_1, 0, 0) node _fpiu_io_in_bits_req_in1_T_2 = eq(fpiu_io_in_bits_req_in1_truncIdx_1, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in1_T_3 = mux(_fpiu_io_in_bits_req_in1_T_2, io.req.bits.rs1_data, fpiu_io_in_bits_req_in1_floats_0) node _fpiu_io_in_bits_req_in1_T_4 = mux(_fpiu_io_in_bits_req_in1_T_1, _fpiu_io_in_bits_req_in1_T_3, UInt<65>(0he008000000000000)) connect fpiu_io_in_bits_req.in1, _fpiu_io_in_bits_req_in1_T_4 node _fpiu_io_in_bits_req_in2_prev_unswizzled_T = bits(io.req.bits.rs2_data, 31, 31) node _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(io.req.bits.rs2_data, 52, 52) node _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(io.req.bits.rs2_data, 30, 0) node fpiu_io_in_bits_req_in2_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in2_prev_unswizzled = cat(fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2) node fpiu_io_in_bits_req_in2_prev_prev_sign = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 32, 32) node fpiu_io_in_bits_req_in2_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 22, 0) node fpiu_io_in_bits_req_in2_prev_prev_expIn = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in2_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in2_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in2_prev_prev_expOut_T, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in2_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in2_prev_prev_hi = cat(fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut) node fpiu_io_in_bits_req_in2_floats_0 = cat(fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut) node _fpiu_io_in_bits_req_in2_prev_isbox_T = bits(io.req.bits.rs2_data, 64, 60) node fpiu_io_in_bits_req_in2_prev_isbox = andr(_fpiu_io_in_bits_req_in2_prev_isbox_T) node fpiu_io_in_bits_req_in2_oks_0 = and(fpiu_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in2_truncIdx_T = or(io.req.bits.uop.fp_ctrl.typeTagIn, UInt<1>(0h0)) node fpiu_io_in_bits_req_in2_truncIdx = bits(_fpiu_io_in_bits_req_in2_truncIdx_T, 0, 0) node _fpiu_io_in_bits_req_in2_T = eq(fpiu_io_in_bits_req_in2_truncIdx, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in2_T_1 = mux(_fpiu_io_in_bits_req_in2_T, UInt<1>(0h1), fpiu_io_in_bits_req_in2_oks_0) node _fpiu_io_in_bits_req_in2_truncIdx_T_1 = or(io.req.bits.uop.fp_ctrl.typeTagIn, UInt<1>(0h0)) node fpiu_io_in_bits_req_in2_truncIdx_1 = bits(_fpiu_io_in_bits_req_in2_truncIdx_T_1, 0, 0) node _fpiu_io_in_bits_req_in2_T_2 = eq(fpiu_io_in_bits_req_in2_truncIdx_1, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in2_T_3 = mux(_fpiu_io_in_bits_req_in2_T_2, io.req.bits.rs2_data, fpiu_io_in_bits_req_in2_floats_0) node _fpiu_io_in_bits_req_in2_T_4 = mux(_fpiu_io_in_bits_req_in2_T_1, _fpiu_io_in_bits_req_in2_T_3, UInt<65>(0he008000000000000)) connect fpiu_io_in_bits_req.in2, _fpiu_io_in_bits_req_in2_T_4 node _fpiu_io_in_bits_req_in3_prev_unswizzled_T = bits(io.req.bits.rs3_data, 31, 31) node _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(io.req.bits.rs3_data, 52, 52) node _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(io.req.bits.rs3_data, 30, 0) node fpiu_io_in_bits_req_in3_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in3_prev_unswizzled = cat(fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2) node fpiu_io_in_bits_req_in3_prev_prev_sign = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 32, 32) node fpiu_io_in_bits_req_in3_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 22, 0) node fpiu_io_in_bits_req_in3_prev_prev_expIn = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in3_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in3_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in3_prev_prev_expOut_T, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in3_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in3_prev_prev_hi = cat(fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut) node fpiu_io_in_bits_req_in3_floats_0 = cat(fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut) node _fpiu_io_in_bits_req_in3_prev_isbox_T = bits(io.req.bits.rs3_data, 64, 60) node fpiu_io_in_bits_req_in3_prev_isbox = andr(_fpiu_io_in_bits_req_in3_prev_isbox_T) node fpiu_io_in_bits_req_in3_oks_0 = and(fpiu_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in3_truncIdx_T = or(io.req.bits.uop.fp_ctrl.typeTagIn, UInt<1>(0h0)) node fpiu_io_in_bits_req_in3_truncIdx = bits(_fpiu_io_in_bits_req_in3_truncIdx_T, 0, 0) node _fpiu_io_in_bits_req_in3_T = eq(fpiu_io_in_bits_req_in3_truncIdx, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in3_T_1 = mux(_fpiu_io_in_bits_req_in3_T, UInt<1>(0h1), fpiu_io_in_bits_req_in3_oks_0) node _fpiu_io_in_bits_req_in3_truncIdx_T_1 = or(io.req.bits.uop.fp_ctrl.typeTagIn, UInt<1>(0h0)) node fpiu_io_in_bits_req_in3_truncIdx_1 = bits(_fpiu_io_in_bits_req_in3_truncIdx_T_1, 0, 0) node _fpiu_io_in_bits_req_in3_T_2 = eq(fpiu_io_in_bits_req_in3_truncIdx_1, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in3_T_3 = mux(_fpiu_io_in_bits_req_in3_T_2, io.req.bits.rs3_data, fpiu_io_in_bits_req_in3_floats_0) node _fpiu_io_in_bits_req_in3_T_4 = mux(_fpiu_io_in_bits_req_in3_T_1, _fpiu_io_in_bits_req_in3_T_3, UInt<65>(0he008000000000000)) connect fpiu_io_in_bits_req.in3, _fpiu_io_in_bits_req_in3_T_4 when io.req.bits.uop.fp_ctrl.swap23 : connect fpiu_io_in_bits_req.in3, fpiu_io_in_bits_req.in2 connect fpiu_io_in_bits_req.typ, io.req.bits.uop.fp_typ node _fpiu_io_in_bits_req_fmt_T = eq(io.req.bits.uop.fp_ctrl.typeTagIn, UInt<1>(0h0)) node _fpiu_io_in_bits_req_fmt_T_1 = mux(_fpiu_io_in_bits_req_fmt_T, UInt<1>(0h0), UInt<1>(0h1)) connect fpiu_io_in_bits_req.fmt, _fpiu_io_in_bits_req_fmt_T_1 node _fpiu_io_in_bits_T = eq(io.req.bits.uop.fp_ctrl.typeTagOut, UInt<1>(0h0)) node _fpiu_io_in_bits_T_1 = and(io.req.bits.uop.fp_ctrl.toint, _fpiu_io_in_bits_T) node _fpiu_io_in_bits_T_2 = eq(io.req.bits.uop.fp_ctrl.wflags, UInt<1>(0h0)) node _fpiu_io_in_bits_T_3 = and(_fpiu_io_in_bits_T_1, _fpiu_io_in_bits_T_2) when _fpiu_io_in_bits_T_3 : connect fpiu_io_in_bits_req.fmt, UInt<1>(0h0) connect fpiu_io_in_bits_req.fmaCmd, io.req.bits.uop.fcn_op connect fpiu.io.in.bits.in3, fpiu_io_in_bits_req.in3 connect fpiu.io.in.bits.in2, fpiu_io_in_bits_req.in2 connect fpiu.io.in.bits.in1, fpiu_io_in_bits_req.in1 connect fpiu.io.in.bits.fmt, fpiu_io_in_bits_req.fmt connect fpiu.io.in.bits.typ, fpiu_io_in_bits_req.typ connect fpiu.io.in.bits.fmaCmd, fpiu_io_in_bits_req.fmaCmd connect fpiu.io.in.bits.rm, fpiu_io_in_bits_req.rm connect fpiu.io.in.bits.vec, fpiu_io_in_bits_req.vec connect fpiu.io.in.bits.wflags, fpiu_io_in_bits_req.wflags connect fpiu.io.in.bits.sqrt, fpiu_io_in_bits_req.sqrt connect fpiu.io.in.bits.div, fpiu_io_in_bits_req.div connect fpiu.io.in.bits.fma, fpiu_io_in_bits_req.fma connect fpiu.io.in.bits.fastpipe, fpiu_io_in_bits_req.fastpipe connect fpiu.io.in.bits.toint, fpiu_io_in_bits_req.toint connect fpiu.io.in.bits.fromint, fpiu_io_in_bits_req.fromint connect fpiu.io.in.bits.typeTagOut, fpiu_io_in_bits_req.typeTagOut connect fpiu.io.in.bits.typeTagIn, fpiu_io_in_bits_req.typeTagIn connect fpiu.io.in.bits.swap23, fpiu_io_in_bits_req.swap23 connect fpiu.io.in.bits.swap12, fpiu_io_in_bits_req.swap12 connect fpiu.io.in.bits.ren3, fpiu_io_in_bits_req.ren3 connect fpiu.io.in.bits.ren2, fpiu_io_in_bits_req.ren2 connect fpiu.io.in.bits.ren1, fpiu_io_in_bits_req.ren1 connect fpiu.io.in.bits.wen, fpiu_io_in_bits_req.wen connect fpiu.io.in.bits.ldst, fpiu_io_in_bits_req.ldst node _fpiu_out_T = eq(io.req.bits.uop.fp_ctrl.fastpipe, UInt<1>(0h0)) node _fpiu_out_T_1 = and(fpiu.io.in.valid, _fpiu_out_T) reg fpiu_out_REG : UInt<1>, clock connect fpiu_out_REG, _fpiu_out_T_1 regreset fpiu_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect fpiu_out_pipe_v, fpiu_out_REG reg fpiu_out_pipe_b : { in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}, clock when fpiu_out_REG : connect fpiu_out_pipe_b, fpiu.io.out.bits regreset fpiu_out_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect fpiu_out_pipe_pipe_v, fpiu_out_pipe_v reg fpiu_out_pipe_pipe_b : { in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}, clock when fpiu_out_pipe_v : connect fpiu_out_pipe_pipe_b, fpiu_out_pipe_b regreset fpiu_out_pipe_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect fpiu_out_pipe_pipe_pipe_v, fpiu_out_pipe_pipe_v reg fpiu_out_pipe_pipe_pipe_b : { in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}, clock when fpiu_out_pipe_pipe_v : connect fpiu_out_pipe_pipe_pipe_b, fpiu_out_pipe_pipe_b wire fpiu_out : { valid : UInt<1>, bits : { in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}} connect fpiu_out.valid, fpiu_out_pipe_pipe_pipe_v connect fpiu_out.bits, fpiu_out_pipe_pipe_pipe_b wire fpiu_result : { data : UInt<65>, exc : UInt<5>} connect fpiu_result.data, fpiu_out.bits.toint connect fpiu_result.exc, fpiu_out.bits.exc inst fpmu of FPToFP connect fpmu.clock, clock connect fpmu.reset, reset node _fpmu_io_in_valid_T = and(io.req.valid, io.req.bits.uop.fp_ctrl.fastpipe) connect fpmu.io.in.valid, _fpmu_io_in_valid_T connect fpmu.io.in.bits.in3, fpiu.io.in.bits.in3 connect fpmu.io.in.bits.in2, fpiu.io.in.bits.in2 connect fpmu.io.in.bits.in1, fpiu.io.in.bits.in1 connect fpmu.io.in.bits.fmt, fpiu.io.in.bits.fmt connect fpmu.io.in.bits.typ, fpiu.io.in.bits.typ connect fpmu.io.in.bits.fmaCmd, fpiu.io.in.bits.fmaCmd connect fpmu.io.in.bits.rm, fpiu.io.in.bits.rm connect fpmu.io.in.bits.vec, fpiu.io.in.bits.vec connect fpmu.io.in.bits.wflags, fpiu.io.in.bits.wflags connect fpmu.io.in.bits.sqrt, fpiu.io.in.bits.sqrt connect fpmu.io.in.bits.div, fpiu.io.in.bits.div connect fpmu.io.in.bits.fma, fpiu.io.in.bits.fma connect fpmu.io.in.bits.fastpipe, fpiu.io.in.bits.fastpipe connect fpmu.io.in.bits.toint, fpiu.io.in.bits.toint connect fpmu.io.in.bits.fromint, fpiu.io.in.bits.fromint connect fpmu.io.in.bits.typeTagOut, fpiu.io.in.bits.typeTagOut connect fpmu.io.in.bits.typeTagIn, fpiu.io.in.bits.typeTagIn connect fpmu.io.in.bits.swap23, fpiu.io.in.bits.swap23 connect fpmu.io.in.bits.swap12, fpiu.io.in.bits.swap12 connect fpmu.io.in.bits.ren3, fpiu.io.in.bits.ren3 connect fpmu.io.in.bits.ren2, fpiu.io.in.bits.ren2 connect fpmu.io.in.bits.ren1, fpiu.io.in.bits.ren1 connect fpmu.io.in.bits.wen, fpiu.io.in.bits.wen connect fpmu.io.in.bits.ldst, fpiu.io.in.bits.ldst connect fpmu.io.lt, fpiu.io.out.bits.lt node _fpmu_double_T = and(io.req.valid, io.req.bits.uop.fp_ctrl.fastpipe) node _fpmu_double_T_1 = eq(io.req.bits.uop.fp_ctrl.typeTagOut, UInt<1>(0h1)) regreset fpmu_double_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect fpmu_double_pipe_v, _fpmu_double_T reg fpmu_double_pipe_b : UInt<1>, clock when _fpmu_double_T : connect fpmu_double_pipe_b, _fpmu_double_T_1 regreset fpmu_double_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect fpmu_double_pipe_pipe_v, fpmu_double_pipe_v reg fpmu_double_pipe_pipe_b : UInt<1>, clock when fpmu_double_pipe_v : connect fpmu_double_pipe_pipe_b, fpmu_double_pipe_b regreset fpmu_double_pipe_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect fpmu_double_pipe_pipe_pipe_v, fpmu_double_pipe_pipe_v reg fpmu_double_pipe_pipe_pipe_b : UInt<1>, clock when fpmu_double_pipe_pipe_v : connect fpmu_double_pipe_pipe_pipe_b, fpmu_double_pipe_pipe_b regreset fpmu_double_pipe_pipe_pipe_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0) connect fpmu_double_pipe_pipe_pipe_pipe_v, fpmu_double_pipe_pipe_pipe_v reg fpmu_double_pipe_pipe_pipe_pipe_b : UInt<1>, clock when fpmu_double_pipe_pipe_pipe_v : connect fpmu_double_pipe_pipe_pipe_pipe_b, fpmu_double_pipe_pipe_pipe_b wire fpmu_double_pipe_pipe_pipe_pipe_out : { valid : UInt<1>, bits : UInt<1>} connect fpmu_double_pipe_pipe_pipe_pipe_out.valid, fpmu_double_pipe_pipe_pipe_pipe_v connect fpmu_double_pipe_pipe_pipe_pipe_out.bits, fpmu_double_pipe_pipe_pipe_pipe_b node _io_resp_valid_T = or(fpiu_out.valid, fpmu.io.out.valid) node _io_resp_valid_T_1 = or(_io_resp_valid_T, sfma.io.out.valid) node _io_resp_valid_T_2 = or(_io_resp_valid_T_1, dfma.io.out.valid) connect io.resp.valid, _io_resp_valid_T_2 node _fpu_out_data_opts_bigger_swizzledNaN_T = andr(UInt<20>(0hfffff)) node _fpu_out_data_opts_bigger_swizzledNaN_T_1 = bits(dfma.io.out.bits.data, 31, 31) node _fpu_out_data_opts_bigger_swizzledNaN_T_2 = bits(dfma.io.out.bits.data, 32, 32) node _fpu_out_data_opts_bigger_swizzledNaN_T_3 = bits(dfma.io.out.bits.data, 30, 0) node fpu_out_data_opts_bigger_swizzledNaN_lo_hi = cat(UInt<20>(0hfffff), _fpu_out_data_opts_bigger_swizzledNaN_T_2) node fpu_out_data_opts_bigger_swizzledNaN_lo = cat(fpu_out_data_opts_bigger_swizzledNaN_lo_hi, _fpu_out_data_opts_bigger_swizzledNaN_T_3) node fpu_out_data_opts_bigger_swizzledNaN_hi_lo = cat(UInt<7>(0h7f), _fpu_out_data_opts_bigger_swizzledNaN_T_1) node fpu_out_data_opts_bigger_swizzledNaN_hi_hi = cat(UInt<4>(0hf), _fpu_out_data_opts_bigger_swizzledNaN_T) node fpu_out_data_opts_bigger_swizzledNaN_hi = cat(fpu_out_data_opts_bigger_swizzledNaN_hi_hi, fpu_out_data_opts_bigger_swizzledNaN_hi_lo) node fpu_out_data_opts_bigger_swizzledNaN = cat(fpu_out_data_opts_bigger_swizzledNaN_hi, fpu_out_data_opts_bigger_swizzledNaN_lo) node _fpu_out_data_opts_bigger_T = andr(UInt<3>(0h7)) node fpu_out_data_opts_bigger = mux(_fpu_out_data_opts_bigger_T, fpu_out_data_opts_bigger_swizzledNaN, UInt<65>(0h1ffffffffffffffff)) node fpu_out_data_opts_0 = or(fpu_out_data_opts_bigger, UInt<1>(0h0)) node _fpu_out_data_T = eq(UInt<1>(0h1), UInt<1>(0h1)) node _fpu_out_data_T_1 = mux(_fpu_out_data_T, dfma.io.out.bits.data, fpu_out_data_opts_0) node _fpu_out_data_opts_bigger_swizzledNaN_T_4 = andr(UInt<20>(0hfffff)) node _fpu_out_data_opts_bigger_swizzledNaN_T_5 = bits(sfma.io.out.bits.data, 31, 31) node _fpu_out_data_opts_bigger_swizzledNaN_T_6 = bits(sfma.io.out.bits.data, 32, 32) node _fpu_out_data_opts_bigger_swizzledNaN_T_7 = bits(sfma.io.out.bits.data, 30, 0) node fpu_out_data_opts_bigger_swizzledNaN_lo_hi_1 = cat(UInt<20>(0hfffff), _fpu_out_data_opts_bigger_swizzledNaN_T_6) node fpu_out_data_opts_bigger_swizzledNaN_lo_1 = cat(fpu_out_data_opts_bigger_swizzledNaN_lo_hi_1, _fpu_out_data_opts_bigger_swizzledNaN_T_7) node fpu_out_data_opts_bigger_swizzledNaN_hi_lo_1 = cat(UInt<7>(0h7f), _fpu_out_data_opts_bigger_swizzledNaN_T_5) node fpu_out_data_opts_bigger_swizzledNaN_hi_hi_1 = cat(UInt<4>(0hf), _fpu_out_data_opts_bigger_swizzledNaN_T_4) node fpu_out_data_opts_bigger_swizzledNaN_hi_1 = cat(fpu_out_data_opts_bigger_swizzledNaN_hi_hi_1, fpu_out_data_opts_bigger_swizzledNaN_hi_lo_1) node fpu_out_data_opts_bigger_swizzledNaN_1 = cat(fpu_out_data_opts_bigger_swizzledNaN_hi_1, fpu_out_data_opts_bigger_swizzledNaN_lo_1) node _fpu_out_data_opts_bigger_T_1 = andr(UInt<3>(0h7)) node fpu_out_data_opts_bigger_1 = mux(_fpu_out_data_opts_bigger_T_1, fpu_out_data_opts_bigger_swizzledNaN_1, UInt<65>(0h1ffffffffffffffff)) node fpu_out_data_opts_0_1 = or(fpu_out_data_opts_bigger_1, UInt<1>(0h0)) node _fpu_out_data_T_2 = eq(UInt<1>(0h0), UInt<1>(0h1)) node _fpu_out_data_T_3 = mux(_fpu_out_data_T_2, sfma.io.out.bits.data, fpu_out_data_opts_0_1) node _fpu_out_data_opts_bigger_swizzledNaN_T_8 = andr(UInt<20>(0hfffff)) node _fpu_out_data_opts_bigger_swizzledNaN_T_9 = bits(fpmu.io.out.bits.data, 31, 31) node _fpu_out_data_opts_bigger_swizzledNaN_T_10 = bits(fpmu.io.out.bits.data, 32, 32) node _fpu_out_data_opts_bigger_swizzledNaN_T_11 = bits(fpmu.io.out.bits.data, 30, 0) node fpu_out_data_opts_bigger_swizzledNaN_lo_hi_2 = cat(UInt<20>(0hfffff), _fpu_out_data_opts_bigger_swizzledNaN_T_10) node fpu_out_data_opts_bigger_swizzledNaN_lo_2 = cat(fpu_out_data_opts_bigger_swizzledNaN_lo_hi_2, _fpu_out_data_opts_bigger_swizzledNaN_T_11) node fpu_out_data_opts_bigger_swizzledNaN_hi_lo_2 = cat(UInt<7>(0h7f), _fpu_out_data_opts_bigger_swizzledNaN_T_9) node fpu_out_data_opts_bigger_swizzledNaN_hi_hi_2 = cat(UInt<4>(0hf), _fpu_out_data_opts_bigger_swizzledNaN_T_8) node fpu_out_data_opts_bigger_swizzledNaN_hi_2 = cat(fpu_out_data_opts_bigger_swizzledNaN_hi_hi_2, fpu_out_data_opts_bigger_swizzledNaN_hi_lo_2) node fpu_out_data_opts_bigger_swizzledNaN_2 = cat(fpu_out_data_opts_bigger_swizzledNaN_hi_2, fpu_out_data_opts_bigger_swizzledNaN_lo_2) node _fpu_out_data_opts_bigger_T_2 = andr(UInt<3>(0h7)) node fpu_out_data_opts_bigger_2 = mux(_fpu_out_data_opts_bigger_T_2, fpu_out_data_opts_bigger_swizzledNaN_2, UInt<65>(0h1ffffffffffffffff)) node fpu_out_data_opts_0_2 = or(fpu_out_data_opts_bigger_2, UInt<1>(0h0)) node _fpu_out_data_T_4 = eq(fpmu_double_pipe_pipe_pipe_pipe_out.bits, UInt<1>(0h1)) node _fpu_out_data_T_5 = mux(_fpu_out_data_T_4, fpmu.io.out.bits.data, fpu_out_data_opts_0_2) node _fpu_out_data_T_6 = mux(fpiu_out.valid, fpiu_result.data, _fpu_out_data_T_5) node _fpu_out_data_T_7 = mux(sfma.io.out.valid, _fpu_out_data_T_3, _fpu_out_data_T_6) node fpu_out_data = mux(dfma.io.out.valid, _fpu_out_data_T_1, _fpu_out_data_T_7) node _fpu_out_exc_T = mux(fpiu_out.valid, fpiu_result.exc, fpmu.io.out.bits.exc) node _fpu_out_exc_T_1 = mux(sfma.io.out.valid, sfma.io.out.bits.exc, _fpu_out_exc_T) node fpu_out_exc = mux(dfma.io.out.valid, dfma.io.out.bits.exc, _fpu_out_exc_T_1) invalidate io.resp.bits.uop.debug_tsrc invalidate io.resp.bits.uop.debug_fsrc invalidate io.resp.bits.uop.bp_xcpt_if invalidate io.resp.bits.uop.bp_debug_if invalidate io.resp.bits.uop.xcpt_ma_if invalidate io.resp.bits.uop.xcpt_ae_if invalidate io.resp.bits.uop.xcpt_pf_if invalidate io.resp.bits.uop.fp_typ invalidate io.resp.bits.uop.fp_rm invalidate io.resp.bits.uop.fp_val invalidate io.resp.bits.uop.fcn_op invalidate io.resp.bits.uop.fcn_dw invalidate io.resp.bits.uop.frs3_en invalidate io.resp.bits.uop.lrs2_rtype invalidate io.resp.bits.uop.lrs1_rtype invalidate io.resp.bits.uop.dst_rtype invalidate io.resp.bits.uop.lrs3 invalidate io.resp.bits.uop.lrs2 invalidate io.resp.bits.uop.lrs1 invalidate io.resp.bits.uop.ldst invalidate io.resp.bits.uop.ldst_is_rs1 invalidate io.resp.bits.uop.csr_cmd invalidate io.resp.bits.uop.flush_on_commit invalidate io.resp.bits.uop.is_unique invalidate io.resp.bits.uop.uses_stq invalidate io.resp.bits.uop.uses_ldq invalidate io.resp.bits.uop.mem_signed invalidate io.resp.bits.uop.mem_size invalidate io.resp.bits.uop.mem_cmd invalidate io.resp.bits.uop.exc_cause invalidate io.resp.bits.uop.exception invalidate io.resp.bits.uop.stale_pdst invalidate io.resp.bits.uop.ppred_busy invalidate io.resp.bits.uop.prs3_busy invalidate io.resp.bits.uop.prs2_busy invalidate io.resp.bits.uop.prs1_busy invalidate io.resp.bits.uop.ppred invalidate io.resp.bits.uop.prs3 invalidate io.resp.bits.uop.prs2 invalidate io.resp.bits.uop.prs1 invalidate io.resp.bits.uop.pdst invalidate io.resp.bits.uop.rxq_idx invalidate io.resp.bits.uop.stq_idx invalidate io.resp.bits.uop.ldq_idx invalidate io.resp.bits.uop.rob_idx invalidate io.resp.bits.uop.fp_ctrl.vec invalidate io.resp.bits.uop.fp_ctrl.wflags invalidate io.resp.bits.uop.fp_ctrl.sqrt invalidate io.resp.bits.uop.fp_ctrl.div invalidate io.resp.bits.uop.fp_ctrl.fma invalidate io.resp.bits.uop.fp_ctrl.fastpipe invalidate io.resp.bits.uop.fp_ctrl.toint invalidate io.resp.bits.uop.fp_ctrl.fromint invalidate io.resp.bits.uop.fp_ctrl.typeTagOut invalidate io.resp.bits.uop.fp_ctrl.typeTagIn invalidate io.resp.bits.uop.fp_ctrl.swap23 invalidate io.resp.bits.uop.fp_ctrl.swap12 invalidate io.resp.bits.uop.fp_ctrl.ren3 invalidate io.resp.bits.uop.fp_ctrl.ren2 invalidate io.resp.bits.uop.fp_ctrl.ren1 invalidate io.resp.bits.uop.fp_ctrl.wen invalidate io.resp.bits.uop.fp_ctrl.ldst invalidate io.resp.bits.uop.op2_sel invalidate io.resp.bits.uop.op1_sel invalidate io.resp.bits.uop.imm_packed invalidate io.resp.bits.uop.pimm invalidate io.resp.bits.uop.imm_sel invalidate io.resp.bits.uop.imm_rename invalidate io.resp.bits.uop.taken invalidate io.resp.bits.uop.pc_lob invalidate io.resp.bits.uop.edge_inst invalidate io.resp.bits.uop.ftq_idx invalidate io.resp.bits.uop.is_mov invalidate io.resp.bits.uop.is_rocc invalidate io.resp.bits.uop.is_sys_pc2epc invalidate io.resp.bits.uop.is_eret invalidate io.resp.bits.uop.is_amo invalidate io.resp.bits.uop.is_sfence invalidate io.resp.bits.uop.is_fencei invalidate io.resp.bits.uop.is_fence invalidate io.resp.bits.uop.is_sfb invalidate io.resp.bits.uop.br_type invalidate io.resp.bits.uop.br_tag invalidate io.resp.bits.uop.br_mask invalidate io.resp.bits.uop.dis_col_sel invalidate io.resp.bits.uop.iw_p3_bypass_hint invalidate io.resp.bits.uop.iw_p2_bypass_hint invalidate io.resp.bits.uop.iw_p1_bypass_hint invalidate io.resp.bits.uop.iw_p2_speculative_child invalidate io.resp.bits.uop.iw_p1_speculative_child invalidate io.resp.bits.uop.iw_issued_partial_dgen invalidate io.resp.bits.uop.iw_issued_partial_agen invalidate io.resp.bits.uop.iw_issued invalidate io.resp.bits.uop.fu_code[0] invalidate io.resp.bits.uop.fu_code[1] invalidate io.resp.bits.uop.fu_code[2] invalidate io.resp.bits.uop.fu_code[3] invalidate io.resp.bits.uop.fu_code[4] invalidate io.resp.bits.uop.fu_code[5] invalidate io.resp.bits.uop.fu_code[6] invalidate io.resp.bits.uop.fu_code[7] invalidate io.resp.bits.uop.fu_code[8] invalidate io.resp.bits.uop.fu_code[9] invalidate io.resp.bits.uop.iq_type[0] invalidate io.resp.bits.uop.iq_type[1] invalidate io.resp.bits.uop.iq_type[2] invalidate io.resp.bits.uop.iq_type[3] invalidate io.resp.bits.uop.debug_pc invalidate io.resp.bits.uop.is_rvc invalidate io.resp.bits.uop.debug_inst invalidate io.resp.bits.uop.inst invalidate io.resp.bits.predicated connect io.resp.bits.data, fpu_out_data connect io.resp.bits.fflags.valid, io.resp.valid connect io.resp.bits.fflags.bits, fpu_out_exc	module FPU( // @[fpu.scala:34:7] input clock, // @[fpu.scala:34:7] input reset, // @[fpu.scala:34:7] input io_req_valid, // @[fpu.scala:36:14] input [31:0] io_req_bits_uop_inst, // @[fpu.scala:36:14] input [31:0] io_req_bits_uop_debug_inst, // @[fpu.scala:36:14] input io_req_bits_uop_is_rvc, // @[fpu.scala:36:14] input [39:0] io_req_bits_uop_debug_pc, // @[fpu.scala:36:14] input io_req_bits_uop_iq_type_0, // @[fpu.scala:36:14] input io_req_bits_uop_iq_type_1, // @[fpu.scala:36:14] input io_req_bits_uop_iq_type_2, // @[fpu.scala:36:14] input io_req_bits_uop_iq_type_3, // @[fpu.scala:36:14] input io_req_bits_uop_fu_code_0, // @[fpu.scala:36:14] input io_req_bits_uop_fu_code_1, // @[fpu.scala:36:14] input io_req_bits_uop_fu_code_2, // @[fpu.scala:36:14] input io_req_bits_uop_fu_code_3, // @[fpu.scala:36:14] input io_req_bits_uop_fu_code_4, // @[fpu.scala:36:14] input io_req_bits_uop_fu_code_5, // @[fpu.scala:36:14] input io_req_bits_uop_fu_code_6, // @[fpu.scala:36:14] input io_req_bits_uop_fu_code_7, // @[fpu.scala:36:14] input io_req_bits_uop_fu_code_8, // @[fpu.scala:36:14] input io_req_bits_uop_fu_code_9, // @[fpu.scala:36:14] input io_req_bits_uop_iw_issued, // @[fpu.scala:36:14] input io_req_bits_uop_iw_issued_partial_agen, // @[fpu.scala:36:14] input io_req_bits_uop_iw_issued_partial_dgen, // @[fpu.scala:36:14] input [1:0] io_req_bits_uop_iw_p1_speculative_child, // @[fpu.scala:36:14] input [1:0] io_req_bits_uop_iw_p2_speculative_child, // @[fpu.scala:36:14] input io_req_bits_uop_iw_p1_bypass_hint, // @[fpu.scala:36:14] input io_req_bits_uop_iw_p2_bypass_hint, // @[fpu.scala:36:14] input io_req_bits_uop_iw_p3_bypass_hint, // @[fpu.scala:36:14] input [1:0] io_req_bits_uop_dis_col_sel, // @[fpu.scala:36:14] input [11:0] io_req_bits_uop_br_mask, // @[fpu.scala:36:14] input [3:0] io_req_bits_uop_br_tag, // @[fpu.scala:36:14] input [3:0] io_req_bits_uop_br_type, // @[fpu.scala:36:14] input io_req_bits_uop_is_sfb, // @[fpu.scala:36:14] input io_req_bits_uop_is_fence, // @[fpu.scala:36:14] input io_req_bits_uop_is_fencei, // @[fpu.scala:36:14] input io_req_bits_uop_is_sfence, // @[fpu.scala:36:14] input io_req_bits_uop_is_amo, // @[fpu.scala:36:14] input io_req_bits_uop_is_eret, // @[fpu.scala:36:14] input io_req_bits_uop_is_sys_pc2epc, // @[fpu.scala:36:14] input io_req_bits_uop_is_rocc, // @[fpu.scala:36:14] input io_req_bits_uop_is_mov, // @[fpu.scala:36:14] input [4:0] io_req_bits_uop_ftq_idx, // @[fpu.scala:36:14] input io_req_bits_uop_edge_inst, // @[fpu.scala:36:14] input [5:0] io_req_bits_uop_pc_lob, // @[fpu.scala:36:14] input io_req_bits_uop_taken, // @[fpu.scala:36:14] input io_req_bits_uop_imm_rename, // @[fpu.scala:36:14] input [2:0] io_req_bits_uop_imm_sel, // @[fpu.scala:36:14] input [4:0] io_req_bits_uop_pimm, // @[fpu.scala:36:14] input [19:0] io_req_bits_uop_imm_packed, // @[fpu.scala:36:14] input [1:0] io_req_bits_uop_op1_sel, // @[fpu.scala:36:14] input [2:0] io_req_bits_uop_op2_sel, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_ldst, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_wen, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_ren1, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_ren2, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_ren3, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_swap12, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_swap23, // @[fpu.scala:36:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagIn, // @[fpu.scala:36:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagOut, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_fromint, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_toint, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_fastpipe, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_fma, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_div, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_sqrt, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_wflags, // @[fpu.scala:36:14] input io_req_bits_uop_fp_ctrl_vec, // @[fpu.scala:36:14] input [5:0] io_req_bits_uop_rob_idx, // @[fpu.scala:36:14] input [3:0] io_req_bits_uop_ldq_idx, // @[fpu.scala:36:14] input [3:0] io_req_bits_uop_stq_idx, // @[fpu.scala:36:14] input [1:0] io_req_bits_uop_rxq_idx, // @[fpu.scala:36:14] input [6:0] io_req_bits_uop_pdst, // @[fpu.scala:36:14] input [6:0] io_req_bits_uop_prs1, // @[fpu.scala:36:14] input [6:0] io_req_bits_uop_prs2, // @[fpu.scala:36:14] input [6:0] io_req_bits_uop_prs3, // @[fpu.scala:36:14] input [4:0] io_req_bits_uop_ppred, // @[fpu.scala:36:14] input io_req_bits_uop_prs1_busy, // @[fpu.scala:36:14] input io_req_bits_uop_prs2_busy, // @[fpu.scala:36:14] input io_req_bits_uop_prs3_busy, // @[fpu.scala:36:14] input io_req_bits_uop_ppred_busy, // @[fpu.scala:36:14] input [6:0] io_req_bits_uop_stale_pdst, // @[fpu.scala:36:14] input io_req_bits_uop_exception, // @[fpu.scala:36:14] input [63:0] io_req_bits_uop_exc_cause, // @[fpu.scala:36:14] input [4:0] io_req_bits_uop_mem_cmd, // @[fpu.scala:36:14] input [1:0] io_req_bits_uop_mem_size, // @[fpu.scala:36:14] input io_req_bits_uop_mem_signed, // @[fpu.scala:36:14] input io_req_bits_uop_uses_ldq, // @[fpu.scala:36:14] input io_req_bits_uop_uses_stq, // @[fpu.scala:36:14] input io_req_bits_uop_is_unique, // @[fpu.scala:36:14] input io_req_bits_uop_flush_on_commit, // @[fpu.scala:36:14] input [2:0] io_req_bits_uop_csr_cmd, // @[fpu.scala:36:14] input io_req_bits_uop_ldst_is_rs1, // @[fpu.scala:36:14] input [5:0] io_req_bits_uop_ldst, // @[fpu.scala:36:14] input [5:0] io_req_bits_uop_lrs1, // @[fpu.scala:36:14] input [5:0] io_req_bits_uop_lrs2, // @[fpu.scala:36:14] input [5:0] io_req_bits_uop_lrs3, // @[fpu.scala:36:14] input [1:0] io_req_bits_uop_dst_rtype, // @[fpu.scala:36:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[fpu.scala:36:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[fpu.scala:36:14] input io_req_bits_uop_frs3_en, // @[fpu.scala:36:14] input io_req_bits_uop_fcn_dw, // @[fpu.scala:36:14] input [4:0] io_req_bits_uop_fcn_op, // @[fpu.scala:36:14] input io_req_bits_uop_fp_val, // @[fpu.scala:36:14] input [2:0] io_req_bits_uop_fp_rm, // @[fpu.scala:36:14] input [1:0] io_req_bits_uop_fp_typ, // @[fpu.scala:36:14] input io_req_bits_uop_xcpt_pf_if, // @[fpu.scala:36:14] input io_req_bits_uop_xcpt_ae_if, // @[fpu.scala:36:14] input io_req_bits_uop_xcpt_ma_if, // @[fpu.scala:36:14] input io_req_bits_uop_bp_debug_if, // @[fpu.scala:36:14] input io_req_bits_uop_bp_xcpt_if, // @[fpu.scala:36:14] input [2:0] io_req_bits_uop_debug_fsrc, // @[fpu.scala:36:14] input [2:0] io_req_bits_uop_debug_tsrc, // @[fpu.scala:36:14] input [64:0] io_req_bits_rs1_data, // @[fpu.scala:36:14] input [64:0] io_req_bits_rs2_data, // @[fpu.scala:36:14] input [64:0] io_req_bits_rs3_data, // @[fpu.scala:36:14] input [2:0] io_req_bits_fcsr_rm, // @[fpu.scala:36:14] output [64:0] io_resp_bits_data, // @[fpu.scala:36:14] output [4:0] io_resp_bits_fflags_bits // @[fpu.scala:36:14] ); wire io_resp_valid; // @[fpu.scala:34:7] wire _fpmu_io_out_valid; // @[fpu.scala:84:20] wire [64:0] _fpmu_io_out_bits_data; // @[fpu.scala:84:20] wire [4:0] _fpmu_io_out_bits_exc; // @[fpu.scala:84:20] wire _fpiu_io_out_bits_in_ldst; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_wen; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_ren1; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_ren2; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_ren3; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_swap12; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_swap23; // @[fpu.scala:75:20] wire [1:0] _fpiu_io_out_bits_in_typeTagIn; // @[fpu.scala:75:20] wire [1:0] _fpiu_io_out_bits_in_typeTagOut; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_fromint; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_toint; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_fastpipe; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_fma; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_div; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_sqrt; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_wflags; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_in_vec; // @[fpu.scala:75:20] wire [2:0] _fpiu_io_out_bits_in_rm; // @[fpu.scala:75:20] wire [1:0] _fpiu_io_out_bits_in_fmaCmd; // @[fpu.scala:75:20] wire [1:0] _fpiu_io_out_bits_in_typ; // @[fpu.scala:75:20] wire [1:0] _fpiu_io_out_bits_in_fmt; // @[fpu.scala:75:20] wire [64:0] _fpiu_io_out_bits_in_in1; // @[fpu.scala:75:20] wire [64:0] _fpiu_io_out_bits_in_in2; // @[fpu.scala:75:20] wire [64:0] _fpiu_io_out_bits_in_in3; // @[fpu.scala:75:20] wire _fpiu_io_out_bits_lt; // @[fpu.scala:75:20] wire [63:0] _fpiu_io_out_bits_store; // @[fpu.scala:75:20] wire [63:0] _fpiu_io_out_bits_toint; // @[fpu.scala:75:20] wire [4:0] _fpiu_io_out_bits_exc; // @[fpu.scala:75:20] wire _sfma_io_out_valid; // @[fpu.scala:71:20] wire [64:0] _sfma_io_out_bits_data; // @[fpu.scala:71:20] wire [4:0] _sfma_io_out_bits_exc; // @[fpu.scala:71:20] wire _dfma_io_out_valid; // @[fpu.scala:67:20] wire [64:0] _dfma_io_out_bits_data; // @[fpu.scala:67:20] wire [4:0] _dfma_io_out_bits_exc; // @[fpu.scala:67:20] wire io_req_valid_0 = io_req_valid; // @[fpu.scala:34:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[fpu.scala:34:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[fpu.scala:34:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[fpu.scala:34:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[fpu.scala:34:7] wire io_req_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0; // @[fpu.scala:34:7] wire io_req_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1; // @[fpu.scala:34:7] wire io_req_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2; // @[fpu.scala:34:7] wire io_req_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3; // @[fpu.scala:34:7] wire io_req_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0; // @[fpu.scala:34:7] wire io_req_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1; // @[fpu.scala:34:7] wire io_req_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2; // @[fpu.scala:34:7] wire io_req_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3; // @[fpu.scala:34:7] wire io_req_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4; // @[fpu.scala:34:7] wire io_req_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5; // @[fpu.scala:34:7] wire io_req_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6; // @[fpu.scala:34:7] wire io_req_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7; // @[fpu.scala:34:7] wire io_req_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8; // @[fpu.scala:34:7] wire io_req_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9; // @[fpu.scala:34:7] wire io_req_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued; // @[fpu.scala:34:7] wire io_req_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen; // @[fpu.scala:34:7] wire io_req_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen; // @[fpu.scala:34:7] wire [1:0] io_req_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child; // @[fpu.scala:34:7] wire [1:0] io_req_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child; // @[fpu.scala:34:7] wire io_req_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint; // @[fpu.scala:34:7] wire io_req_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint; // @[fpu.scala:34:7] wire io_req_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint; // @[fpu.scala:34:7] wire [1:0] io_req_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel; // @[fpu.scala:34:7] wire [11:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[fpu.scala:34:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[fpu.scala:34:7] wire [3:0] io_req_bits_uop_br_type_0 = io_req_bits_uop_br_type; // @[fpu.scala:34:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[fpu.scala:34:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[fpu.scala:34:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[fpu.scala:34:7] wire io_req_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence; // @[fpu.scala:34:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[fpu.scala:34:7] wire io_req_bits_uop_is_eret_0 = io_req_bits_uop_is_eret; // @[fpu.scala:34:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[fpu.scala:34:7] wire io_req_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc; // @[fpu.scala:34:7] wire io_req_bits_uop_is_mov_0 = io_req_bits_uop_is_mov; // @[fpu.scala:34:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[fpu.scala:34:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[fpu.scala:34:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[fpu.scala:34:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[fpu.scala:34:7] wire io_req_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename; // @[fpu.scala:34:7] wire [2:0] io_req_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel; // @[fpu.scala:34:7] wire [4:0] io_req_bits_uop_pimm_0 = io_req_bits_uop_pimm; // @[fpu.scala:34:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[fpu.scala:34:7] wire [1:0] io_req_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel; // @[fpu.scala:34:7] wire [2:0] io_req_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23; // @[fpu.scala:34:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn; // @[fpu.scala:34:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec; // @[fpu.scala:34:7] wire [5:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[fpu.scala:34:7] wire [3:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[fpu.scala:34:7] wire [3:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[fpu.scala:34:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[fpu.scala:34:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[fpu.scala:34:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[fpu.scala:34:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[fpu.scala:34:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[fpu.scala:34:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[fpu.scala:34:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[fpu.scala:34:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[fpu.scala:34:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[fpu.scala:34:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[fpu.scala:34:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[fpu.scala:34:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[fpu.scala:34:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[fpu.scala:34:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[fpu.scala:34:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[fpu.scala:34:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[fpu.scala:34:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[fpu.scala:34:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[fpu.scala:34:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[fpu.scala:34:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[fpu.scala:34:7] wire [2:0] io_req_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd; // @[fpu.scala:34:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[fpu.scala:34:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[fpu.scala:34:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[fpu.scala:34:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[fpu.scala:34:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[fpu.scala:34:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[fpu.scala:34:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[fpu.scala:34:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[fpu.scala:34:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[fpu.scala:34:7] wire io_req_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw; // @[fpu.scala:34:7] wire [4:0] io_req_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op; // @[fpu.scala:34:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[fpu.scala:34:7] wire [2:0] io_req_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm; // @[fpu.scala:34:7] wire [1:0] io_req_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ; // @[fpu.scala:34:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[fpu.scala:34:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[fpu.scala:34:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[fpu.scala:34:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[fpu.scala:34:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[fpu.scala:34:7] wire [2:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[fpu.scala:34:7] wire [2:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[fpu.scala:34:7] wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[fpu.scala:34:7] wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[fpu.scala:34:7] wire [64:0] io_req_bits_rs3_data_0 = io_req_bits_rs3_data; // @[fpu.scala:34:7] wire [2:0] io_req_bits_fcsr_rm_0 = io_req_bits_fcsr_rm; // @[fpu.scala:34:7] wire [64:0] _dfma_io_in_bits_req_in1_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _dfma_io_in_bits_req_in2_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _dfma_io_in_bits_req_in3_T = 65'h0; // @[FPU.scala:372:31] wire [4:0] fpu_out_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [4:0] fpu_out_data_opts_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26] wire [4:0] fpu_out_data_opts_bigger_swizzledNaN_hi_hi_2 = 5'h1F; // @[FPU.scala:336:26] wire _fpu_out_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42] wire _fpu_out_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56] wire _fpu_out_data_T = 1'h1; // @[package.scala:39:86] wire _fpu_out_data_opts_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42] wire _fpu_out_data_opts_bigger_T_1 = 1'h1; // @[FPU.scala:249:56] wire _fpu_out_data_opts_bigger_swizzledNaN_T_8 = 1'h1; // @[FPU.scala:338:42] wire _fpu_out_data_opts_bigger_T_2 = 1'h1; // @[FPU.scala:249:56] wire [63:0] io_resp_bits_uop_exc_cause = 64'h0; // @[fpu.scala:34:7] wire [6:0] io_resp_bits_uop_pdst = 7'h0; // @[fpu.scala:34:7] wire [6:0] io_resp_bits_uop_prs1 = 7'h0; // @[fpu.scala:34:7] wire [6:0] io_resp_bits_uop_prs2 = 7'h0; // @[fpu.scala:34:7] wire [6:0] io_resp_bits_uop_prs3 = 7'h0; // @[fpu.scala:34:7] wire [6:0] io_resp_bits_uop_stale_pdst = 7'h0; // @[fpu.scala:34:7] wire [19:0] io_resp_bits_uop_imm_packed = 20'h0; // @[fpu.scala:34:7] wire [2:0] io_resp_bits_uop_imm_sel = 3'h0; // @[fpu.scala:34:7] wire [2:0] io_resp_bits_uop_op2_sel = 3'h0; // @[fpu.scala:34:7] wire [2:0] io_resp_bits_uop_csr_cmd = 3'h0; // @[fpu.scala:34:7] wire [2:0] io_resp_bits_uop_fp_rm = 3'h0; // @[fpu.scala:34:7] wire [2:0] io_resp_bits_uop_debug_fsrc = 3'h0; // @[fpu.scala:34:7] wire [2:0] io_resp_bits_uop_debug_tsrc = 3'h0; // @[fpu.scala:34:7] wire [5:0] io_resp_bits_uop_pc_lob = 6'h0; // @[fpu.scala:34:7] wire [5:0] io_resp_bits_uop_rob_idx = 6'h0; // @[fpu.scala:34:7] wire [5:0] io_resp_bits_uop_ldst = 6'h0; // @[fpu.scala:34:7] wire [5:0] io_resp_bits_uop_lrs1 = 6'h0; // @[fpu.scala:34:7] wire [5:0] io_resp_bits_uop_lrs2 = 6'h0; // @[fpu.scala:34:7] wire [5:0] io_resp_bits_uop_lrs3 = 6'h0; // @[fpu.scala:34:7] wire [4:0] io_resp_bits_uop_ftq_idx = 5'h0; // @[fpu.scala:34:7] wire [4:0] io_resp_bits_uop_pimm = 5'h0; // @[fpu.scala:34:7] wire [4:0] io_resp_bits_uop_ppred = 5'h0; // @[fpu.scala:34:7] wire [4:0] io_resp_bits_uop_mem_cmd = 5'h0; // @[fpu.scala:34:7] wire [4:0] io_resp_bits_uop_fcn_op = 5'h0; // @[fpu.scala:34:7] wire [3:0] io_resp_bits_uop_br_tag = 4'h0; // @[fpu.scala:34:7] wire [3:0] io_resp_bits_uop_br_type = 4'h0; // @[fpu.scala:34:7] wire [3:0] io_resp_bits_uop_ldq_idx = 4'h0; // @[fpu.scala:34:7] wire [3:0] io_resp_bits_uop_stq_idx = 4'h0; // @[fpu.scala:34:7] wire [11:0] io_resp_bits_uop_br_mask = 12'h0; // @[fpu.scala:34:7] wire [1:0] io_resp_bits_uop_iw_p1_speculative_child = 2'h0; // @[fpu.scala:34:7] wire [1:0] io_resp_bits_uop_iw_p2_speculative_child = 2'h0; // @[fpu.scala:34:7] wire [1:0] io_resp_bits_uop_dis_col_sel = 2'h0; // @[fpu.scala:34:7] wire [1:0] io_resp_bits_uop_op1_sel = 2'h0; // @[fpu.scala:34:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[fpu.scala:34:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[fpu.scala:34:7] wire [1:0] io_resp_bits_uop_rxq_idx = 2'h0; // @[fpu.scala:34:7] wire [1:0] io_resp_bits_uop_mem_size = 2'h0; // @[fpu.scala:34:7] wire [1:0] io_resp_bits_uop_dst_rtype = 2'h0; // @[fpu.scala:34:7] wire [1:0] io_resp_bits_uop_lrs1_rtype = 2'h0; // @[fpu.scala:34:7] wire [1:0] io_resp_bits_uop_lrs2_rtype = 2'h0; // @[fpu.scala:34:7] wire [1:0] io_resp_bits_uop_fp_typ = 2'h0; // @[fpu.scala:34:7] wire [39:0] io_resp_bits_uop_debug_pc = 40'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_is_rvc = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_iq_type_0 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_iq_type_1 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_iq_type_2 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_iq_type_3 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fu_code_0 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fu_code_1 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fu_code_2 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fu_code_3 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fu_code_4 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fu_code_5 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fu_code_6 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fu_code_7 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fu_code_8 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fu_code_9 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_iw_issued = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_iw_issued_partial_agen = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_iw_issued_partial_dgen = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_iw_p1_bypass_hint = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_iw_p2_bypass_hint = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_iw_p3_bypass_hint = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_is_sfb = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_is_fence = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_is_fencei = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_is_sfence = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_is_amo = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_is_eret = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_is_sys_pc2epc = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_is_rocc = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_is_mov = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_edge_inst = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_taken = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_imm_rename = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_ldst = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_wen = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_ren1 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_ren2 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_ren3 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_swap12 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_swap23 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_fromint = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_toint = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_fma = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_div = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_sqrt = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_wflags = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_ctrl_vec = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_prs1_busy = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_prs2_busy = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_prs3_busy = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_ppred_busy = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_exception = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_mem_signed = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_uses_ldq = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_uses_stq = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_is_unique = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_flush_on_commit = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_ldst_is_rs1 = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_frs3_en = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fcn_dw = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_fp_val = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_xcpt_pf_if = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_xcpt_ae_if = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_xcpt_ma_if = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_bp_debug_if = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_uop_bp_xcpt_if = 1'h0; // @[fpu.scala:34:7] wire io_resp_bits_predicated = 1'h0; // @[fpu.scala:34:7] wire _fpu_out_data_T_2 = 1'h0; // @[package.scala:39:86] wire [31:0] io_resp_bits_uop_inst = 32'h0; // @[fpu.scala:34:7] wire [31:0] io_resp_bits_uop_debug_inst = 32'h0; // @[fpu.scala:34:7] wire dfma_io_in_bits_req_ldst = io_req_bits_uop_fp_ctrl_ldst_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_ldst = io_req_bits_uop_fp_ctrl_ldst_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_ldst = io_req_bits_uop_fp_ctrl_ldst_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_wen = io_req_bits_uop_fp_ctrl_wen_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_wen = io_req_bits_uop_fp_ctrl_wen_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_wen = io_req_bits_uop_fp_ctrl_wen_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_ren1 = io_req_bits_uop_fp_ctrl_ren1_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_ren1 = io_req_bits_uop_fp_ctrl_ren1_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_ren1 = io_req_bits_uop_fp_ctrl_ren1_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_ren2 = io_req_bits_uop_fp_ctrl_ren2_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_ren2 = io_req_bits_uop_fp_ctrl_ren2_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_ren2 = io_req_bits_uop_fp_ctrl_ren2_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_ren3 = io_req_bits_uop_fp_ctrl_ren3_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_ren3 = io_req_bits_uop_fp_ctrl_ren3_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_ren3 = io_req_bits_uop_fp_ctrl_ren3_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_swap12 = io_req_bits_uop_fp_ctrl_swap12_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_swap12 = io_req_bits_uop_fp_ctrl_swap12_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_swap12 = io_req_bits_uop_fp_ctrl_swap12_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_swap23 = io_req_bits_uop_fp_ctrl_swap23_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_swap23 = io_req_bits_uop_fp_ctrl_swap23_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_swap23 = io_req_bits_uop_fp_ctrl_swap23_0; // @[fpu.scala:34:7, :49:19] wire [1:0] dfma_io_in_bits_req_typeTagIn = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[fpu.scala:34:7, :49:19] wire [1:0] sfma_io_in_bits_req_typeTagIn = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[fpu.scala:34:7, :49:19] wire [1:0] fpiu_io_in_bits_req_typeTagIn = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[fpu.scala:34:7, :49:19] wire [1:0] _fpiu_io_in_bits_req_in1_truncIdx_T = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[package.scala:38:21] wire [1:0] _fpiu_io_in_bits_req_in1_truncIdx_T_1 = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[package.scala:38:21] wire [1:0] _fpiu_io_in_bits_req_in2_truncIdx_T = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[package.scala:38:21] wire [1:0] _fpiu_io_in_bits_req_in2_truncIdx_T_1 = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[package.scala:38:21] wire [1:0] _fpiu_io_in_bits_req_in3_truncIdx_T = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[package.scala:38:21] wire [1:0] _fpiu_io_in_bits_req_in3_truncIdx_T_1 = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[package.scala:38:21] wire [1:0] dfma_io_in_bits_req_typeTagOut = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[fpu.scala:34:7, :49:19] wire [1:0] sfma_io_in_bits_req_typeTagOut = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[fpu.scala:34:7, :49:19] wire [1:0] fpiu_io_in_bits_req_typeTagOut = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_fromint = io_req_bits_uop_fp_ctrl_fromint_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_fromint = io_req_bits_uop_fp_ctrl_fromint_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_fromint = io_req_bits_uop_fp_ctrl_fromint_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_toint = io_req_bits_uop_fp_ctrl_toint_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_toint = io_req_bits_uop_fp_ctrl_toint_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_toint = io_req_bits_uop_fp_ctrl_toint_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_fastpipe = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_fastpipe = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_fastpipe = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_fma = io_req_bits_uop_fp_ctrl_fma_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_fma = io_req_bits_uop_fp_ctrl_fma_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_fma = io_req_bits_uop_fp_ctrl_fma_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_div = io_req_bits_uop_fp_ctrl_div_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_div = io_req_bits_uop_fp_ctrl_div_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_div = io_req_bits_uop_fp_ctrl_div_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_sqrt = io_req_bits_uop_fp_ctrl_sqrt_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_sqrt = io_req_bits_uop_fp_ctrl_sqrt_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_sqrt = io_req_bits_uop_fp_ctrl_sqrt_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_wflags = io_req_bits_uop_fp_ctrl_wflags_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_wflags = io_req_bits_uop_fp_ctrl_wflags_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_wflags = io_req_bits_uop_fp_ctrl_wflags_0; // @[fpu.scala:34:7, :49:19] wire dfma_io_in_bits_req_vec = io_req_bits_uop_fp_ctrl_vec_0; // @[fpu.scala:34:7, :49:19] wire sfma_io_in_bits_req_vec = io_req_bits_uop_fp_ctrl_vec_0; // @[fpu.scala:34:7, :49:19] wire fpiu_io_in_bits_req_vec = io_req_bits_uop_fp_ctrl_vec_0; // @[fpu.scala:34:7, :49:19] wire [2:0] dfma_io_in_bits_req_rm = io_req_bits_uop_fp_rm_0; // @[fpu.scala:34:7, :49:19] wire [2:0] sfma_io_in_bits_req_rm = io_req_bits_uop_fp_rm_0; // @[fpu.scala:34:7, :49:19] wire [2:0] fpiu_io_in_bits_req_rm = io_req_bits_uop_fp_rm_0; // @[fpu.scala:34:7, :49:19] wire [1:0] dfma_io_in_bits_req_typ = io_req_bits_uop_fp_typ_0; // @[fpu.scala:34:7, :49:19] wire [1:0] sfma_io_in_bits_req_typ = io_req_bits_uop_fp_typ_0; // @[fpu.scala:34:7, :49:19] wire [1:0] fpiu_io_in_bits_req_typ = io_req_bits_uop_fp_typ_0; // @[fpu.scala:34:7, :49:19] wire [64:0] _dfma_io_in_bits_req_in1_T_1 = io_req_bits_rs1_data_0; // @[FPU.scala:372:26] wire [64:0] _dfma_io_in_bits_req_in2_T_1 = io_req_bits_rs2_data_0; // @[FPU.scala:372:26] wire [64:0] _dfma_io_in_bits_req_in3_T_1 = io_req_bits_rs3_data_0; // @[FPU.scala:372:26] wire _io_resp_valid_T_2; // @[fpu.scala:93:38] wire io_resp_bits_fflags_valid = io_resp_valid; // @[fpu.scala:34:7] wire [64:0] fpu_out_data; // @[fpu.scala:96:8] wire [4:0] fpu_out_exc; // @[fpu.scala:102:8] wire [4:0] io_resp_bits_fflags_bits_0; // @[fpu.scala:34:7] wire [64:0] io_resp_bits_data_0; // @[fpu.scala:34:7] wire _GEN = io_req_valid_0 & io_req_bits_uop_fp_ctrl_fma_0; // @[fpu.scala:34:7, :68:36] wire _dfma_io_in_valid_T; // @[fpu.scala:68:36] assign _dfma_io_in_valid_T = _GEN; // @[fpu.scala:68:36] wire _sfma_io_in_valid_T; // @[fpu.scala:72:36] assign _sfma_io_in_valid_T = _GEN; // @[fpu.scala:68:36, :72:36] wire _GEN_0 = io_req_bits_uop_fp_ctrl_typeTagOut_0 == 2'h1; // @[fpu.scala:34:7, :68:74] wire _dfma_io_in_valid_T_1; // @[fpu.scala:68:74] assign _dfma_io_in_valid_T_1 = _GEN_0; // @[fpu.scala:68:74] wire _fpmu_double_T_1; // @[fpu.scala:88:79] assign _fpmu_double_T_1 = _GEN_0; // @[fpu.scala:68:74, :88:79] wire _dfma_io_in_valid_T_2 = _dfma_io_in_valid_T & _dfma_io_in_valid_T_1; // @[fpu.scala:68:{36,51,74}] wire [1:0] dfma_io_in_bits_req_fmaCmd; // @[fpu.scala:49:19] wire [1:0] dfma_io_in_bits_req_fmt; // @[fpu.scala:49:19] wire [64:0] dfma_io_in_bits_req_in1; // @[fpu.scala:49:19] wire [64:0] dfma_io_in_bits_req_in2; // @[fpu.scala:49:19] wire [64:0] dfma_io_in_bits_req_in3; // @[fpu.scala:49:19] wire _dfma_io_in_bits_req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _sfma_io_in_bits_req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14] wire _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] dfma_io_in_bits_req_in1_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in1_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in1_prev_prev_sign = dfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in1_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in1_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in1_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_expOut_T \| _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in1_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in1_floats_0 = {dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _sfma_io_in_bits_req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _fpiu_io_in_bits_req_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49] wire dfma_io_in_bits_req_in1_prev_isbox = &_dfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in1_oks_0 = dfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in1 = _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:372:26] wire _dfma_io_in_bits_req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _sfma_io_in_bits_req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14] wire _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] dfma_io_in_bits_req_in2_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in2_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in2_prev_prev_sign = dfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in2_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in2_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in2_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_expOut_T \| _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in2_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in2_floats_0 = {dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _sfma_io_in_bits_req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _fpiu_io_in_bits_req_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49] wire dfma_io_in_bits_req_in2_prev_isbox = &_dfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in2_oks_0 = dfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in2 = _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:372:26] wire _dfma_io_in_bits_req_in3_prev_unswizzled_T = io_req_bits_rs3_data_0[31]; // @[FPU.scala:357:14] wire _sfma_io_in_bits_req_in3_prev_unswizzled_T = io_req_bits_rs3_data_0[31]; // @[FPU.scala:357:14] wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T = io_req_bits_rs3_data_0[31]; // @[FPU.scala:357:14] wire _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = io_req_bits_rs3_data_0[52]; // @[FPU.scala:358:14] wire _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = io_req_bits_rs3_data_0[52]; // @[FPU.scala:358:14] wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = io_req_bits_rs3_data_0[52]; // @[FPU.scala:358:14] wire [30:0] _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = io_req_bits_rs3_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = io_req_bits_rs3_data_0[30:0]; // @[FPU.scala:359:14] wire [30:0] _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = io_req_bits_rs3_data_0[30:0]; // @[FPU.scala:359:14] wire [1:0] dfma_io_in_bits_req_in3_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in3_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in3_prev_prev_sign = dfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in3_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in3_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in3_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_expOut_T \| _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in3_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in3_floats_0 = {dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in3_prev_isbox_T = io_req_bits_rs3_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _sfma_io_in_bits_req_in3_prev_isbox_T = io_req_bits_rs3_data_0[64:60]; // @[FPU.scala:332:49] wire [4:0] _fpiu_io_in_bits_req_in3_prev_isbox_T = io_req_bits_rs3_data_0[64:60]; // @[FPU.scala:332:49] wire dfma_io_in_bits_req_in3_prev_isbox = &_dfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in3_oks_0 = dfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in3 = io_req_bits_uop_fp_ctrl_swap23_0 ? dfma_io_in_bits_req_in2 : _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:372:26] wire _GEN_1 = io_req_bits_uop_fp_ctrl_typeTagIn_0 == 2'h0; // @[fpu.scala:34:7, :58:24] wire _dfma_io_in_bits_req_fmt_T; // @[fpu.scala:58:24] assign _dfma_io_in_bits_req_fmt_T = _GEN_1; // @[fpu.scala:58:24] wire _sfma_io_in_bits_req_fmt_T; // @[fpu.scala:58:24] assign _sfma_io_in_bits_req_fmt_T = _GEN_1; // @[fpu.scala:58:24] wire _fpiu_io_in_bits_req_fmt_T; // @[fpu.scala:58:24] assign _fpiu_io_in_bits_req_fmt_T = _GEN_1; // @[fpu.scala:58:24] wire _dfma_io_in_bits_req_fmt_T_1 = ~_dfma_io_in_bits_req_fmt_T; // @[fpu.scala:58:{19,24}] wire _GEN_2 = io_req_bits_uop_fp_ctrl_typeTagOut_0 == 2'h0; // @[fpu.scala:34:7, :59:47] wire _dfma_io_in_bits_T; // @[fpu.scala:59:47] assign _dfma_io_in_bits_T = _GEN_2; // @[fpu.scala:59:47] wire _sfma_io_in_valid_T_1; // @[fpu.scala:72:74] assign _sfma_io_in_valid_T_1 = _GEN_2; // @[fpu.scala:59:47, :72:74] wire _sfma_io_in_bits_T; // @[fpu.scala:59:47] assign _sfma_io_in_bits_T = _GEN_2; // @[fpu.scala:59:47] wire _fpiu_io_in_bits_T; // @[fpu.scala:59:47] assign _fpiu_io_in_bits_T = _GEN_2; // @[fpu.scala:59:47] wire _dfma_io_in_bits_T_1 = io_req_bits_uop_fp_ctrl_toint_0 & _dfma_io_in_bits_T; // @[fpu.scala:34:7, :59:{25,47}] wire _dfma_io_in_bits_T_2 = ~io_req_bits_uop_fp_ctrl_wflags_0; // @[fpu.scala:34:7, :59:56] wire _dfma_io_in_bits_T_3 = _dfma_io_in_bits_T_1 & _dfma_io_in_bits_T_2; // @[fpu.scala:59:{25,53,56}] assign dfma_io_in_bits_req_fmt = _dfma_io_in_bits_T_3 ? 2'h0 : {1'h0, _dfma_io_in_bits_req_fmt_T_1}; // @[fpu.scala:49:19, :58:{13,19}, :59:{53,73}, :60:15] assign dfma_io_in_bits_req_fmaCmd = io_req_bits_uop_fcn_op_0[1:0]; // @[fpu.scala:34:7, :49:19, :63:16] wire [1:0] sfma_io_in_bits_req_fmaCmd = io_req_bits_uop_fcn_op_0[1:0]; // @[fpu.scala:34:7, :49:19, :63:16] wire [1:0] fpiu_io_in_bits_req_fmaCmd = io_req_bits_uop_fcn_op_0[1:0]; // @[fpu.scala:34:7, :49:19, :63:16] wire _sfma_io_in_valid_T_2 = _sfma_io_in_valid_T & _sfma_io_in_valid_T_1; // @[fpu.scala:72:{36,51,74}] wire [1:0] sfma_io_in_bits_req_fmt; // @[fpu.scala:49:19] wire [64:0] sfma_io_in_bits_req_in1; // @[fpu.scala:49:19] wire [64:0] sfma_io_in_bits_req_in2; // @[fpu.scala:49:19] wire [64:0] sfma_io_in_bits_req_in3; // @[fpu.scala:49:19] wire [1:0] sfma_io_in_bits_req_in1_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in1_floats_0 = {sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in1_prev_isbox = &_sfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in1_oks_0 = sfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in1_sign = io_req_bits_rs1_data_0[64]; // @[FPU.scala:274:17] wire [51:0] sfma_io_in_bits_req_in1_fractIn = io_req_bits_rs1_data_0[51:0]; // @[FPU.scala:275:20] wire [11:0] sfma_io_in_bits_req_in1_expIn = io_req_bits_rs1_data_0[63:52]; // @[FPU.scala:276:18] wire [75:0] _sfma_io_in_bits_req_in1_fractOut_T = {sfma_io_in_bits_req_in1_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in1_fractOut = _sfma_io_in_bits_req_in1_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in1_expOut_expCode = sfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in1_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in1_expOut_commonCase = _sfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in1_expOut_T = sfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in1_expOut_T_1 = sfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in1_expOut_T_2 = _sfma_io_in_bits_req_in1_expOut_T \| _sfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in1_expOut_T_3 = sfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_4 = {sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_5 = sfma_io_in_bits_req_in1_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in1_expOut = _sfma_io_in_bits_req_in1_expOut_T_2 ? _sfma_io_in_bits_req_in1_expOut_T_4 : _sfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in1_hi = {sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in1_floats_1 = {sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in1_T = sfma_io_in_bits_req_in1_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in1_T_1 = sfma_io_in_bits_req_in1_floats_0 \| _sfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in1 = {32'h0, _sfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:372:26] wire [1:0] sfma_io_in_bits_req_in2_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in2_floats_0 = {sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in2_prev_isbox = &_sfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in2_oks_0 = sfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in2_sign = io_req_bits_rs2_data_0[64]; // @[FPU.scala:274:17] wire [51:0] sfma_io_in_bits_req_in2_fractIn = io_req_bits_rs2_data_0[51:0]; // @[FPU.scala:275:20] wire [11:0] sfma_io_in_bits_req_in2_expIn = io_req_bits_rs2_data_0[63:52]; // @[FPU.scala:276:18] wire [75:0] _sfma_io_in_bits_req_in2_fractOut_T = {sfma_io_in_bits_req_in2_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in2_fractOut = _sfma_io_in_bits_req_in2_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in2_expOut_expCode = sfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in2_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in2_expOut_commonCase = _sfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in2_expOut_T = sfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in2_expOut_T_1 = sfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in2_expOut_T_2 = _sfma_io_in_bits_req_in2_expOut_T \| _sfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in2_expOut_T_3 = sfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_4 = {sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_5 = sfma_io_in_bits_req_in2_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in2_expOut = _sfma_io_in_bits_req_in2_expOut_T_2 ? _sfma_io_in_bits_req_in2_expOut_T_4 : _sfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in2_hi = {sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in2_floats_1 = {sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in2_T = sfma_io_in_bits_req_in2_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in2_T_1 = sfma_io_in_bits_req_in2_floats_0 \| _sfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in2 = {32'h0, _sfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:372:26] wire [1:0] sfma_io_in_bits_req_in3_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in3_floats_0 = {sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in3_prev_isbox = &_sfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in3_oks_0 = sfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in3_sign = io_req_bits_rs3_data_0[64]; // @[FPU.scala:274:17] wire [51:0] sfma_io_in_bits_req_in3_fractIn = io_req_bits_rs3_data_0[51:0]; // @[FPU.scala:275:20] wire [11:0] sfma_io_in_bits_req_in3_expIn = io_req_bits_rs3_data_0[63:52]; // @[FPU.scala:276:18] wire [75:0] _sfma_io_in_bits_req_in3_fractOut_T = {sfma_io_in_bits_req_in3_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in3_fractOut = _sfma_io_in_bits_req_in3_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in3_expOut_expCode = sfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in3_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in3_expOut_commonCase = _sfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in3_expOut_T = sfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in3_expOut_T_1 = sfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in3_expOut_T_2 = _sfma_io_in_bits_req_in3_expOut_T \| _sfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in3_expOut_T_3 = sfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_4 = {sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_5 = sfma_io_in_bits_req_in3_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in3_expOut = _sfma_io_in_bits_req_in3_expOut_T_2 ? _sfma_io_in_bits_req_in3_expOut_T_4 : _sfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in3_hi = {sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in3_floats_1 = {sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in3_T = sfma_io_in_bits_req_in3_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in3_T_1 = sfma_io_in_bits_req_in3_floats_0 \| _sfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in3 = io_req_bits_uop_fp_ctrl_swap23_0 ? sfma_io_in_bits_req_in2 : {32'h0, _sfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:372:26] wire _sfma_io_in_bits_req_fmt_T_1 = ~_sfma_io_in_bits_req_fmt_T; // @[fpu.scala:58:{19,24}] wire _sfma_io_in_bits_T_1 = io_req_bits_uop_fp_ctrl_toint_0 & _sfma_io_in_bits_T; // @[fpu.scala:34:7, :59:{25,47}] wire _sfma_io_in_bits_T_2 = ~io_req_bits_uop_fp_ctrl_wflags_0; // @[fpu.scala:34:7, :59:56] wire _sfma_io_in_bits_T_3 = _sfma_io_in_bits_T_1 & _sfma_io_in_bits_T_2; // @[fpu.scala:59:{25,53,56}] assign sfma_io_in_bits_req_fmt = _sfma_io_in_bits_T_3 ? 2'h0 : {1'h0, _sfma_io_in_bits_req_fmt_T_1}; // @[fpu.scala:49:19, :58:{13,19}, :59:{53,73}, :60:15] wire _fpiu_io_in_valid_T = io_req_bits_uop_fp_ctrl_fastpipe_0 & io_req_bits_uop_fp_ctrl_wflags_0; // @[fpu.scala:34:7, :76:75] wire _fpiu_io_in_valid_T_1 = io_req_bits_uop_fp_ctrl_toint_0 \| _fpiu_io_in_valid_T; // @[fpu.scala:34:7, :76:{54,75}] wire _fpiu_io_in_valid_T_2 = io_req_valid_0 & _fpiu_io_in_valid_T_1; // @[fpu.scala:34:7, :76:{36,54}] wire [64:0] _fpiu_io_in_bits_req_in1_T_4; // @[FPU.scala:369:10] wire [64:0] _fpiu_io_in_bits_req_in2_T_4; // @[FPU.scala:369:10] wire [1:0] fpiu_io_in_bits_req_fmt; // @[fpu.scala:49:19] wire [64:0] fpiu_io_in_bits_req_in1; // @[fpu.scala:49:19] wire [64:0] fpiu_io_in_bits_req_in2; // @[fpu.scala:49:19] wire [64:0] fpiu_io_in_bits_req_in3; // @[fpu.scala:49:19] wire [1:0] fpiu_io_in_bits_req_in1_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in1_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in1_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in1_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in1_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T \| _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in1_floats_0 = {fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in1_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in1_oks_0 = fpiu_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in1_truncIdx = _fpiu_io_in_bits_req_in1_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in1_T = fpiu_io_in_bits_req_in1_truncIdx; // @[package.scala:38:47, :39:86] wire _fpiu_io_in_bits_req_in1_T_1 = _fpiu_io_in_bits_req_in1_T \| fpiu_io_in_bits_req_in1_oks_0; // @[package.scala:39:{76,86}] wire fpiu_io_in_bits_req_in1_truncIdx_1 = _fpiu_io_in_bits_req_in1_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in1_T_2 = fpiu_io_in_bits_req_in1_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _fpiu_io_in_bits_req_in1_T_3 = _fpiu_io_in_bits_req_in1_T_2 ? io_req_bits_rs1_data_0 : fpiu_io_in_bits_req_in1_floats_0; // @[package.scala:39:{76,86}] assign _fpiu_io_in_bits_req_in1_T_4 = _fpiu_io_in_bits_req_in1_T_1 ? _fpiu_io_in_bits_req_in1_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in1 = _fpiu_io_in_bits_req_in1_T_4; // @[FPU.scala:369:10] wire [1:0] fpiu_io_in_bits_req_in2_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in2_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in2_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in2_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in2_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T \| _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in2_floats_0 = {fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in2_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in2_oks_0 = fpiu_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in2_truncIdx = _fpiu_io_in_bits_req_in2_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in2_T = fpiu_io_in_bits_req_in2_truncIdx; // @[package.scala:38:47, :39:86] wire _fpiu_io_in_bits_req_in2_T_1 = _fpiu_io_in_bits_req_in2_T \| fpiu_io_in_bits_req_in2_oks_0; // @[package.scala:39:{76,86}] wire fpiu_io_in_bits_req_in2_truncIdx_1 = _fpiu_io_in_bits_req_in2_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in2_T_2 = fpiu_io_in_bits_req_in2_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _fpiu_io_in_bits_req_in2_T_3 = _fpiu_io_in_bits_req_in2_T_2 ? io_req_bits_rs2_data_0 : fpiu_io_in_bits_req_in2_floats_0; // @[package.scala:39:{76,86}] assign _fpiu_io_in_bits_req_in2_T_4 = _fpiu_io_in_bits_req_in2_T_1 ? _fpiu_io_in_bits_req_in2_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in2 = _fpiu_io_in_bits_req_in2_T_4; // @[FPU.scala:369:10] wire [1:0] fpiu_io_in_bits_req_in3_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in3_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in3_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in3_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in3_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T \| _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in3_floats_0 = {fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in3_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in3_oks_0 = fpiu_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in3_truncIdx = _fpiu_io_in_bits_req_in3_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in3_T = fpiu_io_in_bits_req_in3_truncIdx; // @[package.scala:38:47, :39:86] wire _fpiu_io_in_bits_req_in3_T_1 = _fpiu_io_in_bits_req_in3_T \| fpiu_io_in_bits_req_in3_oks_0; // @[package.scala:39:{76,86}] wire fpiu_io_in_bits_req_in3_truncIdx_1 = _fpiu_io_in_bits_req_in3_truncIdx_T_1[0]; // @[package.scala:38:{21,47}] wire _fpiu_io_in_bits_req_in3_T_2 = fpiu_io_in_bits_req_in3_truncIdx_1; // @[package.scala:38:47, :39:86] wire [64:0] _fpiu_io_in_bits_req_in3_T_3 = _fpiu_io_in_bits_req_in3_T_2 ? io_req_bits_rs3_data_0 : fpiu_io_in_bits_req_in3_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in3_T_4 = _fpiu_io_in_bits_req_in3_T_1 ? _fpiu_io_in_bits_req_in3_T_3 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in3 = io_req_bits_uop_fp_ctrl_swap23_0 ? fpiu_io_in_bits_req_in2 : _fpiu_io_in_bits_req_in3_T_4; // @[FPU.scala:369:10] wire _fpiu_io_in_bits_req_fmt_T_1 = ~_fpiu_io_in_bits_req_fmt_T; // @[fpu.scala:58:{19,24}] wire _fpiu_io_in_bits_T_1 = io_req_bits_uop_fp_ctrl_toint_0 & _fpiu_io_in_bits_T; // @[fpu.scala:34:7, :59:{25,47}] wire _fpiu_io_in_bits_T_2 = ~io_req_bits_uop_fp_ctrl_wflags_0; // @[fpu.scala:34:7, :59:56] wire _fpiu_io_in_bits_T_3 = _fpiu_io_in_bits_T_1 & _fpiu_io_in_bits_T_2; // @[fpu.scala:59:{25,53,56}] assign fpiu_io_in_bits_req_fmt = _fpiu_io_in_bits_T_3 ? 2'h0 : {1'h0, _fpiu_io_in_bits_req_fmt_T_1}; // @[fpu.scala:49:19, :58:{13,19}, :59:{53,73}, :60:15] wire _fpiu_out_T = ~io_req_bits_uop_fp_ctrl_fastpipe_0; // @[fpu.scala:34:7, :78:51] wire _fpiu_out_T_1 = _fpiu_io_in_valid_T_2 & _fpiu_out_T; // @[fpu.scala:76:36, :78:{48,51}] reg fpiu_out_REG; // @[fpu.scala:78:30] reg fpiu_out_pipe_v; // @[Valid.scala:141:24] reg fpiu_out_pipe_b_in_ldst; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_wen; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_ren1; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_ren2; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_ren3; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_swap12; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_swap23; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_fromint; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_toint; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_fastpipe; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_fma; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_div; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_sqrt; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_wflags; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_in_vec; // @[Valid.scala:142:26] reg [2:0] fpiu_out_pipe_b_in_rm; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_typ; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_b_in_fmt; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_b_in_in1; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_b_in_in2; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_b_in_in3; // @[Valid.scala:142:26] reg fpiu_out_pipe_b_lt; // @[Valid.scala:142:26] reg [63:0] fpiu_out_pipe_b_store; // @[Valid.scala:142:26] reg [63:0] fpiu_out_pipe_b_toint; // @[Valid.scala:142:26] reg [4:0] fpiu_out_pipe_b_exc; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_v; // @[Valid.scala:141:24] reg fpiu_out_pipe_pipe_b_in_ldst; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_wen; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_ren1; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_ren2; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_ren3; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_swap12; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_swap23; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_fromint; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_toint; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_fastpipe; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_fma; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_div; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_sqrt; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_wflags; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_in_vec; // @[Valid.scala:142:26] reg [2:0] fpiu_out_pipe_pipe_b_in_rm; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_typ; // @[Valid.scala:142:26] reg [1:0] fpiu_out_pipe_pipe_b_in_fmt; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_pipe_b_in_in1; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_pipe_b_in_in2; // @[Valid.scala:142:26] reg [64:0] fpiu_out_pipe_pipe_b_in_in3; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_b_lt; // @[Valid.scala:142:26] reg [63:0] fpiu_out_pipe_pipe_b_store; // @[Valid.scala:142:26] reg [63:0] fpiu_out_pipe_pipe_b_toint; // @[Valid.scala:142:26] reg [4:0] fpiu_out_pipe_pipe_b_exc; // @[Valid.scala:142:26] reg fpiu_out_pipe_pipe_pipe_v; // @[Valid.scala:141:24] wire fpiu_out_valid = fpiu_out_pipe_pipe_pipe_v; // @[Valid.scala:135:21, :141:24] reg fpiu_out_pipe_pipe_pipe_b_in_ldst; // @[Valid.scala:142:26] wire fpiu_out_bits_in_ldst = fpiu_out_pipe_pipe_pipe_b_in_ldst; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_wen; // @[Valid.scala:142:26] wire fpiu_out_bits_in_wen = fpiu_out_pipe_pipe_pipe_b_in_wen; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_ren1; // @[Valid.scala:142:26] wire fpiu_out_bits_in_ren1 = fpiu_out_pipe_pipe_pipe_b_in_ren1; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_ren2; // @[Valid.scala:142:26] wire fpiu_out_bits_in_ren2 = fpiu_out_pipe_pipe_pipe_b_in_ren2; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_ren3; // @[Valid.scala:142:26] wire fpiu_out_bits_in_ren3 = fpiu_out_pipe_pipe_pipe_b_in_ren3; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_swap12; // @[Valid.scala:142:26] wire fpiu_out_bits_in_swap12 = fpiu_out_pipe_pipe_pipe_b_in_swap12; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_swap23; // @[Valid.scala:142:26] wire fpiu_out_bits_in_swap23 = fpiu_out_pipe_pipe_pipe_b_in_swap23; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_typeTagIn = fpiu_out_pipe_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_typeTagOut = fpiu_out_pipe_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_fromint; // @[Valid.scala:142:26] wire fpiu_out_bits_in_fromint = fpiu_out_pipe_pipe_pipe_b_in_fromint; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_toint; // @[Valid.scala:142:26] wire fpiu_out_bits_in_toint = fpiu_out_pipe_pipe_pipe_b_in_toint; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_fastpipe; // @[Valid.scala:142:26] wire fpiu_out_bits_in_fastpipe = fpiu_out_pipe_pipe_pipe_b_in_fastpipe; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_fma; // @[Valid.scala:142:26] wire fpiu_out_bits_in_fma = fpiu_out_pipe_pipe_pipe_b_in_fma; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_div; // @[Valid.scala:142:26] wire fpiu_out_bits_in_div = fpiu_out_pipe_pipe_pipe_b_in_div; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_sqrt; // @[Valid.scala:142:26] wire fpiu_out_bits_in_sqrt = fpiu_out_pipe_pipe_pipe_b_in_sqrt; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_wflags; // @[Valid.scala:142:26] wire fpiu_out_bits_in_wflags = fpiu_out_pipe_pipe_pipe_b_in_wflags; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_in_vec; // @[Valid.scala:142:26] wire fpiu_out_bits_in_vec = fpiu_out_pipe_pipe_pipe_b_in_vec; // @[Valid.scala:135:21, :142:26] reg [2:0] fpiu_out_pipe_pipe_pipe_b_in_rm; // @[Valid.scala:142:26] wire [2:0] fpiu_out_bits_in_rm = fpiu_out_pipe_pipe_pipe_b_in_rm; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_fmaCmd = fpiu_out_pipe_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_typ; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_typ = fpiu_out_pipe_pipe_pipe_b_in_typ; // @[Valid.scala:135:21, :142:26] reg [1:0] fpiu_out_pipe_pipe_pipe_b_in_fmt; // @[Valid.scala:142:26] wire [1:0] fpiu_out_bits_in_fmt = fpiu_out_pipe_pipe_pipe_b_in_fmt; // @[Valid.scala:135:21, :142:26] reg [64:0] fpiu_out_pipe_pipe_pipe_b_in_in1; // @[Valid.scala:142:26] wire [64:0] fpiu_out_bits_in_in1 = fpiu_out_pipe_pipe_pipe_b_in_in1; // @[Valid.scala:135:21, :142:26] reg [64:0] fpiu_out_pipe_pipe_pipe_b_in_in2; // @[Valid.scala:142:26] wire [64:0] fpiu_out_bits_in_in2 = fpiu_out_pipe_pipe_pipe_b_in_in2; // @[Valid.scala:135:21, :142:26] reg [64:0] fpiu_out_pipe_pipe_pipe_b_in_in3; // @[Valid.scala:142:26] wire [64:0] fpiu_out_bits_in_in3 = fpiu_out_pipe_pipe_pipe_b_in_in3; // @[Valid.scala:135:21, :142:26] reg fpiu_out_pipe_pipe_pipe_b_lt; // @[Valid.scala:142:26] wire fpiu_out_bits_lt = fpiu_out_pipe_pipe_pipe_b_lt; // @[Valid.scala:135:21, :142:26] reg [63:0] fpiu_out_pipe_pipe_pipe_b_store; // @[Valid.scala:142:26] wire [63:0] fpiu_out_bits_store = fpiu_out_pipe_pipe_pipe_b_store; // @[Valid.scala:135:21, :142:26] reg [63:0] fpiu_out_pipe_pipe_pipe_b_toint; // @[Valid.scala:142:26] wire [63:0] fpiu_out_bits_toint = fpiu_out_pipe_pipe_pipe_b_toint; // @[Valid.scala:135:21, :142:26] reg [4:0] fpiu_out_pipe_pipe_pipe_b_exc; // @[Valid.scala:142:26] wire [4:0] fpiu_out_bits_exc = fpiu_out_pipe_pipe_pipe_b_exc; // @[Valid.scala:135:21, :142:26] wire [4:0] fpiu_result_exc = fpiu_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] fpiu_result_data; // @[fpu.scala:80:26] assign fpiu_result_data = {1'h0, fpiu_out_bits_toint}; // @[Valid.scala:135:21] wire _GEN_3 = io_req_valid_0 & io_req_bits_uop_fp_ctrl_fastpipe_0; // @[fpu.scala:34:7, :85:36] wire _fpmu_io_in_valid_T; // @[fpu.scala:85:36] assign _fpmu_io_in_valid_T = _GEN_3; // @[fpu.scala:85:36] wire _fpmu_double_T; // @[fpu.scala:88:39] assign _fpmu_double_T = _GEN_3; // @[fpu.scala:85:36, :88:39] reg fpmu_double_pipe_v; // @[Valid.scala:141:24] reg fpmu_double_pipe_b; // @[Valid.scala:142:26] reg fpmu_double_pipe_pipe_v; // @[Valid.scala:141:24] reg fpmu_double_pipe_pipe_b; // @[Valid.scala:142:26] reg fpmu_double_pipe_pipe_pipe_v; // @[Valid.scala:141:24] reg fpmu_double_pipe_pipe_pipe_b; // @[Valid.scala:142:26] reg fpmu_double_pipe_pipe_pipe_pipe_v; // @[Valid.scala:141:24] wire fpmu_double_pipe_pipe_pipe_pipe_out_valid = fpmu_double_pipe_pipe_pipe_pipe_v; // @[Valid.scala:135:21, :141:24] reg fpmu_double_pipe_pipe_pipe_pipe_b; // @[Valid.scala:142:26] wire fpmu_double_pipe_pipe_pipe_pipe_out_bits = fpmu_double_pipe_pipe_pipe_pipe_b; // @[Valid.scala:135:21, :142:26] wire _fpu_out_data_T_4 = fpmu_double_pipe_pipe_pipe_pipe_out_bits; // @[Valid.scala:135:21] wire _io_resp_valid_T = fpiu_out_valid \| _fpmu_io_out_valid; // @[Valid.scala:135:21] wire _io_resp_valid_T_1 = _io_resp_valid_T \| _sfma_io_out_valid; // @[fpu.scala:71:20, :91:35, :92:38] assign _io_resp_valid_T_2 = _io_resp_valid_T_1 \| _dfma_io_out_valid; // @[fpu.scala:67:20, :92:38, :93:38] assign io_resp_valid = _io_resp_valid_T_2; // @[fpu.scala:34:7, :93:38] wire _fpu_out_data_opts_bigger_swizzledNaN_T_1 = _dfma_io_out_bits_data[31]; // @[FPU.scala:340:8] wire _fpu_out_data_opts_bigger_swizzledNaN_T_2 = _dfma_io_out_bits_data[32]; // @[FPU.scala:342:8] wire [30:0] _fpu_out_data_opts_bigger_swizzledNaN_T_3 = _dfma_io_out_bits_data[30:0]; // @[FPU.scala:343:8] wire [20:0] fpu_out_data_opts_bigger_swizzledNaN_lo_hi = {20'hFFFFF, _fpu_out_data_opts_bigger_swizzledNaN_T_2}; // @[FPU.scala:336:26, :342:8] wire [51:0] fpu_out_data_opts_bigger_swizzledNaN_lo = {fpu_out_data_opts_bigger_swizzledNaN_lo_hi, _fpu_out_data_opts_bigger_swizzledNaN_T_3}; // @[FPU.scala:336:26, :343:8] wire [7:0] fpu_out_data_opts_bigger_swizzledNaN_hi_lo = {7'h7F, _fpu_out_data_opts_bigger_swizzledNaN_T_1}; // @[FPU.scala:336:26, :340:8] wire [12:0] fpu_out_data_opts_bigger_swizzledNaN_hi = {5'h1F, fpu_out_data_opts_bigger_swizzledNaN_hi_lo}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_swizzledNaN = {fpu_out_data_opts_bigger_swizzledNaN_hi, fpu_out_data_opts_bigger_swizzledNaN_lo}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger = fpu_out_data_opts_bigger_swizzledNaN; // @[FPU.scala:336:26, :344:8] wire [64:0] fpu_out_data_opts_0 = fpu_out_data_opts_bigger; // @[FPU.scala:344:8, :398:14] wire _fpu_out_data_opts_bigger_swizzledNaN_T_5 = _sfma_io_out_bits_data[31]; // @[FPU.scala:340:8] wire _fpu_out_data_opts_bigger_swizzledNaN_T_6 = _sfma_io_out_bits_data[32]; // @[FPU.scala:342:8] wire [30:0] _fpu_out_data_opts_bigger_swizzledNaN_T_7 = _sfma_io_out_bits_data[30:0]; // @[FPU.scala:343:8] wire [20:0] fpu_out_data_opts_bigger_swizzledNaN_lo_hi_1 = {20'hFFFFF, _fpu_out_data_opts_bigger_swizzledNaN_T_6}; // @[FPU.scala:336:26, :342:8] wire [51:0] fpu_out_data_opts_bigger_swizzledNaN_lo_1 = {fpu_out_data_opts_bigger_swizzledNaN_lo_hi_1, _fpu_out_data_opts_bigger_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8] wire [7:0] fpu_out_data_opts_bigger_swizzledNaN_hi_lo_1 = {7'h7F, _fpu_out_data_opts_bigger_swizzledNaN_T_5}; // @[FPU.scala:336:26, :340:8] wire [12:0] fpu_out_data_opts_bigger_swizzledNaN_hi_1 = {5'h1F, fpu_out_data_opts_bigger_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_swizzledNaN_1 = {fpu_out_data_opts_bigger_swizzledNaN_hi_1, fpu_out_data_opts_bigger_swizzledNaN_lo_1}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_1 = fpu_out_data_opts_bigger_swizzledNaN_1; // @[FPU.scala:336:26, :344:8] wire [64:0] fpu_out_data_opts_0_1 = fpu_out_data_opts_bigger_1; // @[FPU.scala:344:8, :398:14] wire [64:0] _fpu_out_data_T_3 = fpu_out_data_opts_0_1; // @[package.scala:39:76] wire _fpu_out_data_opts_bigger_swizzledNaN_T_9 = _fpmu_io_out_bits_data[31]; // @[FPU.scala:340:8] wire _fpu_out_data_opts_bigger_swizzledNaN_T_10 = _fpmu_io_out_bits_data[32]; // @[FPU.scala:342:8] wire [30:0] _fpu_out_data_opts_bigger_swizzledNaN_T_11 = _fpmu_io_out_bits_data[30:0]; // @[FPU.scala:343:8] wire [20:0] fpu_out_data_opts_bigger_swizzledNaN_lo_hi_2 = {20'hFFFFF, _fpu_out_data_opts_bigger_swizzledNaN_T_10}; // @[FPU.scala:336:26, :342:8] wire [51:0] fpu_out_data_opts_bigger_swizzledNaN_lo_2 = {fpu_out_data_opts_bigger_swizzledNaN_lo_hi_2, _fpu_out_data_opts_bigger_swizzledNaN_T_11}; // @[FPU.scala:336:26, :343:8] wire [7:0] fpu_out_data_opts_bigger_swizzledNaN_hi_lo_2 = {7'h7F, _fpu_out_data_opts_bigger_swizzledNaN_T_9}; // @[FPU.scala:336:26, :340:8] wire [12:0] fpu_out_data_opts_bigger_swizzledNaN_hi_2 = {5'h1F, fpu_out_data_opts_bigger_swizzledNaN_hi_lo_2}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_swizzledNaN_2 = {fpu_out_data_opts_bigger_swizzledNaN_hi_2, fpu_out_data_opts_bigger_swizzledNaN_lo_2}; // @[FPU.scala:336:26] wire [64:0] fpu_out_data_opts_bigger_2 = fpu_out_data_opts_bigger_swizzledNaN_2; // @[FPU.scala:336:26, :344:8] wire [64:0] fpu_out_data_opts_0_2 = fpu_out_data_opts_bigger_2; // @[FPU.scala:344:8, :398:14] wire [64:0] _fpu_out_data_T_5 = _fpu_out_data_T_4 ? _fpmu_io_out_bits_data : fpu_out_data_opts_0_2; // @[package.scala:39:{76,86}] wire [64:0] _fpu_out_data_T_6 = fpiu_out_valid ? fpiu_result_data : _fpu_out_data_T_5; // @[Valid.scala:135:21] wire [64:0] _fpu_out_data_T_7 = _sfma_io_out_valid ? _fpu_out_data_T_3 : _fpu_out_data_T_6; // @[package.scala:39:76] wire [64:0] _fpu_out_data_T_1; // @[package.scala:39:76] assign fpu_out_data = _dfma_io_out_valid ? _fpu_out_data_T_1 : _fpu_out_data_T_7; // @[package.scala:39:76] assign io_resp_bits_data_0 = fpu_out_data; // @[fpu.scala:34:7, :96:8] wire [4:0] _fpu_out_exc_T = fpiu_out_valid ? fpiu_result_exc : _fpmu_io_out_bits_exc; // @[Valid.scala:135:21] wire [4:0] _fpu_out_exc_T_1 = _sfma_io_out_valid ? _sfma_io_out_bits_exc : _fpu_out_exc_T; // @[fpu.scala:71:20, :103:8, :104:8] assign fpu_out_exc = _dfma_io_out_valid ? _dfma_io_out_bits_exc : _fpu_out_exc_T_1; // @[fpu.scala:67:20, :102:8, :103:8] assign io_resp_bits_fflags_bits_0 = fpu_out_exc; // @[fpu.scala:34:7, :102:8] always @(posedge clock) begin // @[fpu.scala:34:7] fpiu_out_REG <= _fpiu_out_T_1; // @[fpu.scala:78:{30,48}] if (fpiu_out_REG) begin // @[fpu.scala:78:30] fpiu_out_pipe_b_in_ldst <= _fpiu_io_out_bits_in_ldst; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_wen <= _fpiu_io_out_bits_in_wen; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_ren1 <= _fpiu_io_out_bits_in_ren1; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_ren2 <= _fpiu_io_out_bits_in_ren2; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_ren3 <= _fpiu_io_out_bits_in_ren3; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_swap12 <= _fpiu_io_out_bits_in_swap12; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_swap23 <= _fpiu_io_out_bits_in_swap23; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_typeTagIn <= _fpiu_io_out_bits_in_typeTagIn; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_typeTagOut <= _fpiu_io_out_bits_in_typeTagOut; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fromint <= _fpiu_io_out_bits_in_fromint; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_toint <= _fpiu_io_out_bits_in_toint; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fastpipe <= _fpiu_io_out_bits_in_fastpipe; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fma <= _fpiu_io_out_bits_in_fma; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_div <= _fpiu_io_out_bits_in_div; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_sqrt <= _fpiu_io_out_bits_in_sqrt; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_wflags <= _fpiu_io_out_bits_in_wflags; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_vec <= _fpiu_io_out_bits_in_vec; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_rm <= _fpiu_io_out_bits_in_rm; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fmaCmd <= _fpiu_io_out_bits_in_fmaCmd; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_typ <= _fpiu_io_out_bits_in_typ; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_fmt <= _fpiu_io_out_bits_in_fmt; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_in1 <= _fpiu_io_out_bits_in_in1; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_in2 <= _fpiu_io_out_bits_in_in2; // @[Valid.scala:142:26] fpiu_out_pipe_b_in_in3 <= _fpiu_io_out_bits_in_in3; // @[Valid.scala:142:26] fpiu_out_pipe_b_lt <= _fpiu_io_out_bits_lt; // @[Valid.scala:142:26] fpiu_out_pipe_b_store <= _fpiu_io_out_bits_store; // @[Valid.scala:142:26] fpiu_out_pipe_b_toint <= _fpiu_io_out_bits_toint; // @[Valid.scala:142:26] fpiu_out_pipe_b_exc <= _fpiu_io_out_bits_exc; // @[Valid.scala:142:26] end if (fpiu_out_pipe_v) begin // @[Valid.scala:141:24] fpiu_out_pipe_pipe_b_in_ldst <= fpiu_out_pipe_b_in_ldst; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_wen <= fpiu_out_pipe_b_in_wen; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_ren1 <= fpiu_out_pipe_b_in_ren1; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_ren2 <= fpiu_out_pipe_b_in_ren2; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_ren3 <= fpiu_out_pipe_b_in_ren3; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_swap12 <= fpiu_out_pipe_b_in_swap12; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_swap23 <= fpiu_out_pipe_b_in_swap23; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_typeTagIn <= fpiu_out_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_typeTagOut <= fpiu_out_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fromint <= fpiu_out_pipe_b_in_fromint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_toint <= fpiu_out_pipe_b_in_toint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fastpipe <= fpiu_out_pipe_b_in_fastpipe; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fma <= fpiu_out_pipe_b_in_fma; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_div <= fpiu_out_pipe_b_in_div; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_sqrt <= fpiu_out_pipe_b_in_sqrt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_wflags <= fpiu_out_pipe_b_in_wflags; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_vec <= fpiu_out_pipe_b_in_vec; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_rm <= fpiu_out_pipe_b_in_rm; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fmaCmd <= fpiu_out_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_typ <= fpiu_out_pipe_b_in_typ; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_fmt <= fpiu_out_pipe_b_in_fmt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_in1 <= fpiu_out_pipe_b_in_in1; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_in2 <= fpiu_out_pipe_b_in_in2; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_in_in3 <= fpiu_out_pipe_b_in_in3; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_lt <= fpiu_out_pipe_b_lt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_store <= fpiu_out_pipe_b_store; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_toint <= fpiu_out_pipe_b_toint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_b_exc <= fpiu_out_pipe_b_exc; // @[Valid.scala:142:26] end if (fpiu_out_pipe_pipe_v) begin // @[Valid.scala:141:24] fpiu_out_pipe_pipe_pipe_b_in_ldst <= fpiu_out_pipe_pipe_b_in_ldst; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_wen <= fpiu_out_pipe_pipe_b_in_wen; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_ren1 <= fpiu_out_pipe_pipe_b_in_ren1; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_ren2 <= fpiu_out_pipe_pipe_b_in_ren2; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_ren3 <= fpiu_out_pipe_pipe_b_in_ren3; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_swap12 <= fpiu_out_pipe_pipe_b_in_swap12; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_swap23 <= fpiu_out_pipe_pipe_b_in_swap23; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_typeTagIn <= fpiu_out_pipe_pipe_b_in_typeTagIn; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_typeTagOut <= fpiu_out_pipe_pipe_b_in_typeTagOut; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fromint <= fpiu_out_pipe_pipe_b_in_fromint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_toint <= fpiu_out_pipe_pipe_b_in_toint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fastpipe <= fpiu_out_pipe_pipe_b_in_fastpipe; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fma <= fpiu_out_pipe_pipe_b_in_fma; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_div <= fpiu_out_pipe_pipe_b_in_div; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_sqrt <= fpiu_out_pipe_pipe_b_in_sqrt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_wflags <= fpiu_out_pipe_pipe_b_in_wflags; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_vec <= fpiu_out_pipe_pipe_b_in_vec; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_rm <= fpiu_out_pipe_pipe_b_in_rm; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fmaCmd <= fpiu_out_pipe_pipe_b_in_fmaCmd; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_typ <= fpiu_out_pipe_pipe_b_in_typ; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_fmt <= fpiu_out_pipe_pipe_b_in_fmt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_in1 <= fpiu_out_pipe_pipe_b_in_in1; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_in2 <= fpiu_out_pipe_pipe_b_in_in2; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_in_in3 <= fpiu_out_pipe_pipe_b_in_in3; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_lt <= fpiu_out_pipe_pipe_b_lt; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_store <= fpiu_out_pipe_pipe_b_store; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_toint <= fpiu_out_pipe_pipe_b_toint; // @[Valid.scala:142:26] fpiu_out_pipe_pipe_pipe_b_exc <= fpiu_out_pipe_pipe_b_exc; // @[Valid.scala:142:26] end if (_fpmu_double_T) // @[fpu.scala:88:39] fpmu_double_pipe_b <= _fpmu_double_T_1; // @[Valid.scala:142:26] if (fpmu_double_pipe_v) // @[Valid.scala:141:24] fpmu_double_pipe_pipe_b <= fpmu_double_pipe_b; // @[Valid.scala:142:26] if (fpmu_double_pipe_pipe_v) // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_b <= fpmu_double_pipe_pipe_b; // @[Valid.scala:142:26] if (fpmu_double_pipe_pipe_pipe_v) // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_pipe_b <= fpmu_double_pipe_pipe_pipe_b; // @[Valid.scala:142:26] if (reset) begin // @[fpu.scala:34:7] fpiu_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpiu_out_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpiu_out_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpmu_double_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[fpu.scala:34:7] fpiu_out_pipe_v <= fpiu_out_REG; // @[Valid.scala:141:24] fpiu_out_pipe_pipe_v <= fpiu_out_pipe_v; // @[Valid.scala:141:24] fpiu_out_pipe_pipe_pipe_v <= fpiu_out_pipe_pipe_v; // @[Valid.scala:141:24] fpmu_double_pipe_v <= _fpmu_double_T; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_v <= fpmu_double_pipe_v; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_v <= fpmu_double_pipe_pipe_v; // @[Valid.scala:141:24] fpmu_double_pipe_pipe_pipe_pipe_v <= fpmu_double_pipe_pipe_pipe_v; // @[Valid.scala:141:24] end always @(posedge) FPUFMAPipe_l4_f64 dfma ( // @[fpu.scala:67:20] .clock (clock), .reset (reset), .io_in_valid (_dfma_io_in_valid_T_2), // @[fpu.scala:68:51] .io_in_bits_ldst (dfma_io_in_bits_req_ldst), // @[fpu.scala:49:19] .io_in_bits_wen (dfma_io_in_bits_req_wen), // @[fpu.scala:49:19] .io_in_bits_ren1 (dfma_io_in_bits_req_ren1), // @[fpu.scala:49:19] .io_in_bits_ren2 (dfma_io_in_bits_req_ren2), // @[fpu.scala:49:19] .io_in_bits_ren3 (dfma_io_in_bits_req_ren3), // @[fpu.scala:49:19] .io_in_bits_swap12 (dfma_io_in_bits_req_swap12), // @[fpu.scala:49:19] .io_in_bits_swap23 (dfma_io_in_bits_req_swap23), // @[fpu.scala:49:19] .io_in_bits_typeTagIn (dfma_io_in_bits_req_typeTagIn), // @[fpu.scala:49:19] .io_in_bits_typeTagOut (dfma_io_in_bits_req_typeTagOut), // @[fpu.scala:49:19] .io_in_bits_fromint (dfma_io_in_bits_req_fromint), // @[fpu.scala:49:19] .io_in_bits_toint (dfma_io_in_bits_req_toint), // @[fpu.scala:49:19] .io_in_bits_fastpipe (dfma_io_in_bits_req_fastpipe), // @[fpu.scala:49:19] .io_in_bits_fma (dfma_io_in_bits_req_fma), // @[fpu.scala:49:19] .io_in_bits_div (dfma_io_in_bits_req_div), // @[fpu.scala:49:19] .io_in_bits_sqrt (dfma_io_in_bits_req_sqrt), // @[fpu.scala:49:19] .io_in_bits_wflags (dfma_io_in_bits_req_wflags), // @[fpu.scala:49:19] .io_in_bits_vec (dfma_io_in_bits_req_vec), // @[fpu.scala:49:19] .io_in_bits_rm (dfma_io_in_bits_req_rm), // @[fpu.scala:49:19] .io_in_bits_fmaCmd (dfma_io_in_bits_req_fmaCmd), // @[fpu.scala:49:19] .io_in_bits_typ (dfma_io_in_bits_req_typ), // @[fpu.scala:49:19] .io_in_bits_fmt (dfma_io_in_bits_req_fmt), // @[fpu.scala:49:19] .io_in_bits_in1 (dfma_io_in_bits_req_in1), // @[fpu.scala:49:19] .io_in_bits_in2 (dfma_io_in_bits_req_in2), // @[fpu.scala:49:19] .io_in_bits_in3 (dfma_io_in_bits_req_in3), // @[fpu.scala:49:19] .io_out_valid (_dfma_io_out_valid), .io_out_bits_data (_dfma_io_out_bits_data), .io_out_bits_exc (_dfma_io_out_bits_exc) ); // @[fpu.scala:67:20] assign _fpu_out_data_T_1 = _dfma_io_out_bits_data; // @[package.scala:39:76] FPUFMAPipe_l4_f32 sfma ( // @[fpu.scala:71:20] .clock (clock), .reset (reset), .io_in_valid (_sfma_io_in_valid_T_2), // @[fpu.scala:72:51] .io_in_bits_ldst (sfma_io_in_bits_req_ldst), // @[fpu.scala:49:19] .io_in_bits_wen (sfma_io_in_bits_req_wen), // @[fpu.scala:49:19] .io_in_bits_ren1 (sfma_io_in_bits_req_ren1), // @[fpu.scala:49:19] .io_in_bits_ren2 (sfma_io_in_bits_req_ren2), // @[fpu.scala:49:19] .io_in_bits_ren3 (sfma_io_in_bits_req_ren3), // @[fpu.scala:49:19] .io_in_bits_swap12 (sfma_io_in_bits_req_swap12), // @[fpu.scala:49:19] .io_in_bits_swap23 (sfma_io_in_bits_req_swap23), // @[fpu.scala:49:19] .io_in_bits_typeTagIn (sfma_io_in_bits_req_typeTagIn), // @[fpu.scala:49:19] .io_in_bits_typeTagOut (sfma_io_in_bits_req_typeTagOut), // @[fpu.scala:49:19] .io_in_bits_fromint (sfma_io_in_bits_req_fromint), // @[fpu.scala:49:19] .io_in_bits_toint (sfma_io_in_bits_req_toint), // @[fpu.scala:49:19] .io_in_bits_fastpipe (sfma_io_in_bits_req_fastpipe), // @[fpu.scala:49:19] .io_in_bits_fma (sfma_io_in_bits_req_fma), // @[fpu.scala:49:19] .io_in_bits_div (sfma_io_in_bits_req_div), // @[fpu.scala:49:19] .io_in_bits_sqrt (sfma_io_in_bits_req_sqrt), // @[fpu.scala:49:19] .io_in_bits_wflags (sfma_io_in_bits_req_wflags), // @[fpu.scala:49:19] .io_in_bits_vec (sfma_io_in_bits_req_vec), // @[fpu.scala:49:19] .io_in_bits_rm (sfma_io_in_bits_req_rm), // @[fpu.scala:49:19] .io_in_bits_fmaCmd (sfma_io_in_bits_req_fmaCmd), // @[fpu.scala:49:19] .io_in_bits_typ (sfma_io_in_bits_req_typ), // @[fpu.scala:49:19] .io_in_bits_fmt (sfma_io_in_bits_req_fmt), // @[fpu.scala:49:19] .io_in_bits_in1 (sfma_io_in_bits_req_in1), // @[fpu.scala:49:19] .io_in_bits_in2 (sfma_io_in_bits_req_in2), // @[fpu.scala:49:19] .io_in_bits_in3 (sfma_io_in_bits_req_in3), // @[fpu.scala:49:19] .io_out_valid (_sfma_io_out_valid), .io_out_bits_data (_sfma_io_out_bits_data), .io_out_bits_exc (_sfma_io_out_bits_exc) ); // @[fpu.scala:71:20] FPToInt fpiu ( // @[fpu.scala:75:20] .clock (clock), .reset (reset), .io_in_valid (_fpiu_io_in_valid_T_2), // @[fpu.scala:76:36] .io_in_bits_ldst (fpiu_io_in_bits_req_ldst), // @[fpu.scala:49:19] .io_in_bits_wen (fpiu_io_in_bits_req_wen), // @[fpu.scala:49:19] .io_in_bits_ren1 (fpiu_io_in_bits_req_ren1), // @[fpu.scala:49:19] .io_in_bits_ren2 (fpiu_io_in_bits_req_ren2), // @[fpu.scala:49:19] .io_in_bits_ren3 (fpiu_io_in_bits_req_ren3), // @[fpu.scala:49:19] .io_in_bits_swap12 (fpiu_io_in_bits_req_swap12), // @[fpu.scala:49:19] .io_in_bits_swap23 (fpiu_io_in_bits_req_swap23), // @[fpu.scala:49:19] .io_in_bits_typeTagIn (fpiu_io_in_bits_req_typeTagIn), // @[fpu.scala:49:19] .io_in_bits_typeTagOut (fpiu_io_in_bits_req_typeTagOut), // @[fpu.scala:49:19] .io_in_bits_fromint (fpiu_io_in_bits_req_fromint), // @[fpu.scala:49:19] .io_in_bits_toint (fpiu_io_in_bits_req_toint), // @[fpu.scala:49:19] .io_in_bits_fastpipe (fpiu_io_in_bits_req_fastpipe), // @[fpu.scala:49:19] .io_in_bits_fma (fpiu_io_in_bits_req_fma), // @[fpu.scala:49:19] .io_in_bits_div (fpiu_io_in_bits_req_div), // @[fpu.scala:49:19] .io_in_bits_sqrt (fpiu_io_in_bits_req_sqrt), // @[fpu.scala:49:19] .io_in_bits_wflags (fpiu_io_in_bits_req_wflags), // @[fpu.scala:49:19] .io_in_bits_vec (fpiu_io_in_bits_req_vec), // @[fpu.scala:49:19] .io_in_bits_rm (fpiu_io_in_bits_req_rm), // @[fpu.scala:49:19] .io_in_bits_fmaCmd (fpiu_io_in_bits_req_fmaCmd), // @[fpu.scala:49:19] .io_in_bits_typ (fpiu_io_in_bits_req_typ), // @[fpu.scala:49:19] .io_in_bits_fmt (fpiu_io_in_bits_req_fmt), // @[fpu.scala:49:19] .io_in_bits_in1 (fpiu_io_in_bits_req_in1), // @[fpu.scala:49:19] .io_in_bits_in2 (fpiu_io_in_bits_req_in2), // @[fpu.scala:49:19] .io_in_bits_in3 (fpiu_io_in_bits_req_in3), // @[fpu.scala:49:19] .io_out_bits_in_ldst (_fpiu_io_out_bits_in_ldst), .io_out_bits_in_wen (_fpiu_io_out_bits_in_wen), .io_out_bits_in_ren1 (_fpiu_io_out_bits_in_ren1), .io_out_bits_in_ren2 (_fpiu_io_out_bits_in_ren2), .io_out_bits_in_ren3 (_fpiu_io_out_bits_in_ren3), .io_out_bits_in_swap12 (_fpiu_io_out_bits_in_swap12), .io_out_bits_in_swap23 (_fpiu_io_out_bits_in_swap23), .io_out_bits_in_typeTagIn (_fpiu_io_out_bits_in_typeTagIn), .io_out_bits_in_typeTagOut (_fpiu_io_out_bits_in_typeTagOut), .io_out_bits_in_fromint (_fpiu_io_out_bits_in_fromint), .io_out_bits_in_toint (_fpiu_io_out_bits_in_toint), .io_out_bits_in_fastpipe (_fpiu_io_out_bits_in_fastpipe), .io_out_bits_in_fma (_fpiu_io_out_bits_in_fma), .io_out_bits_in_div (_fpiu_io_out_bits_in_div), .io_out_bits_in_sqrt (_fpiu_io_out_bits_in_sqrt), .io_out_bits_in_wflags (_fpiu_io_out_bits_in_wflags), .io_out_bits_in_vec (_fpiu_io_out_bits_in_vec), .io_out_bits_in_rm (_fpiu_io_out_bits_in_rm), .io_out_bits_in_fmaCmd (_fpiu_io_out_bits_in_fmaCmd), .io_out_bits_in_typ (_fpiu_io_out_bits_in_typ), .io_out_bits_in_fmt (_fpiu_io_out_bits_in_fmt), .io_out_bits_in_in1 (_fpiu_io_out_bits_in_in1), .io_out_bits_in_in2 (_fpiu_io_out_bits_in_in2), .io_out_bits_in_in3 (_fpiu_io_out_bits_in_in3), .io_out_bits_lt (_fpiu_io_out_bits_lt), .io_out_bits_store (_fpiu_io_out_bits_store), .io_out_bits_toint (_fpiu_io_out_bits_toint), .io_out_bits_exc (_fpiu_io_out_bits_exc) ); // @[fpu.scala:75:20] FPToFP fpmu ( // @[fpu.scala:84:20] .clock (clock), .reset (reset), .io_in_valid (_fpmu_io_in_valid_T), // @[fpu.scala:85:36] .io_in_bits_ldst (fpiu_io_in_bits_req_ldst), // @[fpu.scala:49:19] .io_in_bits_wen (fpiu_io_in_bits_req_wen), // @[fpu.scala:49:19] .io_in_bits_ren1 (fpiu_io_in_bits_req_ren1), // @[fpu.scala:49:19] .io_in_bits_ren2 (fpiu_io_in_bits_req_ren2), // @[fpu.scala:49:19] .io_in_bits_ren3 (fpiu_io_in_bits_req_ren3), // @[fpu.scala:49:19] .io_in_bits_swap12 (fpiu_io_in_bits_req_swap12), // @[fpu.scala:49:19] .io_in_bits_swap23 (fpiu_io_in_bits_req_swap23), // @[fpu.scala:49:19] .io_in_bits_typeTagIn (fpiu_io_in_bits_req_typeTagIn), // @[fpu.scala:49:19] .io_in_bits_typeTagOut (fpiu_io_in_bits_req_typeTagOut), // @[fpu.scala:49:19] .io_in_bits_fromint (fpiu_io_in_bits_req_fromint), // @[fpu.scala:49:19] .io_in_bits_toint (fpiu_io_in_bits_req_toint), // @[fpu.scala:49:19] .io_in_bits_fastpipe (fpiu_io_in_bits_req_fastpipe), // @[fpu.scala:49:19] .io_in_bits_fma (fpiu_io_in_bits_req_fma), // @[fpu.scala:49:19] .io_in_bits_div (fpiu_io_in_bits_req_div), // @[fpu.scala:49:19] .io_in_bits_sqrt (fpiu_io_in_bits_req_sqrt), // @[fpu.scala:49:19] .io_in_bits_wflags (fpiu_io_in_bits_req_wflags), // @[fpu.scala:49:19] .io_in_bits_vec (fpiu_io_in_bits_req_vec), // @[fpu.scala:49:19] .io_in_bits_rm (fpiu_io_in_bits_req_rm), // @[fpu.scala:49:19] .io_in_bits_fmaCmd (fpiu_io_in_bits_req_fmaCmd), // @[fpu.scala:49:19] .io_in_bits_typ (fpiu_io_in_bits_req_typ), // @[fpu.scala:49:19] .io_in_bits_fmt (fpiu_io_in_bits_req_fmt), // @[fpu.scala:49:19] .io_in_bits_in1 (fpiu_io_in_bits_req_in1), // @[fpu.scala:49:19] .io_in_bits_in2 (fpiu_io_in_bits_req_in2), // @[fpu.scala:49:19] .io_in_bits_in3 (fpiu_io_in_bits_req_in3), // @[fpu.scala:49:19] .io_out_valid (_fpmu_io_out_valid), .io_out_bits_data (_fpmu_io_out_bits_data), .io_out_bits_exc (_fpmu_io_out_bits_exc), .io_lt (_fpiu_io_out_bits_lt) // @[fpu.scala:75:20] ); // @[fpu.scala:84:20] assign io_resp_bits_data = io_resp_bits_data_0; // @[fpu.scala:34:7] assign io_resp_bits_fflags_bits = io_resp_bits_fflags_bits_0; // @[fpu.scala:34:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLError : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_20 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect nodeIn, auto.in inst a_q of Queue1_TLBundleA_a14d64s7k1z4u connect a_q.clock, clock connect a_q.reset, reset connect a_q.io.enq.valid, nodeIn.a.valid connect a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect a_q.io.enq.bits.data, nodeIn.a.bits.data connect a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect a_q.io.enq.bits.address, nodeIn.a.bits.address connect a_q.io.enq.bits.source, nodeIn.a.bits.source connect a_q.io.enq.bits.size, nodeIn.a.bits.size connect a_q.io.enq.bits.param, nodeIn.a.bits.param connect a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, a_q.io.enq.ready wire da : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} regreset idle : UInt<1>, clock, reset, UInt<1>(0h1) node _a_last_T = and(a_q.io.deq.ready, a_q.io.deq.valid) node _a_last_beats1_decode_T = dshl(UInt<12>(0hfff), a_q.io.deq.bits.size) node _a_last_beats1_decode_T_1 = bits(_a_last_beats1_decode_T, 11, 0) node _a_last_beats1_decode_T_2 = not(_a_last_beats1_decode_T_1) node a_last_beats1_decode = shr(_a_last_beats1_decode_T_2, 3) node _a_last_beats1_opdata_T = bits(a_q.io.deq.bits.opcode, 2, 2) node a_last_beats1_opdata = eq(_a_last_beats1_opdata_T, UInt<1>(0h0)) node a_last_beats1 = mux(a_last_beats1_opdata, a_last_beats1_decode, UInt<1>(0h0)) regreset a_last_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_last_counter1_T = sub(a_last_counter, UInt<1>(0h1)) node a_last_counter1 = tail(_a_last_counter1_T, 1) node a_last_first = eq(a_last_counter, UInt<1>(0h0)) node _a_last_last_T = eq(a_last_counter, UInt<1>(0h1)) node _a_last_last_T_1 = eq(a_last_beats1, UInt<1>(0h0)) node a_last = or(_a_last_last_T, _a_last_last_T_1) node a_last_done = and(a_last, _a_last_T) node _a_last_count_T = not(a_last_counter1) node a_last_count = and(a_last_beats1, _a_last_count_T) when _a_last_T : node _a_last_counter_T = mux(a_last_first, a_last_beats1, a_last_counter1) connect a_last_counter, _a_last_counter_T node _T = and(da.ready, da.valid) node _r_beats1_decode_T = dshl(UInt<12>(0hfff), da.bits.size) node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0) node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1) node r_beats1_decode = shr(_r_beats1_decode_T_2, 3) node r_beats1_opdata = bits(da.bits.opcode, 0, 0) node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0)) regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _r_counter1_T = sub(r_counter, UInt<1>(0h1)) node r_counter1 = tail(_r_counter1_T, 1) node da_first = eq(r_counter, UInt<1>(0h0)) node _r_last_T = eq(r_counter, UInt<1>(0h1)) node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0)) node da_last = or(_r_last_T, _r_last_T_1) node r_3 = and(da_last, _T) node _r_count_T = not(r_counter1) node r_4 = and(r_beats1, _r_count_T) when _T : node _r_counter_T = mux(da_first, r_beats1, r_counter1) connect r_counter, _r_counter_T node _T_1 = or(idle, da_first) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Error.scala:34 assert (idle \|\| da_first) // we only send Grant, never GrantData => simplified flow control below\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _q_io_deq_ready_T = and(da.ready, da_last) node _q_io_deq_ready_T_1 = and(_q_io_deq_ready_T, idle) node _q_io_deq_ready_T_2 = eq(a_last, UInt<1>(0h0)) node _q_io_deq_ready_T_3 = or(_q_io_deq_ready_T_1, _q_io_deq_ready_T_2) connect a_q.io.deq.ready, _q_io_deq_ready_T_3 node _da_valid_T = and(a_q.io.deq.valid, a_last) node _da_valid_T_1 = and(_da_valid_T, idle) connect da.valid, _da_valid_T_1 wire _da_bits_opcode_WIRE : UInt<3>[8] connect _da_bits_opcode_WIRE[0], UInt<1>(0h0) connect _da_bits_opcode_WIRE[1], UInt<1>(0h0) connect _da_bits_opcode_WIRE[2], UInt<1>(0h1) connect _da_bits_opcode_WIRE[3], UInt<1>(0h1) connect _da_bits_opcode_WIRE[4], UInt<1>(0h1) connect _da_bits_opcode_WIRE[5], UInt<2>(0h2) connect _da_bits_opcode_WIRE[6], UInt<3>(0h4) connect _da_bits_opcode_WIRE[7], UInt<3>(0h4) connect da.bits.opcode, _da_bits_opcode_WIRE[a_q.io.deq.bits.opcode] connect da.bits.param, UInt<1>(0h0) connect da.bits.size, a_q.io.deq.bits.size connect da.bits.source, a_q.io.deq.bits.source connect da.bits.sink, UInt<1>(0h0) connect da.bits.denied, UInt<1>(0h1) connect da.bits.data, UInt<1>(0h0) node da_bits_corrupt_opdata = bits(da.bits.opcode, 0, 0) connect da.bits.corrupt, da_bits_corrupt_opdata connect nodeIn.d, da wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<14>(0h0) connect _WIRE.bits.source, UInt<7>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_2.bits.sink, UInt<1>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) extmodule plusarg_reader_42 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_43 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32	module TLError( // @[Error.scala:21:9] input clock, // @[Error.scala:21:9] input reset, // @[Error.scala:21:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _a_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _a_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [3:0] _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire auto_in_a_valid_0 = auto_in_a_valid; // @[Error.scala:21:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Error.scala:21:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Error.scala:21:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Error.scala:21:9] wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Error.scala:21:9] wire [13:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Error.scala:21:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Error.scala:21:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Error.scala:21:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Error.scala:21:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Error.scala:21:9] wire [7:0][2:0] _GEN = '{3'h4, 3'h4, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0}; wire auto_in_d_bits_denied = 1'h1; // @[Error.scala:21:9] wire nodeIn_d_bits_denied = 1'h1; // @[MixedNode.scala:551:17] wire da_bits_denied = 1'h1; // @[Error.scala:28:18] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Error.scala:21:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] da_bits_param = 2'h0; // @[Error.scala:28:18] wire auto_in_d_bits_sink = 1'h0; // @[Error.scala:21:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire da_bits_sink = 1'h0; // @[Error.scala:28:18] wire [63:0] auto_in_d_bits_data = 64'h0; // @[Error.scala:21:9] wire [63:0] nodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17] wire [63:0] da_bits_data = 64'h0; // @[Error.scala:28:18] wire [2:0] _da_bits_opcode_WIRE_6 = 3'h4; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_7 = 3'h4; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_5 = 3'h2; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_2 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_3 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_4 = 3'h1; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_0 = 3'h0; // @[Bundles.scala:47:27] wire [2:0] _da_bits_opcode_WIRE_1 = 3'h0; // @[Bundles.scala:47:27] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Error.scala:21:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Error.scala:21:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Error.scala:21:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Error.scala:21:9] wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Error.scala:21:9] wire [13:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Error.scala:21:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Error.scala:21:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Error.scala:21:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Error.scala:21:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Error.scala:21:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[Error.scala:21:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Error.scala:21:9] wire [3:0] auto_in_d_bits_size_0; // @[Error.scala:21:9] wire [6:0] auto_in_d_bits_source_0; // @[Error.scala:21:9] wire auto_in_d_bits_corrupt_0; // @[Error.scala:21:9] wire auto_in_d_valid_0; // @[Error.scala:21:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Error.scala:21:9] wire da_ready = nodeIn_d_ready; // @[Error.scala:28:18] wire da_valid; // @[Error.scala:28:18] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Error.scala:21:9] wire [2:0] da_bits_opcode; // @[Error.scala:28:18] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Error.scala:21:9] wire [3:0] da_bits_size; // @[Error.scala:28:18] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Error.scala:21:9] wire [6:0] da_bits_source; // @[Error.scala:28:18] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Error.scala:21:9] wire da_bits_corrupt; // @[Error.scala:28:18] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Error.scala:21:9] wire _da_valid_T_1; // @[Error.scala:36:35] assign nodeIn_d_valid = da_valid; // @[Error.scala:28:18] assign nodeIn_d_bits_opcode = da_bits_opcode; // @[Error.scala:28:18] assign nodeIn_d_bits_size = da_bits_size; // @[Error.scala:28:18] assign nodeIn_d_bits_source = da_bits_source; // @[Error.scala:28:18] wire da_bits_corrupt_opdata; // @[Edges.scala:106:36] assign nodeIn_d_bits_corrupt = da_bits_corrupt; // @[Error.scala:28:18] wire _q_io_deq_ready_T_3; // @[Error.scala:35:46] wire _a_last_T = _q_io_deq_ready_T_3 & _a_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21] wire [26:0] _a_last_beats1_decode_T = 27'hFFF << _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [11:0] _a_last_beats1_decode_T_1 = _a_last_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_last_beats1_decode_T_2 = ~_a_last_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_last_beats1_decode = _a_last_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_last_beats1_opdata_T = _a_q_io_deq_bits_opcode[2]; // @[Decoupled.scala:362:21] wire a_last_beats1_opdata = ~_a_last_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_last_beats1 = a_last_beats1_opdata ? a_last_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_last_counter; // @[Edges.scala:229:27] wire [9:0] _a_last_counter1_T = {1'h0, a_last_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_last_counter1 = _a_last_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_last_first = a_last_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_last_last_T = a_last_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_last_last_T_1 = a_last_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_last = _a_last_last_T \| _a_last_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_last_done = a_last & _a_last_T; // @[Decoupled.scala:51:35] wire [8:0] _a_last_count_T = ~a_last_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_last_count = a_last_beats1 & _a_last_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_last_counter_T = a_last_first ? a_last_beats1 : a_last_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _T = da_ready & da_valid; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << da_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36] assign da_bits_corrupt_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire da_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire da_last = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire r_3 = da_last & _T; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = da_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _q_io_deq_ready_T = da_ready & da_last; // @[Edges.scala:232:33] wire _q_io_deq_ready_T_1 = _q_io_deq_ready_T; // @[Error.scala:35:{26,37}] wire _q_io_deq_ready_T_2 = ~a_last; // @[Edges.scala:232:33] assign _q_io_deq_ready_T_3 = _q_io_deq_ready_T_1 \| _q_io_deq_ready_T_2; // @[Error.scala:35:{37,46,49}] wire _da_valid_T = _a_q_io_deq_valid & a_last; // @[Decoupled.scala:362:21] assign _da_valid_T_1 = _da_valid_T; // @[Error.scala:36:{25,35}] assign da_valid = _da_valid_T_1; // @[Error.scala:28:18, :36:35] assign da_bits_opcode = _GEN[_a_q_io_deq_bits_opcode]; // @[Decoupled.scala:362:21] assign da_bits_corrupt = da_bits_corrupt_opdata; // @[Edges.scala:106:36] always @(posedge clock) begin // @[Error.scala:21:9] if (reset) begin // @[Error.scala:21:9] a_last_counter <= 9'h0; // @[Edges.scala:229:27] r_counter <= 9'h0; // @[Edges.scala:229:27] end else begin // @[Error.scala:21:9] if (_a_last_T) // @[Decoupled.scala:51:35] a_last_counter <= _a_last_counter_T; // @[Edges.scala:229:27, :236:21] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] end always @(posedge) TLMonitor_20 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a14d64s7k1z4u a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (_q_io_deq_ready_T_3), // @[Error.scala:35:46] .io_deq_valid (_a_q_io_deq_valid), .io_deq_bits_opcode (_a_q_io_deq_bits_opcode), .io_deq_bits_size (_a_q_io_deq_bits_size), .io_deq_bits_source (da_bits_source) ); // @[Decoupled.scala:362:21] assign da_bits_size = _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Error.scala:21:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Error.scala:21:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Error.scala:21:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Error.scala:21:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Error.scala:21:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Error.scala:21:9] endmodule

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